APPLICATION NOTE 25

TC4426/27/28 SYSTEM
DESIGN PRACTICE
By David Gillooly

The TC4426/4427/4428 are CMOS buffer/drivers built The TC4426 family outputs are CMOS. Low quiescent
using TelCom Semiconductor' new Tough CMOS process. power and high output voltage drive (very important with 5
They are improved versions of the earlier TC426/427/428 V supply operation) result. Since the outputs are CMOS
family of buffer/drivers (with which they are pin compatible) the potential for activating a parasitic SCR exists. This
and are capable of giving reliable service in far more must be avoided to prevent potential device destruction. If
demanding electrical environments. They will not latch up the TC4426 output, like any CMOS chip, is driven below
under any conditions within their power and voltage ratings. ground or above the positive power supply an internal
They are not subject to damage when up to 5V of noise parasitic SCR can be turned on. The high current flow can
spiking (of either polarity) occurs on the ground pin. They
VCC (PIN 6)
can accept, without damage or logic upset, up to 500 mA of
reverse current (of either polarity) being forced back into P-CHANNEL
their outputs. All terminals are fully protected against up to
4 kV of electrostatic discharge.
As a result, the TC4426/4427/4428 drivers are much
easier to use, more flexible in operation, and much more
OUTPUT
forgiving than any other drivers (CMOS or bipolar) currently
available. Because they are fabricated in CMOS, they INTERNAL

dissipate a minimum of power and provide rail-to-rail volt-

age swings to ensure the logic state of any load they are
N-CHANNEL
driving.
The TC4426/27/28 fast switching times are made pos- GROUND (PIN 3)
sible by a low impedance CMOS output stage. The high
peak currents make 30 ns rise/fall times possible. Figure 1: TC4426 Output
The rapid rise/fall times do, however, require systems
be designed with adequate power supply decoupling and VCC
INTERNAL TC4426
GATE DRIVE
TC4426
OUTPUT
stray lead inductance minimization. Practices which are
adequate for 1µs rise/fall times and 20 mA peak currents will
not be adequate with the TC4426 family. The same laws of
GROUND
physics apply in both systems. The results may be negli-
gible in one and of prime importance in another. S G D D G S

For example, a 0.1µH power lead inductance (4" of

0.025" diameter wire) can cause a voltage spike 1000 times Q2
larger in a fast system with an unbypassed supply. Q1
R2

P-WELL

Low Speed System High Speed System R1

LS = 0.1µH LS = 0.1µH
DVOUT = 18 V DVOUT = 18 V
t = 1µs t = 30ns
P-CHANNEL N-CHANNEL
IPK = 20mA IPK = 600mA
CL = 1000 pF CL = 1000 pF Figure 2: Output Stage IC Layout
di
DV SUPPLY = L di DV SUPPLY = L
dt dt VCC (PIN 6)
= 2 mV = 2.0 V
R1
The system design practices needed are not difficult Q1
to apply. The simple good engineering practice of bypassing DP
the power supply, minimizing stray lead inductance, and
grounding unused driver inputs will solve most system DN
Q2
problems. Nothing new required — just a little careful R2
application of techniques common to any high speed CMOS
system. GROUND (PIN 3)

Figure 3: Equivalent SCR Circuit

AN25-1
 TC4426/27/28 SYSTEM
DESIGN PRACTICE

AN-25
damage the device. The actual TC4426 output stage is
shown in Figure 1. The IC layout and simplified equivalent STRAY INDUCTANCE
IN POWER SUPPLY
SCR circuit are shown in Figures 2 and 3.
VS = 18 V
The IC parasitic SCR can be turned on if DP is raised LS = 50nH
above VCC or if D N is forced below ground. An inductive V+

load at the output can also create a voltage swing at the 6

output that exceeds the positive supply or undershoots ASSUME:

∆I0 = 0.6 A
ground. ∆t = 20 ns
VIN
If the output is raised above the positive supply, cur- 3

rent is injected into the emitter of Q1 and swept into the

collector. The Q1 collector feeds the base of Q2 and R2.
When the base of Q2 reaches 0.6 V Q2 turns on. This ∆V = L di = 50 (10-9) 0.6 = 1.5 V
dt 20 X 10-9
forces Q1 on. The SCR is now "fired" shorting the positive
STRAY INDUCTANCE IN POWER SUPPLY CAN CAUSE
power supply to ground. A similar situation exists when the VOLTAGE AT V+ TO EXCEED ABSOLUTE MAXIMUM
output is driven below ground. RATING. SOLUTION IS TO BYPASS SUPPLY AS CLOSE
The internal SCR can also be triggered by excessive TO PINS 6 & 3 AS POSSIBLE
voltage on the power supply that results in internal voltage Figure 5: Stray Supply Lead Inductance Can Decrease Reliability
breakdown. The current injected can trigger the SCR ac-
tion.
VS
By limiting the current injected into the TC4426 output
when the output is above the positive power supply latch
0.1µf
up is avoided. The limiting current is: 1µf
MONOLITHIC
CAPACITOR
V BE
I≤
R2 II RONP
where: 6

RONP = ON resistance of P channel device. (15 ohms TIE UNUSED

INPUTS TO TC4426/
maximum) GROUND 27/28
VBE = Q2 base emitter turn on voltage. 3
(Approximately 0.6 V)
R2 = Bulk resistance
Assuming the ON resistance dominates, the current
should be limited to 40 mA. A similar analysis with the
output below ground indicates the current pulled out of the NOTES: 1. LOW INDUCTANCE 0.1f CERAMIC DISK OR
TC4426 output should be limited to 60 mA. The maximum MONOLITHIC CAPACITORS
allowable latch current is temperature sensitive. At high 2. BYPASS AS CLOSE TO PIN 6 & 3 AS PHYSICALLY
POSSIBLE
chip temperature the base emitter voltages are reduced. A 3. REMEMBER UNUSED INPUTS SHOULD BE
1°C rise lowers VBE by 2.2 mV. GROUNDED
4. BYPASSING IS IMPORTANT
VCC MAKE CONNECTIONS
CLOSE TO DEVICE PINS Figure 6: Suggested Bypass Procedure

0.1µf
1µf CERAMIC
DISK
SCHOTTKY C
DIODES

CONNECT
TO PIN 3 MAKE CONNECTIONS
CLOSE TO DEVICE PINS
VIN
VIN DS0026
INPUT OUTPUT
TC4426/ R
27/28 3

THE UNUSED MINIMIZE LEAD

INPUT TO
GROUND LENGTH TO
POWER MOSFET

Figure 7: TC4426 Has CMOS Inputs. Speed Up

Figure 4: Equivalent SCR Circuit Capacitors Are Not Required

2
TC4426/27/28 SYSTEM
DESIGN PRACTICE

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Current limiting with a series output resistor may not The DS0026 has a bipolar input. A speed up capaci-
be practical in all systems. The output rise and fall times tor is normally used to decrease switching time. Base
may increase. An alternate solution uses low forward volt- storage time is reduced. The capacitor causes a voltage
age output clamp diodes to bypass the SCR trigger cur- spike drive at the input that extends beyond V CC or ground.
rent around the device. The TC4426 input is CMOS and does not require a speed
External output clamp diodes prevent the TC4426 up capacitor. In converting DS0026 sockets to the TC4426/
output from being pulled far enough outside the power 27/28 the capacitor should be remove. This will maximize
supply range to turn on the parasitic SCR. (See App. Note drive to the device and minimize transition time. Benefits
31) include fewer components and reduced insertion costs.
The external diodes must have a lower forward on See Figure 8.
base to emitter voltage than the parasitic transistor junc- The TC4426/27/28 outputs feature a low impedance
tions. Schottky small signal diodes are suitable. Several P channel pull-up MOS device and low impedance
possible types are: N channel pull-down MOS device. The low resistance
outputs are responsible for the 30 ns rise and fall times.
• Hewlett Packard: P/N 5082-2303 The CMOS construction minimizes current drain.
• Motorola: P/N MBR120P The output N and P channel devices should not be
• Varo: P/N VSB52 (Four diode bridge) forced to conduct current simultaneously. This can hap-
To be effective the output clamp diodes must be pen if an unused input is left floating. Unused inputs must
connected close to the output, supply and ground device be connected to ground or the positive supply. A ground
pins. connection will minimize steady state supply current. This
Supply bypass capacitors must also be connected is common engineering practice followed in CMOS logic
between VCC (Pin 6) and Ground (Pin 3). Connections system design but is sometimes overlooked during a "quick"
must be close to the actual device pins (approx. 0.5"). A bench evaluation. Floating inputs cause excessive current
0.1 µf ceramic disk capacitor in parallel with a 1µf low ESR flow and may potentially destroy the driver.
film capacitor is suggested. Without supply bypassing, The input drive signal should also have rise and fall
power supply lead inductance can cause voltage break- times less than 1µs. This minimizes time spent in the
down. The bypass capacitors also supply the transient output stage transition region.
current needed during capacitive load charging.
A 10 to 15 ohm resistor in series with the power Package Power Dissipation
supply filters voltage spikes present at the TC4426/27/28 Input signal duty cycle, power supply voltage, and ca-
supply terminal. Should latch up occur, this will also limit pacitive load influence package power dissipation. Given
current. Rise and fall time will not be affected if the recom- power dissipation and package thermal resistance the maxi-
mended supply bypassing is used. See Figure 8. mum ambient operation temperature is easily calculated. The
CerDIP 8-pin package junction to ambient thermal resistance
is 150°C/W. At 25°C the package is rated at 800 nW maxi-
VS
mum dissipation. Maximum allowable chip temperature is
150°C.
RL 10-15 OHMS Three components make up total package power dissi-
pation:
• Capacitive load dissipation (P C)
0.1 µf AVX RAM GUARD
1µf
CERAMIC MLC
• Quiescent power (P Q)
WIMA • Transition power (P T)
MKS-2
The capacitive load caused dissipation is a direct function
6 of frequency, capacitive load, and supply voltage. The
package power dissipation per driver is:
INPUT TC4426/ OUTPUT
27/28 EQ. 1: PC = f C VS2
TIE UNUSED
INPUTS TO 3 where: F = Switching frequency
GROUND C = Capacitive load
VS = Supply voltage
Figure 8: RL Current Limiting Protects Device and Will
Not Degrade Switching Speed

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 TC4426/27/28 SYSTEM
DESIGN PRACTICE

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Quiescent power dissipation depends on input signal duty Table 1 gives the total package power dissipation for
cycle. A logic low input results in a low power dissipation several different cases using the formulas developed above.
mode with only 0.4 mA total current drain. Logic high signals If only one driver is active divide the package power
raise the current to 8 mA maximum. The quiescent power dissipation numbers by two in Table 1.
dissipation per driver is:

EQ. 2 : PQ = V S (D (IH) = (1-D) IL)

2
where: IH = Quiescent current with both inputs high (8 mA Max) Table 1: TC4426 Package Power Dissipation
IL = Quiescent current with both inputs low (0.4 mA
Package Power Dissipation
Max) CerDIP Package (uJA = 150 °C/W)
D = Duty cycle Max
Input Ambient
Transition power dissipation is normally not significant. It Capacitive Input Supply Stage AC Spike Total Operating
Load Frequency Voltage Power Power Power Power Temp
arises because the output stage N and P channel MOS (pf) (kHz) (V) (mW) (mW) (mW) (mW) (°C)
transistors are on simultaneously for a very short period
1000 50 18 75 32 2 109 125
when the output changes. The transition package power 1000 100 18 75 64 5 144 125
dissipation power driver is approximately: 1000 200 18 75 129 11 215 117
1000 400 18 75 259 23 357 96
EQ. 3: PT = f VS (1.63 x 10-9) 1000
1000
1000
50
18
12
75
50
648
14
58
1
781
65
32
125
1000 100 12 50 28 3 81 125
An example shows the relative magnitude for each term. 1000 200 12 50 57 7 114 125
Both drivers are driven with a 50% duty cycle signal at the 1000 400 12 50 115 15 180 122
1000 1000 12 50 288 39 377 93
same frequency. Capacitive load is the same for each 2000 50 18 75 64 2 141 125
driver. 1000 1800 12 50 518 70 638 54
50 4000 18 75 129 234 438 84
Example 1: 1000 100 18 75 64 5 144 125
500 100 18 75 32 5 112 125
500 200 15 63 45 9 117 125
C = 1000 pf 500 100 15 63 22 4 89 125
VS = 18 V
D = 50% Notes: 1. Duty Cycle = 50%
2. Each input driven.
f = 200kHz
3. Each output with load C.
PD = Package power dissipation = PC + PT + PQ 4. Ambient operating temperature should not exceed 85°C for
= 130 mW + 11.7 mW + 38 mW "IJA" device or 125°C for "MJA" device.
= 180 mW
Max. operating temperature = TJ - uJA (PD)
= 123°C
where:
TV = Max. allowable junction temperature (150°C)
uJA = Junction to ambient thermal resistance (150°C/W,
CerDIP)

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Printed in the U.S.A 7/9/96