COMPUTER ORGANIZATION AND DESIGN 6th
Edition
The Hardware/Software Interface
Chapter 4
The Processor
§4.8 Data Hazards: Forwarding vs. Stalling
Data Hazards in ALU Instructions
◼ Consider this sequence:
sub $2, $1,$3
and $12,$2,$5
or $13,$6,$2
add $14,$2,$2
sw $15,100($2)
◼ We can resolve hazards with forwarding
◼ How do we detect when to forward?
Chapter 4 — The Processor — 2
Dependencies & Forwarding
Chapter 4 — The Processor — 3
Detecting the Need to Forward
◼ Pass register numbers along pipeline
◼ e.g., ID/EX.RegisterRs = register number for Rs
sitting in ID/EX pipeline register
◼ ALU operand register numbers in EX stage
are given by
◼ ID/EX.RegisterRs, ID/EX.RegisterRt
◼ Data hazards when
Fwd from
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs EX/MEM
pipeline reg
1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs Fwd from
MEM/WB
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt pipeline reg
Chapter 4 — The Processor — 4
Detecting the Need to Forward
◼ But only if forwarding instruction will write
to a register!
◼ EX/MEM.RegWrite, MEM/WB.RegWrite
◼ And only if Rd for that instruction is not
$zero
◼ EX/MEM.RegisterRd ≠ 0,
MEM/WB.RegisterRd ≠ 0
Chapter 4 — The Processor — 5
Forwarding Paths
Chapter 4 — The Processor — 6
Forwarding Conditions
Mux control Source Explanation
ForwardA = 00 ID/EX The first ALU operand comes from the register file.
ForwardA = 10 EX/MEM The first ALU operand is forwarded from the prior
ALU result.
ForwardA = 01 MEM/WB The first ALU operand is forwarded from data
memory or an earlier ALU result.
ForwardB = 00 ID/EX The second ALU operand comes from the register
file.
ForwardB = 10 EX/MEM The second ALU operand is forwarded from the prior
ALU result.
ForwardB = 01 MEM/WB The second ALU operand is forwarded from data
memory or an earlier ALU result.
Chapter 4 — The Processor — 7
Datapath with Forwarding
Chapter 4 — The Processor — 8
Load-Use Data Hazard
Need to stall
for one cycle
Chapter 4 — The Processor — 9
Load-Use Hazard Detection
◼ Check when using instruction is decoded
in ID stage
◼ ALU operand register numbers in ID stage
are given by
◼ IF/ID.RegisterRs, IF/ID.RegisterRt
◼ Load-use hazard when
◼ ID/EX.MemRead and
((ID/EX.RegisterRt = IF/ID.RegisterRs) or
(ID/EX.RegisterRt = IF/ID.RegisterRt))
◼ If detected, stall and insert bubble
Chapter 4 — The Processor — 10
How to Stall the Pipeline
◼ Force control values in ID/EX register
to 0
◼ EX, MEM and WB do nop (no-operation)
◼ Prevent update of PC and IF/ID register
◼ Using instruction is decoded again
◼ Following instruction is fetched again
◼ 1-cycle stall allows MEM to read data for lw
◼ Can subsequently forward to EX stage
Chapter 4 — The Processor — 11
Load-Use Data Hazard
Stall inserted
here
Chapter 4 — The Processor — 12
Datapath with Hazard Detection
Chapter 4 — The Processor — 13
Stalls and Performance
The BIG Picture
◼ Stalls reduce performance
◼ But are required to get correct results
◼ Compiler can arrange code to avoid
hazards and stalls
◼ Requires knowledge of the pipeline structure
Chapter 4 — The Processor — 14
§4.9 Control Hazards
Branch Hazards
◼ If branch outcome determined in MEM
Flush these
instructions
(Set control
values to 0)
PC
Chapter 4 — The Processor — 15
Reducing Branch Delay
◼ Move hardware to determine outcome to ID
stage
◼ Target address adder
◼ Register comparator
◼ Example: branch taken
36: sub $10, $4, $8
40: beq $1, $3, 7
44: and $12, $2, $5
48: or $13, $2, $6
52: add $14, $4, $2
56: slt $15, $6, $7
...
72: lw $4, 50($7)
Chapter 4 — The Processor — 16
Example: Branch Taken
Chapter 4 — The Processor — 17
Example: Branch Taken
Chapter 4 — The Processor — 18
Data Hazards for Branches
◼ If a comparison register is a destination of
2nd or 3rd preceding ALU instruction
add $1, $2, $3 IF ID EX MEM WB
add $4, $5, $6 IF ID EX MEM WB
… IF ID EX MEM WB
beq $1, $4, target IF ID EX MEM WB
◼ Can resolve using forwarding
Chapter 4 — The Processor — 19
Data Hazards for Branches
◼ If a comparison register is a destination of
preceding ALU instruction or 2nd preceding
load instruction
◼ Need 1 stall cycle
lw $1, addr IF ID EX MEM WB
add $4, $5, $6 IF ID EX MEM WB
beq stalled IF ID
beq $1, $4, target ID EX MEM WB
Chapter 4 — The Processor — 20
Data Hazards for Branches
◼ If a comparison register is a destination of
immediately preceding load instruction
◼ Need 2 stall cycles
lw $1, addr IF ID EX MEM WB
beq stalled IF ID
beq stalled ID
beq $1, $0, target ID EX MEM WB
Chapter 4 — The Processor — 21
