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Stop Watch DSD

This document describes a Verilog implementation of a stopwatch interface that uses a 3-digit BCD counter to count 0.1 second ticks and display the time on a 7-segment display. It contains two modules - a stopwatch interface module that generates the 0.1 second ticks and increments the BCD counter, and a display multiplexer module that multiplexes the display digits and drives the 7-segment LED display.

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Awais Shams
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67 views7 pages

Stop Watch DSD

This document describes a Verilog implementation of a stopwatch interface that uses a 3-digit BCD counter to count 0.1 second ticks and display the time on a 7-segment display. It contains two modules - a stopwatch interface module that generates the 0.1 second ticks and increments the BCD counter, and a display multiplexer module that multiplexes the display digits and drives the 7-segment LED display.

Uploaded by

Awais Shams
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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`timescale 1ns / 1ps

module stop_watch_if

input wire clk ,

input wire go, clr,

output wire [3:0] d2, dl, d0

);

// declaration

localparam DVSR = 5000000;

reg [22:0] ms_reg;

wire [22:0] ms_next ;

reg [3:0] d2_reg, d1_reg, d0_reg;

reg [3:0] d2_next , d1_next , d0_next ;

wire ms_tick;

// body

// register

always @(posedge clk)

begin

ms_reg <= ms_next;

d2_reg <= d2_next;

d1_reg <= d1_next;

d0_reg <= d0_next;

end

// next-state logic

// 0.1 sec tick generator : mod-5000000


assign ms_next = ( clr||(ms_reg==DVSR && go) ) ? 4'b0 : (go) ? ms_reg + 1 : ms_reg ;

assign ms_tick = (ms_reg==DVSR) ? 1'b1 : 1'b0;

// 3-digit bcd counter

always@(*)

begin

// default: keep the previous value

d0_next = d0_reg;

d1_next = d1_reg;

d2_next = d2_reg;

if (clr)

begin

d0_next = 4'b0;

d1_next = 4'b0;

d2_next = 4'b0;

end

else if (ms_tick)

if (d0_reg != 9)

d0_next = d0_reg + 1;

else // reach XX9

begin

d0_next = 4'b0;

if (d1_reg != 9)

d1_next = d1_reg + 1;

else // reach X99

begin
d1_next = 4'b0;

if (d2_reg != 9)

d2_next = d2_reg + 1;

else // reach 999

d2_next = 4'b0;

end

end

end

// output logic

assign d0 = d0_reg;

assign d1 = d1_reg;

assign d2 = d2_reg;

endmodule

`timescale 1ns / 1ps

module disp_hex_mux

input wire clk, reset,

input wire [3:0] hex3, hex2, hex1, hex0, // hex digits

input wire [3:0] dp_in, // 4 decimal points

output reg [3:0] an, // enable I-out-of-4 asserted low

output reg [7:0] sseg // led segments

);
// constant declaration

// refreshing rate around 800 Hz (50 MH.z/2"16)

localparam N = 18;

// internal signal declaration

reg [N-1:0] q_reg;

wire [N-1:0] q_next;

reg [3:0] hex_in;

reg dp;

// N-bit counter

// register

always @(posedge clk, posedge reset)

if (reset)

q_reg <= 0;

else

q_reg <= q_next;

// next-state logic

assign q_next = q_reg + 1;

// 2 MSBs of counter to control 4-to-l multiplexing

// and to generate active-low enable signal

always@*

case (q_reg [N-1: N-2])

2'b00:

begin

an = 4'b1110;

hex_in = hex0;
dp = dp_in[0] ;

end

2'b01:

begin

an = 4'b1101;

hex_in = hex1;

dp = dp_in [1] ;

end

2'b10:

begin

an = 4'b1011;

hex_in = hex2;

dp = dp_in [2] ;

end

default:

begin

an = 4'b0111;

hex_in = hex3;

dp = dp_in[3];

end

endcase

// hex to seven-segment led display

always@(*)

begin
case (hex_in)

4'h0: sseg [6:0]= 7'b0000001;

4'h1: sseg [6:0]= 7'b1001111;

4'h2: sseg [6:0]= 7'b0010010;

4'h3: sseg [6:0]= 7'b0000110;

4'h4: sseg [6:0]= 7'b1001100;

4'h5: sseg [6:0]= 7'b0100100;

4'h6: sseg [6:0]= 7'b0100000;

4'h7: sseg [6:0]= 7'b0001111;

4'h8: sseg [6:0]= 7'b0000000;

4'h9: sseg [6:0]= 7'b0000100;

4'ha: sseg [6:0]= 7'b0001000;

4'hb: sseg [6:0]= 7'b1100000;

4'hc: sseg [6:0]= 7'b0110001;

4'hd: sseg [6:0]= 7'b1000010;

4'he: sseg [6:0]= 7'b0110000;

default:sseg [6:0]= 7'b0111000; //4'hf

endcase

sseg[7]= dp;

end

endmodule

`timescale 1ns / 1ps


module stop_watch_if_fpga(

input wire clk ,

input wire go, clr,

output wire [3:0] an,

output wire [7:0]sseg

);

wire [3:0] d2 ,d1 ,d0;

stop_watch_if unit_SW (.clk(clk) ,.go(go) ,.clr(clr) ,.d2(d2) ,.dl(d1),.d0(d0) );

disp_hex_mux unit_DISP
(.clk(clk), .reset(1'b0), .hex3(1'b0), .hex2(d2), .hex1(d1), .hex0(d0), .dp_in(4'b0010), .an(an),

.sseg(sseg))

endmodule

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