Transmitter section: a © The transmitter section accepts parallel data from CPU and converts them into serial data. The transmitter section is double buffered, ic., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits. * When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register. * If buffer register is empty, then TxRDY goes high. * If output register is empty then TxEMPTY goes high © The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART. * The clock frequency can be 1,16 or 64 times the baud rate. Receiver Section: * The receiver section accepts serial data and converts them into parallel data. + The receiver section is double buffered, ic., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data. + When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again. * Ifthe line is still low, then the input register accepts the following bits, forms a charac- ter and loads it into the buffer register. * The CPU reads the parallel data from the buffer register. * When the input register loads a parallel data to buffer register, the RxRDY line goes high. * The clock signal RxC (low) controls the rate at which bits are received by the USART. * During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in » the data transmission. * During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character. MODEM Control: ain is 8251 called a USAR? Define the mode word register a * The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines. « This unit takes care of handshake signals for MODEM interface. - [=] ronous mode. U USART: ‘ammable chip designed for sy It includes Read(The input port and an output are requir Gi) In data transmission, the MPU converts a Par! bits. (iii) In data reception, the MPU converts se! (iv) Data transfer is synchronized between the through time delays. * Since 8251 performs all the above functions on t Mode Word Register of 8251 allel word into a stream rial bits into parallel word, MPU and slow responding perip} the chip, it is called Us Dy | D5 00> 5 bits y 01 6 bite Parity Contot 10-7 bits "> iy 11 ebits ' Framing Control eager eRe E- Barea cone 11 EVEN panty 01 1 stop bit 10-5 1% stop bt 11.5 2600p bts & Fig. 9. 48911. Bxplain 8279 Programmable Keyboard/display i i i play interface with block diag oR Di aw and explain the block diagram of keyboard display controller 8279, >>two key lockout mode or >>N-key rollover, ~ In two key lockout mode if 2 keys are pressed InN key rollover mode, simultaneous keys an can also be set up so that no key is recongnized This has a FIFO RAM. The status logic RQ(interrupt request) signal when FIFO ig until only one key ig Keeps track ;Butlors: (RAM Status eee | pai os Lal ase 254 = Jt esa OUT Ay RY OUT, 8, a Ao Pugh, CMUSTB Fig. 11. 8279 Block Diagram DISPLAY SECTION: This section has 8 output lines divided into 2 groups of 4. A, —A, and B, —B,. These lines can be used in both ways, 8 lines or 2 sets of 4 lines. The display can be blanked using BD line. The section has 16x8 display RAM. SCAN SECTION: This section has scan counter and 4 scan lines. SL, ~ SL,. These 4 scan lines can be decoded using a 4 - 16 decoder to generate 16 lines for scanning. These 16 lines can be connected to rows of a matrix keyboard and digit drivers of multiplexed display. MPU INBTERFACE SECTION: This section has 8 bi-directional lines. DB, — DB,,. 1 ints rupt request line(IRQ). 6 lines for interfacing including buffer address lines A,. When A, is high - signals are interpreted as control word or status. When A, is low - signal is interpreted as data IRQ goes high whenever data is ready to be loaded into MPU. aso] 0! C Q12. Give the block diagram and features of 8259. Ans, Features: * 8 levels of interrupts. * Can be cascaded in master-slave configuration to handle 64 levels of inte * Internal priority resolver. __ * Fixed priority mode and rotating priority mode. . Beeridcally maskable interrupts.— — ye ‘apvancen M ncn 98 — uty} —re.rech)— (UN 086 mode, Provides Ini ion. LL inetruct a byte CA + In 8085 mode, provides number, i pit + Polled and vectored mode umber is Prot Starting address of ISR or vector * No clock required oe m £8259 internal block diagra i. sl roe = Data bus oa able. butter | Read/ We] we | No) toe Beer ssanas— Fig. 12. wv [e253] : Q.13. Explain the block diagram of 8253. Ans. Il examine the block diagram and next I'l explore the internal registers ar tl they are all identical. The block labeled data bus bi i i n to/from the microprocessor, and to the interna se cuties ee ding and the vriting eral 7, contains the programmed £oryln effect this register defines hig Each counter in the block diagram ha in and gate, are inputs, The third, labeled ounce nd depends on how the device i initialized gs on out PUt, The Counters: SRE: There are 3 counters ®t Of €ach othen controls thea oo 39 — [UTU]— [B.TECH — [UNTTAN]— ADVANCED MICROPROCESSORS & en.wikipedia org/wiki/DRAM> memory. The last counter (A1=1, A0=0) generates tones | PC speaker . Besides the counters, a typical Intel 8253 microchip also contains the following components: ote bas |-—cuxo or vo ae) ts 1 cone SED sito: Ky] KO] 70 >= oar cure ieort a —_+d la} w—a4 Foo | fl |-—cuxs ao——+| we ef [o— GATE 1 M+ booie 3) -— our ee ona |—caxe woes a o [oure VA Fig. 13. Block diagram of an 8253 programmable interval timer Data/Bus Buffer: This block contains the logic to buffer the data bus to/ pro- cessor, and i s. Ithas 8 input pins, usually labelled as D7..D0, where D7 is _ the MSB . Read/Write Logic: The Read/Write Logic block has 5 pins, which are listed below. Notice that /K denotes an active low signal. P/RD: read signal + TWR: write signal 4 ICS: chip select signal 4 AO, Al: address lines Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to the Control Word Register, one needs to set /CS=0, /(RD=1, /WR=0, A1=A0=1. . Control Word Register ‘This register contains the programmed information which will be sent (by the microproces- sor ) to the device. It defines how the PIT logi- cally works. Each access to these ports takes about 1 pis. ‘i To initialize the counters, the microprocessor must write a control word (CW) in ter. This can be done by setting proper'values for the pins of the Read/Write Logi then by sending the control word to the Data/Bus Buffer block. Q.14, What are the operating modes of 8253? Miniatiione << OR”a O Word set the operat, Ans. Operation Modes: The D3, D2, and D1 bits of the Control Wor pi ‘ating 3 bit is ignored, so the mime of the timer, There are 6 modes in total; for modes 2.and sare oa dand 4 Gara tty IB modes 6 and 7 are aliases for modes 2 and 3. Notice that, for ‘ i GATE starts the count. set to HIGH to enable counting. For mode 5, the rising edge of Mode 0 (000): Interrupt on iti coe stse dilay under, <0 gaa d s used for the generation of accural ait esc cou Sy ‘ill Recreesnatihg from the initial COUNT value loaded into it, down toy eee Counting rate is equal to the input clock frequency. ; i The OUT pin is set low after the Control Word is written, and cee poe a as s cycle after the COUNT programmed. OUT remains low until the ater meee point OUT will be set high until the counter is reloaded or the Contro! ce ten. 1}, Mode Gate signal should remain active high for normal counting. If Gate goes low counting ga, Th terminated and current count is latched till Gate pulse goes high again. as Mode 1 (001): Programmable One Shot 3 ae In this mode $253 can be used as monostable multivibrator. GATE input is used as trigge, lise input. og OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin th 5 one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high an cae remains high until the CLK pulse after the next trigger. After writing the Control Word and initial count, the Counter is armed. A trigger results: | loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-sha ( pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration. The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after anytrig ger. The one-shot pulse can be repeated without rewriting the same count into the counter ‘ GATE has no effect on OUT. If a new count is written to the Counter during a oneshot pule -cted unless the counter is Tetris the current one-shot is not affe iggered. In that case, the Counte _ is loaded with. Mode 2 (X10): Rate Generator In this mode, the device acts as a divide-by-n counter, which is commonly mera real-time clock interrupt. | then go high again, and the whole Process repeats itself. The time between the igh pulses d ; cone eet iaeed using the flog fea tapend on th preset count.in the counter‘ register, x! Value to be loaded into counter = put f_—- 41 — [UTU) — [B.TECH.] — [UNIT-II] — ADVANCED MICROPROCESSORS & Suppose n is the number loaded into the counter (the COUNT message), the output will be ie 0 + high for $ counts, and low for counts, ifm is even. ‘ n+l - |e high for “counts, and low for "=" counts, it i odd. Mode 4 (100): Software Triggered Strobe After Control Word and COUNT is loaded, the output will remain high until the counter reaches zero. The counter will then generate a low pulse for 1 clock eycle (a strobe) - after that the output will become high again. Mode 5 (101): Hardware Triggered Strobe ‘This mode is similar to mode 4. However, the counting process is triggered by the GATE input. ‘After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle - after that it will become high again, to repeat the cycle on the next rising edge of GATE. Q.15. Explain the interrupt structure of 8259? (UTU 2012-13) Ans. Interrupt structure of 8259 Z ~ (® Manage eight interrupts according to the instructions written into its control registers. ~ (i) Vector an interrupt request anywhere in memory map. (Gi) Resolve eight levels of interrupt priorities in variety of modes. (iv) Mask each interrupt request individually, = (v) Read the status of pending interrupts, inservice interrupts and masked interrupt. (vi) Be set up to accept either level or edge triggered interrupt request. (vii) Be expanded to 64-priority levels by basically addition 8259.INTRODUCTION TO 80186,80286,80486 Q.1. Show the block diagram of 80186 and explain its memory organiz ee Address bus (20 bits) General registers ALU data bus (16 bits)The Execution Unit executes all instructions, provides data and addresses to,the Bus. | Interface Unit manipulates the general registers and the Processor Status Word. The 16-bit ALU within the Execution Unit maintains the CPU status and controls flags and manipulates the general registers and instruction operands, All registers and data paths in the Execution Unit are 16-bits wide for fast internal transfers, Memory organization of 80186: Program memory—program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction. Data memory—the processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment). Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access, Stack memory can be placed anywhere in memory. The stack can be located at odd memory addresses, but it is not recommend led for performance reasons (see “Data Memory” above). Reserved locations: 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment:offset. FFFF0h - FFFFFh - after RESET the FFFF0h address. Q2. Explain the registers of 80186. Ans. Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instr ‘uctions, stack, data and extra data. To specify wherein 1 MB of processor memory these 4 segments are located the processor uses four segment registers: Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor ipstructions, The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register ie automatically updated during far jump, far call and far return instructions, Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. Data segment (DS) is a 16-bit register containing address of 64KB segment with data, By default, the processor assumes that all data referenced by general registers CX, DX) and index register (SI, D1) is located in the data segment, DS register can be using POP and LDS instructions. r Extra segment (ES) is a 16-bit register containing address of 64KB segment, u ogram data. By default, the processor assumes that the DI regi, fer rin manipulation instructions, ES register can be changed x processor always starts program execution at the program (AX, BX,CESSORS & conTroLers a __44— [UTU) — [B.TECH] — [UNIT] — ADVANCED MICROPI __ It is possible to change default segments used by general and index registers by prefixin instructions with a CS, SS, DS or ES prefix. All general registers of the 80186 microprocessor can be used operations. for arithmetic and log, —~ Q.3. What are the general purpose registers of 80186/ Ans. Accumulator register consists of 28-bit registers AL and AH. which can be combine, together and used as a 16-bit register AX. AL in this case contains the low-order byte of thy word, and AH contains the high-order byte. Accumulator can be used for I/O operations ane a string manipulation. bit registers BL and BH, which can be combined together ane “BL in this case contains the low-order byte of the word, and Bi @.5. WI ‘ains a data pointer used for based, base: Ans- In Reg CH, which can be combined together ane = Imn Base register consists o! used as a 16-bit register B: contains the high-order byte. BX register usually cont: indexed or register indirect addressing. Count register consists of 2 8-bit registers CL and cased ae-a 16-bit register CX. When combined, CL register contains the low-order byte of th Dir word, and CH contains the high-order byte. Count register can be used as a counter sn strin Reg manipulation and shifUrotate instructions. located Data register consists of 28-bit registers DL and DH, which can be combined together ani Bas cused as a 16-bit register DX. When combined, DL register contains the low-order byte of the Bp), t sword, and DH contains the high-order byte. Data register can be used as a port number indO tpg Gperations. In integer 32-bit multiply and divide instruction the DX register contains high 4. pp) order word of the initial or resulting number. a ‘The following registers are both general and index registers: : aa Stack Pointer (SP) is a 16-bit register pointing to program stack. a Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is _contes usually used for based, based indexed or register indirect addressing. pointe ‘Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Q Destination Index (DI) is a 16-bit register. DI is used for indexed, based i fend Nien indexed . y indirect addressing, as well as a destination data address in string manipulati register indi manipulation Ans. Q4. Explain the flags of 80186, ‘Ans. Flags is a 16-bit register containing nine 1-bit flage: ‘+ Overflow Flag (OF) - setifthe result: b Be io ir into deal sparen. Arte Positive number, or is too amall negativeAnd 45— [UTU] —[B.TECH.] — [UNIT-Itl] — ADVANCED MICROPROCESSORS & CONTROLLERS lo, Bis * Zero Flag (ZF) - set if the result is zero. * Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bite 0-3 in the AL OMbing register. te of int * Parity Flag (PF) - set if parity (the number of “1” bits) in the low-order byte of the result Ons a, ng is even. * Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit hey ang during last result calculation. 7d By @.6. What are the addressing modes of 80186, , base) Ane. Implied - the data value/data address is implicitly associated with the instruction Register - references the data in a register or in a register pair. er ore Immediate - the data is provided in the instruction, : a Direct - the instruction operand specifies the memory address where data is located. ng Register indirect - instruction specifies a register containing an address, where data is ; located. This addressing mode works with SI, DI, BX and BP registers, of th Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or in Pa BP), the resulting value is a pointer to location where data resides, Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DD), the resulting value is a pointer to location where data resides Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the rk contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a Pointer to location where data resides, St! Q.6,Give the architecture and key features of 80286, oR ané Draw and discuss the internal block diagram of 80286. (UTU 2011-12) 10" Ans. Key Features: * 16-bit date bus * 24-bit non-multiplexed bus * Packaged in a 68-pin ceramic pack ve * 80286 has 2" = 16 M Byte of physical memory accessibility (Physical address Sogmont| adder sizos Address latches and driven Processor i extension Soginent interlace Ottsot oan adder Bus control Bus transceivers 6 Byte pre-latch queue 3 Decoded instruction queue Instruction decoder Instruction unit (IU) N — M | BUSY INTR ERROR Fig. 2. Basic Architecture of 80286 Q.7. Explain the memory addressing in 80286. Ans. Memory Addressing in 80286: 1. Real Addressing Mode - It is just like as in 8086. Address is 20 | and 16 bit offset. When 80286 is hardware reset, it automatica mode. 2. Protected Virtual Addressing Mode (PVAM) - In this we have 1G and 16 Mbyte of physical memory. The address is 24 bit. To enter Status Word (PSW) is loaded by the instruction LPSW. 15Qs. Give an introduction to 80486 CPU 80486 DX from Intel is the first 32-bit microproc Freed enhancement. 80486 has five stages of pipelining. Two out of five stages see weed for decoding complex instructions of 80486 architecture. The 80486 is also the fest the fax86 processors to have an on-chip cache. This 8 Kbytes of cache is a unified date et one and acts on the physical addresses, 4 unified data and code cache Note: 80486 SX does not have floating point unit 32-bit address linés: (A, -A,,, BE, - BE, ) 92-bit data lines: (D ,- D,,) S2-BIT Data Bus Linear address bus [eae "| US Inerace [Seqmeniaton ndaross Pate a | no 131 ‘unit Fa Cache unit vers pe Ao AST Dessipior|| unt” [Pryscer -—__| Bacal" |_reasters ee act) tants index | Umit and —] | Trenstation aoe transcenvers [00-031 Tae | ‘ature || Toskgelse us contd 4 Fes feb cont Displacement bus Prefetcher 32-Byte code queue asus Decode ut Decoded instruction Coniror path Fig. 3. Improvements: The instruction set of the i486 is very similar to its predecessor, the Intel 80386 with the addition of only a few extra instructions, such as CMPXCHG which executes the compare- and-swap. The XADD which executes the fetch-rind-add returning the original value, unlike the ADD instruction that only returned some flags. From a performance point of view, the architecture of the i486 is a vast improvement over the 80386. It has an on-chip unified instruction and data cache an on-chip floating-point unit (FPU), except in the SX and SL models, and an enhanced bus. Simple instructions (such as ALU Teg, reg) execute in one clock cycle. These improvements yield a rough doubling in ALU performance over the 386 at the same clock rate. A 16-MHz 486 therefore has a performance similar to a 33-MHz. 386 and the older design has to reach 50 MHz to be comparable with a 25- MHz 486 part.80486? Q.9. What are differences between 80386 and Ans. + An 8 KB on-chip SRAM stores cae +h internal cache but sup) Pi tastriction uy. 2 Ba abind pipelining allows the 486 to Be oe ine on ke y ‘ Bee ALU reg,im overy clock cycle. The 386 nee ee an ; j 5 Js) with a ;togey, . FPU (disabled or absent in SX model eee Seatac slbeeieinse on more extensive hardware eee 1887, this gives,” floating point calculations compared to the i386 combination. * Improved MMU performance. : : ‘The 486 has a 32-bit data bus and a 32-bit address bus. oe Pinte na 30-pin (8-bit) SIMMs or one 72-pin (32-bit) SIMM on a pris meprecars, Jost ty 80386, the 82-bit address bus of the 80486 enabled up to 4 gigabytes of memory to be dir addressed using a flat memory model with 32-bit linear addresses in pro node, dt with the 80386, the ability to use memory directly without segmentation helped performanc. compliant operating systems and applications. PENTIUM MICROPROCESSOR Q.10. Explain the architecture of Pentium microprocessor. Ans. The Pentium family oftprocessors originated from the 80486 microprocessor. The tex “Pentium processor” refers to a family of microprocessors that share a common architectu and instruction set. The first Pentium processors were introduced in 1993. It runs at a clo: frequency of either 60 or 66 MHz and has 3.1 million transistors. Some of the features of Penti: architecture are * Complex Instruction Set Computer (CISC) architecture with Reduced Instruction &: Computer (RISC) performance. + 64-Bit Bus * Upward code compatibility. * Pentium processor uses Superscalar architecture and hence can issue multipl instructions per cycle, * Multiple Instruction Issue (MII) capability. * Pentium processor executes instructions in five stages. This staging, or Pipelining, allow the processor to overlap multiple instructions so that it takes less time co execute tw instructions in a row. instructions and data, 7p, t recently used ins\ J vied a alower off-chip cache. " « The Pentium processor fetches the branch target instruction before it executes the bran¢ instruction, * The Pentium processor has two separate 8-kilob instructions and one for data. It allows the instructions from the cache simultaneously. * When data is modified only the data in the cache ie changed, Mfemory data ie cheot™! only when the Pentium processor replaces the modified data in the cache with «afer set of data yte (KB) caches on chip, one fo! Pentium processor to fetch data ao!* The Pentium processor haw clock cycles than the 80486 pro Integer ALU] | Integor ALU Rogistor Set Data Cache Fig. 4. Architecture of Pentium Q11 Explain the Pentium pipeline stages. ‘Ans. The Pentium’s basic integer pipeline is five stages long, with the stages broken down as follows: Pre-fetch:Instruction J Decode Instruction and generate,control word Generate control word Generate contro! word Generate data memory address Generate data memory addres Access data cache Access data cache Calculate ALU result Calculate ALU result Write back result Write back result t UPipe V Pipe Fig. 5. Pentium pipeline stages 1. Pre-feteh/Fetch : Instructions are fetched from the instruction cache and aligned in pre-fetch buffers for decoding.m’s internal instruction formas, Br, 4 51 — [UT if necessary. Also, a4, 3 Ny The 2, Decode1:Instructions are decoded into the Pentiw prediction also takes place at this stage. artis, 8. Decode? : Same as above, and microcode ROM kicks in Intel computations take place at this stage. r wt use dui 4. Exeoute : The integer hardware executes the instruction. ee chip. 5. Write-back : The results of the computation are written back to the register fil. Totes Q.12. Explain the operating modes and floating point of Pentium microprocess, 4 single 5 Ans. The Pentium processor has two primary operating modes- ‘ pls i a 1. Protected Mode - In this mode all instructions and architectural feature, wlpeata available, providing the highest performance and capability. This is the recommen,,_ ethan mode that all new applications and operating systems should target. ne 2. Real-Address Mode - This mode provides the programming environment of the [n),(] see at | ‘8086 processor, with a few extensions. Reset initialization places the processor in »-, WOive mode where, with a single instruction, it can switch to protected mode 3. Floating Point Unit : There are 8 general-purpose 80-bit Floating point registzy. Floating point unit has 8 stages of pipelining. First five are similar to integer un; Since the possibility of error is more in Floating Point unit (FPU) than in integer un: additional error checking stage is there in FPU. The floating point unit is shown a 1s. Core below: Exponent aut], -_{— wantssaosuk FAO =" FEXP FADD re rele: ro] Lee] a veessor 2 ne inb FANOIPMUL fore ature: Fig. 6. Floating Point Unit FRD - Floating Point Rounding FDD - Floating Point Division FADD - Floating Point Addition FEXP - Floating Point Exponent FAND - Floating Point And FMUL - Floating Point Multiply INTRODUCTION TO DUAL CORE AND CORDTO DUO. e smar wnning’ Q.13. Give an introdu ajead Ans. A dual-core processor is a CPU with two “ . wese sys integrated circuit. Each processor has its own cac} 2 aportarThe Intel Core Duo, the AMD X2, and the dual-core PowerPC G! 5 z 5 are all examples nat use dual-core technologies. These CPUs each combine two processor cores on icon chip. This is different than a “dual processor” configuration, in which two phy sparate CPUs work together. However, some high-end machines, such as the Po juad, use two separate dual-core processors together, providing up to four times the p fa single processor. While a dual-core system has twice the processing power of a single-processor oes not always perform twice as fast. This is because the software running on the ay not be able to take full advantage or both processors. Some operating systems and re optimized for multiprocessing, while others are not. Though programs that have been — ptimized for multiple processors will run especially fast on dual-core systems, most programs “ill see at least some benefit from multiple processors as well. gATive an introduction to Core to duo. ns. Core 2 is basically a brand name which refers to the wide range of Intel's processors. The - esign of the core 2 duo processors is based on the Intel's micro architecture range. These sodels are embedded on single die or integrated circuit unlike quad core processors which are mbedded on the two IC's. However core based processors lack in Hyper threading technique. this technique enables the user to perform multiple tasks simultaneously using software and rocessor at the same time. This brand came to the knowledge in 2006. tange of core 2 Processors = There is a wide variety and range of products associated with the core 2 Duo technology. yore 2 Duo with a processor £4300 was released in 2007 having L2 cache of 2MB. The next rocessor is known as core 2 Duo E4400 released in April 2007. Core 2 Duo £4500 and E4600 vere released in 22 July and October, 21 2007 respectively.:These processors also contain the 2 cache of about 2MB. Core 2 duo E4700 was released in 2008 in the month of March. This srocessor has the frequency rate of 2600MHz with L2cache of 2MB. Intel core 2 duo processors ome in both 45nm and 65nm having virtualization, trusted exect ‘on technology and clock speed of about 2 GHz. Features of Core 2 Duo Core 2 Duo is a wave of technology and improved processors. This processor is entrenched with variable features. The core 2 Duo processors have sustained the backward compatibility with the software and existing hardware. Though the older hardware is not capable of making use of the advanced features of the core 2 duo still they are compatible to work well with them. Instead if we put it in other words our supporting processor is able to match well with ther. The existing motherboard like Intel LGA 755 is capable enough to accept the core 2 duo processing only with the up gradation of BIOS. Modern core 2 Duo processors are also efficient enough to run two operating systems at a time by help working virtual machines, The virtual machines are smart enough to share physical hardware, having separate operating system and busy running their own applications. Therefore core 2 Duo processors have removed the need for the high end servers. The inclusion of advanced security features is also a drastic improvement in these systems. It is core 2 Duo which has enabled to set the trusted Platform Module as an important standard for upcoming PC's.2 Q.15. What are the improvements to core eta Ans. The introductions of core 2 duo processors ha’ tion has helped in increasing tt he books. The features like appropriate power consump’ roved core 2 processors are," . life of the current net books, Besides being really ae ower needs needed to chary: cache. This compromise is made in order to aie ie eee Allendale processor, computers. However the cache size is varied. Like for xe Weetits Merom pro a cache while Conroe has 4 MB cache, The reduced power ni ee cars oo made it desirable to use for net books. The cache utilization is regarding iy a 2 do pn . 'Samazing as the 2core allows the caches to compete for cache allocation. T me Be the re Speed of the processor is simple remarkable. Moreover the processor is capable of ry, instructions in single clock cycle, This is the highest speed as compared to the previous , Core 2 duo processors have the capability to replace AMD's 4 core processor which wa, , to beat the efficiency of the core 2 Processors and their underlined features. Q16. Discuss crystal frequency versus machine cycle. Write 8051 Progra, generate a time delay. (UTU 21) Ans. Crystal Frequency vs Machine Cycle: The clock frequency ‘¢ establishes the. interval of time within the Microcontroller, called pulse ‘P time. The smallest internal ¢ di pecomplish any simple instruction, or part of a complex instructions is the machin The machine cycle is itself made up of 6-states, A state is the basic time interval for dis eperations of the micro controller such as fetching an opepde byte, decoding an opcode, exes, an opeode or writing a data byte. Two oscillator pulaes define cach state. oS Po Pel) APE SPRUMP: SP, Py Eyase, wm LLL LL] e}.| -™ 0 improved the functionin, Seen Cee 6 —— ee One Machine Cycle per Fig. 7, , Time Delay program: (Software time {t uses 12 Milz crystal for a loop delay of 1 me, 5 fau- delay, 0a 6 h ; 166 x 6 eycles = 996 loop cycles £ au. dlysb, Of 4h ; try 500 (1f4h) me; LSB ia A * equ. dlymsb, 01h ; MSB in B delay) * org 0000 h Blink: ; Set b ns j i demonstrate a L-sec LED blink rate : ; mov a # dlylsh ; pass the designed delay ti i 3 mov Voy algae y time to softtime 4 ( a call softime ‘ call for 500 ms delay @ 12 MHz : dr pl. 0 stun off LED 6 mOv a, # dly Ish delay another 500 me, 1 mov b, # dly insb 8 a call softime sjmp blink’ j loop to start Roy Softime {me delay routine named “softime” ee push 07 h ; overhead of; 2 cycles,push ace orl a, b cive a, # OOH, OK pop ace simp done OK: pop ace Timer: mOv r7, # delay Onemil nop nop nop nop djnzr7, one mil nop nop dec a cine a, # dffh, noroll dec b no roll: cine a, # 00 h, timer cjne a, b, timer done: pop 07 h ret end Q.17. Explain the feature Ans. Feature: . Contains 21 million ; 2only if A =B ; 2 3 Soverhead cycles to enter. +1 for mOVR7, total loop; 1004 cycles 51 for each NOP this loop takes 6 cycles: total 996 cycles 52 for the DINZ 51 for the NOP 31 for the NOP :1 for DEC, 1000 cycles at this point E ; 2 cycles to see if rollover. joverhead of 1 cycle each B decrements j;adds B cycles to total delay :2 cycles to see if done ;overhead to 2 cycles each B + 1 decrement jadds 2B + 2 cycles to:total delay yoverhead of 2 cycles to return overhead of 2 cycles to return ‘ 4 cycles to return of different available advance microprocessors. (UTU 2012-13) transistor, 3 integer units as well as floating point unit to increase the performance of most software. |. contains 256 k level saeE Basic clock frequency is 150 MHz and 160 MHz. Internal 16 k level one (11) cache 8 K for date & 8 k for instructions. two (L2) cache. . It used 3-execution engines so it can execute up to three instructions at a time, which conflict & still execute in parallel. ae It is optimized to execute 32-bit code effectually. It can address either a 4 G byte memory system or a 64 G byte memory system. 8. It has 36 bit address but if configured for a 64 G memory system. Q.18. What is the difference between dual core and core to duo, (UTU 2012-13) Ans. Please see Q. 13 and 14 of same unit. oo0o0Program Address Register [r2con | tan | tHo_| ntorrupt, Serial Port, and Tuner Blovhs Turn tag! [instruction Control RegisterSS = WT) — fe.tecHy — tunmavy Pin Description “0 ton Signal eh logical tate on tn ane ee unto this pin back to k turned on. ‘Bical state zero atarts the program snocinted don il a x anew as if the ‘ort 3 = As with Py Olea ri ‘ort 1, each However, each pin of Port 9 hye tof these pins can be fs of Port 3 1 used as universal input Pin 10: RXD - serial input aah ee te for comituniont asynchronous communication or serial output for Pin 11: TXD- cemimuniaton, utr as Pin 12: INTO - input for interrupt 0. Pin 13: INT1 - input for interrupt 1. Pin 14: TO - clock input of counter 0. Pin 15: 71 - clock input of counter 1 Pin 16: WR - signal for writing to external (add-on) RAM memory. Pin 17: RD - signal for reading from external RAM memory. ae X2 and X1; Input and output of internal oscillator. Quartz crystal controlling the quency commonly connects to these pins. Capacitances within the oscillator mechanism (see the image) are not critical and are normally about 30pF. Instead of a quartz crystal, miniature ceramic resonators can be used for dictating the pace. In that case, manufacturers recommend using somewhat higher capacitances (about 47 pF). 20: GND. Ground 21- 28: Port 2 - If external memory is not present, pins of Port 2 act as universal input/output. If external memory is present, this is the location of the higher address byte, ie. addresses A8 - A165. 29: PSEN - MCU activates this bit (brings to low state) upon each reading of byte (instruction) from program memory. If external ROM is used for storing the program, PSEN is directly connected to its control pins. 80: ALE -Before each reading of the external memory, MCU sends the lower byte of the address register (addresses AO - A7) to port PO and activates the output ALE. External register (74HCT373 or TAHCTS75 circuits are common), memorizes the state of port PO i ‘and uses it as part of the address for memory chip. upon receiving a signal from ALE pin, 1 on ALE is off, and port PO is During the second part of the mechanical MCU cycle, signal on ALE is off, and ps twed 26 Data Bus. ro (mass) designates the ports P2 and P3 for : i in to the logical state ze: ; Ried Brings pers to leas of the presence of the internal memory’ This means that transferring addresses FG)" Ts the MCU it will not be executed, but the one from the if he high logical state even if there is a program ew ; tead, Conversely, bringing the pin oe re is e Ba eae first the internal, and then the external (if present). Care Port 0 can be used as universal input/output, if REAR art 0.2 Similan i ot oot | memory is used, PO behaves as address output (A! external memory is not use ynchronous communication or clock output for synchronous. put (Data Bus) when ALR - A7) when ALE pin is at high logical level, or as data outp' RE Tow logical level. 40: VCC - Power +5V, Pin, 57- ‘ort 3 controller. Bg Difference in microprocessor and micro-control ies Microprocessor se in or two operational coq, (@ Have many operational codes for moving It has one data from external memory to the CPU. moving data from external mem, CPU. | Gi) Te may have one or two types of bit- ~ Ithas many types of bit handling | __ handling instructions. : instructions. / @ Icis concerned with rapid movement of | ~ It is concerned with Tapid movemen, code & data from external addresses to of bits within the chip. the chip, () Tt must have ma: my additional parts to — It can function as a computer with tp, be operational. addition of no external digital parts Q2. Exp! the followi, ing consequences: ving the infini: mei SE Port bit grounds th: °F ‘akes the pin act as hi, e, 5V) at output, external ” Bape added for comecting Be pints mae xternal “pull Up" resistor needs to b wri Port 1 a This is “true” V/O port, devoid of d i br As ” ual function, charact sti re "esisor Port Lis fully compatible with tt iret MBC foe Pore, Flaving the pull’ fog Port 2 ; When using external memor a 'Y, this: Port conta: M0), similarto Port 0, Otherwie, Wome used as univer ren oo Port. emPort 3 oe . i i Beside its role as universal I/O port, each pin of Port 3 has an alternate function. use one of these functions, the pin in question hai i 18 to be designated as i Le. pit of register P3 needs to be sot. From a hardware standpolat, Port Se vais Port MEMORY ORGANIZATION IN 8051 i Sc Memory Organization in 8051. The 8051 has three very general ty; aoe Gab Momory, and External RAM On - Chip: On-Chip Memory refers to any memory (Code, RAM, or other) te ah ‘y (Code, RAM, )) that physically Fetecae microcontroller itself. On-chip memory can be of several types, but we'll get into External Code Memory: External Code Memory is off-chip. This is often in the form of an external EPROM. Se OTE a ae External RAM: External RAM is RAM memory that resides off-chip. This is often in the form of standard static RAM or flash refers to any memory (Code, RAM, or other) that physically exists on the microcontroller itself. On-chip memory can be of several types, but we'll get into that shortly. Code Memory: Code memory is the memory that holds the actual 8051 program that is to perun. This memory is limited to 64K and comes in many shapes and sizes: Code memory may be found on-chip, either burned into the microcontroller as ROM or EPROM. Code may also be stored completely off-chip in an external ROM or, more commonly, an external EPROM. Flash RAMis also another popular method of storing a program. Various combinations of these memory types may also be used—that is to say, it is possible to have 4K of code memory on-chip and 64k of code memory off-chip in an EPROM. External RAM: As an obvious opposite of Internal RAM, the 8051 also supports what is called External RAM. As the name suggests, External RAM is any random access memory which is found off-chip. Since the memory is off-chip it is not as flexible in terms of accessing, and is also slower. For example, to increment an Internal RAM location by 1 requires only 1 instruction and 1 instruction cycle. To increment a I-byte value stored in External RAM requires 4 instructions and 7 instruction cycles. In this case, external memory is 7 times slower! On-Chip Memory: As mentioned earlier, the 8051 includes a certain amount of on-chip memory. On-chip memory is really one of two types: Internal RAM and Special Function Register (SFR) memory ’ The 8051 has a bank of 128 bytes of Internal RAM. This Internal RAM is found on-chip on the 8051 60 it is the fastest RAM available, and it is also the most flexible in terms of reading, writing, and modifying its contents. Internal RAM is volatile, s0 when the 8051 is reset this memory is cleared. The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8 bytes (00h - 07h) are “register bank 0°. By manipulating certain SFRs, a program may choose to use register banks 1, 2, or 3. These alternative register banks are located in internal RAM in addresses 08h through 1Fh Bit Memory also lives and is part of internal RAM. Bit memory actually resides in internal RAM, from addresses 20h through 2F'h. The 80 bytes remaining of Internal RAM, from addresses 80h through 7Fh, may be used by user variables that need to be accessed frequently or at high- speed. This area is also utilized by the microcontroller as a storage area for the operating stack.Sy reserved for the stack i, \ ‘This fact severely limite the 8051's stack since, the area Ttack ans! %, 50 the stack andy. %, = be shared between iter and usually itis less since these 80 bytes has to oS Ni synonys BOB MICROCONTROLLER Intomal RAM External Code loternal Code (Optional) Fig. 2. Give a short note on registers of 8051, OR Explain the register bank, selection of register bank: Pro of 8051? Which bits of the PSW are responsib|. ‘s? oR Give the format of PSW in 8051. (TU 2011 : Ans. Register banks: On chip memory MAP in 8051 ‘The 8051 uses 8“R” registers which are used in ‘any ofits instructions, These “R’ regis generally et 0% 0 through 7 (RO, Ri, Re, Rw R5, R6, and R7). These registe. woefully used to assist in manipulating valnee eo moving data from one memory locati @ | Another. Forexample, todd the valucatRa the Accumulator, we wouldexecute tenn, instruction: rel ADD A, Ra on inius ifthe Accumulator (A) contained the value Gand R4 contained the value 3, the Accumulator would contain the value 9 after this instr However, ‘uction was executed, - 28 the memory map shows, the “R° Register Rd is really Part of Internal RY Specifically, RA is address 04h, Thus the above instruction accomplishes the same thing ast following operation; ADD A, 04h ! 2 the value found in Internal RAM address 04h to the value of! Accumulator, leaving the result in the A « ‘ccumulator. Since R4 18 really Internal RAM 04h, b above instruction effectively accomplished the same thing. As the memory map shows in Fig, 4, the 8051 is first booted up, regiexample, if your program instructs the 8051 to register bank synonymous wit Internal RAM address 1Ch, ge a 1AM cuor ~ on 10 18 », Gus 00-9F - Bis 40-76 % General 1 FAM 7 20 SFR Fig. 4. oR Program status word (PSW) register. Teoris8s 18BiotwAve 9:8 ivislar uel cy | ac | ro | ast] aso] o | — | e Fig. 3. Bit Symbol Function Be RIS i + Register bank select bit 1 3 RSO + Register bank select bit 0 Bits 4 & 3: are responsible for selection of register banks. Q5. Give Special function register of 8051 and its type. Ans. Special Function Registers (SFR): The 8051 is a flexible microcontroller with a relatively large number of modes of operations. Your program may inspect and/or change the operating mode of the 8051 by manipulating the values of the 8051's Special Function Registers (SFRe). SFRs are accessed as if they were normal Internal RAM. The only difference is that Internal RAM is from address 00h through 7Fh whereas SFR registers exist in the address range of 80h through FFh. Each SFR has an address (80h through FFh) and a name. Although the address range of 80h through FFh offer 128 possible addresses, there are only 21 SFRs in a étandard 8051. All other addresses in the SFR range (80h through FFh) are considered invalid. Writing to or reading from these registers may produce undefined values or behavior. SFR Types: The SFRs that have a blue background are SFRs related to the I/O ports. The 8051 has four I/O ports of 8 bits, for a total of 32 1/0 lines. Whether a given I/O line is high or low and the value read from the line are controlled by the SFRs in green. TCON controls the timers, SCON controls the serial port.t ‘These SFRs can be thought of as auxilia, eae 4 ie bviously the 8051 ¢ The remaining SFRs, are “other ae y the A | ithout them. For example, once the alates Bia avec ta el port using the SBUF reg! a interru will be I function registers. 2 . Explain spand DPL/DPH Special J Ber eres Address 81h); This is the stack pointer of th i ns. . Q9. 8h take Will be tend from in j,,"\ %9- Sh indicates where the next value to be taken from the st Baeicste vain, a) Filta ie ontothe tac, the value willbe written a Re viont stack at address 08h, This SFR is modified by all instructions Rae tent i PUSH, POP, LCALL, RET, RETI, and whenever interrupts are provol ero. DPLDPH (Data Pointer Low/High, Addresses 82h/83h): The SFRs DPL and yp, together to representa 16-bit value called the Data Poi inter. The data Sad fen Bo rat, Pegarding external RAM and some instructions involving code seep. E ee an unsig, two-byte integer value, it can represent values from 0000h to FFFFh (01 hrough 65 Q 5 de ve short note on. ‘TCON,TMOD And SCON Special Functions. (UTU 201; ly ‘ON (Timer Control, Addresses 88h, Bit-Addressable): The Timer Control : The Serial Control SFR This SFR controls the bau. al port is activated to recei eive data, and also contai, flags that are set when a byte is Successfully sent or received. , @8. What are the IIS AND 1p or Define the interuppt priority of 8051, (UTU 2012-13) up Ans. IE (Interrupt Enable, Adresse, Ash): The Interrupt Enable SER ic Used to enable 6°! and disable specific interrupts, The low Ths) He SER ate used to enable/dieatt, the specif’ Us interrupts, whereas the highest itis wed yo sable or disable ALL interruncs ‘Thus, ifthe hish bit of1E is 0 all interrupts are disablon *egardless of whether an individuay interruptisenabel ms by setting a lower bit. meow! TP nterrupt Priority, Addresses Bah, Big example, if we configure the 8051 so that all interrupt, the serial interrupt will always be 4interrupt is currently executing. However, if a xecuting rrently \ , if a serial interruy i oth will be able to interrupt the serial interrupt routine since Ae see eee highe: priority. Q9. Short note on: (a) SBUF (b) PSW ; (c) ACC Ans. SBUF (Serial Control, Addresses 99h): The Serial Buffer SFR is used to send and receive data via the on-board serial port. Any value written to SBUF will be sent out the serial ports TND pin. Likewise, any value which the 8051 receives via the serial port's RKD pin will Pedaliveredto the user program via SBUF, In'other words, SBUP eerves ad tte oem when written to and as an input port when read from. sh PSW (Program Status Word, Addresses Doh, Bit - Addressable): The Program Status Word is used to store a number of important bits that are set and cleared by 8051 instructions. The PSW SFR contains the carry flag, the auxiliary carry flag, the overflow flag, and the parity fag. Additionally, the PSW register contains the register bank select flags which are used to select which of the “R” register banks are currently selected. ACC (Accumulator, Addresses E0h, Bit - Addressable): The Accumulator is one of the most-used SFRs on the 8051 since it is involved in eo many instructions. The Accumulator resides as an SFR at EOh, which means the instruction MOV A,#20h is really the same as MOV F0h#20h. However, it is a good idea to use the first method since it only requires two bytes whereas the second option requires three bytes. TIMERS: Q.10. Explain the Timers of 8051. (UTU 2012-13) Ans. The 8051 comes equipped with two timers, both of which may be controlled, set, read, and configured individually. The 8051 timers have three general functions: 1) Keeping time and/or calculating the amount of time between events, 2) Counting the events themselves, or 3) Generating baud rates for the serial port. How does a TIMER count ? How does a timer count? The answer to this question is very simple: A timer always counts up. It doesn’t matter whether the timer is being used as a timer, a counter, or a baud rate generator: A timer is always incremented by the microcontroller. Using TIMER to measure Time Obviously, one of the primary uses of timers is to measure time, When a timer is used to measure time it is also called an “interval timer” since it is measuring the time of the interval between two events, How long does a ‘TIMER tale a count ? First, when a timer is in interval timer mode (as opposed to event counter mode) and correctly configured, it will increment by 1 every machine cycle, A single machine cycle consists of 12 crystal pulses. Thus a running timer will be incremented;oe 11,059,000 / 12 = 921,583 is re. 921,583 times per second. Unlike instructions—some of which require chine cy, i ted 7 2, and others 4—the timers are consistent: They will always ee tite once per cycle. Thus if timer has counted from 0 to 60,000 you may cal ‘ “Ys me tim ‘ying ser Syne 50,000 / 921,583 = 0542 tra lir -0542 seconds have passed, In plain English, about half ofa tonth of a second, or One-tiven, Heed ‘of a second. nd of Obviously its not. very useful to know .0542 seconds have passed. If you want to wait for the timer to count from 0 to 50,0 event once per second you'd have How can you wait “half of a time?” to exec, rial 5 100 18.45, ®ansm: F it, You can’t. So we come to another important Calculation “E021 ee an: nchré ‘Let's say we want to know how many times the timer will be incremented in .05 Seconds i can do simple multiplication: 05 * 921,583 = 46,079.15, Asy ‘This tells us that it will take 05 mmu seconds (1/20th of a Second) to count from 0 to 46,079, Actua, the t somite it 049999887 seconds ac were off by gnal 000000163 seconds—however, thats close enough for ight Eorsmment work. Consider that if you were building a ck [ teaa]ne fs watch on the 8051 and made the above assumption. data. your watch would o: 7 wet , gain about one second every 2 ad in months. Again, I think f requires ine or 1, ta mm nger distances. The obvious ira) 1s the reduction in the data. ‘ee to settle on the data bus, we ‘nication. If we imagine the compared with Paralle! here it takes lus for dat byte using parallel} cor tem wI adata63 — [UTU] — [8.TECH.] — [UNITV] — ADVANCED MIGROPROCESSORS & CONTROLLERS _ me for data bi i same timeframe its settling on the serial line, it transfer byte {aing serial communication (us for each bit), Sree ae synchronous Serial Communication : Synchronous serial communication requires an extra line for the clock signal. For serial communication, the 8-bit parallel data byte must be Shifted down the serial line (in transmission), Therefore, one bit is followed by another. Some kind of system must be used to determine how long each bit is on the line, For exaiyl, the serial ystem designer may decide each bit will be on the line for 1us and, as explained above, Seansmission of the full eight bits would take Bus, With synchronous communication, the cloce Signal is transmitted on a separate line, as shown in the diagram. In this way, the receiver is gynchronized with the transmitter. As we shall see, the 8051 serial port in mode 0 is an example of eynchronous serial communication. ‘Asynchronous Serial Communication: A good example of asynchronous serial ‘communication is the interface between a keyboard and a computer. In this case, the keyboard je the transmitter and the computer is the receiver. With asynchronous communication, a clock ‘Gqnal is not sent with the data. There are a number of reasons why this form of communication ‘tbe desirable over synchronous communication. One advantage is the fact that the physical tine for the clock is not needed. Also, asynchronous communication is better over long distances Ifwe try to synchronize a remote receiver by sending the clock signal, due to propagation delays ‘and interference, the validity of the clock is lost. Another reason for not transmitting the clock rises when the data rate is erratic. For example, data rate from a keyboard to a computer is dependent upon the typist. The user may type at a rate of sixty words per minute, but at. other times he/she may type a lot less. And for long periods there may be no data sent at all, Because of this erratic data rate an asynchronous communication system is suitable. Q.12. Explain the serial communication protocol. ‘Ans. Serial Communication Protocol: In any communication system, the receiver must know what kind of data to expect and at what rate the data will arrive. In both synchronous and asynchronous serial communication, the receiver needs to know with which bit the transmitter begins. In most systems the LSB is the first bit transmitted. For an asynchronous system, the number of bits transmitted per second must be known by the receiver. Since the clock signal is not transmitted, the receiver needs to know what clock frequency the transmitter is using so that it can use the same. The receiver also needs to know how many bits per word the transmitter is using (in most cases we deal with 8-bit words, but we will see cases where nine bits are transmitted per word). And the receiver needs to know where the data begins and where the data stops. All these parameters make up the protocol. If the receiver uses the same protocol as the transmitter is should receive the data correctly (although errors can occur and we will look at how we catch these errors at a later date). If the receiver uses a protocol other than the one used by the transmitter, then the two devices are effectively speaking two different languages and the data received will be garbage. Start Bits and Stop Bits In asynchronous communication, at least two extra bits are transmitted with the data word; a start bit and a stop bit. ‘Therefore, if the transmitter is using an 8-bit system, the actual number of bits transmitted per word is ten. In most protocols the start bit is a logic 0 while the stop bit is logic 1. Therefore, when no data is being sent the data line is continuously HIGH. The receiver waits for a1 to transition. In other words, it awaits a transition from the stop bit (no data) to the start bit (logic 0). Once this transition occurs the Teceiver knows a data byte will follow. Since it knows the data rate (because it is defined in the \SY by the transmitto, Protocol) it uses the same clock as frequency as that used by ang ample, ifthe protocol qn", gg _ u correct number of bits and stores them ina Meera Sa, ihe next eight tem) O5— WU iO ht ther se ee is bit eater the end of the data, If the next Re pea 3 ice eo ~ erty wilh th reriattaloniend the receiver dumpe Pn a receiver waits for the next data word, ie, it waits for a Q18. Explain the 8051 serial port, 2.14. Wh: Ans, The 8051 Serial Port: The 8051 includes $7 90) an onchip sevial port that can be programmed peas Toga 7. ati tooperate in one of four different modes and at a (wtito-only) ew Ada range of frequencies. In serial communication the et. They asta rate is known as the baud rate, which simply rogram means the number of bits transmitted per second, {In the serial port modes that allow variable baud Fates, this baud rate is set by timer 1. The 8051 serial port is full duplex. In other words, it can transmit and receive data at the ‘Stored in the read-only register. There are two separate data lines, one for transmission (TXD) and one for reception (RXD). Therefore, the serial port can be transmitting data down the TXD line while it is at the Same time receiving data onthe RXD line. The TXD line is pin 11 of the microcontroller (P3.1) while the RY MOV This i Fad oan 10(P3.0). Therefore, external access ecete Be vale to the seria! Port is achieved by, connecting to these ‘ast ~~ Pins. For example, if you wanted lo connect a keyboard eget 7 ‘play to the Serial port yivectly - This is detailed in the dias MOV below. This he serial port is to chaiit in the ved serial data into parvisn't ine RAM. It * Serial transmission ig changing parallel data to serial data, whateve * Serial reception is changing seviel data into parallel data Indix * Both are achieved through the use of shi registers, pea As discussed earlier, synchronous communication requives the clock signal to be sent al’ ee with the data while asynchronous communication requires the use of stop bits and start bi MO\ However, the programmer wishing to use the 8051 need not worry about such things, To trans data along the serial line you simply write to the sevial by p uuffer and to access data received on! serial port you simply read data from the Serial buffer, For example: