Nios 2.

1 CPU

April 2002, Version 1.1 Data Sheet

Introduction The 2.1 version of the Nios® CPU is a pipelined general-purpose RISC
microprocessor. Nios supports both 32-bit and 16-bit architectural
variants and both 16 and 32-bit variants use 16-bit instructions. The
principal features of the Nios instruction set architecture are:

■ Large, windowed register file — Nios implementations can include up

to 512 internal general-purpose registers. The compiler uses the
internal registers to accelerate subroutine calls and local variable
access.

■ Simple, complete instruction set — Both 32-bit and 16-bit Nios variants
use 16-bit-wide instructions. 16-bit instructions reduce code footprint
and instruction-memory bandwidth.

■ Powerful addressing modes — The Nios instruction set includes Load

and Store instructions that the compiler uses to accelerate structure
access and local-variable (stack) access.

■ Extensibility — Users can incorporate custom logic directly into the

Nios arithmetic logic unit (ALU). The automatically-generated
software development kit (SDK) includes macros for accessing
custom instruction hardware for C and assembly-language
programs.

f See the Nios 16-Bit Programmer’s Reference Manual and the Nios 32-Bit
Programmer’s Reference Manual for an extensive discussion of the Nios 32-
bit and 16-bit instruction set architecture. The latest revisions of all Nios
documentation are at http://www.altera.com/literature/lit-nio.html.

Nios 2.1 The Nios version 2.1 implementation is a five-stage pipeline with separate
instruction and data-memory masters (Harvard memory architecture).
Implementation Both instruction and data-memory control ports are implemented as
Details Avalon™ bus masters. Using the SOPC Builder system design tool, you
can specify connections between both Nios bus masters and any Avalon
slaves in your system such as memory and peripherals. The SOPC Builder
automatically inserts arbiters as required.

f See the Avalon Bus Specification Reference Manual for bus master and
avalon-slave signal and timing details.

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DS-NIOSCPU-1.1
Nios 2.1 CPU Data Sheet

Instruction Bus-Master
The Nios instruction master is a 16-bit wide, latency-aware Avalon bus
master. This master is only used to fetch instructions from memory that
will be executed by the Nios CPU. This master never performs any write
operations. Because this master is latency-aware, it can perform posted-
read operations to latent memory devices. The instruction master issues
new read requests before data is returned by the bus. Nios uses a branch-
not-taken prediction scheme to issue speculative addresses. Native
support for latency minimizes the impact of latent memory and increases
the overall fMax of the system as a whole. Penalties occur only for mis-
predicted branches.

The Avalon bus generated by SOPC Builder automatically includes

dynamic bus-sizing logic. Consequently, the Nios instruction master can
be connected to 8- 16- and 32-bit-wide memory.

f See the Avalon Bus Specification Reference Manual for bus master and
avalon-slave signal and timing details.

Data Bus-Master
The Nios data master is 32 bits wide for 32-bit architecture variants and
16-bits wide for 16-bit architecture variants. The data master is used for
three purposes:

1. To fetch data from memory when the CPU executes a load-

instruction (LD, LDP, LDS).

2. To write data to memory when the CPU executes a store-instruction

(ST, STP, STS, ST8s, ST8d, ST16s, ST16d, STS8s, STS16s).

3. To fetch interrupt-vectors from the interrupt-vector table when the

CPU executes a TRAP instruction or processes an internal or external
exception.

Because it is not meaningful to predict data addresses or continue

execution before data is retrieved, the Nios data master does not support
latency. Consequently, slave latency is seen by the data master as wait-
states. When the Nios data master is connected to zero-wait-state
memory, load and store operations can be completed in a single clock-
cycle.

1 This assumes there is no arbitration conflicts with other masters,

including the CPU’s own instruction-master.

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 Nios 2.1 CPU Data Sheet

For highest performance, the data master should be assigned higher

arbitration priority on any slave that is shared by both instruction and
data masters.

Shift Unit
Previous Nios architecture implementations (version 1.1.1 or earlier)
allowed user-configuration of the internal shift-unit. Nios now uses fixed
(non-configurable) barrel-shifter logic that executes all shift instructions
(ASR, ASRI, ASL, ASLI, LSL, LSLI, RLC and RRC) in two clock cycles,
regardless of the shift-distance.

Multiply Support
Nios supports three different options for implementing integer
multiplication operations from software:

1. The MUL Instruction – A 32-bit Nios CPU can optionally be

configured to include a hardware 16x16 –> 32 integer multiplier. This
hardware is used by the MUL instruction to compute a 32-bit result
in three clock cycles. When the MUL option is selected, it will make
use of the C-runtime libraries in the automatically-generated SDK.
This option is not supported in the 16-bit Nios instruction set.

When using the MUL option with Altera® StratixTM devices, the
hardware multiplier uses the DSP blocks for implementation.

2. The MSTEP Instruction – A 32-bit Nios CPU can optionally be

configured to include hardware for executing one step of a 16x16
multiply. This hardware is used by the MSTEP instruction to
produce a partial multiplication result in two clocks. When the
MSTEP option is selected, the C-runtime libraries in the
automatically-generated SDK implements multiplication operations.
It does this by issuing strings of successive MSTEP operations such
as 16-sequential MSTEPs to perform a 16x16 –> 32 multiplication.
The amount of logic resources needed to implement MSTEP is less
than 5% of the total CPU logic. Since the amount is so small, the
MSTEP option is the default.

1 This option is not supported in the 16-bit Nios instruction set.

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Nios 2.1 CPU Data Sheet

3. Software Multiplication – The C-runtime libraries in the automatically

generated SDK implement integer multiplication with sequences of
shift and add instructions when neither MSTEP nor MUL options are
enabled. Software multiplication gives the smallest possible CPU
logic utilization, but the slowest execution of multiplication
operations.

Interrupt Support
Version 2.1 of Nios allows optional removal of support for TRAP
instructions, hardware interrupts, and internal exceptions. This option is
intended for use only in Nios systems where the processor is
implementing a very simple control function (that is, not running complex
software). When so configured, the Nios will not:

■ include an irq input-pin

■ process undefined behavior for TRAP instructions
■ generate exceptions when a SAVE or RESTORE instruction
underflows/overflows the register file

Select this option only if:

■ You want the smallest possible Nios CPU core.

■ You know absolutely that your application software does not
generate register-window underflow/overflow exceptions. That is,
the subroutine call-depth is less than the number of available register-
windows.
■ You do not have any hardware interrupt sources.
■ Your assembly-language code does not include TRAP instructions.

1 The Nios SDK does not generate TRAP instructions in compiled

code. By default, interrupt support is enabled. TRAPs,
interrupts, and exceptions work exactly as described in the Nios
16-Bit Programmer’s Reference Manual and the Nios 32-Bit
Programmer’s Reference Manual.

PTF Nios 2.1 CPU configuration options are determined by assignments in

your system PTF file. Each Nios CPU will have a corresponding MODULE
Assignments section in your system PTF containing the assignment:

class = “altera_nios”;

Table 1 lists the CPU’s PTF assignments followed by a detailed

description. These assignments are found in the
MODULE/WIZARD_SCRIPT_ARGUMENTS section unless otherwise
noted and are used by the Nios generator-program to control HDL and
SDK generation.

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 Nios 2.1 CPU Data Sheet

Table 1. CPU PTF Assignments

Assignment Type Allowed Values Default Requires

CPU_Architecture String nios_32, nios_16 nios_32
mstep Boolean 1, 0 1
multiply Boolean 1, 0 0
rom_decoder Boolean 1, 0 1
wvalid_wr Boolean 1, 0 0
num_regs Integer 128, 256, 512 256
include_debug Boolean 1, 0 0
include_trace Boolean 1, 0 0 include_debug=1
reset_slave String (module/slave slash-delimited (“/”) path to None -
section path name) slave section (must be
specified)
reset_offset hexadecimal integer any hexidecimal integer in None -
(byte-offset) the range 0-0xFFFFFFFF (must be
specified)
vecbase_slave String slash-delimited (“/”) path to None -
(module/slave slave section (must be
section path name) specified)
vecbase_offset hexadecimal integer any hexidecimal integer in None -
(byte-offset) the range 0-0xFFFFFFFF (must be
specified)
support_interrupts Boolean 1, 0 1
implement_forward_b1 Boolean 1, 0 1
support_rlc_rcc Boolean 1, 0 0
germs_monitor_id String (10 Any ASCII string, max 10 “” (empty
characters or fewer) characters string)
mainmem_slave String (module/slave slash-delimited (“/”) path to None -
section path name) slave section (must be
specified)
datamem_slave String (module/slave slash-delimited (“/”) path to None -
section path name) slave section (must be
specified)
maincomm_slave String (module/slave slash-delimited (“/”) path to None -
section path name) slave section (must be
specified)
debugcomm_slave String (module/slave slash-delimited (“/”) path to None -
section path name) slave section (must be
specified)

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Nios 2.1 CPU Data Sheet

CPU Architecture Assignment

This assignment selects which architecture variant will be generated.
When CPU_Architecture is nios_16, logic will be generated that
implements the 16-bit instruction set architecture (16-bit-wide registers,
ALU, and data bus-master), as described in the Nios 16-Bit Programmer’s
Reference Manual. Also, the Data_Width assignment in the MASTER data
master/SYSTEM_BUILDER_INFO section must be set to 16.

When CPU_Architecture is nios_32, logic will be generated that

implements the 32-bit instruction set architecture (32-bit-wide registers,
ALU, and data bus-master), as described in the Nios 32-Bit Programmer’s
Reference Manual. Also, the Data_Width assignment in the MASTER data
master/SYSTEM_BUILDER_INFO section must be set to 32.

In either case, the SDK associated with this CPU will be generated with the
correct libraries and default compiler options necessary to create software
for the selected architecture variant.

MSTEP Assignment
This assignment may be set to 1 only for 32-bit Nios cores. When mstep =
1, the generated Nios CPU includes hardware that implements the MSTEP
instruction. The generated SDK makes use of MSTEP in the C-runtime
libraries. When mstep = 0, the MSTEP instruction is not implemented,
and the C-runtime libraries will not use it.

MULTIPLY Assignment
This assignment may be set to 1 only for 32-bit Nios cores. When
multiply = 1, the generated Nios CPU includes hardware that
implements the MUL instruction, and the generated SDK makes use of
MUL in the C-runtime libraries. When multiply = 0, the MUL
instruction is not implemented, and the C-runtime libraries will not use it.
Issuing the MUL instruction when multiply = 0 produces an undefined
result.

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 Nios 2.1 CPU Data Sheet

rom_decoder Assignment
The Nios CPU includes internal instruction-decode logic that takes the
incoming 16-bit instruction word as input and produces approximately 80
control signals that determine the operation performed by the data path
logic. A significant portion of the instruction-decoder logic can be
implemented either as logic elements (LEs) or as an internal ROM memory
using a single embedded-system block (ESB) in APEX™-family devices.
When rom_decoder = 1, a single ESB (APEX) is used in the instruction-
decode logic, saving approximately 52-58 LEs. The exact savings depends
on which other CPU options have been selected. When rom_decoder =
0, no memory resources are used in the instruction decoder, reducing the
CPU’s ESB-utilization by exactly one.

wvalid_wr Assignment
Control-register number 2 (%ctl2) is the WVALID register. Software can
always read this register to determine the limits of travel on current
window pointer (CWP). WVALID determines when underflow and
overflow exceptions are generated. A detailed description of the WVALID
register appears in the Nios 32-Bit Programmer’s Reference Manual and Nios
16-Bit Programmer’s Reference Manual. Regardless of the setting of
wvalid_wr, the WVALID register is initialized at reset so that the entire
windowed register file is available to software (LO_LIMIT = 1 and
HI_LIMIT = <number-of-registers> - 2). The vast majority of compiled
programs never need to alter the initially-set WVALID value.

The default CWP-manager library included in the automatically-

generated SDK never writes the WVALID register. When the PTF-
parameter wvalid_wr = 0, the WVALID register is not writable. A
WRCTL instruction with %ctrl2 as the destination has no effect. By
implementing WVALID read-only, the total logic utilization of the CPU is
reduced by approximately 15 LEs. Also, WVALID is protected from
accidental modification by errant software.

When wvalid_wr = 1, WVALID is implemented as a readable and

writable register. Software can modify WVALID by performing a WRCTL
instruction with %ctrl2 as the destination. Some real-time operating
system (RTOS) software may modify WVALID in order to, for example,
partition the register file into kernel and user segments. Such RTOS
software will require a writable WVALID register (wvalid_wr = 1) in
order to run correctly.

1 Check the manufacturer’s documentation for your RTOS

software to determine its CPU hardware requirements.

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Nios 2.1 CPU Data Sheet

num_regs Assignment
This assignment value determines the total number of registers
implemented in the CPU’s windowed-register file. Larger register files
use more on-chip memory resources. Larger register files allow deeper
subroutine-nesting before a register-window underflow exception is
generated. With 128 registers, software can call subroutines 7-levels deep
before an underflow exception is generated. With 512 registers, software
can call subroutines 31-levels deep before an underflow exception is
generated. Software that frequently generates underflow/overflow
exceptions may experience significant performance degradation. In
practice, even complicated software can live comfortably in 512 registers
although recursive algorithms can cause even simple software to execute
very deep-subroutine nesting. The best setting for num_regs depends on
the complexity and performance requirements of the application software
and the amount of on-chip memory resources available.

include_debug Assignment
The Nios 2.1 CPU includes an optional internal-debug core. This core,
when used with appropriate software (included GDB-stub), allows
hardware breakpoints to be set on various types of memory-access
including both data and instruction accesses to ranges of memories.
Breakpoints can be further qualified to trigger only when certain data
values are detected for read or write (LD/ST) operations.

f For more detailed instructions on using the internal debug core to set
breakpoints, See the Nios Software Development Reference Manual.

The debug core can be implemented either with or without support for an
external trace-capture buffer. See “include_trace Assignment” on page 9.
When include_debug = 1, the CPU will use considerably more logic
resources.

1 The size of the internal debug core is a significant fraction of the

total CPU size.

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 Nios 2.1 CPU Data Sheet

include_trace Assignment
The Nios internal debug core can be implemented with (include_trace
= 1) or without (include_trace = 0) support for an off-chip SSRAM
trace memory buffer. When include_trace = 1, the Nios CPU core will
grow an additional dedicated set of pins which can be connected directly
to a trace memory board, available from 3rd-party partners. Software and
libraries included in the Nios Development Kit allow limited capture and
display facilities for trace data gathered by the internal debug core into an
external buffer. Third-party software is available for controlling trace
capture, disassembly, and display from within an integrated development
environment (IDE).

f Visit the Altera® web site, http://www.altera.com/nios, for details about

all available Nios third-party hardware and software debugging tools. See
the Nios Software Development Reference Manual for debug information.

reset_slave Assignment
The Nios CPU logic is generated with a built-in reset address. The value
of the reset address is derived from two PTF assignments: reset_slave
and reset_offset. The reset_slave assignment is used to extract a
base-address from the slave port of the specified slave-port on the
specified module. The reset_offset assignment specifies a byte-offset
that is applied to the indicated devices’s base-address.

<reset-address> = base-address-of-reset_slave + reset_offset;

After system reset is asserted and released, the CPU will fetch its first
instruction from the computed reset-address. For example, consider a
system with a Nios CPU and an on-chip memory module named
boot_rom mapped at base-address 0x400. In this example, suppose the
on-chip memory module has a single slave-port named s1. Suppose that
this memory contains the CPU’s startup program based at the beginning
of the memory.

To construct a CPU which executes this startup program at reset, that is

with a reset-address of 0x400, set the following PTF-assignments:

reset_slave = “boot_rom/s1”;

reset_offset = “0x0”;

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Nios 2.1 CPU Data Sheet

reset_offset Assignment
See “reset_slave Assignment” on page 9 for reset_offset assignment
information.

vecbase_slave Assignment
The Nios CPU logic is generated with a built-in vector-table base address.
The vector-table address is derived from two PTF assignments:
vecbase_slave and vecbase_offset. The vecbase_slave
assignment is used to extract a base address from the slave port of the
specified slave port on the specified module. The vebase_offset
assignment specifies a byte offset which is applied to the indicated
devices’s base address.

<vector-table-base-address> = base-address-of-vecbase_slave + vecbase_offset;

Whenever an exception is processed due to external hardware interrupt,

internal exception, or execution of a TRAP instruction, the CPU fetches
exception-handler addresses from the vector table at this computed
address. For example, consider a system with a Nios CPU and a 4K
memory module named general_purpose_ram mapped at base
address 0x1000. In this example, suppose the on-chip memory module has
a single slave port named s1. Suppose the highest 256 bytes, the size of the
vector-table for 32-bit Nios CPU, is used as the vector table. To construct
a CPU that uses the memory region starting at 0x1F00 as its vector table,
set the following PTF assignments:

vecbase_slave = “general_purpose_ram/s1”;

vecbase_offset = “0xF00”;

f The Nios 16-Bit Programmer’s Reference Manual and Nios 32-Bit

Programmer’s Reference Manual contains a detailed description of the
exception-handling process.

vecbase_offset Assignment
See “vecbase_slave Assignment” on page 10.

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 Nios 2.1 CPU Data Sheet

support_interrupts Assignment
When the assignment support_interrupts = 0, the Nios CPU will
have neither irq nor irqnumber input signals on its Avalon bus master
interface and therefore cannot receive hardware interrupts. The CPU will
not generate internal exceptions for register-window underflows and
overflows. The results of executing a TRAP instruction is undefined.

In short, the CPU does not support interrupts, exceptions, or TRAP

instructions. See “Interrupt Support” on page 4 for a description of when
systems may use a CPU with no interrupt support.

When support_interrupts = 1, the Nios CPU will support interrupts,

exceptions, and traps exactly as described in the Nios 32-Bit Programmer’s
Reference Manual and Nios 16-Bit Programmer’s Reference Manual.

1 The default setting is shown in Table 1.

implement_forward_b1
This assignment controls the CPU’s handling of certain types of pipeline-
data hazards. The CPU always hides all pipeline implementation details
from software, and behaves exactly as indicated in the Nios 32-Bit
Programmers’ Reference Manual and 16-Bit Programmer’s Reference Manual
regardless of this setting.

When implement_forward_b1 = 1, the CPU will include a data-

forwarding multiplexer on the B input of the ALU. This allows the CPU to
process an instruction stream where the B operand of an instruction is
modified by the previous instruction without introducing a stall cycle in
between. This reduces the number pipeline stalls at the expense of some
additional logic (~32 LEs) and a potential reduction in fMax.

Most compiled code does not encounter this class of data hazard very
often. Performance on the Dhrystone benchmark (at a fixed clock
frequency) is improved by about three percent when
implement_forward_b1 = 1. When implement_forward_b1 = 0, the
CPU will stall for one clock-cycle when the b operand of an instruction
was modified by its immediate predecessor.

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Nios 2.1 CPU Data Sheet

support_rlc_rrc Assignment
These instructions rotate a register right or left (respectively) by one bit
through the carry flag. These instructions are never used by the compiler.
Support for these instructions requires some dedicated logic (between 12-
21) that can usually be saved. When assignment support_rlc_rrc = 0,
the CPU does not support these instructions, and the behavior of both
RRC and RLC instructions is undefined. When assignment
support_rlc_rrc = 1, the CPU supports RLC and RRC instructions.
Use this setting if you have written any assembly-language software that
explicitly uses these instructions.

f See the complete Nios instruction set including the RRC and RLC
instructions in the Nios 32-Bit Programmer’s Reference Manual and Nios 16-
Bit Programmer’s Reference Manual.

germs_monitor_id Assignment
The Nios CPU is generated along with a custom SDK including libraries,
example programs, and utilities. One of the several programs generated
as part of the Nios SDK is a customized GERMS monitor (boot-monitor
program). The GERMS monitor prints a message at start up. The contents
of this message are taken from the CPU’s germs_monitor_id
assignment. It is often useful to set different id messages to display
different hardware revision levels of your system.

mainmem_slave Assignment
The Nios CPU is generated along with a custom SDK including libraries,
example programs, and utilities. C programs are, by default, compiled to
reside at a base address within the system’s designated main-memory
device. This PTF assignment is used to designate the memory device
where, by default, compiled programs will be located. The generated SDK
is aware of the vector table, and will set the base address of compiled
programs to avoid the vector-table if, for example, the vector table is
mapped at the beginning of the designated main memory device.

datamem_slave Assignment
The Nios CPU is generated along with a custom SDK including libraries,
example programs, and utilities. C programs are, by default, compiled
with their stack, heap (malloc data) and writable global variables within
the system’s designated data-memory device. This PTF assignment is
used to designate the memory device where, by default, compiled
programs’ writable data will be located. The generated SDK is aware of
the vector table, and will locate the stack and heap to avoid conflicts.

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 Nios 2.1 CPU Data Sheet

maincomm_slave Assignment
The Nios CPU is generated along with a custom SDK including libraries,
example programs, and utilities. Some libraries and utilities implicitly
make use of a standard output or console device, for example, the printf
library. The SDK uses a designated Avalon UART peripheral as the
default I/O device for many text input-output functions. The PTF
assignment maincomm_slave designates which UART is used by the
generated SDK for default text I/O.

1 The designated device must be an Avalon UART.

debugcomm_slave Assignment
The Nios CPU is generated along with a custom SDK including libraries,
example programs, and utilities. One such utility is a resident GDB stub
which communicates with host debugging software over a designated
serial device (Avalon UART). The PTF assignment debugcomm_slave
designates which Avalon UART is used by the debug stub. It can be the
same UART as the maincomm_slave, but it is generally easier to debug
systems with separate debugcomm_slave and maincomm_slave
UARTs.

1 The designated device must be an Avalon UART.

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Nios 2.1 CPU Data Sheet

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