Geethanjali College of Engineering and Technology

Department of Electronics and Communication Engineering

Microprocessors and Microcontrollers Objective Question Bank

Unit – I: 8086 Microprocessors

1. 8086 Microprocessor supports _______ modes of operation.
A. 2
B. 3
C. 4
D. 5

2. Which of the following is not a feature of 8086?

A. It uses two stages of pipelining

B. It is available in 3 versions based on the frequency of operation
C. Fetch stage can prefetch up to 6 bytes of instructions
D. It has 512 vectored interrupts.

3. 8086 can access up to

A. 512 KB
B. 1 MB
C. 2 MB
D. 256 KB
4. 8086 has ___ address bus.

A. 16-bit
B. 18-bit
C. 20-bit
D. 24-bit
5. Which flag is set to 1 when the result of arithmetic or logical operation is zero else it
is set to 0?

A. Binary bit
B. Zero flag
C. Sign flag
D. Overflow flag
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Department of Electronics and Communication Engineering
Microprocessors and Microcontrollers Objective Question Bank
6. Which flag represents the result when the system capacity is exceeded?

A. Carry flag
B. Auxiliary flag
C. Trap flag
D. Overflow flag
7. ___ is an edge triggered input, which causes an interrupt request to the
microprocessor.

A. NMI
B. INTR
C. INTA
D. ALE

8. ________ signal is used to write the data into the memory or the output device
depending on the status of M/IO signal.

A. IR
B. HLDA
C. HR
D. WR

9. ________ signal is used to read the data into the memory or the output device
depending on the status of M/IO signal.

A. RD
B. HLDA
C. INTR
D. WR

10. A microprocessor is a chip integrating _____ functions of a CPU of a computer.

A. multiple
B. single
C. double
D. triple
 Geethanjali College of Engineering and Technology
Department of Electronics and Communication Engineering
Microprocessors and Microcontrollers Objective Question Bank
11. The microprocessor can read/write 16 bit data from or to
A. memory
B. I /O device
C. processor
D. register
12. The intel 8086 microprocessor is a ____ processor
A. 8 bit
B. 16 bit
C. 32 bit
D. 4 bit
13. In 8086 microprocessor, the data bus is _____ bit wide
A. 12 bit
B. 10 bit
C. 16 bit
D. 20 bit
14. The work of EU is
A. encoding
B. decoding
C. processing
D. Calculations

15. The 16 bit status flag of 8086 microprocessor is responsible to indicate

A. the condition of result of ALU operation
B. the condition of memory
C. the result of addition
D. the result of subtraction

16. The CF is known as

A. carry flag
B. condition flag
C. common flag
D. single flag
17. The SF is called as
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Microprocessors and Microcontrollers Objective Question Bank
A. service flag
B. sign flag
C. single flag
D. condition flag

18. The register AX is formed by grouping

A. AH & AL
B. BH & BL
C. CH & CL
D. DH & DL

19. The Stack is indicated by

A. single pointer
B. stack pointer
C. source pointer
D. destination pointer

20. The index register are used to hold

A. memory register
B. offset address
C. segment memory
D. offset memory
21. The BIU contains FIFO register of____ bytes
A. 8
B. 12
C. 4
D. 6
22. The BIU prefetches the instruction from memory and store them in
A. queue
B. register
C. memory
D. stack

23. The 1 MB of memory can be divided into segments of ___ size.

 Geethanjali College of Engineering and Technology
Department of Electronics and Communication Engineering
Microprocessors and Microcontrollers Objective Question Bank
A. 1 Kbyte
B. 64 Kbyte
C. 33 Kbyte
D. 34 Kbyte

24. The 1 MB of memory can be divided into _______ segments

A. 4
B. 8
C. 16
D. 32

25. The 16 bit flag register of 8086 microprocessor is responsible to indicate

A. the condition of result of ALU operation
B. the condition of memory
C. the result of addition
D. the result of subtraction

1. A 2. D 3. B 4. C 5. C 6. D 7. B 8. D 9. A
10.A 11. A 12. B 13. C 14. B 15. A 16. A 17. B 18. A
19. B 20. B 21.D 22. A 23. B 24. C 25. A
 Geethanjali College of Engineering and Technology
Department of Electronics and Communication Engineering
Microprocessors and Microcontrollers Objective Question Bank

Unit – II: Instruction set and assembly language programming of 8086

1. The result of MOV AL, 65 will be stored as

A. store 0110 0101 in AL
B. store 42H in AL
C. store 40H in AL
D. store 0100 0001 in AL
2. The instruction, MOV AX, 0005H belongs to the address mode
A. register relative
B. Direct
C. Immediate
D. register
3. The instruction, MOV AX, [BX] is an example of
A. register indirect addressing mode
B. direct addressing mode
C. immediate addressing mode
D. based indexed addressing mode
4. The instruction, MOV AX, [2500H] is an example of
A. immediate addressing mode
B. direct addressing mode
C. indirect addressing mode
D. register addressing mode
5. The instruction, MOV AX, BX is an example of
A. immediate addressing mode
B. direct addressing mode
C. indirect addressing mode
D. register addressing mode

6. If the data is present in a register and it is referred using the particular register, then it is
A. direct addressing mode
B. register addressing mode
C. indexed addressing mode
D. immediate addressing mode
 Geethanjali College of Engineering and Technology
Department of Electronics and Communication Engineering
Microprocessors and Microcontrollers Objective Question Bank

7. The instruction, MOV AX,50H[BX] is an example of

A. direct addressing mode
B. register addressing mode
C. register relative addressing mode
D. register indirect addressing mode
8. The addressing mode that is used in unconditional branch instructions is
A. intrasegment direct addressing mode
B. intrasegment indirect addressing mode
C. intrasegment direct and indirect addressing mode
D. intersegment direct addressing mode

9. The instruction, “INC” increases the contents of the specified register or memory location by
A. 2
B. 0
C. 1
D. 3

10. The instruction that subtracts 1 from the contents of the specified register/memory location
is
A. INC
B. SUBB
C. SUB
D. DEC

11. The flag that acts as Borrow flag in the instruction, SBB is
A. direction flag
B. carry flag
C. parity flag
D. trap flag
12. The instruction, CMP to compare source and destination operands, it performs
A. addition
B. subtraction
C. division
 Geethanjali College of Engineering and Technology
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Microprocessors and Microcontrollers Objective Question Bank
D. multiplication

13. Which of the following is a mnemonic?

A. ADD
B. ADC
C. AAA
D. ADD & ADC
14. The expansion of DAA is
A. decimal adjust after addition
B. decimal adjust before addition
C. decimal adjust accumulator
D. decimal adjust auxiliary

15. The ROR instruction rotates the contents of the destination operand to
A. left
B. right
C. left and then right
D. right and then left

16. The instruction that performs logical AND operation and the result of the operation is not
available is
A. AAA
B. AND
C. TEST
D. XOR

17. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX
register becomes zero is
A. SCAS
B. REP
C. CMPS
D. STOS

18. The instructions that are used to call a subroutine from the main program and return to the
main program after execution of called function are
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A. CALL, JMP
B. JMP, IRET
C. CALL, RET
D. JMP, RET

19. Which of the following is not a machine controlled instruction?

A. HLT
B. CLC
C. LOCK
D. ESC
20. NOP instruction introduces
A. Address
B. Delay
C. Memory location
D. None of the mentioned

21. The directive used to inform the assembler, the names of the logical segments to be assumed
for different segments used in the program is
A. ASSUME
B. SEGMENT
C. SHORT
D. DB

22. The directive that updates the location counter to the next even address while executing a
series of instructions is
A. ODD
B. EVEN
C. DB
D. EQU

23. The labels or constants that can be used by any module in the program is possible when they
are declared as
A. PUBLIC
B. LOCAL
 Geethanjali College of Engineering and Technology
Department of Electronics and Communication Engineering
Microprocessors and Microcontrollers Objective Question Bank
C. GLOBAL
D. Either PUBLIC or GLOBAL
24. The directive that directs the assembler to start the memory allotment for a particular
segment/block/code from the declared address is
A. OFFSET
B. LABEL
C. ORG
D. GROUP

25. The directive that defines word data is

A. DQ
B. DT
C. DB
D. DW

Answer Key:
1. D 2. C 3. A 4. B 5. D
6.B 7. C 8. B 9.A 10. C
11. B 12.B 13. C 14.A 15.B
16.C 17. B 18. C 19. B 20. B
21. A 22. B 23. A 24. C 25. D

Unit – III: I/O Interface/Interrupts/serial communication

1. The ______ is a general purpose programmable I/O device designed to transfer the
data from I/O to interrupt I/O.
 Geethanjali College of Engineering and Technology
Department of Electronics and Communication Engineering
Microprocessors and Microcontrollers Objective Question Bank

A. 8285A
B. 8241A
C. 8255A
D. 8251A
2. How many ports 8255A has?
A. 2
B. 3
C. 4
D. 5
3. Which port can be split into two parts?
A. PORT A
B. PORT B
C. PORT C
D. PORT D
4. All the functions of the ports of 8255 are achieved by programming the bits of an
internal register called
A. data bus control
B. read logic control
C. control word register
D. mode register
5. The data bus buffer is controlled by
A. control word register
B. read/write control logic
C. data bus
D. Address bus
6. The port that is used for the generation of handshake lines in mode 1 or mode 2 is
A. port A
B. port B
C. port C Lower
D. port C Upper
7. If A1=0, A0=1 then the input read cycle is performed from

A. port A to data bus

B. port B to data bus
C. port C to data bus
D. CWR to data bus
 Geethanjali College of Engineering and Technology
Department of Electronics and Communication Engineering
Microprocessors and Microcontrollers Objective Question Bank
8. The pin that clears the control word register of 8255 when enabled is
A. CLEAR
B. SET
C. RESET
D. CLK
9. In which mode do all the Ports of the 8255 PPI work as Input-Output units for data
transfer?
A.BSR mode
B. Mode 0 of I/O mode
C. Mode 1 of I/O mode
D.Mode 2 of I/O mode
10. In which of the following modes we do not consider the D6, D5 and D4 bits of the
control word?
A. BSR mode
B. Mode 0 of I/O mode
C. Mode 1 of I/O mode
D.Mode 2 of I/O mode

11. In ADC 0808 if _______ pin is high, it enables output.

A. EOC
B. I/P0-I/P7
C. SOC
D. OE
12. Which of the following is not a mode of data transmission?
A. simplex
B. duplex
C. semi duplex
D. half duplex
13. If the data is transmitted only in one direction over a single communication channel,
then it is of

A. simplex mode
B. duplex mode
C. semi duplex mode
D. half duplex mode
14. In 8251A, the pin that controls the rate at which the character is to be transmitted, is
A. TXC(active low)
 Geethanjali College of Engineering and Technology
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Microprocessors and Microcontrollers Objective Question Bank
B. TXC(active high)
C. TXD(active low)
D. RXC(active low)
15. The signal that may be used either to interrupt the CPU or polled by the CPU is
A. TXRDY(Transmitter ready)
B. RXRDY (Receiver ready output)
C. DSR(active low)
D. DTR(active low)
16. The time taken by the ADC from the active edge of SOC pulse till the active edge of
EOC signal is called:
A. Conversion over
B. Conversion delay
C. Conversion signal
D. Conversion error
17. 8251 contains _______bits control word register.
A. 8
B.16
C.24
D.32
18. ____________register must be initialized before any use of 8251.
A. Command word
B. Control word
C. Mode word
D. Format word
19. If the character length of L1 and L2 is 0 and 1 the number of bits is _____________
A.5
B.6
C.7
D.8

20. Parity error in status instruction format is set when

A. OE is set to 1
B. FE is set to 1
C. PE is set to 1
D. PE is set to 01.
21. 8086 consists of _____________ number of hardware interrupts
A. 2
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B. 3
C. 4
D. 5
22. 8086 supports ___________ number of software interrupts
A. 2
B. 32
C. 225
D. 256
23. Address of Interrupt Service Routine is stored in _______ registers
A. CS:IP
B. CS:BX
C. DS:IP
D. DS:BX
24. _________ is an example of dedicated interrupts
A. NMI
B. INT36
C. TRAP
D. RESET
25. Full form of ISR is
A. Interrupt service return
B. Interrupt Service Routine
C. Interrupt Service Procedure
D. Interrupt source return

Answer Key:
1. C 2. B 3. C 4. C 5. B
6. D 7. D 8. A 9. B 10. A
11. D 12. C 13. A 14. A 15. B
16. B 17. A 18. A 19. A 20. C
21. A 22. D 23. A 24. A 25. B

Unit – IV: Microcontrollers

1. Which operations are performed by the bit manipulating instructions of boolean
processor?
A. Complement bit
B. Addition of bit
C. Shifting of bit
D. Comparision of bits
 Geethanjali College of Engineering and Technology
Department of Electronics and Communication Engineering
Microprocessors and Microcontrollers Objective Question Bank

2. Which data memory control and handle the operation of several peripherals by
assigning them in the category of special function registers?
A. Internal on-chip RAM
B. External off-chip RAM
C. External RAM
D. Flash memory

3. Why is the speed accessibility of external data memory slower than internal on-chip
RAM?
A. Due to multiplexing of lower order byte of address-data bus
B. Due to multiplexing of higher order byte of address-data bus
C. Due to demultiplexing of lower order byte of address-data bus
D. Due to demultiplexing of higher order byte of address-data bus

4. Which register usually store the output generated by ALU in several arithmetic and
logical operations?
A. Accumulator
B. Special Function Register
C. Timer Register
D. Stack Pointer

5. AT89C2051 has RAM of:

A. 128 bytes
B. 256 bytes
C. 64 bytes
D. 512 bytes

6. 8051 series has how many 16 bit registers?

A. 2
B. 3
C. 1
D. 0
7. When 8051 wakes up then 0x00 is loaded to which register?
A. PSW
B. SP
C. PC
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Microprocessors and Microcontrollers Objective Question Bank
D. SFR
8. When the microcontroller executes some arithmetic operations, then the flag bits of
which register are affected?
A. PSW
B. SP
C. DPTR
D. PC
9. How are the status of the carry, auxiliary carry and parity flag affected if the write
instruction
MOV A,#9C
ADD A,#64H
A. CY=0,AC=0,P=0
B. CY=1,AC=1,P=0
C. CY=0,AC=1,P=0
D. CY=1,AC=1,P=1

10. How are the bits of the register PSW affected if we select Bank2 of 8051?
A. PSW.5=0 and PSW.4=1
B. PSW.2=0 and PSW.3=1
C. PSW.3=1 and PSW.4=1
D. PSW.3=0 and PSW.4=1

11. If we push data onto the stack then the stack pointer
A. increases with every push
B. decreases with every push
C. increases & decreases with every push
D. decreases & increases with every push

12. On power up, the 8051 uses which RAM locations for register R0- R7
A. 00-2F
B. 00-07
C. 00-7F
D. 00-0F

13. How many bytes of bit addressable memory is present in 8051 based
microcontrollers?
A. 8 bytes
B. 32 bytes
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C. 16 bytes
D. 128 bytes

14. It is possible to set the auxiliary carry flag while performing addition or subtraction
operations only when the carry exceeds _______
A. 1st bit
B. 2nd bit
C. 3rd bit
D. 4th bit
15. Which locations of 128 bytes on-chip additional RAM are generally reserved for
special functions?
A. 80H to 0FFH
B. 70H to 0FFH
C. 90H to 0FFH
D. 60H to 0FFH
16. Which commands are used for addressing the off-chip data and associated codes
respectively by data pointer?
A. MOVX & MOVC
B. MOVY & MOVB
C. MOVZ & MOVA
D. MOVC & MOVY
17. Which instruction find its utility in loading the data pointer with 16 bits immediate
data?
A. MOV
B. INC
C. DEC
D. ADDC

18. What is the maximum capability of addressing the off-chip data memory & off-chip
program memory in a data pointer?
A. 8K
B. 16K
C. 32K
D. 64K
19. Which among the below stated registers does not belong to the category of special
function registers?
A. TCON & TMOD
B. TH0 & TL0
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C. P0 & P1
D. SP & PC
20. Where should the pin 19 (XTAL1), acting as an input of inverting amplifier as well as
part of an oscillator circuit, be connected under the application of external clock?
A. to XTAL2
B. to Vcc
C. to GND
D. to ALE
21. What is the required baud rate for an efficient operation of serial port devices in 8051
microcontroller?
A. 1200
B. 2400
C. 4800
D. 9600
22. Which among the below mentioned functions does not belong to the category of
alternate functions usually performed by Port 3 (Pins 10-17)?
A. External Interrupts
B. Internal Interrupts
C. Serial Ports
D. Read / Write Control signals

23. Which output control signal is activated after every six oscillator periods while
fetching the external program memory and almost remains high during internal
program execution?
A. ALE
B. PSEN
C. EA
D. XLAT
24. The upper 128 bytes of an internal data memory from 80H through FFH usually
represent _______.
A. general-purpose registers
B. special function registers
C. stack pointers
D. program counters
25. What is the bit addressing range of addressable individual bits over the on-chip
RAM?
A. 00H to FFH
B. 01H to 7FH
C. 00H to 7FH
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Department of Electronics and Communication Engineering
Microprocessors and Microcontrollers Objective Question Bank
D. 80H to FFH

Answer Key:
1. A 2. A 3.A 4. A 5. A
6. A 7. C 8. D 9. B 10. D
11. A 12. B 13. C 14. C 15. A
16. A 17. A 18.D 19. D 20. C
21. D 22. B 23. B 24. B 25. C

Unit – V: Interrupts/Timers counters/Serial communication

1. What is the divisional range of program memory for internal memory when
enable access pin is held high?
A. 0000H – 0FFFH
B. 0000H – 1000H
C. 0001H – 0FFFH
D. 0001H – 1FFFH

2. What is the divisional range of external memory portion when enable access
pin is held high (unity)?
A. 1000H – FFFFH
B. 0FFFH-FFFFH
C. 01FFH – FFFFH
D. 0001H – 1FFFH
3. Which special function register play a vital role in the timer/counter mode
selection process by allocating the bits in it?
A. TMOD
B. TCON
C. SCON
D. PCON
4. Which bit must be set in TCON register in order to start the ‘Timer 0’ while
operating in ‘Mode 0’?
A. TR0
B. TF0
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C. IT0
D. IE0

5. Which among the following control/s the timer1 especially when it is

configured as a timer in mode’0', where gate and TR1 bits are attributed to be
‘1” in TMOD register?
A. TR1
B. External input at (INT1)
C. TF1
D. External input at (INT0)

6. What is the maximum delay generated by the 12 MHz clock frequency in

accordance to an auto-reload mode (Mode 2) operation of the timer?
A. 125 µs
B. 250 µs
C. 256 µs
D. 1200 µs
7. Which devices are specifically being used for converting serial to parallel and
from parallel to serial respectively?
A. timers
B. counters
C. registers
D. serial communication
8. Which of the following best describes the use of framing in asynchronous
means of communication?
A. it binds the data properly
B. it tells us about the start and stops of the data to be transmitted or
received
C. it is used for error checking
D. it is used for flow control
9. Which of the following signal control the flow of data?
A.RTS
B.DTR
C.DTE
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D.CTS
10. Which of the following is the logic level understood by the micro-
controller/micro-processor?
A. TTLlogiclevel
B. RS232logiclevel
C. TTL & RS232 logic level
D. DTL logic level
11. What is a null modem connection?
A. no data transmission
B. no MAX232
C. the RxD of oneis the TxD for the other
D. no serial communication
12. With what frequency UART operates( where f denoted the crystal
frequency )?
A. f/12
B. f/32
C. f/144
D. f/12 divided by 32

13. What is the function of the SCON register?

A. to control SBUF and SMOD registers
B. to program the start bit, stop bit, and data bits of framing
C. to control SMOD registers
D. none of the mentioned
14. What should be done if we want to double the baud rate?
A. change a bit of the TMOD register
B. change a bit of the PCON register
C. change a bit of the SCON register
D. change a bit of the SBUF register
15. When an interrupt is enabled, then where does the pointer moves
immediately after this interrupt has occurred?
A. to the next instruction which is to be executed
B. to the first instruction of ISR
C. to a fixed location in memory called interrupt vector table
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D. to the end of the program
16. What are the contents of the IE register, when the interrupt of the memory
location 0x00 is caused?
A. 0xFFH
B. 0x00H
C. 0x10H
D. 0xF0H
17. Which pin of the external hardware is said to exhibit INT0 interrupt?
A. pin no 10
B. pin no 11
C. pin no 12
D. pin no 13
18. Which bit of the IE register is used to enable TxD/RxD interrupt?
A. IE.D5
B. IE.D2
C. IE.D3
D. IE.D4
19. Which register is used to make the interrupt level or an edge triggered pulse?
A. TCON
B. IE
C. IPR
D. SCON
20. What is the correct order of priority that is set after a controller gets reset?
A. RI/TI > TF1 > TF0 > INT1 > INT0
B. RI/TI < TF1 < TF0 < INT1 < INT0
C. INT0 > TF0 > INT1 > TF1 > RI/TI
D. INT0 < TF0 < INT1 < TF1 < RI/TI
21. LJMP refers to
A. Local jump
B. Long Jump
C. Last Jump
D. Large Jump
22. If we need to operate a key of a keyboard in an interrupt mode, then it will
generate what kind of interrupt?
A. ES
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B. EX0/EX1
C. T0/T1
D. RESET
23. In TMOD register if c/T’ sets to 1 it acts as ________
A. Clock
B. Timer
C. Counter
D. Reset circuit
24. In SCON register if SM2 is activated then it indicates ________
A. working with single processor
B. disabled processor
C. working with multiprocessor
D. disable multiprocessor
25. In PCON register IDL bit respresents _______
A. reset mode
B. set mode
C. ideal mode
D. serial port
26. In TCON register if TF0 or TF1 bit is set to 1 then _______
A. Underflow occurs
B. Overflow occurs
C. Timer run bit 1
D. Counter bit is 1

Answer Key:
1.A 2. A 3. A 4. A 5. B
6. C 7. C 8. B 9. B 10. A
11. C 12. D 13. B 14. B 15. C
16. B 17. C 18. D 19. A 20. C
21. B 22.B 23. C 24. C 25. C
26. B