INTRODUCTION ADDERS/SUBTRECTURS MUX/DEMUX

ENCODER/DECODER
 • A combinational circuit consists of
Combinational
logic gates
Circuit • It’s outputs at any time are
determined directly from the present
N number of M number of combination of inputs without regard
inputs outputs to previous inputs
 PRODUCE DIFFERENT OUTPUTS

PERFORM LOGIC

ACCEPTS DIFFERENT INPUTES

Code conversion & Sample Example.
Design of combinational circuit
 FIND:
READ PROBLEM STATEMENT
NO OF INPUT
NO OF OUTPUT

WRITE T/T
PREPARE K-MAP FOR
ACCORDING TO GIVEN
EACH INDIVIDUAL O/P
LOGIC

DRAW LOGIC CIRCUIT ACCORDING TO DERIVIED BOOLEAN EQUATION

 A CIRCUIT HAS 4 INPUTS AND 2 OUTPUTS ONE OF THE OUTPUT IS HIGH WHEN MAJORITY OF INPUTS
ARE HIGH THE SECOND OUTPUT IS HIGH ONLY WHEN ALL INPUTS ARE OF SAME TYPE.
4-bit Binary O/P O/P

NO OF I/P:4 (A,B,C,D) A B C D Y Z
0 0 0 0 0 1
NO OF O/P:2 (Y,Z) 0 0 0 1 0 0
0 0 1 0 0 0
CONDITION FOR O/P:
0 0 1 1 0 0
1. Y=1 When majority of i/p=1 0 1 0 0 0 0
2. Z=1 when all i/p are same 0 1 0 1 0 0
0 1 1 0 0 0
0 1 1 1 1 0
Y= 𝑚(7,11,13,14,15) 1 0 0 0 0 0
1 0 0 1 0 0
0
Z= 𝑚(0,15) 1
1
0
0
1
1
0
1
0
1 0
1 1 0 0 0 0
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 1 1
 A CIRCUIT HAS 4 INPUTS AND 2 OUTPUTS ONE OF THE OUTPUT IS HIGH WHEN MAJORITY OF INPUTS
ARE HIGH THE SECOND OUTPUT IS HIGH ONLY WHEN ALL INPUTS ARE OF SAME TYPE.

NO OF I/P:4 (A,B,C,D)
CD
NO OF O/P:2 (Y,Z)
00 01 11 10
AB
0 4 12 8
CONDITION FOR O/P: 00
1. Y=1 When majority of i/p=1
1 5 13 9
2. Z=1 when all i/p are same 01 BCD
1
Y= 𝑚(7,11,13,14,15) 3 7 15 11
11 1 1 1
Y=ACD+ABD+ABC+BCD 2 6 14 10
10 1

ABD ACD
 A CIRCUIT HAS 4 INPUTS AND 2 OUTPUTS ONE OF THE OUTPUT IS HIGH WHEN MAJORITY OF INPUTS
ARE HIGH THE SECOND OUTPUT IS HIGH ONLY WHEN ALL INPUTS ARE OF SAME TYPE.

NO OF I/P:4 (A,B,C,D)
CD
NO OF O/P:2 (Y,Z)
00 01 11 10
AB
0 4 12 8
CONDITION FOR O/P: 00 1
1. Y=1 When majority of i/p=1
1 5 13 9
2. Z=1 when all i/p are same 01

Z= 𝑚(0,15) 11
3 7
1
15 11

Z=A’B’C’D’+ABCD 2 6 14 10
10

A’B’C’D’ ABCD
A CIRCUIT HAS 4 INPUTS AND 2 OUTPUTS ONE OF THE OUTPUT IS HIGH WHEN MAJORITY OF INPUTS
ARE HIGH THE SECOND OUTPUT IS HIGH ONLY WHEN ALL INPUTS ARE OF SAME TYPE.
A
C
D

A
B
D

A
B
C Y=ACD+ABD+ABC+BCD
B
C
D

A
B
C
D

A’
B
C’
D’
Z=A’B’C’D’+ABCD
 4-bit Binary 4-bit Gray
BINARY TO GRAY CONVERTER B4 B3 B2 B1 G4 G3 G2 G1
0 0 0 0 0 0 0 0

NO OF I/P:4 (B4,B3,B2,B1) 0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
NO OF O/P:4 (G4,G3,G2,G1)
0 0 1 1 0 0 1 0
CONDITION FOR O/P: 0 1 0 0 0 1 1 0

BINARY TO GRAY CONVERSION 0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
 4-bit Binary 4-bit Gray
BINARY TO GRAY CONVERTER B4 B3 B2 B1 G4 G3 G2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1

𝐺4 = 𝑚(8,9,10,11,12,13,14,15) 0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
𝐺3 = 𝑚(4,5,6,7,8,9,10,11)
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
𝐺2 = 𝑚(2,3,4,5,10,11,12,13) 1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
𝐺1 = 𝑚(1,2,5,6,9,10,13,14) 1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
 BINARY TO GRAY CONVERTER

B4B3
00 01 11 10 B4B3
B2B1 00 01 11 10
0 4 12 8 B2B1
00 1 1 0 4 12 8
00 1 1
1 5 13 9
01 1 1 1 5 13 9
01 1 1
3 7 15 11
11 1 1 3 7 15 11
11 1 1
2 6 14 10
10 1 1 2 6 14 10
10 1 1
G4 = B4
G3 = B4’B3 + B4B3’ = B4 ⨁ B3
𝐺4 = 𝑚(8,9,10,11,12,13,14,15) 𝐺3 = 𝑚(4,5,6,7,8,9,10,11)
 BINARY TO GRAY CONVERTER

B4B3 B4B3
00 01 11 10 00 01 11 10
B2B1 B2B1
0 4 0 4 12 8
12 8
00 1 1 00

1 1 5 13 9
5 13 9 01
01 1 1 1 1
1 1
3 7 3 7 15 11
15 11 11
11 1 1
2 2 6 14 10
6 14 10
10 1 1 10 1 1 1 1

G2 = B3’B2 + B3B2’ = B3 ⨁ B2 G1 = B2’B1 + B2B1’ = B2 ⨁ B1

𝐺2 = 𝑚(2,3,4,5,10,11,12,13) 𝐺1 = 𝑚(1,2,5,6,9,10,13,14)
 BINARY TO GRAY CONVERTER

G4 = B4 B4 G4
G3 = B4’B3 + B4B3’ = B4 ⨁ B3 G3
B3
G2 = B3’B2 + B3B2’ = B3 ⨁ B2
G2
G1 = B2’B1 + B2B1’ = B2 ⨁ B1 B2

G1
B1
 4-bit Binary 2’s comp
B4 B3 B2 B1 W X Y Z
2’s compliment of given number 0 0 0 0 0 0 0 0

NO OF I/P:4 (B4,B3,B2,B1) 0 0 0 1 1 1 1 1
0 0 1 0 1 1 1 0
NO OF O/P:4 (W,X,Y,Z)
0 0 1 1 1 1 0 1
CONDITION FOR O/P: 0 1 0 0 1 1 0 0

BINARY TO 2’s compliment CONVERSION 0 1 0 1 1 0 1 1

0 1 1 0 1 0 1 0
0 1 1 1 1 0 0 1
1 0 0 0 1 0 0 0
1 0 0 1 0 1 1 1
1 0 1 0 0 1 1 0
1 0 1 1 0 1 0 1
1 1 0 0 0 1 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 0 1 0
1 1 1 1 0 0 0 1
 4-bit Binary 2’s comp
B4 B3 B2 B1 W X Y Z
2’s compliment of given number 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1
0 0 1 0 1 1 1 0

W= 𝑚(1,2,3,4,5,6,7,8) 0 0 1 1 1 1 0 1
0 1 0 0 1 1 0 0
0 1 0 1 1 0 1 1
X= 𝑚(1,2,3,4,9,10,11,12)
0 1 1 0 1 0 1 0
0 1 1 1 1 0 0 1
Y= 𝑚(1,2,5,6,9,10,13,14) 1 0 0 0 1 0 0 0
1 0 0 1 0 1 1 1
𝑍= 𝑚(1,3,5,7,9,11,13,15) 1 0 1 0 0 1 1 0
1 0 1 1 0 1 0 1
1 1 0 0 0 1 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 0 1 0
1 1 1 1 0 0 0 1
 2’s compliment of given number

B1B2 B1B2
00 01 11 10 00 01 11 10
B3B4 B3B4
0 1 3 2 0 1 3 2
00 1 1 1 00 1 1 1
4 5 7 6 4 5 7 6
01 1 1 1 1 01 1
12 13 15 14 12 13 15 14
11 11 1
8 9 11 10 8 9 11 10
10 1 10 1 1 1

W= 𝑚(1,2,3,4,5,6,7,8) X= 𝑚(1,2,3,4,9,10,11,12)
 2’s compliment of given number

B1B2 B1B2
00 01 11 10 00 01 11 10
B3B4 B3B4
0 1 3 2 0 1 3 2
00 1 1 00 1 1
4 5 7 6 4 5 7 6
01 1 1 01 1 1
12 13 15 14 12 13 15 14
11 1 11
1 1 1
8 9 11 10 8 9 11 10
10 1 1 10 1 1

Y= 𝑚( 1,2,5,6,9,10,13,14) Z= 𝑚( 1,3,5,7,9,11,13,15)
 2’s compliment of given number

Z = B2
Y = B1’B2 + B1B2’ = B1 ⨁ B2
X = B1B4’ + B2B4’+B1’B2’B3

W = B3’B4+ B2B3’+B1 B2’ B4’

 BCD to Excess-3 converter
8421 BCD XS - 3
NO OF I/P:4 (B4,B3,B2,B1) B4 B3 B2 B1 X4 X3 X2 X1
NO OF O/P:4 (X4,X3,X2,X1) 0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
CONDITION FOR O/P:
BCD TO EX-3 CONVERSION
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
 BCD to Excess-3 converter
8421 BCD XS - 3
B4 B3 B2 B1 X4 X3 X2 X1
𝑋4 = 𝑚 5,6,7,8,9 + 𝑑(10,11,12,13,14,15)
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
𝑋3 = 𝑚 1,2,3,4,9 + 𝑑(10,11,12,13,14,15)
0 0 1 0 0 1 0 1
𝑋2 = 𝑚 0,3,4,7,8 + 𝑑(10,11,12,13,14,15) 0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
𝑋1 = 𝑚 0,2,4,6,8 + 𝑑(10,11,12,13,14,15) 0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
 BCD to Excess-3 converter

B2B1 B2B1
00 01 11 10 00 01 11 10
B4B3 B4B3
0 1 3 2 0 1 3 2
00 00 1 1 1
4 5 7 6 4
01 5 7 6
1 1 1 01 1
12 13 15 14 12 13
11 15 14
x x x x 11 x x x x
8 9 11 10 8 9 11 10
10 1 1 x x 10 1 x x

𝑋4 = 𝑚 5,6,7,8,9 + 𝑑(10,11,12,13,14,15) 𝑋3 = 𝑚 1,2,3,4,9 + 𝑑(10,11,12,13,14,15)

 BCD to Excess-3 converter

B2B1 B2B1
00 01 11 10 00 01 11 10
B4B3 B4B3
0 1 3 2 0 1 3 2
00 1 1 00 1 1
4 5 7 6 4
01 1 5 7 6
1 01 1
1
12 13 15 14 12 13
11 15 14
x x x x 11 x x x x
8 9 11 10 8 9 11 10
10 1 x x 10 1 x x

𝑋4 = 𝑚 0,3,4,7,8 + 𝑑(10,11,12,13,14,15) 𝑋3 = 𝑚 0,2,4,6,8 + 𝑑(10,11,12,13,14,15)

 BCD to Excess-3 converter
B4
B3
B2 X4
X1 = B1’ B3
B1
X2 = B2’B1’ + B2B1 B3
B2’
X3 = B3B2’B1’ + B3’ B1 + B3’ B2 B1’
B3’
X4 = B4 + B3B2 + B3B1 B1 X3
B3’
B2
B2’
B1’
X2
B2
B1
B1’ X1
Adders & Subtractors
 Half Adder Inputs Outputs
A B Sum Carry
A combinational circuit which adds 0 0 0 0
two one-bit binary numbers is 0 1 1 0
called a half-adder。 1 0 1 0
1 1 0 1

NO OF I/P:2 (A,B) A 0 1 A 0 1
NO OF O/P:2 (Sum,Carry) B B
0 1 0 1
CONDITION FOR O/P: 0 1 0
Addition of two bits 2 3 2 3
1 1 1 1

Sum = A’B + AB’ = A ⨁ B Carry = A◦B

 Half Adder

A
B S=A⊕B

In multi-digit addition we have to

C = AB
add two bits along with the carry
of previous digit addition. Such
addition requires addition of 3
bits. This is not possible in
half-adders。

1
 Full Adder

The full-adder adds the bits X and Y and the carry

from the previous column called carry-in Z and
outputs the sum bit S and the carry bit called Inputs Outputs
carry-out C
X Y Z S C
0 0 0 0 0
0 0 1 1 0
NO OF I/P:3 (X,Y,Z) 0 1 0 1 0
NO OF O/P:2 (Sum, Carry)
0 1 1 0 1
CONDITION FOR O/P: 1 0 0 1 0
Addition of three bits
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 XY
00 01 11 10 S = X’Y’Z + X’YZ’ + XY’Z’ + XYZ
Full Adder Z
0 2 6 4 = (XY’ + X’Y)Z’ + (XY+ X’Y’)Z
Inputs Outputs 0 1 1 = WZ’ + W’Z (XY’ + X’Y=W= X ⊕ Y )

X Y Z S C 1 3 = W⊕Z
1 1 17 5
0 0 0 0 0 = X ⊕Y⊕ Z
0 0 1 1 0
0 1 0 1 0
XY
00 01 11 10
Z
0 1 1 0 1 0 2 6 4
1 0 0 1 0 0 1 C = X’YZ + XY’Z + XYZ’ + XYZ
1 0 1 0 1 1 3 7 5 = (X’Y + XY’)Z + XY(Z+Z’)
1 1 1 1
1 1 0 0 1 = (X ⊕ Y)Z + XY
1 1 1 1 1
Full Adder

X S = X ⊕Y⊕ Z
Y

Z
C= (X ⊕ Y)Z + XY
Full Adder

X S = X ⊕Y⊕ Z
Y

Z
C= (X ⊕ Y)Z + XY

Half Adder Half Adder

 Half Subtractor Inputs Outputs
A B D B
NO OF I/P:2 (A,B)
NO OF O/P:2 (D,B) 0 0 0 0
CONDITION FOR O/P: 0 1 1 1
Subtraction of two bits 1 0 1 0
1 1 0 0

A 0 1 A 0 1
B B
0 1 0 1
0 1 0 1
2 3 2 3
1 1 1

D = A’B + AB’ = A ⨁ B B = A’◦B

Half Subtractor

A
D=A⊕B
B

B = A’B
 Full Subtractor

NO OF I/P:3 (X,Y,Z)
NO OF O/P:2 (D,B)
Inputs Outputs
CONDITION FOR O/P:
X Y Z D B
Difference of three bits
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
 XY
00 01 11 10 D = X’Y’Z + X’YZ’ + XY’Z’ + XYZ
Full Subtractor Z
0 2 6 4 = (XY’ + X’Y)Z’ + (XY+ X’Y’)Z
0 1 1 = WZ’ + W’Z (XY’ + X’Y=W= X ⊕ Y )
Inputs Outputs = W⊕Z
1 3
X Y Z D B 1 1 17 5
= X ⊕Y⊕ Z
0 0 0 0 0
0 0 1 1 1 XY
00 01 11 10
0 1 0 1 1 Z
0 2 6 4
0 1 1 0 1 0 1 B = X’Y’Z + X’YZ’ + X’YZ + XYZ
1 0 0 1 0 1 3 7 5 = (Y ⊕ Z)X’+ YZ
1 0 1 0 0 1 1 1 1
1 1 0 0 0
1 1 1 1 1
Full Subtractor

X
Y D = X ⊕Y⊕ Z

B = (Y ⊕ Z)X’+ YZ
 Binary Parallel Adder

A = 1010 A4 A3 A2 A1 =1010 B = 1011 B4 B3 B2 B1= 1011

1 1 0 0 1 1 1 0
B4 A4 B3 A3 B2 A2 B1 A1

0 1 0
0
C3 C2 C1
FA4 FA3 FA2 FA1 Cin

Cout C4 S4 S3 S2 S1
1 0 1 0 1
 Look Ahead carry Adder

The method of speeding up the addition is based on: Carry generate & Carry propagate functions.

Consider one full adder stage; say the nth stage of a parallel adder shown in below Figure.

An Bn = Gn
An Cn+1 = (An ⊕ Bn) Cn + An Bn
HA An ⊕ Bn = Pn Pn Cn
Bn
HA Sn = An ⊕ Bn ⊕ Cn
Cn

Cn+1 = (An ⊕ Bn) Cn + An Bn = Pn Cn + Gn Sn = An ⊕ Bn ⊕ Cn = Pn + Cn

 Look Ahead carry Adder

Based on these, the expressions for the carry-outs of various full adders are as follows:

C2 = G1 + P1 C1
C3 = G2 + P2 C2
= G2 + P2 (G1 + P1 C1)
= G2 + P2 G1 + P2 P1 C1
C4 = G3 + P3 C3
= G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 C1
C5 = G4 + P4 C4
= G4 + P4 G3 + P4 P3 G2 + P4 P3 P2 G1 + P4 P3 P2 P1 C1
Look Ahead carry Adder

B4
A4 P4 C5 C5

P4 S4
G4 C4

B3
A3 P3

P3 S3
G3 C3
Look ahead
B2
A2 P2 carry adder

P2 S2
G2 C2

B1
A1 P1

P1 S1
G1
C1 C1
Multiplexer/ De-multiplexer
&
Encoder/Decoder
 A multiplexer(MUX) is a device that allows digital
information from several sources to be routed onto a single
line for transmission over that line to a common
I0
destination 。 I1 mx1
 Consider an integer ‘m’, which is constrained by the Y
following relation: I2 MUX 1 output
。
。
m = 2n, where m and n are both integers. 。
 A m-to-1 Multiplexer has Im-1
• m Inputs: I0, I1, I2, ................ I(m-1) 。。
• One Output: Y
• n Control inputs: S0, S1, S2, ...... S(n-1) Enable (G) Sn-1 S1 S0
• One (or more) Enable input(s)
n control inputs
 2n inputs

clrs I0 Enable Select Inputs Output

I1 I0 I1 I2 I3 G S1 S0 Y
zee 4x1
Y 0
I2 MUX 1 output 0 X X
star
sony I3 1 0 0 clrs
1 0 1 zee
Enable (G) 1 1 0 star
S1 S0 1 1 1 sony
0 0
0 1 Y = G(S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3)
1 0
1 1
n=2 control inputs
I3

I2
Y = G(S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3)

I1

I0

S1 S0 Enable (G)
 Enable Select Inputs O/p
I0
G S2 S1 S0 Y
I1
I2 0 x x x 0
I3 8x1 1 0 0 0 I0
I4 MUX Output = Y
I5 1 0 0 1 I1
I6 1 0 1 0 I2
I7
1 0 1 1 I3
1 1 0 0 I4
1 1 0 1 I5
Enable (G) 1 1 1 0 I6
S2 S1 S 0 1 1 1 1 I7
 G S3 S2 S1 S0 Y
1 0 0 0 0 I0
I0 1 0 0 0 1 I1
I1 1 0 0 1 0 I2
I2
I3 1 0 0 1 1 I3
I4 1 0 1 0 0 I4
I5 1 0 1 0 1 I5
I6 16 x 1
I7 Output = Y
1 0 1 1 0 I6
MUX
I8 1 0 1 1 1 I7
I9 1 1 0 0 0 I8
I10
I11 1 1 0 0 1 I9
I12 1 1 0 1 0 I10
I13 1 1 0 1 1 I11
I14
I15 1 1 1 0 0 I12
1 1 1 0 1 I13
Enable (G) 1 1 1 1 0 I14
S 3 S2 S1 S0
1 1 1 1 1 I15
 I0
I1 4x1 MUX Select Inputs O/p
Y
I2 MUX 1 output G=S2 S1 S0 Y
A
I3 A 0 0 0 I0
Enable (G’) A 0 0 1 I1
S1 S0 A 0 1 0 I2
S2
Enable (G) A 0 1 1 I3
I4 B 1 0 0 I4
B 1 0 1 I5
I5 4x1 B 1 1 0 I6
Y
I6 MUX 1 output B 1 1 1 I7
B
I7
 A demultiplexer(DEMUX) is a device that allows digital
information from one source to be routed onto a multiple O0
lines for transmission over different destinations。
O1
1 input 1xM
 Consider an integer ‘m’, which is constrained by the O2
following relation:
DEMUX 。
D 。
。
m = 2n, where m and n are both integers. Om-1
 A 1-to-m demultiplexer has
• Input: D (only one i/p) 。。
• Outputs: O0, O1, O2, ................ O(m-1)
• n Control inputs: S0, S1, S2, ...... S(n-1) Enable (G) Sn-1 S1 S0
• One (or more) Enable input(s)
n control inputs
 2n Outputs
clrs O0 = D Enable Control I/P Outputs
zee D 1x4 O1 = D G S1 S0 O0 O1 O2 O3
0 X X 0 0 0 0
1 input DEMUX O2 = D
star 1 0 0 clrs 0 0 0
sony O3 = D 1 0 1 0 zee 0 0
1 1 0 0 0 star 0
1 1 1 0 0 0 sony
Enable (G)
S1 S0
0 0
0 1
1 0
1 1
n=2 control inputs
D S1 S1 ’ S0 S0 ’

O0 = D S 1’ S0’

O1 = D S 1’ S0

O 2 = D S 1 S0 ’

O 3 = D S 1 S0
 Select
En Inputs
OUTPUT

G S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
O0 0 x x x 0 0 0 0 0 0 0 0
O1 1 0 0 0 D 0 0 0 0 0 0 0
O2
1x8 O3 1 0 0 1 0 D 0 0 0 0 0 0
Input = D
DEMUX O4 1 0 1 0 0 0 D 0 0 0 0 0
O5
1 0 1 1 0 0 0 D 0 0 0 0
O6
O7 1 1 0 0 0 0 0 0 D 0 0 0
1 1 0 1 0 0 0 0 0 D 0 0
1 1 1 0 0 0 0 0 0 0 D 0
1 1 1 1 0 0 0 0 0 0 0 D
Enable (G)
S2 S1 S0
  Implement the function using MUX。 F(a,b,c)=Σm(0,2,4,6)

Logic 1 Logic 0

1. As it has 3 variable so we can use 8:1 mux.

I0
I1
2. The decimal number represents corresponding minterms I2
3. So connect this numbers to logic 1 line e.g 0,2,4,6 I3 8x1
4. Connect others to logic 0 line e.g 1,3,5,7
I4 MUX Output
I5 F(a,b,c)
5. Connect variable as a select input. I6
I7

S2 S1 S0
Enable (G)
A B C
  Realize the logic function of truth table given below using MUX。
A B C Y
Logic 1 Logic 0
0 0 0 0
0 0 1 1
0 1 0 0 F(a,b,c)=Σm(1,3,4,6) I0
0 1 1 1
I1
I2
1 0 0 1 I3 8x1
1 0 1 0 I4 MUX Output
1 1 0 1 I5 F(a,b,c)
I6
1 1 1 0 I7
1. As it has 3 variable so we can use 8:1 mux.
2. So connect this numbers to logic 1 line e.g 1,3,4,6
S2 S1 S0
3. Connect others to logic 0 line e.g 0,2,5,7
4. Connect variable as a select input. Enable (G)
A B C
 Implement a full adder using 8:1 MUX。
X Y Z S C
Logic 1 Logic 0 Logic 1 Logic 0
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0 I0 I0
0 1 1 0 1
I1 I1
I2 I2
1 0 0 1 0 I3 8x1 I3 8x1
1 0 1 0 1 I4 MUX I4 MUX
1 1 0 0 1 I5 I5
I6 I6
1 1 1 1 1 I7 I7
SUM(a,b,c)=Σm(1,2,4,7)
CARRY(a,b,c)=Σm(3,5,6,7)
S2 S1 S0 S2 S1 S0
Enable (G) Enable (G)
X Y Z X Y Z
Output SUM(a,b,c) Output CARRY(a,b,c)
 Implement the function F(a,b,c)=Σm(1,3,4,6) using 4:1 MUX。

A A’

I/P D0 D1 D2 D3
A’ 0 1 2 3
D0
A 4 5 6 7
D1 4x1
FINAL A A’ A A’ D2 MUX Output
D3 F(a,b,c)

S1 S0
Enable (G)
B C
 Implement a full adder using 4:1 MUX。

SUM(X,Y,Z)=Σm(1,2,4,7)
X X’ X 10
I/P D0 D1 D2 D3
X’ 0 1 2 3
X 4 5 6 7
FINAL X X’ X’ X
D0 D0
D1 4x1 4x1
CARRY(a,b,c)=Σm(3,5,6,7) D1
D2 MUX D2 MUX
I/P D0 D1 D2 D3 D3 D3
X’ 0 1 2 3
X 4 5 6 7
FINAL 0 X X X’
S1 S0 S1 S0
Enable (G) Enable (G)
Y Z Y Z
Output SUM(X,Y,Z) Output CARRY(X,Y,Z)
  Implement a Function using 8:1 MUX。

F(a,b,c,d)=Σm(2,4,5,7,10,14)
I/P D0 D1 D2 D3 D4 D5 D6 D7
A’ 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15
FINAL 0 0 1 0 A’ A’ A A’

 Implement a Function using 16:1 MUX。

F(a,b,c,d,e)=Σm(2,4,5,7,10,14,15,16,17,25,26,30,31)

I/P D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

A’ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

FINAL A A A’ 0 A’ 0 0 A’ 0 A 1 0 0 0 1 1
 A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2N unique output lines 。
 logic circuit that accepts a set of inputs which represents a binary number and
activates the only output that corresponds to the input number 。
 In its general form, a decoder has N input lines to handle N bits and M output lines
such that only one output line is activated for each one of the possible combinations
of inputs 。

I0 O0
I1 O1
I2 O2
. .
N inputs
. Decoder .
M outputs M = 2N
. .
IN-2 OM-2
IN-1 OM-1
  A decoder circuit has 2 input lines and 22 = 4 output lines 。
 a decoder circuit looks at its inputs, determines which binary number is present
there, and activates the specific output which corresponds to that number; all other
outputs remain inactive.

I/P Outputs
A B D0 D1 D2 D3
0 0 1 0 0 0
D0
A D1 0 1 0 1 0 0
2 to 4 D2
B 1 0 0 0 1 0
Decoder
D3 1 1 0 0 0 1
D0=A’B’ D1=A’B D2=AB’ D3=AB
A A’ B B’

D0 = A’ B’

D1 = A’B

D2 = AB’

D3 = AB
 Inputs OUTPUT
A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
D0 0 0 1 0 1 0 0 0 0 0 0
D1
D2 0 1 0 0 0 1 0 0 0 0 0
A
3 to 8 D3 0 1 1 0 0 0 1 0 0 0 0
B D4
C Decoder 1 0 0 0 0 0 0 1 0 0 0
D5
D6 1 0 1 0 0 0 0 0 1 0 0
D7
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
A A’ B B’ C C
’
D7 = ABC

D6 = ABC’

D5 = AB’C

D4 = AB’C’

D3 = A’BC

D2 = A’BC’

D1 = A’B’C

D0 = A’B’C’
  An encoder is a combinational circuit that generates binary number from 2N input
lines to a maximum of N unique output lines 。
 logic circuit that accepts a set of inputs and activates the only output that
corresponds to the input number which represents a binary number 。

I0 O0
I1 O1
I2 O2
. .
M = 2N M inputs
. Encoder .
N outputs
. .
IM-2 ON-2
IM-1 ON-1
 INPUT OUTPUT
D0 D1 D2 D3 D4 D5 D6 D7 B0 B1 B2
1 0 0 0 0 0 0 0 0 0 0
D0 0 1 0 0 0 0 0 0 0 0 1
D1 0 0 1 0 0 0 0 0 0 1 0
D2 B0
D3 BCD to 0 0 0 1 0 0 0 0 0 1 1
B1
D4 Binary 0 0 0 0 1 0 0 0 1 0 0
B2
D5 Encoder
0 0 0 0 0 1 0 0 1 0 1
D6
D7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

B0 = D4 + D5 + D6 + D7 B1 = D2 + D3 + D6 + D7
B2 = D1 + D3 + D5 + D7
D0 D1 D2 D3 D4 D5 D6 D7

B0

B1

B2
 An additional bit called parity bit is added to the data bits and the word containing
the data bits and the parity bit is transmitted 。
 when transmitted and processed is susceptible to noise that can alter its 1s to 0s and
0s to 1s 。
 At the receiving end the number of 1s in the word received are counted and the error,
if any, is detected 。
 Data: 001 than two type of parity bit can be as follows

Even Parity Odd Parity

0 0 1 1 0 0 1 0

Data Parity bit Data Parity bit

 AB
Inputs Outputs 00 01 11 10
C
parity bit
A B C (f) 0 1 1
0 0 0 0
0 0 1 1 1 1 1
0 1 0 1
𝑓 = 𝐴′ 𝐵′ 𝐶 + 𝐴′ 𝐵𝐶′+ 𝐴𝐵𝐶 + 𝐴𝐵′𝐶′
0 1 1 0
1 0 0 1 𝑓 = 𝐴′ 𝐵′ 𝐶 + 𝐵𝐶 ′ + 𝐴(𝐵𝐶 + 𝐵′ 𝐶 ′ )
1 0 1 0 𝑓 = 𝐴′ 𝐵 ⨁ 𝐶 + 𝐴 𝐵 ⨁ 𝐶 ′
𝐴⊕𝐵
A
1 1 0 0 𝑓 =𝐴⊕𝐵⨁𝐶
B f
1 1 1 1 C
 A comparator is a logic circuit used to compare the magnitudes of two binary numbers 。
 Comparator circuit provides 3 outputs
1. A = B
2. A > B
3. A < B
 2 binary numbers are equal if and only if all their corresponding bits coincide 。
 1-bit Magnitude Comparator
A < B(L)
A0 B0 L E G
0 0 0 1 0 A0
B0 A = B(E)
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0 A > B(G)
A1 A0 B1 B0 A<B A=B A>B
0 0 0 0 0 1 0
0 0 0 1 1 0 0  Let the two 2-bit numbers be A =
0 0 1 0 1 0 0 A1A0 and B = B1B0。
0 0 1 1 1 0 0
Equal
0 1 0 0 0 0 1
 If A1 & B1 coincide and if A0 & B0
0 1 0 1 0 1 0
coincide then A = B.
0 1 1 0 1 0 0
0 1 1 1 1 0 0 Greater
1 0 0 0 0 0 1  If A1 = 1 & B1 = 0, then A > B or
1 0 0 1 0 0 1
 If A1&B1 coincide and A0=1&B0 = 0,
then A > B.
1 0 1 0 0 1 0
1 0 1 1 1 0 0 Less
1 1 0 0 0 0 1  If A1 = 0 & B1 = 1, then A < B or
1 1 0 1 0 0 1  If A1&B1 coincide and A0=0&B0= 1,
1 1 1 0 0 0 1
then A < B.
1 1 1 1 0 1 0
 A1A0 A1A0 A1A0
00 01 11 10 00 01 11 10 00 01 11 10
B1B0 BB B1B0
0 1 3 2 1 0 0 1 3 2 0 1 3 2
00 1 00 1 1 1 00
4 5 7 6 4 5 7 6 4 5 7 6
01 1 01 1 1 01 1
12 13 15 14 12 13 15 14 12 13 15 14
11 1 11 11 1 1 1
8 9 11 10 8 9 11 10 8 9 11 10
10 1 10 1 10 1 1

(A = B ) = (A1 ⊙ B1)(A0 ⊙ B0) (A < B) = A1’B1 + (A1 ⊙ B1) A0’B0 A > B = A1B1’ + (A1 ⊙ B1) A0B0’
 A1
B1’
A0 A > B(G)
B0’

A1
B1
A = B(E)
A0
B0

B0 A0’
A < B(L)
A1’
B1
 D3 D2 D1 D0 Y Z
0 0 0 0 X X
 It is a logic circuit that responds to just 0 0 0 1 0 0
one input in accordance with some priority
0 0 1 0 0 1
system, among all those that may be
simultaneously HIGH. 0 0 1 1 0 1
 The relative magnitudes of the inputs; 0 1 0 0 1 0
whichever decimal input is the largest, is
0 1 0 1 1 0
the one that is encoded.
 If both decimal 3 and decimal 4 are 0 1 1 0 1 0
activated simultaneously, then a priority 0 1 1 1 1 0
encoder would encode decimal 4.
1 0 0 0 1 1
Inputs Outputs
1 0 0 1 1 1
D3 D2 D1 D0 Y Z
1 0 1 0 1 1
0 0 0 0 x x
1 0 1 1 1 1
0 0 0 1 0 0 1 1 0 0 1 1
0 0 1 x 0 1 1 1 0 1 1 1
0 1 x x 1 0 1 1 1 0 1 1
1 x x x 1 1 1 1 1 1 1 1
 D1D0 D1D0
00 01 11 10 00 01 11 10
D3D2 D3D2
0 1 3 2 0 1 3 2
00 00 1 1
4 5 7 6 4 5 7 6
01 1 1 1 1 01

12 13 15 14 12 13 15 14
11 1 1 1 11 1 1 1 1
1
8 9 11 10 8 9 11 10
10 1 1 1 1 10 1 1 1 1

Y = D2 + D3 Z = D1D2 ‘ + D3
D3 Z = D3 + D2’ D1

D2
D1
D0
Y = D3 + D2
 FIND:
READ PROBLEM STATEMENT
NO OF INPUT
NO OF OUTPUT

WRITE T/T
PREPARE K-MAP FOR
ACCORDING TO GIVEN
EACH INDIVIDUAL O/P
LOGIC

DRAW LOGIC CIRCUIT ACCORDING TO DERIVIED BOOLEAN EQUATION

Half Adder Half Subtractor Parallel Adder Look Ahead carry Adder
Full Adder Full Subtractor
 Multiplixers

Demultiplixers

Encoders

Decoders