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Lab 3 DLD

This document describes an experiment on implementing half adders and full adders using logic gates. The objective is to realize half adders and full adders using AND and XOR gates. The experiment involves verifying the gates, making the appropriate connections according to circuit diagrams, applying various input combinations to determine the output sum and carry bits, and answering questions about combinational circuits, differences between logical and arithmetic operations, designing a full adder using half adders, and the components of a full adder.

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BARKAT Ali
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56 views5 pages

Lab 3 DLD

This document describes an experiment on implementing half adders and full adders using logic gates. The objective is to realize half adders and full adders using AND and XOR gates. The experiment involves verifying the gates, making the appropriate connections according to circuit diagrams, applying various input combinations to determine the output sum and carry bits, and answering questions about combinational circuits, differences between logical and arithmetic operations, designing a full adder using half adders, and the components of a full adder.

Uploaded by

BARKAT Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EXPERMENT NO.

03 HALF ADDER AND FULL ADDER DIGITAL LOGIC DESIGN LAB MANUAL

EXPARIMENT No. :3

Student Name: MUHAMMAD UMAR FAROOQ Roll No: 20TC1019

Date: _________________ Instructor Signature: _____________

HALF ADDER AND FULL ADDER

OBJECTIVE:
To realize half adder and full adder using AND & X-OR gates.

EQUIPMENT REQURIED:
IC trainers, power supply, connecting wires.

COURSE OF ACTION:
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according
to the truth table.
4. Note down the output readings for half adder and full adder sum/carry
bit for different combinations of inputs.

HALF-ADDER:
Department of Information and Communication Engineering 1|Page
EXPERMENT NO. 03 HALF ADDER AND FULL ADDER DIGITAL LOGIC DESIGN LAB MANUAL

(2-bit value)
Truth table

Input Inpu Outpu Carry


(X) t (Y) t (sum)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Expression:

Sum = x' y + x y'

Carry = x y

Circuit diagram:

FULL-ADDER

Department of Information and Communication Engineering 2|Page


EXPERMENT NO. 03 HALF ADDER AND FULL ADDER DIGITAL LOGIC DESIGN LAB MANUAL

Truth table
Input (X) Input (Y) Input (Z) Output Carry
(sum)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 1
1 1 1 1 1

Expression:
Sum = z(x' y + x y') '+ z'(x' y + x y')
Carry = z(x' y + x y') + x y

Circuit diagram:

Department of Information and Communication Engineering 3|Page


EXPERMENT NO. 03 HALF ADDER AND FULL ADDER DIGITAL LOGIC DESIGN LAB MANUAL

Questions about above Experiment


Q1: What is combinational circuit with example?

A: A Combinational Circuit consist of logic gates whose outputs at any


instant of time are determined directly from the present combination of
inputs without regard to previous input. Examples of combinational
circuits: Adder, Subtractor, Converter, and Encoder/Decoder.

Q2: What is the difference between logical and arithmetic?


A:
Department of Information and Communication Engineering 4|Page
EXPERMENT NO. 03 HALF ADDER AND FULL ADDER DIGITAL LOGIC DESIGN LAB MANUAL

Arithmetic Logical
Arithmetic operators perform their  Logical operators compare two
actions on numbers. Assignment values and, based on whether the
operators assign values to comparison is true (or false),
variables. return either a “true” or “false.”

Q3: Design a full adder using half adders?

A:

Q4: At which gates Full-adder consist of?


A: A full-adder consist of 2 half-adder and OR gate it’s basically output
of 2 half-adder which are X-OR and AND gate and Cin inputs.
______________________________________________

Department of Information and Communication Engineering 5|Page

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