A Major Project Report

Submitted in partial fulfillment of the requirement for the award of the degree of

BACHELOR OF TECHNOLOGY
(ELECTRICAL & ELECTRONICS ENGINEERING)
To

ARYABHATTA KNOWLEDGE UNIVERSITY

Submitted by
NAME ROLL No. REGISTRATION No.
AMRITA KUMARI 154001 15103103343
RAMAKANT KUMAR 154002 15101103017
AAKASH KUMAR 154003 15103103345
TAUSIF IQBAL 154004 15103103346
SONU KUMAR 154005 15103103347
TUSHAR KUMAR 154006 15103103348

Under the supervision of

Mr. Ritesh Kumar
Assistant Professor
NSIT Bihta Patna

Department of Electrical & Electronics Engineering

NETAJI SUBHAS INSTITUTE OF TECHNOLOGY,
BIHTA, PATNA-801118
May 2019
 CANDIDATE’S DECLARATION

We Amrita Kumari (154001), Ramakant Kumar (154002), Aakash Kumar (154003),

Tausif Iqbal (154004), Sonu Kumar (154005), Tushar Kumar (154006), students of
Bachelor of Technology (Electrical & Electronics Engineering) at Netaji Subhas Institute of
Technology, Bihta, Patna, declare that the work presented in this major project titled
“Hardware Implementation of Single Phase 7-Level Inverter”, submitted to Aryabhatta
Knowledge University, Patna during academic year (2015-2019) for the award of Bachelor
of Technology degree in Electrical & Electronics Engineering, is my original work. All work
done in this major project is entirely my own except for the reference quoted. To the best of
my knowledge this work has not been submitted to any other university or institution for
award of any degree.

Date: NAME ROLL No. Sign.

Place: NSIT, Bihta 1. AMRITA KUMARI 154001

2. RAMAKANT KUMAR 154002
3. AAKASH KUMAR 154003
4. TAUSIF IQBAL 154004
5. SONU KUMAR 154005
6. TUSHAR KUMAR 154006
 CERTIFICATE

It is to certify that work embodies in this report entitled “Hardware Implementation of

Single Phase 7-Level Inverter” submitted by Amrita Kumari (154001), Ramakant
Kumar (154002), Aakash Kumar (154003), Tausif Iqbal (154005), Sonu Kumar (15400),
Tushar Kumar (154006), in partial fulfillment of the requirement for the award of the
degree of “Bachelor of Technology in Electrical & Electronics Engineering” to Aryabhatta
Knowledge University, Bihta,Patna during the academic year 2015-2019.According to best
of my knowledge is a record of bonafide piece of work, carried out by him under my
guidance in Department of Electrical & Electronics Engineering, Netaji Subhas Institute of
Technology,Bihta,Patna. To the best of my knowledge this work has not been submitted to
any other university or institution for award of any degree.

Supervisor HOD
Mr. Ritesh Kumar Dr. Jyotirmayee Dalei
Assistant Professor Associate Professor & Head
Dept. of EEE Dept. of EEE
N.S.I.T, Bihta N.S.I.T, Bihta
 APPROVAL

This project entitled “Hardware Implementation of Single Phase 7-Level Inverter”

submitted by

SL. No. NAME ROLL No.

1. AMRITA KUMARI 154001
2. RAMAKANT KUMAR 154002
3. AAKASH KUMAR 154003
4. TAUSIF IQBAL 154004
5. SONU KUMAR 154005
6. TUSHAR KUMAR 154006

is approved for the award of degree of Bachelor of Technology in Electrical & Electronics
Engineering.

INTERNAL EXAMINER EXTERNAL EXAMINER

 ACKNOWLEDGEMENT

It is with a feeling of immense gratitude and regard that we thank our guide, Mr. Ritesh
Kumar (Assistant Professor), Dept. of Electrical & Electronics Engineering, for his
valuable and expert guidance which he has provided us within the course of this project. We
are indebted to her valuable suggestions and highly productive discussions from time to time
that have been instrumental in giving direction to this project and without which this project
could never have been completed.

We specially thank our Head of Department, Dr. Jyotirmayee Dalei, without whose
permission, this project could not have materialized. We are sincerely thankful to her for
providing us with such sophisticated laboratories and equipment’s wherein we could carry
out the experiments related to the project.

We wish to express our heartfelt thanks to the faculty and staff members of the Department of
Electrical & Electronics Engineering, N.S.I.T, who despite being busy with their own
assignments, gave us time and provided us with all the help we needed. We would also like to
express gratitude to the lab in-charge and technicians who helped us throughout the duration
in carrying out experiments related to the project.

We are highly indebted to the Library Department of our institute which provided us with an
excellent collection of reference books, research journals and articles that helped us in
completing this project. Along with this we would like to thank the IT Department of our
institute for the internet facility that they provided.

We hope this project work will serve as a reference for further research work that may be
carried out in this project.

Student Name Roll No.

1. AMRITA KUMARI 154001
2. RAMAKANT KUMAR 154002
3. AAKASH KUMAR 154003
4. TAUSIF IQBAL 154004
5. SONU KUMAR 154005
6. TUSHAR KUMAR 154006

a
 ABSTRACT

Tough the multilevel inverters hold attractive features, usage of more

switches in the conventional configuration poses a limitation to its wide
range application.Therefore, a renewed 7-level multilevel inverter topology
is introduced incorporating the least number of unidirectional switches and
gate trigger circuitry, thereby ensuring the minimum switching losses,
reducing size and installation cost. The new topology is well suited for
drives and renewable energy applications. The performance quality in terms
of THD and switching losses of the new MLI is compared with conventional
cascaded MLI and other existing 7-level reduced switch topologies using
carrier-based PWM techniques.The results are validated using
MATLAB/SIMULINK.

i
 CONTENTS
ACKNOWLEDGEMENTS a

ABSTRACT i

TABLE OF CONTENTS ii

LIST OF FIGURE iv-v

LIST OF TABLE vi

LIST OF ABBERVIATION vii-viii

CHAPTER 1: MULTILEVEL INVERTER AN OVERVIEW 1-4

1.1 INTRODUCTION 1

1.2 INVERTER 2

1.3 ADVANTAGES AND DISADVANTAGES 3

1.4 ORGANIZATION OF THE REPORT 4

1.5 SUMMARY 4

CHAPTER 2: LITERATURE REVIEW 5-25

2.1 INTRODUCTION 5

2.2 LITERATURE REVIEW 5

2.2.1 MULTILEVEL INVERTER 5

2.2.2 FLYING CAPACITOR MULTILEVEL INVERTER 12

2.2.3 CASCADED MULTILEVEL INVERTER 16

2.3 SWITCH REDUCTION TOPOLOGIES IN MLI 19

2.3.1 THREE LEVEL MLI 19

2.3.2 FIVE LEVEL MLI 20

ii
 2.4 HARMONIC ELIMINATION IN MLI 21

2.4.1 CONTROL SCHEME 22

2.5 INFERENCES DRAWN OUT OF LITERATURE 24

REVIEW
2.6 SUMMARY 25

CHAPTER 3: PROPOSED WORK 26-30

3.1 PROBLEM DEFINITION 26

3.2 OBJECTIVES 26

3.3 PURPOSED WORK 26

3.3.1 HARMONIC ELIMINATION 27

3.4 SUMMARY 30

CHAPTER 4: METHODOLOGY 31-49

4.1 IMPLEMENTATION STRATEGY 31

4.2 SIMULINK MODEL OF DIFFERENT MULTILEVEL 32

INVERTER
4.3 HARDWARE COMPONENTS 43

4.4 HARDWARE SETUP 46

4.5 EXPERIMENTAL RESULT 47

4.6 SUMMARY 49

CHAPTER 5: CONCLUSIONS AND FUTURE WORK 50-51

5.1 CONCLUSION 50

5.2 FUTURE WORK 51

REFERENCES 52-54

iii
 LIST OF FIGURE
Figure 1.1 General block diagram of inverter 2

Figure 1.2 Block diagram of VSI and CSI Inverters 2

Figure 2.1 Topology of the diode clamped inverter (a) three level inverter, (b) five level 7
inverter
Figure 2.2 Output voltage in three level diode clamped inverter (a) leg voltage (b) 8
output phase voltage
Figure 2.3 Capacitor-clamped multilevel inverter circuit topologies, (a) 3-level inverter 13
(b) 5-level inverter
Figure 2.4 Single phase structures of cascaded inverter (a) 3-level (b) 5-level, (c) 7- 17
level
Figure 2.5 Three phase seven level cascaded multilevel inverter (Y Configuration) 18

Figure 2.6 Control Scheme for MLI 22

Figure 3.1 Diagram of the proposed model 29

Figure 3.2 Block diagram of seven level inverter 30

Figure 4.1 Simulation of three level inverter 32

Figure 4.2 Simulation of five level inverter 32

Figure 4.3 Simulation of seven level inverter 33

Figure 4.4 Output waveform of seven level inverter 33

Figure 4.5 PWM circuit of seven level inverter used in MATLAB 33

Figure 4.6 PWM waveform of seven level inverter 34

Figure 4.7 FFT Analysis 34

Figure 4.8 Simulation of nine level inverter 35

Figure 4.9 Simulation of eleven level inverter 35

iv
Figure 4.10 Simulation of thirteen level inverter 36

Figure 4.11 Simulation of fifteen level inverter 36

Figure 4.12 Simulation of three level inverter with RL load 37

Figure 4.13 Simulation of five level inverter with RL load 38

Figure 4.14 Simulation of seven level inverter with RL load 38

Figure 4.15 Simulation of nine level inverter with RL load 39

Figure 4.16 Simulation of eleven level inverter with RL load 40

Figure 4.17 Simulation of thirteen level inverter with RL load 41

Figure 4.18 Simulation of fifteen level inverter with RL load 42

Figure 4.19 Pin diagram of microcontroller 44

Figure 4.20 Driver circuit 45

Figure 4.21 Experimental setup of seven level inverter 46

Figure 4.22 Output waveform of seven level inverter 47

Figure 4.23 Gate pulses of MOSFET Pin 22, 23, 24 and 25 48

Figure 4.24 Gate pulses of MOSFET Pin 23, 24, 25 and 26 48

v
 LIST OF TABLE

Table 2.1 Switching states in one leg of the three level diode clamped inverter 7

Table 2.2 Switching state in one leg of the five level diode clamped inverter 9

Table 4.1 Comparison of THD with Reference Papers 31

Table 4.2 THD analysis of R load 37

Table 4.3 THD analysis of RL load 42

Table 4.4 Hardware components Used 43

Table 4.5 Switching scheme for seven level inverter 7- switch topology 47

vi
 LIST OF ABBREVIATIONS
FACTS Flexible AC Transmission Systems

SVG Static VAR Generation

MLI Multi-Level Inverter

CMC Cascaded Multilevel Converter

CMI Cascaded Multi-level Inverter

HBBB H-bridge building block

PWM Pulse Width Modulation

SVM Space-Vector Modulation

CM Common-Mode

NPC Neutral-Point Clamped

ARCP Auxiliary Resonant Commutated Pole

ZVT Zero-Voltage Transition

VSI Voltage Source Inverter

THD Total Harmonic Distortion

SHE Selective Harmonic Elimination

SVC Space Vector Control

UPFC Unified Power-Flow Controller

CSI Current Source Inverter

DCI Diode Clamped Inverter

vii
FCMLI Flying Capacitor Multi Level Inverter

HV High Voltage

LV Low Voltage

FPGA Field Programmable Gate Array

SPWM Sinusoidal Pulse Width Modulation

DC Direct Current

DSP Digital Signal Processing

PLD Programmable Logic Device

CMI Common Mode Interference

MPC Multiple Point Clamped

viii
 CHAPTER 1

MULTILEVEL INVERTER AN OVERVIEW

1.1 INTRODUCTION

Numerous industrial applications have initiated to require higher power apparatus in

recent years. Some medium voltage motor drives and utility applications require medium
voltage and megawatt power level. For a medium voltage grid, it is troublesome to
connect only one power semiconductor switch directly. As a result, a multilevel power
converter structure has been introduced as an alternative in high power and medium
voltage situations. A multilevel converter not only achieves high power ratings, but also
enables the use of renewable energy sources. Renewable energy source such as
photovoltaic, wind, and fuel cells can be easily interfaced to a multilevel converter system
for high power applications.

The concept of multilevel converters has been introduced since 1975. The term
multilevel began with the three-level converter. Subsequently, several multilevel
converter topologies have been developed. However, the elementary concept of a
multilevel converter to achieve higher power is to use a series of power semiconductor
switches with several lower voltage dc sources to perform the power conversion by
synthesizing a staircase voltage waveform. Capacitors, batteries, and renewable energy
voltage source can be used as the multiple dc voltage sources. The commutation of the
power switches aggregate these multiple dc source in order to achieve high voltage at the
output; however, the rated voltage of the power semiconductor switches depends only
upon the rating of the dc voltage source to which they are connected.

One clear disadvantage of multilevel power conversion is the higher number of

semiconductor switches required. It should be pointed out that lower voltage rated
switches can be used in the multilevel converter and, therefore, the active semiconductor
cost is not appreciably increased when compared with the two level cases. However, each
active semiconductor added requires associated gate drive circuits and adds further
complexity to the converter mechanical layout. Another disadvantage of multilevel power
converters is that the small voltage steps are typically produced by isolated volt-age
sources or a bank of series capacitors. Isolated voltage sources may not always be readily
available, and series capacitors require voltage balancing. To some extent, the voltage

1
balancing can be addressed by using redundant switching states, which exist due to the
high number of semiconductor devices.

1.2 INVERTER

A device that converts DC power into AC power at desired output voltage and frequency
is called an Inverter. Phase controlled converters when operated in the inverter mode are
called line commutated inverters. But line commutated inverters require at the output
terminals an existing AC supply which is used for their commutation. This means that
line commutated inverters can‟t function as isolated AC voltage sources or as variable
frequency generators with DC power at the input. Therefore, voltage level, frequency and
waveform on the AC side of the line commutated inverters can‟t be changed. On the other
hand, force commutated inverters provide an independent AC output voltage of adjustable
voltage and adjustable frequency and have therefore much wider application.

Fig.1.1 General Block Diagram of Inverter

Based on their operation the inverters can be broadly classified into:

• Voltage Source Inverters (VSI)

• Current Source Inverters (CSI)

Fig.1.2 Block Diagram of VSI and CSI Inverters

2
A voltage source inverter is one where the independently controlled ac output is a voltage
waveform.

A current source inverter is one where the independently controlled ac output is a current
waveform.

Some industrial applications of inverters are for adjustable- speed ac drives, induction
heating, stand by air-craft power supplies, UPS uninterruptible power supplies) for
computers, HVDC transmission lines etc.

Used. These inverters usually require a fairly high input voltage - 48 volts or more. Some,
like the Sunny Boy, go up to 600 volts DC input.

1.3 ADVANTAGES AND DISADVANTAGES

A multilevel converter has several advantages over a conventional two-level converter

that uses high switching frequency pulse width modulation (PWM). The attractive
features of a multilevel converter can be briefly summarized as follows.

• Staircase waveform quality: Multilevel converters not only can generate the
output voltages with very low distortion, but also can reduce the dv/dt stresses; therefore
electromagnetic compatibility (EMC) problems can be reduced.

• Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage;

therefore, the stress in the bearings of a motor connected to a multilevel motor drive can
be reduced. Furthermore, CM voltage can be eliminated by using advanced modulation
strategies

• Input current: Multilevel converters can draw input current with low distortion.

• Switching frequency: Multilevel converters can operate at both fundamental

switching frequency and high switching frequency PWM. It should be noted that lower
switching frequency usually means lower switching loss and higher efficiency.

Unfortunately, multilevel converters do have some disadvantages. One particular

disadvantage is the greater number of power semiconductor switches needed. Although
lower voltage rated switches can be utilized in a multilevel converter, each switch
requires a related gate drive circuit. This may cause the overall system to be more
expensive and complex.

3
Plentiful multilevel converter topologies have been proposed during the last two decades
Contemporary research has engaged novel converter topologies and unique modulation
schemes. Moreover, three different major multilevel converter structures have been
reported in the literature: cascaded H-bridges converter with separate dc sources, diode
clamped (neutral- clamped), and flying capacitors (capacitor clamped). Moreover,
abundant modulation techniques and control paradigms have been developed for
multilevel converters such as sinusoidal pulse width modulation (SPWM), selective
harmonic elimination (SHE-PWM), space vector modulation (SVM), and others. In
addition, many multilevel converter applications focus on industrial medium-voltage
motor drives, utility interface for renewable energy systems, flexible AC transmission
system (FACTS), and traction drive systems.

1.4 Organization of the report

The outline of the present work as reported in the project is described in brief as follow:

Chapter 1: This is the introductory chapter of the report. Basics of the inverter are
reviewed. Objectives of the present work are highlighted.

Chapter 2: In this chapter, review of multilevel inverter, and power electronics converter
topologies are described

Chapter 3: In this chapter, proposed seven level inverter is described.

Chapter 4: In this chapter, Modelling of different level inverter is carried out using
MATLAB/SIMULINK and followed by its hardware implementation.

Chapter 5: This chapter concludes the work presented in the report. Further, it highlights
the limitation and future scope of the work presented in the report.

1.5 SUMMARY

In this chapter, multilevel inverter is discussed in brief and basics of inverter are
explained. The PWM techniques are given in detail. The types of inverters have been
discussed including voltage source inverters, current source inverters.

4
 CHAPTER 2

LITERATURE REVIEW

2.1 INTRODUCTION

Literature review is very significant step in any research project as it established the need
and background of the work to be taken up. It generates related queries regarding
improvements in the work already undertaken prior to the present work and allows
unsolved problems/hypotheses to emerge and thus, clearly defines all boundaries
regarding the development of a research project. The investigator went through several
IEEE and other international journals for various Multilevel Inverter topologies and their
applications which are listed in the reference.

2.2 LITERATURE REVIEW

The demand of quality power is increasing continuously. The problem of global warming
and rate of decrease of non-renewable energy sources are increasing day by day. Hence
renewable energy sources such as fuel cell, solar, Magneto hydro Dynamic (MHD),
geothermal are the best alternatives to solve the problem of environmental issue and
increasing demand of energy. The output of these resources is dc, therefore to connect
these resources to the grid; multilevel inverter is the key device. But the output of
multilevel inverter has power quality issues such as harmonic generation and notching
due to conversion of dc to ac and high number of switch. An exhaustive literature review
has been carried out and presented as readymade reference for researchers in the field of
Harmonic Elimination

2.2.1 MULTILEVEL INVERTER

Multilevel inverter provides a suitable solution for medium and high-power system to
synthesize an output which allows a reduction of harmonic content in voltage and current
waveforms. Multilevel refers to the multiple connections of individual inverter termed as
„stage‟ to provide the output voltage with required „levels‟. Rodriguez et al. in [1] have
presented a new class of multilevel inverters based on a multilevel dc link (MLDCL) and
a bridge inverter to reduce the number of switches, clamping diodes, or capacitors.
Compared with the cascaded H-bridge, diode-clamped, and flying-capacitor multilevel

5
inverters, the MLDCL inverters could significantly reduce the switch count as well as the
number of gate drivers as the number of voltage levels increases.

The cascaded multilevel inverter has received special attention among the different
topologies for multilevel inverter, due to its modularity and simplicity of control
technique as mentioned by D. Mohan et al. in [2].

 Diode - clamped Multi-level inverter

 Flying - capacitor Multi-level inverter
 Cascade Multi-level inverter

2.2.1.1 DIODE-CLAMPED MULTILEVEL INVERTER

Jimenez et al in [3], have presented a new topology of a diode clamped inverter, in which
the diode is used as the clamping device to clamp the dc bus voltage so as to achieve steps
in the output voltage. The neutral point converter in 1981 was essentially a three-level
diode-clamped inverter. A three-level diode clamped inverter consists of two pairs of
switches and two diodes. Each switch pairs works in complimentary mode and the diodes
used to provide access to mid-point voltage. In a three-level inverter each of the three
phases of the inverter shares a common dc bus, which has been subdivided by two
capacitors into three levels. The DC bus voltage is split into three voltage levels by using
two series connections of DC capacitors, C1 and C2. The voltage stress across each
switching device is limited to Vdc through the clamping diodes DC1 and DC2. It is assumed
that the total dc link voltage is Vdc and mid-point is regulated at half of the dc link
voltage, the voltage across each capacitor is Vdc/2 (Vc1=Vc2=Vdc/2). In a three level diode
clamped inverter, there are three different possible switching states which apply the stair
case voltage on output voltage relating to DC link capacitor voltage rate. For a three-level
inverter, a set of two switches is on at any given time and in a five-level inverter, a set of
four switches is on at any given time and so on. Fig-2.1 shows the circuit for a diode
clamped inverter for a three-level and a five-level inverter. Switching states of the three
level inverter are summarized in table-2.1.

6
 Table-2.1 Switching states in one leg of the three-level diode clamped inverter

Switch Status State Pole Voltage

S1=ON,S2=ON S1'=OFF,S2′=OFF S=+ve Vao=Vdc/2

S1=OFF,S2=ON S1'=ON,S2′=OFF S=0 Vao=0

S1=OFF,S2=OFF S1'=ON,S2′=ON S=-ve Vao=-Vdc/2

(a) (b)

Fig.2.1 Topology of the Diode-Clamped Inverter

(a) three-level inverter, (b) five-level inverter

The line voltage Vab consists of a phase-leg a voltage and a phase-leg b voltage. The
resulting line voltage is a 5-level staircase waveform for three-level inverter and 9-
level staircase waveform for a five-level inverter. This means that an N-level diode-
clamped inverter has an N-level output phase voltage and a (2N-1)-level output line
voltage. In general the voltage across each capacitor for an N level diode clamped
inverter at steady state is Vdc/(N-1). Although each active switching device is required

7
to block only a voltage level of Vdc, the clamping diodes require different ratings for
reverse voltage blocking.

In general for an N level diode clamped inverter, for each leg 2(N-1) switching
devices, (N-1)*(N-2) clamping diodes and (N-1) dc link capacitors are required. By
increasing the number of voltage levels the quality of the output voltage is improved
and the voltage waveform becomes closer to sinusoidal waveform. However,
capacitor voltage balancing will be the critical issue in high level inverters. When N is
sufficiently high, the number of diodes and the number of switching devices will
increase and make the system impracticable to implement. If the inverter runs under
pulse width modulation (PWM), the diode reverse recovery of these clamping diodes
becomes the major design challenge.

Though the structure is more complicated than the two-level inverter, the operation is
straightforward.

(a) (b)

Fig.2.2 Output voltage in three-level diode-clamped inverter (a) leg voltage

(b) output phase voltage

8
2.2.1.2 Operation of DCMLI.

Fig 2.2(a) shows a three-level diode-clamped converter in which the dc bus consists
of two capacitors, C1, C2. For dc-bus voltage Vdc, the voltage across each capacitor is
Vdc/2 and each device voltage stress will be limited to one capacitor voltage level
Vdc/2 through clamping diodes. To explain how the staircase voltage is synthesized,
the neutral point n is considered as the output phase voltage reference point. There are
three switch combinations to synthesize three-level voltages across a and n.

1) Voltage level Van= Vdc/2, turn on the switches S1 and S2.

2) Voltage level Van= 0, turn on the switches S2 and S1′.

3) Voltage level Van= - Vdc/2 turn on the switches S1′, S2′.

Fig. 2.2(b) shows a five-level diode-clamped converter in which the dc bus consists of
four capacitors, C1, C2, C3, and C4. For dc-bus voltage Vdc, the voltage across each
capacitor is Vdc/4 and each device voltage stress will be limited to one capacitor
voltage level Vdc/4 through clamping diodes. Switching states of the five level
inverter are summarized in table-2.2

Table-2.2. Switching states in one leg of the five-level diode clamped inverter

Switch state
Voltage Vao
S1 S2 S3 S4 S1‟ S2‟ S3‟ S4‟

Vao=Vdc 1 1 1 1 0 0 0 0

Vao=Vdc/2 0 1 1 1 1 0 0 0

Vao=0 0 0 1 1 1 1 0 0

Vao=-Vdc/2 0 0 0 1 1 1 1 0

Vao=-Vdc 0 0 0 0 1 1 1 1

To explain how the staircase voltage is synthesized, the neutral point n is considered as
the output phase voltage reference point. There are five switch combinations to synthesize

9
five level voltages across a and n.

1) Voltage level Van= Vdc; turn on all upper switches S1, S2, S3 and S4.

2) Voltage level Van= Vdc/2, turn on the switches S2, S3, S4 and S1′.

3) Voltage level Van= 0, turn on the switches S3, S4, S1′ and S2′.

4) Voltage level Van= - Vdc/2 turn on the switches S4, S1′, S2′, S3′.

5) Voltage level Van= - Vdc; turn on all lower switches S1′, S2′, S3′ and S4′.

Four complementary switch pairs exist in each phase. The complementary switch pair is
defined such that turning on one of the switches will exclude the other from being turned
on. In this example, the four complementary pairs are (S1 –S1′), (S2- S2′), (S3 – S3′), and
(S4 - S4′).

Although each active switching device is only required to block a voltage level of Vdc/ (m-
1), the clamping diodes must have different voltage ratings for reverse voltage blocking.
Using D1′ of Fig. 2.1(b) as an example, when lower devices S₂′- S4′, are turned on,
D1′needs to block three capacitor voltages, or 3Vdc/4, and D1 needs to block Vdc/4.
Similarly, D2 and D2′ need to block 2Vdc/4, and D3 needs to block 3Vdc/4. Assuming that
each blocking diode voltage rating is the same as the active device voltage rating, the
number of diodes required for each phase will be (m-1)*(m-2). This number represents a
quadratic increase in m.

There are some complementary switches and in a practical implementation, some dead
time is inserted between the gating signals and their complements meaning that both
switches in a complementary pair may be switched off for a small amount of time during a
transition. However, for the discussion herein, the dead time will be ignored.

2.2.1.3 Features of Diode clamped MLI

1) High-Voltage Rating Required for Blocking Diodes:

Although each active switching device is only required to block a voltage level of Vdc/ (m-
l), the clamping diodes need to have different voltage ratings for reverse voltage blocking.

Using D1′ of Fig.2.1 (5-level diode clamped inverter) as an example, when all lower
devices, S1′- S4′ are turned on, D1′ needs to block three capacitor voltages, or 3Vdc/4.

10
Similarly, D2 and D2′ need to block 2Vdc/4, and D3 needs to block 3Vdc/4. Assuming that
each blocking diode voltage rating is the same as the active device voltage rating, the
number of diodes required for each phase will be (m - 1) * (m - 2). This number represents
a quadratic increase in m. When m is sufficiently high, the number of diodes required will
make the system impractical to implement.

2) Unequal Device Rating:

In figure-2 it can be seen that switch S1 conducts only during Vao = Vdc, while switch S4
conducts over the entire cycle except during Vao = 0. Such an unequal conduction duty
requires different current ratings for switching devices. When the inverter design is to use
the average duty for all devices, the outer switches may be oversized, and the inner
switches may be undersized. If the design is to suit the worst case, then each phase will
have 2 x (m - 2) outer devices oversized. In comparison with the traditional transformer
coupling multi-pulse converters using six-step operation for each converter, such unequal
conduction duty is indeed an advantageous feature because the six-step operation needs
maximum duty in each device and circulating currents between converters through
transformers.

3) Capacitor Voltage Unbalance:

In most applications, a power converter needs to transfer real power from ac to dc

(rectifier operation) or dc to ac (inverter operation). When operating at unity power factor,
the charging time for rectifier operation (or discharging time for inverter operation) for
each capacitor is different. Such a capacitor charging profile repeats every half cycle, and
the result is unbalanced capacitor voltages between different levels. The voltage
unbalance problem in a multilevel converter can be solved by several approaches, such as
replacing capacitors by a controlled constant dc voltage source such as pulse-width
modulation (PWM) voltage regulators or batteries. The use of a controlled dc voltage will
result in system complexity and cost penalties. With the high power nature of utility
power systems, the converter switching frequency must be kept to a minimum to avoid
switching losses and electromagnetic interference (EMI) problems. When operating at
zero power factor, however, the capacitor voltages can be balanced by equal charge and
discharge in one-half cycle. This indicates that the converter can transfer pure reactive
power without the voltage unbalance problem.

11
2.2.1.4 Advantages and Disadvantages of DCMLI

Advantages:

1. All of the phases share a common dc bus, which minimizes the capacitance
requirements of the converter. For this reason, a back-to-back topology is not only
possible but also practical for uses such as a high-voltage back-to-back inter-connection or
an adjustable speed drive.

2. The capacitors can be pre-charged as a group.

3. Efficiency is high for fundamental frequency switching.

4. When the number of levels is high enough, harmonic content will be low enough to
avoid the need for filters.

Disadvantages:

1. Real power flow is difficult for a single inverter because the intermediate dc levels will
tend to overcharge or discharge without precise monitoring and control.

2. The number of clamping diodes required is quadratically related to the number of levels
[1], which can be cumbersome for units with a high number of levels.

2.2.2. FLYING CAPACITOR MULTILEVEL INVERTER

Palanivel et al in [4], have discussed a capacitor clamped inverter alternatively known as

flying capacitor was proposed in 1992. The structure of this inverter is similar to that of
the diode- clamped inverter except that instead of using clamping diodes, the inverter uses
capacitors in their place. The flying capacitor involves series connection of capacitor
clamped switching cells. This topology has a ladder structure of dc side capacitors, where
the voltage on each capacitor differs from that of the next capacitor. The voltage
increment between two adjacent capacitor legs gives the size of the voltage steps in the
output waveform. Figure 2.3 shows the three-level and five-level capacitor clamped
inverters respectively.

2.2.2.1. Operation of FCMLI.

In the operation of flying capacitor multi-level inverter, each phase node (a, b, or c) can be
connected to any node in the capacitor bank (V3, V2, V1). Connection of the a-phase to

12
positive node V3 occurs when S1 and S2 are turned on and to the neutral point voltage
when S2 and S1′ are turned on. The negative node V1 is connected when S1′ and S2′are
turned on. The clamped capacitor C1 is charged when S1 and S1′ are turned on and is
discharged when S2 and S2′ are turned on. The charge of the capacitor can be balanced by
proper selection of the zero states. In comparison to the three-level diode-clamped
inverter, an extra switching state is possible. In particular, there are two transistor states,
which make up the level V3. Considering the direction of the a-phase flying capacitor
current Ia for the redundant states, a decision can be made to charge or discharge the
capacitor and therefore, the capacitor voltage can be regulated to its desired value by
switching within the phase. As with the three-level flying capacitor inverter, the highest
and lowest switching states do not change the charge of the capacitors. The two
intermediate voltage levels contain enough redundant states so that both capacitors can be
regulated to their ideal voltages.

(a) (b)

Fig.2.3 Capacitor-clamped multilevel inverter circuit topologies, (a) 3-level inverter

(b) 5-level inverter.

Similar to the diode clamped inverter, the capacitor clamping requires a large number of
bulk capacitors to clamp the voltage. Provided that the voltage rating of each capacitor

13
used is the same as that of the main power switch, an N level converter will require a total
of (N-1) * (N-2) / 2 clamping capacitors per phase in addition to the (N-1) main dc bus
capacitors.

Unlike the diode-clamped inverter, the flying-capacitor inverter does not require all of the
switches that are on (conducting) in a consecutive series. Moreover, the flying-capacitor
inverter has phase redundancies, whereas the diode-clamped inverter has only line-line
redundancies [1, 3]. These redundancies allow a choice of charging/discharging specific
capacitors and can be incorporated in the control system for balancing the voltages across
the various levels.

The voltage synthesis in a five-level capacitor-clamped converter has more flexibility than
a diode-clamped converter. Using Fig. 2.3(b) as the example, the voltage of the five-level
phase-leg „a‟ output with respect to the neutral point n (i.e. Van), can be synthesized by the
following switch combinations.

1) Voltage level Van= Vdc/2, turn on all upper switches S1 - S4.

2) Voltage level Van= Vdc/4, there are three combinations.

a. Turn on switches S1, S2, S3 and S1′. {(Van= Vdc/2) of upper C4‟s (-Vdc/4) of C1‟s}.

b. Turn on switches S2, S3, S4 and S4′. {(Van= 3Vdc/4) of upper C3‟s (-Vdc/2) of C4‟s}.

c. Turn on switches S1, S3, S4 and S3′. {(Van= Vdc/2) of upper C4‟s (-3Vdc/4) or C3‟s
(+Vdc/2) of upper C2‟s).

3) Voltage level Van= 0, turn on upper switches S3, S4, and lower switch S1′, S2′.

4) Voltage level Van= -Vdc/4, turn on upper switch S1 and lower switches S1′, S2′and S3′.

5) Voltage level Van= -Vdc/2, turn on all lower switches S1′, S2′, S3′ and S4′.

2.2.2.2 Features of FCMLI

The major problem in this inverter is the requirement of a large number of storage
capacitors. Provided that the voltage rating of each capacitor used is the same as that of
the main power switch, an m-level converter will require a total of (m - 1) x (m - 2)/2
auxiliary capacitors per phase leg in addition to (m - 1) main dc bus capacitors. With the
assumption that all capacitors have the same voltage rating, an m-level diode-clamp

14
inverter only requires (m - 1) capacitors.

In order to balance the capacitor charge and discharge, one may employ two or more
switch combinations for middle voltage levels (i.e., 3Vdc/4. Vdc/2, and Vdc/4) in one or
more fundamental cycles. Thus, by proper selection of switch combinations, the flying-
capacitor multilevel converter may be used in real power conversions. However, when it
involves real power conversions, the selection of a switch combination becomes very
complicated, and the switching frequency needs to be higher than the fundamental
frequency. In summary, advantages and disadvantages of a flying capacitor multilevel
voltage source converter are as follows.

2.2.2.3 Advantages and Disadvantages of (FCMLI).

Advantages

Compared to the diode-clamped inverter, this topology has several unique and attractive
features as described below:

 Added clamping diodes are not needed.

 It has switching redundancy within the phase, which can be used to balance the flying
capacitors so that only one dc source is needed.

 The required number of voltage levels can be achieved without the use of the
transformer.

 This assists in reducing the cost of the converter and again reduces power loss.

 Unlike the diode clamped structure where the series string of capacitors share the
same voltage, in the capacitor-clamped voltage source converter the capacitors within
a phase leg are charged to different voltage levels.

 Real and reactive power flow can be controlled.

 The large number of capacitors enables the inverter to ride through short duration
outages and deep voltage sags.

Disadvantages

 Converter initialization i.e., before the converter can be modulated by any modulation

15
 scheme the capacitors must be set up with the required voltage level as the initial
charge. This complicates the modulation process and becomes a hindrance to the
operation of the converter.

 Control is complicated to track the voltage levels for all of the capacitors.

 Pre-charging all of the capacitors to the same voltage level and start-up are complex.

 Switching utilization and efficiency are poor for real power transmission.

 Since the capacitors have large fractions of the dc bus voltage across them, rating of
the capacitors are a design challenge.

 The large numbers of capacitors are both more expensive and bulky than clamping
diodes in multilevel diode-clamped converters.

 Packaging is also more difficult in inverters with a high number of levels.

2.2.3 CASCADED MULTI-LEVEL INVERTER

Nedungatt et al [5], have presented a new topology of a cascaded multilevel inverter or

series H-bridge inverter. This series H-bridge inverter has been introduced in 1995. Since
then, the CMI has been utilized in a wide range of applications. With its modularity and
flexibility, the CMI shows superiority in high-power applications, especially shunt and
series connected FACTS controllers. The CMI synthesizes its output nearly sinusoidal
voltage waveforms by combining many isolated voltage levels. By adding more H-bridge
converters, the amount of Var can simply increase without redesign the power stage, and
build-in redundancy against individual H-bridge converter failure can be realized. A series
of single-phase full bridges makes up a phase for the inverter. A three-phase CMI
topology is essentially composed of three identical phase legs of the series-chain of H-
bridge converters, which can possibly generate different output voltage waveforms and
offers the potential for AC system phase-balancing. This feature is impossible in other
VSC topologies utilizing a common DC link. Since this topology consists of series power
conversion cells, the voltage and power level may be easily scaled. The dc link supply for
each full bridge converter is provided separately, and this is typically achieved using
diode rectifiers fed from isolated secondary windings of a three-phase transformer. Phase-
shifted transformers can supply the cells in medium-voltage systems in order to provide
high power quality at the utility connection.

16
 (a) (b) (c)

Fig.2.4 Single phase structures of Cascaded inverter (a) 3-level, (b) 5-level, (c) 7-
level

2.2.3.1 Operation of CMLI.

The converter topology is based on the series connection of single-phase inverters with
separate dc sources. Fig. 2.5 shows the power circuit for one phase leg of a three-level,
five- level and seven-level cascaded inverter. The resulting phase voltage is synthesized
by the addition of the voltages generated by the different cells. In a 3-level cascaded
inverter each single-phase full-bridge inverter generates three voltages at the output: +Vdc,
0, -Vdc (zero, positive dc voltage, and negative dc voltage). This is made possible by
connecting the capacitors sequentially to the ac side via the power switches. The resulting
output ac voltage swings from -Vdc to +Vdc with three levels, -2Vdc to +2Vdc with five-
level and -3Vdc to +3Vdc with seven-level inverter. The staircase waveform is nearly
sinusoidal, even without filtering.

For a three-phase system, the output voltage of the three cascaded converters can be
connected in either wye (Y) or delta (Δ) configurations. For example, a wye-configured 7-
level converter using a CMC with separated capacitors is illustrated in the fig. 2.6.

17
 Fig.2.4 Three-phase 7-level cascaded multilevel inverter (Y-configuration)

2.2.3.2 Features of CMLI

For real power conversions, (ac to dc and dc to ac), the cascaded-inverter needs separate
dc sources. The structure of separate dc sources is well suited for various renewable
energy sources such as fuel cell, photovoltaic, and biomass, etc.

Connecting separated dc sources between two converters in a back -to-back fashion is not
possible because a short circuit will be introduced when two back -to-back converters are
not switching synchronously.

In summary, advantages and disadvantages of the cascaded inverter based multilevel

voltage source converter can be listed below.

2.2.3.3 Advantages and Disadvantages of CMLI.

Advantages

 The regulation of the DC buses is simple.

 Modularity of control can be achieved. Unlike the diode clamped and capacitor
clamped inverter where the individual phase legs must be modulated by a central
controller, the full-bridge inverters of a cascaded structure can be modulated
separately.

 Requires the least number of components among all multilevel converters to achieve

18
 the same number of voltage levels.

 Soft-switching can be used in this structure to avoid bulky and lossy resistor-
capacitor-diode snubbers.

Disadvantages

 Communication between the full-bridges is required to achieve the synchronization of

reference and the carrier waveforms.

 Needs separate dc sources for real power conversions, and thus its applications are
somewhat limited.

2.3 Switch Reduction Topologies in MLI

Multilevel inverter does have some disadvantages. One of the drawbacks is the need of
large number of power semiconductor switches. Even though the switched required are of
low rating, each power switch requires proper isolation and gate driver circuit. A lot of
number of researcher has proposed different topology for different level of multilevel
inverter.

2.3.1 Three Level MLI

Lakshmi et al. in [6] have presented a new topology of a hybrid capacitor-clamp cascade
multilevel converter that was derived from two popular topologies. The new concept of
the converter was based on the connection of multiple three-level capacitor-clamp
converter modules with different dc bus voltages. A detailed example of HCCMC was
given. The proposed converter was also verified by computer simulation using MATLAB-
Simulink. Simulation results were also presented.

Ahmed et al. in [7] have proposed the design and operational principles of a three-phase
three-level nine switch voltage source inverter. The proposed topology consisted of three
bi-directional switches inserted between the source and the full-bridge power switches of
the classical three-phase inverter. To validate the proposed topology, both simulation and
analysis have been performed. In addition, a prototype has been designed, implemented
and tested. Selected simulation and experimental results have been provided [8].

19
2.3.2 Five Level MLI

Chiasson et al. in [9] have discussed a 3-phase 5-level cascade multilevel inverter to be
used as a drive for a PM traction motor using a single dc power source. The 5-level
inverter consisted of a standard 3-leg inverter (one leg for each phase) and an H-bridge in
series with each inverter leg, which used a capacitor as a dc source. It was shown that one
could simultaneously maintain the regulation of the capacitor voltage while achieving an
output voltage waveform which was 25% higher than that obtained using a standard 3-leg
inverter by itself.

Agelidis et al. in [10] have proposed the selective harmonic elimination of a new family of
multilevel inverters using genetic algorithms. The GA technique finds the optimal solution
set of switching angles. The new family of the 5-level inverter has a main H bridge
inverter, two auxiliary switches and two dc sources. Experimental implementation proved
the effectiveness of both the new inverter topology and the presented GA technique.

Corzine et al. in [11] have presented a study for a cascaded H-bridge multilevel direct
torque control (DTC) induction motor drive. In this case, symmetrical and asymmetrical
arrangements of five- and seven-level H-bridge inverters were compared in order to find
an optimum arrangement with lower switching losses and optimized output voltage
quality. The carried-out experiments showed that an asymmetrical configuration provides
nearly sinusoidal voltages with very low distortion, using less switching devices.
Moreover, torque ripples were greatly reduced.

Yuan et al. in [12] have described a five-/nine-level twelve-switch inverter for three-phase
high-speed electric machines having a low per-unit leakage reactance. Operational and
design details were described for the NPC-CI inverter using a three-limb inductor core,
including practical considerations for the inverter construction and operation, 480 V/208
V inductor mass comparison between six- and twelve-switch topologies, natural voltage
balancing of the split capacitor dc link, and voltage stresses of the freewheel diodes.
Improvements in machine performance were illustrated using two experimental test rigs:
an unloaded 18 000-r/min 15-HP induction machine to illustrate improved harmonic
quality when operating with a limited switching frequency and a high fundamental output
frequency, and a loaded 2-HP utility speed induction machine to demonstrate transient
performance.

20
Tolbert et al. in [13] have discussed an analytical algebraic method based on formulating
the line-voltage THD of multilevel inverters with unequal dc sources. This method, which
was general and applicable to each number of switching angles, was implemented to a
five-level inverter with staircase waveform as a case study. The implementing process of
this method could be easily repeated for each number of levels. The accuracy of the
proposed method was illustrated in comparison with the approximate method. Some
advantages of the extracted formulas of line-voltage THD were simplicity and rapidity in
calculations, considering all harmonics and the possibility of finding optimal switching
angles analytically. Experimental results were presented to validate the theory.

Patel et al. in [14] have proposed a multilevel inverter that has been conceptualized to
reduce component count, particularly for a large number of output levels. It comprised
floating input dc sources alternately connected in opposite polarities with one another
through power switches. Each input dc level appeared in the stepped load voltage either
individually or in additive combinations with other input levels. The working principle of
the proposed topology was demonstrated with the help of a single-phase five-level
inverter. The topology was investigated through simulations and validated experimentally
on a laboratory prototype. An exhaustive comparison of the proposed topology was also
made against the classical cascaded H-bridge topology.

Mckenzie et al. in [15] have proposed a new algorithm for asymmetric source
configuration suitable for CCS-MLI. A control scheme was also proposed for equal load
sharing in five-level topology. Investigations were made for possibility of equal load
sharing in higher level structures and fundamental frequency switching of switches
bearing higher voltage stresses. Various concepts were verified with simulations and
experimental studies.

Sun et al. in [16] have implemented cascaded multilevel inverter through the series
connection of single-phase modular power bridges. The practicality and performance of
the presented modular implementation concepts have been confirmed through the close
match between simulation and experimental results obtained using a modular cascaded
five-level inverter prototype [17].

2.4 HARMONIC ELIMINATION IN MLI

The issue of elimination of harmonics in the multilevel circuit is a promising challenge in

21
industries. According to Duffey et al. in [18] the update IEEE519 standard limit of Total
Harmonic Distortion (THD) on the output voltage of the converter circuit for voltage ≤69
V should be maintained within a limit of 5%. The harmonic elimination in multilevel
inverter can easily be achieved by making use of suitable switching schemes rather than
using filters. The conventional switching strategies of inverter can be classified under
three main group, mentioned below:

(i) Sinusoidal Pulse Width Modulation (SPWM)

(ii) Selective Harmonic Elimination Pulse Width Modulation (SHE-PWM)

(iii) Space vector Pulse Width Modulation (SV-PWM)

2.4.1 Control Scheme

The multilevel inverter efficiency mainly depends on parameters such as losses due to
switching of the solid-state devices and harmonics which are in turn depended on the
modulation strategies used to control the inverter. Fig 2.1 depicts the various control
schemes of a multilevel inverter

Mohammadreza [19] performed the comparison of different inverter topologies on the

basis of their weight, cost, power loss and harmonic content, which is summarized in
Table 2.1.
Multilevel Inverter control Schemes

Fundamental Switching High Switching

Frequency Frequency

SV-PWM SHE-PWM SV-PWM SHE-PWM SPWM

Fig.2.5 Control scheme for MLI

22
Farokhnia et al. in [20] have proposes a modified SHE-PWM technique to extend the
modulation range of the standard SHE-PWM of multilevel converters. An efficient
optimization/minimization technique assisted with GA is applied to find the switching
angles. The analytical and simulation results are verified based on a 30- kVA
experimental setup. Effectiveness of the proposed SHE-PWM technique is
demonstrated under various operational scenarios.

Farokhnia et al. in [21] have proposed a switching strategy based on minimization of

total harmonic distortion (MTHD) for the cascaded multilevel inverter to reduce the
THD. They considered the alterable DC sources instead of constant DC sources.
Experimental result verifies both the theoretical and simulation result.

Dahidah et al.in [22] have provides a comprehensive review of the SHE-PWM

modulation technique, aimed at its application to multilevel converter. This review
focused on various aspects of multilevel SHE-PWM, including different problem
formulations, solving algorithms, and implementation in various multilevel converter
topologies. It is found that, SHE-PWM is an attractive modulation technique for a
wide range of low switching frequency applications owing to its unique features.

Harish et al. in [23] has proposed new topology. The proposed topology constitutes
the conventional three-phase bridge with three bidirectional switches. PWM
technique is Employed and showed high flexibility and simplicity in control.

Podder et al.in [24] have proposed a modified carrier to generate PWM signal. In this
paper, the original triangular carrier signal is divided into three equal parts. Proposed
PWM method reduces THD of the output voltage of inverter up to 5.8% than the
traditional triangular carrier based PWM.

Prakash et al. in [25] have proposed a new multilevel inverter topology. The proposed
method is well suited for a high-power application and it built with three dc sources
and six Switches. Multi carrier PWM technique is used for sine wave generation.
MATLAB/SIMULINKTM model is designed for seven level proposed topology.

Kurian et al. in [26] have proposed a four switch three phase multilevel inverter for
renewable energy sources. A SPWM is used to control the switching of the four
switches. A simulation result is evaluated and verified with prototype. Colak et al. in
[27] have been reviewed the most common multilevel inverter topologies and control

23
schemes. Many new hybrid topologies can be designed through the combinations of
three main MLI topologies. Besides the combination of topologies, the trade-offs in
MLI structures can be dealt by using AH-MLIs that is formed using different DC
source levels in inverter cells. hybrid modulation methods have been proposed that
provide to get higher power cells switched at low frequency and low power cells
switched with high frequency.

2.5 INFERENCES DRAWN OUT OF LITERATURE REVIEW

The following inferences have been drawn after going through the numerous
literatures:

 Very little work has been reported in regard of application of multilevel

inverter with equal and unequal dc voltage source for H-bridge from
renewable zero pollution energy resources such as wind, solar, bio and
geothermal.

 MATLABTM/SIMULINKTM have emerged as popular tools and are widely

used for modeling, control and simulation purpose of various electrical system
including the component of solar Inverter and under a verity of operating
condition in high power application isolated bidirectional dc-dc converters are
used because they proved galvanic isolation by transformer.

 Various multilevel inverter structures such as diode-clamped, flying capacitor

and cascaded H-bridge inverter have developed but the THD is not minimized
to get ripple free output power.

 To minimize the THD, different modulation schemes such as SPWM

(Sinusoidal Plus Width Modulation), SHEPWM (Selective Harmonics
Sinusoidal Plus Width Modulation), and SVPWM (Space Vector Sinusoidal
Plus Width Modulation) have developed and implemented on cascaded H-
bridge Inverters.

 Switching angles can be calculated offline and stored in lookup table. But for
some operating point might be missing. This also involves large memory space
for programming code.

 The performance of cascaded multilevel inverter is compared based on

24
 computation of switching angles using GA, PSO as well as conventional
Newton Raphson method.

 To reduce the number of dc sources, different multilevel structures have been

proposed.

 To get the 3-phase output power, multilevel three phase inverters have been
proposed by connecting three single phase multilevel inverters.

 To minimize the switches and dc sources, asynchronous and synchronous

multilevel inverters have been developed.

 Multilevel inverters with unidirectional and bidirectional switches have been

developed.

 Various controllers µc, µp, DSP processor such as dsPIC and FPGA are used
for generating firing pulses.

2.6 SUMMARY

In this chapter, a literature review of several international journals such as IEEE, IET,
and IETE etc., for various multilevel inverter topologies, dc to dc converters,
controllers and their applications have been done. After studying these papers, some
inferences have been drawn out such as high THD in output power, need of solid state
control, green power from renewable resources to power multilevel inverters and
hardware implementation issues.

25
 CHAPTER 3

PROPOSED WORK

3.1 PROBLEM DEFINITION

Based on the exhaustive literature review, the inferences drawn out of the
analysis of the literature and the scope of investigations, the investigator proposes the
harmonic elimination in a multilevel inverter with reduced number of switch and dc
voltage sources.

3.2 OBJECTIVES

The main objectives of the research are as follows:

 To minimize the number of static switches and reduce the switching losses.

 To minimize the number of sources.

 To reduce the output THD less than <5% (as per IEEE519).

 To validate the experimental results with the simulation results.

3.3 PROPOSED WORK

The demand of quality power is increasing continuously. The problem of global

warming and rate of decrease of non-renewable energy sources are increasing day by
day. Hence renewable energy sources such as solar, fuel cell, Magneto hydro
Dynamic (MHD), geothermal are the best alternatives to solve the problem of
environmental issue and increasing demand of energy. The output of these resources
is dc, therefore to connect these resources to the grid, multilevel inverter is key
device. But the output of multilevel inverter has power quality issues such as
harmonic generation and notching due to conversion of dc-ac and high number of
switch. The recent multilevel inverters have many switches and more harmonics
content in output supply. The aim of this thesis is to develop a seven level Inverter
with reduced number of switches and minimize the harmonics distortion in generated
power. The inverters which produce which produce an output voltage or a current. In
high-power and high-voltage applications these two- level inverters however have
some limitations in operating at high frequency mainly due to switching losses and

26
constraints of device rating. This is where multilevel inverters are advantageous.
Increasing the number of voltage levels in the inverter without requiring higher rating
on individual devices can increase power rating. The unique structure of multilevel
voltage source inverters‟ allows them to reach high voltages with low harmonics
without the use of transformers or series-connected synchronized-switching devices.
The harmonic content of the output voltage waveform decreases significantly.

 To design and analysis the seven level inverter using MATLAB/SIMULINK.

 Collecting information about simulation work and requisite theory /formulae.

 Simulation of the seven level inverter, study of the obtained simulated results
and analysis (THD factor, FFT analysis).

 Application of the inverter. Modeling of the circuit and harmonic elimination.

 To compare the result with latest literature.

3.3.1 HARMONIC ELIMINATION

Several modulation techniques have been discussed in literature for minimizing the
switching losses and to eliminate the harmonic contents.

3.3.1.1 SELECTIVE HARMONIC ELIMNATION (SHE)

The selective harmonic elimination (SHE) technique uses fundamental switching

frequency modulation strategy for obtaining the desired output. In this method the
switching angles are chosen in such a way, that it eliminates the selective harmonics
in the output voltage. However, in a three-phase system, as the triplen harmonics such
as 3rd ,9th etc. get cancelled in a line–to-line voltage, the selective lower order
harmonics such as 5th,7th ,11th, and 13th can be chosen as target harmonics for
elimination. For a single-phase system the triplen harmonics have to be considered for
harmonic elimination. The Fourier series analysis is used to obtain the amplitude of
the output voltage waveform. Further, the output voltage equation is synthesized in
such as:

∑ (4.1)

Where, N is equal to 7 for 15-level inverter.

27
 Where N= 1, 3, 5, 7, 9, 11……………….

Vdc is the maximum dc voltage of the multilevel inverter. The firing angles
must fulfil the following limits.

(4.2)

The main objective of selective harmonic elimination technique is to find the firing angles
. So that fundamental component of output is adjusted to desired
amplitude and non-triple odd harmonic components can be eliminated. There are no triple
order harmonics in 3-phase system. Mathematically, for a 3-phase system with
symmetrical topology following set of different order harmonics equations are
formulated.

∑ (4.3)

∑ (4.4)

∑ (4.5)

∑ (4.6)

∑ (4.7)

Where M is known as modulation index which is formulated as:

28
 (4.8)

3.3.1.2 TOTAL HARMONIC DISTORTION (THD)

Step 1 Evaluate the fitness function (THD)

√( ) (4.9)

Step 2 Check the constraints of eq. (4.2)

Step 3 Choose the parent chromosomes.

Step 4 Generate the new offspring using crossover and mutation.

Step 5 Check if termination condition (the maximum number of iterations) is reached.

Otherwise go to step 2

Step 6 If optimized switching angles are obtained, end the problem.

The diagram of the proposed work is shown in Fig.3.1. It consists of seven level
inverter, three dc sources with load.

Fig.3.1 Diagram of the Proposed Model

29
3.3.1.3 BLOCK DIAGRAM

H-BRIDGE
AC LLLOAD
RECTIFIER MULTILEVEL
SUPLLLY
INVERTER

ISOLATER AND
DRIVER

MICROCONTROLLER
PWM GENERATION
CIRCUIT

POWER SOURCE

Fig 3.2 Block Diagram of Seven Level Inverter

3.4 SUMMARY

In this chapter, objectives of proposed work have been discussed such as to develop
MATLAB/SIMULINK models for seven level inverter with R-Load, RL-Load. The
problems are formulated and the diagram of proposed system is also discussed.

30
 CHAPTER 4

METHODOLOGY

4.1 IMPLEMENTATION STRATEGY

The proposed model of seven level inverter will be implemented using the following
steps:

 Design MATLAB/SIMULINK model of multilevel three phase inverters by

taking R and RL load.

 Validating the experimental results of proposed multilevel inverter with

simulation results.

 Compare the proposed work results with another system investigated in latest
literature.

Table 4.1 Comparison of THD with Reference Papers

SL.NO. Reference and Author No of Switch THD Proposed THD

1 MOHAN et. al [2] 8 28.96 19.98

2 LAKSHMI et. al [6] 9 23.82 12.06

This can be observed from the figure following which are generated by
simulating a single phase H-Bridge Multilevel inverter using MATLAB
SIMULINK for Seven level inverter and compared the THD which are Tabulated
below. Input voltage 100V for each H-Bridge. For R load value is 100Ω and with RL
load value is R=20Ω, L=100*10-3 H.

31
4.2 SIMULINK MODEL OF DIFFERENT MULTI-LEVEL INVERTER

Fig.4.1. Simulation of Three Level Inverter

Fig.4.2 Simulation of Five Level Inverter

32
 Fig.4.3 Simulation Model of Seven Level Inverter

Fig 4.4 Output Waveform of Seven Level Inverter

Fig 4.5 PWM Circuit of Seven Level Inverter Used in MATLAB

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Fig.4.6 PWM Waveform of 7-Sevel Inverter

Fig 4.7 FFT Analysis

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Fig.4.8 Simulation of Nine Level Inverter

Fig.4.9 Simulation of Eleven Level Inverter

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Fig.4.10 Simulation of Thirteen Level Inverter

Fig.4.11 Simulation of Fifteen Level Inverter

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 TABLE 4.2 THD ANALYSIS WITH R-LOAD

SL NO LEVEL THD (%)

1 THREE 54.42

2 FIVE 19.98

3 SEVEN 12.06

4 NINE 10.41

5 ELEVEN 8.86

6 THIRTEEN 8.10

7 FIFTEEN 7.11

Fig.4.12 Simulation of Three Level Inverter with RL-Load

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Fig.4.13 Simulation of Five Level Inverter with RL-Load

Fig.4.14 Simulation of Seven Level Inverter with RL-Load

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Fig.4.15 Simulation of Nine Level Inverter with RL-Load

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Fig.4.16 Simulation Of Eleven Level Inverter With RL-Load

40
Fig.4.17 Simulation Of Thirteen Level Inverter With RL-Load

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 Fig.4.18 Simulation of Fifteen Level Inverter with RL-Load

TABLE 4.3 THD ANALYSIS OF RL-LOAD

SL NO LEVEL THD (%)

1 THREE 54.56
2 FIVE 20.01
3 SEVEN 12.06
4 NINE 10.45
5 ELEVEN 13.03
6 THIRTEEN 8.13
7 FIFTEEN 7.13

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4.3 Hardware components

Table 4.4 Hardware Components Used

SL no Name of component Specification

1 MOSFET IRF840
2 Step down transformer 230/12V
3 Diode IN4007
4 Capacitors 1000µF, 100nF
5 Zener Diode IN3997
6 Resistors 1KΩ, 100KΩ
7 Microcontroller DsPIC 30F2010
8 Voltage regulator 7805
9 Opto coupler TLP250

MOSFET (IRF840)

This N-channel enhancement mode silicon gate power field effect transistor is an
advanced power MOSFET. All of these power MOSFET for applications such as
switching regulators, switching converters, motor drives. This MOSFET features are 8A,
500V, rDS(ON) = 0.850Ω and high input impedance.

Step down transformer (230/12V)

In step down transformer in which the secondary winding is more than primary winding.
Due to this windings it able to step down the voltage. A transformer changes electricity
from high to low voltage or low to high voltage with constant frequency. Step down 230V
AC to 12V AC with a maximum of 1A current.

MICROCONTROLLER (DsPIC 30F2010)

In this project, microcontroller (Dspic 30F2010) is utilized to generate gete pulse, for the
MOSFETS.
Description about the microcontroller is given below:

 Modified Harvard architecture

 C compiler optimized instruction set architecture

43
 84 base instructions with flexible addressing modes
 24-bit wide instruction, 16-bit wide data path
 12 Kbytes on-chip Flash program space
 512 bytes on-chip data RAM
 1 Kbyte non-volatile data EEPROM
 16*16-bit working register array
 Up to 30 MIPs operation:-DC to 40 MHz external clock input, 4 MHz-10 MHz
oscillator input with PLL active (4x, 8x, 16x )
 27 interrupt sources
 6 PWM output channels
 10-bit Analog to Digital Converter with 500 Ksps (for 10-bit A/D) conversion rate, six
input channels, Conversion available during sleep and idle
 Programmable brown-out detection and reset generation
Pin Diagram of the controller is presented in figure 4.19 and Pin description is given in
table 4.5.

Fig.4.19 Pin Diagram of Microcontroller

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 Table 4.5 Pinout I/O Description

Pin Name Pin type Buffer type Description

AN0-AN5 I Analog Analog input channels
AVDD P P Positive supply for analog module
AVSS P P Ground reference for analog module
FLTA I ST PWM fault A input
PWM1L O - PWM 1 low output
PWM1H O - PWM 1 high output
PWM2L O - PWM 2 low output
PWM2H O - PWM 2 high output
PWM3L O - PWM 3 low output
PWM3H O - PWM 3 high ouput
VDD P - Positive supply for logic and I/O pins.
VSS P - Ground reference for logic and I/O pins.
VREF+ I Analog Analog voltage reference (low) input
VREF- I Analog Analog voltage reference (low) input

Driver Circuit:
The fundamental motivation behind driver circuit (is to improve the switching voltage for
the MOSFET or any switching device. And also it gives the isolation between the power
circuit and the microcontroller circuit. In this project TLP250 opto-coupler is used, which
isolates the power circuit with the microcontroller circuit. Signal from microcontroller is
given to the driver circuit. Figure 4.20 shows the driver circuit for the experimental setup.

Fig.4.20 Driver Circuit

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4.4 Hardware setup

To verify the simulation results, a multilevel voltage source converter (VSC), which can
be used for 7level, using cascaded converters with separated DC sources, as shown in 4.2
is used as a hardware prototype. Seven MOSFET modules are used as the main switches,
which are connected in full-bridge converter configuration. Each power stage is supplied
by a variable DC source. In this level seven MOSFET using, four MOSFET for main
circuit and three MOSFET for auxiliary circuit. The main switch is S1, S2, S3, S4 and
auxiliary switch are SA1, SA2, SA3.The PWM generates by the help of microcontroller
and the pin number is 22, 23, 24, 25 and 26. The input voltage is Vin=24V.

Fig 4.21 Experimental setup for seven level inverter

46
 Table 4.6 Switching scheme for seven level 7-switch topology

SL no. SA1 SA2 SA3 S1 S2 S3 S4 Output voltage

1 OFF OFF ON ON OFF OFF ON +3Vdc
2 OFF ON OFF ON OFF OFF ON +2Vdc
3 ON OFF OFF ON OFF OFF ON +Vdc
4 OFF OFF OFF OFF OFF OFF OFF 0
5 ON OFF OFF OFF ON ON OFF -Vdc
6 OFF ON OFF OFF ON ON OFF -2Vdc
7 OFF OFF ON OFF ON ON OFF -3Vdc

4.5 Experimental Result

Fig 4.22 shows the experimental results of 7-level cascaded inverter respectively.

Fig.4.22 Waveform of 7 level inverter

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Fig.4.23. Gate Pulses for MOSFET Pin 22, 23, 24 and 25

Fig.4.24. Gate Pulses for MOSFET Pin 23, 24, 25 and 26

48
SUMMARY

In this chapter design of multilevel inverter discussed in detail, relevant waveforms are
presented and analysed. And fig 4.21 is the experimental setup of seven level inverter.
Form this analysis it can be concluded that multilevel inverters offer a low total harmonic
distortion and high efficiency. Multilevel inverters are suitable for high voltages and high
current application and also have higher efficiency because the devices can be switched at
a lower frequency.

49
 CHAPTER 5

CONCLUSIONS AND FUTURE SCOPE

The different aspects of seven level inverter have been described. Conclusions of the
report are presented here along with the scope for future research as an extension of the
work pursued in this dissertation.

5.1 CONCLUSION

 The 7-level inverter just seven switches is successfully introduced the circuitry
using MATLAB/ SIMULINK and observed a seven level waveform.
 In Simulink result of seven level inverter is Vout=300V and hardware result of
seven level inverter is Vp-p=38.6.
 Performance is assessed through harmonic analysis and total harmonic distortion
(THD) of voltages and load side are achieved within 12.06 %.

50
5.2 FUTURE WORK

Although this dissertation has covered most of the interesting issues and challenges of the
Cascaded multi-level inverter induction motor drives, additional work has been left for
future research.

 The important challenge in the cascaded multi-level induction motor drive to

develop a fault protection scheme of different semiconductor devices and passive
devices and passive components.
 The redundancy of the cascaded multi-level inverter induction motor drives. Due
to the identical HBBBs used in the CMC, the N+1 rule applied, where N is the
number of HBBBs per phase.
 the three-phase experimentation procedure is testing the converter on an induction
motor drive using conventional torque and speed control structures. Decisions on
the switching frequency and the capacitor dimensioning are to be reached and the
implementation software still is to be built.
 In future work is towards the implementation of nine level, eleven level, thirteen
level and fifteen level. The level of output increases, sinusoidal waveform will be
obtained and reduce the THD.

51
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