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Interim Report

The document summarizes an interim project report on the design of a common source LNA with inductive degeneration in TSMC 65nm technology. The student aimed to achieve targeted specifications including a gain of 20dB at 5.5GHz, noise figure of 1.5dB, IP1dB of -10dBm, and S-parameters within certain ranges. The achieved specifications based on the design are reported, with most being close to but not meeting the targets. Further optimization is needed to improve accuracy.

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38 views8 pages

Interim Report

The document summarizes an interim project report on the design of a common source LNA with inductive degeneration in TSMC 65nm technology. The student aimed to achieve targeted specifications including a gain of 20dB at 5.5GHz, noise figure of 1.5dB, IP1dB of -10dBm, and S-parameters within certain ranges. The achieved specifications based on the design are reported, with most being close to but not meeting the targets. Further optimization is needed to improve accuracy.

Uploaded by

VineethMourya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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ELL833 : CMOS RFIC Design

Interim Project Report


Submitted by: Tenin K Sen (2022EEN2124)

Design of common source LNA with inductive degeneration

Targeted Specifications
Specifications Targeted Value
Technology TSMC 65 nm
Supply 1.2 V
Gain (Voltage Gain) 20 dB
Frequency 5.5 GHz
Power 3.5 mW
Noise Figure 1.5 dB
IIP3/OIP3 -1/12 dBm
IP1dB/OP1dB -10/10 dBm
S11 -20 dB
S12 -10 dB
S21 20 dB
S22 -10 dB

Schematic diagram of the circuit with ADEL window


DC Operating points

Note that all the MOSFETs are biased in the region 2 (Saturation).
Achieved Gain and Frequency
My aim is to design the circuit to have a gain of 20 dB at 5.5 GHz. I achieved a gain of 18.81 dB at 5.49 GHz.

I need to further optimize the design to get more accuracy.

I kept the targeted total power consumption as 4 mW and achieved about 4.46 mW. This also needs further
optimization.

Noise Figure
My aim is to design the circuit to have a noise figure of 20 dB at 5.5 GHz. I achieved a noise figure of 5.67 dB
at 5.49 GHz. I need to further optimize the design to get more accuracy.
IP1dB
My aim is to design the circuit to have a IP1dB of 20 dBm. I achieved a IP1dB of -22.47 dBm. I need to further
optimize the design to get more accuracy.

OP1dB
My aim is to design the circuit to have a OP1dB of 20 dBm. I achieved a IP1dB of 7.2 dBm. I need to further
optimize the design to get more accuracy.
IIP3
My aim is to design the circuit to have a IIP3 of 20 dBm. I achieved a IIP3 of -8.2 dBm. I need to further
optimize the design to get more accuracy.

OIP3
My aim is to design the circuit to have a OIP3 of 20 dBm. I achieved a OIP3 of 16.45 dBm. I need to further
optimize the design to get more accuracy.
S – Parameters
S11
My aim is to design the circuit to have a S11 of -20 dB. I achieved a S11 of -470.12 mdB. I need to further
optimize the design to get more accuracy.

S12
My aim is to design the circuit to have a S12 of -50 dB. I achieved a S12 of -51.09 dB. I need to further
optimize the design to get more accuracy.
S21
My aim is to design the circuit to have a S21 of 20 dBm. I achieved a S21 of 7.89 dB. I need to further
optimize the design to get more accuracy.

S22
My aim is to design the circuit to have a S22 of -10 dBm. I achieved a S22 of -8.345 dBm. I need to further
optimize the design to get more accuracy.
Achieved specifications (till now)
Specifications Targeted Value Achieved Value
Technology TSMC 65 nm TSMC 65 nm
Supply 1.2 V 1.2 V
Gain (Voltage Gain) 20 dB 18.13 dB
Frequency 5.5 GHz 5.49 GHz
Power 4 mW 4.46 mW
Noise Figure 1.5 dB 5.67 dB
IIP3/OIP3 -1/12 dBm -8.2/16.45dBm
IP1dB/OP1dB -10/10 dBm -22.47/7.2 dBm
S11 -20 dB -470.12 mdB
S12 -50 dB -51.09 dB
S21 20 dB 7.89 dB
S22 -10 dB -8.345 dB

References
[1] “RF Microelectronics”, B. Razavi.
[2] “Cascode Common Source LNA with Inductive Degeneration Topology utilizing Different Output
Matching Circuits in 45nm CMOS Technology”, Malti Bansal , Diksha Singh in Fourth International
Conference on Communication and Electronics Systems (ICCES 2019)
[3] “Design of an Inductive Source Degenarative Low Noise Amplifier using 180nm CMOS Technology”,
M. Kiran Kumar, Amrita Sajja, Katti Blessy Beulah ,K. Sree Deepthi , Ravalika D, International Research
Journal of Engineering and Technology (IRJET), 2019
[4] “Design of a 6GHz High-Gain Low Noise Amplifier”, Xusheng Tang, Fengyi Huang, Dawei Zhao.

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