0% found this document useful (0 votes)
66 views36 pages

Lecture 22-Indirect Addressing

This document discusses various addressing modes in microcontrollers, including immediate, direct, indirect, and indexed addressing. It explains how indirect addressing uses file select registers (FSR) to point to other registers. The FSR acts as a pointer by holding the address of another register. Examples are provided to demonstrate how the FSR registers can be used to access sequential memory locations by auto-incrementing the FSR. The goal of one example is to copy data from sequential registers into an output port by iterating through the registers using indirect addressing with auto-incremented FSRs.

Uploaded by

Hassan Shehadi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
66 views36 pages

Lecture 22-Indirect Addressing

This document discusses various addressing modes in microcontrollers, including immediate, direct, indirect, and indexed addressing. It explains how indirect addressing uses file select registers (FSR) to point to other registers. The FSR acts as a pointer by holding the address of another register. Examples are provided to demonstrate how the FSR registers can be used to access sequential memory locations by auto-incrementing the FSR. The goal of one example is to copy data from sequential registers into an output port by iterating through the registers using indirect addressing with auto-incremented FSRs.

Uploaded by

Hassan Shehadi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 36

EENG 211

Microcontrollers
Lecture 22
Chapter 6
Indirect Addressing Mode
1
Addressing Modes
• Immediate
• Direct
• Register Indirect
• Indexed-ROM

2
Immediate Addressing
• The operand is supplied within the instruction code itself and becomes
available to the CPU immediately with the instruction
• The value follows the Opcode part
• Ex: MOVLW k; the literal k is translated within the instruction code
• SUBLW k;
• ADDLW k,
• In PIC, all instructions with a literal are actually using immediate addressing mode

3
Direct Addressing
• Ex: ADDWF filereg, d
• The operand data is in a RAM memory location
• The address (to be accessed for the data) is part of the instruction
• MOVWF
• MOVFF
• ANDWF
• SUBWF
4
Saving the result in direct addressing

Default Destination (when the second parameter is not stated):


result is saved in fileReg (F). 5
Indirect Addressing
• This mode uses a register to act as a pointer to another register
• For a special function register to point to a filereg, it needs to hold 12 address bits
(since PIC18 RAM is 4096 = 212 bytes)
• This can be done using two 8-bit registers (H, L)
• upper 4 bits of H register are unused
• FSR0H and FSR0L : File Select Register 0 Low and High
• FSR1H and FSR1L : File Select Register 1 Low and High
• FSR2H and FSR2L : File Select Register 2 Low and High
6
SFR0, SFR1, SFR2
(all have the same structure)
X X X X
Actual Registers in SFR
FSR0H FSR0L
memory

FSR0 Logical name

7
Indirect addressing
• To load the address into the FSR0 or FSR1 or FSR2:

• FSR0H:0x00 (0000 0000) FSR0L: 0x30 (0011 0000)

unused
8
• The data is read or written to associated registers: INDF0, INDF1, INDF2

FSR0 Associated
INDF0
9
Actual 8-bit Register in
SFR memory
10
11
LFSR details
• In the first word: ff: two bits
designating FSR 0,1, or 2
• ff=00, ff=01, or ff=10
• 𝑘11 𝑘10 𝑘9 𝑘8 : MSBits (→FSRH)
• In the second word:
• 𝑘7 𝑘𝑘𝑘 𝑘𝑘𝑘𝑘0 (→FSRL)

12
LFSR example
• LFSR 1, 0xA39
• FSR1H  0x0A
• FSR1L 0x39
• Instruction Code: EE1A: 1110 1110 0001 1010
F039: 1111 0000 0011 1001

13
• The data is read or written to associated registers: INDF0, INDF1, INDF2

FSR0 Associated
INDF0
14
Actual 8-bit Register in
SFR memory
Ex 6-2

15
Ex 6-2
WREG
0 1 0 1 0 1 0 1

16
Ex 6-2
WREG 0 1 0 1 0 1 0 1

FSR0H FSR0L
X X X X 0 0 0 0 0 1 0 0 0 0 0 0

17
Ex 6-2
WREG 0 1 0 1 0 1 0 1

FSR0H FSR0L
X X X X 0 0 0 0 0 1 0 0 0 0 0 0

RAM Address Contents


…… . . . . . . . .
0x040 0 1 0 1 0 1 0 1

18
Ex 6-2
WREG 0 1 0 1 0 1 0 1

FSR0H FSR0L
X X X X 0 0 0 0 0 1 0 0 0 0 0 1
RAM Address Contents
…… . . . . . . . .
0x040 0 1 0 1 0 1 0 1

19
Ex 6-2
WREG 0 1 0 1 0 1 0 1

FSR0H FSR0L
X X X X 0 0 0 0 0 1 0 0 0 0 0 1
RAM Address Contents
…… . . . . . . . .
0x040 0 1 0 1 0 1 0 1
0x041 0 1 0 1 0 1 0 1

20
Ex 6-2
WREG 0 1 0 1 0 1 0 1

FSR0H FSR0L
X X X X 0 0 0 0 0 1 0 0 0 0 1 0
RAM Address Contents
…… . . . . . . . .
0x040 0 1 0 1 0 1 0 1
0x041 0 1 0 1 0 1 0 1

21
Ex 6-2
WREG 0 1 0 1 0 1 0 1

FSR0H FSR0L
X X X X 0 0 0 0 0 1 0 0 0 0 1 0
RAM Address Contents
…… . . . . . . . .
0x040 0 1 0 1 0 1 0 1
0x041 0 1 0 1 0 1 0 1
0x042 0 1 0 1 0 1 0 1

22
Ex 6-2
WREG 0 1 0 1 0 1 0 1

FSR0H FSR0L
X X X X 0 0 0 0 0 1 0 0 0 1 0 0
RAM Address Contents
…… . . . . . . . .
0x040 0 1 0 1 0 1 0 1
0x041 0 1 0 1 0 1 0 1
0x042 0 1 0 1 0 1 0 1
0x043 0 1 0 1 0 1 0 1
0x044 0 1 0 1 0 1 0 1
23
WREG 0 1 0 1 0 1 0 1
Ex 6-2 FSR0L
FSR0H X X X X 0 0 0 0 0 1 0 0 0 0 0 0
RAM Address Contents
….
0x010 0 0 0 0 0 1 0 1

…… . . . . . . . .
0x040 0 1 0 1 0 1 0 1
0x041 0 1 0 1 0 1 0 1
0x042 0 1 0 1 0 1 0 1
0x043 0 1 0 1 0 1 0 1
0x044 0 1 0 1 0 1 0 1
24
Example 6-3
• Goal: copy contents of registers 0x30 … 0x34 RAM Address Contents
to PORTB, one at a time …… . . . . . . . .

• Assume the contents of those registers 0x030 0 1 0 0 1 0 0 0

contain the ASCII values for “HELLO” 0x031 0 1 0 0 0 1 0 1

• ‘H’ = 0x48 ‘E’ = 0x45 ‘L’= 0x4C 0x032 0 1 0 0 1 1 0 0


0x033 0 1 0 0 1 1 0 0
• ‘L’ = 0x4C ‘O’ = 0x4F
0x034 0 1 0 0 1 1 1 1

25
Ex 6-2 FSR2L
FSR2H X X X X 0 0 0 0 0 0 1 1 0 0 0 0

RAM Address Contents


…… . . . . . . . .
0x030 0 1 0 0 1 0 0 0
0x031 0 1 0 0 0 1 0 1
0x032 0 1 0 0 1 1 0 0
0x033 0 1 0 0 1 1 0 0
0x034 0 1 0 0 1 1 1 1
WREG
0 1 0 1 0 1 0 1
26

PORTB
Auto Increment FSR
• INCF FSR0L will increment the lower byte of FSR0
• However, if FSR0L=FF, the carry from INCF will not propagate to FSR0H
• So the address pointed to will become wrong.
• Solution: use autoincrement /autodecrement

27
POSTINCx, PREINCx, POSTDECx, PLUSWx
x=0,1,2
• In addition to the INDF operand, each FSR register pair also has four
additional indirect operands.
• Like INDF, these are “virtual” registers that cannot be indirectly read or
written to.
• Accessing these registers actually accesses the associated FSR register pair,
but also performs a specific action on it stored value.

28
• POSTDEC: accesses the FSR value (writes to or reads indirectly from RAM), then
automatically decrements the pointer (in FSR) by ‘1’ afterwards
• POSTINC: accesses the FSR value(writes to or reads indirectly from RAM), then
automatically increments the pointer (in FSR) by ‘1’ afterwards
• PREINC: increments the pointer (in FSR) by ‘1’, then uses it in the indirect
addressing operation (read or write in RAM)
• PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the
FSR and uses the new value in the operation. So WREG is used as an offset to the
pointer.
29
• Accessing an INDF register uses the value in the FSR registers without
changing them (pointer remains the same).
• Similarly, accessing a PLUSW register gives the FSR value offset by that in
the W register; but neither FSR nor WREG values is actually changed in the
operation. The addition takes place in the CPU in a temporary location.
• Accessing the other virtual registers (POSTINC, POSTDEC, PREINC)
changes the value of the FSR registers.

30
• Operations on the FSRs with POSTDEC, POSTINC and PREINC affect
the entire register pair
• Rollovers of the FSRnL register, from FFh to 00h,
• carry over to the FSRnH register.
• Results of these operations do not change the value of any flags in the
STATUS register (e.g., Z, N, OV, etc.).

31
POSTINC example
FSR0H
X X X X
0 0 0 1

Goal of this program: 32

Clear Bank1.
POSTINC example
• Referring to the previous program, what needs to be changed in order to let it clear
Bank1, Bank2 and Bank3?
• Answer: BTFSS FSR0H, 2
• What would you change to clear half bank1 only?
• What would you change to clear Bank1 and Bank2 only?
X X X X
0 0 0 1 0 0 0 0
0 0 0 1
• FSR0H FSR0L

33
PIC18 RAM map
• RAM size varies by chip
• Minimum: 256 Bytes= one Bank
• Take the first half of Bank0 (128 bytes)
and the second half of the last bank
(could be also bank0 or could be
bank15)
• Call the combination “Access Bank”
34
Bank 0 is all GPR –
But first half (128Bytes) = Bank 0: GPR 000-07FH
-----------------------------------
PIC18 with 16 banks
Segment 0 of Access Bank
GPR 080-0FFH
Bank 1:
GPR 100-1FFH

Bank 2:
GPR 200-2FFH Access Bank address space:
000 − 07𝐹𝐻
... ∪
𝐹80 − 𝐹𝐹𝐹𝐻
Bank 14:
GPR E00-EFFH
Bank 15: GPR F00-7FFH
Bank 15 is divided:
----------------------------------
First half(128 B): GPR
SFR F80-FFFH
Second half = Segment 1
of Access Banks
35
36

You might also like