DV Assignments

Verilog

Write verilog Code and Testbench for below digital circuits

1. Inverter
2. Buffer
3. Transmission Gate
4. Tristate Buffer
5. Basic and Universal Gates
6. Flip-flops
a) JK
b) SR
c) D Asynchronous Reset
d) Synchronous Reset
e) T
f) Master-Slave Flipflop
7. Regular D latch
8. Serial Adder
9. Counters
a) 4-bit Synchronous Counters
b) 4-bit Asynchronous Counters
c) 8-bit SIngle Up Counter
d) 8-bit Up COunter with Load
e) 8-bit Up-Down Counter
f) Random LFSR
g) LFSR Up/Down
h) Gray Counter
i) One-hot Counter
j) Divide by 2 Counter
k) Divide by 3 counter
l) Divide by 4.5 Counter

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10.Priority Encoder
a) Using if-else
b) Using case

11. Decoders

a. Using Case statement

b. Using assign statement

12. 2:1,4:1,8:1 Mux

a. Using assign
b. Using Case
c. Using If

13. Adders

a. 8-bit Ripple Carry Adder

b. 8-bit Carry look-ahead adder
c. 8-bit Carry Skip Adder
d. 4-bit BCD adder and subs-tractor

14. Multipliers

a. 4*4 Unsigned array Multiplier

b. 4*4 Boot Multipier

15. Comparator’s

a. 4-bit magnitude comparators

b. 4-bit LFSR
c. 4-bit Parity Generator
d. 4-bit Universal Shift register

16. Encoders

a. Encoder using if-else

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 b. Encoder using Case statement

17. FSM to detect Sequence 1110

a) Melay with overlap
b) Melay without overlap
c) Moore with overlap
d) Moore without overlap
18. FIFO Buffer
19. LIFO buffer
20. Memories/RAM
a) Single port RAM Synchronous Read/Write
b) Single port RAM Async read, Sync Write
c) Single port RAM async read/write
d) Dual Port RAM sync read/write
e) Dual Port RAM async Read/Write
f) ROM, EPROM, EEPROM
g) Synchronous FIFO
h) Asynchronous FIFO
i) Content Addressable Memory

21. Parity
a. Using Assign
b. Using Function
c. Serial CRC
d. Parallel CRC
22. Queues
23. Random Number generator

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24. Shift Register
a. Bidirectional Shift register
b. Parallel to serial Converter
c. Serial to parallel Converter
25. 3-bit Arbiter

SV
Array Assignment No1

1. Write a program in the system Verilog to store elements in an array and print it.
Test Data:
Input 10 elements in the array :
element - 0 : 1
element - 1 : 1
element - 2 : 2
.......
Expected Output :
Elements in array are: 1 1 2 3 4 5 6 7 8 9

2. Write a program in the system Verilog to read n number of values in an array and display it in reverse
order.
Test Data :
Input the number of elements to store in the array :3
Input 3 number of elements in the array :
element - 0 : 2
element - 1 : 5
element - 2 : 7
Expected Output :
The values store into the array are :
257
The values store into the array in reverse are :
752

3. Write a program in system Verilog to find the sum of all elements of the array.
Test Data :
Input the number of elements to be stored in the array :3
Input 3 elements in the array :
element - 0 : 2

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element - 1 : 5
element - 2 : 8
Expected Output :
Sum of all elements stored in the array is : 15

4. Write a program in the system Verilog to copy the elements of one array into another array.
Test Data :
Input the number of elements to be stored in the array :3
Input 3 elements in the array :
element - 0 : 15
element - 1 : 10
element - 2 : 12
Expected Output :
The elements stored in the first array are :
15 10 12
The elements copied into the second array are :
15 10 12

5. Write a program in system Verilog to count a total number of duplicate elements in an array.
Test Data :
Input the number of elements to be stored in the array :3
Input 3 elements in the array :
element - 0 : 5
element - 1 : 1
element - 2 : 1
Expected Output :
Total number of duplicate elements found in the array is : 1

6. Write a program in system Verilog to print all unique elements in an array.

Test Data :
Input the number of elements to be stored in the array :3
Input 3 elements in the array :
element - 0 : 1
element - 1 : 5
element - 2 : 1
Expected Output :
The unique elements found in the array are :
5

7. Write a program in system Verilog to merge two arrays of same size sorted in descending order.
Test Data :
Input the number of elements to be stored in the first array :3

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Input 3 elements in the array :
element - 0 : 1
element - 1 : 2
element - 2 : 3
Input the number of elements to be stored in the second array :3
Input 3 elements in the array :
element - 0 : 1
element - 1 : 2
element - 2 : 3
Expected Output :
The merged array in descending order is :
332211

8. Write a program in system Verilog to count the frequency of each element of an array.
Test Data :
Input the number of elements to be stored in the array :3
Input 3 elements in the array :
element - 0 : 25
element - 1 : 12
element - 2 : 43
Expected Output :
The frequency of all elements of an array :
25 occurs 1 times
12 occurs 1 times
43 occurs 1 times

9. Write a program in system Verilog to find the maximum and minimum element in an array.
Test Data :
Input the number of elements to be stored in the array :3
Input 3 elements in the array :
element - 0 : 45
element - 1 : 25
element - 2 : 21
Expected Output :
Maximum element is : 45
Minimum element is : 21

10. Write a program in system Verilog to separate odd and even integers in separate arrays.
Test Data :
Input the number of elements to be stored in the array :5
Input 5 elements in the array :
element - 0 : 25
element - 1 : 47
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element - 2 : 42
element - 3 : 56
element - 4 : 32
Expected Output :
The Even elements are :
42 56 32
The Odd elements are :
25 47

11. Write a program in system Verilog to sort elements of array in ascending order.
Test Data :
Input the size of array : 5
Input 5 elements in the array :
element - 0 : 2
element - 1 : 7
element - 2 : 4
element - 3 : 5
element - 4 : 9
Expected Output :
Elements of array in sorted ascending order:
24579

12. Write a program in system Verilog to sort elements of the array in descending order.
Test Data:
Input the size of array: 3
Input 3 elements in the array :
element - 0 : 5
element - 1 : 9
element - 2 : 1
Expected Output :
Elements of the array in sorted descending order:
951

Array Assignment No2

13. Write a program in system Verilog to insert New value in the array (sorted list )..
Test Data :
Input the size of array : 3
Input 3 elements in the array in ascending order:
element - 0 : 5
element - 1 : 7
element - 2 : 9
Input the value to be inserted : 8

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Expected Output :
The exist array list is :
579
After Insert the list is :
5789

14. Write a program in system Verilog to insert New value in the array (unsorted list ).
Test Data :
Input the size of array : 4
Input 4 elements in the array in ascending order:
element - 0 : 1
element - 1 : 8
element - 2 : 7
element - 3 : 10
Input the value to be inserted : 5
Input the Position, where the value to be inserted :2
Expected Output :
The current list of the array :
1 8 7 10
After Insert the element the new list is :
1 5 8 7 10

15. Write a program in system Verilog to delete an element at desired position from an array.
Test Data :
Input the size of array : 5
Input 5 elements in the array in ascending order:
element - 0 : 1
element - 1 : 2
element - 2 : 3
element - 3 : 4
element - 4 : 5
Input the position where to delete: 3
Expected Output :
The new list is : 1 2 4 5

16. Write a program in system Verilog to find the second largest element in an array.
Test Data :
Input the size of array : 5
Input 5 elements in the array :
element - 0 : 2
element - 1 : 9
element - 2 : 1
element - 3 : 4
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element - 4 : 6
Expected Output :
The Second largest element in the array is : 6

17. Write a program in system Verilog to find the second smallest element in an array.
Test Data :
Input the size of array : 5
Input 5 elements in the array (value must be <9999) :
element - 0 : 0
element - 1 : 9
element - 2 : 4
element - 3 : 6
element - 4 : 5
Expected Output :
The Second smallest element in the array is : 4

18. Write a program in system Verilog for a 2D array of size 3x3 and print the matrix.
Test Data :
Input elements in the matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [0],[2] : 3
element - [1],[0] : 4
element - [1],[1] : 5
element - [1],[2] : 6
element - [2],[0] : 7
element - [2],[1] : 8
element - [2],[2] : 9
Expected Output :
The matrix is :

123
456
789

19. Write a program in system Verilog for addition of two Matrices of same size.
Test Data :
Input the size of the square matrix (less than 5): 2
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [1],[0] : 3
element - [1],[1] : 4
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Input elements in the second matrix :
element - [0],[0] : 5
element - [0],[1] : 6
element - [1],[0] : 7
element - [1],[1] : 8
Expected Output :
The First matrix is :

12
34
The Second matrix is :

56
78
The Addition of two matrix is :

68
10 12

20. Write a program in system Verilog for subtraction of two Matrices.

Test Data :
Input the size of the square matrix (less than 5): 2
Input elements in the first matrix :
element - [0],[0] : 5
element - [0],[1] : 6
element - [1],[0] : 7
element - [1],[1] : 8
Input elements in the second matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [1],[0] : 3
element - [1],[1] : 4
Expected Output :
The First matrix is :

56
78
The Second matrix is :

12
34
The Subtraction of two matrix is :

44

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44

21. Write a program in system Verilog for multiplication of two square Matrices.
Test Data :
Input the rows and columns of first matrix : 2 2
Input the rows and columns of second matrix : 2 2
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [1],[0] : 3
element - [1],[1] : 4
Input elements in the second matrix :
element - [0],[0] : 5
element - [0],[1] : 6
element - [1],[0] : 7
element - [1],[1] : 8
Expected Output :
The First matrix is :

12
34
The Second matrix is :

56
78
The multiplication of two matrix is :

19 22
43 50

22. Write a program in system Verilog to find transpose of a given matrix.

Test Data :
Input the rows and columns of the matrix : 2 2
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [1],[0] : 3
element - [1],[1] : 4
Expected Output :
The matrix is :

12
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34

The transpose of a matrix is :

13
24

23. Write a program in system Verilog to find sum of right diagonals of a matrix.
Test Data :
Input the size of the square matrix : 2
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [1],[0] : 3
element - [1],[1] : 4
Expected Output :
The matrix is :
12
34
Addition of the right Diagonal elements is :5
Elements in array are:

24. Write a program in system Verilog to find the sum of left diagonals of a matrix.
Test Data:
Input the size of the square matrix: 2
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [1],[0] : 3
element - [1],[1] : 4
Expected Output :
The matrix is :
12
34
Addition of the left Diagonal elements is :5

Array Assignment No3

25. Write a program in system Verilog to find sum of rows an columns of a Matrix.
Test Data :
Input the size of the square matrix : 2
Input elements in the first matrix :
element - [0],[0] : 5
element - [0],[1] : 6

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element - [1],[0] : 7
element - [1],[1] : 8
Expected Output :
The First matrix is :
The matrix is :
56
78
The sum or rows and columns of the matrix is :
5 6 11
7 8 15

12 14

26. Write a program in system Verilog to print or display the lower triangular of a given matrix.
Test Data :
Input the size of the square matrix : 3
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [0],[2] : 3
element - [1],[0] : 4
element - [1],[1] : 5
element - [1],[2] : 6
element - [2],[0] : 7
element - [2],[1] : 8
element - [2],[2] : 9
Expected Output :
The matrix is :
123
456
789

Setting zero in lower triangular matrix

123
056
009

27. Write a program in system Verilog to print or display upper triangular matrix.
Test Data :
Input the size of the square matrix : 3
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 2
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element - [0],[2] : 3
element - [1],[0] : 4
element - [1],[1] : 5
element - [1],[2] : 6
element - [2],[0] : 7
element - [2],[1] : 8
element - [2],[2] : 9
Expected Output :
The matrix is :
123
456
789

Setting zero in upper triangular matrix

100
450
789

28. Write a program in system Verilog to calculate determinant of a 3 x 3 matrix.

Test Data :
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 0
element - [0],[2] : -1
element - [1],[0] : 0
element - [1],[1] : 0
element - [1],[2] : 1
element - [2],[0] : -1
element - [2],[1] : -1
element - [2],[2] : 0
Expected Output :
The matrix is :
1 0 -1
001
-1 -1 0

The Determinant of the matrix is: 1

29. Write a program in system Verilog to accept a matrix and determine whether it is a sparse matrix.
Test Data :
Input the number of rows of the matrix : 2
Input the number of columns of the matrix : 2
Input elements in the first matrix :
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element - [0],[0] : 0
element - [0],[1] : 0
element - [1],[0] : 1
element - [1],[1] : 0
Expected Output :
The given matrix is sparse matrix.
There are 3 number of zeros in the matrix

30. Write a program in system Verilog to accept two matrices and check whether they are equal.
Test Data :
Input Rows and Columns of the 1st matrix :2 2
Input Rows and Columns of the 2nd matrix :2 2
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [1],[0] : 3
element - [1],[1] : 4
Input elements in the second matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [1],[0] : 3
element - [1],[1] : 4
Expected Output :
The first matrix is :
12
34
The second matrix is :
12
34
The Matrices can be compared :
Two matrices are equal.

31. Write a program in system Verilog to check whether a given matrix is an identity matrix.
Test Data :
Input number of Rows for the matrix :3
Input number of Columns for the matrix :3
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 0
element - [0],[2] : 0
element - [1],[0] : 0
element - [1],[1] : 1
element - [1],[2] : 0
element - [2],[0] : 0
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element - [2],[1] : 0
element - [2],[2] : 1
Expected Output :
The matrix is :
100
010
001
The matrix is an identity matrix.

32. Write a program in system Verilog to find a pair with given sum in the array.
Expected Output :
The given array : 6 8 4 -5 7 9
The given sum : 15
Pair of elements can make the given sum by the value of index 0 and 5

33. Write a program in system verilog to find the majority element of an array.
A majority element in an array A[] of size n is an element that appears more than n/2 times (and hence there
is at most one such element).
Expected Output :
The given array is : 4 8 4 6 7 4 4 8
There are no Majority Elements in the given array.

34. Write a program in system Verilog to search an element in a row wise and column wise sorted matrix.
Expected Output :
The given array in matrix form is :
15 23 31 39
18 26 36 43
25 28 37 48
30 34 39 50
The given value for searching is: 37
The element Found at the position in the matrix is: 2, 2

35. Write a program in system Verilog to find the row with maximum number of 1s.
Expected Output :
The given 2D array is :
01011
11111
10010
00000
10001

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The index of row with maximum 1s is: 1

36. Write a program in system verilog to find the missing number from a given array. There are no
duplicates in list.
Expected Output:
The given array is : 1 3 4 2 5 6 9 8
The missing number is : 7

Array Assignment No4

37. Write a program in system Verilog to segregate 0s and 1s in an array.

Expected Output:
The given array is:
101001011
The array after segregation is: 0 0 0 0 1 1 1 1 1

38. Write a program in system Verilog to merge one sorted array into another sorted array.
Pivot element is the only element in input array which is smaller than it's previous element.
A pivot element divided a sorted rotated array into two monotonically increasing array.
Expected Output :
The given Large Array is : 10 12 14 16 18 20 22
The given Small Array is : 11 13 15 17 19 21
After merged the new Array is :
10 11 12 13 14 15 16 17 18 19 20 21 22

39. Write a program in system Verilog to rotate an array by N positions.

Expected Output :
The given array is : 0 3 6 9 12 14 18 20 22 25 27
From 4th position the values of the array are : 12 14 18 20 22 25 27
Before 4th position the values of the array are : 0 3 6 9
After rotating from 4th position the array is:
12 14 18 20 22 25 27 0 3 6 9

40. Write a program in system Verilog to move all zeroes to the end of a given array.
Expected Output :
The given array is : 2 5 7 0 4 0 7 -5 8 0
The new array is:
2 5 7 8 4 -5 7 0 0 0

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41. Write a program in system Verilog to segregate even and odd elements on an array.
Expected Output:
The given array is:
17 42 19 7 27 24 30 54 73
The array after segregation is: 54 42 30 24 27 7 19 17 73

42. Write a program in system Verilog to find the smallest missing element from a sorted array.
Expected Output :
The given array is : 0 1 3 4 5 6 7 9
The missing smallest element is: 2

43. Write a program in system Verilog to find majority element of an array.

Expected Output :
The given array is : 1 3 3 7 4 3 2 3 3
The majority of the Element : 3

44. Write a program in system Verilog to find the two repeating elements in a given array.
Expected Output :
The given array is : 2 7 4 7 8 3 4
The repeating elements are: 7 4

45. Write a program in system Verilog to find two elements whose sum is closest to zero.
Expected Output :
The given array is : 38 44 63 -51 -35 19 84 -69 4 -46
The Pair of elements whose sum is minimum are:
[44, -46]

46. Write a program in system Verilog to find the row with maximum number of 1s.
Expected Output :
The given 2D array is :
01011
11111
10010
00000
10001
The index of row with maximum 1s is: 1

47. Generate a array with random elements in range 10 to 100.

Expected Output :
The 1D array is : 13 20 12 38 48 46 30 75 11 99

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48. Generate Fibonacci series where the next element is sum of previous two elements. starting elements is 0
and 1.
Expected Output :
The 1D array is : 0 1 1 2 3 5 8 13 21

1. Give the brief description of System Verilog environment including with all the
components in detail and explain the communication flow clearly?
2. Develop "full adder" sv test bench with packet, generator, scoreboard, coverage,
monitor, test, test-top modules
3. Develop "Jk-flipflop" sv test bench with packet, generator, scoreboard, coverage,
monitor, test, test-top modules
4. Develope "full adder" sv test bench with packet, generator scoreboard, coverage,
monitor, test,test-top modules
5. Give the brief description of System Verilog environment including with all the
components in detail and explain the communication flow clearly?

UVM

1. Explain in detail about UVM factory

2. Give the description of TLM
3. Describe in detail about UVM phases

Assessments
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1. Design a Counter which counts in the pattern
122333444455555…

Design a Dual port RAM With the following specifications.

1. It will take the 32 bit data from the input port ‘din’ whenever the enable signal for
write ‘wr_en’ is asserted.
2. Writes this ‘din’ into the  internal memory. The address to which this data is to be
written can be specified by the input port ‘wr_addr’ (5-bits).
3. Reads this data through the output port ‘dout’ whenever the  enable signal for read
‘rd_en’ is asserted. The address from which the data to be retrieved can be specified
by the input port ‘rd_addr’ (5-bits).

2. Write a program in Verilog which can detect a sequence 1110 in overlapping form
using mealy model
3. Write a program in system verilog to merge two arrays of same size sorted in
decending order.
Test Data :
Input the number of elements to be stored in the first array :3
Input 3 elements in the array :
element - 0 : 1
element - 1 : 2
element - 2 : 3
Input the number of elements to be stored in the second array :3
Input 3 elements in the array :
element - 0 : 1
element - 1 : 2
element - 2 : 3
Expected Output :
The merged array in decending order is :
332211

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4. Write a program in system Verilog to find the second largest element in an array.
Test Data :
Input the size of array : 5
Input 5 elements in the array :
element - 0 : 2
element - 1 : 9
element - 2 : 1
element - 3 : 4
element - 4 : 6
Expected Output :
The Second largest element in the array is : 6

5. Write a program in system verilog to print or display upper triangular matrix.

Test Data :
Input the size of the square matrix : 3
Input elements in the first matrix :
element - [0],[0] : 1
element - [0],[1] : 2
element - [0],[2] : 3
element - [1],[0] : 4
element - [1],[1] : 5
element - [1],[2] : 6
element - [2],[0] : 7
element - [2],[1] : 8
element - [2],[2] : 9
Expected Output :
The matrix is :
123
456
789

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 Setting zero in upper triangular matrix

100
450
789

6. Write a Verilog HDL with testbench for D flipflop asynchronous reset?

SV
1. What is the program block and explain the use of it in SV?
2. How does the fork_join,fork_join_any, fork_join_none is useful in SV explain it with
an example
3. Explain the Concept of semaphore and mailbox with a detailed explain
4. Explain the functionality of Arbiter.

1. What is Polymorphism
2. Why do we use virtual Interface in SV?
3. What is the virtual class in System Verilog
4. What is the difference between reg, logic and wire datatypes in System Verilog
5. Difference between module and class-based TB
6. Why do we use create method in UVM rather than using new constructor?

1. Write a program in system verilog to read n number of values in an array and display

it in reverse order.
Test Data :
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 Input the number of elements to store in the array :3
Input 3 number of elements in the array :
element - 0 : 2
element - 1 : 5
element - 2 : 7
Expected Output :
The values store into the array are :
257
The values store into the array in reverse are :
752
2. FSM to detect Sequence 1001

e) Melay with overlap

f) Melay without overlap
g) Moore with overlap
h) Moore without overlap
3. Declare an associative array where index is 10-bit virtual address and value

corresponding to index is Physical address.

- Create an associative array which contains 20 Physical addresses corresponding to
virtual address.
- Find the size of array, delete all the 20 addresses after deleting store the deleted
address in a local variable prints the entire array after every delete operation.After
every delete is done again regenerate the same array with the previous values

1. Declare a Dynamic Array in which we can store values of int data type which we call it as
Virtual address

a) Allocate 20 memory location for the dynamic array and initialize each location with
some random address where address value should be less than 16 MB.

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 b) Find the size of array, delete all the 20 addresses after deleting store the deleted
address in a local variable prints the entire array after every delete operation. After
every delete is done again regenerate the same array with the previous values
c) Use all array locator method to perform some operation on this array
d) Use all array ordering method and print the result after every operation last print
should return the same value as it printed for the first time
e) Use all array reduction method to perform some operation on each element of this
array

1. Design a Bit stuffing & De stuffing Logic Circuits with the following specifications

Transmitter:
It will take the 32 bit serial data from the input port ‘din’.
Whenever it detects five 1s in the given input data it will stuff 1 .
The serial stuffed data should come from the output port ‘dout’.
Output signal ‘valid’ is present to indicate the data coming from the serial output port ‘dout’ is valid.
Receiver:
Input port of the receiver ‘din’ takes the data from the Transmitter’s output port ‘dout’ whenever the
‘valid’ is high.
Whenever it detects five 1’s in  the data it will de stuff 1 .
The serial de-stuffed data should come from the output port ‘dout’.

2. Represent below decimal expression in hex,octal and binary. Where every two digit should be
separated by _ (For ex: 16’hAA_BB); i.3072 , ii. 5192 , iii. 65536, iv.1048576

3. Develop a parameterized adder which has a input two n bit variable and one num_of_sums (no of
sums to be calculated) where it calculates the sum of 2 n bit variables and stores in a memory.
Memory width should be n+1 and depth depends on the user input num_of_sums; Develop another
Tb module where this adder should be instantiated with 4 different parameters and 10 different input
should be given to each instantiation. Print the output of each input.

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1. Create a Txn Base Class which has two properties address and data of 32 bit .. when a
object is created using base class and randomized it should generate always address
value which is odd and Data value which is even .
Now Create two Class extending the base class where the 1st child class when
randomized create address as odd value and Data also odd number .
2nd child class when randomized create any random address and data .
Create a Generator which uses the base class to generate a packet and send it to driver
using mailbox .
Create 3 different tests which generates 5 different packet using the above generator .
Where every tests should use three different class

1. Describe about System Verilog architecture components in detail?

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 UVM
1. Write a program for packed structure with the size of 50?
2. Write a program for dynamic array with a size of 10 after initializing the size of
dynamic array. Now resize the array to 15 without losing of previous data in the array?
3. Write a test interface with clocking block , test top modules for APB in SV and also
mention skew in clocking block and use of skew in clocking block?

1. Explain UVM phases in brief?

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