RM0433

Reference manual
STM32H742, STM32H743/753 and STM32H750 Value line
advanced Arm®-based 32-bit MCUs

Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32H742xx, STM32H743/53xx and STM32H750xB microcontroller
memory and peripherals.
The STM32H742, STM32H743/753 and STM32H750 are lines of microcontrollers with
different memory sizes, packages and peripherals.
The devices include ST state-of-the-art patented technology.
For ordering information, mechanical, and electrical device characteristics refer to the
corresponding datasheets.
For information on the Arm® Cortex®-M7 with FPU core, refer to the corresponding Arm
Technical Reference Manuals.

Related documents
• Arm® Cortex®-M7 Technical Reference Manual, available from www.arm.com.
• Cortex®-M7 programming manual (PM0253).
• STM32H742xx, STM32H743xx and STM32H753xx datasheets
• STM32H750xB datasheet
• STM32H742 and STM32H743/753 errata sheet
• STM32H750 errata sheet

January 2023 RM0433 Rev 8 1/3353

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Contents RM0433

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

2 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.1.1 Bus matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.1.2 TCM buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.1.3 Bus-to-bus bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.1.4 Inter-domain buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2.1.5 CPU buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2.1.6 Bus master peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.1.7 Clocks to functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.2 AXI interconnect matrix (AXIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.2.1 AXI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.2.2 AXI interconnect main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.2.3 AXI interconnect functional description . . . . . . . . . . . . . . . . . . . . . . . . 110
2.2.4 AXI interconnect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
2.2.5 AXI interconnect register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
2.3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
2.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
2.3.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . 130
2.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
2.5 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
2.6 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

3 RAM ECC monitoring (RAMECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.2 RAMECC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.3 RAMECC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.3.1 RAMECC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

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3.3.2 RAMECC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

3.3.3 RAMECC monitor mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
3.4 RAMECC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
3.4.1 RAMECC interrupt enable register (RAMECC_IER) . . . . . . . . . . . . . . 143
3.4.2 RAMECC monitor x configuration register (RAMECC_MxCR) . . . . . . 144
3.4.3 RAMECC monitor x status register (RAMECC_MxSR) . . . . . . . . . . . . 144
3.4.4 RAMECC monitor x failing address register (RAMECC_MxFAR) . . . . 145
3.4.5 RAMECC monitor x failing data low register (RAMECC_MxFDRL) . . 145
3.4.6 RAMECC monitor x failing data high register (RAMECC_MxFDRH) . 146
3.4.7 RAMECC monitor x failing ECC error code register
RAMECC_MxFECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
3.4.8 RAMECC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

4 Embedded flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
4.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
4.3 FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4.3.1 FLASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4.3.2 FLASH internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
4.3.3 FLASH architecture and integration in the system . . . . . . . . . . . . . . . 150
4.3.4 Flash memory architecture and usage . . . . . . . . . . . . . . . . . . . . . . . . 152
4.3.5 FLASH system performance enhancements . . . . . . . . . . . . . . . . . . . . 156
4.3.6 FLASH data protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
4.3.7 Overview of FLASH operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
4.3.8 FLASH read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
4.3.9 FLASH program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.3.10 FLASH erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.3.11 FLASH parallel operations (STM32H742/743/753 devices only) . . . . 168
4.3.12 Flash memory error protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.3.13 Flash bank and register swapping (STM32H742/743/753 devices only) . .
170
4.3.14 FLASH reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.4 FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.4.1 About option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.4.2 Option byte loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.4.3 Option byte modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.4.4 Option bytes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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4.4.5 Description of user and system option bytes . . . . . . . . . . . . . . . . . . . . 179

4.4.6 Description of data protection option bytes . . . . . . . . . . . . . . . . . . . . . 180
4.4.7 Description of boot address option bytes . . . . . . . . . . . . . . . . . . . . . . . 181
4.5 FLASH protection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
4.5.1 FLASH configuration protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
4.5.2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
4.5.3 Readout protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
4.5.4 Proprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . 189
4.5.5 Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
4.6 FLASH low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
4.6.2 Managing the FLASH domain switching to DStop or DStandby . . . . . 192
4.7 FLASH error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
4.7.2 Write protection error (WRPERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
4.7.3 Programming sequence error (PGSERR) . . . . . . . . . . . . . . . . . . . . . . 194
4.7.4 Strobe error (STRBERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
4.7.5 Inconsistency error (INCERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
4.7.6 Operation error (OPERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
4.7.7 Error correction code error (SNECCERR/DBECCERR) . . . . . . . . . . . 196
4.7.8 Read protection error (RDPERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
4.7.9 Read secure error (RDSERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
4.7.10 CRC read error (CRCRDERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
4.7.11 Option byte change error (OPTCHANGEERR) . . . . . . . . . . . . . . . . . . 198
4.7.12 Miscellaneous HardFault errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
4.8 FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
4.9 FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
4.9.1 FLASH access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . 201
4.9.2 FLASH key register for bank 1 (FLASH_KEYR1) . . . . . . . . . . . . . . . . 201
4.9.3 FLASH option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . 202
4.9.4 FLASH control register for bank 1 (FLASH_CR1) . . . . . . . . . . . . . . . . 202
4.9.5 FLASH status register for bank 1 (FLASH_SR1) . . . . . . . . . . . . . . . . . 207
4.9.6 FLASH clear control register for bank 1 (FLASH_CCR1) . . . . . . . . . . 210
4.9.7 FLASH option control register (FLASH_OPTCR) . . . . . . . . . . . . . . . . 211
4.9.8 FLASH option status register (FLASH_OPTSR_CUR) . . . . . . . . . . . . 212
4.9.9 FLASH option status register (FLASH_OPTSR_PRG) . . . . . . . . . . . . 215

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4.9.10 FLASH option clear control register (FLASH_OPTCCR) . . . . . . . . . . . 217

4.9.11 FLASH protection address for bank 1 (FLASH_PRAR_CUR1) . . . . . . 217
4.9.12 FLASH protection address for bank 1 (FLASH_PRAR_PRG1) . . . . . . 218
4.9.13 FLASH secure address for bank 1 (FLASH_SCAR_CUR1) . . . . . . . . 219
4.9.14 FLASH secure address for bank 1 (FLASH_SCAR_PRG1) . . . . . . . . 219
4.9.15 FLASH write sector protection for bank 1
(FLASH_WPSN_CUR1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
4.9.16 FLASH write sector protection for bank 1
(FLASH_WPSN_PRG1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
4.9.17 FLASH register boot address (FLASH_BOOT_CURR) . . . . . . . . . . . . 221
4.9.18 FLASH register boot address FLASH_BOOT_PRGR) . . . . . . . . . . . . 221
4.9.19 FLASH CRC control register for bank 1 (FLASH_CRCCR1) . . . . . . . . 222
4.9.20 FLASH CRC start address register for bank 1
(FLASH_CRCSADD1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.9.21 FLASH CRC end address register for bank 1
(FLASH_CRCEADD1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
4.9.22 FLASH CRC data register (FLASH_CRCDATAR) . . . . . . . . . . . . . . . . 224
4.9.23 FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R) . . . . . . . . . 225
4.9.24 FLASH key register for bank 2 (FLASH_KEYR2) . . . . . . . . . . . . . . . . 225
4.9.25 FLASH control register for bank 2 (FLASH_CR2) . . . . . . . . . . . . . . . . 226
4.9.26 FLASH status register for bank 2 (FLASH_SR2) . . . . . . . . . . . . . . . . . 230
4.9.27 FLASH clear control register for bank 2 (FLASH_CCR2) . . . . . . . . . . 233
4.9.28 FLASH protection address for bank 2 (FLASH_PRAR_CUR2) . . . . . . 234
4.9.29 FLASH protection address for bank 2 (FLASH_PRAR_PRG2) . . . . . . 234
4.9.30 FLASH secure address for bank 2 (FLASH_SCAR_CUR2) . . . . . . . . 235
4.9.31 FLASH secure address for bank 2 (FLASH_SCAR_PRG2) . . . . . . . . 236
4.9.32 FLASH write sector protection for bank 2
(FLASH_WPSN_CUR2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
4.9.33 FLASH write sector protection for bank 2
(FLASH_WPSN_PRG2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
4.9.34 FLASH CRC control register for bank 2 (FLASH_CRCCR2) . . . . . . . . 238
4.9.35 FLASH CRC start address register for bank 2
(FLASH_CRCSADD2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
4.9.36 FLASH CRC end address register for bank 2
(FLASH_CRCEADD2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
4.9.37 FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R) . . . . . . . . . 240
4.9.38 FLASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . 241

5 Secure memory management (SMM) . . . . . . . . . . . . . . . . . . . . . . . . . 246

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5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

5.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
5.3 Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
5.3.1 Associated features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
5.3.2 Boot state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
5.3.3 Secure access mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
5.4 Root secure services (RSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
5.4.1 Secure area setting service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
5.4.2 Secure area exiting service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
5.5 Secure user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
5.5.1 Access rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
5.5.2 Setting secure user memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
5.6 Summary of flash protection mechanisms . . . . . . . . . . . . . . . . . . . . . . . 252

6 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
6.2 PWR main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
6.3 PWR block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
6.3.1 PWR pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.4 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.4.1 System supply startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
6.4.2 Core domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
6.4.3 PWR external supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
6.4.4 Backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
6.4.5 VBAT battery charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.4.6 Analog supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.4.7 USB regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
6.5 Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
6.5.1 Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . 269
6.5.2 Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
6.5.3 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 270
6.5.4 Analog voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
6.5.5 Battery voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
6.5.6 Temperature thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
6.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
6.6.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

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6.6.2 Voltage scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

6.6.3 Power control modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
6.6.4 Power management examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
6.7 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
6.7.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
6.7.2 Controlling peripheral clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
6.7.3 Entering low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
6.7.4 Exiting from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
6.7.5 CSleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
6.7.6 CStop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
6.7.7 DStop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
6.7.8 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
6.7.9 DStandby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
6.7.10 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
6.7.11 Monitoring low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
6.8 PWR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
6.8.1 PWR control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 303
6.8.2 PWR control status register 1 (PWR_CSR1) . . . . . . . . . . . . . . . . . . . . 304
6.8.3 PWR control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 305
6.8.4 PWR control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 306
6.8.5 PWR CPU control register (PWR_CPUCR) . . . . . . . . . . . . . . . . . . . . 308
6.8.6 PWR D3 domain control register (PWR_D3CR) . . . . . . . . . . . . . . . . . 309
6.8.7 PWR wakeup clear register (PWR_WKUPCR) . . . . . . . . . . . . . . . . . . 310
6.8.8 PWR wakeup flag register (PWR_WKUPFR) . . . . . . . . . . . . . . . . . . . 310
6.8.9 PWR wakeup enable and polarity register (PWR_WKUPEPR) . . . . . . 311
6.8.10 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

7 Low-power D3 domain application example . . . . . . . . . . . . . . . . . . . . 313

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
7.2 EXTI, RCC and PWR interconnections . . . . . . . . . . . . . . . . . . . . . . . . . 313
7.2.1 Interrupts and wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
7.2.2 Block interactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
7.2.3 Role of DMAMUX2 in D3 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
7.3 Low-power application example based on
LPUART1 transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
7.3.1 Memory retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
7.3.2 Memory-to-peripheral transfer using LPUART1 interface . . . . . . . . . . 317

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7.3.3 Overall description of the low-power application example based on

LPUART1 transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
7.3.4 Alternate implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
7.4 Other low-power applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

8 Reset and Clock Control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

8.1 RCC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
8.2 RCC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
8.3 RCC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
8.4 RCC reset block functional description . . . . . . . . . . . . . . . . . . . . . . . . . 328
8.4.1 Power-on/off reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
8.4.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
8.4.3 Local resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
8.4.4 Reset source identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
8.4.5 Low-power mode security reset (lpwr_rst) . . . . . . . . . . . . . . . . . . . . . . 333
8.4.6 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
8.4.7 Power-on and wakeup sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
8.5 RCC clock block functional description . . . . . . . . . . . . . . . . . . . . . . . . . 336
8.5.1 Clock naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
8.5.2 Oscillators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
8.5.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
8.5.4 Clock output generation (MCO1/MCO2) . . . . . . . . . . . . . . . . . . . . . . . 344
8.5.5 PLL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
8.5.6 System clock (sys_ck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
8.5.7 Handling clock generators in Stop and Standby mode . . . . . . . . . . . . 351
8.5.8 Kernel clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
8.5.9 General clock concept overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
8.5.10 Peripheral allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
8.5.11 Peripheral clock gating control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
8.5.12 CPU and bus matrix clock gating control . . . . . . . . . . . . . . . . . . . . . . . 378
8.6 RCC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
8.7 RCC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
8.7.1 Register mapping overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
8.7.2 RCC source control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . 382
8.7.3 RCC internal clock source calibration register (RCC_ICSCR) . . . . . . 386
8.7.4 RCC HSI configuration register (RCC_HSICFGR) . . . . . . . . . . . . . . . 387

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8.7.5 RCC clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . 388

8.7.6 RCC CSI configuration register (RCC_CSICFGR) . . . . . . . . . . . . . . . 389
8.7.7 RCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 390
8.7.8 RCC domain 1 clock configuration register (RCC_D1CFGR) . . . . . . . 393
8.7.9 RCC domain 2 clock configuration register (RCC_D2CFGR) . . . . . . . 395
8.7.10 RCC domain 3 clock configuration register (RCC_D3CFGR) . . . . . . . 396
8.7.11 RCC PLL clock source selection register (RCC_PLLCKSELR) . . . . . . 397
8.7.12 RCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 399
8.7.13 RCC PLL1 dividers configuration register (RCC_PLL1DIVR) . . . . . . . 402
8.7.14 RCC PLL1 fractional divider register (RCC_PLL1FRACR) . . . . . . . . . 404
8.7.15 RCC PLL2 divider configuration register (RCC_PLL2DIVR) . . . . . . . . 405
8.7.16 RCC PLL2 fractional divider register (RCC_PLL2FRACR) . . . . . . . . . 407
8.7.17 RCC PLL3 divider configuration register (RCC_PLL3DIVR) . . . . . . . . 408
8.7.18 RCC PLL3 fractional divider register (RCC_PLL3FRACR) . . . . . . . . . 410
8.7.19 RCC domain 1 kernel clock configuration register
(RCC_D1CCIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
8.7.20 RCC domain 2 kernel clock configuration register
(RCC_D2CCIP1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
8.7.21 RCC domain 2 kernel clock configuration register
(RCC_D2CCIP2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
8.7.22 RCC domain 3 kernel clock configuration register
(RCC_D3CCIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
8.7.23 RCC clock source interrupt enable register (RCC_CIER) . . . . . . . . . . 420
8.7.24 RCC clock source Interrupt flag register (RCC_CIFR) . . . . . . . . . . . . 422
8.7.25 RCC clock source interrupt clear register (RCC_CICR) . . . . . . . . . . . 424
8.7.26 RCC backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 426
8.7.27 RCC clock control and status register (RCC_CSR) . . . . . . . . . . . . . . . 428
8.7.28 RCC AHB3 reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . . . . . 429
8.7.29 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 431
8.7.30 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 433
8.7.31 RCC AHB4 peripheral reset register (RCC_AHB4RSTR) . . . . . . . . . . 434
8.7.32 RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . . . . . . . 436
8.7.33 RCC APB1 peripheral reset register (RCC_APB1LRSTR) . . . . . . . . . 437
8.7.34 RCC APB1 peripheral reset register (RCC_APB1HRSTR) . . . . . . . . . 440
8.7.35 RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 441
8.7.36 RCC APB4 peripheral reset register (RCC_APB4RSTR) . . . . . . . . . . 443
8.7.37 RCC global control register (RCC_GCR) . . . . . . . . . . . . . . . . . . . . . . 445
8.7.38 RCC D3 Autonomous mode register (RCC_D3AMR) . . . . . . . . . . . . . 446

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8.7.39 RCC reset status register (RCC_RSR) . . . . . . . . . . . . . . . . . . . . . . . . 449

8.7.40 RCC AHB3 clock register (RCC_AHB3ENR) . . . . . . . . . . . . . . . . . . . 451
8.7.41 RCC AHB1 clock register (RCC_AHB1ENR) . . . . . . . . . . . . . . . . . . . 453
8.7.42 RCC AHB2 clock register (RCC_AHB2ENR) . . . . . . . . . . . . . . . . . . . 455
8.7.43 RCC AHB4 clock register (RCC_AHB4ENR) . . . . . . . . . . . . . . . . . . . 457
8.7.44 RCC APB3 clock register (RCC_APB3ENR) . . . . . . . . . . . . . . . . . . . . 460
8.7.45 RCC APB1 clock register (RCC_APB1LENR) . . . . . . . . . . . . . . . . . . . 461
8.7.46 RCC APB1 clock register (RCC_APB1HENR) . . . . . . . . . . . . . . . . . . 465
8.7.47 RCC APB2 clock register (RCC_APB2ENR) . . . . . . . . . . . . . . . . . . . . 467
8.7.48 RCC APB4 clock register (RCC_APB4ENR) . . . . . . . . . . . . . . . . . . . . 470
8.7.49 RCC AHB3 Sleep clock register (RCC_AHB3LPENR) . . . . . . . . . . . . 473
8.7.50 RCC AHB1 Sleep clock register (RCC_AHB1LPENR) . . . . . . . . . . . . 475
8.7.51 RCC AHB2 Sleep clock register (RCC_AHB2LPENR) . . . . . . . . . . . . 477
8.7.52 RCC AHB4 Sleep clock register (RCC_AHB4LPENR) . . . . . . . . . . . . 479
8.7.53 RCC APB3 Sleep clock register (RCC_APB3LPENR) . . . . . . . . . . . . 482
8.7.54 RCC APB1 Low Sleep clock register (RCC_APB1LLPENR) . . . . . . . . 483
8.7.55 RCC APB1 High Sleep clock register (RCC_APB1HLPENR) . . . . . . . 487
8.7.56 RCC APB2 Sleep clock register (RCC_APB2LPENR) . . . . . . . . . . . . 489
8.7.57 RCC APB4 Sleep clock register (RCC_APB4LPENR) . . . . . . . . . . . . 492
8.8 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

9 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
9.2 CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
9.3 CRS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
9.4 CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
9.4.1 CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
9.5 CRS internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
9.5.1 Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
9.5.2 Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
9.5.3 Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 508
9.5.4 CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
9.6 CRS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
9.7 CRS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
9.8 CRS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511
9.8.1 CRS control register (CRS_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

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9.8.2 CRS configuration register (CRS_CFGR) . . . . . . . . . . . . . . . . . . . . . . 512

9.8.3 CRS interrupt and status register (CRS_ISR) . . . . . . . . . . . . . . . . . . . 513
9.8.4 CRS interrupt flag clear register (CRS_ICR) . . . . . . . . . . . . . . . . . . . . 515
9.8.5 CRS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

10 Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
10.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
10.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
10.3.1 HSEM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
10.3.2 HSEM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
10.3.3 HSEM lock procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
10.3.4 HSEM write/read/read lock register address . . . . . . . . . . . . . . . . . . . . 520
10.3.5 HSEM unlock procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
10.3.6 HSEM MASTERID semaphore clear . . . . . . . . . . . . . . . . . . . . . . . . . . 521
10.3.7 HSEM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
10.3.8 AHB bus master ID verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
10.4 HSEM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
10.4.1 HSEM register semaphore x (HSEM_Rx) . . . . . . . . . . . . . . . . . . . . . . 524
10.4.2 HSEM read lock register semaphore x (HSEM_RLRx) . . . . . . . . . . . . 525
10.4.3 HSEM interrupt enable register (HSEM_IER) . . . . . . . . . . . . . . . . . . . 526
10.4.4 HSEM interrupt clear register (HSEM_ICR) . . . . . . . . . . . . . . . . . . . . 526
10.4.5 HSEM interrupt status register (HSEM_ISR) . . . . . . . . . . . . . . . . . . . . 526
10.4.6 HSEM interrupt status register (HSEM_MISR) . . . . . . . . . . . . . . . . . . 527
10.4.7 HSEM clear register (HSEM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
10.4.8 HSEM clear semaphore key register (HSEM_KEYR) . . . . . . . . . . . . . 528
10.4.9 HSEM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

11 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
11.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
11.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
11.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
11.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 533
11.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
11.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

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11.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

11.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
11.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
11.3.8 External interrupt/wake-up lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
11.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
11.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
11.3.11 I/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
11.3.12 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
11.3.13 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
11.3.14 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 539
11.3.15 Using the GPIO pins in the backup supply domain . . . . . . . . . . . . . . . 539
11.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
11.4.1 GPIO port mode register (GPIOx_MODER)
(x =A to K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
11.4.2 GPIO port output type register (GPIOx_OTYPER)
(x = A to K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
11.4.3 GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
11.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
11.4.5 GPIO port input data register (GPIOx_IDR)
(x = A to K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
11.4.6 GPIO port output data register (GPIOx_ODR)
(x = A to K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
11.4.7 GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
11.4.8 GPIO port configuration lock register (GPIOx_LCKR)
(x = A to K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
11.4.9 GPIO alternate function low register (GPIOx_AFRL)
(x = A to K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
11.4.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A to J) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
11.4.11 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

12 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 548

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
12.2 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
12.3 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
12.3.1 SYSCFG peripheral mode configuration register (SYSCFG_PMCR) . 548

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12.3.2 SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
12.3.3 SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
12.3.4 SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
12.3.5 SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
12.3.6 SYSCFG configuration register (SYSCFG_CFGR) . . . . . . . . . . . . . . . 555
12.3.7 SYSCFG compensation cell control/status register
(SYSCFG_CCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
12.3.8 SYSCFG compensation cell value register (SYSCFG_CCVR) . . . . . . 559
12.3.9 SYSCFG compensation cell code register (SYSCFG_CCCR) . . . . . . 559
12.3.10 SYSCFG power control register (SYSCFG_PWRCR) . . . . . . . . . . . . . 560
12.3.11 SYSCFG package register (SYSCFG_PKGR) . . . . . . . . . . . . . . . . . . 560
12.3.12 SYSCFG user register 0 (SYSCFG_UR0) . . . . . . . . . . . . . . . . . . . . . . 562
12.3.13 SYSCFG user register 2 (SYSCFG_UR2) . . . . . . . . . . . . . . . . . . . . . . 562
12.3.14 SYSCFG user register 3 (SYSCFG_UR3) . . . . . . . . . . . . . . . . . . . . . . 563
12.3.15 SYSCFG user register 4 (SYSCFG_UR4) . . . . . . . . . . . . . . . . . . . . . . 563
12.3.16 SYSCFG user register 5 (SYSCFG_UR5) . . . . . . . . . . . . . . . . . . . . . . 564
12.3.17 SYSCFG user register 6 (SYSCFG_UR6) . . . . . . . . . . . . . . . . . . . . . . 564
12.3.18 SYSCFG user register 7 (SYSCFG_UR7) . . . . . . . . . . . . . . . . . . . . . . 565
12.3.19 SYSCFG user register 8 (SYSCFG_UR8) . . . . . . . . . . . . . . . . . . . . . . 565
12.3.20 SYSCFG user register 9 (SYSCFG_UR9) . . . . . . . . . . . . . . . . . . . . . . 566
12.3.21 SYSCFG user register 10 (SYSCFG_UR10) . . . . . . . . . . . . . . . . . . . . 566
12.3.22 SYSCFG user register 11 (SYSCFG_UR11) . . . . . . . . . . . . . . . . . . . . 567
12.3.23 SYSCFG user register 12 (SYSCFG_UR12) . . . . . . . . . . . . . . . . . . . . 567
12.3.24 SYSCFG user register 13 (SYSCFG_UR13) . . . . . . . . . . . . . . . . . . . . 568
12.3.25 SYSCFG user register 14 (SYSCFG_UR14) . . . . . . . . . . . . . . . . . . . . 569
12.3.26 SYSCFG user register 15 (SYSCFG_UR15) . . . . . . . . . . . . . . . . . . . . 570
12.3.27 SYSCFG user register 16 (SYSCFG_UR16) . . . . . . . . . . . . . . . . . . . . 571
12.3.28 SYSCFG user register 17 (SYSCFG_UR17) . . . . . . . . . . . . . . . . . . . . 571
12.3.29 SYSCFG register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

13 Block interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

13.1 Peripheral interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
13.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
13.1.2 Connection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

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13.2 Wakeup from low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

13.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
13.3.1 MDMA (D1 domain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
13.3.2 DMAMUX1, DMA1 and DMA2 (D2 domain) . . . . . . . . . . . . . . . . . . . . 602
13.3.3 DMAMUX2, BDMA (D3 domain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

14 MDMA controller (MDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

14.1 MDMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
14.2 MDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
14.3 MDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
14.3.1 MDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
14.3.2 MDMA internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
14.3.3 MDMA overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
14.3.4 MDMA channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
14.3.5 Source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 614
14.3.6 Pointer update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
14.3.7 MDMA buffer transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
14.3.8 Request arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
14.3.9 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
14.3.10 Block transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
14.3.11 Block repeat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
14.3.12 Linked-list mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
14.3.13 MDMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
14.3.14 MDMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
14.3.15 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
14.4 MDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
14.5 MDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
14.5.1 MDMA global interrupt status register (MDMA_GISR0) . . . . . . . . . . . 619
14.5.2 MDMA channel x interrupt status register (MDMA_CxISR) . . . . . . . . . 619
14.5.3 MDMA channel x interrupt flag clear register (MDMA_CxIFCR) . . . . . 621
14.5.4 MDMA channel x error status register (MDMA_CxESR) . . . . . . . . . . . 621
14.5.5 MDMA channel x control register (MDMA_CxCR) . . . . . . . . . . . . . . . . 622
14.5.6 MDMA channel x transfer configuration register (MDMA_CxTCR) . . . 624
14.5.7 MDMA channel x block number of data register (MDMA_CxBNDTR) . 628
14.5.8 MDMA channel x source address register (MDMA_CxSAR) . . . . . . . . 629
14.5.9 MDMA channel x destination address register (MDMA_CxDAR) . . . . 630

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14.5.10 MDMA channel x block repeat address update register

(MDMA_CxBRUR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
14.5.11 MDMA channel x link address register (MDMA_CxLAR) . . . . . . . . . . . 631
14.5.12 MDMA channel x trigger and bus selection register
(MDMA_CxTBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
14.5.13 MDMA channel x mask address register (MDMA_CxMAR) . . . . . . . . 633
14.5.14 MDMA channel x mask data register (MDMA_CxMDR) . . . . . . . . . . . 633
14.5.15 MDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 635

15.1 DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
15.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
15.3 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
15.3.1 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
15.3.2 DMA internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
15.3.3 DMA overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
15.3.4 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
15.3.5 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
15.3.6 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
15.3.7 DMA streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
15.3.8 Source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 639
15.3.9 Pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
15.3.10 Circular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
15.3.11 Double-buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
15.3.12 Programmable data width, packing/unpacking, endianness . . . . . . . . 645
15.3.13 Single and burst transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
15.3.14 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
15.3.15 DMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
15.3.16 DMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
15.3.17 Flow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
15.3.18 Summary of the possible DMA configurations . . . . . . . . . . . . . . . . . . . 653
15.3.19 Stream configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
15.3.20 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
15.4 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
15.5 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
15.5.1 DMA low interrupt status register (DMA_LISR) . . . . . . . . . . . . . . . . . . 656
15.5.2 DMA high interrupt status register (DMA_HISR) . . . . . . . . . . . . . . . . . 657

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15.5.3 DMA low interrupt flag clear register (DMA_LIFCR) . . . . . . . . . . . . . . 658

15.5.4 DMA high interrupt flag clear register (DMA_HIFCR) . . . . . . . . . . . . . 658
15.5.5 DMA stream x configuration register (DMA_SxCR) . . . . . . . . . . . . . . . 659
15.5.6 DMA stream x number of data register (DMA_SxNDTR) . . . . . . . . . . 662
15.5.7 DMA stream x peripheral address register (DMA_SxPAR) . . . . . . . . . 662
15.5.8 DMA stream x memory 0 address register
(DMA_SxM0AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
15.5.9 DMA stream x memory 1 address register
(DMA_SxM1AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
15.5.10 DMA stream x FIFO control register (DMA_SxFCR) . . . . . . . . . . . . . . 664
15.5.11 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

16 Basic direct memory access controller (BDMA) . . . . . . . . . . . . . . . . 669

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
16.2 BDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
16.3 BDMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
16.3.1 BDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
16.3.2 BDMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
16.4 BDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
16.4.1 BDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
16.4.2 BDMA pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
16.4.3 BDMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
16.4.4 BDMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
16.4.5 BDMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
16.4.6 BDMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . 677
16.4.7 BDMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
16.5 BDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
16.6 BDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
16.6.1 BDMA interrupt status register (BDMA_ISR) . . . . . . . . . . . . . . . . . . . . 679
16.6.2 BDMA interrupt flag clear register (BDMA_IFCR) . . . . . . . . . . . . . . . . 682
16.6.3 BDMA channel x configuration register (BDMA_CCRx) . . . . . . . . . . . 683
16.6.4 BDMA channel x number of data to transfer register
(BDMA_CNDTRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
16.6.5 BDMA channel x peripheral address register (BDMA_CPARx) . . . . . . 687
16.6.6 BDMA channel x memory 0 address register (BDMA_CM0ARx) . . . . 688
16.6.7 BDMA channel x memory 1 address register (BDMA_CM1ARx) . . . . 689
16.6.8 BDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

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17 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . 692

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
17.2 DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
17.3 DMAMUX implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
17.3.1 DMAMUX1 and DMAMUX2 instantiation . . . . . . . . . . . . . . . . . . . . . . . 693
17.3.2 DMAMUX1 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
17.3.3 DMAMUX2 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
17.4 DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
17.4.1 DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
17.4.2 DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
17.4.3 DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
17.4.4 DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
17.4.5 DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
17.5 DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
17.6 DMAMUX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
17.6.1 DMAMUX1 request line multiplexer channel x configuration register
(DMAMUX1_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
17.6.2 DMAMUX2 request line multiplexer channel x configuration register
(DMAMUX2_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
17.6.3 DMAMUX1 request line multiplexer interrupt channel status register
(DMAMUX1_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
17.6.4 DMAMUX2 request line multiplexer interrupt channel status register
(DMAMUX2_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
17.6.5 DMAMUX1 request line multiplexer interrupt clear flag register
(DMAMUX1_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
17.6.6 DMAMUX2 request line multiplexer interrupt clear flag register
(DMAMUX2_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
17.6.7 DMAMUX1 request generator channel x configuration register
(DMAMUX1_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
17.6.8 DMAMUX2 request generator channel x configuration register
(DMAMUX2_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
17.6.9 DMAMUX1 request generator interrupt status register
(DMAMUX1_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
17.6.10 DMAMUX2 request generator interrupt status register
(DMAMUX2_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
17.6.11 DMAMUX1 request generator interrupt clear flag register
(DMAMUX1_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
17.6.12 DMAMUX2 request generator interrupt clear flag register
(DMAMUX2_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
17.6.13 DMAMUX register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

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18 Chrom-ART Accelerator controller (DMA2D) . . . . . . . . . . . . . . . . . . . 715

18.1 DMA2D introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
18.2 DMA2D main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
18.3 DMA2D functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
18.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
18.3.2 DMA2D internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
18.3.3 DMA2D control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
18.3.4 DMA2D foreground and background FIFOs . . . . . . . . . . . . . . . . . . . . 718
18.3.5 DMA2D foreground and background PFC . . . . . . . . . . . . . . . . . . . . . . 718
18.3.6 DMA2D foreground and background CLUT interface . . . . . . . . . . . . . 720
18.3.7 DMA2D blender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
18.3.8 DMA2D output PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
18.3.9 DMA2D output FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
18.3.10 DMA2D output FIFO byte reordering . . . . . . . . . . . . . . . . . . . . . . . . . . 723
18.3.11 DMA2D AXI master port timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
18.3.12 DMA2D transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
18.3.13 DMA2D configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
18.3.14 YCbCr support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
18.3.15 DMA2D transfer control (start, suspend, abort, and completion) . . . . . 729
18.3.16 Watermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
18.3.17 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
18.3.18 AXI dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
18.4 DMA2D interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
18.5 DMA2D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
18.5.1 DMA2D control register (DMA2D_CR) . . . . . . . . . . . . . . . . . . . . . . . . 731
18.5.2 DMA2D interrupt status register (DMA2D_ISR) . . . . . . . . . . . . . . . . . 732
18.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . . . . . . . . . . . 733
18.5.4 DMA2D foreground memory address register (DMA2D_FGMAR) . . . 734
18.5.5 DMA2D foreground offset register (DMA2D_FGOR) . . . . . . . . . . . . . . 734
18.5.6 DMA2D background memory address register (DMA2D_BGMAR) . . 735
18.5.7 DMA2D background offset register (DMA2D_BGOR) . . . . . . . . . . . . . 735
18.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . . 736
18.5.9 DMA2D foreground color register (DMA2D_FGCOLR) . . . . . . . . . . . . 737
18.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . 738
18.5.11 DMA2D background color register (DMA2D_BGCOLR) . . . . . . . . . . . 739
18.5.12 DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740

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18.5.13 DMA2D background CLUT memory address register

(DMA2D_BGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
18.5.14 DMA2D output PFC control register (DMA2D_OPFCCR) . . . . . . . . . . 741
18.5.15 DMA2D output color register (DMA2D_OCOLR) . . . . . . . . . . . . . . . . . 742
18.5.16 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . . . . 742
18.5.17 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . . . . 743
18.5.18 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . . . . 743
18.5.19 DMA2D output memory address register (DMA2D_OMAR) . . . . . . . . 744
18.5.20 DMA2D output offset register (DMA2D_OOR) . . . . . . . . . . . . . . . . . . 744
18.5.21 DMA2D number of line register (DMA2D_NLR) . . . . . . . . . . . . . . . . . 745
18.5.22 DMA2D line watermark register (DMA2D_LWR) . . . . . . . . . . . . . . . . . 745
18.5.23 DMA2D AXI master timer configuration register (DMA2D_AMTCR) . . 746
18.5.24 DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . . . . . . . . . . . . . . 746
18.5.25 DMA2D background CLUT (DMA2D_BGCLUTx) . . . . . . . . . . . . . . . . 747
18.5.26 DMA2D register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747

19 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 749

19.1 NVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
19.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
19.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

20 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . 758

20.1 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
20.2 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
20.2.1 EXTI connections between peripherals, CPU, and D3 domain . . . . . . 759
20.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
20.3.1 EXTI Configurable event input CPU wakeup . . . . . . . . . . . . . . . . . . . . 761
20.3.2 EXTI configurable event input Any wakeup . . . . . . . . . . . . . . . . . . . . . 762
20.3.3 EXTI direct event input CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . 764
20.3.4 EXTI direct event input Any wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . 765
20.3.5 EXTI D3 pending request clear selection . . . . . . . . . . . . . . . . . . . . . . 766
20.4 EXTI event input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
20.5 EXTI functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
20.5.1 EXTI CPU interrupt procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
20.5.2 EXTI CPU event procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
20.5.3 EXTI CPU wakeup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
20.5.4 EXTI D3 domain wakeup for autonomous Run mode procedure . . . . 771

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20.5.5 EXTI software interrupt/event trigger procedure . . . . . . . . . . . . . . . . . 771

20.6 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
20.6.1 EXTI rising trigger selection register (EXTI_RTSR1) . . . . . . . . . . . . . . 772
20.6.2 EXTI falling trigger selection register (EXTI_FTSR1) . . . . . . . . . . . . . 772
20.6.3 EXTI software interrupt event register (EXTI_SWIER1) . . . . . . . . . . . 773
20.6.4 EXTI D3 pending mask register (EXTI_D3PMR1) . . . . . . . . . . . . . . . . 773
20.6.5 EXTI D3 pending clear selection register low (EXTI_D3PCR1L) . . . . 774
20.6.6 EXTI D3 pending clear selection register high (EXTI_D3PCR1H) . . . 774
20.6.7 EXTI rising trigger selection register (EXTI_RTSR2) . . . . . . . . . . . . . . 775
20.6.8 EXTI falling trigger selection register (EXTI_FTSR2) . . . . . . . . . . . . . 776
20.6.9 EXTI software interrupt event register (EXTI_SWIER2) . . . . . . . . . . . 776
20.6.10 EXTI D3 pending mask register (EXTI_D3PMR2) . . . . . . . . . . . . . . . . 777
20.6.11 EXTI D3 pending clear selection register low (EXTI_D3PCR2L) . . . . 778
20.6.12 EXTI D3 pending clear selection register high (EXTI_D3PCR2H) . . . 778
20.6.13 EXTI rising trigger selection register (EXTI_RTSR3) . . . . . . . . . . . . . . 779
20.6.14 EXTI falling trigger selection register (EXTI_FTSR3) . . . . . . . . . . . . . 779
20.6.15 EXTI software interrupt event register (EXTI_SWIER3) . . . . . . . . . . . 780
20.6.16 EXTI D3 pending mask register (EXTI_D3PMR3) . . . . . . . . . . . . . . . . 780
20.6.17 EXTI D3 pending clear selection register low (EXTI_D3PCR3L) . . . . 781
20.6.18 EXTI D3 pending clear selection register high (EXTI_D3PCR3H) . . . 781
20.6.19 EXTI interrupt mask register (EXTI_CPUIMR1) . . . . . . . . . . . . . . . . . 782
20.6.20 EXTI event mask register (EXTI_CPUEMR1) . . . . . . . . . . . . . . . . . . . 782
20.6.21 EXTI pending register (EXTI_CPUPR1) . . . . . . . . . . . . . . . . . . . . . . . 783
20.6.22 EXTI interrupt mask register (EXTI_CPUIMR2) . . . . . . . . . . . . . . . . . 783
20.6.23 EXTI event mask register (EXTI_CPUEMR2) . . . . . . . . . . . . . . . . . . . 784
20.6.24 EXTI pending register (EXTI_CPUPR2) . . . . . . . . . . . . . . . . . . . . . . . 784
20.6.25 EXTI interrupt mask register (EXTI_CPUIMR3) . . . . . . . . . . . . . . . . . 785
20.6.26 EXTI event mask register (EXTI_CPUEMR3) . . . . . . . . . . . . . . . . . . . 786
20.6.27 EXTI pending register (EXTI_CPUPR3) . . . . . . . . . . . . . . . . . . . . . . . 786
20.6.28 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

21 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 790

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
21.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
21.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
21.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
21.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

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21.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

21.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
21.4.1 CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
21.4.2 CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . 793
21.4.3 CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
21.4.4 CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
21.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
21.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

22 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797

22.1 FMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
22.2 FMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
22.3 FMC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
22.4 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
22.5 AXI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
22.5.1 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 801
22.6 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
22.6.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
22.6.2 NAND flash memory address mapping . . . . . . . . . . . . . . . . . . . . . . . . 804
22.6.3 SDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
22.7 NOR flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
22.7.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
22.7.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 811
22.7.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
22.7.4 NOR flash/PSRAM controller asynchronous transactions . . . . . . . . . . 813
22.7.5 Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
22.7.6 NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
22.8 NAND flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
22.8.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
22.8.2 NAND flash supported memories and transactions . . . . . . . . . . . . . . . 848
22.8.3 Timing diagrams for NAND flash memories . . . . . . . . . . . . . . . . . . . . . 849
22.8.4 NAND flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
22.8.5 NAND flash prewait feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
22.8.6 Computation of the error correction code (ECC)
in NAND flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
22.8.7 NAND flash controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853

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22.9 SDRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

22.9.1 SDRAM controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
22.9.2 SDRAM External memory interface signals . . . . . . . . . . . . . . . . . . . . . 859
22.9.3 SDRAM controller functional description . . . . . . . . . . . . . . . . . . . . . . . 860
22.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
22.9.5 SDRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
22.9.6 FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876

23 Quad-SPI interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
23.2 QUADSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
23.3 QUADSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
23.3.1 QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
23.3.2 QUADSPI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
23.3.3 QUADSPI command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
23.3.4 QUADSPI signal interface protocol modes . . . . . . . . . . . . . . . . . . . . . 883
23.3.5 QUADSPI indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
23.3.6 QUADSPI automatic status-polling mode . . . . . . . . . . . . . . . . . . . . . . 887
23.3.7 QUADSPI memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
23.3.8 QUADSPI free-running clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
23.3.9 QUADSPI flash memory configuration . . . . . . . . . . . . . . . . . . . . . . . . 888
23.3.10 QUADSPI delayed data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
23.3.11 QUADSPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
23.3.12 QUADSPI use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
23.3.13 Sending the instruction only once . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
23.3.14 QUADSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
23.3.15 QUADSPI busy bit and abort functionality . . . . . . . . . . . . . . . . . . . . . . 892
23.3.16 NCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
23.4 QUADSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
23.5 QUADSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
23.5.1 QUADSPI control register (QUADSPI_CR) . . . . . . . . . . . . . . . . . . . . . 895
23.5.2 QUADSPI device configuration register (QUADSPI_DCR) . . . . . . . . . 897
23.5.3 QUADSPI status register (QUADSPI_SR) . . . . . . . . . . . . . . . . . . . . . 898
23.5.4 QUADSPI flag clear register (QUADSPI_FCR) . . . . . . . . . . . . . . . . . . 899
23.5.5 QUADSPI data length register (QUADSPI_DLR) . . . . . . . . . . . . . . . . 900
23.5.6 QUADSPI communication configuration register (QUADSPI_CCR) . . 900

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23.5.7 QUADSPI address register (QUADSPI_AR) . . . . . . . . . . . . . . . . . . . . 902

23.5.8 QUADSPI alternate-byte register (QUADSPI_ABR) . . . . . . . . . . . . . . 903
23.5.9 QUADSPI data register (QUADSPI_DR) . . . . . . . . . . . . . . . . . . . . . . . 903
23.5.10 QUADSPI polling status mask register (QUADSPI_PSMKR) . . . . . . . 904
23.5.11 QUADSPI polling status match register (QUADSPI_PSMAR) . . . . . . 904
23.5.12 QUADSPI polling interval register (QUADSPI_PIR) . . . . . . . . . . . . . . 905
23.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . . . . . . . 905
23.5.14 QUADSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906

24 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
24.2 DLYB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
24.3 DLYB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
24.3.1 DLYB diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
24.3.2 DLYB pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
24.3.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
24.3.4 Delay line length configuration procedure . . . . . . . . . . . . . . . . . . . . . . 909
24.3.5 Output clock phase configuration procedure . . . . . . . . . . . . . . . . . . . . 909
24.4 DLYB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
24.4.1 DLYB control register (DLYB_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
24.4.2 DLYB configuration register (DLYB_CFGR) . . . . . . . . . . . . . . . . . . . . 910
24.4.3 DLYB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911

25 Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 912

25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
25.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
25.3 ADC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
25.4 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
25.4.1 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
25.4.2 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
25.4.3 ADC clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
25.4.4 ADC1/2/3 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
25.4.5 Slave AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
25.4.6 ADC deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
25.4.7 Single-ended and differential input channels . . . . . . . . . . . . . . . . . . . . 924
25.4.8 Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT) . . . . . 924

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25.4.9 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . . 930

25.4.10 Constraints when writing the ADC control bits . . . . . . . . . . . . . . . . . . . 931
25.4.11 Channel selection (SQRx, JSQRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
25.4.12 Channel preselection register (ADC_PCSEL) . . . . . . . . . . . . . . . . . . . 932
25.4.13 Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . . 933
25.4.14 Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
25.4.15 Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 934
25.4.16 Starting conversions (ADSTART, JADSTART) . . . . . . . . . . . . . . . . . . . 935
25.4.17 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
25.4.18 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . . 936
25.4.19 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,
JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
25.4.20 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
25.4.21 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . . 943
25.4.22 Queue of context for injected conversions . . . . . . . . . . . . . . . . . . . . . . 944
25.4.23 Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 952
25.4.24 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . 952
25.4.25 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . . 952
25.4.26 Timing diagrams example (single/continuous modes,
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
25.4.27 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
25.4.28 Managing conversions using the DFSDM . . . . . . . . . . . . . . . . . . . . . . 962
25.4.29 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
25.4.30 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) . . 967
25.4.31 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
25.4.32 Dual ADC modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
25.4.33 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
25.4.34 VBAT supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
25.4.35 Monitoring the internal voltage reference . . . . . . . . . . . . . . . . . . . . . . 993
25.5 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
25.6 ADC registers (for each ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
25.6.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 996
25.6.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 999
25.6.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
25.6.4 ADC configuration register (ADC_CFGR) . . . . . . . . . . . . . . . . . . . . . 1010
25.6.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . 1014
25.6.6 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . 1016

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25.6.7 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . 1017

25.6.8 ADC channel preselection register (ADC_PCSEL) . . . . . . . . . . . . . . 1018
25.6.9 ADC watchdog threshold register 1 (ADC_LTR1) . . . . . . . . . . . . . . . 1018
25.6.10 ADC watchdog threshold register 1 (ADC_HTR1) . . . . . . . . . . . . . . . 1019
25.6.11 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . 1020
25.6.12 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . 1021
25.6.13 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . 1022
25.6.14 ADC regular sequence register 4 (ADC_SQR4) . . . . . . . . . . . . . . . . 1023
25.6.15 ADC regular Data Register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . 1024
25.6.16 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . 1025
25.6.17 ADC injected channel y offset register (ADC_OFRy) . . . . . . . . . . . . 1027
25.6.18 ADC injected channel y data register (ADC_JDRy) . . . . . . . . . . . . . . 1028
25.6.19 ADC analog watchdog 2 configuration register
(ADC_AWD2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
25.6.20 ADC analog watchdog 3 configuration register
(ADC_AWD3CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
25.6.21 ADC watchdog lower threshold register 2 (ADC_LTR2) . . . . . . . . . . 1029
25.6.22 ADC watchdog higher threshold register 2 (ADC_HTR2) . . . . . . . . . 1030
25.6.23 ADC watchdog lower threshold register 3 (ADC_LTR3) . . . . . . . . . . 1030
25.6.24 ADC watchdog higher threshold register 3 (ADC_HTR3) . . . . . . . . . 1031
25.6.25 ADC differential mode selection register (ADC_DIFSEL) . . . . . . . . . 1031
25.6.26 ADC calibration factors register (ADC_CALFACT) . . . . . . . . . . . . . . 1032
25.6.27 ADC calibration factor register 2 (ADC_CALFACT2) . . . . . . . . . . . . . 1032
25.7 ADC common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
25.7.1 ADC x common status register (ADCx_CSR) (x=1/2 or 3) . . . . . . . . 1033
25.7.2 ADC x common control register (ADCx_CCR) (x=1/2 or 3) . . . . . . . . 1035
25.7.3 ADC x common regular data register for dual mode
(ADCx_CDR) (x=1/2 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
25.7.4 ADC x common regular data register for 32-bit dual mode
(ADCx_CDR2) (x=1/2 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
25.8 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040

26 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
26.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
26.3 DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
26.4 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
26.4.1 DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046

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26.4.2 DAC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047

26.4.3 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
26.4.4 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
26.4.5 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
26.4.6 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
26.4.7 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
26.4.8 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
26.4.9 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
26.4.10 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
26.4.11 DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
26.4.12 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
26.4.13 Dual DAC channel conversion modes (if dual channels are
available) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
26.5 DAC in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
26.6 DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
26.7 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
26.7.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
26.7.2 DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . 1067
26.7.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
26.7.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
26.7.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
26.7.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
26.7.7 DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
26.7.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
26.7.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
26.7.10 Dual DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
26.7.11 Dual DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
26.7.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . 1072
26.7.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . 1073
26.7.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
26.7.15 DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . 1075

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26.7.16 DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . 1075

26.7.17 DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
26.7.18 DAC channel2 sample and hold sample time register
(DAC_SHSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
26.7.19 DAC sample and hold time register (DAC_SHHR) . . . . . . . . . . . . . . 1078
26.7.20 DAC sample and hold refresh time register (DAC_SHRR) . . . . . . . . 1078
26.7.21 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079

27 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . 1081

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
27.2 VREFBUF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
27.3 VREFBUF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
27.3.1 VREFBUF control and status register (VREFBUF_CSR) . . . . . . . . . 1082
27.3.2 VREFBUF calibration control register (VREFBUF_CCR) . . . . . . . . . 1083
27.3.3 VREFBUF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083

28 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
28.2 COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
28.3 COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
28.3.1 COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
28.3.2 COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
28.3.3 COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
28.3.4 Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
28.3.5 Window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
28.3.6 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
28.3.7 Comparator output blanking function . . . . . . . . . . . . . . . . . . . . . . . . . 1088
28.3.8 Comparator output on GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
28.3.9 Comparator output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
28.3.10 COMP power and speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
28.4 COMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
28.5 COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
28.5.1 Interrupt through EXTI block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
28.5.2 Interrupt through NVIC of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
28.6 SCALER function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
28.7 COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093

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28.7.1 Comparator status register (COMP_SR) . . . . . . . . . . . . . . . . . . . . . . 1093

28.7.2 Comparator interrupt clear flag register (COMP_ICFR) . . . . . . . . . . 1093
28.7.3 Comparator option register (COMP_OR) . . . . . . . . . . . . . . . . . . . . . 1094
28.7.4 Comparator configuration register 1 (COMP_CFGR1) . . . . . . . . . . . 1094
28.7.5 Comparator configuration register 2 (COMP_CFGR2) . . . . . . . . . . . 1096
28.7.6 COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099

29 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100

29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1100
29.2 OPAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1100
29.3 OPAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1100
29.3.1 OPAMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
29.3.2 Initial configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
29.3.3 Signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
29.3.4 OPAMP modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102
29.3.5 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
29.4 OPAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
29.5 OPAMP PGA gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
29.6 OPAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
29.6.1 OPAMP1 control/status register (OPAMP1_CSR) . . . . . . . . . . . . . . . 1110
29.6.2 OPAMP1 trimming register in normal mode (OPAMP1_OTR) . . . . . . 1112
29.6.3 OPAMP1 trimming register in high-speed mode (OPAMP1_HSOTR) 1113
29.6.4 OPAMP option register (OPAMP_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1113
29.6.5 OPAMP2 control/status register (OPAMP2_CSR) . . . . . . . . . . . . . . . 1113
29.6.6 OPAMP2 trimming register in normal mode (OPAMP2_OTR) . . . . . . 1115
29.6.7 OPAMP2 trimming register in high-speed mode (OPAMP2_HSOTR) 1116
29.6.8 OPAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117

30 Digital filter for sigma delta modulators (DFSDM) . . . . . . . . . . . . . . 1118

30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
30.2 DFSDM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
30.3 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1120
30.4 DFSDM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1121
30.4.1 DFSDM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
30.4.2 DFSDM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
30.4.3 DFSDM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123

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30.4.4 Serial channel transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124

30.4.5 Configuring the input serial interface . . . . . . . . . . . . . . . . . . . . . . . . . 1134
30.4.6 Parallel data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
30.4.7 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
30.4.8 Digital filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
30.4.9 Integrator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
30.4.10 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
30.4.11 Short-circuit detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
30.4.12 Extreme detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
30.4.13 Data unit block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
30.4.14 Signed data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
30.4.15 Launching conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
30.4.16 Continuous and fast continuous modes . . . . . . . . . . . . . . . . . . . . . . . 1144
30.4.17 Request precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
30.4.18 Power optimization in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
30.5 DFSDM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1146
30.6 DFSDM DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1148
30.7 DFSDM channel y registers (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . .1148
30.7.1 DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . 1148
30.7.2 DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . 1150
30.7.3 DFSDM channel y analog watchdog and short-circuit detector register
(DFSDM_CHyAWSCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151
30.7.4 DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152
30.7.5 DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . . 1152
30.8 DFSDM filter x module registers (x=0..3) . . . . . . . . . . . . . . . . . . . . . . . .1153
30.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . . . . . . . . 1153
30.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . . . . . . . . 1156
30.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . 1157
30.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . 1159
30.8.5 DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
30.8.6 DFSDM filter x control register (DFSDM_FLTxFCR) . . . . . . . . . . . . . 1160
30.8.7 DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
30.8.8 DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162

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30.8.9 DFSDM filter x analog watchdog high threshold register

(DFSDM_FLTxAWHTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
30.8.10 DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
30.8.11 DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
30.8.12 DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
30.8.13 DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
30.8.14 DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
30.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . 1166
30.8.16 DFSDM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167

31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177

31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177
31.2 DCMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177
31.3 DCMI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177
31.3.1 DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
31.3.2 DCMI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
31.3.3 DCMI clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
31.3.4 DCMI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
31.3.5 DCMI physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
31.3.6 DCMI synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
31.3.7 DCMI capture modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
31.3.8 DCMI crop feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
31.3.9 DCMI JPEG format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
31.3.10 DCMI FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
31.3.11 DCMI data format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
31.4 DCMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1188
31.5 DCMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1189
31.5.1 DCMI control register (DCMI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
31.5.2 DCMI status register (DCMI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
31.5.3 DCMI raw interrupt status register (DCMI_RIS) . . . . . . . . . . . . . . . . 1192
31.5.4 DCMI interrupt enable register (DCMI_IER) . . . . . . . . . . . . . . . . . . . 1193
31.5.5 DCMI masked interrupt status register (DCMI_MIS) . . . . . . . . . . . . . 1194
31.5.6 DCMI interrupt clear register (DCMI_ICR) . . . . . . . . . . . . . . . . . . . . . 1195

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31.5.7 DCMI embedded synchronization code register (DCMI_ESCR) . . . . 1195

31.5.8 DCMI embedded synchronization unmask register (DCMI_ESUR) . 1196
31.5.9 DCMI crop window start (DCMI_CWSTRT) . . . . . . . . . . . . . . . . . . . . 1197
31.5.10 DCMI crop window size (DCMI_CWSIZE) . . . . . . . . . . . . . . . . . . . . . 1197
31.5.11 DCMI data register (DCMI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
31.5.12 DCMI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198

32 LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . 1200

32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
32.2 LTDC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
32.3 LTDC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
32.3.1 LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
32.3.2 LTDC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
32.3.3 LTDC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
32.4 LTDC programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
32.4.1 LTDC global configuration parameters . . . . . . . . . . . . . . . . . . . . . . . 1204
32.4.2 Layer programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
32.5 LTDC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
32.6 LTDC programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1211
32.7 LTDC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
32.7.1 LTDC synchronization size configuration register (LTDC_SSCR) . . . 1212
32.7.2 LTDC back porch configuration register (LTDC_BPCR) . . . . . . . . . . 1212
32.7.3 LTDC active width configuration register (LTDC_AWCR) . . . . . . . . . 1213
32.7.4 LTDC total width configuration register (LTDC_TWCR) . . . . . . . . . . . 1214
32.7.5 LTDC global control register (LTDC_GCR) . . . . . . . . . . . . . . . . . . . . 1214
32.7.6 LTDC shadow reload configuration register (LTDC_SRCR) . . . . . . . 1216
32.7.7 LTDC background color configuration register (LTDC_BCCR) . . . . . 1216
32.7.8 LTDC interrupt enable register (LTDC_IER) . . . . . . . . . . . . . . . . . . . 1217
32.7.9 LTDC interrupt status register (LTDC_ISR) . . . . . . . . . . . . . . . . . . . . 1218
32.7.10 LTDC interrupt clear register (LTDC_ICR) . . . . . . . . . . . . . . . . . . . . . 1218
32.7.11 LTDC line interrupt position configuration register (LTDC_LIPCR) . . 1219
32.7.12 LTDC current position status register (LTDC_CPSR) . . . . . . . . . . . . 1219
32.7.13 LTDC current display status register (LTDC_CDSR) . . . . . . . . . . . . . 1220
32.7.14 LTDC layer x control register (LTDC_LxCR) . . . . . . . . . . . . . . . . . . . 1220
32.7.15 LTDC layer x window horizontal position configuration register
(LTDC_LxWHPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221

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32.7.16 LTDC layer x window vertical position configuration register

(LTDC_LxWVPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222
32.7.17 LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
32.7.18 LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
32.7.19 LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
32.7.20 LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
32.7.21 LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
32.7.22 LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
32.7.23 LTDC layer x color frame buffer length register
(LTDC_LxCFBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
32.7.24 LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227
32.7.25 LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . . . . . . . 1227
32.7.26 LTDC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228

33 JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231

33.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231
33.2 JPEG codec main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231
33.3 JPEG codec block functional description . . . . . . . . . . . . . . . . . . . . . . . 1232
33.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
33.3.2 JPEG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
33.3.3 JPEG decoding procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
33.3.4 JPEG encoding procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
33.4 JPEG codec interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236
33.5 JPEG codec registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237
33.5.1 JPEG codec control register (JPEG_CONFR0) . . . . . . . . . . . . . . . . 1237
33.5.2 JPEG codec configuration register 1 (JPEG_CONFR1) . . . . . . . . . . 1237
33.5.3 JPEG codec configuration register 2 (JPEG_CONFR2) . . . . . . . . . . 1238
33.5.4 JPEG codec configuration register 3 (JPEG_CONFR3) . . . . . . . . . . 1239
33.5.5 JPEG codec configuration register x (JPEG_CONFRx) . . . . . . . . . . 1239
33.5.6 JPEG control register (JPEG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
33.5.7 JPEG status register (JPEG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241
33.5.8 JPEG clear flag register (JPEG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . 1242

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33.5.9 JPEG data input register (JPEG_DIR) . . . . . . . . . . . . . . . . . . . . . . . . 1243

33.5.10 JPEG data output register (JPEG_DOR) . . . . . . . . . . . . . . . . . . . . . . 1243
33.5.11 JPEG quantization memory x (JPEG_QMEMx_y) . . . . . . . . . . . . . . . 1244
33.5.12 JPEG Huffman min (JPEG_HUFFMINx_y) . . . . . . . . . . . . . . . . . . . . 1244
33.5.13 JPEG Huffman min x [alternate] (JPEG_HUFFMINx_y) . . . . . . . . . . 1245
33.5.14 JPEG Huffman base (JPEG_HUFFBASEx) . . . . . . . . . . . . . . . . . . . 1245
33.5.15 JPEG Huffman symbol (JPEG_HUFFSYMBx) . . . . . . . . . . . . . . . . . 1246
33.5.16 JPEG DHT memory (JPEG_DHTMEMx) . . . . . . . . . . . . . . . . . . . . . . 1247
33.5.17 JPEG Huffman encoder ACx (JPEG_HUFFENC_ACx_y) . . . . . . . . . 1247
33.5.18 JPEG Huffman encoder DCx (JPEG_HUFFENC_DCx_y) . . . . . . . . 1248
33.5.19 JPEG codec register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249

34 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . 1251

34.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
34.2 RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
34.3 RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
34.3.1 RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
34.3.2 RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
34.3.3 Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
34.3.4 RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
34.3.5 RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
34.3.6 RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
34.3.7 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
34.3.8 In this case application must clear the SEIS bit interrupt flag. RNG low-
power use 1258
34.4 RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
34.5 RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
34.6 RNG entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
34.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
34.6.2 Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
34.6.3 Data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
34.7 RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
34.7.1 RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
34.7.2 RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
34.7.3 RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
34.7.4 RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262

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35 Cryptographic processor (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263

35.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
35.2 CRYP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
35.3 CRYP implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264
35.4 CRYP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
35.4.1 CRYP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
35.4.2 CRYP internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
35.4.3 CRYP DES/TDES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . 1266
35.4.4 CRYP AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
35.4.5 CRYP procedure to perform a cipher operation . . . . . . . . . . . . . . . . . 1273
35.4.6 CRYP busy state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
35.4.7 Preparing the CRYP AES key for decryption . . . . . . . . . . . . . . . . . . . 1276
35.4.8 CRYP stealing and data padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276
35.4.9 CRYP suspend/resume operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
35.4.10 CRYP DES/TDES basic chaining modes (ECB, CBC) . . . . . . . . . . . 1279
35.4.11 CRYP AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . 1284
35.4.12 CRYP AES counter mode (AES-CTR) . . . . . . . . . . . . . . . . . . . . . . . . 1289
35.4.13 CRYP AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . 1293
35.4.14 CRYP AES Galois message authentication code (GMAC) . . . . . . . . 1298
35.4.15 CRYP AES Counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . 1299
35.4.16 CRYP data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . 1304
35.4.17 CRYP key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
35.4.18 CRYP initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
35.4.19 CRYP DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309
35.4.20 CRYP error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311
35.5 CRYP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
35.6 CRYP processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313
35.7 CRYP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
35.7.1 CRYP control register (CRYP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
35.7.2 CRYP status register (CRYP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316
35.7.3 CRYP data input register (CRYP_DIN) . . . . . . . . . . . . . . . . . . . . . . . 1317
35.7.4 CRYP data output register (CRYP_DOUT) . . . . . . . . . . . . . . . . . . . . 1317
35.7.5 CRYP DMA control register (CRYP_DMACR) . . . . . . . . . . . . . . . . . . 1318
35.7.6 CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . . . . . . . 1319
35.7.7 CRYP raw interrupt status register (CRYP_RISR) . . . . . . . . . . . . . . 1319
35.7.8 CRYP masked interrupt status register (CRYP_MISR) . . . . . . . . . . . 1320

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35.7.9 CRYP key register 0L (CRYP_K0LR) . . . . . . . . . . . . . . . . . . . . . . . . 1321

35.7.10 CRYP key register 0R (CRYP_K0RR) . . . . . . . . . . . . . . . . . . . . . . . . 1321
35.7.11 CRYP key register 1L (CRYP_K1LR) . . . . . . . . . . . . . . . . . . . . . . . . 1322
35.7.12 CRYP key register 1R (CRYP_K1RR) . . . . . . . . . . . . . . . . . . . . . . . . 1322
35.7.13 CRYP key register 2L (CRYP_K2LR) . . . . . . . . . . . . . . . . . . . . . . . . 1323
35.7.14 CRYP key register 2R (CRYP_K2RR) . . . . . . . . . . . . . . . . . . . . . . . . 1323
35.7.15 CRYP key register 3L (CRYP_K3LR) . . . . . . . . . . . . . . . . . . . . . . . . 1324
35.7.16 CRYP key register 3R (CRYP_K3RR) . . . . . . . . . . . . . . . . . . . . . . . . 1324
35.7.17 CRYP initialization vector register 0L (CRYP_IV0LR) . . . . . . . . . . . . 1325
35.7.18 CRYP initialization vector register 0R (CRYP_IV0RR) . . . . . . . . . . . 1325
35.7.19 CRYP initialization vector register 1L (CRYP_IV1LR) . . . . . . . . . . . . 1326
35.7.20 CRYP initialization vector register 1R (CRYP_IV1RR) . . . . . . . . . . . 1326
35.7.21 CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) 1326
35.7.22 CRYP context swap GCM registers (CRYP_CSGCMxR) . . . . . . . . . 1327
35.7.23 CRYP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327

36 Hash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330

36.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330
36.2 HASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330
36.3 HASH implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331
36.4 HASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331
36.4.1 HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331
36.4.2 HASH internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332
36.4.3 About secure hash algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332
36.4.4 Message data feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332
36.4.5 Message digest computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334
36.4.6 Message padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1335
36.4.7 HMAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1337
36.4.8 HASH suspend/resume operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1339
36.4.9 HASH DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
36.4.10 HASH error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
36.5 HASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
36.6 HASH processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342
36.7 HASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
36.7.1 HASH control register (HASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
36.7.2 HASH data input register (HASH_DIN) . . . . . . . . . . . . . . . . . . . . . . . 1345

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36.7.3 HASH start register (HASH_STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346

36.7.4 HASH digest registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
36.7.5 HASH interrupt enable register (HASH_IMR) . . . . . . . . . . . . . . . . . . 1348
36.7.6 HASH status register (HASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
36.7.7 HASH context swap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
36.7.8 HASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1350

37 High-Resolution Timer (HRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352

37.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352
37.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
37.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
37.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
37.3.2 HRTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
37.3.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
37.3.4 Timer A..E timing units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
37.3.5 Master timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377
37.3.6 Set/reset events priorities and narrow pulses management . . . . . . . 1378
37.3.7 External events global conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
37.3.8 External event filtering in timing units . . . . . . . . . . . . . . . . . . . . . . . . 1384
37.3.9 Delayed Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389
37.3.10 Register preload and update management . . . . . . . . . . . . . . . . . . . . 1395
37.3.11 Events propagation within or across multiple timers . . . . . . . . . . . . . 1398
37.3.12 Output management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
37.3.13 Burst mode controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404
37.3.14 Chopper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413
37.3.15 Fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414
37.3.16 Auxiliary outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417
37.3.17 Synchronizing the HRTIM with other timers or HRTIM instances . . . 1420
37.3.18 ADC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
37.3.19 DAC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
37.3.20 HRTIM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426
37.3.21 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1428
37.3.22 HRTIM initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1431
37.3.23 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432
37.4 Application use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433
37.4.1 Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433
37.4.2 Buck converter with synchronous rectification . . . . . . . . . . . . . . . . . . 1434

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37.4.3 Multiphase converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1435

37.4.4 Transition mode Power Factor Correction . . . . . . . . . . . . . . . . . . . . . 1437
37.5 HRTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439
37.5.1 HRTIM Master Timer Control Register (HRTIM_MCR) . . . . . . . . . . . 1439
37.5.2 HRTIM Master Timer Interrupt Status Register (HRTIM_MISR) . . . . 1442
37.5.3 HRTIM Master Timer Interrupt Clear Register (HRTIM_MICR) . . . . . 1443
37.5.4 HRTIM Master Timer DMA / Interrupt Enable Register
(HRTIM_MDIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444
37.5.5 HRTIM Master Timer Counter Register (HRTIM_MCNTR) . . . . . . . . 1446
37.5.6 HRTIM Master Timer Period Register (HRTIM_MPER) . . . . . . . . . . . 1446
37.5.7 HRTIM Master Timer Repetition Register (HRTIM_MREP) . . . . . . . . 1447
37.5.8 HRTIM Master Timer Compare 1 Register (HRTIM_MCMP1R) . . . . 1447
37.5.9 HRTIM Master Timer Compare 2 Register (HRTIM_MCMP2R) . . . . 1448
37.5.10 HRTIM Master Timer Compare 3 Register (HRTIM_MCMP3R) . . . . 1448
37.5.11 HRTIM Master Timer Compare 4 Register (HRTIM_MCMP4R) . . . . 1449
37.5.12 HRTIM Timerx Control Register (HRTIM_TIMxCR) . . . . . . . . . . . . . . 1450
37.5.13 HRTIM Timerx Interrupt Status Register (HRTIM_TIMxISR) . . . . . . . 1454
37.5.14 HRTIM Timerx Interrupt Clear Register (HRTIM_TIMxICR) . . . . . . . 1456
37.5.15 HRTIM Timerx DMA / Interrupt Enable Register
(HRTIM_TIMxDIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457
37.5.16 HRTIM Timerx Counter Register (HRTIM_CNTxR) . . . . . . . . . . . . . . 1460
37.5.17 HRTIM Timerx Period Register (HRTIM_PERxR) . . . . . . . . . . . . . . . 1460
37.5.18 HRTIM Timerx Repetition Register (HRTIM_REPxR) . . . . . . . . . . . . 1461
37.5.19 HRTIM Timerx Compare 1 Register (HRTIM_CMP1xR) . . . . . . . . . . 1461
37.5.20 HRTIM Timerx Compare 1 Compound Register
(HRTIM_CMP1CxR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
37.5.21 HRTIM Timerx Compare 2 Register (HRTIM_CMP2xR) . . . . . . . . . . 1462
37.5.22 HRTIM Timerx Compare 3 Register (HRTIM_CMP3xR) . . . . . . . . . . 1463
37.5.23 HRTIM Timerx Compare 4 Register (HRTIM_CMP4xR) . . . . . . . . . . 1463
37.5.24 HRTIM Timerx Capture 1 Register (HRTIM_CPT1xR) . . . . . . . . . . . 1464
37.5.25 HRTIM Timerx Capture 2 Register (HRTIM_CPT2xR) . . . . . . . . . . . 1464
37.5.26 HRTIM Timerx Deadtime Register (HRTIM_DTxR) . . . . . . . . . . . . . . 1465
37.5.27 HRTIM Timerx Output1 Set Register (HRTIM_SETx1R) . . . . . . . . . . 1467
37.5.28 HRTIM Timerx Output1 Reset Register (HRTIM_RSTx1R) . . . . . . . . 1469
37.5.29 HRTIM Timerx Output2 Set Register (HRTIM_SETx2R) . . . . . . . . . . 1469
37.5.30 HRTIM Timerx Output2 Reset Register (HRTIM_RSTx2R) . . . . . . . . 1470
37.5.31 HRTIM Timerx External Event Filtering Register 1
(HRTIM_EEFxR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471

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37.5.32 HRTIM Timerx External Event Filtering Register 2

(HRTIM_EEFxR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1473
37.5.33 HRTIM Timerx Reset Register (HRTIM_RSTxR) . . . . . . . . . . . . . . . . 1474
37.5.34 HRTIM Timerx Chopper Register (HRTIM_CHPxR) . . . . . . . . . . . . . 1477
37.5.35 HRTIM Timerx Capture 1 Control Register (HRTIM_CPT1xCR) . . . . 1479
37.5.36 HRTIM Timerx Capture 2 Control Register (HRTIM_CPT2xCR) . . . . 1480
37.5.37 HRTIM Timerx Output Register (HRTIM_OUTxR) . . . . . . . . . . . . . . . 1483
37.5.38 HRTIM Timerx Fault Register (HRTIM_FLTxR) . . . . . . . . . . . . . . . . . 1486
37.5.39 HRTIM Control Register 1 (HRTIM_CR1) . . . . . . . . . . . . . . . . . . . . . 1487
37.5.40 HRTIM Control Register 2 (HRTIM_CR2) . . . . . . . . . . . . . . . . . . . . . 1489
37.5.41 HRTIM Interrupt Status Register (HRTIM_ISR) . . . . . . . . . . . . . . . . . 1490
37.5.42 HRTIM Interrupt Clear Register (HRTIM_ICR) . . . . . . . . . . . . . . . . . 1491
37.5.43 HRTIM Interrupt Enable Register (HRTIM_IER) . . . . . . . . . . . . . . . . 1492
37.5.44 HRTIM Output Enable Register (HRTIM_OENR) . . . . . . . . . . . . . . . 1493
37.5.45 HRTIM Output Disable Register (HRTIM_ODISR) . . . . . . . . . . . . . . 1494
37.5.46 HRTIM Output Disable Status Register (HRTIM_ODSR) . . . . . . . . . 1495
37.5.47 HRTIM Burst Mode Control Register (HRTIM_BMCR) . . . . . . . . . . . 1496
37.5.48 HRTIM Burst Mode Trigger Register (HRTIM_BMTRGR) . . . . . . . . . 1498
37.5.49 HRTIM Burst Mode Compare Register (HRTIM_BMCMPR) . . . . . . . 1500
37.5.50 HRTIM Burst Mode Period Register (HRTIM_BMPER) . . . . . . . . . . . 1500
37.5.51 HRTIM Timer External Event Control Register 1 (HRTIM_EECR1) . 1501
37.5.52 HRTIM Timer External Event Control Register 2 (HRTIM_EECR2) . 1503
37.5.53 HRTIM Timer External Event Control Register 3 (HRTIM_EECR3) . 1504
37.5.54 HRTIM ADC Trigger 1 Register (HRTIM_ADC1R) . . . . . . . . . . . . . . . 1505
37.5.55 HRTIM ADC Trigger 2 Register (HRTIM_ADC2R) . . . . . . . . . . . . . . . 1506
37.5.56 HRTIM ADC Trigger 3 Register (HRTIM_ADC3R) . . . . . . . . . . . . . . . 1507
37.5.57 HRTIM ADC Trigger 4 Register (HRTIM_ADC4R) . . . . . . . . . . . . . . . 1509
37.5.58 HRTIM Fault Input Register 1 (HRTIM_FLTINR1) . . . . . . . . . . . . . . . 1511
37.5.59 HRTIM Fault Input Register 2 (HRTIM_FLTINR2) . . . . . . . . . . . . . . . 1513
37.5.60 HRTIM Burst DMA Master timer update Register
(HRTIM_BDMUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515
37.5.61 HRTIM Burst DMA Timerx update Register (HRTIM_BDTxUPR) . . . 1516
37.5.62 HRTIM Burst DMA Data Register (HRTIM_BDMADR) . . . . . . . . . . . 1517
37.5.63 HRTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518

38 Advanced-control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 1527

38.1 TIM1/TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527

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38.2 TIM1/TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527

38.3 TIM1/TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
38.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
38.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
38.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542
38.3.4 External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
38.3.5 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545
38.3.6 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549
38.3.7 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551
38.3.8 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552
38.3.9 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553
38.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554
38.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
38.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558
38.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
38.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
38.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1561
38.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563
38.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569
38.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . 1569
38.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571
38.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
38.3.21 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573
38.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574
38.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576
38.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577
38.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577
38.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580
38.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584
38.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584
38.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585
38.4 TIM1/TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586
38.4.1 TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . 1586
38.4.2 TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . 1587
38.4.3 TIMx slave mode control register
(TIMx_SMCR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590

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38.4.4 TIMx DMA/interrupt enable register

(TIMx_DIER)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
38.4.5 TIMx status register (TIMx_SR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . 1594
38.4.6 TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . . . . . . . . . 1596
38.4.7 TIMx capture/compare mode register 1(TIMx_CCMR1)(x = 1, 8) . . . 1597
38.4.8 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598
38.4.9 TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) . . 1601
38.4.10 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602
38.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
38.4.12 TIMx counter (TIMx_CNT)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
38.4.13 TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . 1607
38.4.14 TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . . . . . . . . . . . . . 1607
38.4.15 TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . . . . . . . . 1608
38.4.16 TIMx capture/compare register 1
(TIMx_CCR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
38.4.17 TIMx capture/compare register 2
(TIMx_CCR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
38.4.18 TIMx capture/compare register 3
(TIMx_CCR3)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
38.4.19 TIMx capture/compare register 4
(TIMx_CCR4)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
38.4.20 TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
38.4.21 TIMx DMA control register
(TIMx_DCR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
38.4.22 TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
38.4.23 TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615
38.4.24 TIMx capture/compare register 5
(TIMx_CCR5)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616
38.4.25 TIMx capture/compare register 6
(TIMx_CCR6)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
38.4.26 TIM1 alternate function option register 1 (TIM1_AF1) . . . . . . . . . . . . 1617
38.4.27 TIM1 Alternate function register 2 (TIM1_AF2) . . . . . . . . . . . . . . . . . 1619
38.4.28 TIM8 Alternate function option register 1 (TIM8_AF1) . . . . . . . . . . . . 1620
38.4.29 TIM8 Alternate function option register 2 (TIM8_AF2) . . . . . . . . . . . . 1622
38.4.30 TIM1 timer input selection register (TIM1_TISEL) . . . . . . . . . . . . . . . 1624

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38.4.31 TIM8 timer input selection register (TIM8_TISEL) . . . . . . . . . . . . . . . 1624

38.4.32 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626
38.4.33 TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628

39 General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . . . . . . . . . . . . . 1631

39.1 TIM2/TIM3/TIM4/TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
39.2 TIM2/TIM3/TIM4/TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
39.3 TIM2/TIM3/TIM4/TIM5 functional description . . . . . . . . . . . . . . . . . . . . 1633
39.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
39.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
39.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645
39.3.4 Capture/Compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
39.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
39.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
39.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
39.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
39.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
39.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
39.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
39.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . 1659
39.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661
39.3.14 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
39.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663
39.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
39.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
39.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . 1666
39.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
39.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674
39.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675
39.4 TIM2/TIM3/TIM4/TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
39.4.1 TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . . . . . . . . . . . . . . 1676
39.4.2 TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . . . . . . . . . . . . . . 1677
39.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . . . . 1679
39.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . . . 1682
39.4.5 TIMx status register (TIMx_SR)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . 1683
39.4.6 TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . . . . . . . 1684
39.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . 1686

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39.4.8 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)

(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
39.4.9 TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . 1690
39.4.10 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691
39.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
39.4.12 TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . 1693
39.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . . . . . . . . . . . . . 1694
39.4.14 TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . 1694
39.4.15 TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . . . . . . . . . . . 1695
39.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . . . . 1695
39.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . . . . 1696
39.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . . . . 1696
39.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . . . . 1697
39.4.20 TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . . . . . . . . . . . 1698
39.4.21 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . . . 1698
39.4.22 TIM2 alternate function option register 1 (TIM2_AF1) . . . . . . . . . . . . 1699
39.4.23 TIM3 alternate function option register 1 (TIM3_AF1) . . . . . . . . . . . . 1699
39.4.24 TIM4 alternate function option register 1 (TIM4_AF1) . . . . . . . . . . . . 1700
39.4.25 TIM5 alternate function option register 1 (TIM5_AF1) . . . . . . . . . . . . 1700
39.4.26 TIM2 timer input selection register (TIM2_TISEL) . . . . . . . . . . . . . . . 1701
39.4.27 TIM3 timer input selection register (TIM3_TISEL) . . . . . . . . . . . . . . . 1701
39.4.28 TIM4 timer input selection register (TIM4_TISEL) . . . . . . . . . . . . . . . 1702
39.4.29 TIM5 timer input selection register (TIM5_TISEL) . . . . . . . . . . . . . . . 1703
39.4.30 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705

40 General-purpose timers (TIM12/TIM13/TIM14) . . . . . . . . . . . . . . . . . 1708

40.1 TIM12/TIM13/TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
40.2 TIM12/TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
40.2.1 TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
40.2.2 TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
40.3 TIM12/TIM13/TIM14 functional description . . . . . . . . . . . . . . . . . . . . . .1711
40.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711
40.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
40.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716
40.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
40.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720

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40.3.6 PWM input mode (only for TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721

40.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
40.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
40.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724
40.3.10 Combined PWM mode (TIM12 only) . . . . . . . . . . . . . . . . . . . . . . . . . 1725
40.3.11 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
40.3.12 Retriggerable one pulse mode (TIM12 only) . . . . . . . . . . . . . . . . . . . 1728
40.3.13 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
40.3.14 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
40.3.15 TIM12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 1729
40.3.16 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . 1732
40.3.17 Timer synchronization (TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
40.3.18 Using timer output as trigger for other timers (TIM13/TIM14) . . . . . . 1733
40.3.19 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
40.4 TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
40.4.1 TIM12 control register 1 (TIM12_CR1) . . . . . . . . . . . . . . . . . . . . . . . 1733
40.4.2 TIM12 control register 2 (TIM12_CR2) . . . . . . . . . . . . . . . . . . . . . . . 1734
40.4.3 TIM12 slave mode control register (TIM12_SMCR) . . . . . . . . . . . . . 1735
40.4.4 TIM12 Interrupt enable register (TIM12_DIER) . . . . . . . . . . . . . . . . . 1737
40.4.5 TIM12 status register (TIM12_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
40.4.6 TIM12 event generation register (TIM12_EGR) . . . . . . . . . . . . . . . . 1738
40.4.7 TIM12 capture/compare mode register 1 (TIM12_CCMR1) . . . . . . . 1739
40.4.8 TIM12 capture/compare mode register 1 [alternate]
(TIM12_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
40.4.9 TIM12 capture/compare enable register (TIM12_CCER) . . . . . . . . . 1743
40.4.10 TIM12 counter (TIM12_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
40.4.11 TIM12 prescaler (TIM12_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
40.4.12 TIM12 auto-reload register (TIM12_ARR) . . . . . . . . . . . . . . . . . . . . . 1745
40.4.13 TIM12 capture/compare register 1 (TIM12_CCR1) . . . . . . . . . . . . . . 1745
40.4.14 TIM12 capture/compare register 2 (TIM12_CCR2) . . . . . . . . . . . . . . 1746
40.4.15 TIM12 timer input selection register (TIM12_TISEL) . . . . . . . . . . . . . 1746
40.4.16 TIM12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
40.5 TIM13/TIM14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
40.5.1 TIMx control register 1 (TIMx_CR1)(x = 13 to 14) . . . . . . . . . . . . . . . 1749
40.5.2 TIMx Interrupt enable register (TIMx_DIER)(x = 13 to 14) . . . . . . . . 1750
40.5.3 TIMx status register (TIMx_SR)(x = 13 to 14) . . . . . . . . . . . . . . . . . . 1750
40.5.4 TIMx event generation register (TIMx_EGR)(x = 13 to 14) . . . . . . . . 1751

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40.5.5 TIMx capture/compare mode register 1

(TIMx_CCMR1)(x = 13 to 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752
40.5.6 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 13 to 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
40.5.7 TIMx capture/compare enable register
(TIMx_CCER)(x = 13 to 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1755
40.5.8 TIMx counter (TIMx_CNT)(x = 13 to 14) . . . . . . . . . . . . . . . . . . . . . . 1756
40.5.9 TIMx prescaler (TIMx_PSC)(x = 13 to 14) . . . . . . . . . . . . . . . . . . . . . 1757
40.5.10 TIMx auto-reload register (TIMx_ARR)(x = 13 to 14) . . . . . . . . . . . . 1757
40.5.11 TIMx capture/compare register 1 (TIMx_CCR1)(x = 13 to 14) . . . . . 1757
40.5.12 TIM13 timer input selection register (TIM13_TISEL) . . . . . . . . . . . . . 1758
40.5.13 TIM14 timer input selection register (TIM14_TISEL) . . . . . . . . . . . . . 1758
40.5.14 TIM13/TIM14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759

41 General-purpose timers (TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . 1761

41.1 TIM15/TIM16/TIM17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
41.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
41.3 TIM16/TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
41.4 TIM15/TIM16/TIM17 functional description . . . . . . . . . . . . . . . . . . . . . 1765
41.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1765
41.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
41.4.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
41.4.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1772
41.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1774
41.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1776
41.4.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1777
41.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778
41.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779
41.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1780
41.4.11 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . 1781
41.4.12 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1782
41.4.13 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784
41.4.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
41.4.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
41.4.16 Retriggerable one pulse mode (TIM15 only) . . . . . . . . . . . . . . . . . . . 1791
41.4.17 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792
41.4.18 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . 1793
41.4.19 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . 1794

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41.4.20 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . 1796

41.4.21 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796
41.4.22 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798
41.4.23 Using timer output as trigger for other timers (TIM16/TIM17) . . . . . . 1798
41.4.24 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798
41.5 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1799
41.5.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . 1799
41.5.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . 1800
41.5.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . 1802
41.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . 1803
41.5.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
41.5.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . 1806
41.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . 1807
41.5.8 TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1808
41.5.9 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . 1811
41.5.10 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1814
41.5.11 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1814
41.5.12 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . 1814
41.5.13 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . 1815
41.5.14 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . 1815
41.5.15 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . 1816
41.5.16 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . 1816
41.5.17 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . 1819
41.5.18 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . 1819
41.5.19 TIM15 alternate register 1 (TIM15_AF1) . . . . . . . . . . . . . . . . . . . . . . 1820
41.5.20 TIM15 input selection register (TIM15_TISEL) . . . . . . . . . . . . . . . . . 1821
41.5.21 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
41.6 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1824
41.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . 1824
41.6.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . 1825
41.6.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . 1826
41.6.4 TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . 1827
41.6.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . 1828
41.6.6 TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829
41.6.7 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830

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41.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . 1832

41.6.9 TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 1834
41.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . 1835
41.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . . . . . . . . 1835
41.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . 1836
41.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . 1836
41.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . 1837
41.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . 1839
41.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . 1840
41.6.17 TIM16 alternate function register 1 (TIM16_AF1) . . . . . . . . . . . . . . . 1841
41.6.18 TIM16 input selection register (TIM16_TISEL) . . . . . . . . . . . . . . . . . 1842
41.6.19 TIM17 alternate function register 1 (TIM17_AF1) . . . . . . . . . . . . . . . 1843
41.6.20 TIM17 input selection register (TIM17_TISEL) . . . . . . . . . . . . . . . . . 1844
41.6.21 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1845

42 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847

42.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
42.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
42.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1848
42.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1848
42.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
42.3.3 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853
42.3.4 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853
42.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854
42.4 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854
42.4.1 TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . . . . . . . . . . . . . . 1854
42.4.2 TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . . . . . . . . . . . . . . 1856
42.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . . . 1856
42.4.4 TIMx status register (TIMx_SR)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . 1857
42.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . . . . . . . 1857
42.4.6 TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . . 1857
42.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . 1858
42.4.8 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . . . . . . . . . . . 1858
42.4.9 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859

43 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860

43.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860

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43.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860

43.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
43.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
43.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
43.4.2 LPTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
43.4.3 LPTIM input and trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
43.4.4 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
43.4.5 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
43.4.6 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867
43.4.7 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1868
43.4.8 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1868
43.4.9 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1870
43.4.10 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1870
43.4.11 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1871
43.4.12 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1872
43.4.13 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1872
43.4.14 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1873
43.4.15 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1873
43.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
43.5 LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
43.6 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1876
43.7 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1876
43.7.1 LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . 1877
43.7.2 LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . 1878
43.7.3 LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . 1878
43.7.4 LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . 1879
43.7.5 LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 1882
43.7.6 LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . 1884
43.7.7 LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . 1884
43.7.8 LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 1885
43.7.9 LPTIM configuration register 2 (LPTIM_CFGR2) . . . . . . . . . . . . . . . 1885
43.7.10 LPTIM3 configuration register 2 (LPTIM3_CFGR2) . . . . . . . . . . . . . 1886
43.7.11 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887

44 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . 1888

44.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888

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44.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888

44.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888
44.3.1 WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
44.3.2 WWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
44.3.3 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
44.3.4 Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
44.3.5 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . 1890
44.3.6 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
44.4 WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
44.5 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
44.5.1 WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . 1892
44.5.2 WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . 1892
44.5.3 WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . 1893
44.5.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893

45 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894

45.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
45.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
45.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
45.3.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
45.3.2 IWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
45.3.3 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
45.3.4 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
45.3.5 Low-power freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
45.3.6 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
45.3.7 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
45.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
45.4.1 IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
45.4.2 IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . 1899
45.4.3 IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1900
45.4.4 IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
45.4.5 IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . 1902
45.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903

46 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904

46.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904

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46.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905

46.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
46.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
46.3.2 RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
46.3.3 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
46.3.4 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910
46.3.5 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
46.3.6 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
46.3.7 Periodic auto-wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
46.3.8 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1912
46.3.9 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914
46.3.10 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915
46.3.11 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915
46.3.12 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1916
46.3.13 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1916
46.3.14 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918
46.3.15 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1919
46.3.16 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
46.3.17 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
46.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
46.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
46.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
46.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
46.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1924
46.6.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926
46.6.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . 1929
46.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1932
46.6.6 RTC wake-up timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . 1933
46.6.7 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1934
46.6.8 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 1935
46.6.9 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1936
46.6.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1936
46.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1937
46.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 1938
46.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 1939
46.6.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . 1940

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46.6.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1941

46.6.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . . . . . . . . . 1942
46.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1945
46.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 1946
46.6.19 RTC option register (RTC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1947
46.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . 1947
46.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948

47 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . 1950

47.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1950
47.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1950
47.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951
47.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951
47.4.1 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1952
47.4.2 I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953
47.4.3 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953
47.4.4 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953
47.4.5 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1954
47.4.6 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1959
47.4.7 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1960
47.4.8 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962
47.4.9 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1971
47.4.10 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 1982
47.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
47.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
47.4.13 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . 1989
47.4.14 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
47.4.15 Wake-up from Stop mode on address match . . . . . . . . . . . . . . . . . . 1996
47.4.16 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1997
47.4.17 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1999
47.4.18 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1999
47.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000
47.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
47.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2003
47.7.1 I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2003
47.7.2 I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2006

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47.7.3 I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . 2008

47.7.4 I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . 2008
47.7.5 I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
47.7.6 I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . 2010
47.7.7 I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . 2011
47.7.8 I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 2014
47.7.9 I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2015
47.7.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . 2015
47.7.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 2016
47.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2016

48 Universal synchronous/asynchronous receiver

transmitter (USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2018
48.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2018
48.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2019
48.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2020
48.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2020
48.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
48.5.1 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
48.5.2 USART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2022
48.5.3 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023
48.5.4 USART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2025
48.5.5 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2025
48.5.6 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2029
48.5.7 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2036
48.5.8 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 2037
48.5.9 USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2039
48.5.10 USART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . 2041
48.5.11 USART Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043
48.5.12 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2044
48.5.13 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 2045
48.5.14 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
48.5.15 USART single-wire Half-duplex communication . . . . . . . . . . . . . . . . 2051
48.5.16 USART receiver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2051
48.5.17 USART Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2052
48.5.18 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2056
48.5.19 Continuous communication using USART and DMA . . . . . . . . . . . . . 2059

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48.5.20 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . 2061
48.5.21 USART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2064
48.6 USART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2067
48.7 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2068
48.8 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2069
48.8.1 USART control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . 2069
48.8.2 USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . 2073
48.8.3 USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . 2076
48.8.4 USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . 2080
48.8.5 USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . 2085
48.8.6 USART guard time and prescaler register (USART_GTPR) . . . . . . . 2085
48.8.7 USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . 2086
48.8.8 USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . 2087
48.8.9 USART interrupt and status register (USART_ISR) . . . . . . . . . . . . . 2088
48.8.10 USART interrupt and status register [alternate] (USART_ISR) . . . . . 2094
48.8.11 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . 2099
48.8.12 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . 2101
48.8.13 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . 2101
48.8.14 USART prescaler register (USART_PRESC) . . . . . . . . . . . . . . . . . . 2102
48.8.15 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2103

49 Low-power universal asynchronous receiver

transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2105
49.1 LPUART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2105
49.2 LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2106
49.3 LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107
49.4 LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2108
49.4.1 LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2108
49.4.2 LPUART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2109
49.4.3 LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2109
49.4.4 LPUART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2110
49.4.5 LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2111
49.4.6 LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2114
49.4.7 LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2118
49.4.8 Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . 2119
49.4.9 LPUART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . 2120

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49.4.10 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2122

49.4.11 LPUART single-wire Half-duplex communication . . . . . . . . . . . . . . . 2123
49.4.12 Continuous communication using DMA and LPUART . . . . . . . . . . . . 2123
49.4.13 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . 2126
49.4.14 LPUART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 2128
49.5 LPUART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2131
49.6 LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2132
49.7 LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2133
49.7.1 LPUART control register 1 (LPUART_CR1) . . . . . . . . . . . . . . . . . . . 2133
49.7.2 LPUART control register 1 [alternate] (LPUART_CR1) . . . . . . . . . . . 2136
49.7.3 LPUART control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . 2139
49.7.4 LPUART control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . 2141
49.7.5 LPUART baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . 2144
49.7.6 LPUART request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . 2145
49.7.7 LPUART interrupt and status register (LPUART_ISR) . . . . . . . . . . . 2145
49.7.8 LPUART interrupt and status register [alternate] (LPUART_ISR) . . . 2150
49.7.9 LPUART interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . 2153
49.7.10 LPUART receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . 2154
49.7.11 LPUART transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . 2154
49.7.12 LPUART prescaler register (LPUART_PRESC) . . . . . . . . . . . . . . . . 2155
49.7.13 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2156

50 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2158

50.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2158
50.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2158
50.3 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159
50.4 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159
50.4.1 SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159
50.4.2 SPI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2161
50.4.3 SPI communication general aspects . . . . . . . . . . . . . . . . . . . . . . . . . 2161
50.4.4 Communications between one master and one slave . . . . . . . . . . . . 2161
50.4.5 Standard multislave communication . . . . . . . . . . . . . . . . . . . . . . . . . 2164
50.4.6 Multimaster communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167
50.4.7 Slave select (SS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 2167
50.4.8 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2171
50.4.9 Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2173

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50.4.10 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2174

50.4.11 SPI data transmission and reception procedures . . . . . . . . . . . . . . . 2174
50.4.12 Procedure for disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2179
50.4.13 Data packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2180
50.4.14 Communication using DMA (direct memory addressing) . . . . . . . . . . 2181
50.5 SPI specific modes and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183
50.5.1 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183
50.5.2 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183
50.5.3 CRC computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2187
50.6 Low-power mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2188
50.7 SPI wakeup and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2191
50.8 I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2192
50.9 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2193
50.9.1 I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2193
50.9.2 Pin sharing with SPI function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2193
50.9.3 Bitfields usable in I2S/PCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194
50.9.4 Slave and master modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2195
50.9.5 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2195
50.9.6 Additional Serial Interface Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . 2201
50.9.7 Startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2203
50.9.8 Stop sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2205
50.9.9 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2205
50.9.10 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2208
50.9.11 FIFOs status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2209
50.9.12 Handling of underrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2209
50.9.13 Handling of overrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2210
50.9.14 Frame error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2211
50.9.15 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2212
50.9.16 Programing examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2214
50.10 I2S wakeup and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2216
50.11 SPI/I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2217
50.11.1 SPI/I2S control register 1 (SPI_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 2217
50.11.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2219
50.11.3 SPI configuration register 1 (SPI_CFG1) . . . . . . . . . . . . . . . . . . . . . . 2219
50.11.4 SPI configuration register 2 (SPI_CFG2) . . . . . . . . . . . . . . . . . . . . . . 2222
50.11.5 SPI/I2S interrupt enable register (SPI_IER) . . . . . . . . . . . . . . . . . . . 2224

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50.11.6 SPI/I2S status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225

50.11.7 SPI/I2S interrupt/status flags clear register (SPI_IFCR) . . . . . . . . . . 2228
50.11.8 SPI/I2S transmit data register (SPI_TXDR) . . . . . . . . . . . . . . . . . . . . 2229
50.11.9 SPI/I2S receive data register (SPI_RXDR) . . . . . . . . . . . . . . . . . . . . 2229
50.11.10 SPI polynomial register (SPI_CRCPOLY) . . . . . . . . . . . . . . . . . . . . . 2230
50.11.11 SPI transmitter CRC register (SPI_TXCRC) . . . . . . . . . . . . . . . . . . . 2230
50.11.12 SPI receiver CRC register (SPI_RXCRC) . . . . . . . . . . . . . . . . . . . . . 2231
50.11.13 SPI underrun data register (SPI_UDRDR) . . . . . . . . . . . . . . . . . . . . 2232
50.11.14 SPI/I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . 2232
50.12 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235

51 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2237

51.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2237
51.2 SAI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2237
51.3 SAI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
51.4 SAI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
51.4.1 SAI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
51.4.2 SAI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240
51.4.3 Main SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240
51.4.4 SAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2241
51.4.5 Audio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2242
51.4.6 Frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2243
51.4.7 Slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2246
51.4.8 SAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2248
51.4.9 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2250
51.4.10 PDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2252
51.4.11 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2260
51.4.12 SPDIF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2262
51.4.13 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2265
51.4.14 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2269
51.4.15 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2272
51.4.16 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2272
51.5 SAI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2273
51.6 SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2274
51.6.1 SAI global configuration register (SAI_GCR) . . . . . . . . . . . . . . . . . . . 2274
51.6.2 SAI configuration register 1 (SAI_ACR1) . . . . . . . . . . . . . . . . . . . . . . 2275

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51.6.3 SAI configuration register 1 (SAI_BCR1) . . . . . . . . . . . . . . . . . . . . . . 2277

51.6.4 SAI configuration register 2 (SAI_ACR2) . . . . . . . . . . . . . . . . . . . . . . 2280
51.6.5 SAI configuration register 2 (SAI_BCR2) . . . . . . . . . . . . . . . . . . . . . . 2282
51.6.6 SAI frame configuration register (SAI_AFRCR) . . . . . . . . . . . . . . . . . 2284
51.6.7 SAI frame configuration register (SAI_BFRCR) . . . . . . . . . . . . . . . . . 2286
51.6.8 SAI slot register (SAI_ASLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2287
51.6.9 SAI slot register (SAI_BSLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288
51.6.10 SAI interrupt mask register (SAI_AIM) . . . . . . . . . . . . . . . . . . . . . . . . 2289
51.6.11 SAI interrupt mask register (SAI_BIM) . . . . . . . . . . . . . . . . . . . . . . . . 2291
51.6.12 SAI status register (SAI_ASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2292
51.6.13 SAI status register (SAI_BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2294
51.6.14 SAI clear flag register (SAI_ACLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 2296
51.6.15 SAI clear flag register (SAI_BCLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 2297
51.6.16 SAI data register (SAI_ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2298
51.6.17 SAI data register (SAI_BDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299
51.6.18 SAI PDM control register (SAI_PDMCR) . . . . . . . . . . . . . . . . . . . . . . 2299
51.6.19 SAI PDM delay register (SAI_PDMDLY) . . . . . . . . . . . . . . . . . . . . . . 2301
51.6.20 SAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2303

52 SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 2305

52.1 SPDIFRX interface introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305
52.2 SPDIFRX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305
52.3 SPDIFRX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305
52.3.1 SPDIFRX pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2306
52.3.2 S/PDIF protocol (IEC-60958) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2307
52.3.3 SPDIFRX decoder (SPDIFRX_DC) . . . . . . . . . . . . . . . . . . . . . . . . . . 2309
52.3.4 SPDIFRX tolerance to clock deviation . . . . . . . . . . . . . . . . . . . . . . . . 2313
52.3.5 SPDIFRX synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313
52.3.6 SPDIFRX handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2315
52.3.7 Data reception management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2317
52.3.8 Dedicated control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2319
52.3.9 Reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2320
52.3.10 Clocking strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2322
52.3.11 DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2322
52.3.12 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2323
52.3.13 Register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2324
52.4 Programming procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2325

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52.4.1 Initialization phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2325

52.4.2 Handling of interrupts coming from SPDIFRX . . . . . . . . . . . . . . . . . . 2326
52.4.3 Handling of interrupts coming from DMA . . . . . . . . . . . . . . . . . . . . . . 2326
52.5 SPDIFRX interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2327
52.5.1 SPDIFRX control register (SPDIFRX_CR) . . . . . . . . . . . . . . . . . . . . 2327
52.5.2 SPDIFRX interrupt mask register (SPDIFRX_IMR) . . . . . . . . . . . . . . 2329
52.5.3 SPDIFRX status register (SPDIFRX_SR) . . . . . . . . . . . . . . . . . . . . . 2330
52.5.4 SPDIFRX interrupt flag clear register (SPDIFRX_IFCR) . . . . . . . . . . 2332
52.5.5 SPDIFRX data input register (SPDIFRX_FMT0_DR) . . . . . . . . . . . . 2333
52.5.6 SPDIFRX data input register (SPDIFRX_FMT1_DR) . . . . . . . . . . . . 2333
52.5.7 SPDIFRX data input register (SPDIFRX_FMT2_DR) . . . . . . . . . . . . 2334
52.5.8 SPDIFRX channel status register (SPDIFRX_CSR) . . . . . . . . . . . . . 2335
52.5.9 SPDIFRX debug information register (SPDIFRX_DIR) . . . . . . . . . . . 2335
52.5.10 SPDIFRX interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2336

53 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . 2337

53.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2337
53.2 SWPMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2338
53.3 SWPMI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2339
53.3.1 SWPMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2339
53.3.2 SWPMI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2339
53.3.3 SWP initialization and activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2340
53.3.4 SWP bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2341
53.3.5 SWPMI_IO (internal transceiver) bypass . . . . . . . . . . . . . . . . . . . . . . 2342
53.3.6 SWPMI bit rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2342
53.3.7 SWPMI frame handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2343
53.3.8 Transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2343
53.3.9 Reception procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2348
53.3.10 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2352
53.3.11 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2354
53.4 SWPMI low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2354
53.5 SWPMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2355
53.6 SWPMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2356
53.6.1 SWPMI configuration/control register (SWPMI_CR) . . . . . . . . . . . . . 2356
53.6.2 SWPMI Bitrate register (SWPMI_BRR) . . . . . . . . . . . . . . . . . . . . . . . 2357
53.6.3 SWPMI Interrupt and Status register (SWPMI_ISR) . . . . . . . . . . . . . 2358

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53.6.4 SWPMI Interrupt Flag Clear register (SWPMI_ICR) . . . . . . . . . . . . . 2359

53.6.5 SWPMI Interrupt Enable register (SMPMI_IER) . . . . . . . . . . . . . . . . 2360
53.6.6 SWPMI Receive Frame Length register (SWPMI_RFL) . . . . . . . . . . 2362
53.6.7 SWPMI Transmit data register (SWPMI_TDR) . . . . . . . . . . . . . . . . . 2362
53.6.8 SWPMI Receive data register (SWPMI_RDR) . . . . . . . . . . . . . . . . . 2362
53.6.9 SWPMI Option register (SWPMI_OR) . . . . . . . . . . . . . . . . . . . . . . . . 2363
53.6.10 SWPMI register map and reset value table . . . . . . . . . . . . . . . . . . . . 2364

54 Management data input/output (MDIOS) . . . . . . . . . . . . . . . . . . . . . . 2365

54.1 MDIOS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365
54.2 MDIOS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365
54.3 MDIOS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
54.3.1 MDIOS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
54.3.2 MDIOS pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
54.3.3 MDIOS protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
54.3.4 MDIOS enabling and disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2367
54.3.5 MDIOS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2368
54.3.6 MDIOS APB frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2369
54.3.7 Write/read flags and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2369
54.3.8 MDIOS error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2370
54.3.9 MDIOS in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2371
54.3.10 MDIOS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2371
54.4 MDIOS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2371
54.4.1 MDIOS configuration register (MDIOS_CR) . . . . . . . . . . . . . . . . . . . 2371
54.4.2 MDIOS write flag register (MDIOS_WRFR) . . . . . . . . . . . . . . . . . . . . 2372
54.4.3 MDIOS clear write flag register (MDIOS_CWRFR) . . . . . . . . . . . . . . 2373
54.4.4 MDIOS read flag register (MDIOS_RDFR) . . . . . . . . . . . . . . . . . . . . 2373
54.4.5 MDIOS clear read flag register (MDIOS_CRDFR) . . . . . . . . . . . . . . 2374
54.4.6 MDIOS status register (MDIOS_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 2374
54.4.7 MDIOS clear flag register (MDIOS_CLRFR) . . . . . . . . . . . . . . . . . . . 2375
54.4.8 MDIOS input data register x (MDIOS_DINRx) . . . . . . . . . . . . . . . . . . 2375
54.4.9 MDIOS output data register x (MDIOS_DOUTRx) . . . . . . . . . . . . . . 2376
54.4.10 MDIOS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2376

55 Secure digital input/output MultiMediaCard interface (SDMMC) . . 2378

55.1 SDMMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2378
55.2 SDMMC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2378

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55.3 SDMMC bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2379

55.4 SDMMC operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2381
55.5 SDMMC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2382
55.5.1 SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2382
55.5.2 SDMMC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2382
55.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2383
55.5.4 SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2385
55.5.5 SDMMC AHB slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2407
55.5.6 SDMMC AHB master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2407
55.5.7 MDMA request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2409
55.5.8 AHB and SDMMC_CK clock relation . . . . . . . . . . . . . . . . . . . . . . . . . 2410
55.6 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2411
55.6.1 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2411
55.6.2 CMD12 send timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2419
55.6.3 Sleep (CMD5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2422
55.6.4 Interrupt mode (Wait-IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2423
55.6.5 Boot operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2424
55.6.6 Response R1b handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2427
55.6.7 Reset and card cycle power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2428
55.7 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2429
55.8 Ultra-high-speed phase I (UHS-I) voltage switch . . . . . . . . . . . . . . . . . 2430
55.9 SDMMC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2433
55.10 SDMMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2435
55.10.1 SDMMC power control register (SDMMC_POWER) . . . . . . . . . . . . . 2435
55.10.2 SDMMC clock control register (SDMMC_CLKCR) . . . . . . . . . . . . . . 2436
55.10.3 SDMMC argument register (SDMMC_ARGR) . . . . . . . . . . . . . . . . . . 2438
55.10.4 SDMMC command register (SDMMC_CMDR) . . . . . . . . . . . . . . . . . 2438
55.10.5 SDMMC command response register (SDMMC_RESPCMDR) . . . . 2440
55.10.6 SDMMC response x register (SDMMC_RESPxR) . . . . . . . . . . . . . . 2441
55.10.7 SDMMC data timer register (SDMMC_DTIMER) . . . . . . . . . . . . . . . 2441
55.10.8 SDMMC data length register (SDMMC_DLENR) . . . . . . . . . . . . . . . 2442
55.10.9 SDMMC data control register (SDMMC_DCTRL) . . . . . . . . . . . . . . . 2443
55.10.10 SDMMC data counter register (SDMMC_DCNTR) . . . . . . . . . . . . . . 2444
55.10.11 SDMMC status register (SDMMC_STAR) . . . . . . . . . . . . . . . . . . . . . 2445
55.10.12 SDMMC interrupt clear register (SDMMC_ICR) . . . . . . . . . . . . . . . . 2448
55.10.13 SDMMC mask register (SDMMC_MASKR) . . . . . . . . . . . . . . . . . . . . 2450

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55.10.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . 2453

55.10.15 SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . . . . . . . . . . . 2453
55.10.16 SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . . . . . . . 2454
55.10.17 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . . . 2455
55.10.18 SDMMC IDMA buffer 0 base address register
(SDMMC_IDMABASE0R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2455
55.10.19 SDMMC IDMA buffer 1 base address register
(SDMMC_IDMABASE1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2456
55.10.20 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2456

56 Controller area network with flexible data rate (FDCAN) . . . . . . . . 2459

56.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2459
56.2 FDCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2462
56.3 FDCAN implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2462
56.4 FDCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2463
56.4.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2464
56.4.2 Message RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2473
56.4.3 FIFO acknowledge handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2484
56.4.4 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2485
56.4.5 Clock calibration on CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2486
56.4.6 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2490
56.4.7 TTCAN operations (FDCAN1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 2491
56.4.8 TTCAN configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2492
56.4.9 Message scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2494
56.4.10 TTCAN gap control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2501
56.4.11 Stop watch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2502
56.4.12 Local time, cycle time, global time,
and external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 2502
56.4.13 TTCAN error level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2505
56.4.14 TTCAN message handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2506
56.4.15 TTCAN interrupt and error handling . . . . . . . . . . . . . . . . . . . . . . . . . 2509
56.4.16 Level 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510
56.4.17 Synchronization to external time schedule . . . . . . . . . . . . . . . . . . . . 2512
56.4.18 FDCAN Rx buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . 2513
56.4.19 FDCAN Tx buffer element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2515
56.4.20 FDCAN Tx event FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2517
56.4.21 FDCAN standard message ID filter element . . . . . . . . . . . . . . . . . . . 2518
56.4.22 FDCAN extended message ID filter element . . . . . . . . . . . . . . . . . . . 2520

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56.4.23 FDCAN trigger memory element . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2521

56.5 FDCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2523
56.5.1 FDCAN core release register (FDCAN_CREL) . . . . . . . . . . . . . . . . . 2523
56.5.2 FDCAN Endian register (FDCAN_ENDN) . . . . . . . . . . . . . . . . . . . . . 2523
56.5.3 FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . 2524
56.5.4 FDCAN test register (FDCAN_TEST) . . . . . . . . . . . . . . . . . . . . . . . . 2525
56.5.5 FDCAN RAM watchdog register (FDCAN_RWD) . . . . . . . . . . . . . . . 2525
56.5.6 FDCAN CC control register (FDCAN_CCCR) . . . . . . . . . . . . . . . . . . 2526
56.5.7 FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . 2528
56.5.8 FDCAN timestamp counter configuration register (FDCAN_TSCC) . 2529
56.5.9 FDCAN timestamp counter value register (FDCAN_TSCV) . . . . . . . 2530
56.5.10 FDCAN timeout counter configuration register (FDCAN_TOCC) . . . 2530
56.5.11 FDCAN timeout counter value register (FDCAN_TOCV) . . . . . . . . . 2531
56.5.12 FDCAN error counter register (FDCAN_ECR) . . . . . . . . . . . . . . . . . 2532
56.5.13 FDCAN protocol status register (FDCAN_PSR) . . . . . . . . . . . . . . . . 2532
56.5.14 FDCAN transmitter delay compensation register (FDCAN_TDCR) . . 2534
56.5.15 FDCAN interrupt register (FDCAN_IR) . . . . . . . . . . . . . . . . . . . . . . . 2535
56.5.16 FDCAN interrupt enable register (FDCAN_IE) . . . . . . . . . . . . . . . . . 2538
56.5.17 FDCAN interrupt line select register (FDCAN_ILS) . . . . . . . . . . . . . . 2540
56.5.18 FDCAN interrupt line enable register (FDCAN_ILE) . . . . . . . . . . . . . 2541
56.5.19 FDCAN global filter configuration register (FDCAN_GFC) . . . . . . . . 2542
56.5.20 FDCAN standard ID filter configuration register (FDCAN_SIDFC) . . 2543
56.5.21 FDCAN extended ID filter configuration register (FDCAN_XIDFC) . . 2543
56.5.22 FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . . . . . 2544
56.5.23 FDCAN high priority message status register (FDCAN_HPMS) . . . . 2545
56.5.24 FDCAN new data 1 register (FDCAN_NDAT1) . . . . . . . . . . . . . . . . . 2545
56.5.25 FDCAN new data 2 register (FDCAN_NDAT2) . . . . . . . . . . . . . . . . . 2546
56.5.26 FDCAN Rx FIFO 0 configuration register (FDCAN_RXF0C) . . . . . . . 2546
56.5.27 FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . . . . . . . . . 2547
56.5.28 FDCAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . . . 2548
56.5.29 FDCAN Rx buffer configuration register (FDCAN_RXBC) . . . . . . . . . 2548
56.5.30 FDCAN Rx FIFO 1 configuration register (FDCAN_RXF1C) . . . . . . . 2549
56.5.31 FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . . . . . . . . . 2550
56.5.32 FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . . . 2551
56.5.33 FDCAN Rx buffer element size configuration register
(FDCAN_RXESC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2551
56.5.34 FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . . . . . . 2552

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56.5.35 FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . . . . . 2553

56.5.36 FDCAN Tx buffer element size configuration register
(FDCAN_TXESC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2554
56.5.37 FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . . 2554
56.5.38 FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . . . . . . 2555
56.5.39 FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . 2556
56.5.40 FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) 2556
56.5.41 FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . 2557
56.5.42 FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2557
56.5.43 FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2558
56.5.44 FDCAN Tx event FIFO configuration register (FDCAN_TXEFC) . . . 2558
56.5.45 FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . . . . . . 2559
56.5.46 FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . . 2560
56.5.47 FDCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2560
56.6 TTCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2564
56.6.1 FDCAN TT trigger memory configuration register (FDCAN_TTTMC) 2564
56.6.2 FDCAN TT reference message configuration register
(FDCAN_TTRMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2564
56.6.3 FDCAN TT operation configuration register (FDCAN_TTOCF) . . . . . 2565
56.6.4 FDCAN TT matrix limits register (FDCAN_TTMLM) . . . . . . . . . . . . . 2567
56.6.5 FDCAN TUR configuration register (FDCAN_TURCF) . . . . . . . . . . . 2568
56.6.6 FDCAN TT operation control register (FDCAN_TTOCN) . . . . . . . . . 2569
56.6.7 FDCAN TT global time preset register (FDCAN_TTGTP) . . . . . . . . . 2571
56.6.8 FDCAN TT time mark register (FDCAN_TTTMK) . . . . . . . . . . . . . . . 2571
56.6.9 FDCAN TT interrupt register (FDCAN_TTIR) . . . . . . . . . . . . . . . . . . 2572
56.6.10 FDCAN TT interrupt enable register (FDCAN_TTIE) . . . . . . . . . . . . . 2574
56.6.11 FDCAN TT interrupt line select register (FDCAN_TTILS) . . . . . . . . . 2576
56.6.12 FDCAN TT operation status register (FDCAN_TTOST) . . . . . . . . . . 2577
56.6.13 FDCAN TUR numerator actual register (FDCAN_TURNA) . . . . . . . . 2579
56.6.14 FDCAN TT local and global time register (FDCAN_TTLGT) . . . . . . . 2580
56.6.15 FDCAN TT cycle time and count register (FDCAN_TTCTC) . . . . . . . 2580
56.6.16 FDCAN TT capture time register (FDCAN_TTCPT) . . . . . . . . . . . . . 2581
56.6.17 FDCAN TT cycle sync mark register (FDCAN_TTCSM) . . . . . . . . . . 2581
56.6.18 FDCAN TT trigger select register (FDCAN_TTTS) . . . . . . . . . . . . . . 2582
56.6.19 FDCAN TT register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2582
56.7 CCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2584

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56.7.1 Clock calibration unit core release register (FDCAN_CCU_CREL) . . 2584

56.7.2 Calibration configuration register (FDCAN_CCU_CCFG) . . . . . . . . . 2584
56.7.3 Calibration status register (FDCAN_CCU_CSTAT) . . . . . . . . . . . . . . 2586
56.7.4 Calibration watchdog register (FDCAN_CCU_CWD) . . . . . . . . . . . . 2586
56.7.5 Clock calibration unit interrupt register (FDCAN_CCU_IR) . . . . . . . . 2587
56.7.6 Clock calibration unit interrupt enable register (FDCAN_CCU_IE) . . 2588
56.7.7 CCU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2588

57 USB on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . . . . . . . . . . 2590

57.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2590
57.2 OTG_HS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2591
57.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2591
57.2.2 Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2592
57.2.3 Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2592
57.3 OTG_HS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2593
57.4 OTG_HS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2593
57.4.1 OTG_HS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2593
57.4.2 OTG_HS pin and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595
57.4.3 OTG_HS core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595
57.4.4 Embedded full-speed OTG PHY connected to OTG_HS . . . . . . . . . 2596
57.4.5 OTG detections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2596
57.4.6 High-speed OTG PHY connected to OTG_HS . . . . . . . . . . . . . . . . . 2596
57.5 OTG_HS dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2597
57.5.1 ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2597
57.5.2 HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2597
57.5.3 SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2598
57.6 OTG_HS as a USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2598
57.6.1 SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599
57.6.2 Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599
57.6.3 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2600
57.7 OTG_HS as a USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2602
57.7.1 SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2603
57.7.2 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2603
57.7.3 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2605
57.7.4 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2606
57.8 OTG_HS SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2607

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57.8.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2607

57.8.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2607
57.9 OTG_HS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2608
57.10 OTG_HS Dynamic update of the OTG_HFIR register . . . . . . . . . . . . . 2609
57.11 OTG_HS data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2609
57.11.1 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2610
57.11.2 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2611
57.11.3 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2612
57.12 OTG_HS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2614
57.13 OTG_HS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . 2616
57.13.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2616
57.14 OTG_HS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2621
57.14.1 OTG control and status register (OTG_GOTGCTL) . . . . . . . . . . . . . 2621
57.14.2 OTG interrupt register (OTG_GOTGINT) . . . . . . . . . . . . . . . . . . . . . 2624
57.14.3 OTG AHB configuration register (OTG_GAHBCFG) . . . . . . . . . . . . . 2626
57.14.4 OTG USB configuration register (OTG_GUSBCFG) . . . . . . . . . . . . . 2627
57.14.5 OTG reset register (OTG_GRSTCTL) . . . . . . . . . . . . . . . . . . . . . . . . 2630
57.14.6 OTG core interrupt register (OTG_GINTSTS) . . . . . . . . . . . . . . . . . . 2633
57.14.7 OTG interrupt mask register (OTG_GINTMSK) . . . . . . . . . . . . . . . . . 2637
57.14.8 OTG receive status debug read register (OTG_GRXSTSR) . . . . . . . 2641
57.14.9 OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . . 2642
57.14.10 OTG status read and pop registers (OTG_GRXSTSP) . . . . . . . . . . . 2643
57.14.11 OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . 2644
57.14.12 OTG receive FIFO size register (OTG_GRXFSIZ) . . . . . . . . . . . . . . 2645
57.14.13 OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2645
57.14.14 OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2646
57.14.15 OTG general core configuration register (OTG_GCCFG) . . . . . . . . . 2647
57.14.16 OTG core ID register (OTG_CID) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2649
57.14.17 OTG core LPM configuration register (OTG_GLPMCFG) . . . . . . . . . 2649
57.14.18 OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2653
57.14.19 OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2653
57.14.20 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2654
57.14.21 OTG host configuration register (OTG_HCFG) . . . . . . . . . . . . . . . . . 2654

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57.14.22 OTG host frame interval register (OTG_HFIR) . . . . . . . . . . . . . . . . . 2655

57.14.23 OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2656
57.14.24 OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2657
57.14.25 OTG host all channels interrupt register (OTG_HAINT) . . . . . . . . . . 2658
57.14.26 OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2658
57.14.27 OTG host frame list base address register
(OTG_HFLBADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2659
57.14.28 OTG host port control and status register (OTG_HPRT) . . . . . . . . . . 2659
57.14.29 OTG host channel x characteristics register (OTG_HCCHARx) . . . . 2662
57.14.30 OTG host channel x split control register (OTG_HCSPLTx) . . . . . . . 2663
57.14.31 OTG host channel x interrupt register (OTG_HCINTx) . . . . . . . . . . . 2664
57.14.32 OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . 2665
57.14.33 OTG host channel x transfer size register (OTG_HCTSIZx) . . . . . . . 2667
57.14.34 OTG host channel x transfer size register (OTG_HCTSIZSGx) . . . . 2668
57.14.35 OTG host channel x DMA address register in buffer DMA [alternate]
(OTG_HCDMAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2670
57.14.36 OTG host channel x DMA address register in scatter/gather DMA
[alternate] (OTG_HCDMASGx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2670
57.14.37 OTG host channel-n DMA address buffer register
(OTG_HCDMABx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2671
57.14.38 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2672
57.14.39 OTG device configuration register (OTG_DCFG) . . . . . . . . . . . . . . . 2672
57.14.40 OTG device control register (OTG_DCTL) . . . . . . . . . . . . . . . . . . . . 2674
57.14.41 OTG device status register (OTG_DSTS) . . . . . . . . . . . . . . . . . . . . . 2676
57.14.42 OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2677
57.14.43 OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2678
57.14.44 OTG device all endpoints interrupt register (OTG_DAINT) . . . . . . . . 2679
57.14.45 OTG all endpoints interrupt mask register
(OTG_DAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2680
57.14.46 OTG device VBUS discharge time register
(OTG_DVBUSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2681
57.14.47 OTG device VBUS pulsing time register
(OTG_DVBUSPULSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2681
57.14.48 OTG device threshold control register (OTG_DTHRCTL) . . . . . . . . . 2682
57.14.49 OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2683

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57.14.50 OTG device each endpoint interrupt register (OTG_DEACHINT) . . . 2683

57.14.51 OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2684
57.14.52 OTG device each IN endpoint-1 interrupt mask register
(OTG_HS_DIEPEACHMSK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2684
57.14.53 OTG device each OUT endpoint-1 interrupt mask register
(OTG_HS_DOEPEACHMSK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2685
57.14.54 OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . . 2687
57.14.55 OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . . 2689
57.14.56 OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2691
57.14.57 OTG device IN endpoint x DMA address register
(OTG_DIEPDMAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2691
57.14.58 OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2692
57.14.59 OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . 2692
57.14.60 OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2693
57.14.61 OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . 2695
57.14.62 OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2697
57.14.63 OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2698
57.14.64 OTG device OUT endpoint x control register
(OTG_DOEPCTLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2698
57.14.65 OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2701
57.14.66 OTG power and clock gating control register (OTG_PCGCCTL) . . . 2702
57.14.67 OTG_HS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2703
57.15 OTG_HS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2715
57.15.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2715
57.15.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2716
57.15.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2717
57.15.4 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2717
57.15.5 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2718
57.15.6 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2750
57.15.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2770
57.15.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2772

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58 Ethernet (ETH): media access control

(MAC) with DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2778
58.1 Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2778
58.2 Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2778
58.2.1 Standard compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2778
58.2.2 MAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2778
58.2.3 Transaction layer (MTL) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2780
58.2.4 DMA block features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2781
58.2.5 Bus interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2781
58.3 Ethernet pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2782
58.4 Ethernet architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2783
58.4.1 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2784
58.4.2 MTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2793
58.4.3 MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2793
58.5 )Ethernet functional description: MAC . . . . . . . . . . . . . . . . . . . . . . . . . 2798
58.5.1 Double VLAN processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2798
58.5.2 Source address and VLAN insertion, replacement, or deletion . . . . . 2799
58.5.3 Packet filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2801
58.5.4 IEEE 1588 timestamp support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2807
58.5.5 Checksum offload engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2832
58.5.6 TCP segmentation offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2838
58.5.7 IPv4 ARP offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2844
58.5.8 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2845
58.5.9 Flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2846
58.5.10 MAC management counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2849
58.5.11 Interrupts generated by the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2851
58.5.12 MAC and MMC register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 2851
58.6 Ethernet functional description: PHY interfaces . . . . . . . . . . . . . . . . . . 2852
58.6.1 Station management agent (SMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 2852
58.6.2 Media independent interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2859
58.6.3 Reduced media independent interface (RMII) . . . . . . . . . . . . . . . . . . 2860
58.7 Ethernet low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2864
58.7.1 Low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2864
58.7.2 Energy Efficient Ethernet (EEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2870
58.8 Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2875
58.8.1 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2875

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58.8.2 MTL interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2876

58.8.3 MAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2877
58.9 Ethernet programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2878
58.9.1 DMA initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2878
58.9.2 MTL initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2879
58.9.3 MAC initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2879
58.9.4 Performing normal receive and transmit operation . . . . . . . . . . . . . . 2880
58.9.5 Stopping and starting transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 2881
58.9.6 Programming guidelines for switching to new descriptor list
in RxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2881
58.9.7 Programming guidelines for switching the AHB clock frequency . . . . 2881
58.9.8 Programming guidelines for MII link state transitions . . . . . . . . . . . . 2882
58.9.9 Programming guidelines for IEEE 1588 timestamping . . . . . . . . . . . 2883
58.9.10 Programming guidelines for PTP offload feature . . . . . . . . . . . . . . . . 2884
58.9.11 Programming guidelines for Energy Efficient Ethernet (EEE) . . . . . . 2888
58.9.12 Programming guidelines for flexible pulse-per-second (PPS) output 2890
58.9.13 Programming guidelines for TSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2892
58.9.14 Programming guidelines to perform VLAN filtering on the receive . . 2893
58.10 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2893
58.10.1 Descriptor overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2893
58.10.2 Descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2894
58.10.3 Transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2896
58.10.4 Receive descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2909
58.11 Ethernet registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2921
58.11.1 Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2921
58.11.2 Ethernet DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2921
58.11.3 Ethernet MTL registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2947
58.11.4 Ethernet MAC and MMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2959

59 HDMI-CEC controller (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3056

59.1 HDMI-CEC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3056
59.2 HDMI-CEC controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . 3056
59.3 HDMI-CEC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3057
59.3.1 HDMI-CEC pin and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . 3057
59.3.2 HDMI-CEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3058
59.3.3 Message description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3058
59.3.4 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3059

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59.4 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3059

59.4.1 SFT option bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3061
59.5 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3061
59.5.1 Bit error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3061
59.5.2 Message error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3062
59.5.3 Bit rising error (BRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3062
59.5.4 Short bit period error (SBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3062
59.5.5 Long bit period error (LBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3062
59.5.6 Transmission error detection (TXERR) . . . . . . . . . . . . . . . . . . . . . . . 3064
59.6 HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3065
59.7 HDMI-CEC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3066
59.7.1 CEC control register (CEC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3066
59.7.2 CEC configuration register (CEC_CFGR) . . . . . . . . . . . . . . . . . . . . . 3067
59.7.3 CEC Tx data register (CEC_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3069
59.7.4 CEC Rx data register (CEC_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . 3069
59.7.5 CEC interrupt and status register (CEC_ISR) . . . . . . . . . . . . . . . . . . 3069
59.7.6 CEC interrupt enable register (CEC_IER) . . . . . . . . . . . . . . . . . . . . . 3071
59.7.7 HDMI-CEC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3073

60 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3074

60.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3074
60.2 Debug infrastructure features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3075
60.3 Debug infrastructure functional description . . . . . . . . . . . . . . . . . . . . . 3075
60.3.1 Debug infrastructure block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3075
60.3.2 Debug infrastructure pins and internal signals . . . . . . . . . . . . . . . . . . 3076
60.3.3 Debug infrastructure powering, clocking and reset . . . . . . . . . . . . . . 3077
60.4 Debug access port functional description . . . . . . . . . . . . . . . . . . . . . . . 3079
60.4.1 Serial-wire and JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . 3079
60.4.2 Access ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3093
60.5 Trace and debug subsystem functional description . . . . . . . . . . . . . . . 3099
60.5.1 System ROM tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3099
60.5.2 Global timestamp generator (TSG) . . . . . . . . . . . . . . . . . . . . . . . . . . 3108
60.5.3 Cross trigger interfaces (CTI) and matrix (CTM) . . . . . . . . . . . . . . . . 3115
60.5.4 Trace funnel (CSTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3135
60.5.5 Embedded trace FIFO (ETF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3145
60.5.6 Trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167

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60.5.7 Serial wire output (SWO) and SWO trace funnel (SWTF) . . . . . . . . . 3185
60.5.8 Microcontroller debug unit (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . 3208
60.6 Cortex-M7 debug functional description . . . . . . . . . . . . . . . . . . . . . . . . 3214
60.6.1 Cortex-M7 ROM tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3215
60.6.2 Cortex-M7 data watchpoint and trace unit (DWT) . . . . . . . . . . . . . . . 3227
60.6.3 Cortex-M7 instrumentation trace macrocell (ITM) . . . . . . . . . . . . . . . 3240
60.6.4 Cortex-M7 breakpoint unit (FPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3249
60.6.5 Cortex-M7 embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . 3257
60.6.6 Cortex-M7 cross trigger interface (CTI) . . . . . . . . . . . . . . . . . . . . . . . 3289
60.7 References for debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . 3289

61 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3290

61.1 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3290
61.2 Flash size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3292
61.3 Package data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3292

62 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3293

63 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3294

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List of tables

Table 1. Peripherals versus products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 2. Availability of security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 3. Bus-master-to-bus-slave interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 4. ASIB configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 5. AMIB configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 6. AXI interconnect register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 7. Memory map and default device memory area attributes. . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 8. Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 9. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 10. RAMECC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 11. ECC controller mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 12. RAMECC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 13. FLASH internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 14. Flash memory organization on STM32H750xB devices . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 15. Flash memory organization on STM32H742xI/743xI/753xI devices. . . . . . . . . . . . . . . . . 153
Table 16. Flash memory organization on STM32H742xG/743xG devices . . . . . . . . . . . . . . . . . . . . 154
Table 17. FLASH recommended number of wait states and programming delay . . . . . . . . . . . . . . 160
Table 18. FLASH parallelism parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 19. FLASH AXI interface memory map vs swapping option . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 20. Flash register map vs swapping option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 21. Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 22. Flash interface register protection summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 23. RDP value vs readout protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 24. Protection vs RDP Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 25. RDP transition and its effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 26. Effect of low-power modes on the embedded flash memory . . . . . . . . . . . . . . . . . . . . . . 191
Table 27. Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 28. Register map and reset value table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 29. List of preferred terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 30. RSS API addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 31. Summary of flash protected areas access rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 32. PWR input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . . . . 256
Table 33. PWR internal input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 34. Supply configuration control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 35. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 36. PDDS_Dn low-power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 37. Low-power exit mode flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 38. CSleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 39. CStop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 40. DStop mode overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 41. DStop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Table 42. Stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 43. Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Table 44. DStandby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 45. Standby and Stop flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 46. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 47. Low-power modes monitoring pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 48. GPIO state according to CPU and domain state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

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Table 49. Power control register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Table 50. BDMA and DMAMUX2 initialization sequence (DMAMUX2_INIT) . . . . . . . . . . . . . . . . . . 320
Table 51. LPUART1 Initial programming (LPUART1_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Table 52. LPUART1 start programming (LPUART1_Start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Table 53. RCC input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . . . . 326
Table 54. RCC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table 55. Reset distribution summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table 56. Reset source identification (RCC_RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Table 57. Ratio between clock timer and pclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Table 58. STOPWUCK and STOPKERWUCK description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Table 59. HSIKERON and CSIKERON behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Table 60. Kernel clock distribution overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Table 61. System states overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Table 62. Peripheral clock enabling for D1 and D2 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Table 63. Peripheral clock enabling for D3 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Table 64. Interrupt sources and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Table 65. RCC_RSR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Table 66. RCC_AHB3ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Table 67. RCC_AHB1ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Table 68. RCC_AHB2ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Table 69. RCC_AHB4ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Table 70. RCC_APB3ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Table 71. RCC_APB1ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Table 72. RCC_APB1ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Table 73. RCC_APB2ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Table 74. RCC_APB4ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Table 75. RCC_AHB3LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Table 76. RCC_AHB1LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Table 77. RCC_AHB2LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Table 78. RCC_AHB4LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Table 79. RCC_APB3LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Table 80. RCC_APB1LLPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Table 81. RCC_APB1HLPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Table 82. RCC_APB2LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Table 83. RCC_APB4LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
Table 84. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Table 85. CRS features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Table 86. CRS internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Table 87. Effect of low-power modes on CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Table 88. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Table 89. CRS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Table 90. HSEM internal input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Table 91. Authorized AHB bus master ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Table 92. HSEM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Table 93. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Table 94. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Table 95. SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Table 96. Peripherals interconnect matrix (D2 domain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Table 97. Peripherals interconnect matrix (D3 domain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
Table 98. Peripherals interconnect matrix details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Table 99. EXTI wakeup inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
Table 100. EXTI pending requests clear inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

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RM0433 List of tables

Table 101. MDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Table 102. DMAMUX1, DMA1 and DMA2 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
Table 103. DMAMUX2 and BDMA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Table 104. MDMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Table 105. MDMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Table 106. MDMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Table 107. DMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Table 108. Source and destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Table 109. Source and destination address registers in double-buffer mode (DBM = 1) . . . . . . . . . . 645
Table 110. Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . . . . . . . . . . . . . . . . 646
Table 111. Restriction on NDT versus PSIZE and MSIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Table 112. FIFO threshold configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Table 113. Possible DMA configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Table 114. DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Table 115. DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
Table 116. BDMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Table 117. BDMA internal input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Table 118. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 677
Table 119. BDMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Table 120. BDMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Table 121. DMAMUX1 and DMAMUX2 instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Table 122. DMAMUX1: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . 694
Table 123. DMAMUX1: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . 695
Table 124. DMAMUX1: assignment of trigger inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Table 125. DMAMUX1: assignment of synchronization inputs to resources . . . . . . . . . . . . . . . . . . . 696
Table 126. DMAMUX2: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . 697
Table 127. DMAMUX2: assignment of trigger inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Table 128. DMAMUX2: assignment of synchronization inputs to resources . . . . . . . . . . . . . . . . . . . 698
Table 129. DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
Table 130. DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Table 131. DMAMUX register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Table 132. DMA2D internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Table 133. Supported color mode in input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Table 134. Data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Table 135. Alpha mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Table 136. Supported CLUT color mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Table 137. CLUT data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Table 138. Supported color mode in output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Table 139. Data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Table 140. Standard data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Table 141. Output FIFO byte reordering steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Table 142. MCU order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Table 143. DMA2D interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Table 144. DMA2D register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
Table 145. NVIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Table 146. EXTI Event input configurations and register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
Table 147. Configurable Event input Asynchronous Edge detector reset . . . . . . . . . . . . . . . . . . . . . 762
Table 148. EXTI Event input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Table 149. Masking functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
Table 150. Asynchronous interrupt/event controller register map and reset values . . . . . . . . . . . . . . 787
Table 151. CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
Table 152. CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

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Table 153. FMC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800

Table 154. FMC bank mapping options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Table 155. NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Table 156. NOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Table 157. NAND memory mapping and timing registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Table 158. NAND bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Table 159. SDRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Table 160. SDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
Table 161. SDRAM address mapping with 8-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
Table 162. SDRAM address mapping with 16-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
Table 163. SDRAM address mapping with 32-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Table 164. Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
Table 165. Non-multiplexed I/O NOR flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
Table 166. 16-bit multiplexed I/O NOR flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Table 167. Non-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Table 168. 16-Bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Table 169. NOR flash/PSRAM: Example of supported memories
and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
Table 170. FMC_BCRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
Table 171. FMC_BTRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
Table 172. FMC_BCRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
Table 173. FMC_BTRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
Table 174. FMC_BWTRx bitfields (mode A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
Table 175. FMC_BCRx bitfields (mode 2/B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
Table 176. FMC_BTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
Table 177. FMC_BWTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
Table 178. FMC_BCRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Table 179. FMC_BTRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Table 180. FMC_BWTRx bitfields (mode C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Table 181. FMC_BCRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Table 182. FMC_BTRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Table 183. FMC_BWTRx bitfields (mode D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Table 184. FMC_BCRx bitfields (Muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
Table 185. FMC_BTRx bitfields (Muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
Table 186. FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . . 835
Table 187. FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . . 835
Table 188. FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . . 836
Table 189. FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . . 837
Table 190. Programmable NAND flash access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
Table 191. 8-bit NAND flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
Table 192. 16-bit NAND flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Table 193. Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Table 194. ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
Table 195. SDRAM signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
Table 196. FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
Table 197. QUADSPI internal signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Table 198. QUADSPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Table 199. QUADSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Table 200. QUADSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Table 201. DLYB internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
Table 202. Delay block control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
Table 203. DLYB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911

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Table 204. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

Table 205. ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
Table 206. ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
Table 207. ADC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
Table 208. Configuring the trigger polarity for regular external triggers . . . . . . . . . . . . . . . . . . . . . . . 938
Table 209. Configuring the trigger polarity for injected external triggers . . . . . . . . . . . . . . . . . . . . . . 938
Table 210. ADC1, ADC2 and ADC3 - External triggers for regular channels . . . . . . . . . . . . . . . . . . . 939
Table 211. ADC1, ADC2 and ADC3 - External triggers for injected channels . . . . . . . . . . . . . . . . . . 940
Table 212. TSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Table 213. Offset computation versus data resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Table 214. 16-bit data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Table 215. Numerical examples for 16-bit format (bold indicates saturation). . . . . . . . . . . . . . . . . . . 958
Table 216. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Table 217. Analog watchdog 1,2,3 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
Table 218. Oversampler operating modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
Table 219. ADC interrupts per each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Table 220. DELAY bits versus ADC resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Table 221. ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
Table 222. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
Table 223. ADC register map and reset values (master and slave ADC
common registers) offset =0x300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Table 224. DAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
Table 225. DAC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Table 226. DAC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Table 227. DAC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
Table 228. Sample and refresh timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
Table 229. Channel output modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
Table 230. Effect of low-power modes on DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Table 231. DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
Table 232. DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
Table 233. VREF buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Table 234. VREFBUF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Table 235. COMP input/output internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Table 236. COMP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Table 237. COMP1_OUT assignment to GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
Table 238. COMP2_OUT assignment to GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
Table 239. Comparator behavior in the low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
Table 240. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
Table 241. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
Table 242. COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
Table 243. Operational amplifier possible connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
Table 244. Operating modes and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
Table 245. Effect of low-power modes on the OPAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
Table 246. OPAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
Table 247. DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
Table 248. DFSDM external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Table 249. DFSDM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Table 250. DFSDM triggers connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Table 251. DFSDM break connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
Table 252. Filter maximum output resolution (peak data values from filter output)
for some FOSR values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138

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Table 253. Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . 1139
Table 254. DFSDM interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
Table 255. DFSDM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
Table 256. DCMI input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
Table 257. DCMI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
Table 258. Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . 1180
Table 259. Positioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . 1180
Table 260. Positioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . 1180
Table 261. Positioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . 1181
Table 262. Data storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . 1186
Table 263. Data storage in RGB progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
Table 264. Data storage in YCbCr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
Table 265. Data storage in YCbCr progressive video format - Y extraction mode . . . . . . . . . . . . . . 1188
Table 266. DCMI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
Table 267. DCMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
Table 268. LTDC external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Table 269. LTDC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
Table 270. Clock domain for each register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
Table 271. LTDC register access and update durations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
Table 272. Pixel data mapping versus color format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
Table 273. LTDC interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
Table 274. LTDC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228
Table 275. JPEG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
Table 276. JPEG codec interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236
Table 277. JPEG codec register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
Table 278. RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
Table 279. RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
Table 280. RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
Table 281. CRYP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
Table 282. Counter mode initialization vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
Table 283. GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
Table 284. GCM mode IV registers initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
Table 285. CCM mode IV registers initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
Table 286. DES/TDES data swapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
Table 287. AES data swapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
Table 288. Key endianness in CRYP_KxR/LR registers (AES 128/192/256-bit keys) . . . . . . . . . . . 1308
Table 289. Key endianness in CRYP_KxR/LR registers (DES K1 and TDES K1/2/3) . . . . . . . . . . . 1308
Table 290. Initialization vector endianness in CRYP_IVx(L/R)R registers (AES) . . . . . . . . . . . . . . . 1309
Table 291. Initialization vector endianness in CRYP_IVx(L/R)R registers (DES/TDES) . . . . . . . . . 1309
Table 292. Cryptographic processor configuration for
memory-to-peripheral DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309
Table 293. Cryptographic processor configuration for
peripheral-to-memory DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310
Table 294. CRYP interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
Table 295. Processing latency for ECB, CBC and CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313
Table 296. Processing time (in clock cycle) for GCM and CCM per 128-bit block . . . . . . . . . . . . . . 1313
Table 297. CRYP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327
Table 298. HASH internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332
Table 299. Hash processor outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1335
Table 300. HASH interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342
Table 301. Processing time (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342

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Table 302. HASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1350

Table 303. HRTIM Input/output summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
Table 304. Timer resolution and min. PWM frequency for fHRTIM = 400 MHz . . . . . . . . . . . . . . . . . 1358
Table 305. Period and Compare registers min and max values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
Table 306. Timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
Table 307. Events mapping across Timer A to E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
Table 308. Deadtime resolution and max absolute values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
Table 309. External events mapping and associated features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
Table 310. Output set/reset latency and jitter vs external event operating mode . . . . . . . . . . . . . . . 1382
Table 311. Filtering signals mapping per time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
Table 312. Windowing signals mapping per timer (EEFLTR[3:0] = 1111) . . . . . . . . . . . . . . . . . . . . 1387
Table 313. HRTIM preloadable control registers and associated update sources . . . . . . . . . . . . . . 1396
Table 314. Update enable inputs and sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
Table 315. Master timer update event propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
Table 316. TIMx update event propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
Table 317. Reset events able to generate an update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
Table 318. Update event propagation for a timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
Table 319. Output state programming, x= A..E, y = 1 or 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
Table 320. Timer output programming for burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
Table 321. Burst mode clock sources from general purpose timer. . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Table 322. Fault inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415
Table 323. Sampling rate and filter length vs FLTFxF[3:0] and clock setting . . . . . . . . . . . . . . . . . . 1416
Table 324. Effect of sync event vs timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421
Table 325. HRTIM interrupt summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427
Table 326. HRTIM DMA request summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1428
Table 327. RTIM global register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
Table 328. HRTIM Register map and reset values: Master timer. . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
Table 329. HRTIM Register map and reset values: TIMx (x= A..E) . . . . . . . . . . . . . . . . . . . . . . . . . 1520
Table 330. HRTIM Register map and reset values: Common functions. . . . . . . . . . . . . . . . . . . . . . 1524
Table 331. Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568
Table 332. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575
Table 333. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
Table 334. Output control bits for complementary OCx and OCxN channels with break feature . . . 1606
Table 335. TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626
Table 336. TIM8 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
Table 337. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664
Table 338. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682
Table 339. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693
Table 340. TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
Table 341. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
Table 342. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
Table 343. TIM12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
Table 344. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756
Table 345. TIM13/TIM14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
Table 346. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1803
Table 347. Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1813
Table 348. TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
Table 349. Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834
Table 350. TIM16/TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1845
Table 351. TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859

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List of tables RM0433

Table 352. STM32H742, STM32H743/753 and STM32H750 LPTIM features. . . . . . . . . . . . . . . . . 1861

Table 353. LPTIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
Table 354. LPTIM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
Table 355. LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
Table 356. LPTIM2 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
Table 357. LPTIM3 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
Table 358. LPTIM4 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
Table 359. LPTIM5 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1865
Table 360. LPTIM1 input 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1865
Table 361. LPTIM1 input 2 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1865
Table 362. LPTIM2 input 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1865
Table 363. LPTIM2 input 2 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
Table 364. LPTIM3 input 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
Table 365. Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867
Table 366. Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
Table 367. Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
Table 368. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1876
Table 369. LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887
Table 370. WWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
Table 371. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
Table 372. IWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
Table 373. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903
Table 374. RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
Table 375. RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
Table 376. RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1909
Table 377. RTC functions over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910
Table 378. Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
Table 379. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
Table 380. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948
Table 381. STM32H742, STM32H743/753 and STM32H750 I2C implementation . . . . . . . . . . . . . 1951
Table 382. I2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953
Table 383. I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953
Table 384. Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1955
Table 385. I2C-SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . 1957
Table 386. I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962
Table 387. I2C-SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1973
Table 388. Examples of timing settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
Table 389. Examples of timing settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
Table 390. Examples of timing settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
Table 391. SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1986
Table 392. SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
Table 393. Examples of TIMEOUTA settings (max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . 1989
Table 394. Examples of TIMEOUTB settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
Table 395. Examples of TIMEOUTA settings (max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
Table 396. Effect of low-power modes on the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000
Table 397. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
Table 398. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2016
Table 399. USART / LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2020
Table 400. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2035
Table 401. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 2038
Table 402. Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . 2039
Table 403. USART frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2044

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RM0433 List of tables

Table 404. Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2067

Table 405. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2068
Table 406. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2103
Table 407. USART / LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107
Table 408. Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . 2118
Table 409. Error calculation for programmed baud rates at fCK = 100 MHz . . . . . . . . . . . . . . . . . . 2119
Table 410. Tolerance of the LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2120
Table 412. Effect of low-power modes on the LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2131
Table 413. LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2132
Table 414. LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2156
Table 415. STM32H742xx, STM32H743/53xx and STM32H750xB SPI features . . . . . . . . . . . . . . 2159
Table 416. SPI wakeup and interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2191
Table 417. Bitfields usable in PCM/I2S mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194
Table 418. WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . . . . . . . . . . . . . . . 2202
Table 419. Serial data line swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2202
Table 420. CLKGEN programming examples for usual I2S frequencies . . . . . . . . . . . . . . . . . . . . . 2207
Table 421. I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2216
Table 422. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235
Table 423. STM32H743/753/745/755/747/757 SAI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
Table 424. SAI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240
Table 425. SAI input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240
Table 426. External synchronization selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2242
Table 427. Clock generator programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2250
Table 428. TDM settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2257
Table 429. TDM frame configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2259
Table 430. SOPD pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263
Table 431. Parity bit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263
Table 432. Audio sampling frequency versus symbol rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2264
Table 433. SAI interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2273
Table 434. SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2303
Table 435. SPDIFRX internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2306
Table 436. SPDIFRX pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2306
Table 437. Transition sequence for preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2312
Table 438. Minimum spdifrx_ker_ck frequency versus audio sampling rate . . . . . . . . . . . . . . . . . . 2322
Table 439. Bit field property versus SPDIFRX state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2324
Table 440. SPDIFRX interface register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2336
Table 441. SWPMI input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . 2339
Table 442. SWPMI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2340
Table 443. Effect of low-power modes on SWPMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2354
Table 444. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2355
Table 445. Buffer modes selection for transmission/reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2357
Table 446. SWPMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2364
Table 447. MDIOS input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . 2366
Table 448. MDIOS internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
Table 449. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2371
Table 450. MDIOS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2376
Table 451. SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2378
Table 452. SDMMC operation modes SD and SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2381
Table 453. SDMMC operation modes e•MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2381
Table 454. SDMMC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2382
Table 455. SDMMC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2383
Table 456. SDMMC Command and data phase selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2384

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Table 457. Command token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2390

Table 458. Short response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2391
Table 459. Short response without CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2391
Table 460. Long response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2391
Table 461. Specific Commands overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2392
Table 462. Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2393
Table 463. Command path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2393
Table 464. Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2401
Table 465. Data path status flags and clear bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2401
Table 466. Data path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403
Table 467. Data FIFO access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2404
Table 468. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2405
Table 469. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2406
Table 470. SDMMC connections to MDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2410
Table 471. AHB and SDMMC_CK clock frequency relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2410
Table 472. SDIO special operation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2411
Table 473. 4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . . . . . . . . . . . . . . . 2415
Table 474. CMD12 use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2419
Table 475. SDMMC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2433
Table 476. Response type and SDMMC_RESPxR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2441
Table 477. SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2456
Table 478. CAN subsystem I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2459
Table 479. CAN subsystem I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2460
Table 480. Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2462
Table 481. DLC coding in FDCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2467
Table 482. Example of filter configuration for Rx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2479
Table 483. Example of filter configuration for Debug messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 2480
Table 484. Possible configurations for frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2480
Table 485. Tx buffer/FIFO - queue element size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2481
Table 486. First byte of level 1 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2491
Table 487. First four bytes of level 2 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2492
Table 488. First four bytes of level 0 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2492
Table 489. TUR configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2493
Table 490. System matrix, Node A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2498
Table 491. Trigger list, Node A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2499
Table 492. Number of data bytes transmitted with a reference message. . . . . . . . . . . . . . . . . . . . . 2506
Table 493. Rx buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2513
Table 494. Rx buffer and FIFO element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2513
Table 495. Tx buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2515
Table 496. Tx buffer element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2515
Table 497. Tx Event FIFO element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2517
Table 498. Tx Event FIFO element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2517
Table 499. Standard message ID filter element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2518
Table 500. Standard message ID filter element field description . . . . . . . . . . . . . . . . . . . . . . . . . . . 2519
Table 501. Extended message ID filter element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2520
Table 502. Extended message ID filter element field description . . . . . . . . . . . . . . . . . . . . . . . . . . . 2520
Table 503. Trigger memory element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2521
Table 504. Trigger memory element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2521
Table 505. FDCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2560
Table 506. FDCAN TT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2582
Table 507. CCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2588
Table 508. OTG_HS speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2591

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Table 509. OTG_HS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2593

Table 510. OTG_FS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595
Table 511. OTG_HS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595
Table 512. OTG_HS input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595
Table 513. Compatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . 2608
Table 514. Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2616
Table 515. Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2617
Table 516. Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2619
Table 517. Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2621
Table 518. Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2621
Table 519. TRDT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2630
Table 520. Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2675
Table 521. OTG_HS register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2703
Table 522. Ethernet peripheral pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2782
Table 523. Ethernet internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2783
Table 524. Priority scheme for Tx DMA and Rx DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2792
Table 525. Double VLAN processing features in Tx path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2798
Table 526. Double VLAN processing in Rx path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2799
Table 527. VLAN insertion or replacement based on VLTI bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2800
Table 528. Destination address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2803
Table 529. Source address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2804
Table 530. VLAN match status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2805
Table 531. Ordinary clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2808
Table 532. End-to-end transparent clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . . 2809
Table 533. Peer-to-peer transparent clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . 2810
Table 534. Egress and ingress latency for PHY interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2813
Table 535. Minimum PTP clock frequency example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2814
Table 536. Message format defined in IEEE 1588-2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2815
Table 537. Message format defined in IEEE 1588-2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2815
Table 538. IPv6-UDP PTP packet fields required for control and status . . . . . . . . . . . . . . . . . . . . . 2816
Table 539. Ethernet PTP packet fields required for control and status . . . . . . . . . . . . . . . . . . . . . . 2817
Table 540. Timestamp Snapshot Dependency on ETH_MACTSCR bits . . . . . . . . . . . . . . . . . . . . . 2819
Table 541. PTP message generation criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2825
Table 542. Common PTP message header fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2827
Table 543. MAC Transmit PTP mode and one-step timestamping operation. . . . . . . . . . . . . . . . . . 2830
Table 544. Transmit checksum offload engine functions for different packet types . . . . . . . . . . . . . 2835
Table 545. Receive checksum offload engine functions for different packet types . . . . . . . . . . . . . 2837
Table 546. TSO: TCP and IP header fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2841
Table 547. Pause packet fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2846
Table 548. Tx MAC flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2847
Table 549. Rx MAC flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2847
Table 550. Size of the maximum receive packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2850
Table 551. MCD clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2853
Table 552. MDIO Clause 45 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2854
Table 553. MDIO Clause 22 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2855
Table 554. Remote wake-up packet filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2866
Table 555. Description of the remote wake-up filter fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2867
Table 556. Remote wake-up packet and PMT interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . 2868
Table 557. Transfer complete interrupt behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2876
Table 558. TDES0 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2896
Table 559. TDES1 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2897
Table 560. TDES2 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2897

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Table 561. TDES3 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2898

Table 562. TDES0 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2901
Table 563. TDES1 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2901
Table 564. TDES2 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2902
Table 565. TDES3 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2902
Table 566. TDES0 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2905
Table 567. TDES1 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2906
Table 568. TDES2 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2906
Table 569. TDES3 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2906
Table 570. RDES0 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2910
Table 571. RDES1 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2910
Table 572. RDES2 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2910
Table 573. RDES3 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2911
Table 574. RDES0 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2912
Table 575. RDES1 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2913
Table 576. RDES2 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2915
Table 577. RDES3 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2916
Table 578. RDES0 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2919
Table 579. RDES1 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2920
Table 580. RDES2 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2920
Table 581. RDES3 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2920
Table 582. ETH_DMA common register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2944
Table 583. ETH_DMA_CH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2944
Table 584. ETH_MTL register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2957
Table 585. Giant Packet Status based on S2KP and JE Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2963
Table 586. Packet Length based on the CST and ACS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2963
Table 587. Ethernet MAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3045
Table 588. HDMI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3057
Table 589. HDMI-CEC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3057
Table 590. Error handling timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3063
Table 591. TXERR timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3064
Table 592. HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3065
Table 593. HDMI-CEC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3073
Table 594. JTAG/Serial-wire debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3076
Table 595. Trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3076
Table 596. Serial-wire trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3076
Table 597. Trigger pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3076
Table 598. Packet request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3080
Table 599. ACK response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3080
Table 600. Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3080
Table 601. JTAG-DP data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3083
Table 602. Debug port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3085
Table 603. MEM-AP registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3095
Table 604. System ROM table 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3099
Table 605. System ROM table 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3100
Table 606. System ROM table 1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 3106
Table 607. System ROM table 2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 3107
Table 608. TSG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3115
Table 609. System CTI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3116
Table 610. System CTI outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3117
Table 611. Cortex-M7 CTI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3117
Table 612. Cortex-M7 CTI outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3118

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Table 613. CTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3133

Table 614. CSTF register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3144
Table 615. ETF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3165
Table 616. TPIU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3183
Table 617. SWO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3195
Table 618. SWTF register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3206
Table 619. DBGMCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3214
Table 620. Cortex-M7 processor ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3215
Table 621. Cortex-M7 PPB ROM table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3215
Table 622. Cortex-M7 processor ROM table register map and reset values . . . . . . . . . . . . . . . . . . 3221
Table 623. Cortex-M7 PPB ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . 3226
Table 624. Cortex-M7 DWT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3238
Table 625. Cortex-M7 ITM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3248
Table 626. Cortex-M7 FPB register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3255
Table 627. Cortex-M7 ETM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3285
Table 628. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3294

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List of figures RM0433

List of figures

Figure 1. System architecture for STM32H742xx, STM32H743/53xx and STM32H750xB devices 105
Figure 2. AXI interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 3. RAM ECC controller implementation schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 4. Connection between RAM ECC controller and RAMECC monitoring unit . . . . . . . . . . . . 141
Figure 5. FLASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 6. Detailed FLASH architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 7. Embedded flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 8. Embedded flash memory usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 9. FLASH protection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 10. FLASH read pipeline architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 11. FLASH write pipeline architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 12. Flash bank swapping sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 13. RDP protection transition scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 14. Example of protected region overlapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 15. Flash memory areas and services in Standard and Secure access modes . . . . . . . . . . . 248
Figure 16. Bootloader state machine in Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 17. Core access to flash memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 18. Power control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 19. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 20. System supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 21. Device startup with VCORE supplied from voltage regulator . . . . . . . . . . . . . . . . . . . . . . 262
Figure 22. Device startup with VCORE supplied in Bypass mode
from external regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 23. Backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 24. USB supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 25. Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 26. BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 27. PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 28. AVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 29. VBAT thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 30. Temperature thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 31. Switching VCORE from VOS1 to VOS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 32. VCORE voltage scaling versus system power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 33. Power control modes detailed state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 34. Dynamic voltage scaling in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 35. Dynamic voltage scaling behavior with D1,
D2 and system in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 36. Dynamic Voltage Scaling D1, D2, system Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 37. Dynamic voltage scaling behavior with D1 and D2 in DStandby mode and
D3 in autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 38. EXTI, RCC and PWR interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 39. Timing diagram of SRAM4-to-LPUART1 transfer with BDMA and D3 domain
in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 40. BDMA and DMAMUX2 interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 41. Timing diagram of LPUART1 transmission with D3 domain
in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Figure 42. RCC Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 43. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

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RM0433 List of figures

Figure 44. Boot sequences versus system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

Figure 45. Top-level clock tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Figure 46. HSE/LSE clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Figure 47. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 48. PLLs Initialization Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Figure 49. Core and bus clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 50. Kernel clock distribution for SAIs and DFSDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 51. Kernel clock distribution for SPIs and SPI/I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Figure 52. Kernel clock distribution for I2Cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Figure 53. Kernel clock distribution for UARTs, USARTs and LPUART1 . . . . . . . . . . . . . . . . . . . . . 359
Figure 54. Kernel clock distribution for LTDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 55. Kernel clock distribution for SDMMC, QUADSPI and FMC . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 56. Kernel clock distribution for USB (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 57. Kernel clock distribution for Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Figure 58. Kernel clock distribution for ADCs, SWPMI, RNG and FDCAN (2) . . . . . . . . . . . . . . . . . . 363
Figure 59. Kernel clock distribution for LPTIMs and HDMI-CEC (2) . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Figure 60. Peripheral allocation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Figure 61. Kernel Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 62. Peripheral kernel clock enable logic details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 63. Bus clock enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 64. RCC mapping overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Figure 65. CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Figure 66. CRS counter behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Figure 67. HSEM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Figure 68. Procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Figure 69. Interrupt state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Figure 70. Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Figure 71. Basic structure of a 5-Volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Figure 72. Input floating / pull up / pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Figure 73. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Figure 74. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 75. High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 76. Analog inputs connected to ADC inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Figure 77. MDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Figure 78. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Figure 79. Peripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Figure 80. Memory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Figure 81. Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Figure 82. FIFO structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Figure 83. BDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Figure 84. DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Figure 85. Synchronization mode of the DMAMUX request line multiplexer channel . . . . . . . . . . . . 702
Figure 86. Event generation of the DMA request line multiplexer channel . . . . . . . . . . . . . . . . . . . . 702
Figure 87. DMA2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Figure 88. Intel 8080 16-bit mode (RGB565) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Figure 89. Intel 8080 18/24-bit mode (RGB888) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 90. EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
Figure 91. Configurable event triggering logic CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
Figure 92. Configurable event triggering logic Any wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
Figure 93. Direct event triggering logic CPU Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
Figure 94. Direct event triggering logic Any Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
Figure 95. D3 domain Pending request clear logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

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Figure 96. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

Figure 97. FMC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Figure 98. FMC memory banks (default mapping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Figure 99. Mode 1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
Figure 100. Mode 1 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
Figure 101. Mode A read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Figure 102. Mode A write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
Figure 103. Mode 2 and mode B read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Figure 104. Mode 2 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Figure 105. Mode B write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
Figure 106. Mode C read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Figure 107. Mode C write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Figure 108. Mode D read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
Figure 109. Mode D write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
Figure 110. Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
Figure 111. Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
Figure 112. Asynchronous wait during a read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Figure 113. Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Figure 114. Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Figure 115. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . . 834
Figure 116. Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . . 836
Figure 117. NAND flash controller waveforms for common memory access. . . . . . . . . . . . . . . . . . . . 850
Figure 118. Access to non ‘CE don’t care’ NAND-flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Figure 119. Burst write SDRAM access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
Figure 120. Burst read SDRAM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
Figure 121. Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) . . . . . . . . . . . . 863
Figure 122. Read access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
Figure 123. Write access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
Figure 124. Self-refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
Figure 125. Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
Figure 126. QUADSPI block diagram when dual-flash mode is disabled . . . . . . . . . . . . . . . . . . . . . . 879
Figure 127. QUADSPI block diagram when dual-flash mode is enabled. . . . . . . . . . . . . . . . . . . . . . . 880
Figure 128. Example of read command in quad-SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Figure 129. Example of a DDR command in quad-SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
Figure 130. NCS when CKMODE = 0 (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Figure 131. NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 893
Figure 132. NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 893
Figure 133. NCS when CKMODE = 1 with an abort (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . 894
Figure 134. DLYB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
Figure 135. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Figure 136. ADC Clock scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
Figure 137. ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Figure 138. ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
Figure 139. ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
Figure 140. ADC3 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Figure 141. ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
Figure 142. Updating the ADC offset calibration factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
Figure 143. Mixing single-ended and differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
Figure 144. Enabling / Disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
Figure 145. Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Figure 146. Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Figure 147. Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937

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Figure 148. Triggers are shared between ADC master and ADC slave . . . . . . . . . . . . . . . . . . . . . . . 939
Figure 149. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Figure 150. Example of JSQR queue of context (sequence change) . . . . . . . . . . . . . . . . . . . . . . . . . 945
Figure 151. Example of JSQR queue of context (trigger change) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Figure 152. Example of JSQR queue of context with overflow before conversion . . . . . . . . . . . . . . . 946
Figure 153. Example of JSQR queue of context with overflow during conversion . . . . . . . . . . . . . . . 947
Figure 154. Example of JSQR queue of context with empty queue (case JQM=0). . . . . . . . . . . . . . . 947
Figure 155. Example of JSQR queue of context with empty queue (case JQM=1). . . . . . . . . . . . . . . 948
Figure 156. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . . 948
Figure 157. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Figure 158. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . 949
Figure 159. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 950
Figure 160. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 950
Figure 161. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 951
Figure 162. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Figure 163. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Figure 164. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Figure 165. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 954
Figure 166. Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 167. Right alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 168. Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Figure 169. Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Figure 170. Example of overrun (OVRMOD = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
Figure 171. Example of overrun (OVRMOD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
Figure 172. AUTDLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . . . 964
Figure 173. AUTDLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Figure 174. AUTDLY=1, regular HW conversions interrupted by injected conversions. . . . . . . . . . . . . . .
(DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
Figure 175. AUTDLY=1, regular continuous conversions interrupted by injected conversions . . . . . . 966
Figure 176. AUTDLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
Figure 177. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Figure 178. ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 969
Figure 179. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) . . . . . . . . . . . . . . 969
Figure 180. ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 970
Figure 181. ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 970
Figure 182. 16-bit result oversampling with 10-bits right shift and rouding . . . . . . . . . . . . . . . . . . . . . 971
Figure 183. Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Figure 184. Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
Figure 185. Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . . 974
Figure 186. Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Figure 187. Oversampling in auto-injected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Figure 188. Dual ADC block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
Figure 189. Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 979
Figure 190. Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 981
Figure 191. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . . 982
Figure 192. Interleaved mode on 1 channel in single conversion mode: dual ADC mode . . . . . . . . . 983
Figure 193. Interleaved conversion with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983

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Figure 194. Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984

Figure 195. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . . 985
Figure 196. Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
Figure 197. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
Figure 198. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . . . . . . . . . . . . 987
Figure 199. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
Figure 200. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
Figure 201. DMA Requests in regular simultaneous mode when DAMDF=0b00 . . . . . . . . . . . . . . . . 988
Figure 202. DMA requests in regular simultaneous mode when DAMDF=0b10 . . . . . . . . . . . . . . . . . 989
Figure 203. DMA requests in interleaved mode when DAMDF=0b10 . . . . . . . . . . . . . . . . . . . . . . . . . 989
Figure 204. Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
Figure 205. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Figure 206. VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Figure 207. Dual-channel DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
Figure 208. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
Figure 209. Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
Figure 210. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . 1050
Figure 211. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Figure 212. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . 1052
Figure 213. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Figure 214. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . 1053
Figure 215. DAC Sample and hold mode phase diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
Figure 216. Comparator functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Figure 217. Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Figure 218. Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Figure 219. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
Figure 220. Scaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
Figure 221. Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102
Figure 222. Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103
Figure 223. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . . . . . . . . 1104
Figure 224. PGA mode, internal gain setting (x2/x4/x8/x16),
inverting input used for filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
Figure 225. PGA mode, non-inverting gain setting (x2/x4/x8/x16)
or inverting gain setting (x-1/x-3/x-7/x-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
Figure 226. Example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
Figure 227. PGA mode, non-inverting gain setting (x2/x4/x8/x16) or inverting gain
setting (x-1/x-3/x-7/x-15) with filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Figure 228. Example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Figure 229. Single DFSDM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
Figure 230. Input channel pins redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Figure 231. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
Figure 232. Clock absence timing diagram for SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
Figure 233. Clock absence timing diagram for Manchester coding . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
Figure 234. First conversion for Manchester coding (Manchester synchronization) . . . . . . . . . . . . . 1132
Figure 235. DFSDM_CHyDATINR registers operation modes and assignment . . . . . . . . . . . . . . . . 1136
Figure 236. Example: Sinc3 filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
Figure 237. DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
Figure 238. DCMI signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
Figure 239. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
Figure 240. Frame capture waveforms in snapshot mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183

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Figure 241. Frame capture waveforms in continuous grab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184

Figure 242. Coordinates and size of the window after cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
Figure 243. Data capture waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
Figure 244. Pixel raster scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
Figure 245. LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Figure 246. LTDC synchronous timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
Figure 247. Layer window programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
Figure 248. Blending two layers with background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
Figure 249. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
Figure 250. JPEG codec block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
Figure 251. RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
Figure 252. Entropy source model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
Figure 253. RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
Figure 254. CRYP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
Figure 255. AES-ECB mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
Figure 256. AES-CBC mode overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
Figure 257. AES-CTR mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
Figure 258. AES-GCM mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
Figure 259. AES-GMAC mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
Figure 260. AES-CCM mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272
Figure 261. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
Figure 262. DES/TDES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
Figure 263. DES/TDES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
Figure 264. DES/TDES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
Figure 265. DES/TDES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
Figure 266. AES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
Figure 267. AES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285
Figure 268. AES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
Figure 269. AES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
Figure 270. Message construction for the Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
Figure 271. AES-CTR mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
Figure 272. AES-CTR mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
Figure 273. Message construction for the Galois/counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293
Figure 274. Message construction for the Galois Message Authentication Code mode . . . . . . . . . . 1298
Figure 275. Message construction for the Counter with CBC-MAC mode. . . . . . . . . . . . . . . . . . . . . 1299
Figure 276. 64-bit block construction according to the data type (IN FIFO). . . . . . . . . . . . . . . . . . . . 1306
Figure 277. 128-bit block construction according to the data type. . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
Figure 278. HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331
Figure 279. Message data swapping feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333
Figure 280. HASH suspend/resume mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339
Figure 281. High-resolution timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
Figure 282. Timer A..E overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
Figure 283. Continuous timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
Figure 284. Single-shot timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
Figure 285. Timer reset resynchronization (prescaling ratio above 32) . . . . . . . . . . . . . . . . . . . . . . . 1363
Figure 286. Repetition rate vs HRTIM_REPxR content in continuous mode. . . . . . . . . . . . . . . . . . . 1364
Figure 287. Repetition counter behavior in single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
Figure 288. Compare events action on outputs: set on compare 1, reset on compare 2 . . . . . . . . . 1366
Figure 289. Timing unit capture circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
Figure 290. Auto-delayed overview (Compare 2 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
Figure 291. Auto-delayed compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
Figure 292. Push-pull mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372

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Figure 293. Push-pull mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373

Figure 294. Complementary outputs with deadtime insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
Figure 295. Deadtime insertion vs deadtime sign (1 indicates negative deadtime) . . . . . . . . . . . . . . 1374
Figure 296. Complementary outputs for low pulse width (SDTRx = SDTFx = 0). . . . . . . . . . . . . . . . 1375
Figure 297. Complementary outputs for low pulse width (SDTRx = SDTFx = 1). . . . . . . . . . . . . . . . 1375
Figure 298. Complementary outputs for low pulse width (SDTRx = 0, SDTFx = 1). . . . . . . . . . . . . . 1375
Figure 299. Complementary outputs for low pulse width (SDTRx = 1, SDTFx=0). . . . . . . . . . . . . . . 1376
Figure 300. Master timer overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377
Figure 301. External event conditioning overview (1 channel represented) . . . . . . . . . . . . . . . . . . . 1380
Figure 302. Latency to external events falling edge (counter reset and output set) . . . . . . . . . . . . 1383
Figure 303. Latency to external events (output reset on external event) . . . . . . . . . . . . . . . . . . . . . . 1383
Figure 304. Event blanking mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 305. Event postpone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 306. External trigger blanking with edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
Figure 307. External trigger blanking, level sensitive triggering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
Figure 308. Event windowing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387
Figure 309. External trigger windowing with edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
Figure 310. External trigger windowing, level sensitive triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
Figure 311. Delayed Idle mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390
Figure 312. Burst mode and delayed protection priorities (DIDL = 0) . . . . . . . . . . . . . . . . . . . . . . . . 1391
Figure 313. Burst mode and delayed protection priorities (DIDL = 1) . . . . . . . . . . . . . . . . . . . . . . . . 1392
Figure 314. Balanced Idle protection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393
Figure 315. Output management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403
Figure 316. HRTIM output states and transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403
Figure 317. Burst mode operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
Figure 318. Burst mode trigger on external event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Figure 319. Delayed burst mode entry with deadtime enabled and IDLESx = 1 . . . . . . . . . . . . . . . . 1409
Figure 320. Delayed Burst mode entry during deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410
Figure 321. Burst mode exit when the deadtime generator is enabled . . . . . . . . . . . . . . . . . . . . . . . 1411
Figure 322. Burst mode emulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413
Figure 323. Carrier frequency signal insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413
Figure 324. HRTIM outputs with Chopper mode enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414
Figure 325. Fault protection circuitry (FAULT1 fully represented, FAULT2..5 partially). . . . . . . . . . . 1415
Figure 326. Fault signal filtering (FLTxF[3:0]= 0010: fSAMPLING = fHRTIM, N = 4) . . . . . . . . . . . . . . 1416
Figure 327. Auxiliary outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
Figure 328. Auxiliary and main outputs during burst mode (DIDLx = 0) . . . . . . . . . . . . . . . . . . . . . . 1419
Figure 329. Deadtime distortion on auxiliary output when exiting burst mode. . . . . . . . . . . . . . . . . . 1419
Figure 330. Counter behavior in synchronized start mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
Figure 331. ADC trigger selection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
Figure 332. Combining several updates on a single hrtim_dac_trgx output . . . . . . . . . . . . . . . . . . . 1425
Figure 333. DMA burst overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429
Figure 334. Burst DMA operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430
Figure 335. Registers update following DMA burst transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1431
Figure 336. Buck converter topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433
Figure 337. Dual Buck converter management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434
Figure 338. Synchronous rectification depending on output current . . . . . . . . . . . . . . . . . . . . . . . . . 1434
Figure 339. Buck with synchronous rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1435
Figure 340. 3-phase interleaved buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
Figure 341. 3-phase interleaved buck converter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437
Figure 342. Transition mode PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437
Figure 343. Transition mode PFC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438
Figure 344. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528

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Figure 345. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1530
Figure 346. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1530
Figure 347. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532
Figure 348. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532
Figure 349. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
Figure 350. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
Figure 351. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . 1534
Figure 352. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . 1534
Figure 353. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
Figure 354. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
Figure 355. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
Figure 356. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
Figure 357. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . 1538
Figure 358. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . 1539
Figure 359. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
Figure 360. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1540
Figure 361. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
Figure 362. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . 1541
Figure 363. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1542
Figure 364. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1543
Figure 365. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
Figure 366. TIM1/TIM8 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
Figure 367. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1545
Figure 368. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546
Figure 369. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
Figure 370. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
Figure 371. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548
Figure 372. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1549
Figure 373. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549
Figure 374. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . 1550
Figure 375. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . 1550
Figure 376. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . 1551
Figure 377. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553
Figure 378. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
Figure 379. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556
Figure 380. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
Figure 381. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1559
Figure 382. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
Figure 383. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . 1561
Figure 384. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
Figure 385. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . 1562
Figure 386. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1563
Figure 387. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565
Figure 388. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . 1567
Figure 389. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . 1568
Figure 390. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1569
Figure 391. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569
Figure 392. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570
Figure 393. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571
Figure 394. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
Figure 395. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574
Figure 396. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . 1575

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Figure 397. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . 1576
Figure 398. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577
Figure 399. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579
Figure 400. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580
Figure 401. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581
Figure 402. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582
Figure 403. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1583
Figure 404. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
Figure 405. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1634
Figure 406. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1634
Figure 407. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
Figure 408. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
Figure 409. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
Figure 410. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637
Figure 411. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . 1637
Figure 412. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . 1638
Figure 413. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639
Figure 414. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639
Figure 415. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
Figure 416. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
Figure 417. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
Figure 418. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . 1642
Figure 419. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643
Figure 420. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1643
Figure 421. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
Figure 422. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . 1644
Figure 423. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1645
Figure 424. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1646
Figure 425. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646
Figure 426. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
Figure 427. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
Figure 428. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
Figure 429. Capture/Compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . 1649
Figure 430. Capture/Compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
Figure 431. Output stage of Capture/Compare channel (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . 1650
Figure 432. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
Figure 433. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
Figure 434. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
Figure 435. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
Figure 436. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1657
Figure 437. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
Figure 438. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660
Figure 439. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661
Figure 440. Retriggerable one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663
Figure 441. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . 1664
Figure 442. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . 1665
Figure 443. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
Figure 444. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667
Figure 445. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
Figure 446. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1669
Figure 447. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
Figure 448. Master/slave connection example with 1 channel only timers . . . . . . . . . . . . . . . . . . . . 1670

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Figure 449. Gating TIM2 with OC1REF of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671

Figure 450. Gating TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
Figure 451. Triggering TIM2 with update of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
Figure 452. Triggering TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
Figure 453. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674
Figure 454. General-purpose timer block diagram (TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
Figure 455. General-purpose timer block diagram (TIM13/TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
Figure 456. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1712
Figure 457. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1712
Figure 458. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
Figure 459. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
Figure 460. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
Figure 461. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
Figure 462. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
Figure 463. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716
Figure 464. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1717
Figure 465. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717
Figure 466. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
Figure 467. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1719
Figure 468. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
Figure 469. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 1720
Figure 470. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
Figure 471. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724
Figure 472. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
Figure 473. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
Figure 474. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727
Figure 475. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
Figure 476. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
Figure 477. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1730
Figure 478. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731
Figure 479. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731
Figure 480. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1763
Figure 481. TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764
Figure 482. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1766
Figure 483. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1766
Figure 484. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1768
Figure 485. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1768
Figure 486. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
Figure 487. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
Figure 488. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
Figure 489. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
Figure 490. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1772
Figure 491. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1773
Figure 492. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1773
Figure 493. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1774
Figure 494. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1775
Figure 495. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1775
Figure 496. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 1776

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Figure 497. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . 1776
Figure 498. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778
Figure 499. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1780
Figure 500. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1781
Figure 501. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782
Figure 502. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783
Figure 503. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . 1783
Figure 504. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1784
Figure 505. Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
Figure 506. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788
Figure 507. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
Figure 508. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
Figure 509. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792
Figure 510. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1793
Figure 511. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794
Figure 512. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
Figure 513. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796
Figure 514. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
Figure 515. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1849
Figure 516. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1849
Figure 517. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
Figure 518. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1851
Figure 519. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1851
Figure 520. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1852
Figure 521. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1852
Figure 522. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853
Figure 523. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1854
Figure 524. Low-power timer block diagram (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . . 1861
Figure 525. Low-power timer block diagram (LPTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1862
Figure 526. Low-power timer block diagram (LPTIM4 and LPTIM5) . . . . . . . . . . . . . . . . . . . . . . . . . 1862
Figure 527. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867
Figure 528. LPTIM output waveform, single counting mode configuration . . . . . . . . . . . . . . . . . . . . 1869
Figure 529. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1869
Figure 530. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . 1870
Figure 531. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1871
Figure 532. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
Figure 533. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
Figure 534. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890
Figure 535. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
Figure 536. RTC block overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
Figure 537. Detailed RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
Figure 538. Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
Figure 539. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1952
Figure 540. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1954
Figure 541. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1956
Figure 542. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1959
Figure 543. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1960
Figure 544. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1961
Figure 545. Slave initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1964

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Figure 546. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . . . . . . . . . . . . 1966
Figure 547. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . . . . . . . . . . . . 1967
Figure 548. Transfer bus diagrams for I2C slave transmitter (mandatory events only) . . . . . . . . . . . 1968
Figure 549. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . . . . . . . . . . . . . 1969
Figure 550. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . . . . . . . . . . . . . 1970
Figure 551. Transfer bus diagrams for I2C slave receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1970
Figure 552. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1972
Figure 553. Master initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974
Figure 554. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974
Figure 555. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1975
Figure 556. Transfer sequence flow for I2C master transmitter for N ≤ 255 bytes . . . . . . . . . . . . . . 1976
Figure 557. Transfer sequence flow for I2C master transmitter for N > 255 bytes . . . . . . . . . . . . . . 1977
Figure 558. Transfer bus diagrams for I2C master transmitter
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1978
Figure 559. Transfer sequence flow for I2C master receiver for N ≤ 255 bytes . . . . . . . . . . . . . . . . 1980
Figure 560. Transfer sequence flow for I2C master receiver for N > 255 bytes . . . . . . . . . . . . . . . . 1981
Figure 561. Transfer bus diagrams for I2C master receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1982
Figure 562. Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1986
Figure 563. Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . . . . 1990
Figure 564. Transfer bus diagrams for SMBus slave transmitter (SBC = 1) . . . . . . . . . . . . . . . . . . . 1990
Figure 565. Transfer sequence flow for SMBus slave receiver N bytes + PEC. . . . . . . . . . . . . . . . . 1992
Figure 566. Bus transfer diagrams for SMBus slave receiver (SBC = 1). . . . . . . . . . . . . . . . . . . . . . 1993
Figure 567. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994
Figure 568. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996
Figure 569. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2002
Figure 570. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
Figure 571. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2024
Figure 572. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026
Figure 573. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2029
Figure 574. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2030
Figure 575. usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2033
Figure 576. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2034
Figure 577. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2035
Figure 578. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2042
Figure 579. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043
Figure 580. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 2046
Figure 581. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 2047
Figure 582. USART example of synchronous master transmission. . . . . . . . . . . . . . . . . . . . . . . . . . 2048
Figure 583. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2048
Figure 584. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2049
Figure 585. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2050
Figure 586. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2052
Figure 587. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2054
Figure 588. IrDA SIR ENDEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2058
Figure 589. IrDA data modulation (3/16) - Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2058
Figure 590. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2060
Figure 591. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2061

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Figure 592. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2061

Figure 593. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2062
Figure 594. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2063
Figure 595. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . . . . . . . 2066
Figure 596. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2066
Figure 597. LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2108
Figure 598. LPUART word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2110
Figure 599. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2112
Figure 600. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2114
Figure 601. lpuart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2117
Figure 602. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2121
Figure 603. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2122
Figure 604. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2124
Figure 605. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2125
Figure 606. Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2126
Figure 607. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2126
Figure 608. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2127
Figure 609. Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2130
Figure 610. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2130
Figure 611. SPI2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2160
Figure 612. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2162
Figure 613. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2162
Figure 614. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2163
Figure 615. Master and three independent slaves at star topology . . . . . . . . . . . . . . . . . . . . . . . . . . 2164
Figure 616. Master and three slaves at circular (daisy chain) topology . . . . . . . . . . . . . . . . . . . . . . . 2166
Figure 617. Multimaster application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167
Figure 618. Scheme of SS control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2169
Figure 619. Data flow timing control (SSOE=1, SSOM=0, SSM=0) . . . . . . . . . . . . . . . . . . . . . . . . . 2169
Figure 620. SS interleaving pulses between data (SSOE=1, SSOM=1,SSM=0). . . . . . . . . . . . . . . . 2170
Figure 621. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2172
Figure 622. Data alignment when data size is not equal to 8-bit, 16-bit or 32-bit . . . . . . . . . . . . . . . 2173
Figure 623. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 2181
Figure 624. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183
Figure 625. Optional configurations of slave’s behavior at detection of underrun condition . . . . . . . 2185
Figure 626. Low-power mode application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2189
Figure 627. Waveform examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2196
Figure 628. Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . . . . . . . . . . . . . . . 2197
Figure 629. I2S Philips standard waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2197
Figure 630. Master MSB Justified 16-bit or 32-bit full-accuracy length . . . . . . . . . . . . . . . . . . . . . . . 2198
Figure 631. Master MSB justified 16 or 24-bit data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2198
Figure 632. Slave MSB justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2199
Figure 633. LSB justified 16 or 24-bit data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2199
Figure 634. Master PCM when the frame length is equal the data length . . . . . . . . . . . . . . . . . . . . . 2200
Figure 635. Master PCM standard waveforms (16 or 24-bit data length) . . . . . . . . . . . . . . . . . . . . . 2200
Figure 636. Slave PCM waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2201
Figure 637. Startup sequence, I2S Philips standard, master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2204
Figure 638. Startup sequence, I2S Philips standard, slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2204
Figure 639. Stop sequence, I2S Philips standard, master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2205

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Figure 640. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2206

Figure 641. Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2208
Figure 642. Handling of underrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2210
Figure 643. Handling of overrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2211
Figure 644. Frame error detection, with FIXCH=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2212
Figure 645. Frame error detection, with FIXCH=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2212
Figure 646. SAI functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239
Figure 647. Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2243
Figure 648. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . 2245
Figure 649. FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2246
Figure 650. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . 2247
Figure 651. First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2247
Figure 652. Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2248
Figure 653. PDM typical connection and timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2252
Figure 654. Detailed PDM interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2253
Figure 655. Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2254
Figure 656. SAI_ADR format in TDM, 32-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2255
Figure 657. SAI_ADR format in TDM, 16-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2256
Figure 658. SAI_ADR format in TDM, 8-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2257
Figure 659. AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2260
Figure 660. Example of typical AC’97 configuration on devices featuring at least
2 embedded SAIs (three external AC’97 decoders) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2261
Figure 661. SPDIF format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2262
Figure 662. SAI_xDR register ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263
Figure 663. Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . 2267
Figure 664. Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . 2268
Figure 665. Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2269
Figure 666. Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2270
Figure 667. FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2270
Figure 668. SPDIFRX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2306
Figure 669. S/PDIF sub-frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2307
Figure 670. S/PDIF block format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2307
Figure 671. S/PDIF Preambles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2308
Figure 672. Channel coding example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2309
Figure 673. SPDIFRX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310
Figure 674. Noise filtering and edge detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310
Figure 675. Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2312
Figure 676. Synchronization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2314
Figure 677. Synchronization process scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2315
Figure 678. SPDIFRX States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2316
Figure 679. SPDIFRX_FMTx_DR register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2318
Figure 680. Channel/user data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2319
Figure 681. S/PDIF overrun error when RXSTEO = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2321
Figure 682. S/PDIF overrun error when RXSTEO = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2322
Figure 683. SPDIFRX interface interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2323
Figure 684. S1 signal coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2337
Figure 685. S2 signal coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2337
Figure 686. SWPMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2339
Figure 687. SWP bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2342
Figure 688. SWP frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2343
Figure 689. SWPMI No software buffer mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2344
Figure 690. SWPMI No software buffer mode transmission, consecutive frames . . . . . . . . . . . . . . . 2345

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Figure 691. SWPMI Multi software buffer mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2347

Figure 692. SWPMI No software buffer mode reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2349
Figure 693. SWPMI single software buffer mode reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2350
Figure 694. SWPMI Multi software buffer mode reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2352
Figure 695. SWPMI single buffer mode reception with CRC error. . . . . . . . . . . . . . . . . . . . . . . . . . . 2353
Figure 696. MDIOS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
Figure 697. MDIO protocol write frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2367
Figure 698. MDIO protocol read frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2367
Figure 699. SDMMC “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2379
Figure 700. SDMMC (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2379
Figure 701. SDMMC (multiple) block write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2380
Figure 702. SDMMC (sequential) stream read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2380
Figure 703. SDMMC (sequential) stream write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2380
Figure 704. SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2382
Figure 705. SDMMC Command and data phase relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2384
Figure 706. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2386
Figure 707. Command/response path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2387
Figure 708. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2388
Figure 709. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2394
Figure 710. DDR mode data packet clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2395
Figure 711. DDR mode CRC status / boot acknowledgment clocking. . . . . . . . . . . . . . . . . . . . . . . . 2395
Figure 712. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2396
Figure 713. CLKMUX unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2407
Figure 714. Asynchronous interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2412
Figure 715. Synchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2412
Figure 716. Synchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2413
Figure 717. Asynchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2414
Figure 718. Asynchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2414
Figure 719. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . . . . . . . . . . . . . . . . . . . . 2417
Figure 720. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104 . . . . . . . . . . . . . . . . . . . . . . 2417
Figure 721. Read Wait with SDMMC_CK < 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2418
Figure 722. Read Wait with SDMMC_CK > 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2419
Figure 723. CMD12 stream timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2421
Figure 724. CMD5 Sleep Awake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2423
Figure 725. Normal boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425
Figure 726. Alternative boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2426
Figure 727. Command response R1b busy signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2427
Figure 728. SDMMC state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2428
Figure 729. Card cycle power / power up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2429
Figure 730. CMD11 signal voltage switch sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2430
Figure 731. Voltage switch transceiver typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2432
Figure 732. CAN subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2461
Figure 733. FDCAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2463
Figure 734. Transceiver delay measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2468
Figure 735. Pin control in bus monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2470
Figure 736. Pin control in loop back mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2472
Figure 737. Message RAM configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2473
Figure 738. Standard message ID filter path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2476
Figure 739. Extended message ID filter path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2477
Figure 740. Example of mixed configuration dedicated Tx buffers / Tx FIFO . . . . . . . . . . . . . . . . . . 2483
Figure 741. Example of mixed configuration dedicated Tx buffers / Tx queue . . . . . . . . . . . . . . . . . 2483
Figure 742. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2485

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Figure 743. Bypass operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2487

Figure 744. FSM calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2488
Figure 745. Cycle time and global time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2503
Figure 746. TTCAN level 0 and level 2 drift compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2504
Figure 747. Level 0 schedule synchronization state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2511
Figure 748. Level 0 master to slave relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2512
Figure 749. USB1 OTG_HS high-speed block diagram (OTG_HS1) . . . . . . . . . . . . . . . . . . . . . . . . 2594
Figure 750. USB2 OTG_HS high-speed block diagram (OTG_HS2) . . . . . . . . . . . . . . . . . . . . . . . . 2594
Figure 751. OTG_HS A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2597
Figure 752. OTG_HS peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599
Figure 753. OTG_HS host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2603
Figure 754. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . . . . . . . . . . . . 2607
Figure 755. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2609
Figure 756. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 2610
Figure 757. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . 2611
Figure 758. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2615
Figure 759. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2720
Figure 760. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2721
Figure 761. Normal bulk/control OUT/SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2722
Figure 762. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2726
Figure 763. Normal interrupt OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2729
Figure 764. Normal interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2734
Figure 765. Isochronous OUT transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2736
Figure 766. Isochronous IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2739
Figure 767. Normal bulk/control OUT/SETUP transactions - DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 2741
Figure 768. Normal bulk/control IN transaction - DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2743
Figure 769. Normal interrupt OUT transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2744
Figure 770. Normal interrupt IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2745
Figure 771. Normal isochronous OUT transaction - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
Figure 772. Normal isochronous IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2747
Figure 773. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2753
Figure 774. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2755
Figure 775. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2762
Figure 776. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2771
Figure 777. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2772
Figure 778. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2773
Figure 779. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2774
Figure 780. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2776
Figure 781. Ethernet high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2784
Figure 782. DMA transmission flow (standard mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2787
Figure 783. DMA transmission flow (OSP mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2789
Figure 784. Receive DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2791
Figure 785. Overview of MAC transmission flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2795
Figure 786. MAC reception flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2797
Figure 787. Packet filtering sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2801
Figure 788. Networked time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2810
Figure 789. Propagation delay calculation in clocks supporting
peer-to-peer path correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811
Figure 790. System time update using fine correction method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2821
Figure 791. TCP segmentation offload overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2838
Figure 792. TCP segmentation offload flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2839
Figure 793. Header and payload fields of segmented packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2842

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Figure 794. Supported PHY interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2852

Figure 795. SMA Interface block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2852
Figure 796. MDIO packet structure (Clause 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2853
Figure 797. MDIO packet structure (Clause 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2854
Figure 798. SMA write operation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2856
Figure 799. Write data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2857
Figure 800. Read data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2857
Figure 801. Media independent interface (MII) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2859
Figure 802. RMII block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2861
Figure 803. Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2862
Figure 804. Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2863
Figure 805. LPI transitions (Transmit, 100 Mbds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2871
Figure 806. LPI Tx clock gating (when LPITCSE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2872
Figure 807. LPI transitions (receive, 100 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2873
Figure 808. Descriptor ring structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2894
Figure 809. DMA descriptor ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2895
Figure 810. Transmit descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2896
Figure 811. Transmit descriptor write-back format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2901
Figure 812. Transmit context descriptor format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2905
Figure 813. Receive normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2909
Figure 814. Receive normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2912
Figure 815. Receive context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2919
Figure 816. Generation of ETH_DMAISR flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2937
Figure 817. HDMI-CEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3058
Figure 818. Message structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3058
Figure 819. Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3059
Figure 820. Bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3059
Figure 821. Signal free time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3060
Figure 822. Arbitration phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3060
Figure 823. SFT of three nominal bit periods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3060
Figure 824. Error bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3061
Figure 825. Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3063
Figure 826. TXERR detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3064
Figure 827. Block diagram of debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3075
Figure 828. Power domains of debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3077
Figure 829. Clock domains of debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3078
Figure 830. SWD successful data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3081
Figure 831. JTAG TAP state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3082
Figure 832. Debug and access port connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3093
Figure 833. APB-D CoreSight component topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3101
Figure 834. Global timestamp distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3109
Figure 835. Embedded cross trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3116
Figure 836. Mapping of trigger inputs to outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3118
Figure 837. ETF state transition diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3147
Figure 838. Cortex-M7 CoreSight topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3216

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1 Documentation conventions

1.1 General information

The STM32H742, STM32H743/753 and STM32H750 devices have an Arm®(a) Cortex®-M7
with FPU core.

1.2 List of abbreviations for registers

The following abbreviations(b) are used in register descriptions:

read/write (rw) Software can read and write to this bit.

read-only (r) Software can only read this bit.
write-only (w) Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo) Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.) Reserved bit, must be kept at reset value.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of
them may not be used in the current document.

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Documentation conventions RM0433

1.3 Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
• Word: data of 32-bit length.
• Half-word: data of 16-bit length.
• Byte: data of 8-bit length.
• Double word: data of 64-bit length.
• Flash word: data of 256-bit length
• IAP (in-application programming): IAP is the ability to re-program the flash memory
of a microcontroller while the user program is running.
• ICP (in-circuit programming): ICP is the ability to program the flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
• Option bytes: product configuration bits stored in the flash memory.
• AHB: advanced high-performance bus.
• APB: advanced peripheral bus.
• AXI: Advanced extensible interface protocol.
• PCROP: proprietary code readout protection.
• RDP: readout protection.

1.4 Availability of peripherals

For availability of peripherals and their number across all sales types, refer to the particular
device datasheet.
The following table shows the availability of peripherals per product.The below legend is
used
1: STM32H742xI/G
2: STM32H743xI/G
3: STM32H750xB
4: STM32H753xI/G

Table 1. Peripherals versus products

Peripheral name Availability Peripheral name Availability Peripheral name Availability

RAMECC 1-2-3-4 COMP 1-2-3-4 LPUART 1-2-3-4

(1)
FLASH 1-2-3-4 OPAMP 1-2-3-4 SPI 1-2-3-4
PWR 1-2-3-4 DFSDM 1-2-3-4 SAI 1-2-3-4
RCC 1-2-3-4 DCMI 1-2-3-4 SPDIFRX 1-2-3-4
CRS 1-2-3-4 LTDC 2-3-4 SWPMI 1-2-3-4
HSEM 1-2-3-4 JPEG 2-3-4 MDIOS 1-2-3-4
GPIO 1-2-3-4 RNG 1-2-3-4 SDMMC 1-2-3-4
SYSCFG 1-2-3-4 CRYP 3-4 FDCAN 1-2-3-4
MDMA 1-2-3-4 HASH 3-4 OTG_HS 1-2-3-4

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RM0433 Documentation conventions

Table 1. Peripherals versus products (continued)

Peripheral name Availability Peripheral name Availability Peripheral name Availability

DMA 1-2-3-4 HRTIM 1-2-3-4 ETH 1-2-3-4

BDMA 1-2-3-4 TIM1/TIM8 1-2-3-4 HDMI-CEC 1-2-3-4
TIM2/TIM3/TIM4/
DMAMUX 1-2-3-4 1-2-3-4 - -
TIM5
TIM12/TIM13/TIM
DMA2D 1-2-3-4 1-2-3-4 - -
14
TIM15/TIM16/TIM
NVIC 1-2-3-4 1-2-3-4 - -
17
EXTI 1-2-3-4 TIM6/TIM7 1-2-3-4 - -
CRC 1-2-3-4 LPTIM 1-2-3-4 - -
FMC 1-2-3-4 WWDG 1-2-3-4 - -
QUADSPI 1-2-3-4 IWDG 1-2-3-4 - -
DLYB 1-2-3-4 RTC 1-2-3-4 - -
ADC 1-2-3-4 I2C 1-2-3-4 - -
DAC 1-2-3-4 USART/UART 1-2-3-4 - -
VREFBUF 1-2-3-4 - - - -
1. STBM32H750x embedded flash memory differs from the other products. Please refer to Section 4:
Embedded flash memory (FLASH) for more details on flash memory organization.

Table 2. Availability of security features

STM32H750xB and STM32H742xI/G and
Security feature
STM32H753xI STM32H743xI/G

Embedded flash memory (FLASH):

– Flash Secure-only area
Security memory management:
– Secure access mode Available Not available
– Root secure services (RSS)
Cryptographic processor (CRYP)
Hash processor (HASH)

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2 Memory and bus architecture

2.1 System architecture

An AXI bus matrix, two AHB bus matrices and bus bridges allow interconnecting bus
masters with bus slaves, as illustrated in Table 3 and Figure 1.

Table 3. Bus-master-to-bus-slave interconnect

Bus master / type(1)
Cortex-M7 - AXIM

Cortex-M7 - AHBP

Cortex-M7 - ITCM

Cortex-M7 -DTCM

DMA1 - PERIPH

DMA2 - PERIPH

SDMMC2 - AHB
Eth. MAC - AHB

USBHS1 - AHB

USBHS2 - AHB
MDMA - AHBS

DMA1 - MEM

DMA2 - MEM

BDMA - AHB
MDMA - AXI
SDMMC1

DMA2D

LTDC
Bus slave / type(1) Interconnect path and type(2)

ITCM - - X - - - X - - - - - - - - - - -
DTCM - - - X - - X - - - - - - - - - - -
AHB3 peripherals X - - - - X - - - X X X X X X X X -
APB3 peripherals X - - - - X - - - X X X X X X X X -
Flash bank 1 X - - - X X - X X X X X X X X X X -
Flash bank 2(3) X - - - X X - X X X X X X X X X X -
AXI SRAM X - - - X X - X X X X X X X X X X -
QUADSPI X - - - X X - X X X X X X X X X X -
FMC X - - - X X - X X X X X X X X X X -
SRAM 1 X - - - - X - X - X X X X X X X X -
SRAM 2 X - - - - X - X - X X X X X X X X -
SRAM 3 X - - - - X - X - X X X X X X X X -
AHB1 peripherals - X - - - X - X - X X X X - - - - -
APB1 peripherals - X - - - X - X - X X X X - - - - -
AHB2 peripherals - X - - - - - - - X X X X - - - - -
APB2 peripherals - X - - - X - X - X X X X - - - - -
AHB4 peripherals X - - - - X - - - X X X X X X X X X

APB4 peripherals X - - - - X - - - X X X X X X X X X

SRAM4 X - - - - X - - - X X X X X X X X X

Backup RAM X - - - - X - - - X X X X X X X X X

1. Bold font type denotes 64-bit bus, plain type denotes 32-bit bus.
2. “X” = access possible, “-” = access not possible, shading = access useful/usable.
3. Bank 2 is not available on STM32H750xB devices.

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RM0433
ITCM

SDMMC2
Ethernet
DMA1

DMA2
AHBP

MAC
Cortex®-M7

USB

USB
HS1

HS2
ITCM-RAM
AHBS
DTCM-RAM L1-Cache

DMA2_PERIPH
DMA1_PERIPH
DMA1_MEM

DMA2_MEM
DTCM AXIM
SDMMC1 MDMA DMA2D LTDC D1-to-D2 AHB bus

AHB
APB3

APB
SRAM1
AHB
AHB3 SRAM2
AXI Flash
Bank 1(1) SRAM3

AXI Flash AHB1

Bank 2(1)

APB
AXI FMC AHB2
RM0433 Rev 8

AXI
QUADSPI APB1
AXI AXI
SRAM APB2

GPV 64-bit AXI bus matrix

D1 Domain
D2-to-D1 AHB bus
32-bit AHB bus matrix
D2 Domain
D2-to-D1 AHB bus

D2-to-D3 AHB bus

Memory and bus architecture

Flash memory bank 2 is not available on STM32H750xB devices. D1-to-D3 AHB bus BDMA

Legend
TCM AHB
32-bit bus AHB4 APB4
AXI APB
64-bit bus Master interface
SRAM4
Bus multiplexer Slave interface
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32-bit AHB bus matrix Bkp SRAM

D3 Domain
MSv39741V6
Memory and bus architecture RM0433

2.1.1 Bus matrices

AXI bus matrix in D1 domain
The D1 domain multi AXI bus matrix ensures and arbitrates concurrent accesses from
multiple masters to multiple slaves. This allows efficient simultaneous operation of high-
speed peripherals.
The arbitration uses a round-robin algorithm with QoS capability.
Refer to Section 2.2: AXI interconnect matrix (AXIM) for more information on AXI
interconnect.

AHB bus matrices in D2 and D3 domains

The AHB bus matrices in D2 and D3 domains ensure and arbitrate concurrent accesses
from multiple masters to multiple slaves. This allows efficient simultaneous operation of
high-speed peripherals.
The arbitration uses a round-robin algorithm.

2.1.2 TCM buses

The DTCM and ITCM (data and instruction tightly coupled RAMs) are connected through
dedicated TCM buses directly to the Cortex-M7 core. The MDMA controller can access the
DTCM and ITCM through AHBS, a specific CPU slave AHB. The ITCM is accessed by
Cortex-M7 at CPU clock speed, with zero wait states.

2.1.3 Bus-to-bus bridges

To allow peripherals with different types of buses to communicate together, there is a
number of bus-to-bus bridges in the system.
The AHB/APB bridges in D1 and D3 domains allow connecting peripherals on APB3 and
APB4 to AHB3 and AHB4, respectively. The AHB/APB bridges in D2 domain allow
peripherals on APB1 and APB2 to connect to AHB1. These AHB/APB bridges provide full
synchronous interfacing, which allows the APB peripherals to operate with clocks
independent of AHB that they connect to.
The AHB/APB bridges also allow APB1 and APB2 peripherals to connect to DMA1 and
DMA2 peripheral buses, respectively, without transiting through AHB1.
The AHB/APB bridges convert 8-bit / 16-bit APB data to 32-bit AHB data, by replicating it to
the three upper bytes / the upper half-word of the 32-bit word.
The AXI bus matrix incorporates AHB/AXI bus bridge functionality on its slave bus
interfaces. The AXI/AHB bus bridges on its master interfaces marked as 32-bit in Figure 1
are outside the matrix.
The Cortex-M7 CPU provides AHB/TCM-bus (ITCM and DTCM buses) translation from its
AHBS slave AHB, allowing the MDMA controller to access the ITCM and DTCM.

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2.1.4 Inter-domain buses

D2-to-D1 AHB
This 32-bit bus connects the D2 domain to the AXI bus matrix in the D1 domain. It allows
bus masters in the D2 domain to access resources (bus slaves) in the D1 domain and
indirectly, via the D1-to-D3 AHB, in the D3 domain.

D1-to-D2 AHB
This 32-bit bus connects the D1 domain to the D2 domain AHB bus matrix. It allows bus
masters in the D1 domain to access resources (bus slaves) in the D2 domain.

D1-to-D3 AHB
This 32-bit bus connects the D1 domain to the D3 domain AHB bus matrix. It allows bus
masters in the D1 domain to access resources (bus slaves) in the D3 domain.

D2-to-D3 AHB
This 32-bit bus connects the D2 domain to the D3 domain AHB bus matrix. It allows bus
masters in the D2 domain to access resources (bus slaves) in the D3 domain.

2.1.5 CPU buses

Cortex®-M7 AXIM bus
The Cortex®-M7 CPU uses the 64-bit AXIM bus to access all memories (excluding ITCM,
and DTCM) and AHB3, AHB4, APB3 and APB4 peripherals (excluding AHB1, APB1 and
APB2 peripherals).
The AXIM bus connects the CPU to the AXI bus matrix in the D1 domain.

Cortex®-M7 ITCM bus

The Cortex®-M7 CPU uses the 64-bit ITCM bus for fetching instructions from and accessing
data in the ITCM.

Cortex®-M7 DTCM bus

The Cortex®-M7 CPU uses the 2x32-bit DTCM bus for accessing data in the DTCM. The
2x32-bit DTCM bus allows load/load and load/store instruction pairs to be dual-issued on
the DTCM memory. It can also fetch instructions.

Cortex®-M7 AHBS bus

The Cortex®-M7 CPU uses the 32-bit AHBS slave bus to allow the MDMA controller to
access the ITCM and the DTCM.

Cortex®-M7 AHBP bus

The Cortex®-M7 CPU uses the 32-bit AHBP bus for accessing AHB1, AHB2, APB1 and
APB2 peripherals via the AHB bus matrix in the D2 domain.

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2.1.6 Bus master peripherals

SDMMC1
The SDMMC1 uses a 32-bit bus, connected to the AXI bus matrix, through which it can
access internal AXI SRAM and Flash memories, and external memories through the Quad-
SPI controller and the FMC.

SDMMC2
The SDMMC2 uses a 32-bit bus, connected to the AHB bus matrix in D2 domain. Through
the system bus matrices, it can access the internal AXI SRAM, SRAM1, SRAM2, SRAM3
and Flash memories, and external memories through the Quad-SPI controller and the FMC.

MDMA controller
The MDMA controller has two bus masters: an AXI 64-bit bus, connected to the AXI bus
matrix and an AHB 32-bit bus connected to the Cortex-M7 AHBS slave bus.
The MDMA is optimized for DMA data transfers between memories since it supports linked
list transfers that allow performing a chained list of transfers without the need for CPU
intervention. Through the system bus matrices and the Cortex-M7 AHBS slave bus, the
MDMA can access all internal and external memories through the Quad-SPI controller and
the FMC.

DMA1 and DMA2 controllers

The DMA1 and DMA2 controllers have two 32-bit buses - memory bus and peripheral bus,
connected to the AHB bus matrix in D2 domain.
The memory bus allows DMA data transfers between memories. Through the system bus
matrices, the memory bus can access all internal memories except ITCM and DTCM, and
external memories through the Quad-SPI controller and the FMC.
The peripheral bus allows DMA data transfers between two peripherals, between two
memories or between a peripheral and a memory. Through the system bus matrices, the
peripheral bus can access all internal memories except ITCM and DTCM, external
memories through the Quad-SPI controller and the FMC, and all AHB and APB peripherals.
A direct access to APB1 and APB2 is available, without passing through AHB1. Direct path
to APB1 and APB2 bridges allows reducing the bandwidth usage on AHB1 bus by improving
data treatment efficiency for APB and AHB peripherals.

BDMA controller
The BDMA controller uses a 32-bit bus, connected to the AHB bus matrix in D3 domain, for
DMA data transfers between two peripherals, between two memories or between a
peripheral and a memory. BDMA transfers are limited to the D3 domain resources. It can
access the internal SRAM4, backup RAM, and AHB4 and APB4 peripherals through the
AHB bus matrix in the D3 domain.

Chrom-Art Accelerator (DMA2D)

The DMA2D graphics accelerator uses a 64-bit bus, connected to the AXI bus matrix.
Through the system bus matrices, internal AXI SRAM, SRAM1, SRAM2, SRAM3 and Flash
memories, and external memories through the Quad-SPI controller and the FMC.

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LCD-TFT controller (LTDC)

The LCD-TFT display controller, LTDC, uses a 64-bit bus, connected to the AXI bus matrix,
through which it can access internal AXI SRAM and Flash memories, and external
memories through the Quad-SPI controller and the FMC.

Ethernet MAC
The Ethernet MAC uses a 32-bit bus, connected to the AHB bus matrix in the D2 domain.
Through the system bus matrices, it can access all internal memories except ITCM and
DTCM, and external memories through the Quad-SPI controller and the FMC.

USBHS1 and USBHS2 peripherals

The USBHS1 and USBHS2 peripherals use 32-bit buses, connected to the AHB bus matrix
in the D2 domain. Through the system bus matrices, they can access all internal memories
except ITCM and DTCM, and external memories through the Quad-SPI controller and the
FMC.

2.1.7 Clocks to functional blocks

Upon reset, clocks to blocks such as peripherals and some memories are disabled (except
for the SRAM, DTCM, ITCM and Flash memory). To operate a block with no clock upon
reset, the software must first enable its clock through RCC_AHBxENR or RCC_APBxENR
register, respectively.

2.2 AXI interconnect matrix (AXIM)

2.2.1 AXI introduction

The AXI (advanced extensible interface) interconnect is based on the Arm® CoreLink™
NIC-400 Network Interconnect. The interconnect has six initiator ports, or ASIBs (AMBA
slave interface blocks), and seven target ports, or AMIBs (AMBA master interface blocks).
The ASIBs are connected to the AMIBs via an AXI switch matrix.
Each ASIB is a slave on an AXI bus or AHB (advanced high-performance bus). Similarly,
each AMIB is a master on an AXI or AHB bus. Where an ASIB or AMIB is connected to an
AHB, it converts between the AHB and the AXI protocol.
The AXI interconnect includes a GPV (global programmer view) which contains registers for
configuring certain parameters, such as the QoS (quality of service) level at each ASIB.
Any accesses to unallocated address space are handled by the default slave, which
generates the return signals. This ensures that such transactions complete and do not block
the issuing master and ASIB.

2.2.2 AXI interconnect main features

• 64-bit AXI bus switch matrix with six ASIBs and seven AMIBs, in D1 domain
• AHB/AXI bridge function built into the ASIBs
• concurrent connectivity of multiple ASIBs to multiple AMIBs
• programmable traffic priority management (QoS - quality of service)
• software-configurable via GPV

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2.2.3 AXI interconnect functional description

Block diagram
The AXI interconnect is shown in Figure 2.

Figure 2. AXI interconnect

Masters: D2 AHB C-M7 SDMMC1 MDMA DMA2D LTDC

AHB AXI AHB AXI AXI AXI

ASIBs: INI 1 INI 2 INI 3 INI 4 INI 5 INI 6

default
GPV AXI switch matrix
slave

AXI
AMIBs: TARG 1 TARG 2 TARG 3 TARG 4 TARG 5 TARG 6 TARG 7
interconnect

AXI AXI AXI AXI AXI AXI AXI

AXI/AHB AXI/AHB AXI

Flash A Flash B FMC QSPI
Slaves: bridge bridge SRAM

AHB AHB
32-bit bus
AHB3 periphs D2 domain
64-bit bus
D3 domain MSv39758V1

ASIB configuration
Table 4 summarizes the characteristics of the ASIBs.

Table 4. ASIB configuration

Bus R/W
ASIB Connected master Protocol
width issuing

INI 1 AHB from D2 domain AHB-lite 32 1/4

INI 2 Cortex-M7 AXI4 64 7/32
INI 3 SDMMC1 AHB-lite 32 1/4
INI 4 MDMA AXI4 64 4/1
INI 5 DMA2D AXI4 64 2/1
INI 6 LTDC AXI4 64 1/1

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RM0433 Memory and bus architecture

AMIB configuration
Table 5 summarizes the characteristics of the AMIBs.

Table 5. AMIB configuration

Bus R/W/Total
AMIB Connected slave Protocol
width acceptance

TARG 1 Peripheral 3 and D3 AHB AXI4(1) 32 1/1/1

(1)
TARG 2 D2 AHB AXI4 32 1/1/1
TARG 3 Flash A AXI4 64 3/2/5
TARG 4 Flash B AXI4 64 3/2/5
TARG 5 FMC AXI4 64 3/3/6
TARG 6 QUADSPI AXI4 64 2/1/3
TARG 7 AXI SRAM AXI3 64 2/2/2
1. Conversion to AHB protocol is done via an AXI/AHB bridge sitting between AXI interconnect and the
connected slave.

Quality of service (QoS)

The AXI switch matrix uses a priority-based arbitration when two ASIB simultaneously
attempt to access the same AMIB. Each ASIB has programmable read channel and write
channel priorities, known as QoS, from 0 to 15, such that the higher the value, the higher the
priority. The read channel QoS value is programmed in the AXI interconnect - INI x read
QoS register (AXI_INIx_READ_QOS), and the write channel in the AXI interconnect - INI x
write QoS register (AXI_INIx_WRITE_QOS). The default QoS value for all channels is 0
(lowest priority).
If two coincident transactions arrive at the same AMIB, the higher priority transaction passes
before the lower priority. If the two transactions have the same QoS value, then a least-
recently-used (LRU) priority scheme is adopted.
The QoS values should be programmed according to the latency requirements for the
application. Setting a higher priority for an ASIB ensures a lower latency for transactions
initiated by the associated bus master. This can be useful for real-time-constrained tasks,
such as graphics processing (LTDC, DMA2D). Assigning a high priority to masters that can
make many and frequent accesses to the same slave (such as the Cortex-M7 CPU) can
block access to that slave by other lower-priority masters.

Global programmer view (GPV)

The GPV contains configuration registers for the AXI interconnect (see Section 2.2.4).
These registers are only accessible by the Cortex-M7 CPU.

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2.2.4 AXI interconnect registers

AXI interconnect - peripheral ID4 register (AXI_PERIPH_ID_4)
Address offset: 0x1FD0
Reset value: 0x0000 0004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0]

r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 4KCOUNT[3:0]: Register file size
0x0: N/A
Bits 3:0 JEP106CON[3:0]: JEP106 continuation code
0x4: Arm®

AXI interconnect - peripheral ID0 register (AXI_PERIPH_ID_0)

Address offset: 0x1FE0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0]

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PARTNUM[7:0]: Peripheral part number bits 0 to 7
0x00: Part number = 0x400

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AXI interconnect - peripheral ID1 register (AXI_PERIPH_ID_1)

Address offset: 0x1FE4
Reset value: 0x0000 00B4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8]

r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 JEP106ID[3:0]: JEP106 identity bits 0 to 3
0xB: Arm® JEDEC code
Bits 3:0 PARTNUM[11:8]: Peripheral part number bits 8 to 11
0x4: Part number = 0x400

AXI interconnect - peripheral ID2 register (AXI_PERIPH_ID_2)

Address offset: 0x1FE8
Reset value: 0x0000 002B

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4]

r r r

Bits 7:4 REVISION[3:0]: Peripheral revision number

0x2: r0p2
Bit 3 JEDEC: JEP106 code flag
0x1: JEDEC allocated code
Bits 2:0 JEP106ID[6:4]: JEP106 Identity bits 4 to 6
0x3: Arm® JEDEC code

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AXI interconnect - peripheral ID3 register (AXI_PERIPH_ID_3)

Address offset: 0x1FEC
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. REV_AND[3:0] CUST_MOD_NUM[3:0]

r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 REV_AND[3:0]: Customer version
0: None
Bits 3:0 CUST_MOD_NUM[3:0]: Customer modification
0: None

AXI interconnect - component ID0 register (AXI_COMP_ID_0)

Address offset: 0x1FF0
Reset value: 0x0000 000D

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0]

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE7:0]: Preamble bits 0 to 7
0xD: Common ID value

114/3353 RM0433 Rev 8

RM0433 Memory and bus architecture

AXI interconnect - component ID1 register (AXI_COMP_ID_1)

Address offset: 0x1FF4
Reset value: 0x0000 00F0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8]

r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 CLASS[3:0]: Component class
0xF: Generic IP component class
Bits 3:0 PREAMBLE[11:8]: Preamble bits 8 to 11
0x0: Common ID value

AXI interconnect - component ID2 register (AXI_COMP_ID_2)

Address offset: 0x1FF8
Reset value: 0x0000 0005

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12]

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[19:12]: Preamble bits 12 to 19
0x05: Common ID value

RM0433 Rev 8 115/3353

128
Memory and bus architecture RM0433

AXI interconnect - component ID3 register (AXI_COMP_ID_3)

Address offset: 0x1FFC
Reset value: 0x0000 00B1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20]

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[27:20]: Preamble bits 20 to 27
0xB1: Common ID value

AXI interconnect - TARG x bus matrix issuing functionality register

(AXI_TARGx_FN_MOD_ISS_BM)
Address offset: 0x1008 + 0x1000 * x, where x = 1 to 7
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE READ
_ISS_ _ISS_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
OVERR OVERR
IDE IDE
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WRITE_ISS_OVERRIDE: Switch matrix write issuing override for target
0: Normal issuing capability
1: Set switch matrix write issuing capability to 1
Bit 0 READ_ISS_OVERRIDE: Switch matrix read issuing override for target
0: Normal issuing capability
1: Set switch matrix read issuing capability to 1

116/3353 RM0433 Rev 8

RM0433 Memory and bus architecture

AXI interconnect - TARG x bus matrix functionality 2 register

(AXI_TARGx_FN_MOD2)
Address offset: 0x1024 + 0x1000 * x, where x = 1, 2 and 7
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPAS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. S_MER
GE
rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 BYPASS_MERGE: Disable packing of beats to match the output data width. Unaligned
transactions are not realigned to the input data word boundary.
0: Normal operation
1: Disable packing

AXI interconnect - TARG x long burst functionality modification register

(AXI_TARGx_FN_MOD_LB)
Address offset: 0x102C + 0x1000 * x, where x = 1 and 2
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FN_MO
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
D_LB
rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 FN_MOD_LB: Controls burst breaking of long bursts
0: Long bursts can not be generated at the output of the ASIB
1: Long bursts can be generated at the output of the ASIB

RM0433 Rev 8 117/3353

128
Memory and bus architecture RM0433

AXI interconnect - TARG x issuing functionality modification register

(AXI_TARGx_FN_MOD)
Address offset: 0x1108 + 0x1000 * x, where x = 1, 2 and 7
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE READ
_ISS_ _ISS_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
OVERR OVERR
IDE IDE
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WRITE_ISS_OVERRIDE: Override AMIB write issuing capability
0: Normal issuing capability
1: Force issuing capability to 1
Bit 0 READ_ISS_OVERRIDE: Override AMIB read issuing capability
0: Normal issuing capability
1: Force issuing capability to 1

AXI interconnect - INI x functionality modification 2 register

(AXI_INIx_FN_MOD2)
Address offset: 0x41024 + 0x1000 * x, where x = 1 and 3
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPAS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. S_MER
GE
rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 BYPASS_MERGE: Disables alteration of transactions by the up-sizer unless required by the
protocol
0: Normal operation
1: Transactions pass through unaltered where allowed

118/3353 RM0433 Rev 8

RM0433 Memory and bus architecture

AXI interconnect - INI x AHB functionality modification register

(AXI_INIx_FN_MOD_AHB)
Address offset: 0x41028 + 0x1000 * x, where x = 1 and 3
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_IN RD_IN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. C_OVE C_OVE
RRIDE RRIDE
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WR_INC_OVERRIDE: Converts all AHB-Lite read transactions to a series of single beat AXI
transactions.
0: Override disabled
1: Override enabled
Bit 0 RD_INC_OVERRIDE: Converts all AHB-Lite write transactions to a series of single beat AXI
transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write
response.
0: Override disabled
1: Override enabled

AXI interconnect - INI x read QoS register (AXI_INIx_READ_QOS)

Address offset: 0x41100 + 0x1000 * x, where x = 1 to 76
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AR_QOS[3:0]

rw

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 AR_QOS[3:0]: Read channel QoS setting
0x0: Lowest priority
0xF: Highest priority

RM0433 Rev 8 119/3353

128
Memory and bus architecture RM0433

AXI interconnect - INI x write QoS register (AXI_INIx_WRITE_QOS)

Address offset: 0x41104 + 0x1000 * x, where x = 1 to 76
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AW_QOS[3:0]

rw

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 AW_QOS[3:0]: Write channel QoS setting
0x0: Lowest priority
0xF: Highest priority

AXI interconnect - INI x issuing functionality modification register

(AXI_INIx_FN_MOD)
Address offset: 0x41108 + 0x1000 * x, where x = 1 to 76
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE READ
_ISS_ _ISS_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
OVERR OVERR
IDE IDE
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WRITE_ISS_OVERRIDE: Override ASIB write issuing capability
0: Normal issuing capability
1: Force issuing capability to 1
Bit 0 READ_ISS_OVERRIDE: Override ASIB read issuing capability
0: Normal issuing capability
1: Force issuing capability to 1

120/3353 RM0433 Rev 8

 2.2.5

Offset

0x1FF4
0x1FF0
0x1FE8
0x1FE4
0x1FE0
0x1FD8
0x1FD4
0x1FD0

0x1FEC
0x1FDC
RM0433

ID_1
ID_0
ID_3
ID_2
ID_1
ID_0
ID_7
ID_6
ID_5
_ID_4

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

AXI_COMP_
AXI_COMP_
AXI_PERIPH

AXI_PERIPH_
AXI_PERIPH_
AXI_PERIPH_
AXI_PERIPH_
AXI_PERIPH_
AXI_PERIPH_
AXI_PERIPH_
Register name

Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
21
AXI interconnect register map

Res. Res. Res. Res. Res. Res. Res. Res. Res.

Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
18

RM0433 Rev 8
Res. Res. Res. Res. Res. Res. Res. Res. Res.
Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
9
Table 6. AXI interconnect register map and reset values

Res. Res. Res. Res. Res. Res. Res. Res. Res.

Res. Res. Res. Res. Res. Res. Res. Res. Res. 8
7
REVISION JEP106ID 4KCOUNT 6
CLASS[3:0] REV_AND[3:0]
[3:0] [3:0] [3:0] 5
4
JEDEC 3
Reserved
Reserved
Reserved

PREAMBLE CUST_MOD_NUM PARTNUM JEP106CON 2

JEP106ID
PARTNUM[7:0]

[11:8] [3:0] [11:8] [3:0]

PREAMBLE[7:0]
[6:4] 1

1 1 1 1 0 0 0 0
0 0 0 0 1 1 0 1
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 1
1 0 1 1 0 1 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0

0
Memory and bus architecture

121/3353
128
 0x3004
0x2108
0x2104
0x2028
0x2024
0x2020
0x2008
0x2004
Offset

0x1FF8

0x202C
0x1FFC

0x2030 -
0x2000 -

0x210C -
0x200C -

122/3353
ID_3
ID_2

ISS_BM

FN_MOD

Reserved
Reserved
Reserved
Reserved
Reserved

FN_MOD2
FN_MOD_

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
AXI_COMP_
AXI_COMP_

AXI_TARG1_
AXI_TARG1_
AXI_TARG1_
AXI_TARG1_

FN_MOD_LB
Register name

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
29
Memory and bus architecture

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
18

RM0433 Rev 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. 7
Table 6. AXI interconnect register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. Res. Res. 6

Res. Res. Res. Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. Res. Res. Res. Res. Res. 3
Res. Res. Res. Res. Res. Res. Res. Res. Res. 2
Res. WRITE_ISS_OVERRIDE Res. Res. Res. Res. Res. WRITE_ISS_OVERRIDE Res. 1
PREAMBLE[27:20]
PREAMBLE[19:12]

0 0
1 0 1 1 0 0 0 1
0 0 0 0 0 1 0 1

0
0
0 0

0
RM0433

Res. READ_ISS_OVERRIDE Res. FN_MOD_LB Res. BYPASS_MERGE Res. READ_ISS_OVERRIDE Res.

 0x5004
0x4008
0x4004
0x3108
0x3104
0x3028
0x3024
0x3020
0x3008
Offset

0x302C

0x3030 -

0x400C -
0x310C -
0x300C -
RM0433

ISS_BM
ISS_BM

FN_MOD

Reserved
Reserved
Reserved
Reserved
Reserved

FN_MOD_
FN_MOD2
FN_MOD_

Reset value
Reset value
Reset value
Reset value
Reset value

AXI_TARG3_
AXI_TARG2_
AXI_TARG2_
AXI_TARG2_
AXI_TARG2_

FN_MOD_LB
Register name

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
18

RM0433 Rev 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7
Table 6. AXI interconnect register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2
Res. WRITE_ISS_OVERRIDE Res. WRITE_ISS_OVERRIDE Res. Res. Res. Res. Res. WRITE_ISS_OVERRIDE 1

0 0
0 0
0
0
0 0

0
Memory and bus architecture

123/3353
Res. READ_ISS_OVERRIDE Res. READ_ISS_OVERRIDE Res. FN_MOD_LB Res. BYPASS_MERGE Res. READ_ISS_OVERRIDE

128
 0x8024
0x8020
0x8008
0x8004
0x7008
0x7004
0x6008
0x6004
0x5008
Offset

0x800C -
0x700C -
0x600C -
0x500C -

124/3353
ISS_BM
ISS_BM
ISS_BM
ISS_BM

Reserved
Reserved
Reserved
Reserved

FN_MOD2
FN_MOD_
FN_MOD_
FN_MOD_
FN_MOD_

Reset value
Reset value
Reset value
Reset value
Reset value

AXI_TARG7_
AXI_TARG7_
AXI_TARG6_
AXI_TARG5_
AXI_TARG4_
Register name

Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
29
Memory and bus architecture

Res. Res. Res. Res. Res. Res. Res. Res. Res.

Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
18

RM0433 Rev 8
Res. Res. Res. Res. Res. Res. Res. Res. Res.
Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. 9
Res. Res. Res. Res. Res. Res. Res. Res. Res. 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. 7
Table 6. AXI interconnect register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. Res. Res. 6

Res. Res. Res. Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. Res. Res. Res. Res. Res. 3
Res. Res. Res. Res. Res. Res. Res. Res. Res. 2
Res. Res. WRITE_ISS_OVERRIDE Res. WRITE_ISS_OVERRIDE Res. WRITE_ISS_OVERRIDE Res. WRITE_ISS_OVERRIDE 1

0
0 0
0 0
0 0
0 0

0
RM0433

BYPASS_MERGE Res. READ_ISS_OVERRIDE Res. READ_ISS_OVERRIDE Res. READ_ISS_OVERRIDE Res. READ_ISS_OVERRIDE

 0x8108
0x8104
Offset

0x810C-

0x42108
0x42104
0x42100
0x42028
0x42024
0x42020
0x8028 -

0x430FC
0x420FC

0x4210C-
0x4202C-
RM0433

FN_MOD
FN_MOD

Reserved
Reserved
Reserved
Reserved

AXI_INI1_
AXI_INI1_
AXI_INI1_
AXI_INI1_
FN_MOD2

MOD_AHB

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

READ_QOS
AXI_TARG7_

WRITE_QOS
AXI_INI1_FN_
Register name

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
18

RM0433 Rev 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7
Table 6. AXI interconnect register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. Res. Res. Res. Res. 3
Res. Res. Res. Res. Res. Res. Res. Res. 2

[3:0]
[3:0]
Res. WRITE_ISS_OVERRIDE Res. WR_INC_OVERRIDE Res. Res. WRITE_ISS_OVERRIDE Res. 1
AR_QOS

AW_QOS

0 0
0 0 0 0
0 0 0 0
0 0
0
0 0

RD_INC_OVERRIDE 0
Memory and bus architecture

125/3353
Res. READ_ISS_OVERRIDE Res. BYPASS_MERGE Res. READ_ISS_OVERRIDE Res.

128
 Offset

0x44104
0x44100
0x44028
0x44024
0x43108
0x43104
0x43100

0x4310C

0x440FC
0x4402C-
- 0x44020

126/3353
FN_MOD

Reserved
Reserved

AXI_INI3_
AXI_INI3_
AXI_INI3_
AXI_INI3_
AXI_INI2_
AXI_INI2_
AXI_INI2_

FN_MOD2

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

READ_QOS
READ_QOS

WRITE_QOS
WRITE_QOS

FN_MOD_AHB
Register name

Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
29
Memory and bus architecture

Res. Res. Res. Res. Res. Res. Res. Res. Res.

Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
18

RM0433 Rev 8
Res. Res. Res. Res. Res. Res. Res. Res. Res.
Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. 9
Res. Res. Res. Res. Res. Res. Res. Res. Res. 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. 7
Table 6. AXI interconnect register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. Res. Res. 6

Res. Res. Res. Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. Res. 3
Res. Res. Res. Res. Res. 2

[3:0]
[3:0]
[3:0]
[3:0]

Res. WR_INC_OVERRIDE Res. Res. WRITE_ISS_OVERRIDE 1

AR_QOS
AR_QOS

AW_QOS
AW_QOS

0 0 0 0
0 0 0 0
0 0
0
0 0
0 0 0 0
0 0 0 0

RD_INC_OVERRIDE 0
RM0433

Res. BYPASS_MERGE Res. READ_ISS_OVERRIDE

 Offset

0x47100
0x46108
0x46104
0x46100
0x45108
0x45104
0x45100
0x44108

0x470FC
0x460FC
0x450FC

0x4610C-
0x4510C-
0x4410C-
RM0433

FN_MOD
FN_MOD
FN_MOD

Reserved
Reserved
Reserved

AXI_INI6_
AXI_INI5_
AXI_INI5_
AXI_INI5_
AXI_INI4_
AXI_INI4_
AXI_INI4_
AXI_INI3_

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

READ_QOS
READ_QOS
READ_QOS

WRITE_QOS
WRITE_QOS
Register name

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
18

RM0433 Rev 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7
Table 6. AXI interconnect register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. Res. Res. 3
Res. Res. Res. Res. Res. Res. 2

[3:0]
[3:0]
[3:0]
[3:0]
[3:0]

Res. WRITE_ISS_OVERRIDE Res. WRITE_ISS_OVERRIDE Res. WRITE_ISS_OVERRIDE 1

AR_QOS
AR_QOS
AR_QOS

AW_QOS
AW_QOS

0 0 0 0
0 0
0 0 0 0
0 0 0 0
0 0
0 0 0 0
0 0 0 0
0 0

0
Memory and bus architecture

127/3353
Res. READ_ISS_OVERRIDE Res. READ_ISS_OVERRIDE Res. READ_ISS_OVERRIDE

128
 Offset

0x47108
0x47104

128/3353
FN_MOD
AXI_INI6_
AXI_INI6_

Reset value
Reset value
WRITE_QOS
Register name

Res. Res. 31
Res. Res. 30
29
Memory and bus architecture

Res. Res.
Res. Res. 28
Res. Res. 27
Res. Res. 26
Res. Res. 25
Res. Res. 24
Res. Res. 23
Res. Res. 22
Res. Res. 21
Res. Res. 20
Res. Res. 19
18

RM0433 Rev 8
Res. Res.
Res. Res. 17
Res. Res. 16
Res. Res. 15
Res. Res. 14
Res. Res. 13
Res. Res. 12
Res. Res. 11
Res. Res. 10
Res. Res. 9
Refer to Section 2.3 on page 129 for the register boundary addresses.

Res. Res. 8
Res. Res. 7
Table 6. AXI interconnect register map and reset values (continued)

Res. Res. 6
Res. Res. 5
Res. Res. 4
Res. 3
Res. 2
[3:0]

WRITE_ISS_OVERRIDE 1
AW_QOS

0 0
0 0 0 0

0
RM0433

READ_ISS_OVERRIDE
RM0433

2.3 Memory organization

2.3.1 Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

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 RM0433

2.3.2 Memory map and register boundary addresses

Table 7. Memory map and default device memory area attributes

Boundary Attribute Execute
Region Arm® Cortex®-M7 Type
address s never

0xD0000000 -
FMC SDRAM Bank2 (or Reserved in case of FMC remap)
0xDFFFFFFF

0xCC000000 -
FMC SDRAM Bank1 (or remap of FMC NOR/PSRAM/SRAM 4 Bank1)
0xCFFFFFFF
External Devices

0xC8000000 -
FMC SDRAM Bank1 (or remap of FMC NOR/PSRAM/SRAM 3 Bank1)
0xCBFFFFFF
Device - Yes
0xC4000000 -
FMC SDRAM Bank1 (or remap of FMC NOR/PSRAM/SRAM 2 Bank1)
0xC7FFFFFF

0xC0000000 -
FMC SDRAM Bank1 (or remap of FMC NOR/PSRAM/SRAM 1 Bank1)
0xC3FFFFFF
0xA0000000 -
Reserved
0xBFFFFFFF

0x90000000 - Write-
QUADSPI
0x9FFFFFFF through
0x80000000 - cache
FMC NAND Flash memory attribute
0x8FFFFFFF

0x70000000 -
External Memories

Reserved (or remap of FMC SDRAM Bank2)

0x7FFFFFFF

0x6C000000 -
FMC NOR/PSRAM/SRAM 4 Bank1 (or remap of FMC SDRAM Bank1) Normal Write- No
0x6FFFFFFF
back,
0x68000000 - write
FMC NOR/PSRAM/SRAM 3 Bank1 (or remap of FMC SDRAM Bank1)
0x6BFFFFFF allocate
cache
0x64000000 -
FMC NOR/PSRAM/SRAM 2 Bank1 (or remap of FMC SDRAM Bank1) attribute
0x67FFFFFF

0x60000000 -
FMC NOR/PSRAM/SRAM 1 Bank1 (or remap of FMC SDRAM Bank1)
0x63FFFFFF
Peripherals

0x40000000 -
Peripherals (refer to Table 8: Register boundary addresses) Device - Yes
0x5FFFFFFF

130/3353 RM0433 Rev 8

RM0433

Table 7. Memory map and default device memory area attributes

Boundary Attribute Execute
Region Arm® Cortex®-M7 Type
address s never

0x38801000 -
Reserved
0x3FFFFFFF

0x38800000 -
Backup SRAM
0x38800FFF

0x38010000 -
Reserved
0x387FFFFF
0x38000000 -
SRAM4
0x3800FFFF

0x30048000 -
Reserved
0x37FFFFFF
Write-
0x30040000 - back,
SRAM3
0x30047FFF write
RAM

Normal No
0x30020000 - allocate
SRAM2 cache
0x3003FFFF
attribute
0x30000000 -
SRAM1
0x3001FFFF

0x24080000 -
Reserved
0x2FFFFFFF
0x24000000 -
AXI SRAM
0x2407FFFF

0x20020000 -
Reserved
0x23FFFFFF

0x20000000 -
DTCM
0x2001FFFF

0x1FF20000 -
Reserved
0x1FFFFFFF

Bank 1:
0x1FF00000 -
0x1FF1FFFF
System memory
Bank 2:
0x1FF40000 -
0x1FF5FFFF
Write-
0x08200000 -
Reserved through
Code

0x1FEFFFFF Normal No
cache
0x08100000 - attribute
Flash memory bank 2(1)
0x081FFFFF

0x08000000 -
Flash memory bank 1(2)
0x080FFFFF

0x00010000 -
Reserved
0x07FFFFFF

0x00000000 -
ITCM
0x0000FFFF

1. Flash memory bank 2 boundary is limited to 0x08100000 - 0x0817FFFF on STM32H742xG/STM32H743xG. It is reserved on

STM32H750xB.
2. Flash memory bank 1 boundary is limited to 0x08000000 - 0x0807FFFF and 0x08000000 - 0x0801FFFFon
STM32H742xG/STM32H743xG and STM32H750xB boundary, respectively.

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 RM0433

All the memory map areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”. For the detailed mapping of available memory and register areas,
refer to the following table.
The following table gives the boundary addresses of the peripherals available in the
devices.

Table 8. Register boundary addresses(1)

Boundary address Peripheral Bus Register map

0x58027000 - 0x580273FF RAMECC3 Section 3.4: RAMECC registers

0x58026400 - 0x580267FF HSEM Section 10.4: HSEM registers
0x58026000 - 0x580263FF ADC3 Section 25.7: ADC common registers
0x58025800 - 0x58025BFF DMAMUX2 Section 17.6: DMAMUX registers
0x58025400 - 0x580257FF BDMA Section 16.6: BDMA registers
0x58024C00 - 0x58024FFF CRC Section 21.4: CRC registers
0x58024800 - 0x58024BFF PWR Section 6.8: PWR register description
0x58024400 - 0x580247FF RCC Section 8.7: RCC register description
0x58022800 - 0x58022BFF GPIOK Section 11.4: GPIO registers
0x58022400 - 0x580227FF GPIOJ AHB4 Section 11.4: GPIO registers
0x58022000 - 0x580223FF GPIOI (D3) Section 11.4: GPIO registers
0x58021C00 - 0x58021FFF GPIOH Section 11.4: GPIO registers
0x58021800 - 0x58021BFF GPIOG Section 11.4: GPIO registers
0x58021400 - 0x580217FF GPIOF Section 11.4: GPIO registers
0x58021000 - 0x580213FF GPIOE Section 11.4: GPIO registers
0x58020C00 - 0x58020FFF GPIOD Section 11.4: GPIO registers
0x58020800 - 0x58020BFF GPIOC Section 11.4: GPIO registers
0x58020400 - 0x580207FF GPIOB Section 11.4: GPIO registers
0x58020000 - 0x580203FF GPIOA Section 11.4: GPIO registers

132/3353 RM0433 Rev 8

RM0433

Table 8. Register boundary addresses(1) (continued)

Boundary address Peripheral Bus Register map

0x58005800 - 0x58006BFF Reserved Reserved

0x58005400 - 0x580057FF SAI4 Section 51.6: SAI registers
0x58004C00 - 0x58004FFF Reserved Reserved
0x58004800 - 0x58004BFF IWDG1 Section 45.4: IWDG registers
0x58004000 - 0x580043FF RTC & BKP registers Section 46.6: RTC registers
0x58003C00 - 0x58003FFF VREF Section 27.3: VREFBUF registers
0x58003800 - 0x58003BFF COMP1 - COMP2 Section 28.7: COMP registers
0x58003000 - 0x580033FF LPTIM5 APB4 Section 43.7: LPTIM registers
0x58002C00 - 0x58002FFF LPTIM4 (D3) Section 43.7: LPTIM registers
0x58002800 - 0x58002BFF LPTIM3 Section 43.7: LPTIM registers
0x58002400 - 0x580027FF LPTIM2 Section 43.7: LPTIM registers
0x58001C00 - 0x58001FFF I2C4 Section 47.7: I2C registers
0x58001400 - 0x580017FF SPI6 Section 50.11: SPI/I2S registers
0x58000C00 - 0x58000FFF LPUART1 Section 49.7: LPUART registers
0x58000400 - 0x580007FF SYSCFG Section 12.3: SYSCFG registers
0x58000000 - 0x580003FF EXTI Section 20.6: EXTI registers
0x52009000 - 0x520093FF RAMECC1 Section 3.4: RAMECC registers
Delay Block
0x52008000 - 0x52008FFF Section 24.4: DLYB registers
SDMMC1
0x52007000 - 0x52007FFF SDMMC1 Section 55.10: SDMMC registers
Delay Block
0x52006000 - 0x52006FFF Section 24.4: DLYB registers
QUADSPI
QUADSPI control reg-
0x52005000 - 0x52005FFF Section 23.5: QUADSPI registers
isters

AHB3 Section 22.7.6: NOR/PSRAM controller registers,

0x52004000 - 0x52004FFF FMC control registers (D1) Section 22.8.7: NAND flash controller registers,
Section 22.9.5: SDRAM controller registers
0x52003000 - 0x52003FFF JPEG Section 33.5: JPEG codec registers
Flash interface regis-
0x52002000 - 0x52002FFF Section 4.9: FLASH registers
ters
0x52001000 - 0x52001FFF Chrom-Art (DMA2D) Section 18.5: DMA2D registers
0x52000000 - 0x52000FFF MDMA Section 14.5: MDMA registers
0x51000000 - 0x510FFFFF GPV Section 2.2: AXI interconnect matrix (AXIM)
0x50003000 - 0x50003FFF WWDG1 Section 44.5: WWDG registers
APB3
0x50001000 - 0x50001FFF LTDC Section 32.7: LTDC registers
(D1)
0x50000000 - 0x50000FFF Reserved -
0x48023000 - 0x480233FF RAMECC2 Section 3.4: RAMECC registers

RM0433 Rev 8 133/3353

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 RM0433

Table 8. Register boundary addresses(1) (continued)

Boundary address Peripheral Bus Register map

Delay Block
0x48022800 - 0x48022BFF Section 24.4: DLYB registers
SDMMC2
0x48022400 - 0x480227FF SDMMC2 Section 55.10: SDMMC registers
AHB2
0x48021800 - 0x48021BFF RNG Section 34.7: RNG registers
(D2)
0x48021400 - 0x480217FF HASH Section 36.7: HASH registers
0x48021000 - 0x480213FF CRYPTO Section 35.7: CRYP registers
0x48020000 - 0x480203FF DCMI Section 31.5: DCMI registers
0x40080000 - 0x400BFFFF USB2 OTG_FS Section 57.14: OTG_HS registers
0x40040000 - 0x4007FFFF USB1 OTG_HS Section 57.14: OTG_HS registers
0x40028000 - 0x400293FF ETHERNET MAC Section 58.11: Ethernet registers
0x40024400 - 0x400247FF Reserved AHB1 Reserved
0x40022000 - 0x400223FF ADC1 - ADC2 (D2) Section 25.7: ADC common registers
0x40020800 - 0x40020BFF DMAMUX1 Section 17.6: DMAMUX registers
0x40020400 - 0x400207FF DMA2 Section 15.5: DMA registers
0x40020000 - 0x400203FF DMA1 Section 15.5: DMA registers
0x40017400 - 0x400177FF HRTIM Section 37.5: HRTIM registers
Section 30.7: DFSDM channel y registers (y=0..7),
0x40017000 - 0x400173FF DFSDM1 Section 30.8: DFSDM filter x module registers
(x=0..3)
0x40016000 - 0x400163FF SAI3 Section 51.6: SAI registers
0x40015C00 - 0x40015FFF SAI2 Section 51.6: SAI registers
0x40015800 - 0x40015BFF SAI1 Section 51.6: SAI registers
0x40015000 - 0x400153FF SPI5 Section 50.11: SPI/I2S registers
0x40014800 - 0x40014BFF TIM17 APB2 Section 41.6: TIM16/TIM17 registers
0x40014400 - 0x400147FF TIM16 (D2) Section 41.6: TIM16/TIM17 registers
0x40014000 - 0x400143FF TIM15 Section 41.5: TIM15 registers
0x40013400 - 0x400137FF SPI4 Section 50.11: SPI/I2S registers
0x40013000 - 0x400133FF SPI1 / I2S1 Section 50.11: SPI/I2S registers
0x40011400 - 0x400117FF USART6 Section 48.8: USART registers
0x40011000 - 0x400113FF USART1 Section 48.8: USART registers
0x40010400 - 0x400107FF TIM8 Section 38.4: TIM1/TIM8 registers
0x40010000 - 0x400103FF TIM1 Section 38.4: TIM1/TIM8 registers

134/3353 RM0433 Rev 8

RM0433

Table 8. Register boundary addresses(1) (continued)

Boundary address Peripheral Bus Register map

0x4000AC00 - 0x4000D3FF CAN Message RAM Section 56.5: FDCAN registers

0x4000A800 - 0x4000ABFF CAN CCU Section 56.5: FDCAN registers
0x4000A400 - 0x4000A7FF FDCAN2 Section 56.5: FDCAN registers
0x4000A000 - 0x4000A3FF FDCAN1 Section 56.5: FDCAN registers
0x40009400 - 0x400097FF MDIOS Section 54.4: MDIOS registers
0x40009000 - 0x400093FF OPAMP Section 29.6: OPAMP registers
0x40008800 - 0x40008BFF SWPMI Section 53.6: SWPMI registers
0x40008400 - 0x400087FF CRS Section 9.8: CRS registers
0x40007C00 - 0x40007FFF UART8 Section 48.8: USART registers
0x40007800 - 0x40007BFF UART7 Section 48.8: USART registers
0x40007400 - 0x400077FF DAC1 Section 26.7: DAC registers
0x40006C00 - 0x40006FFF HDMI-CEC Section 59.7: HDMI-CEC registers
0x40005C00 - 0x40005FFF I2C3 Section 47.7: I2C registers
0x40005800 - 0x40005BFF I2C2 Section 47.7: I2C registers
0x40005400 - 0x400057FF I2C1 Section 47.7: I2C registers
0x40005000 - 0x400053FF UART5 Section 48.8: USART registers
APB1
0x40004C00 - 0x40004FFF UART4 Section 48.8: USART registers
(D2)
0x40004800 - 0x40004BFF USART3 Section 48.8: USART registers
0x40004400 - 0x400047FF USART2 Section 48.8: USART registers
0x40004000 - 0x400043FF SPDIFRX1 Section 52.5: SPDIFRX interface registers
0x40003C00 - 0x40003FFF SPI3 / I2S3 Section 50.11: SPI/I2S registers
0x40003800 - 0x40003BFF SPI2 / I2S2 Section 50.11: SPI/I2S registers
0x40002C00 - 0x40002FFF Reserved Reserved
0x40002400 - 0x400027FF LPTIM1 Section 43.7: LPTIM registers
0x40002000 - 0x400023FF TIM14 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers
0x40001C00 - 0x40001FFF TIM13 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers
0x40001800 - 0x40001BFF TIM12 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers
0x40001400 - 0x400017FF TIM7 Section 42.4: TIM6/TIM7 registers
0x40001000 - 0x400013FF TIM6 Section 42.4: TIM6/TIM7 registers
0x40000C00 - 0x40000FFF TIM5 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers
0x40000800 - 0x40000BFF TIM4 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers
0x40000400 - 0x400007FF TIM3 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers
0x40000000 - 0x400003FF TIM2 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers
1. Accessing a reserved area results in a bus error. Accessing undefined memory space in a peripheral returns zeros.

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 RM0433

2.4 Embedded SRAM

The STM32H742xx, STM32H743/53xx and STM32H750xB devices feature:
• Up to 864 Kbytes of System SRAM
• 128 Kbytes of data TCM RAM
• 64 Kbytes of instruction TCM RAM
• 4 Kbytes of backup SRAM
The embedded system SRAM is divided into up to five blocks over the three power
domains:
• D1 domain, AXI SRAM:
– AXI SRAM is mapped at address 0x2400 0000 and accessible by all system
masters except BDMA through D1 domain AXI bus matrix. AXI SRAM can be
used for application data which are not allocated in DTCM RAM or reserved for
graphic objects (such as frame buffers)
• D2 domain, AHB SRAM:
– AHB SRAM1 is mapped at address 0x3000 0000 and accessible by all system
masters except BDMA through D2 domain AHB matrix. AHB SRAM1 can be used
as DMA buffers to store peripheral input/output data in D2 domain.
– AHB SRAM2 is mapped at address 0x3002 0000 and accessible by all system
masters except BDMA through D2 domain AHB matrix. AHB SRAM2 can be used
as DMA buffers to store peripheral input/output data in D2 domain.
– AHB SRAM3 is mapped at address 0x3004 0000 and accessible by all system
masters except BDMA through D2 domain AHB matrix. AHB SRAM3 can be used
as buffers to store peripheral input/output data for Ethernet and USB.
• D3 domain, AHB SRAM:
– AHB SRAM4 is mapped at address 0x3800 0000 and accessible by most of
system masters through D3 domain AHB matrix. AHB SRAM4 can be used as
BDMA buffers to store peripheral input/output data in D3 domain. It can also be
used to retain some application data when D1 and D2 domain enter DStandby
mode.
The system AHB SRAM can be accessed as bytes, half-words (16-bit units) or words (32-bit
units), while the system AXI SRAM can be accessed as bytes, half-words, words or double-
words (64-bit units). These memories can be addressed at maximum system clock
frequency without wait state.
The AHB masters can read/write-access an SRAM section concurrently with the Ethernet
MAC or the USB OTG HS peripheral accessing another SRAM section. For example, the
Ethernet MAC accesses the SRAM2 while the CPU accesses the SRAM1, concurrently.
The TCM SRAMs are dedicated to the Cortex®-M7:
• DTCM-RAM on TCM interface is mapped at the address 0x2000 0000 and accessible
by Cortex®-M7, and by MDMA through AHBS slave bus of the Cortex®-M7 CPU. The
DTCM-RAM can be used as read-write segment to host critical real-time data (such as
stack and heap) for application running on Cortex®-M7 CPU.
• ITCM-RAM on TCM interface mapped at the address 0x0000 0000 and accessible by
Cortex®-M7 and by MDMA through AHBS slave bus of the Cortex®-M7 CPU. The
ITCM-RAM can be used to host code for time-critical routines (such as interrupt
handlers) that requires deterministic execution.

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The backup RAM is mapped at the address 0x3880 0000 and is accessible by most of the
system masters through D3 domain’s AHB matrix. With a battery connected to the VBAT pin,
the backup SRAM can be used to retain data during low-power mode (Standby and VBAT
mode).

Error code correction (ECC)

SRAM data are protected by ECC:
• 7 ECC bits are added per 32-bit word.
• 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
When an incomplete word is written to an internal SRAM and a reset occurs, the last
incomplete word is not really written. This is due to the ECC behavior. To ensure that an
incomplete word is written to SRAM, write an additional dummy incomplete word to the
same RAM at a different address before issuing a reset.

2.5 Flash memory overview

The Flash memory interface manages CPU AXI accesses to the Flash memory. It
implements the erase and program Flash memory operations and the read and write
protection mechanisms.
The Flash memory is organized as follows:
• Two main memory block divided into sectors.
• An information block:
– System memory from which the device boots in System memory boot mode
– Option bytes to configure read and write protection, BOR level, watchdog
software/hardware and reset when the device is in Standby or Stop mode.
Refer to Section 4: Embedded flash memory (FLASH) for more details.

2.6 Boot configuration

In the STM32H742, STM32H743/753 and STM32H750, two different boot areas can be
selected through the BOOT pin and the boot base address programmed in the
BOOT_ADD0 and BOOT_ADD1 option bytes as shown in the Table 9.

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Table 9. Boot modes

Boot mode selection
Boot area
Boot address option
BOOT
bytes

Boot address defined by user option byte BOOT_ADD0[15:0]

0 BOOT_ADD0[15:0] ST programmed value:
Flash memory at 0x0800 0000
Boot address defined by user option byte BOOT_ADD1[15:0]
1 BOOT_ADD1[15:0] ST programmed value:
System memory in bank 1 at 0x1FF0 0000

The values on the BOOT pin are latched on the 4th rising edge of SYSCLK after reset
release. It is up to the user to set the BOOT pin after reset.
The BOOT pin is also re-sampled when the device exits the Standby mode. Consequently,
they must be kept in the required Boot mode configuration when the device is in the Standby
mode.
After startup delay, the selection of the boot area is done before releasing the processor
reset.
The BOOT_ADD0 and BOOT_ADD1 address option bytes allows to program any boot
memory address from 0x0000 0000 to 0x3FFF 0000 which includes:
• All Flash address space
• All RAM address space: ITCM, DTCM RAMs and SRAMs
• The TCM-RAM
The BOOT_ADD0 / BOOT_ADD1 option bytes can be modified after reset in order to boot
from any other boot address after next reset.
If the programmed boot memory address is out of the memory mapped area or a reserved
area, the default boot fetch address is programmed as follows:
• Boot address 0: FLASH at 0x0800 0000
• Boot address 1: ITCM-RAM at 0x0000 0000
When the Flash level 2 protection is enabled, only boot from Flash memory is available. If
the boot address already programmed in the BOOT_ADD0 / BOOT_ADD1 option bytes is
out of the memory range or belongs to the RAM address range, the default fetch will be
forced from Flash memory at address 0x0800 0000 .

Embedded bootloader
The embedded bootloader code is located in system memory. It is programmed by ST
during production. It is used to reprogram the Flash memory using one of the following serial
interfaces:
• USART1 on PA9/PA10 and PB14/PB15 pins, USART2 on PA3/PA2 pins, and USART3
on PB10/PB11 pins.
• I2C1 on PB6/PB9 pins, I2C2 on PF0/PF1 pins, and I2C3 on PA8/PC9 pins.
• USB OTG FS in Device mode (DFU) on PA11/PA12 pins
• SPI1 on PA4/PA5/PA6/PA7 pins, SPI2 on PI0/PI1/PI2/PI3 pins, SPI3 on
PC10/PC11/PC12/PA15 pins, and SPI4 on PE11/PE12/PE13/PE14 pins.

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For additional information, refer to the application note AN2606.

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3 RAM ECC monitoring (RAMECC)

3.1 Introduction
The STM32H742, STM32H743/753 and STM32H750 devices feature a RAM ECC
monitoring unit (RAMECC). It provides a mean for application software to verify ECC status
and execute service routines when an error occurs.
Note: For further information on STM32 RAMECC usage, refer to application note AN5342 “Error
correction code (ECC) management for internal memories protection on STM32H7 Series”
available from www.st.com.

3.2 RAMECC main features

SRAM data are protected by ECC. The ECC mechanism is based on the SECDED
algorithm. It supports single- and double-error detection, as well as single-error correction:
• 7 ECC bits are added per 32-bit word.
• 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
RAM data word integrity is checked at each memory read access, or partial RAM word write
operation. Two cycles are required to perform a partial RAM word write (read-modify-write).
The RAMECC monitoring unit includes the following features:
• RAM ECC monitoring per domain
• RAM failing address/data identification

3.3 RAMECC functional description

3.3.1 RAMECC block diagram

An ECC controller is associated to each RAM area. It performs the following functions:
• ECC encoding: ECC code computation and storage.
• ECC decoding: RAM data word loading and ECC code decoding to detect errors
• Error detection: single- and double-error detection
• Error correction: single-error correction.
Note: All the RAM ECC controllers are always enabled.
Figure 3 describes the implementation of RAM ECC controllers.

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Figure 3. RAM ECC controller implementation schematic

Bus protocol(1)

ECC wrapper
RAM
RAM area
protocol
ecc_diag_evt

RAM ECC controller

(1) Bus protocols: TCM, AXI, AHB

MSv46166V1

A dedicated RAM ECC monitoring area is defined for each domain (see Section 3.3.3:
RAMECC monitor mapping. The RAMECC allows the collection of ECC diagnostic events
from each RAM ECC controller and provides a mean for the CPU to verify the ECC status.
Figure 4 shows the connection schematic between the RAM ECC controller and the
RAMECC monitoring unit.

Figure 4. Connection between RAM ECC controller and RAMECC monitoring unit
32-bit AHB
bus

RAMECC registers
ramecc_hclk

RAM1 ECC ecc_diag_evt1

controller

x RAM areas Event ECC error

Masking ramecc_it
monitoring events

RAMx ECC ecc_diag_evtx

controller

RAMECC monitoring unit

MSv46167V1

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3.3.2 RAMECC internal signals

Table 10 gives the list of the internal signals that control the RAMECC unit.

Table 10. RAMECC internal input/output signals

Internal signal name Signal type Description

ramecc_hclk Input AHB clock

ECC diagnostic event generated by RAMx ECC
ecc_diag_evtx Input
controller x
Interrupt generated by the RAMECC monitoring unit
ramecc_it Output
when an ECC error is detected.

3.3.3 RAMECC monitor mapping

STM32H742, STM32H743/753 and STM32H750 devices features three RAMECC
monitoring units (one per domain). The inputs from the ECC controllers are mapped as
described in Table 11. The RAM ECC event monitoring status and configuration registers
are described in Section 3.4: RAMECC registers.

Table 11. ECC controller mapping

Monitor SRAM ECC event monitoring status and Size in Address
RAMECC units
number configuration registers Kbytes Offset

1 AXI SRAM ECC monitoring unit 512 0x20

2 ITCM-RAM ECC monitoring unit 64 0x40
D1 domain
3 DTCM-RAM ECC D0TCM 64 0x60
RAMECC unit
4 monitoring unit D1TCM 64 0x80
5 ETM RAM ECC monitoring unit 4 0xA0
1 SRAM1 ECC monitoring SRAM1_0 64 0x20
2 unit SRAM1_1 64 0x40
D2 domain
3 SRAM2 ECC monitoring SRAM2_0 64 0x60
RAMECC unit
4 unit SRAM2_1 64 0x80
5 SRAM3 ECC monitoring unit 32 0xA0

D3 domain 1 SRAM4 ECC monitoring unit 64 0x20

RAMECC unit 2 Backup RAM ECC monitoring unit 4 0x40

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3.4 RAMECC registers

RAMECC registers can be accessed only in 32-bit (word) mode. Byte and half-word formats
are not allowed.

3.4.1 RAMECC interrupt enable register (RAMECC_IER)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GECCDEBWIE

GECCDEIE

GECCSEIE

GIE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 GECCDEBWIE: Global ECC double error on byte write (BW) interrupt enable
When GECCDEBWIE bit is set to 1, an interrupt is generated when an ECC double detection
error occurs during a byte write operation to RAM (incomplete word write).
0: no interrupt generated when an ECC double detection error occurs on byte write
1: interrupt generated if an ECC double detection error occurs on byte write
Bit 2 GECCDEIE: Global ECC double error interrupt enable
When GECCDEIE bit is set to 1, an interrupt is generated when an ECC double detection
error occurs during a read operation from RAM.
0: no interrupt generated when an ECC double detection error occurs
1: interrupt generated if an ECC double detection error occurs
Bit 1 GECCSEIE: Global ECC single error interrupt enable
When GECCSEIE bit is set to 1, an interrupt is generated when an ECC single error occurs
during a read operation from RAM.
0: no interrupt generated when an ECC single error occurs
1: interrupt generated when an ECC single error occurs
Bit 0 GIE: Global interrupt enable
When GIE bit is set to 1, an interrupt is generated when an enabled global ECC error
(GECCDEBWIE, GECCDEIE or GECCSEIE) occurs.
0: no interrupt generated when an ECC error occurs
1: interrupt generated when an ECC error occurs

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3.4.2 RAMECC monitor x configuration register (RAMECC_MxCR)

Address offset: 0x20 * x
Reset value: 0x0000 0000
x is the ECC monitoring unit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCEL ECCDE ECCDE ECCSE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN BWIE IE IE
rw rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ECCELEN: ECC error latching enable
When ECCELEN bit is set to 1, if an ECC error occurs (both for single error correction or
double detection) during a read operation, the context (address, data and ECC code) that
generated the error are latched to their respective registers.
0: no error context preserved when an ECC error occurs
1: error context preserved when an ECC error occurs
Bit 4 ECCDEBWIE: ECC double error on byte write (BW) interrupt enable
When ECCDEBWIE bit is set to 1, monitor x generates an interrupt when an ECC double
detection error occurs during a byte write operation to RAM.
0: no interrupt generated when an ECC double detection error occurs on byte write
1: interrupt generated if an ECC double detection error occurs on byte write
Bit 3 ECCDEIE: ECC double error interrupt enable
When ECCDEIE bit is set to 1, monitor x generates an interrupt when an ECC double
detection error occurs during a read operation from RAM.
0: no interrupt generated when an ECC double detection error occurs
1: interrupt generated if an ECC double detection error occurs
Bit 2 ECCSEIE: ECC single error interrupt enable
When ECCSEIE bit is set to 1, monitor x generates an interrupt when an ECC single error
occurs during a read operation from RAM.
0: no interrupt generated when an ECC single error occurs
1: interrupt generated when an ECC single error occurs
Bits 1:0 Reserved, must be kept at reset value.

3.4.3 RAMECC monitor x status register (RAMECC_MxSR)

Address offset: 0x24 + 0x20 * (x - 1), (x= ECC monitoring unit number)
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBW
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DEDF SEDCF
DF
rc_w0 rc_w0 rc_w0

Bits 31: 3 Reserved, must be kept at reset value.

Bit 2 DEBWDF: ECC double error on byte write (BW) detected flag
This bit is set by hardware. It is cleared by software by writing a 0
0: no error detected
1: error detected
Bit 1 DEDF: ECC double error detected flag
This bit is set by hardware. It is cleared by software by writing a 0
0: no error detected
1: error detected
Bit 0 SEDCF: ECC single error detected and corrected flag
This bit is set by hardware. It is cleared by software by writing a 0
0: no error detected and corrected
1: error detected and corrected

3.4.4 RAMECC monitor x failing address register (RAMECC_MxFAR)

Address offset: 0x28 + 0x20 * (x-1), (x= ECC monitoring unit number)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FADD[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FADD[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 FADD[31:0]: ECC error failing address

When an ECC error occurs the FADD bitfield contains the address that generated the ECC
error.

3.4.5 RAMECC monitor x failing data low register (RAMECC_MxFDRL)

Address offset: 0x2C + 0x20 * (x-1), (x= ECC monitoring unit number)
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAL[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAL[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 FDATAL[31:0]: Failing data low

When an ECC error occurs the FDATAL bitfield contains the LSB part of the data that
generated the error. For 32-bit word SRAM, this bitfield contains the full memory word that
generated the error.

3.4.6 RAMECC monitor x failing data high register (RAMECC_MxFDRH)

Address offset: 0x30 + 0x20 * (x-1), (x= ECC monitoring unit number)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAH[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAH[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 FDATAH[31:0]: Failing data high (64-bit memory)

When an ECC error occurs the FDATAH bitfield contains the MSB part of the data that
generated the error.

Note: This register is reserved in case of 32-bit word SRAM.

3.4.7 RAMECC monitor x failing ECC error code register

RAMECC_MxFECR)
Address offset: 0x34 + 0x20 * (x-1), (x= ECC monitoring unit number)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEC[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 FEC [31:0]: Failing error code

When an ECC error occurs the FEC bitfield contains the ECC failing code that generated the
error.

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3.4.8 RAMECC register map

Table 12. RAMECC register map and reset values

Register Register size
Offset name
reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
value

GECCDEBWIE
GECCDEIE
GECCSEIE
RAMECC_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

GIE
IER
0x00

Reset value 0 0 0 0

ECCDEBWIE
ECCELEN

ECCDEIE
ECCSEIE
RAMECC_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
0x20 * x
MxCR
(x = monitoring
unit number)

Reset value 0 0 0 0

DEBWDF

SEDCF
DEDF
RAMECC_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x24+0x20 *(x -1)
MxSR
(x = monitoring
unit number)
Reset value 0 0 0

0x28+0x20 * (x -1) RAMECC_

FADD[31:0]
MxFAR
(x = monitoring
unit number) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x2C+0x20 * (x -1) RAMECC_

FDATAL[31:0]
MxFDRL
(x = monitoring
unit number) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x30+0x20 * (x -1) RAMECC_

FDATAH[31:0]
MxFDRH
(x = monitoring
unit number) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x34+0x20 * (x -1) RAMECC_

FEC[31:0]
MxFECR
(x = monitoring
unit number) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 129 for the register boundary addresses.

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4 Embedded flash memory (FLASH)

4.1 Introduction
The embedded flash memory (FLASH) manages the accesses of any master to the
embedded non-volatile memory, that is 2 Mbytes. It implements the read, program and
erase operations, error corrections as well as various integrity and confidentiality protection
mechanisms.
The embedded flash memory manages the automatic loading of non-volatile user option
bytes at power-on reset, and implements the dynamic update of these options.

4.2 FLASH main features

• 2 Mbytes of non-volatile memory divided into two banks of 1 Mbyte each
• flash memory read operations supporting multiple length (64 bits, 32bits, 16bits or one
byte)
• Flash memory programming by 256 bits
• 128-Kbyte sector erase, bank erase and dual-bank mass erase
• Dual-bank organization supporting:
– simultaneous operations: two read/program/erase operations executed in parallel
on both banks (only available on STM32H742/743/753)
– Bank swapping: the address mapping of the user flash memory of each bank can
be swapped, along with the corresponding registers.
• Error Code Correction (ECC): one error detection/correction or two error detections per
256-bit flash word using 10 ECC bits
• Cyclic redundancy check (CRC) hardware module
• User configurable non-volatile option bytes
• Flash memory enhanced protections, activated by option bytes
– Read protection (RDP), preventing unauthorized flash memory dump to safeguard
sensitive application code
– Write-protection of sectors (WRPS), available per bank (128 Kbyte sectors)
– Two proprietary code readout protection (PCROP) areas (one per user flash
bank). When enabled, this area is execute-only.
– Two secure-only areas (one per user flash bank). When enabled this area is
accessible only if the STM32 microcontroller operates in Secure access mode.
• Read and write command queues to streamline flash operations

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4.3 FLASH functional description

4.3.1 FLASH block diagram

Figure 5 shows the embedded flash memory block diagram.

Figure 5. FLASH block diagram

sys_ck

d1_rst
32-bit AHB bus

AHB Interface
Register
Configuration banks
port

flash_it IRQ Logic

64-bit AXI bus

AXI Interface 1 256

256
System bus Non-volatile
ECC, redundancy Memory Bank1
Flash
Interface Control, Status
po_rst Logic

ECC, redundancy
64-bit AXI bus

Control, Status
AXI Interface 2 256 Non-volatile
Memory Bank2
System bus 256

FLASH

MSv41902V3

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4.3.2 FLASH internal signals

Table 13 describes a list of the useful to know internal signals available at embedded flash
memory level. These signals are not available on the microcontroller pads.

Table 13. FLASH internal input/output signals

Internal signal name Signal type Description

D1 domain bus clock (embedded flash memory AXI

sys_ck Input
interface clock)
po_rst Input Power on reset
d1_rst Input D1 domain system reset
flash_it Output Embedded flash memory interface interrupt request

4.3.3 FLASH architecture and integration in the system

The embedded flash memory is a central resource for the whole microcontroller. It serves as
an interface to two non-volatile memory banks, and organizes the memory in a very specific
way. The embedded flash memory also proposes a set of security features to protect the
assets stored in the non-volatile memory at boot time, at run-time and during firmware and
configuration upgrades.
The embedded flash memory offers two 64-bit AXI slave ports for code and data accesses,
plus a 32-bit AHB configuration slave port used for register bank accesses.
Note: The application can simultaneously request a read and a write operation through each AXI
interface.
The embedded flash memory microarchitecture is shown in Figure 6.

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Figure 6. Detailed FLASH architecture

32-bit AHB bus

AHB interface Bank

Flash interface logic
registers

CRC module
ready

memory interface 1
flash_it IRQ logic Erase queue1
Command

Non-volatile
Read command Read queue1 Flash
256-bit
(x3) Bank1
AXI interface 1
64-bit AXI bus

Write command ECC

Write queue1
buffer
Write
data

Write data
(x2)
Write response
Erase queue2
Read data
System ready
Read queue2

memory interface 2
buses
Read command (x3) Command

Non-volatile
64-bit AXI bus

AXI Interface 2

Write command Write queue2 Flash

256-bit Bank2
(x2)
buffer
Write
data

Write data ECC

Write response
Read data

FLASH

MSv48853V1

Behind the system interfaces, the embedded flash memory implements various command
queues and buffers to perform flash read, write and erase operations with maximum
efficiency.
Thanks to the addition of a read and write data buffer, the AXI slave port handles the
following access types:
• Multiple length: 64 bits, 32 bits, 16 bits and 8 bits
• Single or burst accesses
• Write wrap burst must not cross 32-byte aligned address boundaries to target exactly
one flash word
The AHB configuration slave port supports 8-bit, 16-bit and 32-bit word accesses.
The embedded flash memory is built in such a way that only one read or write operation can
be executed at a time on a given bank.

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4.3.4 Flash memory architecture and usage

Flash memory architecture
Figure 7 shows the non-volatile memory organization supported by the embedded flash
memory.

Figure 7. Embedded flash memory organization

Secure- Bank2
only Sector 0
Write- Sector 1
protected Sector 2
System memory (per bank)
PCROP- Flash Sector 3
# Size: 128 Kbytes
protected interface Sector 4
# 10-bit ECC per 256-bit Flash word
logic Sector 5
Sector 6
Sector 7 System memory 2

AXI system
bus
Bank1
Sector 0 System memory 1 Option Bytes
Sector 1
Write locked
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7

AHB config.port
User main memory (per bank)
# 8 sectors of 128 Kbytes each
# 10-bit ECC per 256-bit Flash word
MSv46171V2

Note: On STM32H750xB, bank 2 is not available and bank 1 contains only one 128 Kbyte sector.
The embedded flash non-volatile memory is composed of:
• For STM32H742/743/753 devices: a 2-Mbyte main memory block, organized as two
banks of 1 Mbyte each. Each bank is in turn divided in eight 128-Kbyte sectors and
features Flash-word rows of 256 bits + 10 bits of ECC per word.
• For STM32H750xB devices: a 128-Kbyte user Flash memory block containing one
user sector of 128 Kbytes (4 K Flash words).
• A system memory block of 256 Kbytes, divided into two 128 Kbyte banks. The system
memory is ECC protected.
• A set of non-volatile option bytes loaded at reset by the embedded flash memory and
accessible by the application software only through the AHB configuration register
interface.

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The overall flash memory architecture is summarized in Table 14, Table 15 and Table 16.

Table 14. Flash memory organization on STM32H750xB devices

Size Access SNB1/2
Flash memory area Address range Region name (1)
(bytes) interface

User main 0x0800 0000-

Bank 1 128 K Sector 0 AXI ports 0x0
memory 0x0801 FFFF
0x1FF0 0000- System flash
Bank 1 128 K N/A(2)
System 0x1FF1 FFFF (read-only)
AXI ports
memory 0x1FF4 0000-
Bank 2 128 K System flash N/A(2)
0x1FF5 FFFF
User option Registers
Option bytes Bank 1 N/A - N/A
bytes only(3)
1. SNB1/2 contains the target sector number for an erase operation. See Section 4.3.10 for details.
2. Cannot be erased by application software.
3. Only bank 1 option byte registers are applicable. Bank 2 option byte registers must be kept at reset value.

Table 15. Flash memory organization on STM32H742xI/743xI/753xI devices

Size Access SNB1/2
Flash memory area Address range Region name (1)
(bytes) interface

0x0800 0000-
128 K Sector 0 0x0
0x0801 FFFF
0x0802 0000-
128 K Sector 1 0x1
Bank 1 0x0803 FFFF
... ... ... ...
0x080E 0000-
128 K Sector 7 0x7
User main 0x080F FFFF
AXI ports
memory 0x0810 0000-
128 K Sector 0 0x0
0x0811 FFFF
0x0812 0000-
128 K Sector 1 0x1
Bank 2 0x0813 FFFF
... ... ... ...
0x081E 0000-
128 K Sector 7 0x7
0x081F FFFF
0x1FF0 0000- System flash
Bank 1 128 K N/A(2)
System 0x1FF1 FFFF (read-only)
AXI ports
memory 0x1FF4 0000-
Bank 2 128 K System flash N/A(2)
0x1FF5 FFFF
User option Registers
Option bytes Bank 1 N/A - N/A
bytes only
1. SNB1/2 contains the target sector number for an erase operation. See Section 4.3.10 for details.
2. Cannot be erased by application software.

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Table 16. Flash memory organization on STM32H742xG/743xG devices

Size Access SNB1/2
Flash memory area Address range Region name (1)
(bytes) interface

0x0800 0000-
128 K Sector 0 0x0
0x0801 FFFF
0x0802 0000-
128 K Sector 1 0x1
Bank 1 0x0803 FFFF
... ... ... ...
0x0806 0000-
128 K Sector 3 0x3
User main 0x0807 FFFF
AXI ports
memory 0x0810 0000-
128 K Sector 0 0x0
0x0811 FFFF
0x0812 0000-
128 K Sector 1 0x1
Bank 2 0x0813 FFFF
... ... ... ...
0x0816 0000-
128 K Sector 3 0x3
0x0817 FFFF
0x1FF0 0000- System flash
Bank 1 128 K N/A(2)
System 0x1FF1 FFFF (read-only)
AXI ports
memory 0x1FF4 0000-
Bank 2 128 K System flash N/A(2)
0x1FF5 FFFF
User option Registers
Option bytes Bank 1 N/A - N/A
bytes only
1. SNB1/2 contains the target sector number for an erase operation. See Section 4.3.10 for details.
2. Cannot be erased by application software.

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Partition usage
Figure 8 shows how the embedded flash memory is used both by STMicroelectronics and
the application software.

Figure 8. Embedded flash memory usage

SWAP_BANK=0

SWAP_BANK=1
STM32 STM32
Standard mode Secure access
secure area
mode

Application
Bank1 Bank2 software
Application secure
Application software
User memory
software
Application
Bank2 Bank1 software
Application secure
software
jump

reserved Secure bootloader

System Secure library
memory Bank1
Bootloader Bootloader

User option bytes Bank1 User option bytes

Managed through
registers only reserved Bank2 reserved

MSv46173V4

User and system memories are used differently according to whether the microcontroller is
configured by the application software in Standard mode or in Secure access mode. This
selection is done through the SECURITY option bit (see Section 4.4.6):
• In Standard mode, the user memory contains the application code and data, while the
system memory is loaded with the STM32 bootloader. When a reset occurs, the core
jumps to the boot address configured through the BOOT pin and the BOOT_ADD0/1
option bytes.
• In Secure access mode, dedicated libraries can be used for secure boot. They are
located in user flash and system flash memory:
– ST libraries in system flash memory assist the application software boot with
special features such as secure boot and secure firmware install (SFI).
– Application secure libraries in user flash memory are used for secure firmware
update (SFU).

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In Secure access mode, the microcontroller always boots into the secure bootloader
code (unique entry point). Then, if no secure services are required, this code securely
jumps to the requested boot address configured through the BOOT pin and the option
bytes, as shown in Figure 8 (see Section 5: Secure memory management (SMM) for
details).
Note: For more information on option byte setup for boot, refer to Section 4.4.7.
Additional partition usage is the following:
• The option bytes are used by STMicroelectronics and by the application software as
non-volatile product options (e.g. boot address, protection configuration and reset
behaviors).
Note: For further information on STM32 bootloader flashing by STMicroelectronics, refer to
application note AN2606 “STM32 microcontroller system memory boot mode” available
from www.st.com.

Bank swapping
As shown in Figure 8, the embedded flash memory offers a bank swapping feature that can
be configured through the SWAP_BANK bit, always available for the application. For more
information please refer to Section 4.3.13.

4.3.5 FLASH system performance enhancements

The embedded flash memory uses read and write command queues (one per bank) in order
to enhance flash operations.

4.3.6 FLASH data protection schemes

Figure 9 gives an overview of the protection mechanisms supported by the embedded flash
memory. A PCROP and a secure-only area can be defined for each bank. The properties of
these protected areas are detailed in Section 4.5.

Figure 9. FLASH protection mechanisms

secure access only (SEC)

execute only, no read access (PCROP)
ST firmware update code area
Bank 1 Bank 2
Sector 7 Sector 7
Sector 6 Sector 6
User option

User option

SEC_AREA_END1
SEC_AREA_START1 Sector 5 Sector 5 PROT_AREA_END2
bytes

bytes

Sector 4 Sector 4
user

PROT_AREA_START2
Sector 3 Sector 3
PROT_AREA_END1 Sector 2 Sector 2 SEC_AREA_END2
PROT_AREA_START1 Sector 1 Sector 1 SEC_AREA_START2
Sector 0 Sector 0
system

Sytem Flash1 Sytem Flash2

Write-locked by ST

MSv46175V2

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4.3.7 Overview of FLASH operations

Read operations
The embedded flash memory can perform read operations on the whole non-volatile
memory using various granularities: 64 bits, 32 bits, 16 bits or one byte. User and system
flash memories are read through the AXI interface, while the option bytes are read through
the register interface.
The embedded flash memory supports read-while-write operations provided the read and
write operations target different banks. Similarly read-while-read operations are supported
when two read operations target different banks.
To increase efficiency, the embedded flash memory implements the buffering of consecutive
read requests in the same bank.
For more details on read operations, refer to Section 4.3.8: FLASH read operations.

Program/erase operations
The embedded flash memory supports the following program and erase operations:
• Single flash word write (256-bit granularity), with the possibility for the application to
force-write a user flash word with less than 256 bits
• Single sector erase
• Bank erase (single or dual)
• Option byte update
Thanks to its dual bank architecture, the embedded flash memory can perform any of the
above write or erase operation on one bank while a read or another program/erase
operation is executed on the other bank.
Note: Program and erase operations are subject to the various protection that could be set on the
embedded flash memory, such as write protection and global readout protection (see next
sections for details).
To increase efficiency, the embedded flash memory implements the buffering of consecutive
write accesses in the same bank.
For more details refer to Section 4.3.9: FLASH program operations and Section 4.3.10:
FLASH erase operations.

Protection mechanisms
The embedded flash memory supports different protection mechanisms:
• Global readout protection (RDP)
• Proprietary code readout protection (PCROP)
• Write protection
• Secure access only protection
For more details refer to Section 4.5: FLASH protection mechanisms.

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Option byte loading

Under specific conditions, the embedded flash memory reliably loads the non-volatile option
bytes stored in non-volatile memory, thus enforcing boot and security options to the whole
system when the embedded flash memory becomes functional again. For more details refer
to Section 4.4: FLASH option bytes.

Bank/register swapping
The embedded flash memory allows swapping bank 1 and bank 2 memory mapping. This
feature can be used after a firmware upgrade to restart the microcontroller on the new
firmware after a system reset. For more details on the feature, refer to Section 4.3.13: Flash
bank and register swapping (STM32H742/743/753 devices only).

4.3.8 FLASH read operations

Read operation overview
The embedded flash memory supports, for each memory bank, the execution of one read
command while two are waiting in the read command queue. Multiple read access types are
also supported as defined in Section 4.3.3: FLASH architecture and integration in the
system.
The read commands to each bank are associated with a 256-bit read data buffer.
Note: The embedded flash memory can perform single error correction and double error detection
while read operations are being executed (see Section 4.3.12: Flash memory error
protections).
The AXI interface read channel operates as follows:
• When the read command queue is full, any new AXI read request stalls the bus read
channel interface and consequently the master that issued that request.
• If several consecutive read accesses request data that belong to the same flash data
word (256 bits), the data are read directly from the current data read buffer, without
triggering additional flash read operations. This mechanism occurs each time a read
access is granted. When a read access is rejected for security reasons (e.g. PCROP
protected word), the corresponding read error response is issued by the embedded
flash memory and no read operation to flash memory is triggered.
The Read pipeline architecture is summarized in Figure 10.
For more information on bus interfaces, refer to Section 4.3.3: FLASH architecture and
integration in the system.

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Figure 10. FLASH read pipeline architecture

ready

memory interface 1
Read queue1
(x3)

Non-volatile
64-bit AXI bus

AXI Interface1

Flash
Write queue1 256-bit
Bank1
(x2)
ECC

buffer
Read
To AXI

data
1 or 2

ready

memory interface 2
Read queue2
(x3)

Non-volatile
64-bit AXI bus

AXI Interface2

Flash
Write queue2 256-bit Bank2
(x2)
ECC

buffer
Read
To AXI data
1 or 2

FLASH

MSv46169V2

Single read sequence

The recommended simple read sequence is the following:
1. Freely perform read accesses to any AXI-mapped area.
2. The embedded flash memory effectively executes the read operation from the read
command queue buffer as soon as the non-volatile memory is ready and the previously
requested operations on this specific bank have been served.

Adjusting read timing constraints

The embedded flash memory clock must be enabled and running before reading data from
non-volatile memory.
To correctly read data from flash memory, the number of wait states (LATENCY) must be
correctly programmed in the flash access control register (FLASH_ACR) according to the
embedded flash memory AXI interface clock frequency (sys_ck) and the internal voltage
range of the device (Vcore).
Table 17 shows the correspondence between the number of wait states (LATENCY), the
programming delay parameter (WRHIGHFREQ), the embedded flash memory clock
frequency and its supply voltage ranges.

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Table 17. FLASH recommended number of wait states and programming delay(1)
AXI Interface clock frequency vs VCORE range
Number of Programming
wait states delay
VOS3 range VOS2 range VOS1 range VOS0 range
(LATENCY) (WRHIGHFREQ)
0.95 V - 1.05 V 1.05 V - 1.15 V 1.15 V - 1.26 V 1.26 V - 1.40 V

0 WS (1
FLASH clock 00 [0;45 MHz] [0;55 MHz] [0;70 MHz] [0;70 MHz]
cycle)

1 WS (2
FLASH clock 01 ]45 MHz;90 MHz] ]55 MHz;110 MHz] ]70 MHz;140 MHz] ]70 MHz;140 MHz]
cycles)

2 WS (3 01 ]90 MHz;135 MHz] ]110 MHz;165 MHz] ]140 MHz;185 MHz] ]140 MHz;185 MHz]
FLASH clock
cycles) 10 - - ]185 MHz;210 MHz] ]185 MHz;210 MHz]

3 WS (4
FLASH clock 10 ]135 MHz;180 MHz] ]165 MHz;225 MHz] ]210 MHz;225 MHz] ]210 MHz;225 MHz]
cycles)

4 WS (5
FLASH clock 10 ]180 MHz;225 MHz] 225 MHz - ]225 MHz;240 MHz]
cycles)

1. Refer to the Reset and clock control section RCC section for the maximum product FACLK frequency.

Adjusting system frequency

After power-on, a default 7 wait-state latency is specified in FLASH_ACR register, in order
to accommodate AXI interface clock frequencies with a safety margin (see Table 17).
When changing the AXI bus frequency, the application software must follow the below
sequence in order to tune the number of wait states required to access the non-volatile
memory.
To increase the embedded flash memory clock source frequency:
1. If necessary, program the LATENCY and WRHIGHFREQ bits to the right value in the
FLASH_ACR register, as described in Table 17.
2. Check that the new number of wait states is taken into account by reading back the
FLASH_ACR register.
3. Modify the embedded flash memory clock source and/or the AXI bus clock prescaler in
the RCC_CFGR register of the reset and clock controller (RCC).
4. Check that the new embedded flash memory clock source and/or the new AXI bus
clock prescaler value are taken in account by reading back the embedded flash
memory clock source status and/or the AXI bus prescaler value in the RCC_CFGR
register of the reset and clock controller (RCC).
To decrease the embedded flash memory clock source frequency:
1. Modify the embedded flash memory clock source and/or the AXI bus clock prescaler in
the RCC_CFGR register of reset and clock controller (RCC).
2. Check that the embedded flash memory new clock source and/or the new AXI bus
clock prescaler value are taken into account by reading back the embedded flash

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memory clock source status and/or the AXI interface prescaler value in the
RCC_CFGR register of reset and clock controller (RCC).
3. If necessary, program the LATENCY and WRHIGHFREQ bits to the right value in
FLASH_ACR register, as described in Table 17.
4. Check that the new number of wait states has been taken into account by reading back
the FLASH_ACR register.

Error code correction (ECC)

The embedded flash memory embeds an error correction mechanism. Single error
correction and double error detection are performed for each read operation. For more
details, refer to Section 4.3.12: Flash memory error protections.

Read errors
When the ECC mechanism is not able to correct the read operation, the embedded flash
memory reports read errors as described in Section 4.7.7: Error correction code error
(SNECCERR/DBECCERR).

Read interrupts
See Section 4.8: FLASH interrupts for details.

4.3.9 FLASH program operations

Program operation overview
The virgin state of each non-volatile memory bitcell is 1. The embedded flash memory
supports programming operations that can change (reset) any memory bitcell to 0. However
these operations do not support the return of a bit to its virgin state. In this case an erase
operation of the entire sector is required.
A program operation consists in issuing write commands. The embedded flash memory
supports, for each memory bank, the execution of one write command while one command
is waiting in the write command queue. Since a 10-bit ECC code is associated to each 256-
bit data flash word, only write operations by 256 bits are executed in the non-volatile
memory.
Note: The application can decide to write as little as 8 bits to a 256 flash word. In this case, a
force-write mechanism to the 256 bits + ECC is used (see FW1/2 bit of FLASH_CR1/2
register).
System flash memory bank 1 cannot be written by the application software. System flash
memory bank 2 can be written by STMicroelectronics secure firmware only.
It is not recommended to overwrite a flash word that is not virgin. The result may lead to an
inconsistent ECC code that will be systematically reported by the embedded flash memory,
as described in Section 4.7.7: Error correction code error (SNECCERR/DBECCERR).
The AXI interface write channel operates as follows:
• A 256-bit write data buffer is associated with each AXI interface. It supports multiple
write access types (64 bits, 32 bits, 16 bits and 8 bits).
• When the write queue is full, any new AXI write request stalls the bus write channel
interface and consequently the master that issued that request.
The write pipeline architecture is described in Figure 11.

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For more information on bus interfaces, refer to Section 4.3.3: FLASH architecture and
integration in the system.

Figure 11. FLASH write pipeline architecture

Flash Interface Logic

ready

memory interface 1
Read queue1
Write command (x3) Command

Non-volatile
64-bit AXI bus

AXI Interface1

Flash
Write queue1 256-bit
Bank1
(x2)
buffer
Write
data

Write data ECC

Write response

System
buses ready

memory interface 2
Read queue2
(x3) Command
Write command

Non-volatile
64-bit AXI bus

AXI Interface2

Flash
Write queue2 256-bit Bank2
(x2)
buffer
Write
data

Write data ECC

Write response

FLASH

MSv46182V2

Managing write protections

Before programming a user sector, the application software must check the protection of the
targeted flash memory area.
The embedded flash memory checks the protection properties of the write transaction target
at the output of the write queue buffer, just before the effective write operation to the non-
volatile memory:
• If a write protection violation is detected, the write operation is canceled and write
protection error (WRPERR1/2) is raised in FLASH_SR1/2 register.
• If the write operation is valid, the 10-bit ECC code is concatenated to the 256 bits of
data and the write to non-volatile memory is effectively executed.
Note: No write protection check is performed when the embedded flash memory accepts AXI write
requests.
The write protection flag does not need to be cleared before performing a new programming
operation.

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Monitoring ongoing write operations

The application software can use three status flags located in FLASH_SR1/2 in order to
monitor ongoing write operations. Those status are available for each bank.
• BSY1/2: this bit indicates that an effective write, erase or option byte change operation
is ongoing to the non-volatile memory.
• QW1/2: this bit indicates that a write, erase or option byte change operation is pending
in the write queue or command queue buffer. It remains high until the write operation is
complete. It supersedes the BSY1/2 status bit.
• WBNE1/2: this bit indicates that the embedded flash memory is waiting for new data to
complete the 256-bit write buffer. In this state the write buffer is not empty. It is reset as
soon as the application software fills the write buffer, force-writes the operation using
FW1/2 bit in FLASH_CR1/2, or disables all write operations in the corresponding bank.

Enabling write operations

Before programming the user flash memory in bank 1 (respectively bank 2), the application
software must make sure that PG1 bit (respectively PG2) is set to 1 in FLASH_CR1
(respectively FLASH_CR2). If it is not the case, an unlock sequence must be used (see
Section 4.5.1: FLASH configuration protection) and the PG1/2 bit must be set.
When the option bytes need to be modified or a mass erase needs to be started, the
application software must make sure that FLASH_OPTCR is unlocked. If it is not the case,
an unlock sequence must be used (see Section 4.5.1: FLASH configuration protection).
Note: The application software must not unlock a register that is already unlocked, otherwise this
register will remain locked until next system reset.

If needed, the application software can update the programming delay and programming
parallelism as described at the end of this section.

Single write sequence

The recommended single write sequence in bank 1/2 is the following:
1. Unlock the FLASH_CR1/2 register, as described in Section 4.5.1: FLASH configuration
protection (only if register is not already unlocked).
2. Enable write operations by setting the PG1/2 bit in the FLASH_CR1/2 register.
3. Check the protection of the targeted memory area.
4. Write one flash-word corresponding to 32-byte data starting at a 32-byte aligned
address.
5. Check that QW1 (respectively QW2) has been raised and wait until it is reset to 0.
If step 4 is executed incrementally (e.g. byte per byte), the write buffer can become partially
filled. In this case the application software can decide to force-write what is stored in the
write buffer by using FW1/2 bit in FLASH_CR1/2 register. In this particular case, the
unwritten bits are automatically set to 1. If no bit in the write buffer is cleared to 0, the FW1/2
bit has no effect.

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Note: Using a force-write operation prevents the application from updating later the missing bits
with a value different from 1, which is likely to lead to a permanent ECC error.
Any write access requested while the PG1/2 bit is cleared to 0 is rejected. In this case, no
error is generated on the bus, but the PGSERR1/2 flag is raised.
Clearing the programming sequence error (PGSERR) and inconsistency error (INCERR) is
mandatory before attempting a write operation (see Section 4.7: FLASH error management
for details).

Adjusting programming timing constraints

Program operation timing constraints depend of the embedded flash memory clock
frequency, which directly impacts the performance. If timing constraints are too tight, the
non-volatile memory will not operate correctly, if they are too lax, the programming speed
will not be optimal.
The user must therefore trim the optimal programming delay through the WRHIGHFREQ
parameter in the FLASH_ACR register. Refer to Table 17 in Section 4.3.8: FLASH read
operations for the recommended programming delay depending on the embedded flash
memory clock frequency.
FLASH_ACR configuration register is common to both banks.
The application software must check that no program/erase operation is ongoing before
modifying WRHIGHFREQ parameter.
Caution: Modifying WRHIGHFREQ while programming/erasing the flash memory might corrupt the
flash memory content.

Adjusting programming parallelism

The parallelism is the maximum number of bits that can be written to 0 in one shot during a
write operation. The programming parallelism is also used during sector and bank erase.
There is no hardware limitation on programming parallelism. The user can select different
parallelisms depending on the application requirements: the lower the parallelism, the lower
the peak consumption during a programming operation, but the longer the execution time.
The parallelism is configured through the PSIZE1/2 bits in FLASH_CR1/2 register. Two
distinct values can be defined for bank 1 and 2 (refer to Table 18).

Table 18. FLASH parallelism parameter

PSIZE1/2 Parallelism

00 8 bits (one byte)

01 16 bits
10 32 bits
11 64 bits

Caution: Modifying PSIZE1/2 while programming/erasing the flash memory might corrupt the flash
memory content.

Programming errors
When a program operation fails, an error can be reported as described in Section 4.7:
FLASH error management.

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Programming interrupts
See Section 4.8: FLASH interrupts for details.

4.3.10 FLASH erase operations

Erase operation overview
The embedded flash memory can perform erase operations on 128-Kbyte user sectors, on
one user flash memory bank or on two user flash memory banks (i.e. mass erase).
Note: System flash memory cannot be erased by the application software.
The erase operation forces all non-volatile bit cells to high state, which corresponds to the
virgin state. It clears existing data and corresponding ECC, allowing a new write operation to
be performed. If the application software reads back a word that has been erased, all the
bits will be read at 1, without ECC error.
Erase operations are similar to read or program operations except that the commands are
queued in a special buffer (a two-command deep erase queue).
Erase commands are issued through the AHB configuration interface. If the embedded flash
memory receives simultaneously a write and an erase request for the same bank, both
operations are accepted but the write operation is executed first.
Note: If data cache is enabled after a flash erase operation, it is recommended to invalidate the
cache by software to avoid reading old data.

Erase and security

A user sector can be erased only if it does not contain PCROP, secure-only or write-
protected data (see Section 4.5: FLASH protection mechanisms for details). In other words,
if the application software attempts to erase a user sector with at least one flash word that is
protected, the sector erase operation is aborted and the WRPERR1/2 flag is raised in the
FLASH_SR1/2 register, as described in Section 4.7.2: Write protection error (WRPERR).
The embedded flash memory allows the application software to perform an erase followed
by an automatic protection removal (PCROP, secure-only area and write protection), as
described hereafter.

Enabling erase operations

Before erasing a sector in bank 1 (respectively bank 2), the application software must make
sure that FLASH_CR1 (respectively FLASH_CR2) is unlocked. If it is not the case, an
unlock sequence must be used (see Section 4.5.1: FLASH configuration protection).
Note: The application software must not unlock a register that is already unlocked, otherwise this
register will remain locked until next system reset.
Similar constraints apply to bank erase requests.

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Flash sector erase sequence

To erase a 128-Kbyte user sector, proceed as follows:
1. Check and clear (optional) all the error flags due to previous programming/erase
operation. Refer to Section 4.7: FLASH error management for details.
2. Unlock the FLASH_CR1/2 register, as described in Section 4.5.1: FLASH configuration
protection (only if register is not already unlocked).
3. Set the SER1/2 bit and SNB1/2 bitfield in the corresponding FLASH_CR1/2 register.
SER1/2 indicates a sector erase operation, while SNB1/2 contains the target sector
number.
4. Set the START1/2 bit in the FLASH_CR1/2 register.
5. Wait for the QW1/2 bit to be cleared in the corresponding FLASH_SR1/2 register.
Note: If a bank erase is requested simultaneously to the sector erase (BER1/2 bit set), the bank
erase operation supersedes the sector erase operation.

Standard flash bank erase sequence

To erase all bank sectors except for those containing secure-only and protected data,
proceed as follows:
1. Check and clear (optional) all the error flags due to previous programming/erase
operation. Refer to Section 4.7: FLASH error management for details.
2. Unlock the FLASH_CR1/2 register, as described in Section 4.5.1: FLASH configuration
protection (only if register is not already unlocked).
3. Set the BER1/2 bit in the FLASH_CR1/2 register corresponding to the targeted bank.
4. Set the START1/2 bit in the FLASH_CR1/2 register to start the bank erase operation.
Then wait until the QW1/2 bit is cleared in the corresponding FLASH_SR1/2 register.
Note: BER1/2 and START1/2 bits can be set together, so above steps 3 and 4 can be merged.
If a sector erase is requested simultaneously to the bank erase (SER1/2 bit set), the bank
erase operation supersedes the sector erase operation.

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Flash bank erase with automatic protection-removal sequence

To erase all bank sectors including those containing secure-only and protected data without
performing an RDP regression (see Section 4.5.3), proceed as follows:
1. Check and clear (optional) all the error flags due to previous programming/erase
operation. Refer to Section 4.7: FLASH error management for details.
2. Unlock FLASH_OPTCR register, as described in Section 4.5.1: FLASH configuration
protection (only if register is not already unlocked).
3. If a PCROP-protected area exists set DMEP1/2 bit in FLASH_PRAR_PRG1/2 register.
In addition, program the PCROP area end and start addresses so that the difference is
negative, i.e. PROT_AREA_END1/2 < PROT_AREA_START1/2.
4. If a secure-only area exists set DMES1/2 bit in FLASH_SCAR_PRG1/2 register. In
addition, program the secure-only area end and start addresses so that the difference
is negative, i.e. SEC_AREA_END1/2 < SEC_AREA_START1/2.
5. Set all WRPSn1/2 bits in FLASH_WPSN_PRG1/2R to 1 to disable all sector write
protection.
6. Unlock FLASH_CR1/2 register, only if register is not already unlocked.
7. Set the BER1/2 bit in the FLASH_CR1/2 register corresponding to the target bank.
8. Set the START1/2 bit in the FLASH_CR1/2 register to start the bank erase with
protection removal operation. Then wait until the QW1/2 bit is cleared in the
corresponding FLASH_SR1/2 register. At that point a bank erase operation has erased
the whole bank including the sectors containing PCROP-protected and/or secure-only
data, and an option byte change has been automatically performed so that all the
protections are disabled.
Note: BER1/2 and START1/2 bits can be set together, so above steps 8 and 9 can be merged.
Be aware of the following warnings regarding to above sequence:
• It is not possible to perform the above sequence on one bank while modifying the
protection parameters of the other bank.
• No other option bytes than the one indicated above must be changed, and no
protection change must be performed in the bank that is not targeted by the bank erase
with protection removal request.
• When one or both of the events above occurs, a simple bank erase occurs, no option
byte change is performed and no option change error is set.

Flash mass erase sequence

To erase all sectors of both banks simultaneously (STM32H742/743/753 only), excepted for
those containing secure-only and protected data, the application software can set the MER
bit to 1 in FLASH_OPTCR register, as described below:
1. Check and clear (optional) all the error flags due to previous programming/erase
operation. Refer to Section 4.7: FLASH error management for details.
2. Unlock the two FLASH_CR1/2 registers and FLASH_OPTCR register, as described in
Section 4.5.1: FLASH configuration protection (only if the registers are not already
unlocked).
3. Set the MER bit to 1 in FLASH_OPTCR register. It automatically sets BER1, BER2,
START1 and START2 to 1, thus launching a bank erase operation on both banks. Then
wait until both QW1 and QW2 bits are cleared in the corresponding FLASH_SR1/2
register.

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Flash mass erase with automatic protection-removal sequence

To erase all sectors of both banks simultaneously (STM32H742/743/753 only), including
those containing secure-only and protected data, and without performing an RDP
regression, proceed as follows:
1. Check and clear (optional) all the error flags due to previous programming/erase
operation.
2. Unlock the two FLASH_CR1/2 registers and FLASH_OPTCR register (only if the
registers are not already unlocked).
3. If a PCROP-protected area exists, set DMEP1/2 bit in FLASH_PRAR_PRG1/2 register.
In addition, program the PCROP area end and start addresses so that the difference is
negative. This operation must be performed for both banks.
4. If a secure-only area exists, set DMES1/2 bit in FLASH_SCAR_PRG1/2 register. In
addition, program the secure-only area end and start addresses so that the difference
is negative. This operation must be performed for both banks.
5. Set all WRPSn1/2 bits in FLASH_WPSN_PRG1/2R to 1 to disable all sector write
protections. This operation must be performed for both banks.
6. Set the MER bit to 1 in FLASH_OPTCR register, then wait until the QW1/2 bit is
cleared in the corresponding FLASH_SR1/2 register. At that point, a flash bank erase
with automatic protection removal is executed on both banks. The sectors containing
PCROP-protected and/or secure-only data become unprotected since an option byte
change is automatically performed after the mass erase so that all the protections are
disabled.
Caution: No other option bytes than the ones mentioned in the above sequence must be changed,
otherwise a simple mass erase is executed, no option byte change is performed and no
option change error is raised.

4.3.11 FLASH parallel operations (STM32H742/743/753 devices only)

As the non-volatile memory is divided into two independent banks, the embedded flash
memory interface can drive different operations at the same time on each bank. For
example a read, write or erase operation can be executed on bank 1 while another read,
write or erase operation is executed on bank 2.
In all cases, the sequences described in Section 4.3.8: FLASH read operations,
Section 4.3.9: FLASH program operations and Section 4.3.10: FLASH erase operations
apply.

4.3.12 Flash memory error protections

Error correction codes (ECC)
The embedded flash memory supports an error correction code (ECC) mechanism. It is
based on the SECDED algorithm in order to correct single errors and detects double errors.
This mechanism uses 10 ECC bits per 256-bit flash word, and applies to user and system
flash memory.
More specifically, during each read operation from a 256-bit flash word, the embedded flash
memory also retrieves the 10-bit ECC information, computes the ECC of the flash word, and
compares the result with the reference value. If they do not match, the corresponding ECC

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error is raised as described in Section 4.7.7: Error correction code error

(SNECCERR/DBECCERR).
During each program operation, a 10- bit ECC code is associated to each 256-bit data flash
word, and the resulting 266-bit flash word information is written in non-volatile memory.

Cyclic redundancy codes (CRC)

The embedded flash memory implements a cyclic redundancy check (CRC) hardware
module. This module checks the integrity of a given user flash memory area content (see
Figure 6: Detailed FLASH architecture).
The area processed by the CRC module can be defined either by sectors or by start/end
addresses. It can also be defined as the whole bank (user flash memory area only).
Note: Only one CRC check operation on bank 1 or 2 can be launched at a time. To avoid
corruption, do not configure the CRC calculation on the one bank, while calculating the CRC
on the other bank.
When enabled, the CRC hardware module performs multiple reads by chunks of 4, 16, 64 or
256 consecutive flash-word (i.e. chunks of 128, 512, 2048 or 8192 bytes). These
consecutive read operations are pushed by the CRC module into the required read
command queue together with other AXI read requests, thus avoiding to deny AXI read
commands.
CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7:
X32+ X26+ X23+ X22+ X16+ X12+ X11+ X10+ X8+ X7+ X5+ X4+ X2+ X + 1
The CRC operation is concurrent with option byte change as the same hardware is used for
both operations. To avoid the CRC computation from being corrupted, the application shall
complete the option byte change (by reading the result of the change) before running a CRC
operation, and vice-versa.
The sequence recommended to configure a CRC operation in the bank 1/2 is the following:
1. Unlock FLASH_CR1/2 register, if not already unlocked.
2. Enable the CRC feature by setting the CRC_EN bit in FLASH_CR1/2.
3. Program the desired data size in the CRC_BURST field of FLASH_CRCCR1/2.
4. Define the user flash memory area on which the CRC has to be computed.Two
solutions are possible:
– Define the area start and end addresses by programing FLASH_CRCSADD1/2R
and FLASH_CRCEADD1/2R, respectively,
– or select the targeted sectors by setting the CRC_BY_SECT bit in
FLASH_CRCCR1/2 and by programming consecutively the target sector numbers
in the CRC_SECT field of the FLASH_CRCCR1/2 register. Set ADD_SECT bit
after each CRC_SECT programming.
5. Start the CRC operation by setting the START_CRC bit.
6. Wait until the CRC_BUSY1/2 flag is reset in FLASH_SR1/2 register.
7. Retrieve the CRC result in the FLASH_CRCDATAR register.
The CRC can be computed for a whole bank by setting the ALL_BANK bit in the
FLASH_CRCCR1/2 register.

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Note: The application should avoid running a CRC on PCROP- or secure-only user flash memory
area since it may alter the expected CRC value.
CRC computation does not raise standard read error flags such as RDSERR1/2,
RDPERR1/2 and DBECCERR1/2.

4.3.13 Flash bank and register swapping (STM32H742/743/753 devices only)

Flash bank swapping
The embedded flash memory bank 1 and bank 2 can be swapped in the memory map
accessible through AXI interface. This feature can be used after a firmware upgrade to
restart the device on the new firmware. Bank swapping is controlled by the SWAP_BANK bit
of the FLASH_OPTCR register.
Note: The flash bank swapping is not available on STM32H750xB devices. The SWAP_BANK
option bit must be kept to '0'.
Table 19 shows the memory map that can be accessed from the embedded flash memory
AXI slave interface, depending on the SWAP_BANK bit configuration.

Table 19. FLASH AXI interface memory map vs swapping option

Flash memory
Flash corresponding bank
Size
memory Start address End address Region Name
(bytes)
area SWAP_ SWAP_
BANK=0 BANK=1

0x0800 0000 0x0801 FFFF 128 K Sector 0

0x0802 0000 0x0803 FFFF 128 K Sector 1
Bank 1 Bank 2
... ... ... ...
User 0x080E 0000 0x080F FFFF 128 K Sector 7
main
memory 0x0810 0000 0x0811 FFFF 128 K Sector 0
0x0812 0000 0x0813 FFFF 128 K Sector 1
Bank 2 Bank 1
... ... ... ...
0x081E 0000 0x081F FFFF 128 K Sector 7
System flash memory
Bank 1 0x1FF0 0000 0x1FF1 FFFF 128 K
System (bank 1)
memory System flash memory
Bank 2 0x1FF4 0000 0x1FF5 FFFF 128 K
(bank 2)

The SWAP_BANK bit in FLASH_OPTCR register is loaded from the SWAP_BANK_OPT

option bit only after system reset or POR.
To change the SWAP_BANK bit (for example to apply a new firmware update), respect the
sequence below:

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1. Unlock OPTLOCK bit, if not already unlocked.

2. Set the new desired SWAP_BANK_OPT value in the FLASH_OPTSR_PRG register.
3. Start the option byte change sequence by setting the OPTSTART bit in the
FLASH_OPTCR register.
4. Once the option byte change has completed, FLASH_OPTSR_CUR contains the
expected SWAP_BANK_OPT value, but SWAP_BANK bit in FLASH_OPTCR has not
yet been modified and the bank swapping is not yet effective.
5. Force a system reset or a POR. When the reset rises up, the bank swapping is
effective (SWAP_BANK value updated in FLASH_OPTCR) and the new firmware shall
be executed.
Note: The SWAP_BANK bit in FLASH_OPTCR is read-only and cannot be modified by the
application software.
The SWAP_BANK_OPT option bit in FLASH_OPTSR_PRG can be modified whatever the
RDP level (i.e. even in level 2), thus allowing advanced firmware upgrade in any level of
readout protection.
Figure 12 gives an overview of the bank swapping sequence.

Figure 12. Flash bank swapping sequence

Begin

Update new firmware in

user Flash bank 1/2

FLASH_OPTSR_PRG
Set/unset SWAP_
SWAP_BANK_OPT BANK_
option bit in OPT
FLASH_OPTSR_PRG
Option
byte pro Non-volatile
gramm
Write START bit in ing memory
FLASH_OPTCR to start
The option byte change FLASH_OPTSR_CUR
sequence SWAP ad
byte relo
BANK Option
OPT
System reset
System reset
option byte
reload

SWAP_BANK of
FLASH_OPTSR_CUR is FLASH_OPTCR
copied to SWAP_BANK
bit in FLASH_OPTCR SWAP
BANK User Non-volatile
Flash memory
New swap
policy effe memory Bank1
End ctive
SWAP
Execution of new logic Non-volatile
AXI bus memory
firmware
Bank2

MSv46185V2

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Configuration and option byte register swapping

The embedded flash memory bank swapping option controlled by the SWAP_BANK bit also
swaps the two sets of configuration and option byte registers, as shown in Table 20. One set
of registers is related to bank 1 while the other is related to bank 2. Since some registers are
not specific to any particular bank, they are mapped onto two different addresses so that the
swapping does not affect the access to these registers.

Table 20. Flash register map vs swapping option

Register targeting bank (1)
Address offset (1) Register name
SWAP_BANK=0 SWAP_BANK=1

0x000 or 0x100 FLASH_ACR N/A N/A

0x004 0x104 FLASH_KEYR1 FLASH_KEYR2 Bank 1 Bank 2 Bank 2 Bank 1
0x008 or 0x108 FLASH_OPTKEYR N/A N/A
0x00C 0x10C FLASH_CR1 FLASH_CR2 Bank 1 Bank 2 Bank 2 Bank 1
0x010 0x110 FLASH_SR1 FLASH_SR2 Bank 1 Bank 2 Bank 2 Bank 1
0x014 0x114 FLASH_CCR1 FLASH_CCR2 Bank 1 Bank 2 Bank 2 Bank 1
0x018 or 0x118 FLASH_OPTCR N/A N/A
0x01C or 0x11C FLASH_OPTSR_CUR N/A N/A
0x020 or 0x120 FLASH_OPTSR_PRG N/A N/A
0x024 or 0x124 FLASH_OPTCCR N/A N/A
0x028 0x128 FLASH_PRAR_CUR1 FLASH_PRAR_CUR2 Bank 1 Bank 2 Bank 2 Bank 1
0x02C 0x12C FLASH_PRAR_PRG1 FLASH_PRAR_PRG2 Bank 1 Bank 2 Bank 2 Bank 1
0x030 0x130 FLASH_SCAR_CUR1 FLASH_SCAR_CUR2 Bank 1 Bank 2 Bank 2 Bank 1
0x034 0x134 FLASH_SCAR_PRG1 FLASH_SCAR_PRG2 Bank 1 Bank 2 Bank 2 Bank 1
0x038 0x138 FLASH_WPSGN_CUR1 FLASH_WPSGN_CUR2 Bank 1 Bank 2 Bank 2 Bank 1
0x03C 0x13C FLASH_WPSGN_PRG1 FLASH_WPSGN_PRG2 Bank 1 Bank 2 Bank 2 Bank 1
0x040 or 0x140 FLASH_BOOT_CUR N/A N/A
0x044 or 0x144 FLASH_BOOT_PRG N/A N/A
0x050 0x150 FLASH_CRCCR1 FLASH_CRCCR2 Bank 1 Bank 2 Bank 2 Bank 1
0x054 0x154 FLASH_CRCSADD1R FLASH_CRCSADD2R Bank 1 Bank 2 Bank 2 Bank 1
0x058 0x158 FLASH_CRCEADD1R FLASH_CRCEADD2R Bank 1 Bank 2 Bank 2 Bank 1
0x05C 0x15C FLASH_CRCDATAR N/A N/A
0x060 0x160 FLASH_ECC_FA1R FLASH_ECC_FA2R Bank 1 Bank 2 Bank 2 Bank 1
1. As shown above, some registers are not dedicated to a specific bank and can be accessed at two different addresses.

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4.3.14 FLASH reset and clocks

Reset management
The embedded flash memory can be reset by a D1 domain reset (d1_rst), driven by the
reset and clock control (RCC). The main effects of this reset are the following:
• All registers, except for option byte registers, are cleared, including read and write
latencies. If the bank swapping option is changed, it will be applied.
• Most control registers are automatically protected against write operations. To
unprotect them, new unlock sequences must be used as described in Section 4.5.1:
FLASH configuration protection.
The embedded flash memory can be reset by a power-on reset (po_rst), driven by the reset
and clock control (RCC). When the reset falls, all option byte registers are reset. When the
reset rises up, the option bytes are loaded, potentially applying new features. During this
loading sequence, the device remains under reset and the embedded flash memory is not
accessible.
The Reset signal can have a critical impact on the embedded flash memory:
• The contents of the flash memory are not guaranteed if a device reset occurs during a
flash memory write or erase operation.
• If a reset occurs while the option byte modification is ongoing, the old option byte
values are kept. When it occurs, a new option byte modification sequence is required to
program the new values.

Clock management
The embedded flash memory uses the microcontroller system clock (sys_ck), here the AXI
interface clock.
Depending on the device clock and internal supply voltage, specific read and write latency
settings usually need to be set in the flash access control register (FLASH_ACR), as
explained in Section 4.3.8: FLASH read operations and Section 4.3.9: FLASH program
operations.

4.4 FLASH option bytes

4.4.1 About option bytes

The embedded flash memory includes a set of non-volatile option bytes. They are loaded at
power-on reset and can be read and modified only through configuration registers.
These option bytes are configured by the end-user depending on the application
requirements. Some option bytes might have been initialized by STMicroelectronics during
manufacturing stage.
This section documents:
• When option bytes are loaded
• How application software can modify them
• What is the detailed list of option bytes, together with their default factory values (i.e.
before the first option byte change).

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4.4.2 Option byte loading

There are multiple ways of loading the option bytes into embedded flash memory:
1. Power-on wakeup
When the device is first powered, the embedded flash memory automatically loads all
the option bytes. During the option byte loading sequence, the device remains under
reset and the embedded flash memory cannot be accessed.
2. Wakeup from system Standby
When the D1 power domain, which contains the embedded flash memory, is switched
from DStandby mode to DRun mode, the embedded flash memory behaves as during a
power-on sequence.
3. Dedicated option byte reloading by the application
When the user application successfully modifies the option byte content through the
embedded flash memory registers, the non-volatile option bytes are programmed and
the embedded flash memory automatically reloads all option bytes to update the option
registers.
Note: The option bytes read sequence is enhanced thanks to a specific error correction code.
In case of security issue, the option bytes may be loaded with default values (see
Section 4.4.3: Option byte modification).

4.4.3 Option byte modification

Changing user option bytes
A user option byte change operation can be used to modify the configuration and the
protection settings saved in the non-volatile option byte area of memory bank 1.
The embedded flash memory features two sets of option byte registers:
• The first register set contains the current values of the option bytes. Their names have
the _CUR extension. All “_CUR” registers are read-only. Their values are automatically
loaded from the non-volatile memory after power-on reset, wakeup from system
standby or after an option byte change operation.
• The second register set allows the modification of the option bytes. Their names
contain the _PRG extension. All “_PRG” registers can be accessed in read/write mode.
When the OPTLOCK bit in FLASH_OPTCR register is set, modifying the _PRG registers is
not possible.
When OPTSTART bit is set to 1, the embedded flash memory checks if at least one option
byte needs to be programmed by comparing the current values (_CUR) with the new ones
(_PRG). If this is the case and all the other conditions are met (see Changing security option
bytes), the embedded flash memory launches the option byte modification in its non-volatile
memory and updates the option byte registers with _CUR extension.
If one of the condition described in Changing security option bytes is not respected, the
embedded flash memory sets the OPTCHANGEERR flag to 1 in the FLASH_OPTSR_CUR
register and aborts the option byte change operation. In this case, the _PRG registers are
not overwritten by current option value. The user application can check what was wrong in
their configuration.

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Unlocking the option byte modification

After reset, the OPTLOCK bit is set to 1 and the FLASH_OPTCR is locked. As a result, the
application software must unlock the option configuration register before attempting to
change the option bytes. The FLASH_OPTCR unlock sequence is described in
Section 4.5.1: FLASH configuration protection.

Option byte modification sequence

To modify user option bytes, follow the sequence below:
1. Unlock FLASH_OPTCR register as described in Section 4.5.1: FLASH configuration
protection, unless the register is already unlocked.
2. Write the desired new option byte values in the corresponding option registers
(FLASH_XXX_PRG1/2).
3. Set the option byte start change OPTSTART bit to 1 in the FLASH_OPTCR register.
4. Wait until OPT_BUSY bit is cleared.
Note: If a reset or a power-down occurs while the option byte modification is ongoing, the original
option byte value is kept. A new option byte modification sequence is required to program
the new value.

Changing security option bytes

On top of OPTLOCK bit, there is a second level of protection for security-sensitive option
byte fields. Specific rules must be followed to update them:
• Readout protection (RDP)
A detailed description of RDP option bits is given in Section 4.5.3. The following rules
must be respected to modify these option bits:
– When RDP is set to level 2, no changes are allowed (except for the SWAP bit). As
a result, if the user application attempts to reduce the RDP level, an option byte
change error is raised (OPTCHANGEERR bit in FLASH_OPTSR_CUR register),
and all the programmed changes are ignored.
– When the RDP is set to level 1, requiring a change to level 2 is always allowed.
When requiring a regression to level 0, an option byte change error can occur if
some of the recommendations provided in this chapter have not been followed.
– When the RDP is set to level 0, switching to level 1 or level 2 is possible without
any restriction.
• Sector write protection (WRPSn1/2)
These option bytes manage sector write protection in FLASH_WPSN_CUR1/2R
registers. They can be changed without any restriction when the RDP protection level
is different from level 2.
• PCROP area size (PROT_AREA_START1/2 and PROT_AREA_END1/2)
These option bytes configure the size of the PCROP areas in FLASH_PRAR_CUR1/2
registers. They can be increased without any restriction by the Arm® Cortex®-M7 core.
To remove or reduce a PCROP area, an RDP level 1 to 0 regression (see
Section 4.5.3) or a bank erase with protection removal (see Section 4.3.10) must be

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requested at the same time. DMEP must be set to 1 in either FLASH_PRAR_CUR1/2

or FLASH_PRAR_PRG1/2, otherwise an option byte change error is raised.
• DMEP1/2
When this option bit is set, the content of the corresponding PCROP area is erased
during a RDP level 1 to 0 regression (see Section 4.5.3) or a bank erase with protection
removal (see Section 4.3.10). It is preserved otherwise.
There are no restrictions in setting DMEP1/2 bit. Resetting DMEP1/2 bit from 1 to 0 can
only be done when an RDP level 1 to 0 regression or a bank erase with protection
removal is requested at the same time.
• Secure access mode (SECURITY)
The SECURITY option bit activates the secure access mode described in
Section 4.5.5. This option bit can be freely set by the application software if such mode
is activated on the device. If at least one PCROP or secure-only area is defined as not
null, the only way to deactivate the security option bit (from 1 to 0) is to perform an RDP
level 1 to 0 regression, when DMEP1/2 is set to 1 in either FLASH_PRAR_CUR1/2 or
FLASH_PRAR_PRG1/2 registers, and DMES1/2 is set to 1 in either
FLASH_SCAR_CUR1/2 or FLASH_SCAR_PRG1/2.
If no valid secure-only area and no valid PCROP area are currently defined, the
SECURITY option bit can be freely reset.
Note: It is recommended to have both SEC_AREA_START> SEC_AREA_END and
PROT_AREA_START> PROT_AREA_END programmed when deactivating the
SECURITY option bit during an RDP level 1 to 0 regression.
• Secure-only area size (SEC_AREA_START1/2 and SEC_AREA_END1/2)
These option bytes configure the size of the secure-only areas in
FLASH_SCAR_CUR1/2 registers. They can be changed without any restriction by the
user secure application or by the ST secure library running on the device. For user non-
secure application, the secure-only area size can be removed by performing a bank
erase with protection removal (see Section 4.3.10), or an RDP level 1 to 0 regression
when DMES1/2 set to 1 in either FLASH_SCAR_CUR1/2 or FLASH_SCAR_PRG1/2
(otherwise an option byte change error is raised).
• DMES1/2
When this option bit is set, the content of the corresponding secure-only area is erased
during an RDP level 1 to 0 regression or a bank erase with protection removal, it is
preserved otherwise.
DMES1/2 bits can be set without any restriction. Resetting DMES1/2 bit from 1 to 0 can
only be performed when an RDP level 1 to 0 regression or a bank erase with protection
removal is requested at the same time.

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4.4.4 Option bytes overview

Table 21 lists all the user option bytes managed through the embedded flash memory
registers, as well as their default values before the first option byte change (default factory
value).

Table 21. Option byte organization

Register Bitfield

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OPTCHANGEERR
SWAP_BANK_OP

IWDG_FZ_SDBY

IWDG_FZ_STOP
ST_RAM_SIZE
SECURITY
IO_HSLV
FLASH_OPTSR[31:16]

Res.

Res.

Res.

Res.

Res.

Res.
Res

Res
Default factory value 0 0 0 X X 1 0 0 0 0 0 X X 1 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NRST_STOP_D1
NRST_STDY_D1

IWDG1_SW

BOR_LEV
RDP[7:0]

FLASH_OPTSR[15:0]

Res.

Res.

Res.
Default factory value 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASH_BOOT[31:16]
BOOT_ADD1[15:0]
Default factory value 0x1FF0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_BOOT[15:0]
BOOT_ADD0[15:0]
Default factory value 0x0800

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FLASH_PRAR_x1[31:16]
DMEP1

Res.

Res.

Res.

PROT_AREA_END1

Default factory value 0 0 0 0 0x000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_PRAR_x1[15:0]
Res.

Res.

Res.

Res.

PROT_AREA_START1

Default factory value 0 0 0 0 0x0FF

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Table 21. Option byte organization (continued)

Register Bitfield

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FLASH_PRAR_x2[31:16]

DMEP2

Res.

Res.

Res.
PROT_AREA_END2

Default factory value 0 0 0 0 0x000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_PRAR_x2[15:0]
Res.

Res.

Res.

Res.
PROT_AREA_START2

Default factory value 0 0 0 0 0x0FF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FLASH_SCAR_x1[31:16]
DMES1

Res.

Res.

Res.

SEC_AREA_END1

Default factory value 1 0 0 0 0x000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_SCAR_x1[15:0]
Res.

Res.

Res.

Res.

SEC_AREA_START1

Default factory value 0 0 0 0 0x0FF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FLASH_SCAR_x2[31:16]
DMES2

Res.

Res.

Res.

SEC_AREA_END2

Default factory value 1 0 0 0 0x000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_SCAR_x2[15:0]
Res.

Res.

Res.

Res.

SEC_AREA_START2

Default factory value 0 0 0 0 0x0FF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASH_WPSN_x1[31:16]
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Default factory value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_WPSN_x1[15:0]
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

WRPSn1[7:0]

Default factory value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASH_WPSN_x2[31:16]
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

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Table 21. Option byte organization (continued)

Register Bitfield

Default factory value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_WPSN_x2[15:0]

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
WRPSn2[7:0]

Default factory value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

4.4.5 Description of user and system option bytes

Below the list of the general-purpose option bytes that can be used by the application:
• Watchdog management
– IWDG_FZ_STOP: independent watchdog (IWDG1) counter active in Stop mode if
1 (stop counting or freeze if 0)
– IWDG_FZ_SDBY: independent watchdog (IWDG1) counter active in Standby
mode if 1 (stop counting or freeze if 0)
– IWDG1_SW: hardware (0) or software (1) IWDG1 watchdog control selection
Note: If the hardware watchdog “control selection” feature is enabled (set to 0), the watchdog is
automatically enabled at power-on, thus generating a reset unless the watchdog key
register is written to or the down-counter is reloaded before the end-of-count is reached.
Depending on the configuration of IWDG_STOP and IWDG_STBY options, the IWDG can
continue counting (1) or not (0) when the device is in Stop or Standby mode, respectively.
When the IWDG is kept running during Stop or Standby mode, it can wake up the device
from these modes.
• Reset management
– BOR: Brownout level option, indicating the supply level threshold that
activates/releases the reset (see Section 6.5.2: Brownout reset (BOR))
– NRST_STDBY_D1/2: generates a reset when D1 (respectively D2) domain enters
DStandby mode. It is active low.
– NRST_STOP_D1/2: generates a reset when D1 (respectively D2) domain enters
DStop mode. It is active low.
Note: Whenever a Standby (respectively Stop) mode entry sequence is successfully executed, the
device is reset instead of entering Standby (respectively Stop) mode if NRST_STDBY
(respectively NRST_STOP) is cleared to 0.
• Bank swapping (see Section 4.3.13 on page 170)
SWAP_BANK_OPT: bank swapping option, set to 1 to swap user sectors and registers
after boot.
• Device options
– IO_HSLV: I/O speed optimization at low-voltage if set to 1.

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When STMicroelectronics delivers the device, the values programmed in the general-
purpose option bytes are the following:
• Watchdog management
– IWDG1 active in Standby and Stop modes (option byte value = 0x1)
– IWDG1 not automatically enabled at power-on (option byte value = 0x1)
• Reset management:
– BOR: brownout level option (reset level) equals brownout reset threshold 0 (option
byte value = 0x0)
– A reset is not generated when D1 or D2 domain enters DStandby or DStop low-
power mode (option byte value = 0x1)
• No bank swapping (option byte value = 0x0)
• Device working in the full voltage range with I/O speed optimization at low-voltage
disabled (IO_HSLV=0)
Refer to Section 4.9: FLASH registers for details.

4.4.6 Description of data protection option bytes

Below the list of the option bytes that can be used to enhance data protection:
• RDP[7:0]: Readout protection level (see Section 4.5.3 on page 184 for details).
• WRPSn1/2: write protection option of the corresponding Bank 1 (respectively Bank 2)
sector. It is active low. Refer to Section 4.5.4 on page 189 for details.
• PROT_AREAx: Proprietary code readout protection (refer to Section 4.5.4 on page 189
for details)
– PROT_AREA_START1 (respectively PROT_AREA_END1) contains the first
(respectively last) 256-byte block of the PCROP zone in Bank 1
– PROT_AREA_START2 (respectively PROT_AREA_END2) contains the first
(respectively last) 256-byte block of the PCROP zone in Bank 2
– DMEP1/2: when set to 1, the PCROP area in Bank 1 (respectively Bank 2) is
erased during a RDP protection level regression (change from level 1 to 0) or a
bank erase with protection removal.
• SEC_AREAx: secure access only zones definition (refer to Section 4.5.5 on page 190
for details).
– SEC_AREA_START1 (respectively SEC_AREA_END1) contains the first
(respectively last) 256-byte block of the secure access only zone in Bank 1
– SEC_AREA_START2 (respectively SEC_AREA_END2) contains the first
(respectively last) 256-byte block of the secure access only zone in Bank 2
– DMES1/2: when set to 1 the secure access only zone in Bank 1 (respectively
Bank 2) is erased during a RDP protection level regression (change from level 1 to
0), or a bank erase with protection removal.
• SECURITY: this non-volatile option can be used by the application to manage secure
access mode, as described in Section 4.5.5.
• ST_RAM_SIZE: this non-volatile option defines the amount of DTCM RAM root secure
services (RSS) can use during execution when the SECURITY bit is set. The DTCM
RAM is always fully available for the application whatever the option byte configuration.

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When STMicroelectronics delivers the device, the values programmed in the data protection
option bytes are the following:
• RDP level 0 (option byte value = 0xAA)
• Flash bank erase operations impact secure-only data areas when enabled by the
application (DMES1/2=1). They doe not impact PCROP data areas (DMEP1/2=0).
• PCROP and secure-only zone protections disabled (start addresses higher than end
addresses)
• Write protection enabled (all option byte bits set to 1)
• Secure access mode disabled (SECURITY option byte value = 0)
• RSS can use the DTCM RAM for executing its services (ST_RAM_SIZE)
Refer to Section 4.9: FLASH registers for details.

4.4.7 Description of boot address option bytes

Below the list of option bytes that can be used to configure the appropriate boot address for
your application:
• BOOT_ADD0/1: MSB of the Arm® Cortex®-M7 boot address when BOOT pin is low
(respectively high)
When STMicroelectronics delivers the device, the values programmed in the boot address
option bytes are the following:
• Arm® Cortex®-M7 boot address (MSB): 0x0800 (BOOT pin low for user flash memory)
and 0x1FF0 (BOOT pin high for System flash memory)
Refer to Section 4.9: FLASH registers for details.

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4.5 FLASH protection mechanisms

Since sensitive information can be stored in the flash memory, it is important to protect it
against unwanted operations such as reading confidential areas, illegal programming of
protected area, or illegal flash memory erasing.
The embedded flash memory implements the following protection mechanisms that can be
used by end-user applications to manage the security of embedded non-volatile storage:
• Configuration protection
• Global device Readout protection (RDP)
• Write protection
• Proprietary code readout protection (PCROP)
• Secure access mode areas
This section provides a detailed description of all these security mechanisms.

4.5.1 FLASH configuration protection

The embedded flash memory uses hardware mechanisms to protect the following assets
against unwanted or spurious modifications (e.g. software bugs):
• Option bytes change
• Write operations
• Erase commands
• Interrupt masking
More specifically, write operations to embedded flash memory control registers
(FLASH_CR1/2 and FLASH_OPTCR) are not allowed after reset.
The following sequence must be used to unlock FLASH_CR1/2 register:
1. Program KEY1 to 0x45670123 in FLASH_KEYR1/2 key register.
2. Program KEY2 to 0xCDEF89AB in FLASH_KEYR1/2 key register.
3. LOCK1/2 bit is now cleared and FLASH_CR1/2 is unlocked.
The following sequence must be used to unlock FLASH_OPTCR register:
1. Program OPTKEY1 to 0x08192A3B in FLASH_OPTKEYR option key register.
2. Program OPTKEY2 to 0x4C5D6E7F in FLASH_OPTKEYR option key register.
3. OPTLOCK bit is now cleared and FLASH_OPTCR register is unlocked.
Any wrong sequence locks up the corresponding register/bit until the next system reset, and
generates a bus error.
The FLASH_CR1/2 (respectively FLASH_OPTCR) register can be locked again by software
by setting the LOCK1/2 bit in FLASH_CR1/2 register (respectively OPTLOCK bit in
FLASH_OPTCR register).
In addition the FLASH_CR1/2 register remains locked and a bus error is generated when
the following operations are executed:
• programming a third key value
• writing to a different register belonging to the same bank than FLASH_KEYR1/2 before
FLASH_CR1/2 has been completely unlocked (KEY1 programmed but KEY2 not yet
programmed)
• writing less than 32 bits to KEY1 or KEY2.

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Similarly the FLASH_OPTCR register remains locked and a bus error is generated when
the following operations are executed:
• programming a third key value
• writing to a different register before FLASH_OPTCR has been completely unlocked
(OPTKEY1 programmed but OPTKEY2 not yet programmed)
• writing less than 32 bits to OPTKEY1 or OPTKEY2.
The embedded flash memory configuration registers protection is summarized in Table 22.

Table 22. Flash interface register protection summary

Register name Unlocking register Protected asset

FLASH_ACR N/A -
FLASH_KEYR1/2 N/A -
FLASH_OPTKEYR N/A -
Write operations
FLASH_CR1/2 FLASH_KEYR1/2 Erase commands
Interrupt generation masking sources
FLASH_SR1/2 N/A -
FLASH_CCR1/2 N/A -
Option bytes change
FLASH_OPTCR FLASH_OPTKEYR
Mass erase
Option bytes change. See Section 4.4.3:
FLASH_OPTSR_PRG FLASH_OPTCR
Option byte modification for details.
FLASH_OPTCCR N/A -
Option bytes (PCROP). See
FLASH_PRAR_PRG1/2 FLASH_OPTCR Section 4.4.3: Option byte modification
for details.
Option bytes (security). See
FLASH_SCAR_PRG1/2 FLASH_OPTCR Section 4.4.3: Option byte modification
for details.
FLASH_WPSGN_PRG1/2 FLASH_OPTCR Option bytes (write protection)
FLASH_BOOT_PRGR FLASH_OPTCR Option bytes (boot)
FLASH_CRCCR1/2 -
FLASH_CRCSADD1/2R -
N/A
FLASH_CRCEADD1/2R -
FLASH_CRCDATAR -
FLASH_ECC_FA1/2R N/A -

4.5.2 Write protection

The purpose of embedded flash memory write protection is to protect the embedded flash
memory against unwanted modifications of the non-volatile code and/or data.

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Any 128-Kbyte flash sector can be independently write-protected or unprotected by

clearing/setting the corresponding WRPSn1/2 bit in the FLASH_WPSN_PRG1/2R register.
A write-protected sector can neither be erased nor programmed. As a result, a bank erase
cannot be performed if one sector is write-protected, unless a bank erase is executed during
an RDP level 1 to 0 regression (see Section : Flash bank erase with automatic protection-
removal sequence for details).
The embedded flash memory write-protection user option bits can be modified without any
restriction when the RDP level is set to level 0 or level 1. When it is set to level 2, the write
protection bitfield can no more be changed in the option bytes.
Note: PCROP or secure-only areas are write and erase protected.
Write protection errors are documented in Section 4.7: FLASH error management.

4.5.3 Readout protection (RDP)

The embedded flash memory readout protection is global as it does not apply only to the
embedded flash memory, but also to the other secured regions. This is done by using
dedicated security signals.
In this section other secured regions are defined as:
• Backup SRAM
• RTC backup registers
The global readout protection level is set by writing the values given in Table 23 into the
readout protection (RDP) option byte (see Section 4.4.3: Option byte modification).

Table 23. RDP value vs readout protection level

RDP option byte value Global readout protection level

0xAA Level 0
0xCC Level 2
Any other value Level 1(1)
1. Default protection level when RDP option byte is erased.

Definitions of RDP global protection level

RDP Level 0 (no protection)
When the global read protection level 0 is set, all read/program/erase operations from/to the
user flash memory are allowed (if no others protections are set). This is true whatever the
boot configuration (boot from user or system flash memory, boot from RAM), and whether
the debugger is connected to the device or not. Accesses to the other secured regions are
also allowed.
RDP Level 1 (flash memory content protection)
When the global read protection level 1 is set, the below properties apply:
• The flash memory content is protected against debugger and potential malicious code
stored in RAM. Hence as soon as any debugger is connected or has been connected,

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or a boot is configured in embedded RAM (intrusion), the embedded flash memory

prevents any accesses to flash memory.
• When no intrusion is detected (no boot in RAM, no boot in System flash memory and
no debugger connected), all read/program/erase operations from/to the user flash
memory are allowed (if no others protections are set). Accesses to the other secured
regions are also allowed.
• When an intrusion is detected, no accesses to the user flash memory can be
performed. A bus error is generated when a read access is requested to the flash
memory. In addition, no accesses to other secured regions (read or write) can be
performed.
• When performing an RDP level regression, i.e. programming the RDP protection to
level 0, the user flash memory and the other secured regions are erased, as described
in RDP protection transitions.
• When booting on STM32 bootloader in standard system memory, only the identification
services are available (GET_ID_COMMAND, GET_VER_COMMAND and
GET_CMD_COMMAND).
• When booting from STMicroelectronics non-secure bootloader, only the identification
services are available (GET_ID_COMMAND, GET_VER_COMMAND and
GET_CMD_COMMAND).
RDP Level 2 (device protection and intrusion prevention)
When the global read protection level 2 is set, the below rules apply:
• All debugging features are disabled.
• Like level 0, all read/write/erase operations from/to the user flash memory are allowed
since the debugger and the boot from RAM and System flash memory are disabled.
Accesses to the other secured regions are also allowed.
• Booting from RAM is no more allowed.
• The user option bits described in Section 4.4 can no longer be changed except for the
SWAP bit.
Caution: Memory read protection level 2 is an irreversible operation. When level 2 is activated, the
level of protection cannot be changed back to level 0 or level 1.
Note: The JTAG port is permanently disabled when level 2 is active (acting as a JTAG fuse). As a
consequence. STMicroelectronics is not able to perform analysis on defective parts on
which the level 2 protection has been set.
Apply a power-on reset if the global read protection level 2 is set while the debugger is still
connected.
The above RDP global protection is summarized in Table 24.

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Table 24. Protection vs RDP Level(1)

Inputs Effects

Boot System
User flash Other Option Comment
area Debugger flash
RDP memory secured Bytes
connected memory
access(2) regions(4)
access
access (3)

Level 0 Yes(5)/No R/W/E R R/W R/W

illegal
User Level 1 Yes(3) R no access R/W
access(6)
flash -
memory Level 1 No R/W/E R R/W R/W

Level 2 No R/W/E R R/W R

Level 0 Yes(3)/No R/W/E R R/W R/W -

RAM or
System illegal When selected, only ST basic
Level 1 Yes(3)/No R no access R/W
flash access(6) bootloader is executed
memory No boot from RAM or ST system
Level 2 No Not applicable
flash memory in RDP level 2
1. R = read, W =write, E = erase.
2. PCROP (see Section 4.5.4) and secure-only access control (see Section 4.5.5) applies.
3. Read accesses to secure boot and secure libraries stored in system flash bank 1 possible only from STMicroelectronics
code.
4. The “other secured regions” are defined at the beginning of this section.
5. JTAG interface disabled while secure libraries are executed.
6. Read protection error (RDPERR) with bus error on read operations, Write protection error (WRPERR) on write/erase
operations.

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RDP protection transitions

Figure 13 shows how to switch from one RDP level to another. The transition is effective
after successfully writing the option bytes including RDP (refer to Section 4.4.3 for details on
how to change the option bytes).

Figure 13. RDP protection transition scheme

RDP Level 0
full debug, no
intrusion

RDP Level 1
RDP Level 2
full debug, intrusion
no debug
detection

Legend:

RDP increase (+option modification allowed)

RDP regression (+option modification allowed)
RDP unchanged (+option modification allowed)
RDP unchanged (+only SWAP_BANK option modification allowed)

MSv46187V1

Table 25 details the RDP transitions and their effects on the product.

Table 25. RDP transition and its effects

RDP transition Effect on device
RDP option update
Level before Level after Debugger Option bytes Partial/Mass
change change disconnect change (1) erase

L1 not 0xAA and not 0xCC No Allowed No

L0
L2 0xCC Yes Not allowed No

L2 0xCC Yes Not allowed No

L1
L0 0xAA No Allowed Yes

L0 L0 0xAA
No Allowed No
L1 L1 not 0xAA and not 0xCC

1. Except for bank swapping option bit.

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When the current RDP level is RDP level 1, requesting a new RDP level 0 can cause a full
or partial erase:
• The user flash memory area of the embedded flash memory is fully or partially erased:
– A partial sector erase occurs if PCROP (respectively secure-only) areas are
preserved by the application. It happens when both DMEP1/2 bits (respectively
DMES1/2 bits) are cleared to 0 in FLASH_PRAR_CUR1/2 and
FLASH_PRAR_PRG1/2 (respectively FLASH_SCAR_CUR1/2 and
FLASH_SCAR_PRG1/2). The sectors belonging to the preserved area(s) are not
erased.
– A full bank erase occurs when at least one DMEP1/2 bit is set to 1 in
FLASH_PRAR_CUR1/2 or FLASH_PRAR_PRG1/2, and at least one DMES1/2 bit
is set to 1 in FLASH_SCAR_CUR1/2 or FLASH_SCAR_PRG1/2.
Note: Data in write protection area are not preserved during RDP regression.
• The other secured regions are also erased (Backup SRAM and RTC backup registers)
During a level regression, if a PCROP area overlaps with a secure-only area, the embedded
flash memory performs the erase operation depending on the DMES/DMEP options bits
(see strike-through areas in red in Figure 14). More specifically:
• When DMEP is set in FLASH_PRAR_CUR1/2 or FLASH_PRAR_PRG1/2, the PCROP
area is erased (overlapped or not with secure-only area).
• When DMES is set in FLASH_SCAR_CUR1/2 or FLASH_SCAR_PRG1/2, the secure-
only area is erased (overlapped or not with PCROP area).
Note: The sector protections (PCROP, secure-only) are removed only if the protected sector
boundaries are modified by the user application.

Figure 14. Example of protected region overlapping

Case (A) Case (B)

... ...
Sector 7 Sector 7
SEC_AREA_END
Sector 6 Sector 6
Sector 5 PROT_AREA_END Sector 5
Sector 4 Sector 4
SEC_AREA_START Sector 3
Sector 3 PROT_AREA_START
Sector 2 Sector 2
Sector 1 Sector 1
Sector 0 Sector 0

DMEP = 1 and DMES = 0 DMEP = 0 and DMES = 1

Legend:
secure access only
execute only, no data access (PCROP)
MSv46188V2

About RDP protection errors

Whatever the RDP level, the corresponding error flag is raised when an illegal read or write
access is detected (see Section 4.7: FLASH error management).

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4.5.4 Proprietary code readout protection (PCROP)

The embedded flash memory allows the definition of an “executable-only” area in the user
area of each flash memory bank. In this area, only instruction fetch transactions from the
system, that is no data access (data or literal pool), are allowed. This protection is
particularly efficient to protect third party software intellectual property.
Note: Executable-only area usage requires the native code to be compiled accordingly using
“execute-only” option.

PCROP area programming

One PCROP area can be defined in bank 1 (respectively bank 2) by setting the
PROT_AREA_END1 and PROT_AREA_START1 (respectively PROT_AREA_END2 and
PROT_AREA_START2) option bytes so that the END address is strictly higher than the
START address. PROT_AREA_START and PROT_AREA_END are defined with a
granularity of 256 bytes. This means that the actual PCROP area size (in bytes) is defined
by:
[(PROT_AREA_END - PROT_AREA_START) + 1] x 256
As an example, to set a PCROP area on the first 4 Kbytes of user bank 1 (i.e. from address
0x0800 0000 to address 0x0800 0FFF, both included), the embedded flash memory must be
configured as follows:
• PROT_AREA_START1[11:0] = 0x000
• PROT_AREA_END1[11:0] = 0x00F
The protected area size defined above is equal to:
[(PROT_AREA_END - PROT_AREA_START) + 1] x 256 = 16 x 256 bytes = 4 Kbytes.
The minimum execute-only PCROP area that can be set is 16 flash words (or 512 bytes).
The maximum area is the whole user flash memory, configured by setting to the same value
the PCROP area START and END addresses.
Note: It is recommended to align the PCROP area size with the flash sector granularity in order to
avoid access right issues.

PCROP area properties

Each valid PCROP area has the following properties:
• Arm® Cortex®-M7 debug events are ignored while executing code in this area.
• Only the CPU can access it (Master ID filtering), using only instruction fetch
transactions. In all other cases, accessing the PCROP area is illegal (see below).
• Illegal transactions to a PCROP area (i.e. data read or write, not fetch) are managed as
below:
– Read operations return a zero, write operations are ignored.
– No bus error is generated but an error flag is raised (RDPERR for read, WRPERR
for write).
• A valid PCROP area is erase-protected. As a result:
– No erase operations to a sector located in this area is possible (including the
sector containing the area start address and the end address)

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– No mass erase can be performed if a single valid PCROP area is defined, except
during level regression or erase with protection removal.
• Only the CPU can modify the PCROP area definition and DMEP1/2 bits, as explained
in Changing user option bytes in Section 4.4.3.
• During an RDP level 1 to 0 regression where the PCROP area is not null
– The PCROP area content is not erased if the corresponding DMEP1/2 bit are both
cleared to 0 in FLASH_PRAR_CUR1/2 and FLASH_PRAR_PRG1/2 registers.
– The PCROP area content is erased if either of the corresponding DMEP1/2 bit is
set to 1 in FLASH_PRAR_CUR1/2 or FLASH_PRAR_PRG1/2 register.
For more information on PCROP protection errors, refer to Section 4.7: FLASH error
management.

4.5.5 Secure access mode

The embedded flash memory allows the definition of a secure-only area in the user area of
each flash memory bank. This area can be accessed only while the CPU executes secure
application code. This feature is available only if the SECURITY option bit is set to 1.
Secure-only areas help isolating secure user code from application non-secure code. As an
example, they can be used to protect a customer secure firmware upgrade code, a custom
secure boot library or a third party secure library.

Secure-only area programming

One secure-only area can be defined in bank 1 (respectively bank 2) by setting the
SEC_AREA_END1 and SEC_AREA_START1 (respectively SEC_AREA_END2 and
SEC_AREA_START2) option bytes so that the END address is strictly higher than the
START address. SEC_AREA_START and SEC_AREA_END are defined with a granularity
of 256 bytes. This means that the actual secure-only area size (in bytes) is defined by:
[(SEC_AREA_END - SEC_AREA_START) + 1] x 256
As an example, to set a secure-only area on the first 8 Kbytes of user bank 2 (i.e. from
address 0x0810 0000 to address 0x0810 1FFF, both included), the embedded flash memory
must be configured as follows:
• SEC_AREA_START2[11:0] = 0x000
• SEC_AREA_END2[11:0] = 0x01F
The secure-only area size defined above is equal to:
[(SEC_AREA_END - SEC_AREA_START) + 1] x 256 = 32 x 256 bytes = 8 Kbytes.
Note: These option bytes can be modified only by the CPU running ST security library or
application secure code, except during RDP level regression or erase with protection
removal.
The minimum secure-only area that can be set is 16 flash words (or 512 bytes). The
maximum area is the whole user flash memory bank, configured by setting to the same
value the secure-only area START and END addresses.
Note: It is recommended to align the secure-only area size with flash sector granularity in order to
avoid access right issues.

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Secure access-only area properties

• Arm® Cortex®-M7 debug events are ignored while executing code in this area.
• Only the CPU executing ST secure library or user secure application can access it
(Master ID filtering). In all other cases, accessing the secure-only area is illegal (see
below).
• Illegal transactions to a secure-only area are managed as follows:
– Data read transactions return zero. Data write transactions are ignored. No bus
error is generated but an error flag is raised (RDSERR for read, WRPERR for
write).
– Read instruction transactions generate a bus error and the RDSERR error flag is
raised.
• A valid secure-only area is erase-protected. As a result:
– No erase operations to a sector located in this area are possible (including the
sector containing the area start address and the end address), unless the
application software is executed from a valid secure-only area.
– No mass erase can be performed if a single valid secure-only area is defined,
except during level regression, erase with protection removal or when the
application software is executed from a valid secure-only area.
• Only the CPU can modify the secure-only area definition and DMES1/2 bits, as
explained in Changing user option bytes in Section 4.4.3.
• During an RDP level 1 to 0 regression where the secure-only area is not null:
– the secure-only area content is not erased if the corresponding DMES1/2 bit are
both cleared to 0 in FLASH_SCAR_CUR1/2 and FLASH_SCAR_PRG1/2
registers.
– the secure-only area content is erased if either of the corresponding DMES1/2 bit
is set to 1 in FLASH_SCAR_CUR1/2 or FLASH_SCAR_PRG1/2 register.
For more information on secure-only protection errors, refer to Section 4.7: FLASH error
management.

4.6 FLASH low-power modes

4.6.1 Introduction
The table below summarizes the behavior of the embedded flash memory in the
microcontroller low-power modes. The embedded flash memory belongs to the D1 domain.

Table 26. Effect of low-power modes on the embedded flash memory

Power mode
FLASH power
D1 domain Allowed if
mode (in D1
System voltage range FLASH busy
D1 domain D2 domain domain)
state

DRun,
DRun DStop or VOS1/2/3 Yes Run
Run DStandby
DStop, DStop or
Off No Off
DStandby DStandby

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Table 26. Effect of low-power modes on the embedded flash memory (continued)
Power mode
FLASH power
D1 domain Allowed if
mode (in D1
System voltage range FLASH busy
D1 domain D2 domain domain)
state

DStop or Clock gated or

DStop SVOS3/4/5 No
DStandby Stopped
Stop
DStop or
DStandby No
DStandby Off Off
Standby(1) DStandby DStandby No
1. D3 domain must always be in DStandby mode. When all clocks are stopped and the CPU is in CStop, the
VCORE domain is switched off.

When the system state changes or within a given system state, the embedded flash
memory might get a different voltage supply range (VOS) according to the application. The
procedure to switch the embedded flash memory into various power mode (run, clock gated,
stopped, off) is described hereafter.
Note: For more information in the microcontroller power states, refer to the Power control section
(PWR).

4.6.2 Managing the FLASH domain switching to DStop or DStandby

As explain in Table 26, if the embedded flash memory informs the reset and clock controller
(RCC) that it is busy (i.e. BSY1/2, QW1/2, WBNE1/2 is set), the microcontroller cannot
switch the D1 domain to DStop or DStandby mode.
Note: CRC_BUSY1/2 is not taken into account.
There are two ways to release the embedded flash memory:
• Reset the WBNE1/2 busy flag in FLASH_SR1/2 register by any of the following actions:
a) Complete the write buffer with missing data.
b) Force the write operation without filling the missing data by activating the FW1/2
bit in FLASH_CR1/2 register. This forces all missing data “high”.
c) Reset the PG1/2 bit in FLASH_CR1/2 register. This disables the write buffer and
consequently lead to the loss of its content.
• Poll QW1/2 busy bits in FLASH_SR1/2 register until they are cleared. This will indicate
that all recorded write, erase and option change operations are complete.
The microcontroller can then switch the domain to DStop or DStandby mode.

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4.7 FLASH error management

4.7.1 Introduction
The embedded flash memory automatically reports when an error occurs during a read,
program or erase operation. A wide range of errors are reported:
• Write protection error (WRPERR)
• Programming sequence error (PGSERR)
• Strobe error (STRBERR)
• Inconsistency error (INCERR)
• Operation error (OPERR)
• Error correction code error (SNECCERR/DBECCERR)
• Read protection error (RDPERR)
• Read secure error (RDSERR)
• Option byte change error (OPTCHANGEERR)
The application software can individually enable the interrupt for each error, as detailed in
Section 4.8: FLASH interrupts.
Note: For some errors, the application software must clear the error flag before attempting a new
operation.
Each bank has a dedicated set of error flags in order to identify which bank generated the
error. They are available in flash Status register 1 or 2 (FLASH_SR1/2).

4.7.2 Write protection error (WRPERR)

When an illegal erase/program operation is attempted to the non-volatile memory bank 1
(respectively bank 2), the embedded flash memory sets the write protection error flag
WRPERR1 (respectively WRPERR2) in FLASH_SR1 register (respectively FLASH_SR2).
An erase operation is rejected and flagged as illegal if it targets one of the following memory
areas:
• A sector belonging to a valid PCROP area (even partially)
• A sector belonging to a valid secure-only area (even partially) except if the application
software is executed from a valid secure-only area
• A sector write-locked with WRPSn

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An program operation is ignored and flagged as illegal if it targets one of the following
memory areas:
• The system flash memory (bank 2 only) while the device is not executing ST
bootloader code
• A user flash sector belonging to a valid PCROP area while the device is not executing
an ST secure library
• A user flash sector belonging to a valid secure-only area while the device is not
executing user secure code or ST secure library
• A user sector write-locked with WRPSn
• The bank 1 system flash memory
• The user main flash memory when RDP level is 1 and a debugger has been detected
on the device, or the CPU has not booted from user flash memory.
• A reserved area
When WRPERR1/2 flag is raised, the operation is rejected and nothing is changed in the
corresponding bank. If a write burst operation was ongoing, WRPERR1/2 is raised each
time a flash word write operation is processed by the embedded flash memory.
Note: WRPERR1/2 flag does not block any new erase/program operation.
Not resetting the write protection error flag (WRPERR1/2) does not generate a PGSERR
error.
WRPERR1/2 flag is cleared by setting CLR_WRPERR1/2 bit to 1 in FLASH_CCR1/2
register.
If WRPERRIE1/2 bit in FLASH_CR1/2 register is set to 1, an interrupt is generated when
WRPERR1/2 flag is raised (see Section 4.8: FLASH interrupts for details).

4.7.3 Programming sequence error (PGSERR)

When the programming sequence to the bank 1 (respectively bank 2) is incorrect, the
embedded flash memory sets the programming sequence error flag PGSERR1
(respectively PGSERR2) in FLASH_SR1 register (respectively FLASH_SR2).
More specifically, PGSERR1/2 flag is set if one of below conditions is met:
• A write operation is requested but the program enable bit (PG1/2) has not been set in
FLASH_CR1/2 register prior to the request.
• The inconsistency error (INCERR1/2) has not been cleared to 0 before requesting a
new write operation.
When PGSERR1/2 flag is raised, the current program operation is aborted and nothing is
changed in the corresponding bank. The corresponding write data buffer is also flushed. If a
write burst operation was ongoing, PGSERR1/2 is raised at the end of the burst.
Note: When PGSERR1/2 flag is raised, there is a risk that the last write operation performed by
the application has been lost because of the above protection mechanism. Hence it is
recommended to generate interrupts on PGSERR and verify in the interrupt handler if the
last write operation has been successful by reading back the value in the flash memory.
The PGSERR1/2 flag also blocks any new program operation. This means that PGSERR1
(respectively 2) must be cleared before starting a new program operation on bank 1
(respectively bank 2).

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PGSERR1/2 flag is cleared by setting CLR_PGSERR1/2 bit to 1 in FLASH_CCR1/2

register.
If PGSERRIE1/2 bit in FLASH_CR1/2 register is set to 1, an interrupt is generated when
PGSERR1/2 flag is raised. See Section 4.8: FLASH interrupts for details.

4.7.4 Strobe error (STRBERR)

When the application software writes several times to the same byte in bank 1 (respectively
bank 2) write buffer, the embedded flash memory sets the strobe error flag STRBERR1
(respectively STRBERR2) in FLASH_SR1 register (respectively FLASH_SR2).
When STRBERR1/2 flag is raised, the current program operation is not aborted and new
byte data replace the old ones. The application can ignore the error, proceed with the
current write operation and request new write operations. If a write burst was ongoing,
STRBERR1/2 is raised at the end of the burst.
STRBERR1/2 flag is cleared by setting CLR_STRBERR1/2 bit to 1 in FLASH_CCR1/2
register.
If STRBERRIE1/2 bit in FLASH_CR1/2 register is set to 1, an interrupt is generated when
STRBERR1/2 flag is raised. See Section 4.8: FLASH interrupts for details.

4.7.5 Inconsistency error (INCERR)

When a programming inconsistency to bank 1 (respectively bank 2) is detected, the
embedded flash memory sets the inconsistency error flag INCERR1 (respectively
INCERR2) in register FLASH_SR1 (respectively FLASH_SR2).
More specifically, INCERR flag is set when one of the following conditions is met:
• A write operation is attempted before completion of the previous write operation, e.g.
– The application software starts a write operation to fill the 256-bit write buffer, but
sends a new write burst request to a different flash memory address before the
buffer is full.
– One master starts a write operation, but before the buffer is full, another master
starts a new write operation to the same address or to a different address.
• A wrap burst request issued by a master overlaps two or more 256-bit flash-word
addresses, i.e. wrap bursts must be done within 256-bit flash-word address
boundaries.
Note: INCERR flag must be cleared before starting a new write operation, otherwise a sequence
error (PGSERR) is raised.
It is recommended to follow the sequence below to avoid losing data when an inconsistency
error occurs:
1. Execute a handler routine when INCERR1 or INCERR2 flag is raised.
2. Stop all write requests to embedded flash memory.
3. Verify that the write operations that have been requested just before the INCERR event
have been successful by reading back the programmed values from the memory.
4. Clear the corresponding INCERR1/2 bit.
5. Restart the write operations where they have been interrupted.
INCERR1/2 flag is cleared by setting CLR_INCERR1/2 bit to 1 in FLASH_CCR1/2 register.

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If INCERRIE1/2 bit in FLASH_CR1/2 register is set to 1, an interrupt is generated when

INCERR1/2 flag is raised (see Section 4.8: FLASH interrupts for details).

4.7.6 Operation error (OPERR)

When an error occurred during a write or an erase operation to bank 1 (respectively bank 2),
the embedded flash memory sets the operation error flag OPERR1 (respectively OPERR2)
in FLASH_SR1 register (respectively FLASH_SR2). This error may be caused by an
incorrect non-volatile memory behavior due to cycling issues or to a previous modify
operation stopped by a system reset.
When OPERR1/2 flag is raised, the current program/erase operation is aborted.
OPERR1/2 flag is cleared by setting CLR_OPERR1/2 bit to 1 in FLASH_CCR1/2 register.
If OPERRIE1/2 bit in FLASH_CR1/2 register is set to 1, an interrupt is generated when
OPERR1/2 flag is raised (see Section 4.8: FLASH interrupts for details).

4.7.7 Error correction code error (SNECCERR/DBECCERR)

When a single error correction is detected during a read from bank 1 (respectively bank 2)
the embedded flash memory sets the single error correction flag SNECCERR1 (respectively
SNECCERR2) in FLASH_SR1 register (respectively FLASH_SR2).
When two ECC errors are detected during a read to bank 1 (respectively bank 2), the
embedded flash memory sets the double error detection flag DBECCERR1 (respectively
DBECCERR2) in FLASH_SR1 register (respectively FLASH_SR2). When SNECCERR1/2
flag is raised, the corrected read data are returned. Hence the application can ignore the
error and request new read operations.
If a read burst operation was ongoing, SNECCERR1/2 or DBECCERR1/2 flag is raised
each time a new data is sent back to the requester through the AXI interface.
When SNECCERR1/2 or DBECCERR1/2 flag is raised, the address of the flash word that
generated the error is saved in the FLASH_ECC_FA1/2R register.This register is
automatically cleared when the associated flag that generated the error is reset.
Note: In case of successive single correction or double detection errors, only the address
corresponding to the first error is stored in FLASH_ECC_FA1/2R register.
When DBECCERR1/2 flag is raised, a bus error is generated. In case of successive double
error detections, a bus error is generated each time a new data is sent back to the requester
through the AXI interface.
Note: It is not mandatory to clear SNECCERR1/2 or DBECCERR1/2 flags before starting a new
read operation.
SNECCERR1/2 (respectively DBECCERR1/2) flag is cleared by setting to 1
CLR_SNECCERR1/2 bit (respectively CLR_DBECCERR1/2 bit) in FLASH_CCR1/2
register.
If SNECCERR1/2 (respectively DBECCERR1/2) bit in FLASH_CR1/2 register is set to 1, an
interrupt is generated when SNECCERR1/2 (respectively DBECCERR1/2) flag is raised.
See Section 4.8: FLASH interrupts for details.

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4.7.8 Read protection error (RDPERR)

When a read operation to a PCROP, a secure-only or a RDP protected area is attempted in
non-volatile memory bank 1 (respectively bank 2), the embedded flash memory sets the
read protection error flag RDPERR1 (respectively RDPERR2) in FLASH_SR1 register
(respectively FLASH_SR2).
When RDPERR1/2 flag is raised, the current read operation is aborted but the application
can request new read operations. If a read burst was ongoing, RDPERR1/2 is raised each
time a data is sent back to the requester through the AXI interface.
Note: A bus error is raised if a standard application attempts to execute on a secure-only or a RDP
protected area.
RDPERR1/2 flag is cleared by setting CLR_RDPERR1/2 bit to 1 in FLASH_CCR1/2
register.
If RDPERRIE1/2 bit in FLASH_CR1/2 register is set to 1, an interrupt is generated when
RDPERR1/2 flag is raised (see Section 4.8: FLASH interrupts for details).

4.7.9 Read secure error (RDSERR)

When a read operation is attempted to a secure address in bank 1 (respectively bank 2), the
embedded flash memory sets the read secure error flag RDSERR1 (respectively
RDSERR2) in FLASH_SR1 register (respectively FLASH_SR2). For more information, refer
to Section 4.5.5: Secure access mode.
When RDSERR1/2 flag is raised, the current read operation is aborted and the application
can request new read operations. If a read burst was ongoing, RDSERR1/2 is raised each
time a data is sent back to the requester through the AXI interface.
Note: The bus error is raised only if the illegal access is due to an instruction fetch.
RDSERR1/2 flag is cleared by setting CLR_RDSERR1/2 bit to 1 in FLASH_CCR1/2
register.
If RDSERRIE1/2 bit in FLASH_CR1/2 register is set to 1, an interrupt is generated when
RDSERR1/2 flag is raised (see Section 4.8: FLASH interrupts for details).

4.7.10 CRC read error (CRCRDERR)

After a CRC computation in bank 1 (respectively bank 2), the embedded flash memory sets
the CRC read error flag CRCRDERR1 (respectively CRCRDERR2) in FLASH_SR1 register
(respectively FLASH_SR2) when one or more address belonging to a protected area was
read by the CRC module. A protected area corresponds to a PCROP area (see
Section 4.5.4) or to a secure-only area (see Section 4.5.5).
CRCRDERR1/2 flag is raised when CRCEND1/2 bit is set to 1 (end of CRC calculation). In
this case, it is likely that the CRC result is wrong since illegal read operations to protected
areas return null values.
CRCRDERR1/2 flag is cleared by setting CLR_CRCRDERR1/2 bit to 1 in FLASH_CCR1/2
register.
If CRCRDERRIE1/2 bit in FLASH_CR1/2 register is set to 1, an interrupt is generated when
CRCRDERR1/2 flag is raised together with CRCEND1/2 bit (see Section 4.8: FLASH
interrupts for details).

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4.7.11 Option byte change error (OPTCHANGEERR)

When the embedded flash memory finds an error during an option change operation, it
aborts the operation and sets the option byte change error flag OPTCHANGEERR in
FLASH_OPTSR_CUR register.
OPTCHANGEERR flag is cleared by setting CLR_OPTCHANGEERR bit to 1 in
FLASH_OPTCCR register.
If OPTCHANGEERRIE bit in FLASH_OPTCR register is set to 1, an interrupt is generated
when OPTCHANGEERR flag is raised (see Section 4.8: FLASH interrupts for details).

4.7.12 Miscellaneous HardFault errors

The following events generate a bus error on the corresponding bus interface:
• On AXI system bus:
– accesses to user flash memory while RDP is set to 1 and a illegal condition is
detected (boot from system flash memory, boot from RAM, or debugger
connected)
– fetching to secure-only user flash memory without the correct access rights
• On AHB configuration bus:
– wrong key input to FLASH_KEYR1/2 or FLASH_OPTKEYR

4.8 FLASH interrupts

The embedded flash memory can generate a maskable interrupt to signal the following
events on a given bank:
• Read and write errors (see Section 4.7: FLASH error management)
– Single ECC error correction during read operation
– Double ECC error detection during read operation
– Write inconsistency error
– Bad programming sequence
– Strobe error during write operations
– Non-volatile memory write/erase error (due to cycling issues)
– option change operation error
• Security errors (see Section 4.7: FLASH error management)
– Write protection error
– Read protection error
– Read secure error
– CRC computation on PCROP or secure-only area error
• Miscellaneous events (described below)
– End of programming
– CRC computation complete
These multiple sources are combined into a single interrupt signal, flash_it, which is the
only interrupt signal from the embedded flash memory that drives the NVIC (nested
vectored interrupt controller).

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You can individually enable or disable embedded flash memory interrupt sources by
changing the mask bits in the FLASH_CR1/2 register. Setting the appropriate mask bit to 1
enables the interrupt.
Note: Prior to writing, FLASH_CR1/2 register must be unlocked as explained in Section 4.5.1:
FLASH configuration protection
Table 27 gives a summary of the available embedded flash memory interrupt features. As
mentioned in the table below, some flags need to be cleared before a new operation is
triggered.

Table 27. Flash interrupt request

Clear flag
Bus
Interrupt event Event flag Enable control bit to resume
error
operation

on bank 1 EOP1 EOPIE1

End-of-program event N/A N/A
on bank 2 EOP2 EOPIE2
on bank 1 CRCEND1 CRCENDIE1
CRC complete event N/A N/A
on bank 2 CRCEND2 CRCENDIE2
on bank 1 WRPERR1 WRPERRIE1
Write protection error No No
on bank 2 WRPERR2 WRPERRIE2
on bank 1 PGSERR1 PGSERRIE1
Programming sequence error Yes(1) No
on bank 2 PGSERR2 PGSERRIE2
on bank 1 STRBERR1 STRBERRIE1
Strobe error No No
on bank 2 STRBERR2 STRBERRIE2
on bank 1 INCERR1 INCERRIE1
Inconsistency error Yes(1) No
on bank 2 INCERR2 INCERRIE2
on bank 1 OPERR1 OPERRIE1
Operation error No No
on bank 2 OPERR2 OPERRIE2

ECC single error correction on bank 1 SNECCERR1 SNECCERRIE1

No No
event on bank 2 SNECCERR2 SNECCERRIE2

ECC double error detection on bank 1 DBECCERR1 DBECCERRIE1

No Yes
event on bank 2 DBECCERR2 DBECCERRIE2
on bank 1 RDPERR1 RDPERRIE1
Read protection error No Yes(2)
on bank 2 RDPERR2 RDPERRIE2
on bank 1 RDSERR1 RDSERRIE1 No
(data)
Read secure error No
on bank 2 RDSERR2 RDSERRIE2 Yes
(fetch)
on bank 1 CRCRDERR1 CRCRDERRIE1
CRC read error No No
on bank 2 CRCRDERR2 CRCRDERRIE2
Option Bytes operation error all banks OPTCHANGEERR OPTCHANGEERRIE No No

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1. Programming still possible on the AXI interface that did not trigger the inconsistency error, on the flash bank that does not
have the flag bit raised. See Section 4.7.5: Inconsistency error (INCERR) for details.
2. Bus error occurs only when accessing RDP protected area, as defined in Section 4.5.3: Readout protection (RDP)

The status of the individual maskable interrupt sources described in Table 27 (except for
option byte error) can be read from the FLASH_SR1/2 register. They can be cleared by
setting to 1 the adequate bit in FLASH_CCR1/2 register.
Note: No unlocking mechanism is required to clear an interrupt.

End-of-program event
Setting the end-of-operation interrupt enable bit (EOPIE1/2) in the FLASH_CR1/2 register
enables the generation of an interrupt at the end of an erase operation, a program operation
or an option byte change on bank 1/2. The EOP1/2 bit in the FLASH_SR1/2 register is also
set when one of these events occurs.
Setting CLR_EOP1/2 bit to 1 in FLASH_CCR1/2 register clears EOP1/2 flag.

CRC end of calculation event

Setting the CRC end-of-calculation interrupt enable bit (CRCENDIE1/2) in the
FLASH_CR1/2 register enables the generation of an interrupt at the end of a CRC operation
on bank 1/2. The CRCEND1/2 bit in the FLASH_SR1/2 register is also set when this event
occurs.
Setting CLR_CRCEND1/2 bit to 1 in FLASH_CCR1/2 register clears CRCEND1/2 flag.

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4.9 FLASH registers

4.9.1 FLASH access control register (FLASH_ACR)

Address offset: 0x000 or 0x100
Reset value: 0x0000 0037
For more details, refer to Section 4.3.8: FLASH read operations and Section 4.3.9: FLASH
program operations.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRHIGHFREQ LATENCY

rw rw rw rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:4 WRHIGHFREQ: Flash signal delay
These bits are used to control the delay between non-volatile memory signals during
programming operations. The application software has to program them to the correct value
depending on the embedded flash memory interface frequency. Please refer to Table 17 for
details.
Note: No check is performed by hardware to verify that the configuration is correct.
Bits 3:0 LATENCY: Read latency
These bits are used to control the number of wait states used during read operations on both
non-volatile memory banks. The application software has to program them to the correct
value depending on the embedded flash memory interface frequency and voltage conditions.
0000: zero wait state used to read a word from non-volatile memory
0001: one wait state used to read a word from non-volatile memory
0010: two wait states used to read a word from non-volatile memory
...
0111: seven wait states used to read a word from non-volatile memory
Note: No check is performed by hardware to verify that the configuration is correct.

4.9.2 FLASH key register for bank 1 (FLASH_KEYR1)

Address offset: 0x004
Reset value: 0x0000 0000
FLASH_KEYR1 is a write-only register. The following values must be programmed
consecutively to unlock FLASH_CR1 register:
1. 1st key = 0x4567 0123
2. 2nd key = 0xCDEF 89AB

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

KEY1R

w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

KEY1R

w w w w w w w w w w w w w w w w

Bits 31:0 KEY1R: Non-volatile memory bank 1 configuration access unlock key

4.9.3 FLASH option key register (FLASH_OPTKEYR)

Address offset: 0x008 or 0x108
Reset value: 0x0000 0000
FLASH_OPTKEYR is a write-only register. The following values must be programmed
consecutively to unlock FLASH_OPTCR register:
1. 1st key = 0x0819 2A3B
2. 2nd key = 0x4C5D 6E7F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OPTKEYR

w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPTKEYR

w w w w w w w w w w w w w w w w

Bits 31:0 OPTKEYR: FLASH option bytes control access unlock key

4.9.4 FLASH control register for bank 1 (FLASH_CR1)

Address offset: 0x00C
Reset value: 0x0000 0031

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCRDERRIE1

DBECCERRIE1

SNECCERRIE1

STRBERRIE1

WRPERRIE1
CRCENDIE1

RDSERRIE1

RDPERRIE1

PGSERRIE1
INCERRIE1
OPERRIE1

EOPIE1

Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_EN

START1

PSIZE1

LOCK1
SNB1

BER1

SER1
FW1
Res.

PG1

Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rs

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Bits 31:29 Reserved, must be kept at reset value.

Bit 28 CRCRDERRIE1: Bank 1 CRC read error interrupt enable bit
When CRCRDERRIE1 bit is set to 1, an interrupt is generated when a protected area
(PCROP or secure-only) has been detected during the last CRC computation on bank 1.
CRCRDERRIE1 can be programmed only when LOCK1 is cleared to 0.
0: no interrupt generated when a CRC read error occurs on bank 1
1: interrupt generated when a CRC read error occurs on bank 1
Bit 27 CRCENDIE1: Bank 1 CRC end of calculation interrupt enable bit
When CRCENDIE1 bit is set to 1, an interrupt is generated when the CRC computation has
completed on bank 1. CRCENDIE1 can be programmed only when LOCK1 is cleared to 0.
0: no interrupt generated when CRC computation complete on bank 1
1: interrupt generated when CRC computation complete on bank 1
Bit 26 DBECCERRIE1: Bank 1 ECC double detection error interrupt enable bit
When DBECCERRIE1 bit is set to 1, an interrupt is generated when an ECC double
detection error occurs during a read operation from bank 1. DBECCERRIE1 can be
programmed only when LOCK1 is cleared to 0.
0: no interrupt generated when an ECC double detection error occurs on bank 1
1: interrupt generated if an ECC double detection error occurs on bank 1
Bit 25 SNECCERRIE1: Bank 1 ECC single correction error interrupt enable bit
When SNECCERRIE1 bit is set to 1, an interrupt is generated when an ECC single correction
error occurs during a read operation from bank 1. SNECCERRIE1 can be programmed only
when LOCK1 is cleared to 0.
0: no interrupt generated when an ECC single correction error occurs on bank 1
1: interrupt generated when an ECC single correction error occurs on bank 1
Bit 24 RDSERRIE1: Bank 1 secure error interrupt enable bit
When RDSERRIE1 bit is set to 1, an interrupt is generated when a secure error (access to a
secure-only protected address) occurs during a read operation from bank 1. RDSERRIE1
can be programmed only when LOCK1 is cleared to 0.
0: no interrupt generated when a secure error occurs on bank 1
1: an interrupt is generated when a secure error occurs on bank 1
Bit 23 RDPERRIE1: Bank 1 read protection error interrupt enable bit
When RDPERRIE1 bit is set to 1, an interrupt is generated when a read protection error
occurs (access to an address protected by PCROP or by RDP level 1) during a read
operation from bank 1. RDPERRIE1 can be programmed only when LOCK1 is cleared to 0.
0: no interrupt generated when a read protection error occurs on bank 1
1: an interrupt is generated when a read protection error occurs on bank 1
Bit 22 OPERRIE1: Bank 1 write/erase error interrupt enable bit
When OPERRIE1 bit is set to 1, an interrupt is generated when an error is detected during a
write/erase operation to bank 1. OPERRIE1 can be programmed only when LOCK1 is
cleared to 0.
0: no interrupt generated when a write/erase error occurs on bank 1
1: interrupt generated when a write/erase error occurs on bank 1
Bit 21 INCERRIE1: Bank 1 inconsistency error interrupt enable bit
When INCERRIE1 bit is set to 1, an interrupt is generated when an inconsistency error
occurs during a write operation to bank 1. INCERRIE1 can be programmed only when
LOCK1 is cleared to 0.
0: no interrupt generated when a inconsistency error occurs on bank 1
1: interrupt generated when a inconsistency error occurs on bank 1.

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Bit 20 Reserved, must be kept at reset value.

Bit 19 STRBERRIE1: Bank 1 strobe error interrupt enable bit
When STRBERRIE1 bit is set to 1, an interrupt is generated when a strobe error occurs (the
master programs several times the same byte in the write buffer) during a write operation to
bank 1. STRBERRIE1 can be programmed only when LOCK1 is cleared to 0.
0: no interrupt generated when a strobe error occurs on bank 1
1: interrupt generated when strobe error occurs on bank 1.
Bit 18 PGSERRIE1: Bank 1 programming sequence error interrupt enable bit
When PGSERRIE1 bit is set to 1, an interrupt is generated when a sequence error occurs
during a program operation to bank 1. PGSERRIE1 can be programmed only when LOCK1 is
cleared to 0.
0: no interrupt generated when a sequence error occurs on bank 1
1: interrupt generated when sequence error occurs on bank 1.
Bit 17 WRPERRIE1: Bank 1 write protection error interrupt enable bit
When WRPERRIE1 bit is set to 1, an interrupt is generated when a protection error occurs
during a program operation to bank 1. WRPERRIE1 can be programmed only when LOCK1
is cleared to 0.
0: no interrupt generated when a protection error occurs on bank 1
1: interrupt generated when a protection error occurs on bank 1.
Bit 16 EOPIE1: Bank 1 end-of-program interrupt control bit
Setting EOPIE1 bit to 1 enables the generation of an interrupt at the end of a program
operation to bank 1. EOPIE1 can be programmed only when LOCK1 is cleared to 0.
0: no interrupt generated at the end of a program operation to bank 1.
1: interrupt enabled when at the end of a program operation to bank 1.
Bit 15 CRC_EN: Bank 1 CRC control bit
Setting CRC_EN bit to 1 enables the CRC calculation on bank 1. CRC_EN does not start
CRC calculation but enables CRC configuration through FLASH_CRCCR1 register.
When CRC calculation is performed on bank 1, it can only be disabled by setting CRC_EN bit
to 0. Resetting CRC_EN clears CRC configuration and resets the content of
FLASH_CRCDATAR register.
Clearing CRC_EN to 0 sets CRCDATA to 0x0.
CRC_EN can be programmed only when LOCK1 is cleared to 0.
Bit 14 Reserved, must be kept at reset value.
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:8 SNB1: Bank 1 sector erase selection number
These bits are used to select the target sector for a sector erase operation (they are unused
otherwise). SNB1 can be programmed only when LOCK1 is cleared to 0.
000: sector 0 of bank 1
001: sector 1 of bank 1
...
111: sector 7 of bank 1

Bit 7 START1: Bank 1 erase start control bit

START1 bit is used to start a sector erase or a bank erase operation. START1 can be
programmed only when LOCK1 is cleared to 0.
The embedded flash memory resets START1 when the corresponding operation has been
acknowledged. The user application cannot access any embedded flash memory register
until the operation is acknowledged.

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RM0433 Embedded flash memory (FLASH)

Bit 6 FW1: Bank 1 write forcing control bit

FW1 forces a write operation even if the write buffer is not full. In this case all bits not written
are set to 1 by hardware. FW1 can be programmed only when LOCK1 is cleared to 0.
The embedded flash memory resets FW1 when the corresponding operation has been
acknowledged. The user application cannot access any embedded flash memory register
until the operation is acknowledged.
Note: Using a force-write operation prevents the application from updating later the missing
bits with something else than 1, because it is likely that it will lead to permanent ECC
error.
Write forcing is effective only if the write buffer is not empty (in particular, FW1 does not start
several write operations when the force-write operations are performed consecutively).
Bits 5:4 PSIZE1: Bank 1 program size
PSIZE1 selects the parallelism used by the non-volatile memory during write and erase
operations to bank 1. PSIZE1 can be programmed only when LOCK1 is cleared to 0.
00: programming executed with byte parallelism
01: programming executed with half-word parallelism
10: programming executed with word parallelism
11: programming executed with double word parallelism
Bit 3 BER1: Bank 1 erase request
Setting BER1 bit to 1 requests a bank erase operation on bank 1 (user flash memory only).
BER1 can be programmed only when LOCK1 is cleared to 0.
BER1 has a higher priority than SER1: if both are set, the embedded flash memory executes
a bank erase.
0: bank erase not requested on bank 1
1: bank erase requested on bank 1
Note: Write protection error is triggered when a bank erase is required and some sectors are
protected.

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Embedded flash memory (FLASH) RM0433

Bit 2 SER1: Bank 1 sector erase request

Setting SER1 bit to 1 requests a sector erase on bank 1. SER1 can be programmed only
when LOCK1 is cleared to 0.
BER1 has a higher priority than SER1: if both bits are set, the embedded flash memory
executes a bank erase.
0: sector erase not requested on bank 1
1: sector erase requested on bank 1
Note: Write protection error is triggered when a sector erase is required on a protected sector.
Bit 1 PG1: Bank 1 internal buffer control bit
Setting PG1 bit to 1 enables internal buffer for write operations to bank 1. This allows
preparing program operations even if a sector or bank erase is ongoing.
PG1 can be programmed only when LOCK1 is cleared to 0. When PG1 is reset, the internal
buffer is disabled for write operations to bank 1, and all the data stored in the buffer but not
sent to the operation queue are lost.
0: Internal buffer disabled for write operations to bank 1
1: Internal buffer enabled for write operations to bank 1
Bit 0 LOCK1: Bank 1 configuration lock bit
This bit locks the FLASH_CR1 register. The correct write sequence to FLASH_KEYR1
register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to
FLASH_KEYR1 is performed twice, this bit remains locked until the next system reset.
LOCK1 can be set by programming it to 1. When set to 1, a new unlock sequence is
mandatory to unlock it. When LOCK1 changes from 0 to 1, the other bits of FLASH_CR1
register do not change.
0: FLASH_CR1 register unlocked
1: FLASH_CR1 register locked

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RM0433 Embedded flash memory (FLASH)

4.9.5 FLASH status register for bank 1 (FLASH_SR1)

Address offset: 0x010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DBECCERR1

SNECCERR1

STRBERR1

WRPERR1
CRCEND1

RDSERR1

RDPERR1

PGSERR1
INCERR1
OPERR1

EOP1
Res. Res. Res. Res. Res.

r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_BUSY1

WBNE1

BSY1
QW1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 CRCEND1: Bank 1 CRC end of calculation flag
CRCEND1 bit is raised when the CRC computation has completed on bank 1. An interrupt is
generated if CRCENDIE1 is set to 1. It is not necessary to reset CRCEND1 before restarting
CRC computation. Writing 1 to CLR_CRCEND1 bit in FLASH_CCR1 register clears
CRCEND1.
0: CRC computation not complete on bank 1
1: CRC computation complete on bank 1
Bit 26 DBECCERR1: Bank 1 ECC double detection error flag
DBECCERR1 flag is raised when an ECC double detection error occurs during a read
operation from bank 1. An interrupt is generated if DBECCERRIE1 is set to 1. Writing 1 to
CLR_DBECCERR1 bit in FLASH_CCR1 register clears DBECCERR1.
0: no ECC double detection error occurred on bank 1
1: ECC double detection error occurred on bank 1
Bit 25 SNECCERR1: Bank 1 single correction error flag
SNECCERR1 flag is raised when an ECC single correction error occurs during a read
operation from bank 1. An interrupt is generated if SNECCERRIE1 is set to 1. Writing 1 to
CLR_SNECCERR1 bit in FLASH_CCR1 register clears SNECCERR1.
0: no ECC single correction error occurs on bank 1
1: ECC single correction error occurs on bank 1
Bit 24 RDSERR1: Bank 1 secure error flag
RDSERR1 flag is raised when a read secure error (read access to a secure-only protected
word) occurs on bank 1. An interrupt is generated if RDSERRIE1 is set to 1. Writing 1 to
CLR_RDSERR1 bit in FLASH_CCR1 register clears RDSERR1.
0: no secure error occurs on bank 1
1: a secure error occurs on bank 1
Bit 23 RDPERR1: Bank 1 read protection error flag
RDPERR1 flag is raised when an read protection error (read access to a PCROP-protected
or a RDP-protected area) occurs on bank 1. An interrupt is generated if RDPERRIE1 is set to
1. Writing 1 to CLR_RDPERR1 bit in FLASH_CCR1 register clears RDPERR1.
0: no read protection error occurs on bank 1
1: a read protection error occurs on bank 1

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Embedded flash memory (FLASH) RM0433

Bit 22 OPERR1: Bank 1 write/erase error flag

OPERR1 flag is raised when an error occurs during a write/erase to bank 1. An interrupt is
generated if OPERRIE1 is set to 1. Writing 1 to CLR_OPERR1 bit in FLASH_CCR1 register
clears OPERR1.
0: no write/erase error occurs on bank 1
1: a write/erase error occurs on bank 1
Bit 21 INCERR1: Bank 1 inconsistency error flag
INCERR1 flag is raised when a inconsistency error occurs on bank 1. An interrupt is
generated if INCERRIE1 is set to 1. Writing 1 to CLR_INCERR1 bit in the FLASH_CCR1
register clears INCERR1.
0: no inconsistency error occurs on bank 1
1: a inconsistency error occurs on bank 1
Bit 20 Reserved, must be kept at reset value.
Bit 19 STRBERR1: Bank 1 strobe error flag
STRBERR1 flag is raised when a strobe error occurs on bank 1 (when the master attempts to
write several times the same byte in the write buffer). An interrupt is generated if the
STRBERRIE1 bit is set to 1. Writing 1 to CLR_STRBERR1 bit in FLASH_CCR1 register
clears STRBERR1.
0: no strobe error occurs on bank 1
1: a strobe error occurs on bank 1
Bit 18 PGSERR1: Bank 1 programming sequence error flag
PGSERR1 flag is raised when a sequence error occurs on bank 1. An interrupt is generated
if the PGSERRIE1 bit is set to 1. Writing 1 to CLR_PGSERR1 bit in FLASH_CCR1 register
clears PGSERR1.
0: no sequence error occurs on bank 1
1: a sequence error occurs on bank 1
Bit 17 WRPERR1: Bank 1 write protection error flag
WRPERR1 flag is raised when a protection error occurs during a program operation to bank
1. An interrupt is also generated if the WRPERRIE1 is set to 1. Writing 1 to CLR_WRPERR1
bit in FLASH_CCR1 register clears WRPERR1.
0: no write protection error occurs on bank 1
1: a write protection error occurs on bank 1
Bit 16 EOP1: Bank 1 end-of-program flag
EOP1 flag is set when a programming operation to bank 1 completes. An interrupt is
generated if the EOPIE1 is set to 1. It is not necessary to reset EOP1 before starting a new
operation. EOP1 bit is cleared by writing 1 to CLR_EOP1 bit in FLASH_CCR1 register.
0: no programming operation completed on bank 1
1: a programming operation completed on bank 1
Bits 15:4 Reserved, must be kept at reset value.
Bit 3 CRC_BUSY1: Bank 1 CRC busy flag
CRC_BUSY1 flag is set when a CRC calculation is ongoing on bank 1. This bit cannot be
forced to 0. The user must wait until the CRC calculation has completed or disable CRC
computation on bank 1.
0: no CRC calculation ongoing on bank 1
1: CRC calculation ongoing on bank 1

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RM0433 Embedded flash memory (FLASH)

Bit 2 QW1: Bank 1 wait queue flag

QW1 flag is set when a write, erase or option byte change operation is pending in the
command queue buffer of bank 1. It is not possible to know what type of programming
operation is present in the queue.
This flag is reset by hardware when all write, erase or option byte change operations have
been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It
is reset after a deterministic time if no other operations are requested.
0: no write, erase or option byte change operations waiting in the operation queues of bank 1
1: at least one write, erase or option byte change operation is waiting in the operation queue
of bank 1
Bit 1 WBNE1: Bank 1 write buffer not empty flag
WBNE1 flag is set when the embedded flash memory is waiting for new data to complete the
write buffer. In this state, the write buffer is not empty. WBNE1 is reset by hardware each time
the write buffer is complete or the write buffer is emptied following one of the event below:
– the application software forces the write operation using FW1 bit in FLASH_CR1
– the embedded flash memory detects an error that involves data loss
– the application software has disabled write operations in this bank
This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the
above listed actions, or send the missing data.
0: write buffer of bank 1 empty or full
1: write buffer of bank 1 waiting data to complete
Bit 0 BSY1: Bank 1 busy flag
BSY1 flag is set when an effective write, erase or option byte change operation is ongoing on
bank 1. It is not possible to know what type of operation is being executed.
BSY1 cannot be forced to 0. It is automatically reset by hardware every time a step in a write,
erase or option byte change operation completes.
0: no programming, erase or option byte change operation being executed on bank 1
1: programming, erase or option byte change operation being executed on bank 1

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Embedded flash memory (FLASH) RM0433

4.9.6 FLASH clear control register for bank 1 (FLASH_CCR1)

Address offset: 0x014
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CLR_DBECCERR1

CLR_SNECCERR1

CLR_STRBERR1

CLR_WRPERR1
CLR_CRCEND1

CLR_RDSERR1

CLR_RDPERR1

CLR_PGSERR1
CLR_INCERR1
CLR_OPERR1

CLR_EOP1
Res. Res. Res. Res. Res.

w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 CLR_CRCEND1: Bank 1 CRCEND1 flag clear bit
Setting this bit to 1 resets to 0 CRCEND1 flag in FLASH_SR1 register.
Bit 26 CLR_DBECCERR1: Bank 1 DBECCERR1 flag clear bit
Setting this bit to 1 resets to 0 DBECCERR1 flag in FLASH_SR1 register. If the
SNECCERR1 flag of FLASH_SR1 register is cleared to 0, FLASH_ECC_FA1R register is
reset to 0 as well.
Bit 25 CLR_SNECCERR1: Bank 1 SNECCERR1 flag clear bit
Setting this bit to 1 resets to 0 SNECCERR1 flag in FLASH_SR1 register. If the
DBECCERR1 flag of FLASH_SR1 register is cleared to 0, FLASH_ECC_FA1R register is
reset to 0 as well.
Bit 24 CLR_RDSERR1: Bank 1 RDSERR1 flag clear bit
Setting this bit to 1 resets to 0 RDSERR1 flag in FLASH_SR1 register.
Bit 23 CLR_RDPERR1: Bank 1 RDPERR1 flag clear bit
Setting this bit to 1 resets to 0 RDPERR1 flag in FLASH_SR1 register.
Bit 22 CLR_OPERR1: Bank 1 OPERR1 flag clear bit
Setting this bit to 1 resets to 0 OPERR1 flag in FLASH_SR1 register.
Bit 21 CLR_INCERR1: Bank 1 INCERR1 flag clear bit
Setting this bit to 1 resets to 0 INCERR1 flag in FLASH_SR1 register.
Bit 20 Reserved, must be kept at reset value.
Bit 19 CLR_STRBERR1: Bank 1 STRBERR1 flag clear bit
Setting this bit to 1 resets to 0 STRBERR1 flag in FLASH_SR1 register.
Bit 18 CLR_PGSERR1: Bank 1 PGSERR1 flag clear bit
Setting this bit to 1 resets to 0 PGSERR1 flag in FLASH_SR1 register.

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RM0433 Embedded flash memory (FLASH)

Bit 17 CLR_WRPERR1: Bank 1 WRPERR1 flag clear bit

Setting this bit to 1 resets to 0 WRPERR1 flag in FLASH_SR1 register.
Bit 16 CLR_EOP1: Bank 1 EOP1 flag clear bit
Setting this bit to 1 resets to 0 EOP1 flag in FLASH_SR1 register.
Bits 15:0 Reserved, must be kept at reset value.

4.9.7 FLASH option control register (FLASH_OPTCR)

Address offset: 0x018 or 0x118
Reset value: 0xX000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTCHANGEERRIE
SWAP_BANK

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPTSTART

OPTLOCK
MER
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

w w rs

Bit 31 SWAP_BANK: Bank swapping option configuration bit

SWAP_BANK controls whether bank 1 and bank 2 are swapped or not. This bit is loaded with
the SWAP_BANK_OPT bit of FLASH_OPTSR_CUR register only after reset or POR.
0: bank 1 and bank 2 not swapped
1: bank 1 and bank 2 swapped
Note: The flash bank swapping is not available on STM32H750xB devices. The SWAP_BANK
option bit must be kept at '0'.

Bit 30 OPTCHANGEERRIE: Option byte change error interrupt enable bit

OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs
during an option byte change.
0: no interrupt is generated when an error occurs during an option byte change
1: an interrupt is generated when and error occurs during an option byte change.
Bits 29:5 Reserved, must be kept at reset value.
Bit 4 MER: mass erase request
Setting this bit launches a non-volatile memory bank erase on both banks (i.e. mass erase).
Programming MER bit to 1 automatically sets BER1, BER2, START1 and START2 to 1.
FLASH_OPTCR, FLASH_CR1 and FLASH_CR2 must be unlocked prior to setting MER
high.

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Embedded flash memory (FLASH) RM0433

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 OPTSTART: Option byte start change option configuration bit
OPTSTART triggers an option byte change operation. The user can set OPTSTART only
when the OPTLOCK bit is cleared to 0. The embedded flash memory resets OPTSTART
when the option byte change operation has been acknowledged.
The user application cannot modify any embedded flash memory register until the option
change operation has been completed.
Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG
registers. The FLASH_XXX_PRG registers will be locked until the option byte change
operation has been executed in non-volatile memory.
It is not possible to start an option byte change operation if a CRC calculation is ongoing on
bank 1 or bank 2. Trying to set OPTSTART when CRC_BUSY1/2 of FLASH_SR1/2 register
is set has not effect; the option byte change does not start and no error is generated.
Bit 0 OPTLOCK: FLASH_OPTCR lock option configuration bit
The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The
correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is
executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains
locked until next system reset.
It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence
is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of
FLASH_OPTCR register do not change.
0: FLASH_OPTCR register unlocked
1: FLASH_OPTCR register locked.

4.9.8 FLASH option status register (FLASH_OPTSR_CUR)

Address offset: 0x01C or 0x11C
Reset value: 0xXXXX XXXX (see Table 21: Option byte organization)
This read-only register reflects the current values of corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWAP_BANK_OPT

ST_RAM_SIZE[1:0]
OPTCHANGEERR

IWDG_FZ_SDBY

IWDG_FZ_STOP
SECURITY
IO_HSLV

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NRST_STOP_D1
NRST_STDY_D1

IWDG1_SW

OPT_BUSY
BOR_LEV
Res.

RDP Res.

r r r r r r r r r r r r r r

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RM0433 Embedded flash memory (FLASH)

Bit 31 SWAP_BANK_OPT: Bank swapping option status bit

SWAP_BANK_OPT reflects whether bank 1 and bank 2 are swapped or not.
SWAP_BANK_OPT is loaded to SWAP_BANK of FLASH_OPTCR after a reset.
0: bank 1 and bank 2 not swapped
1: bank 1 and bank 2 swapped
Note: The flash bank swapping is not available on STM32H750xB devices. The SWAP_BANK
option bit must be kept at '0'.

Bit 30 OPTCHANGEERR: Option byte change error flag

OPTCHANGEERR flag indicates that an error occurred during an option byte change
operation. When OPTCHANGEERR is set to 1, the option byte change operation did not
successfully complete. An interrupt is generated when this flag is raised if the
OPTCHANGEERRIE bit of FLASH_OPTCR register is set to 1.
Writing 1 to CLR_OPTCHANGEERR of register FLASH_OPTCCR clears
OPTCHANGEERR.
0: no option byte change errors occurred
1: one or more errors occurred during an option byte change operation.

Bit 29 IO_HSLV: I/O high-speed at low-voltage status bit

This bit indicates that the product operates below 2.7 V.
0: Product working in the full voltage range, I/O speed optimization at low-voltage disabled
1: Product operating below 2.7 V, I/O speed optimization at low-voltage feature allowed
Bits 28:26 Reserved, must be kept at reset value.
Bits 25:24 Reserved, must be kept at reset value.
Bits 23: 22 Reserved, must be kept at reset value.
Bit 21 SECURITY: Security enable option status bit
0: Security feature disabled
1: Security feature enabled.
Bits 20:19 ST_RAM_SIZE[1:0]: ST RAM size option status
00: 2 Kbytes reserved to ST code
01: 4 Kbytes reserved to ST code
10: 8 Kbytes reserved to ST code
11: 16 Kbytes reserved to ST code
Note: This bitfield is effective only when the security is enabled (SECURITY = 1).

Bit 18 IWDG_FZ_SDBY: IWDG Standby mode freeze option status bit

When set the independent watchdog IWDG1 is frozen in system Standby mode.
0: Independent watchdog frozen in Standby mode
1: Independent watchdog keep running in Standby mode.
Bit 17 IWDG_FZ_STOP: IWDG Stop mode freeze option status bit
When set the independent watchdog IWDG1 is in system Stop mode.
0: Independent watchdog frozen in system Stop mode
1: Independent watchdog keep running in system Stop mode.
Bit 16 Reserved, must be kept at reset value.

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Embedded flash memory (FLASH) RM0433

Bits 15:8 RDP: Readout protection level option status byte

0xAA: global readout protection level 0
0xCC: global readout protection level 2
others values: global readout protection level 1.
Bit 7 NRST_STDY_D1: D1 domain DStandby entry reset option status bit
0: a reset is generated when entering DStandby mode on D1 domain
1: no reset generated when entering DStandby mode on D1 domain
Bit 6 NRST_STOP_D1: D1 domain DStop entry reset option status bit
0: a reset is generated when entering DStop mode on D1 domain
1: no reset generated when entering DStop mode on D1 domain.
Bit 5 Reserved, must be kept at reset value.
Bit 4 IWDG1_SW: IWDG1 control mode option status bit
0: IWDG1 watchdog is controlled by hardware
1: IWDG1 watchdog is controlled by software
Bits 3:2 BOR_LEV: Brownout level option status bit
These bits reflects the power level that generates a system reset.uuuuuuuuuuuuu
00: VBOR0, brownout reset threshold 0
01: VBOR1, brownout reset threshold 1
10: VBOR2, brownout reset threshold 2
11: VBOR3, brownout reset threshold 3
Note: Refer to device datasheet for the values of VBORx VDD reset thresholds.
Bit 1 Reserved, must be kept at reset value.
Bit 0 OPT_BUSY: Option byte change ongoing flag
OPT_BUSY indicates if an option byte change is ongoing. When this bit is set to 1, the
embedded flash memory is performing an option change and it is not possible to modify any
embedded flash memory register.
0: no option byte change ongoing
1: an option byte change ongoing and all write accesses to flash registers are blocked until
the option byte change completes.

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RM0433 Embedded flash memory (FLASH)

4.9.9 FLASH option status register (FLASH_OPTSR_PRG)

Address offset: 0x020 or 0x120
Reset value: 0xXXXX XXXX (see Table 21: Option byte organization)
This register is used to program values in corresponding option bits. Values after reset
reflects the current values of the corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWAP_BANK_OPT

ST_RAM_SIZE[1:0]

IWDG_FZ_SDBY

IWDG_FZ_STOP
SECURITY
IO_HSLV

Res.

Res.

Res.

Res.
Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NRST_STOP_D1
NRST_STDY_D1

IWDG1_SW

BOR_LEV
Res.
RDP Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SWAP_BANK_OPT: Bank swapping option configuration bit

SWAP_BANK_OPT option bit is used to configure whether the bank 1 and bank 2 are
swapped or not. This bit is loaded with the SWAP_BANK_OPT bit of FLASH_OPTSR_CUR
register after a reset.
0: bank 1 and bank 2 not swapped
1: bank 1 and bank 2 swapped
Note: The flash bank swapping is not available on STM32H750xB devices. The SWAP_BANK
option bit must be kept at '0'.
Note:
Bit 30 Reserved, must be kept at reset value.
Bit 29 IO_HSLV: I/O high-speed at low-voltage configuration bit
This bit indicates that the product operates below 2.7 V.
0: Product working in the full voltage range, I/O speed optimization at low-voltage disabled
1: Product operating below 2.7 V, I/O speed optimization at low-voltage feature allowed
Bits 28:26 Reserved, must be kept at reset value.
Bits 25:24 Reserved, must be kept at reset value.
Bits 23: 22 Reserved, must be kept at reset value.
Bit 21 SECURITY: Security enable option configuration bit
The SECURITY option bit enables the secure access mode of the device during an option
byte change. The change will be taken into account at next reset (next boot sequence). Once
it is enabled, the security feature can be disabled if no areas are protected by PCROP or
Secure access mode. If there are secure-only or PCROP protected areas, perform a level
regression (from level 1 to 0) and set all the bits to unprotect secure-only areas and PCROP
areas.
0: Security feature disabled
1: Security feature enabled.

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Embedded flash memory (FLASH) RM0433

Bits 20:19 ST_RAM_SIZE[1:0]: ST RAM size option configuration bits

00: 2 Kbytes reserved to ST code
01: 4 Kbytes reserved to ST code
10: 8 Kbytes reserved to ST code
11: 16 Kbytes reserved to ST code
Note: This bitfield is effective only when the security is enabled (SECURITY = 1).

Bit 18 IWDG_FZ_SDBY: IWDG Standby mode freeze option configuration bit

This option bit is used to freeze or not the independent watchdog IWDG1 in system Standby
mode.
0: Independent watchdog frozen in Standby mode
1: Independent watchdog keep running in Standby mode.
Bit 17 IWDG_FZ_STOP: IWDG Stop mode freeze option configuration bit
This option bit is used to freeze or not the independent watchdog IWDG1 in system Stop
mode.
0: Independent watchdog frozen in system Stop mode
1: Independent watchdog keep running in system Stop mode.
Bit 16 Reserved, must be kept at reset value.
Bits 15:8 RDP: Readout protection level option configuration bits
RDP bits are used to change the readout protection level. This change is possible only when
the current protection level is different from level 2. The possible configurations are:
0xAA: global readout protection level 0
0xCC: global readout protection level 2
others values: global readout protection level 1.
Bit 7 NRST_STDY_D1: D1 domain DStandby entry reset option configuration bit
0: a reset is generated when entering DStandby mode on D1 domain.
1: no reset generated when entering DStandby mode on D1 domain
Bit 6 NRST_STOP_D1: D1 domain DStop entry reset option configuration bit
0: a reset is generated when entering DStop mode on D1 domain.
1: no reset generated when entering DStop mode on D1 domain.
Bit 5 Reserved, must be kept at reset value.
Bit 4 IWDG1_SW: IWDG1 control mode option configuration bit
IWDG1_SW option bit is used to select if IWDG1 independent watchdog is controlled by
hardware or by software.
0: IWDG1 watchdog is controlled by hardware
1: IWDG1 watchdog is controlled by software
Bits 3:2 BOR_LEV: Brownout level option configuration bit
These option bits are used to define the power level that generates a system reset.
00: VBOR0, brownout reset threshold 0
01: VBOR1, brownout reset threshold 1
02: VBOR2, brownout reset threshold 2
03: VBOR3, brownout reset threshold 3
Note: Refer to device datasheet for the values of VBORx VDD reset thresholds.
Bits 1:0 Reserved, must be kept at reset value.

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RM0433 Embedded flash memory (FLASH)

4.9.10 FLASH option clear control register (FLASH_OPTCCR)

Address offset: 0x024 or 0x124
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLR_OPTCHANGEERR

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bit 31 Reserved, must be kept at reset value.

Bit 30 CLR_OPTCHANGEERR: OPTCHANGEERR reset bit
This bit is used to reset the OPTCHANGEERR flag in FLASH_OPTSR_CUR register.
FLASH_OPTCCR is write-only.
It is reset by programming it to 1.
Bits 29:0 Reserved, must be kept at reset value.

4.9.11 FLASH protection address for bank 1 (FLASH_PRAR_CUR1)

Address offset: 0x028
Reset value: 0xXXXX 0XXX (see Table 21: Option byte organization)
This read-only register reflects the current values of corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMEP1

Res. Res. Res. PROT_AREA_END1

r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. PROT_AREA_START1

r r r r r r r r r r r r

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Bit 31 DMEP1: Bank 1 PCROP protected erase enable option status bit
If DMEP1 is set to 1, the PCROP protected area in bank 1 is erased when a protection level
regression (change from level 1 to 0) or a bank erase with protection removal occurs.
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 PROT_AREA_END1: Bank 1 PCROP area end status bits
These bits contain the last 256-byte block of the PCROP area in bank 1.
If this address is equal to PROT_AREA_START1, the whole bank 1 is PCROP protected.
If this address is lower than PROT_AREA_START1, no protection is set on bank 1.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 PROT_AREA_START1: Bank 1 PCROP area start status bits
These bits contain the first 256-byte block of the PCROP area in bank 1.
If this address is equal to PROT_AREA_END1, the whole bank 1 is PCROP protected.
If this address is higher than PROT_AREA_END1, no protection is set on bank 1.

4.9.12 FLASH protection address for bank 1 (FLASH_PRAR_PRG1)

Address offset: 0x02C
Reset value: 0xXXXX 0XXX (see Table 21: Option byte organization)
This register is used to program values in corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMEP1

Res. Res. Res. PROT_AREA_END1

rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. PROT_AREA_START1

rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 DMEP1: Bank 1 PCROP protected erase enable option configuration bit
If DMEP1 is set to 1, the PCROP protected area in bank 1 is erased when a protection level
regression (change from level 1 to 0) or a bank erase with protection removal occurs.

Bits 30:28 Reserved, must be kept at reset value.

Bits 27:16 PROT_AREA_END1: Bank 1 PCROP area end configuration bits
These bits contain the last 256-byte block of the PCROP area in bank 1.
If this address is equal to PROT_AREA_START1, the whole bank 1 is PCROP protected.
If this address is lower than PROT_AREA_START1, no protection is set on bank 1.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 PROT_AREA_START1: Bank 1 PCROP area start configuration bits
These bits contain the first 256-byte block of the PCROP area in bank 1.
If this address is equal to PROT_AREA_END1, the whole bank 1 is PCROP protected.
If this address is higher than PROT_AREA_END1, no protection is set on bank 1.

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RM0433 Embedded flash memory (FLASH)

4.9.13 FLASH secure address for bank 1 (FLASH_SCAR_CUR1)

Address offset: 0x030
Reset value: 0xXXXX 0XXX (see Table 21: Option byte organization)
This read-only register reflects the current values of corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMES1

Res. Res. Res. SEC_AREA_END1

r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. SEC_AREA_START1

r r r r r r r r r r r r

Bit 31 DMES1: Bank 1 secure access protected erase enable option status bit
If DMES1 is set to 1, the secure access only area in bank 1 is erased when a protection level
regression (change from level 1 to 0) or a bank erase with protection removal occurs.
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 SEC_AREA_END1: Bank 1 secure-only area end status bits
These bits contain the last 256-byte block of the secure-only area in bank 1.
If this address is equal to SEC_AREA_START1, the whole bank 1 is secure access only.
If this address is lower than SEC_AREA_START1, no protection is set on bank 1.
Note: The non-secure flash area starts at address 0x(SEC_AREA_END1 + 1)00.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 SEC_AREA_START1: Bank 1 secure-only area start status bits
These bits contain the first 256 bytes of block of the secure-only area in bank 1.
If this address is equal to SEC_AREA_END1, the whole bank 1 is secure access only.
If this address is higher than SEC_AREA_END1, no protection is set on bank 1.

4.9.14 FLASH secure address for bank 1 (FLASH_SCAR_PRG1)

Address offset: 0x034
Reset value: 0xXXXX 0XXX (see Table 21: Option byte organization)
This register is used to program values in corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMES1

Res. Res. Res. SEC_AREA_END1

rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. SEC_AREA_START1

rw rw rw rw rw rw rw rw rw rw rw rw

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Bit 31 DMES1: Bank 1 secure access protected erase enable option configuration bit
If DMES1 is set to 1, the secure access only area in bank 1 is erased when a protection level
regression (change from level 1 to 0) or a bank erase with protection removal occurs.

Bits 30:28 Reserved, must be kept at reset value.

Bits 27:16 SEC_AREA_END1: Bank 1 secure-only area end configuration bits
These bits contain the last block of 256 bytes of the secure-only area in bank 1.
If this address is equal to SEC_AREA_START1, the whole bank 1 is secure access only.
If this address is lower than SEC_AREA_START1, no protection is set on bank 1.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 SEC_AREA_START1: Bank 1 secure-only area start configuration bits
These bits contain the first block of 256 bytes of the secure-only area in bank 1.
If this address is equal to SEC_AREA_END1, the whole bank 1 is secure access only.
If this address is higher than SEC_AREA_END1, no protection is set on bank 1.

4.9.15 FLASH write sector protection for bank 1

(FLASH_WPSN_CUR1R)
Address offset: 0x038
Reset value: 0x0000 00XX
This read-only register reflects the current values of corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. WRPSn1

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 WRPSn1: Bank 1 sector write protection option status byte
Each FLASH_WPSGN_CUR1R bit reflects the write protection status of the corresponding
bank 1 sector (0: sector is write protected; 1: sector is not write protected)

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RM0433 Embedded flash memory (FLASH)

4.9.16 FLASH write sector protection for bank 1

(FLASH_WPSN_PRG1R)
Address offset: 0x03C
Reset value: 0x0000 00XX
This register is used to program values in corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. WRPSn1

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 WRPSn1: Bank 1 sector write protection option status byte
Setting each FLASH_WPSGN_PRG1R bit to 0 write-protects the corresponding bank 1
sector (0: sector is write protected; 1: sector is not write protected)

4.9.17 FLASH register boot address (FLASH_BOOT_CURR)

Address offset: 0x040 or 0x140
Reset value: 0xXXXX XXXX (see Table 21: Option byte organization)
This register reflects the current values of corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BOOT_ADD1

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BOOT_ADD0

r r r r r r r r r r r r r r r r

Bits 31:16 BOOT_ADD1: Arm® Cortex®-M7 boot address 1

These bits reflect the MSB of the Arm® Cortex®-M7 boot address when the BOOT pin is high.
Bits 15:0 BOOT_ADD0: Arm® Cortex®-M7 boot address 0
These bits reflect the MSB of the Arm® Cortex®-M7 boot address when the BOOT pin is low.

4.9.18 FLASH register boot address FLASH_BOOT_PRGR)

Address offset: 0x044 or 0x144
Reset value: 0xXXXX XXXX (see Table 21: Option byte organization)
This register is used to program values in corresponding option bits.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BOOT_ADD1

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BOOT_ADD0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 BOOT_ADD1: Arm® Cortex®-M7 boot address 1 configuration

These bits allow configuring the MSB of the Arm® Cortex®-M7 boot address when the BOOT
pin is high.
Bits 15:0 BOOT_ADD0: Arm® Cortex®-M7 boot address 0 configuration
These bits allow configuring the MSB of the Arm® Cortex®-M7 boot address when the BOOT
pin is low.

4.9.19 FLASH CRC control register for bank 1 (FLASH_CRCCR1)

Address offset: 0x050
Reset value: 0x001C 0000
This register can be modified only if CRC_EN bit is set to 1 in FLASH_CR1 register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_BURST

CLEAN_CRC

START_CRC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw w rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_BY_SECT
CLEAN_SECT

CRC_SECT
ADD_SECT

ALL_BANK

Res. Res. Res. Res. Res. Res. Res. Res. Res.

w w rw w rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:20 CRC_BURST: Bank 1 CRC burst size
CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit.
00: every burst has a size of 4 flash words (256-bit)
01: every burst has a size of 16 flash words (256-bit)
10: every burst has a size of 64 flash words (256-bit)
11: every burst has a size of 256 flash words (256-bit)
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CLEAN_CRC: Bank 1 CRC clear bit
Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR
register.

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RM0433 Embedded flash memory (FLASH)

Bit 16 START_CRC: Bank 1 CRC start bit

START_CRC bit triggers a CRC calculation on bank 1 using the current configuration. No
CRC calculation can launched when an option byte change operation is ongoing because all
write accesses to embedded flash memory registers are put on hold until the option byte
change operation has completed.
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 CLEAN_SECT: Bank 1 CRC sector list clear bit
Setting CLEAN_SECT to 1 clears the list of sectors on which the CRC is calculated.
Bit 9 ADD_SECT: Bank 1 CRC sector select bit
Setting ADD_SECT to 1 adds the sector whose number is CRC_SECT to the list of sectors
on which the CRC is calculated.
Bit 8 CRC_BY_SECT: Bank 1 CRC sector mode select bit
When CRC_BY_SECT is set to 1, the CRC calculation is performed at sector level, on the
sectors present in the list of sectors. To add a sector to this list, use ADD_SECT and
CRC_SECT bits. To clean the list, use CLEAN_SECT bit.
When CRC_BY_SECT is reset to 0, the CRC calculation is performed on all addresses
between CRC_START_ADDR and CRC_END_ADDR.
Bit 7 ALL_BANK: Bank 1 CRC select bit
When ALL_BANK is set to 1, all bank 1 user sectors are added to list of sectors on which the
CRC is calculated.
Bits 6:3 Reserved, must be kept at reset value.
Bits 2:0 CRC_SECT: Bank 1 CRC sector number
CRC_SECT is used to select one or more user flash sectors to be added to the list of sectors
on which the CRC is calculated. The CRC can be computed either between two addresses
(using registers FLASH_CRCSADD1R and FLASH_CRCEADD1R) or on a list of sectors. If
this latter option is selected, it is possible to add a sector to the list of sectors by programming
the sector number in CRC_SECT and then setting ADD_SECT to 1.
The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC
computation. CRC_SECT can be set only when CRC_EN of FLASH_CR register is set to 1.
000: sector 0 of bank 1
001: sector 1 of bank 1
...
111: sector 7 of bank 1

4.9.20 FLASH CRC start address register for bank 1

(FLASH_CRCSADD1R)
Address offset: 0x054
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRC_START_ADDR[19:16]

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_START_ADDR[15:2] Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:20 Reserved, must be kept at reset value.

Bits 19:2 CRC_START_ADDR[19:2]: CRC start address on bank 1
CRC_START_ADDR is used when CRC_BY_SECT is cleared to 0. It must be programmed
to the start address of the bank 1 memory area on which the CRC calculation is performed.
Bits 1:0 Reserved, must be kept at reset value.

4.9.21 FLASH CRC end address register for bank 1

(FLASH_CRCEADD1R)
Address offset: 0x058
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRC_END_ADDR[19:16]

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_END_ADDR[15:2] Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:2 CRC_END_ADDR[19:2]: CRC end address on bank 1
CRC_END_ADDR is used when CRC_BY_SECT is cleared to 0. It must be programmed to
the end address of the bank 1 memory area on which the CRC calculation is performed
Bits 1:0 Reserved, must be kept at reset value.

4.9.22 FLASH CRC data register (FLASH_CRCDATAR)

Address offset: 0x05C or 0x15C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CRC_DATA

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_DATA

r r r r r r r r r r r r r r r r

Bits 31:0 CRC_DATA: CRC result

CRC_DATA bits contain the result of the last CRC calculation.

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RM0433 Embedded flash memory (FLASH)

4.9.23 FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R)

Address offset: 0x060
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. FAIL_ECC_ADDR1

r r r r r r r r r r r r r r r

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:0 FAIL_ECC_ADDR1: Bank 1 ECC error address
When an ECC error occurs (both for single correction or double detection) during a read
operation from bank 1, the FAIL_ECC_ADDR1 bitfield indicates the address that generated
the error:
Fail address = FAIL_ECC_ADDR1 * 32 + flash memory Bank 1 address offset
FAIL_ECC_ADDR1 is reset when the flag error in the FLASH_SR1 register
(CLR_SNECCERR1 or CLR_DBECCERR1) is reset.
The embedded flash memory programs the address in this register only when no ECC error
flags are set. This means that only the first address that generated an ECC error is saved.
The address in FAIL_ECC_ADDR1 is relative to the flash memory area where the error
occurred (user flash memory, system flash memory).

4.9.24 FLASH key register for bank 2 (FLASH_KEYR2)

Address offset: 0x104
Reset value: 0x0000 0000
FLASH_KEYR2 is a write-only register. The following values must be programmed
consecutively to unlock FLASH_CR2 register and allow programming/erasing it:
1. 1st key = 0x4567 0123
2. 2nd key = 0xCDEF 89AB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY2R
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

KEY2R

w w w w w w w w w w w w w w w w

Bits 31:0 KEY2R: Bank 2 access configuration unlock key

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4.9.25 FLASH control register for bank 2 (FLASH_CR2)

Address offset: 0x10C
Reset value: 0x0000 0031

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCRDERRIE2

DBECCERRIE2

SNECCERRIE2

STRBERRIE2

WRPERRIE2
CRCENDIE2

RDSERRIE2

RDPERRIE2

PGSERRIE2
INCERRIE2
OPERRIE2

EOPIE2
Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_EN

START2

PSIZE2

LOCK2
SPSS2

BER2

SER2
FW2

PG2
Res. Res. Res. SNB2

rw rw rw rw rw rw rw rw rw rw rw rw rs

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 CRCRDERRIE2: Bank 2 CRC read error interrupt enable bit
When CRCRDERRIE2 bit is set to 1, an interrupt is generated when a protected area
(PCROP or secure-only) has been detected during the last CRC computation on bank 2.
CRCRDERRIE2 can be programmed only when LOCK2 is cleared to 0.
0: no interrupt generated when a CRC read error occurs on bank 2
1: interrupt generated when a CRC read error occurs on bank 2
Bit 27 CRCENDIE2: Bank 2 CRC end of calculation interrupt enable bit
When CRCENDIE2 bit is set to 1, an interrupt is generated when the CRC computation has
completed on bank 2. CRCENDIE2 can be programmed only when LOCK2 is cleared to 0.
0: no interrupt generated when CRC computation complete on bank 2
1: interrupt generated when CRC computation complete on bank 2
Bit 26 DBECCERRIE2: Bank 2 ECC double detection error interrupt enable bit
When DBECCERRIE2 bit is set to 1, an interrupt is generated when an ECC double
detection error occurs during a read operation from bank 2. DBECCERRIE2 can be
programmed only when LOCK2 is cleared to 0.
0: no interrupt generated when an ECC double detection error occurs on bank 2
1: interrupt generated if an ECC double detection error occurs on bank 2
Bit 25 SNECCERRIE2: Bank 2 ECC single correction error interrupt enable bit
When SNECCERRIE2 bit is set to 1, an interrupt is generated when an ECC single correction
error occurs during a read operation from bank 2. SNECCERRIE2 can be programmed only
when LOCK2 is cleared to 0.
0: no interrupt generated when an ECC single correction error occurs on bank 2
1: interrupt generated when an ECC single correction error occurs on bank 2
Bit 24 RDSERRIE2: Bank 2 secure error interrupt enable bit
When RDSERRIE2 bit is set to 1, an interrupt is generated when a secure error (access to a
secure-only protected address) occurs during a read operation from bank 2. RDSERRIE2
can be programmed only when LOCK2 is cleared to 0.
0: no interrupt generated when a secure error occurs on bank 2
1: an interrupt is generated when a secure error occurs on bank 2

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RM0433 Embedded flash memory (FLASH)

Bit 23 RDPERRIE2: Bank 2 read protection error interrupt enable bit

When RDPERRIE2 bit is set to 1, an interrupt is generated when a read protection error
occurs (access to an address protected by PCROP or by RDP level 1) during a read
operation from bank 2. RDPERRIE2 can be programmed only when LOCK2 is cleared to 0.
0: no interrupt generated when a read protection error occurs on bank 2
1: an interrupt is generated when a read protection error occurs on bank 2
Bit 22 OPERRIE2: Bank 2 write/erase error interrupt enable bit
When OPERRIE2 bit is set to 1, an interrupt is generated when an error is detected during a
write/erase operation to bank 2. OPERRIE2 can be programmed only when LOCK2 is
cleared to 0.
0: no interrupt generated when a write/erase error occurs on bank 2
1: interrupt generated when a write/erase error occurs on bank 2
Bit 21 INCERRIE2: Bank 2 inconsistency error interrupt enable bit
When INCERRIE2 bit is set to 1, an interrupt is generated when an inconsistency error
occurs during a write operation to bank 2. INCERRIE2 can be programmed only when
LOCK2 is cleared to 0.
0: no interrupt generated when a inconsistency error occurs on bank 2
1: interrupt generated when a inconsistency error occurs on bank 2.
Bit 20 Reserved, must be kept at reset value.
Bit 19 STRBERRIE2: Bank 2 strobe error interrupt enable bit
When STRBERRIE2 bit is set to 1, an interrupt is generated when a strobe error occurs (the
master programs several times the same byte in the write buffer) during a write operation to
bank 2. STRBERRIE2 can be programmed only when LOCK2 is cleared to 0.
0: no interrupt generated when a strobe error occurs on bank 2
1: interrupt generated when strobe error occurs on bank 2.
Bit 18 PGSERRIE2: Bank 2 programming sequence error interrupt enable bit
When PGSERRIE2 bit is set to 1, an interrupt is generated when a sequence error occurs
during a program operation to bank 2. PGSERRIE2 can be programmed only when LOCK2 is
cleared to 0.
0: no interrupt generated when a sequence error occurs on bank 2
1: interrupt generated when sequence error occurs on bank 2.
Bit 17 WRPERRIE2: Bank 2 write protection error interrupt enable bit
When WRPERRIE2 bit is set to 1, an interrupt is generated when a protection error occurs
during a program operation to bank 2. WRPERRIE2 can be programmed only when LOCK2
is cleared to 0.
0: no interrupt generated when a protection error occurs on bank 2
1: interrupt generated when a protection error occurs on bank 2.
Bit 16 EOPIE2: Bank 2 end-of-program interrupt control bit
Setting EOPIE2 bit to 1 enables the generation of an interrupt at the end of a program
operation to bank 2. EOPIE2 can be programmed only when LOCK2 is cleared to 0.
0: no interrupt generated at the end of a program operation to bank 2.
1: interrupt enabled when at the end of a program operation to bank 2.
Bit 15 CRC_EN: Bank 2 CRC control bit
Setting CRC_EN bit to 1 enables the CRC calculation on bank 2. CRC_EN does not start
CRC calculation but enables CRC configuration through FLASH_CRCCR2 register.
When CRC calculation is performed on bank 2, it can only be disabled by setting CRC_EN bit
to 0. Resetting CRC_EN clears CRC configuration and resets the content of
FLASH_CRCDATAR register.
CRC_EN can be programmed only when LOCK2 is cleared to 0.

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Bit 14 SPSS2: Bank 2 special sector selection bit

Set this bit when accessing non-user sectors of the flash memory. This bit can be
programmed only when LOCK2 is cleared to 0.
0: User sectors selection in bank 2
1: Non-user, special sectors selection in bank 2
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:8 SNB2: Bank 2 sector erase selection number
These bits are used to select the target sector for a sector erase operation (they are unused
otherwise). SNB2 can be programmed only when LOCK2 is cleared to 0.
000: sector 0 of bank 2
001: sector 1 of bank 2
...
111: sector 7 of bank 2

Bit 7 START2: Bank 2 erase start control bit

START2 bit is used to start a sector erase or a bank erase operation. START2 can be
programmed only when LOCK2 is cleared to 0.
The embedded flash memory resets START2 when the corresponding operation has been
acknowledged. The user application cannot access any embedded flash memory register
until the operation is acknowledged.
Bit 6 FW2: Bank 2 write forcing control bit
FW2 forces a write operation even if the write buffer is not full. FW2 can be programmed only
when LOCK2 is cleared to 0.
The embedded flash memory resets FW2 when the corresponding operation has been
acknowledged. The user application cannot access any flash register until the operation is
acknowledged.
Write forcing is effective only if the write buffer is not empty. In particular, FW2 does not start
several write operations when the write operations are performed consecutively.
Bits 5:4 PSIZE2: Bank 2 program size
PSIZE2 selects the maximum number of bits that can be written to 0 in one shot during a
write operation (programming parallelism). PSIZE2 can be programmed only when LOCK2 is
cleared to 0.
00: programming parallelism is byte (8 bits)
01: programming parallelism is half-word (16 bits)
10: programming parallelism is word (32 bits)
11: programming parallelism is double-word (64 bits)
Bit 3 BER2: Bank 2 erase request
Setting BER2 bit to 1 requests a bank erase operation on bank 2 (user flash memory only).
BER2 can be programmed only when LOCK2 is cleared to 0.
BER2 has a higher priority than SER2: if both are set, the embedded flash memory executes
a bank erase.
0: bank erase not requested on bank 2
1: bank erase requested on bank 2
Note: Write protection error is triggered when a bank erase is required and some sectors are
protected.

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RM0433 Embedded flash memory (FLASH)

Bit 2 SER2: Bank 2 sector erase request

Setting SER2 bit to 1 requests a sector erase on bank 2. SER2 can be programmed only
when LOCK2 is cleared to 0.
BER2 has a higher priority than SER2: if both are set, the embedded flash memory executes
a bank erase.
0: sector erase not requested on bank 2
1: sector erase requested on bank 2
Note: Write protection error is triggered when a sector erase is required on protected
sector(s).
Bit 1 PG2: Bank 2 internal buffer control bit
Setting PG2 bit to 1 enables internal buffer for write operations to bank 2. This allows the
preparation of program operations even if a sector or bank erase is ongoing.
PG2 can be programmed only when LOCK2 is cleared to 0. When PG2 is reset, the internal
buffer is disabled for write operations to bank 2 and all the data stored in the buffer but not
sent to the operation queue are lost.
Bit 0 LOCK2: Bank 2 configuration lock bit
This bit locks the FLASH_CR2 register. The correct write sequence to FLASH_KEYR2
register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to
FLASH_KEYR2 is performed twice, this bit remains locked until next system reset.
LOCK2 can be set by programming it to 1. When set to 1, a new unlock sequence is
mandatory to unlock it. When LOCK2 changes from 0 to 1, the other bits of FLASH_CR2
register do not change.
0: FLASH_CR2 register unlocked
1: FLASH_CR2 register locked

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Embedded flash memory (FLASH) RM0433

4.9.26 FLASH status register for bank 2 (FLASH_SR2)

Address offset: 0x110
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DBECCERR2

SNECCERR2

STRBERR2

WRPERR2
CRCEND2

RDSERR2

RDPERR2

PGSERR2
INCERR2
OPERR2

EOP2
Res. Res. Res. Res. Res.

r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_BUSY2

WBNE2

BSY2
QW2
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 CRCEND2: Bank 2 CRC end of calculation flag
CRCEND2 bit is raised when the CRC computation has completed on bank 2. An interrupt is
generated if CRCENDIE2 is set to 1. It is not necessary to reset CRCEND2 before restarting
CRC computation. Writing 1 to CLR_CRCEND2 bit in FLASH_CCR2 register clears
CRCEND2.
0: CRC computation not complete on bank 2
1: CRC computation complete on bank 2
Bit 26 DBECCERR2: Bank 2 ECC double detection error flag
DBECCERR2 flag is raised when an ECC double detection error occurs during a read
operation from bank 2. An interrupt is generated if DBECCERRIE2 is set to 1. Writing 1 to
CLR_DBECCERR2 bit in FLASH_CCR2 register clears DBECCERR2.
0: no ECC double detection error occurs on bank 2
1: ECC double detection error occurs on bank 2
Bit 25 SNECCERR2: Bank 2 single correction error flag
SNECCERR2 flag is raised when an ECC single correction error occurs during a read
operation from bank 2. An interrupt is generated if SNECCERRIE2 is set to 1. Writing 1 to
CLR_SNECCERR2 bit in FLASH_CCR2 register clears SNECCERR2.
0: no ECC single correction error occurs on bank 2
1: ECC single correction error occurs on bank 2
Bit 24 RDSERR2: Bank 2 secure error flag
RDSERR2 flag is raised when a read secure error (read access to a secure-only protected
word) occurs on bank 2. An interrupt is generated if RDSERRIE2 is set to 1. Writing 1 to
CLR_RDSERR2 bit in FLASH_CCR2 register clears RDSERR2.
0: no secure error occurs on bank 2
1: a secure error occurs on bank 2
Bit 23 RDPERR2: Bank 2 read protection error flag
RDPERR2 flag is raised when a read protection error (read access to a PCROP-protected
word or a RDP-protected area) occurs on bank 2. An interrupt is generated if RDPERRIE2 is
set to 1. Writing 1 to CLR_RDPERR2 bit in FLASH_CCR2 register clears RDPERR2.
0: no read protection error occurs on bank 2
1: a read protection error occurs on bank 2

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RM0433 Embedded flash memory (FLASH)

Bit 22 OPERR2: Bank 2 write/erase error flag

OPERR2 flag is raised when an error occurs during a write/erase to bank 2. An interrupt is
generated if OPERRIE2 is 1 set to 1. Writing 1 to CLR_OPERR2 bit in FLASH_CCR2
register clears OPERR2.
0: no write/erase error occurred on bank 2
1: a write/erase error occurred on bank 2
Bit 21 INCERR2: Bank 2 inconsistency error flag
INCERR2 flag is raised when a inconsistency error occurs on bank 2. An interrupt is
generated if INCERRIE2 is set to 1. Writing 1 to CLR_INCERR2 bit in the FLASH_CCR2
register clears INCERR2.
0: no inconsistency error occurred on bank 2
1: an inconsistency error occurred on bank 2.
Bit 20 Reserved, must be kept at reset value.
Bit 19 STRBERR2: Bank 2 strobe error flag
STRBERR2 flag is raised when a strobe error occurs on bank 2 (when the master attempts to
write several times the same byte in the write buffer). An interrupt is generated if the
STRBERRIE2 bit is set to 1. Writing 1 to CLR_STRBERR2 bit in FLASH_CCR2 register
clears STRBERR2.
0: no strobe error occurred on bank 2
1: a strobe error occurred on bank 2.
Bit 18 PGSERR2: Bank 2 programming sequence error flag
PGSERR2 flag is raised when a sequence error occurs on bank 2. An interrupt is generated
if the PGSERRIE2 bit is set to 1. Writing 1 to CLR_PGSERR2 bit in FLASH_CCR2 register
clears PGSERR2.
0: no sequence error occurred on bank 2
1: a sequence error occurred on bank 2.
Bit 17 WRPERR2: Bank 2 write protection error flag
WRPERR2 flag is raised when a protection error occurs during a program operation to bank
2. An interrupt is also generated if the WRPERRIE2 is set to 1. Writing 1 to CLR_WRPERR2
bit in FLASH_CCR2 register clears WRPERR2.
0: no write protection error occurred on bank 2
1: a write protection error occurred on bank 2
Bit 16 EOP2: Bank 2 end-of-program flag
EOP2 flag is set when a programming operation to bank 2 completes. An interrupt is
generated if the EOPIE2 is set to 1. It is not necessary to reset EOP2 before starting a new
operation. EOP2 bit is cleared by writing 1 to CLR_EOP2 bit in FLASH_CCR2 register.
0: no programming operation completed on bank 2
1: a programming operation completed on bank 2
Bits 15:4 Reserved, must be kept at reset value.
Bit 3 CRC_BUSY2: Bank 2 CRC busy flag
CRC_BUSY2 flag is set when a CRC calculation is ongoing on bank 2. This bit cannot be
forced to 0. The user must wait until the CRC calculation has completed or disable CRC
computation on bank 2.
0: no CRC calculation ongoing on bank 2
1: CRC calculation ongoing on bank 2.

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Embedded flash memory (FLASH) RM0433

Bit 2 QW2: Bank 2 wait queue flag

QW2 flag is set when a write or erase operation is pending in the command queue buffer of
bank 2. It is not possible to know what type of operation is present in the queue. This flag is
reset by hardware when all write/erase operations have been executed and thus removed
from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if
no other operations are requested.
0: no write or erase operation is waiting in the operation queues of bank 2
1: at least one write or erase operation is pending in the operation queues of bank 2
Bit 1 WBNE2: Bank 2 write buffer not empty flag
WBNE2 flag is set when embedded flash memory is waiting for new data to complete the
write buffer. In this state the write buffer is not empty. WBNE2 is reset by hardware each time
the write buffer is complete or the write buffer is emptied following one of the event below:
– the application software forces the write operation using FW2 bit in FLASH_CR2
– the embedded flash memory detects an error that involves data loss
– the application software has disabled write operations in this bank
This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the
above listed actions or send the missing data.
0: write buffer of bank 2 empty or full
1: write buffer of bank 2 waiting data to complete
Bit 0 BSY2: Bank 2 busy flag
BSY2 flag is set when an effective write or erase operation is ongoing to bank 2. It is not
possible to know what type of operation is being executed.
BSY2 cannot be forced to 0. It is automatically reset by hardware every time a step in a write,
or erase operation completes.
0: no write or erase operation is executed on bank 2
1: a write or an erase operation is being executed on bank 2.

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RM0433 Embedded flash memory (FLASH)

4.9.27 FLASH clear control register for bank 2 (FLASH_CCR2)

Address offset: 0x114
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CLR_DBECCERR2

CLR_SNECCERR2

CLR_STRBERR2

CLR_WRPERR2
CLR_CRCEND2

CLR_RDSERR2

CLR_RDPERR2

CLR_PGSERR2
CLR_INCERR2
CLR_OPERR2

CLR_EOP2
Res. Res. Res. Res. Res.

w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 CLR_CRCEND2: Bank 2 CRCEND2 flag clear bit
Setting this bit to 1 resets to 0 CRCEND2 flag in FLASH_SR2 register.
Bit 26 CLR_DBECCERR2: Bank 2 DBECCERR2 flag clear bit
Setting this bit to 1 resets to 0 DBECCERR2 flag in FLASH_SR2 register. If the
SNECCERR2 flag of FLASH_SR2 register is cleared to 0, FLASH_ECC_FA2R register is
reset to 0 as well.
Bit 25 CLR_SNECCERR2: Bank 2 SNECCERR2 flag clear bit
Setting this bit to 1 resets to 0 SNECCERR2 flag in FLASH_SR2 register. If the
DBECCERR2 flag of FLASH_SR2 register is cleared to 0, FLASH_ECC_FA2R register is
reset to 0 as well.
Bit 24 CLR_RDSERR2: Bank 2 RDSERR2 flag clear bit
Setting this bit to 1 resets to 0 RDSERR2 flag in FLASH_SR2 register.
Bit 23 CLR_RDPERR2: Bank 2 RDPERR2 flag clear bit
Setting this bit to 1 resets to 0 RDPERR2 flag in FLASH_SR2 register.
Bit 22 CLR_OPERR2: Bank 2 OPERR2 flag clear bit
Setting this bit to 1 resets to 0 OPERR2 flag in FLASH_SR2 register.
Bit 21 CLR_INCERR2: Bank 2 INCERR2 flag clear bit
Setting this bit to 1 resets to 0 INCERR2 flag in FLASH_SR2 register.
Bit 20 Reserved, must be kept at reset value.
Bit 19 CLR_STRBERR2: Bank 2 STRBERR2 flag clear bit
Setting this bit to 1 resets to 0 STRBERR2 flag in FLASH_SR2 register.
Bit 18 CLR_PGSERR2: Bank 2 PGSERR2 flag clear bit
Setting this bit to 1 resets to 0 PGSERR2 flag in FLASH_SR2 register.

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Bit 17 CLR_WRPERR2: Bank 2 WRPERR2 flag clear bit

Setting this bit to 1 resets to 0 WRPERR2 flag in FLASH_SR2 register.
Bit 16 CLR_EOP2: Bank 2 EOP2 flag clear bit
Setting this bit to 1 resets to 0 EOP2 flag in FLASH_SR2 register.
Bits 15:0 Reserved, must be kept at reset value.

4.9.28 FLASH protection address for bank 2 (FLASH_PRAR_CUR2)

Address offset: 0x128
Reset value: 0xXXXX 0XXX (see Table 21: Option byte organization)
This read-only register reflects the current values of corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMEP2

Res. Res. Res. PROT_AREA_END2

r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. PROT_AREA_START2

r r r r r r r r r r r r

Bit 31 DMEP2: Bank 2 PCROP protected erase enable option status bit
If DMEP2 is set to 1, the PCROP protected area in bank 2 is erased when a protection level
regression (change from level 1 to 0) or a bank erase with protection removal occurs.
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 PROT_AREA_END2: Bank 2 PCROP area end status bits
These bits contain the last 256-byte block of the PCROP area in bank 2.
If this address is equal to PROT_AREA_START2, the whole bank 2 is PCROP protected.
If this address is lower than PROT_AREA_START2, no protection is set on bank 2.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 PROT_AREA_START2: Bank 2 PCROP area start status bits
These bits contain the first 256-byte block of the PCROP area in bank 2.
If this address is equal to PROT_AREA_END2, the whole bank 2 is PCROP protected.
If this address is higher than PROT_AREA_END2, no protection is set on bank 2.

4.9.29 FLASH protection address for bank 2 (FLASH_PRAR_PRG2)

Address offset: 0x12C
Reset value: 0xXXXX 0XXX (see Table 21: Option byte organization)
This register is used to program values in corresponding option bits.

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RM0433 Embedded flash memory (FLASH)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMEP2

Res. Res. Res. PROT_AREA_END2

rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. PROT_AREA_START2

rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 DMEP2: Bank 2 PCROP protected erase enable option configuration bit
If DMEP2 is set to 1, the PCROP protected area in bank 2 is erased when a protection level
regression (change from level 1 to 0) or a bank erase with protection removal occurs.

Bits 30:28 Reserved, must be kept at reset value.

Bits 27:16 PROT_AREA_END2: Bank 2 PCROP area end configuration bits
These bits contain the last 256-byte block of the PCROP area in bank 2.
If this address is equal to PROT_AREA_START2, the whole bank 2 is PCROP protected.
If this address is lower than PROT_AREA_START2, no protection is set on bank 2.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 PROT_AREA_START2: Bank 2 PCROP area start configuration bits
These bits contain the first 256-byte block of the PCROP area in bank 2.
If this address is equal to PROT_AREA_END2, the whole bank 2 is PCROP protected.
If this address is higher than PROT_AREA_END2, no protection is set on bank 2.

4.9.30 FLASH secure address for bank 2 (FLASH_SCAR_CUR2)

Address offset: 0x130
Reset value: 0xXXXX 0XXX (see Table 21: Option byte organization)
This read-only register reflects the current values of corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMES2

Res. Res. Res. SEC_AREA_END2

r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. SEC_AREA_START2

r r r r r r r r r r r r

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Embedded flash memory (FLASH) RM0433

Bit 31 DMES2: Bank 2 secure protected erase enable option status bit
If DMES2 is set to 1, the secure protected area in bank 2 is erased when a protection level
regression (change from level 1 to 0) or a bank erase with protection removal occurs.
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 SEC_AREA_END2: Bank 2 secure-only area end status bits
These bits contain the last 256-byte block of the secure-only area in bank 2.
If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.
If this address is lower than SEC_AREA_START2, no protection is set on bank 2.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 SEC_AREA_START2: Bank 2 secure-only area start status bits
These bits contain the first 256-byte block of the secure-only area in bank 2.
If this address is equal to SEC_AREA_END2, the whole bank 2 is secure protected.
If this address is higher than SEC_AREA_END2, no protection is set on bank 2.

4.9.31 FLASH secure address for bank 2 (FLASH_SCAR_PRG2)

Address offset: 0x134
Reset value: 0xXXXX 0XXX (see Table 21: Option byte organization)
This register is used to program values in corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMES2

Res. Res. Res. SEC_AREA_END2

rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. SEC_AREA_START2

rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 DMES2: Bank 2 secure access protected erase enable option configuration bit
If DMES2 is set to 1, the secure access only area in bank 2 is erased when a protection level
regression (change from level 1 to 0) or a bank erase with protection removal occurs.

Bits 30:28 Reserved, must be kept at reset value.

Bits 27:16 SEC_AREA_END2: Bank 2 secure-only area end configuration bits
These bits contain the last of 256 bytes block of the secure-only area in bank 2.
If this address is equal to SEC_AREA_START2, the whole bank 2 is secure access only.
If this address is lower than SEC_AREA_START2, no protection is set on bank 2.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 SEC_AREA_START2: Bank 2 secure-only area start configuration bits
These bits contain the first of 256 bytes block of the secure-only area in bank 2.
If this address is equal to SEC_AREA_END2, the whole bank 2 is secure access only.
If this address is higher than SEC_AREA_END2, no protection is set on bank 2.

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RM0433 Embedded flash memory (FLASH)

4.9.32 FLASH write sector protection for bank 2

(FLASH_WPSN_CUR2R)
Address offset: 0x138
Reset value: 0x0000 00XX
This read-only register reflects the current values of corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. WRPSn2

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 WRPSn2: Bank 2 sector write protection option status byte
Each FLASH_WPSGN_CUR2R bit reflects the write protection status of the corresponding
bank 2 sector (0: sector is write protected; 1: sector is not write protected)

4.9.33 FLASH write sector protection for bank 2

(FLASH_WPSN_PRG2R)
Address offset: 0x13C
Reset value: 0x0000 00XX
This register is used to program values in corresponding option bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. WRPSn2

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 WRPSn2: Bank 2 sector write protection option status byte
Setting WRPSn2 bits to 0 write protects the corresponding bank 2 sector (0: sector is write
protected; 1: sector is not write protected)

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Embedded flash memory (FLASH) RM0433

4.9.34 FLASH CRC control register for bank 2 (FLASH_CRCCR2)

Address offset: 0x150
Reset value: 0x001C 0000
The values in this register can be changed only if CRC_EN bit is set to 1 in FLASH_CR2
register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CRC_BURST

CLEAN_CRC

START_CRC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_BY_SECT
CLEAN_SECT

CRC_SECT
ADD_SECT

ALL_BANK
Res. Res. Res. Res. Res. Res. Res. Res. Res.

w w rw w rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:20 CRC_BURST: Bank 2 CRC burst size
CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit.
00: every burst has a size of 4 flash words (256-bit)
01: every burst has a size of 16 flash words (256-bit)
10: every burst has a size of 64 flash words (256-bit)
11: every burst has a size of 256 flash words (256-bit)
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CLEAN_CRC: Bank 2 CRC clear bit
Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR
register.
Bit 16 START_CRC: Bank 2 CRC start bit
START_CRC bit triggers a CRC calculation on bank 2 using the current configuration. It is not
possible to start a CRC calculation when an option byte change operation is ongoing
because all write accesses to embedded flash memory registers are put on hold until the
option byte change operation has completed.
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 CLEAN_SECT: Bank 2 CRC sector list clear bit
Setting CLEAN_SECT to 1 clears the list of sectors on which the CRC is calculated.
Bit 9 ADD_SECT: Bank 2 CRC sector select bit
Setting ADD_SECT to 1 adds the sector whose number is CRC_SECT to the list of sectors
on which the CRC is calculated.

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RM0433 Embedded flash memory (FLASH)

Bit 8 CRC_BY_SECT: Bank 2 CRC sector mode select bit

When CRC_BY_SECT is set to 1, the CRC calculation is performed at sector level, on the
sectors selected by CRC_SECT.
When CRC_BY_SECT is reset to 0, the CRC calculation is performed on all addresses
between CRC_START_ADDR and CRC_END_ADDR.
Bit 7 ALL_BANK: Bank 2 CRC select bit
When ALL_BANK is set to 1, all bank 2 user sectors are added to the list of sectors on which
the CRC is calculated.
Bits 6:3 Reserved, must be kept at reset value.
Bits 2:0 CRC_SECT: Bank 2 CRC sector number
CRC_SECT is used to select one or more user flash sectors to be added to the CRC
calculation. The CRC can be computed either between two addresses (using registers
FLASH_CRCSADD2R and FLASH_CRCEADD2R) or on a list of sectors. If this latter option
is selected, it is possible to add a sector to the list of sectors by programming the sector
number in CRC_SECT and then setting ADD_SECT. to 1
The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC
computation. CRC_SECT can be set only when CRC_EN of FLASH_CR register is set to 1.
000: sector 0 of bank 2
001: sector 1 of bank 2
...
111: sector 7 of bank 2

4.9.35 FLASH CRC start address register for bank 2

(FLASH_CRCSADD2R)
Address offset: 0x154
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRC_START_ADDR[19:16]

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_START_ADDR[15:2] Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:2 CRC_START_ADDR[19:2]: CRC start address on bank 2
CRC_START_ADDR is used when CRC_BY_SECT is cleared to 0. It must be programmed
to the start address of the bank 2 memory area on which the CRC calculation is performed.
Bits 1:0 Reserved, must be kept at reset value.

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Embedded flash memory (FLASH) RM0433

4.9.36 FLASH CRC end address register for bank 2

(FLASH_CRCEADD2R)
Address offset: 0x158
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRC_END_ADDR[19:16]

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_END_ADDR[15:2] Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:2 CRC_END_ADDR[19:2]: CRC end address on bank 2
CRC_END_ADDR is used when CRC_BY_SECT is cleared to 0. It must be programmed to
the end address of the bank 2 memory area on which the CRC calculation is performed.
Bits 1:0 Reserved, must be kept at reset value.

4.9.37 FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R)

Address offset: 0x160
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. FAIL_ECC_ADDR2

r r r r r r r r r r r r r r r

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:0 FAIL_ECC_ADDR2: Bank 2 ECC error address
When an ECC error occurs (both for single error correction or double detection) during a read
operation from bank 2, the FAIL_ECC_ADDR2 bitfield indicates the address that generated
the error:
Fail address = FAIL_ECC_ADDR2 * 32 + flash memory Bank 2 address offset
FAIL_ECC_ADDR2 is reset when the flag error in the FLASH_SR2 register
(CLR_SNECCERR2 or CLR_DBECCERR2) is reset.
The embedded flash memory programs the address in this register only when no ECC error
flags are set. This means that only the first address that generated an ECC error is saved.

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 0x018
0x014
0x010
0x008
0x004
0x000

0x01C
0x00C
Offset
4.9.38
RM0433

CUR
FLASH_
OPTKEYR
Register

0x00000001
0x00000000
0x00000000
0x00000031
0x00000000
0x00000000
0x00000037

FLASH_SR1
FLASH_CR1
FLASH_ACR

FLASH_CCR1

0xXXXX XXXX
name reset

FLASH_KEYR1

FLASH_OPTCR

FLASH_OPTSR_
0
0
0
SWAP_BANK_OPT SWAP_BANK Res. Res. Res. Res. 31

0
0
0
OPTCHANGEERR OPTCHANGEERRIE Res. Res. Res. Res. 30

0
0

X X X
IO_HSLV Res. Res. Res. Res. Res. 29

0
0
0
Res. Res. Res. Res. CRCRDERRIE1 Res. 28

0
0
0
0
0
Res. Res. CLR_CRCEND1 CRCEND1 CRCENDIE1 Res. 27

0
0
0
0
0
Res. Res. CLR_DBECCERR1 DBECCERR1 DBECCERRIE1 Res. 26

0
0
0
0
0
Res. Res. CLR_SNECCERR1 SNECCERR1 SNECCERRIE1 Res. 25

0
0
0
0
0
Res. Res. CLR_RDSERR1 RDSERR1 RDSERRIE1 Res. 24

0
0
0
0
0

Res. Res. CLR_RDPERR1 RDPERR1 RDPERRIE1 Res. 23

0
0
0
0
0

Res. Res. CLR_OPERRIE1 OPERRIE1 OPERRIE1 Res. 22

0
0
0
0
0

SECURITY Res. CLR_INCERR1 INCERR1 INCERRIE1 0 Res. 21

0

ST_RAM_SIZE
Res. Res. Res. Res. Res. 20

0
0
0
0
0

Res. CLR_STRBERR1 STRBERR1 STRBERRIE1 Res. 19

0
0
0
0
0

IWDG_FZ_SDBY Res. CLR_PGSERR1 PGSERR1 PGSERRIE1 Res. 18

RM0433 Rev 8
0
0
0
0
0

X X X X X
FLASH register map and reset values

IWDG_FZ_STOP Res. CLR_WRPERR1 WRPERR1 WRPERRIE1 Res. 17

0
0
0
0
0

Res. Res. CLR_EOP1 EOP1 EOPIE1 Res. 16

0
0
0

Res. Res. Res. CRC_EN Res. 15

KEY1R

OPTKEYR

0
0

Res. Res. Res. Res. Res. 14

0
0

Res. Res. Res. Res. Res. 13

0
0

Res. Res. Res. Res. Res. 12

RDP
0
0
Table 28. Register map and reset value table

Res. Res. Res. Res. Res. 11

0
0
0

Res. Res. Res. Res. 10

0
0
0

Res. Res. Res. Res. 9

SNB1

0
0
0

Res. Res. Res. Res. 8

0
0
0

NRST_STBY_D1 Res. Res. Res. START1 Res. 7

0
0
0

X X X X X X X X X X
NRST_STOP_D1 Res. Res. Res. FW1 Res. 6
1
0
0
1

Res. Res. Res. Res.

PSIZE1 WRHIGHFREQ
5
1
0
0

0
1

IWDG1_SW MER Res. Res. 4

0
0
0

0
0

BOR_LEV
Res. Res. CRC_BUSY1 BER1 3
0
0
0

0
1

X X X
Res. Res. QW1 SER1
LATENCY
2
0
0
0

0
1

Res. OPTSTART Res. WBNE1 PG1 1

1
0
0

1
1

X
OPT_BUSY OPTLOCK Res. BSY1 LOCK1 0
Embedded flash memory (FLASH)

241/3353
245
Embedded flash memory (FLASH) RM0433

Table 28. Register map and reset value table (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name reset

SWAP_BANK_OPT

NRST_STOP_D1
IWDG_FZ_SDBY
IWDG_FZ_STOP

NRST_STBY_D1
ST_RAM_SIZE

IWDG1_SW
SECURITY

BOR_LEV
IO_HSLV
FLASH_OPTSR_

Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.

Res.
Res.
RDP
PRG
0x020

0xXXXX XXXX X X X X X X X X X X X X X X X X X X X X
CLR_OPTCHANGEERR
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_OPTCCR
0x024

0x00000000 0
DMEP1

FLASH_PRAR_
Res.
Res.
Res.

Res.
Res.
Res.
Res.
PROT_AREA_END1[11:0] PROT_AREA_START1[11:0]
CUR1
0x028

0xXXXX 0XXX X X X X X X X X X X X X X X X X X X X X X X X X X
DMEP1

FLASH_PRAR_
Res.
Res.
Res.

Res.
Res.
Res.
Res.
PROT_AREA_END1[11:0] PROT_AREA_START1[11:0]
PRG1
0x02C

0xXXXX 0XXX X X X X X X X X X X X X X X X X X X X X X X X X X
DMES1

FLASH_SCAR_
Res.
Res.
Res.

Res.
Res.
Res.
Res.

SEC_AREA_END1[11:0] SEC_AREA_START1[11:0]
0x030 CUR1

0xXXXX 0XXX X X X X X X X X X X X X X X X X X X X X X X X X X
DMES1

FLASH_SCAR_
Res.
Res.
Res.

Res.
Res.
Res.
Res.

SEC_AREA_END1[11:0] SEC_AREA_START1[11:0]
PRG1
0x034

0xXXXX 0XXX X X X X X X X X X X X X X X X X X X X X X X X X X

FLASH_WPSN_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

WRPSn1
CUR1R
0x038
0x0000 00XX X X X X X X X X

FLASH_WPSN_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

WRPSn1
0x03C PRG1R

0x0000 00XX X X X X X X X X

FLASH_BOOT_
BOOT_ADD1[15:0] BOOT_ADD0[15:0]
CURR
0x040
0xXXXX XXXX X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

FLASH_BOOT_
BOOT_ADD1[15:0] BOOT_ADD0[15:0]
PRGR
0x044
0xXXXX XXXX X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CRC_BY_SECT
CLEAN_SECT
CRC_BURST

CLEAN_CRC
START_CRC

CRC_SECT
ADD_SECT

ALL_BANK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

FLASH_CRCCR1
0x050

0x001C0000 0 1 0 0 0 0 0 0 0 0 0

242/3353 RM0433 Rev 8

 0x114
0x110
0x108
0x104
0x100
0x060
0x058
0x054

0x10C
0x05C
Offset
RM0433

FA1R

FLASH_
FLASH_
FLASH_
FLASH_

OPTKEYR
Register

CRCDATAR

0x00000000
0x00000000
0x00000031
0x00000000
0x00000000
0x00000037
0x00000000
0x00000000
0x00000000
0x00000000

FLASH_SR2
FLASH_CR2
FLASH_ACR
CRCEADD1R
CRCSADD1R

FLASH_ECC_

FLASH_CCR2
name reset

FLASH_KEYR2

0
0
0
Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
Res. Res. Res. Res. Res. Res. Res. 29

0
0
0
0
Res. Res. CRCRDERRIE2 Res. Res. Res. Res. 28

0
0
0
0
0
0
CLR_CRCEND2 CRCEND2 CRCENDIE2 Res. Res. Res. Res. 27

0
0
0
0
0
0
CLR_DBECCERR2 DBECCERR2 DBECCERRIE2 Res. Res. Res. Res. 26

0
0
0
0
0
0
CLR_SNECCERR2 SNECCERR2 SNECCERRIE2 Res. Res. Res. Res. 25

0
0
0
0
0
0

CLR_RDSERR2 RDSERR2 RDSERRIE2 Res. Res. Res. Res. 24

0
0
0
0
0
0

CLR_RDPERR2 RDPERR2 RDPERRIE2 Res. Res. Res. Res. 23

0
0
0
0
0
0

CLR_OPERR2 OPERR2. OPERRIE2 Res. Res. Res. Res. 22

0
0
0
0
0
0

CLR_INCERR2 INCERR2 INCERRIE2 Res. Res. Res. Res. 21

0
0
0

Res. Res. Res. Res. Res. Res. Res. 20

0
0
0
0
0
0
0
0

CLR_STRBERR2 STRBERR2 STRBERRIE2 Res. Res. 19

0
0
0
0
0
0
0
0

CLR_PGSERR2 PGSERR2 PGSERRIE2 Res. Res. 18

RM0433 Rev 8
0
0
0
0
0
0
0
0

CLR_WRPERR2 WRPERR2 WRPERRIE2 Res. Res. 17

0
0
0
0
0
0
0
0

CLR_EOP2 EOP2 EOPIE2 Res. Res. 16

0
0
0
0
0
0

Res. Res. CRC_EN Res. Res. 15

KEY2R

OPTKEYR

0
0
0
0

0
0
0

Res. Res. SPSS2 Res. 14

CRC_DATA[31:0]

0
0
0

0
0
0

Res. Res. Res. Res. 13

0
0
0

0
0
0

Res. Res. Res. Res. 12

0
0
0

0
0
0

Res. Res. Res. Res. 11

0
0
0
0

0
0
0

Res. Res. Res. 10

0
0
0
0

0
0
0

Res. Res. SNB2[2:0] Res. 9

Table 28. Register map and reset value table (continued)

0
0
0
0

0
0
0

Res. Res. Res. 8

CRC_END_ADDR[31:0]

0
0
0
0

0
0
0
CRC_START_ADDR[31:0]

Res. Res. START2 Res. 7

0
0
0
0

0
0
0

Res. Res. FW2 Res. 6

1
0
0
0

0
0
0

Res. Res.
PSIZE2 WRHIGHFREQ
5

1
0
0
0

0
0
0

4
FAIL_ECC_ADDR1[14:0]

Res. Res.
0
0
0
0

0
0
0
0

Res. CRC_BUSY2
0
BER2 3
0
0
0

0
0
0
0

Res. QW2 SER2

LATENCY
2
0
0
0
0

0
0

Res. WBNE2 PG2 Res. Res. 1

1
0
0
0

0
0

Res. BSY2 LOCK2 Res. Res. 0

Embedded flash memory (FLASH)

243/3353
245
 0x118

0x138
0x134
0x130
0x128
0x124
0x120
0x11C

0x12C
Offset

244/3353
PRG
CUR

PRG2
CUR2
PRG2
CUR2

CUR2R
Register

0x00000000
0x00000001

0x0000 00XX
0xXXXX 0XXX
0xXXXX 0XXX
0xXXXX 0XXX
0xXXXX 0XXX
0xXXXX XXXX
0xXXXX XXXX
name reset

FLASH_SCAR_
FLASH_SCAR_
FLASH_PRAR_
FLASH_PRAR_
FLASH_OPTCR

FLASH_WPSN_
FLASH_OPTSR_
FLASH_OPTSR_

FLASH_OPTCCR
0

X
X
X
X
X
Res. DMES2 DMES2 DMEP2 DMEP2 Res. SWAP_BANK_OPT SWAP_BANK_OPT SWAP_BANK 31

0
X 0
0
Res. Res. Res. Res. Res. CLR_OPTCHANGEERR Res. OPTCHANGEERR OPTCHANGEERRIE 30

X
X
Res. Res. Res. Res. Res. Res. IO_HSLV IO_HSLV Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. 27
Embedded flash memory (FLASH)

Res. Res. Res. Res. Res. 26

Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. 22
Res. Res. SECURITY SECURITY Res. 21
Res. Res.
ST_RAM_SIZE ST_RAM_SIZE
Res. 20
Res. Res. Res. 19

SEC_AREA_END2[11:0]
SEC_AREA_END2[11:0]
PROT_AREA_END2[11:0]
PROT_AREA_END2[11:0]
Res. Res. FZ_IWDG_SDBY IWDG_FZ_SDBY Res. 18

RM0433 Rev 8
X X X X X
X X X X X

Res. Res. FZ_IWDG_STOP IWDG_FZ_STOP Res. 17

X X X X X X X X X X X X
X X X X X X X X X X X X
X X X X X X X X X X X X
X X X X X X X X X X X X
Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. 12
RDP
RDP

Res. Res. Res. 11

Res. Res. Res. 10
Res. Res. Res. 9
Table 28. Register map and reset value table (continued)

Res. Res. Res. 8

Res. nRST_STDY NRST_STBY_D1 Res. 7
X X X X X X X X X X
X X X X X X X X X X

Res. nRST_STOP NRST_STOP_D1 Res. 6

Res. Res. Res. Res. 5
0

Res. IWDG1_SW IWDG1_SW MER 4

Res. Res. 3

WRPSn2
BOR_LEV BOR_LEV
X X X
X X X

SEC_AREA_START2[11:0]
SEC_AREA_START2[11:0]
2

PROT_AREA_START2[11:0]
PROT_AREA_START2[11:0]
Res. Res.
0

Res. Res. Res. OPTSTART 1

1

X X X X X X X X
X X X X X X X X X X X X
X X X X X X X X X X X X
X X X X X X X X X X X X
X X X X X X X X X X X X
X

Res. Res. OPT_BUSY OPTLOCK 0

RM0433
RM0433 Embedded flash memory (FLASH)

Table 28. Register map and reset value table (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name reset
FLASH_WPSN_

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRPSn2
PRG2R
0x13C
0x0000 00XX X X X X X X X X

FLASH_BOOT_
BOOT_ADD1[15:0] BOOT_ADD0[15:0]
CURR
0x140
0xXXXX XXXX X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

FLASH_BOOT_
BOOT_ADD1[15:0] BOOT_ADD0[15:0]
PRGR
0x144
0xXXXX XXXX X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

CRC_BY_SECT
CLEAN_SECT
CRC_BURST

CLEAN_CRC
START_CRC

CRC_SECT
ADD_SECT

ALL_BANK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
FLASH_CRCCR2
0x150

0x001C0000 0 1 0 0 0 0 0 0 0 0 0

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
CRC_START_ADDR[19:2]
CRCS ADD2R
0x154
0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
CRC_END_ADDR[19:2]
CRCEADD2R
0x158
0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_
CRC_DATA[31:0]
0x15C CRCDATAR

0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_ECC_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

FAIL_ECC_ADDR2[15:0]
FA2R
0x160
0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 129 for the register boundary addresses.

RM0433 Rev 8 245/3353

245
Secure memory management (SMM) RM0433

5 Secure memory management (SMM)

5.1 Introduction
STM32H750xB and STM32H753xI microcontrollers offer a first set of protection
mechanisms, which are similar to other STM32 Series:
• Global readout device protection (RDP)
• Write protection (WRP)
• Proprietary code readout protection (PCROP)
A detailed description of these protection mechanisms is given in Section 4: Embedded
flash memory (FLASH).
STM32H750xB and STM32H753xI also offer an additional enhanced protection mode, the
Secure access mode, that makes possible the development of user-defined secure services
(e.g. secure firmware update or secure boot) and guarantees of a safe execution and
protection of both code and data. This mechanism is described in details in Section 5.3:
Secure access mode, Section 5.4: Root secure services (RSS) and Section 5.5: Secure
user software.
The secure memory management unit is contained inside the D1 domain.

5.2 Glossary
The following terms will be used in herein:

Table 29. List of preferred terms

Term Description

Device Security Level

Device state which allows the access to the user Flash memory, the option
Standard mode
bytes and the bootloader area.
Secure access mode Device state which allows the access to all the memory areas of the device.

Memory areas

System memory ST reserved memory area used to store ST ROM code.

User flash memory Flash memory area used to store user code and data.
This area can be configured to be accessed once after reset and be hidden
Secure user
for the firmware stored in the user flash memory after the code stored in this
memory/area(1)
area is executed.

246/3353 RM0433 Rev 8

RM0433 Secure memory management (SMM)

Table 29. List of preferred terms (continued)

Term Description

Software services

STMicroelectronics software executed at reset which allows the download of

Bootloader
firmware from regular communication ports.
Root secure services
STMicroelectronics software which allows the access to secure services.
(RSS)
User software executed once after reset, which can be used to implement
Secure user software secure boot and secure firmware update (SFU).
Secure user software is located in secure user memory.
1. Secure user memory/areas are also named secure-hide protected (HDP) memory/areas.

5.3 Secure access mode

Some sensitive functions require safe execution from potential malicious software attacks.
Secure firmware update (SFU) software is a good example of code that requires a high level
of protection since it handles secret data (such as cryptographic keys) that shall not be
retrieved by other processes.
STM32H750xB and STM32H753xI microcontrollers feature secure memory areas with
restricted access. They allow building secure services that will be executed prior to any user
application. These secure areas, together with the software they contain, are only
accessible when configuring the device in Secure access mode.
Figure 15 gives an overview of flash memory areas and services in Standard and Secure
access modes.

RM0433 Rev 8 247/3353

253
Secure memory management (SMM) RM0433

Figure 15. Flash memory areas and services in Standard and Secure access modes

Option bytes Option bytes

(Bank 1 only) (Bank 1 only)

Bootloader Bootloader
System
Secure bootloader
memory
RSS

Secure user Secure user

software memory
User
User software
memory

User software

Standard Secure access

mode mode

MSv43701V3

1. The protected areas that can only be accessed in Secure access mode are shown in blue.
2. A single secure user area can be defined for each bank.

5.3.1 Associated features

The Secure access mode can be configured through option bytes. When it is set, it enables
access to:
• STMicroelectronics root secure services to set secure user areas (see Section 5.4:
Root secure services (RSS))
• Secure user memory which embeds secure user code and data.
For a summary of access rights for each core, refer to Section 5.6: Summary of flash
protection mechanisms.

5.3.2 Boot state machine

In Secure access mode, booting is forced in the RSS whatever the boot configuration (boot
pins and boot addresses). The RSS can either set a secure user memory area if one has
been requested (see Section 5.5.2: Setting secure user memory areas) or jump directly to
the existing secure user memory. The code located in secure user memory is executed
before the main user application and the bootloader. If no service is required and no secure
area is defined, the RSS jumps to the boot address selected by BOOT0 pin value.
Figure 16 shows the boot state machine.

248/3353 RM0433 Rev 8

RM0433 Secure memory management (SMM)

Figure 16. Bootloader state machine in Secure access mode

Secure access mode System Standard mode

Reset

resetAndInitializeSecureAre
yes as service requested & no No
secure area already set?
Set secure Any secure area is
No Boot @
area(s) set ?

Reset
Bank swapping
Yes
on?
No
Number of Number of
1 2
1 Secure area 2 Secure area
Bank Secure boot@= Secure boot@= Secure boot@=
swapping off Secure User area of Secure User area of Secure User area closer
Bank 1 Bank 1 or 2 to current boot @
Reset

Jump to Secure boot @ RSS

Secure User Area 1 or 2

exitSecureArea (User
application @) User application
MSv50671V1

1. On STM32H750xB devices, only Bank 1 secure user area is applicable and bank swapping is not available.
1.

5.3.3 Secure access mode configuration

Enabling Secure access mode
There is no restriction on how to activate Secure access mode on the device. It is configured
through the SECURITY option bit in FLASH_OPTSR_CUR register (see Section 4.9.8:
FLASH option status register (FLASH_OPTSR_CUR)).
The Secure access mode becomes active after a system reset.

Disabling Secure access mode

Disabling Secure access mode is a more sensitive task as it can only be done if no more
protected code exists on the device. As a result, to come back to Standard mode, secure
user memories and PCROP/execute-only areas shall be removed before clearing the
SECURITY option bit in the FLASH_OPTSR_CUR register.
Protected areas can be removed by performing a flash mass erase (refer to Section 4.3.10:
FLASH erase operations for more details on mass erase sequence).

RM0433 Rev 8 249/3353

253
Secure memory management (SMM) RM0433

5.4 Root secure services (RSS)

The root secure services (RSS) are STMicroelectronics ROM code stored on the device.
They are part of the security features. These firmware services are available in Secure
access mode (see Section 4.5.5: Secure access mode.
Table 30 gives the addresses of the application programming interface (API) described in
the following sections.

Table 30. RSS API addresses

RSS RSS API address

RSS_getVersion 0x1FF0 9500

RSS_exitSecureArea 0x1FF0 9514
RSS_resetAndInitializeSecureAreas 0x1FF0 9518

5.4.1 Secure area setting service

STMicroelectronics provides a service to perform the initialization of secure areas. This
service can be called only once. It is executed after a system reset in Secure access mode
prior to any other software stored in the device.
Caution: RSS software cannot be accessed (read, write, execute and debug) when the
STM32H750xB and STM32H753xI operate in Standard mode. The service can be
automatically accessed with ST programming tool, STM32CubeProgrammer, or called
through a direct call to the resetAndInitializeSecureAreas function defined below.

resetAndInitializeSecureAreas

Prototype void resetAndInitializeSecureAreas(RSS_SecureArea_t area)

Arguments Secure user areas start and end addresses. One or two secure user areas can be set.

This service sets secure user area boundaries, following the values stored in the option
byte registers:
– SEC_AREA_START1 and SEC_AREA_END1 for bank 1
Description
– SEC_AREA_START2 and SEC_AREA_END2 for bank 2
This service can be used only when a secure area is set for the first time.
A system reset is triggered after service completion.

5.4.2 Secure area exiting service

The RSS also provides the exitSecureArea service. This service must be called to jump to
user application. It allows closing safely the secure user area to guarantee that its content
can no more be accessed.
Contrary to the resetAndInitializeSecureAreas service, it does not trigger any system reset.
exitSecureArea function is defined below:

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exitSecureArea

Prototype void exitSecureArea(unsigned int vectors)

Arguments Address of application vectors where to jump after exit

This service is used to exit from secure user software and jump to user main
Description application.
There is no system reset triggered by this service

5.5 Secure user software

A secure user software is a trusted piece of code that is executed after device power-on or
after a system reset. It allows building secure applications such as:
• code signature or integrity checking (user secure boot).
• software license checking
• secure firmware update
• secure initialization

5.5.1 Access rules

Only accessible in Secure access mode, the secure user software is stored in the secure
memory areas.
Only one user secure area can be configured per bank. If two secure areas are defined, the
secure software that is executed is the one closer to current boot address.
After secure user software execution, the code shall jump to the main user application and
prevent access to the secure user area. This is done by calling exitSecureAreas secure
service with the application code address given as parameter.
Once in the application code, any access to the secure user area triggers a flash error.

5.5.2 Setting secure user memory areas

One secure area of configurable size can be set in each bank. The size of each area can be
set from 512 bytes to full bank with a granularity of 256 bytes:
• Secure area in bank 1
Boundaries are configured through SEC_AREA_START1 and SEC_AREA_END1
option bits in FLASH_SCAR_CUR1 (see Section 4.9.13: FLASH secure address for
bank 1 (FLASH_SCAR_CUR1)).
• Secure area in bank 2
Boundaries are configured through SEC_AREA_START2 and SEC_AREA_END2
option bits in FLASH_SCAR_CUR2 (see Section 4.9.30: FLASH secure address for
bank 2 (FLASH_SCAR_CUR2)).
Note: If the secure area start address is equal to the secure area end address, the whole bank is
considered as secure protected.
The above option bits can only be initialized through exitandinitializeSecureAreas service.

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If a secure area already exists, the secure user area code can update its own secure user
area size or create a new one in the other bank.

5.6 Summary of flash protection mechanisms

Figure 17 and Table 31 summarize the access rights of the different flash memory areas,
both in Secure access and Standard modes.

Figure 17. Core access to flash memory areas

RSS
Bootloader

Secure user Secure user

memory 1 memory 2

PCROP PCROP

User Memory 1 User Memory 2

Bank 1 Bank 2

Secure access mode only

MSv43705V3

Table 31. Summary of flash protected areas access rights

Access type Software area Security mode Access

PCROP Any ✓
Execution Secure user software Secure access ✓ (1)
Root secure services Secure access ✓ (1)
PCROP Any No
Read access Secure user software Secure access ✓(1)
Root secure services Secure access ✓ (1)
PCROP Any No
Debug access Secure user software Secure access No
Root secure services Secure access No

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1. Access rights granted after reset until code completion only.

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6 Power control (PWR)

6.1 Introduction
The Power control section (PWR) provides an overview of the supply architecture for the
different power domains and of the supply configuration controller.
It also describes the features of the power supply supervisors and explains how the VCORE
supply domain is configured depending on the operating modes, the selected performance
(clock frequency) and the voltage scaling.

6.2 PWR main features

• Power supplies and supply domains
– Core domains (VCORE)
– VDD domain
– Backup domain (VSW, VBKP)
– Analog domain (VDDA)
• System supply voltage regulation
– Voltage regulator (LDO)
• Peripheral supply regulation
– USB regulator
• Power supply supervision
– POR/PDR monitor
– BOR monitor
– PVD monitor
– AVD monitor
– VBAT thresholds
– Temperature thresholds
• Power management
– VBAT battery charging
– Operating modes
– Voltage scaling control
– Low-power modes

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6.3 PWR block diagram

Figure 18. Power control block diagram

32-bit RCC
AHB Register
bus interface

PDR_ON POR/PDR pwr_por_rst

BOR pwr_bor_rst
VDD
Backup domain

TEMP Power
VBAT charging thresholds management
pwr_d1_wkup
pwr_d2_wkup
VBAT VBAT pwr_d3_wkup
System Supply thresholds

VDDLDO Voltage
VCAP Regulator Voltage
Scaling

VDDA
VSSA exti_c_wkup
Analog domain
VREF+ exti_d3_wkup
VREF-
pwr_wkupx_wkup
EXTI
VDD50USB
USB Regulator
VDD33USB pwr_pvd_wkup
PVD & AVD
VSS pwr_avd_wkup

MSv40894V4

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6.3.1 PWR pins and internal signals

Table 32 lists the PWR inputs and output signals connected to package pins or balls, while
Table 33 shows the internal PWR signals.

Table 32. PWR input/output signals connected to package pins or balls

Signal
Pin name Description
type

Supply
VDD Main I/O and VDD domain supply input
input
Supply
VDDA External analog power supply for analog peripherals
input
Supply
VREF+,VREF- Input/ External reference voltage for ADCs and DAC
Outputs
Supply
VBAT Backup battery supply input
input
Supply
VDDLDO Voltage regulator supply input
input
Supply
VCAP Input/ Digital core domain supply
Output
Supply
VDD50USB USB regulator supply input
input
Supply
VDD33USB Input/ USB regulator supply output
Output
Supply
VSS Main ground
input
Digital
AHB inputs/ AHB register interface
outputs
Digital
PDR_ON Power Down Reset enable
input

Table 33. PWR internal input/output signals

Signal
Signal name Description
type

Digital
pwr_pvd_wkup Programmable voltage detector output
output
Digital
pwr_avd_wkup Analog voltage detector output
output
Digital
pwr_wkupx_wkup CPU wakeup signals (x=1 to 6)
output

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Table 33. PWR internal input/output signals (continued)

Signal
Signal name Description
type

Digital
pwr_por_rst Power-on reset
output
Digital
pwr_bor_rst Brownout reset
output
Digital
exti_c_wkup CPU wakeup request
input
Digital
exti_d3_wkup D3 domain wakeup request
input
Digital
pwr_d1_wkup D1 domain bus matrix clock wakeup request
output
Digital
pwr_d2_wkup D2 domain bus matrix clock wakeup request
output
Digital
pwr_d3_wkup D3 domain bus matrix clock wakeup request
output

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6.4 Power supplies

The device requires VDD power supply as well as independent supplies for VDDLDO, VDDA,
VDDUSB, and VCAP. It also provides regulated supplies for specific functions (voltage
regulator, USB regulator).
• VDD external power supply for I/Os and system analog blocks such as reset, power
management and oscillators
• VBAT optional external power supply for backup domain when VDD is not present (VBAT
mode)
This power supply shall be connected to VDD when no battery is used.
• VDDLDO external power supply for voltage regulator
• VCAP digital core domain supply
This power supply is independent from all the other power supplies:
– When the voltage regulator is enabled, VCORE is delivered by the internal voltage
regulator.
– When the voltage regulator is disabled, VCORE is delivered by an external power
supply through VCAP pin.
• VDDA external analog power supply for ADCs, DACs, OPAMPs, comparators and
voltage reference buffers
This power supply is independent from all the other power supplies.
• VREF+ external reference voltage for ADC and DAC.
– When the voltage reference buffer is enabled, VREF+ and VREF- are delivered by
the internal voltage reference buffer.
– When the voltage reference buffer is disabled, VREF+ is delivered by an
independent external reference supply.
• VSSA separate analog and reference voltage ground.
• VDD50USB external power supply for USB regulator.
• VDD33USB USB regulator supply output for USB interface.
– When the USB regulator is enabled, VDD33USB is delivered by the internal USB
regulator.
– When he USB regulator is disabled, VDD33USB is delivered by an independent
external supply input.
• VSS common ground for all supplies and analog regulator.
Note: Depending on the operating power supply range, some peripherals might be used with
limited features and performance. For more details, refer to section “General operating
conditions” of the device datasheets.

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Figure 19. Power supply overview

VDD33USB

VDD50USB
VSS USB
IOs

USB
regulator

VSS
VCAP
Core domain (VCORE)
Voltage
VDDLDO
regulator

Power

Power
switch

switch
VSS
D3 domain
(System
Level shifter

logic, D1 domain
IO EXTI, D2 domain (CPU, peripherals,
IOs (peripherals, RAM)
logic Peripherals,
RAM) RAM) Flash

VSS

VDD domain
LSI, HSI,
VDD CSI, HSI48, Power
VBAT HSE, PLLs switch
Backup domain
charging
VSW Backup VBKP
VBAT regulator
Power switch

LSE, RTC,
Wakeup logic, Backup
BKUP IO backup RAM
IOs logic registers, Reset

VSS
VDDA Analog domain VSS

REF_BUF ADC, DAC

VREF+ VREF+ OPAMP,
Comparator
VREF- VREF-
VSSA

MSv40895V7

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By configuring the voltage regulator the supply configurations shown in Figure 20 are
supported for the VCORE core domain and an external supply.

Figure 20. System supply configurations

VCAP External supply VCAP

VDDLDO VCORE VDD VDDLDO VCORE
VDD
V reg V reg
VSS (on) VSS (off)

LDO Supply Bypass

MSv41901V1

The different supply configurations are controlled through the LDOEN and BYPASS bits in
PWR control register 3 (PWR_CR3) register according to Table 34.

Table 34. Supply configuration control

BYPASS
LDOEN

Supply
Description
configuration

Default – VCORE Power Domains are supplied from the LDO according to
1 0
configuration VOS.
– VCORE Power Domains are supplied from the LDO according to
VOS.
LDO supply 1 0
– LDO power mode (Main, LP, Off) will follow system low-power
modes.
– VCORE supplied from external source
LDO Bypass 0 1
– LDO bypassed, voltage monitoring still active.
0 0 – Illegal combination, the default configuration is kept. (write data
Illegal
1 1 will be ignored).

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6.4.1 System supply startup

The system startup sequence from power-on in different supply configurations is the
following (see Figure 21 for LDO supply):
1. When the system is powered on, the POR monitors VDD supply. Once VDD is above the
POR threshold level, the voltage regulator is enabled in the default supply
configuration:
– The Voltage converter output level is set at 1.0 V in accordance with the VOS3
level configured in PWR D3 domain control register (PWR_D3CR).
2. The system is kept in reset mode as long as VCORE is not correct.
3. Once VCORE is correct, the system is taken out of reset and the HSI oscillator is
enabled.
4. Once the oscillator is stable, the system is initialized: Flash memory and option bytes
are loaded and the CPU starts in limited run mode (Run*).
5. The software shall then initialize the system including supply configuration
programming in PWR control register 3 (PWR_CR3). Once the supply configuration
has been configured, the ACTVOSRDY bit in PWR control status register 1
(PWR_CSR1) shall be checked to guarantee valid voltage levels:
a) As long as ACTVOSRDY indicates that voltage levels are invalid, the system is in
Run* mode, write accesses to the RAMs are not permitted and VOS shall not be
changed.
b) Once ACTVOSRDY indicates that voltage levels are valid, the system is in normal
Run mode, write accesses to RAMs are allowed and VOS can be changed.
The software has to program the supply configuration in PWR control register 3
(PWR_CR3).

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Figure 21. Device startup with VCORE supplied from voltage regulator

POR threshold

VDD, VDDLDO

pwr_por_rst

1.0V (VOS3)

VCORE

ACTVOSRDY

VOSRDY
Wait
Power Wait
Operating mode Reset HW system Init Run*(1) ACTVOS Run
down Oscillator
RDY(2)

ck_sys

Supply configuration
Supply configuration Default configuration
programmed

BYPASS

LDOEN

SCUEN
(1) (2) (3) (4) (5a) (5b)

MSv41900V3

1. In Run* mode, write operations to RAM are not allowed.

2. Write operations to RAM are allowed and VOS can be changed only when ACTVOSRDY is valid.
When exiting from Standby mode, the supply configuration is known by the system since the
PWR control register 3 (PWR_CR3) register content is retained. However the software shall
still wait for the ACTVOSRDY bit to be set in PWR control status register 1 (PWR_CSR1) to
indicate VCORE voltage levels are valid, before performing write accesses to RAM or
changing VOS.
For packages where VDDLDO is internally connected to VDD, when VCORE is supplied in
Bypass mode (LDO OFF), the VCORE voltage must first settle at a default level higher than
1.1 V. Due to the LDO default state after power-up (enabled by default), the external VCORE
voltage must remain higher than 1.1 V until the LDO is disabled by software.
When the LDO is disabled, the external VCORE voltage can be adjusted according to the
user application needs (refer to section General operating conditions of the datasheet for
details on VCORE level versus the maximum operating frequency).

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Figure 22. Device startup with VCORE supplied in Bypass mode

from external regulator

POR threshold
VDD, VDDLDO

pwr_por_rst

Min V12 at startup 1.1V

VCAP/V12

1.2 V

VCORE

Power Wait
Operating mode Reset HW system Init Run* Run
down Oscillator

ck_sys

Supply
Default configuration BYPASS mode
configuration

BYPASS

LDOEN

SCUEN

MSv62411V2

Note: Before accessing the RAM, it is strongly recommended to switch to the correct VOS setting
depending on the external voltage level as soon as possible.

6.4.2 Core domain

The VCORE core domain supply can be provided by the voltage regulator or by an external
supply (VCAP). VCORE supplies all the digital circuitries except for the backup domain and
the Standby circuitry. The VCORE domain is split into 3 sections:
• D1 domain containing the CPU (Cortex®-M7), Flash memory and peripherals.
• D2 domain containing peripherals.
• D3 domain containing the system control, I/O logic and low-power peripherals.
When a system reset occurs, the voltage regulator is enabled and supplies VCORE. This
allows the system to start up in any supply configurations (see Figure 20).

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After a system reset, the software shall configure the used supply configuration in PWR
control register 3 (PWR_CR3) register before changing VOS in PWR D3 domain control
register (PWR_D3CR) or the RCC ck_sys frequency. The different system supply
configurations are controlled as shown in Table 34.

Voltage regulator
The embedded voltage regulator (LDO) requires external capacitors to be connected to
VCAP pins.
The voltage regulator provides three different operating modes: Main (MR), Low-power (LP)
or Off. These modes will be used depending on the system operating modes (Run, Stop and
Standby).
• Run mode
The LDO regulator is in Main mode and provides full power to the VCORE domain (core,
memories and digital peripherals). The regulator output voltage can be scaled by
software to different voltage levels (VOS0(a), VOS1, VOS2, and VOS3) that are
configured through VOS bits in PWR D3 domain control register (PWR_D3CR). The
VOS voltage scaling allows optimizing the power consumption when the system is
clocked below the maximum frequency. By default VOS3 is selected after system
reset. VOS can be changed on-the-fly to adapt to the required system performance.
• Stop mode
The voltage regulator supplies the VCORE domain to retain the content of registers and
internal memories.
The regulator can be kept in Main mode to allow fast exit from Stop mode, or can be set
in LP mode to obtain a lower VCORE supply level and extend the exit-from-Stop latency.
The regulator mode is selected through the SVOS and LPDS bits in PWR control
register 1 (PWR_CR1). Main mode and LP mode are allowed if SVOS3 voltage scaling
is selected, while only LP mode is possible for SVOS4 and SVOS5 scaling. Due to a
lower voltage level for SVOS4 and SVOS5 scaling, the Stop mode consumption can be
further reduced.
• Standby mode
The voltage regulator is OFF and the VCORE domains are powered down. The content
of the registers and memories is lost except for the Standby circuitry and the backup
domain.
Note: For more details, refer to the voltage regulator section in the datasheets.

6.4.3 PWR external supply

When VCORE is supplied from an external source, different operating modes can be used
depending on the system operating modes (Run, Stop or Standby):
• In Run mode
The external source supplies full power to the VCORE domain (core, memories and
digital peripherals). The external source output voltage is scalable through different
voltage levels (VOS0, VOS1, VOS2 and VOS3). The externally applied voltage level
shall be reflected in the VOS bits of PWR_D3CR register. The RAMs shall only be

a. VOS0 corresponds to VCORE boost allowing to reach the system maximum frequency (refer to Section :
VOS0 activation/deactivation sequence)

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accessed for write operations when the external applied voltage level matches VOS
settings.
• In Stop mode
The external source supplies VCORE domain to retain the content of registers and
internal memories. The regulator can select a lower VCORE supply level to reduce the
consumption in Stop mode.
• In Standby mode
The external source shall be switched OFF and the VCORE domains powered down.
The content of registers and memories is lost except for the Standby circuitry and the
backup domain. The external source shall be switched ON when exiting Standby mode.

6.4.4 Backup domain

To retain the content of the backup domain (RTC, backup registers and backup RAM) when
VDD is turned off, VBAT pin can be connected to an optional standby voltage which is
supplied from a battery or from an another source.
The switching to VBAT is controlled by the power-down reset embedded in the Reset block
that monitors the VDD supply.

Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR

is detected, the power switch between VBAT and VDD remains
connected to VBAT.
During the a startup phase, if VDD is established in less than
tRSTTEMPO (see the datasheet for the value of tRSTTEMPO) and
VDD > VBAT + 0.6 V, a current may be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.

When the VDD supply is present, the backup domain is supplied from VDD. This allows
saving VBAT power supply battery life time.
If no external battery is used in the application, it is recommended to connect VBAT
externally to VDD through a 100 nF external ceramic capacitor.
When the VDD supply is present and higher than the PDR threshold, the backup domain is
supplied by VDD and the following functions are available:
• PC14 and PC15 can be used either as GPIO or as LSE pins.
• PC13 can be used either as GPIO or as RTC_AF1 or RTC_TAMP1 pin assuming they
have been configured by the RTC.
• PI8/RTC_TAMP2 and PC1/RTC_TAMP3 when they are configured by the RTC as
tamper pins.

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Note: Since the switch only sinks a limited amount of current, the use of PC13 to PC15 and PI8
GPIOs is restricted: only one I/O can be used as an output at a time, at a speed limited to
2 MHz with a maximum load of 30 pF. These I/Os must not be used as current sources (e.g.
to drive an LED).
In VBAT mode, when the VDD supply is absent and a supply is present on VBAT, the backup
domain is supplied by VBAT and the following functions are available:
• PC14 and PC15 can be used as LSE pins only.
• PC13 can be used as RTC_AF1 or RTC_TAMP1 pin assuming they have been
configured by the RTC.
• PI8/RTC_TAMP2 and PC1/RTC_TAMP3 when they are configured by the RTC as
tamper pins.

Accessing the backup domain

After reset, the backup domain (RTC registers and RTC backup registers) is protected
against possible unwanted write accesses. To enable access to the backup domain, set the
DBP bit in the PWR control register 1 (PWR_CR1).
For more detail on RTC and backup RAM access, refer to Section 8: Reset and Clock
Control (RCC).

Backup RAM
The backup domain includes 4 Kbytes of backup RAM accessible in 32-bit, 16-bit or 8-bit
data mode. The backup RAM is supplied from the Backup regulator in the backup domain.
When the Backup regulator is enabled through BREN bit in PWR control register 2
(PWR_CR2), the backup RAM content is retained even in Standby and/or VBAT mode (it can
be considered as an internal EEPROM if VBAT is always present.)
The Backup regulator can be ON or OFF depending whether the application needs the
backup RAM function in Standby or VBAT modes.
The backup RAM is not mass erased by an tamper event, instead it is read protected to
prevent confidential data, such as cryptographic private key, from being accessed. To re-
gain access to the backup RAM after a tamper event, the memory area needs to be first
erased. The backup RAM can be erased:
• through the Flash interface when a protection level change from level 1 to level 0 is
requested (refer to the description of Read protection (RDP) in the Flash programming
manual).
• After a tamper event, by performing a dummy write with zero as data to the backup
RAM.

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Figure 23. Backup domain

VBAT
VSW
VDD
Backup domain

VDDLDO Voltage Backup

regulator regulator

Backup IOs
VCAP

VCORE domain
Backup
RAM

interface
Backup

RTC LSE

MSv40338V2

6.4.5 VBAT battery charging

When VDD is present, the external battery connected to VBAT can be charged through an
internal resistance.
VBAT charging can be performed either through a 5 k Ω resistor or through a 1.5 k Ω resistor,
depending on the VBRS bit value in PWR control register 3 (PWR_CR3).
The battery charging is enabled by setting the VBE bit in PWR control register 3
(PWR_CR3). It is automatically disabled in VBAT mode.

6.4.6 Analog supply

Separate VDDA analog supply
The analog supply domain is powered by dedicated VDDA and VSSA pads that allow the
supply to be filtered and shielded from noise on the PCB, thus improving ADC and DAC
conversion accuracy:
• The analog supply voltage input is available on a separate VDDA pin.
• An isolated supply ground connection is provided on VSSA pin.

Analog reference voltage VREF+/VREF-

To achieve better accuracy low-voltage signals, the ADC and DAC also have a separate
reference voltage, available on VREF+ pin. The user can connect a separate external
reference voltage on VREF+.
The VREF+ controls the highest voltage, represented by the full scale value, the lower
voltage reference (VREF-) being connected to VSSA.

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When enabled by ENVR bit in the VREFBUF control and status register (see Section 27:
Voltage reference buffer (VREFBUF)), VREF+ is provided from the internal voltage reference
buffer. The internal voltage reference buffer can also deliver a reference voltage to external
components through VREF+/VREF- pins.
When the internal voltage reference buffer is disabled by ENVR, VREF+ s delivered by an
independent external reference supply voltage.

6.4.7 USB regulator

The USB transceivers are supplied from a dedicated VDD33USB supply that can be provided
either by the integrated USB regulator, or by an external USB supply.
When enabled by USBREGEN bit in PWR control register 3 (PWR_CR3), the VDD33USB is
provided from the USB regulator. Before using VDD33USB, check that it is available by
monitoring USB33RDY bit in PWR control register 3 (PWR_CR3). The VDD33USB supply
level detector shall be enabled through USB33DEN bit in PWR_CR3 register.
When the USB regulator is disabled through USBREGEN bit, VDD33USB can be provided
from an external supply. In this case VDD33USB and VDD50USB shall be connected together.
The VDD33USB supply level detector must be enabled through USB33DEN bit in PWR_CR3
register before using the USB transceivers.
For more information on the USB regulator (see Section 57: USB on-the-go high-speed
(OTG_HS)).

Figure 24. USB supply configurations

VDD33USB VDD30 VDD33USB

VDD50 VDD50USB VDD50USB

USB USB
VSS regulator VSS regulator
(ON) (Bypass)

USB regulator supply External USB supply

MSv40339V1

6.5 Power supply supervision

Power supply level monitoring is available on the following supplies:
• VDD via POR/PDR (see Section 6.5.1), BOR (see Section 6.5.2) and PVD monitor (see
Section 6.5.3)
• VDDA via AVD monitor (see Section 6.5.4)
• VBAT via VBAT threshold (see Section 6.5.5)
• VSW via rst_vsw, which keeps VSW domain in Reset mode as long as the level is not
OK.
• VBKP via a BRRDY bit in PWR control register 2 (PWR_CR2).
• VDD33USB via USBRDY bit in PWR control register 3 (PWR_CR3).

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6.5.1 Power-on reset (POR)/power-down reset (PDR)

The system has an integrated POR/PDR circuitry that ensures proper startup operation.
The system remains in Reset mode when VDD is below a specified VPOR threshold, without
the need for an external reset circuit. Once the VDD supply level is above the VPOR
threshold, the system is taken out of reset (see Figure 25). For more details concerning the
power-on/power-down reset threshold, refer to the electrical characteristics section of the
datasheets.
The PDR can be enabled/disabled by the device PDR_ON input pin.

Figure 25. Power-on reset/power-down reset waveform

VDD

POR

hysteresis PDR

Temporisation TRSTTEMPO

pwr_por_rst
MSv40340V2

1. For thresholds and hysteresis values, please refer to the datasheets.

6.5.2 Brownout reset (BOR)

During power-on, the Brownout reset (BOR) keeps the system under reset until the VDD
supply voltage reaches the specified VBOR threshold.
The VBOR threshold is configured through system option bytes. By default, BOR is OFF. The
following programmable VBOR thresholds can be selected:
• BOR OFF (VBOR0)
• BOR Level 1 (VBOR1)
• BOR Level 2 (VBOR2)
• BOR Level 3 (VBOR3)
For more details on the brown-out reset thresholds, refer to the section “Electrical
characteristics” of the product datasheets.
A system reset is generated when the BOR is enabled and VDD supply voltage drops below
the selected VBOR threshold.

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BOR can be disabled by programming the system option bytes. To disable the BOR
function, VDD must have been higher than VBOR0 to start the system option byte
programming sequence. The power-down is then monitored by the PDR (see
Section 6.5.1).

Figure 26. BOR thresholds

VDD

BORrise

hysteresis
BORfall

pwr_bor_rst

MSv40341V2

1. For thresholds and hysteresis values, please refer to the datasheets.

6.5.3 Programmable voltage detector (PVD)

The PVD can be used to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the PWR control register 1 (PWR_CR1). The PVD can also
be used to monitor a voltage level on the PVD_IN pin. In this case PVD_IN voltage is
compared to the internal VREFINT level.
The PVD is enabled by setting the PVDE bit in PWR control register 1 (PWR_CR1).
A PVDO flag is available in the PWR control status register 1 (PWR_CSR1) to indicate if
VDD or PVD_IN voltage is higher or lower than the PVD threshold. This event is internally
connected to the EXTI and can generate an interrupt, assuming it has been enabled through
the EXTI registers. The pwr_pvd_wkup output interrupt can be generated when VDD or
PVD_IN voltage drops below the PVD threshold and/or when VDD or PVD_IN voltage rises
above the PVD threshold depending on EXTI rising/falling edge configuration. As an
example the service routine could perform emergency shutdown tasks.

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Figure 27. PVD thresholds

VDD or PVD_IN

PVDrise

hysteresis PVDfall

PVDO

PVDEN

SW enable PDR reset

MSv40342V2

1. For thresholds and hysteresis values, please refer to the datasheets.

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6.5.4 Analog voltage detector (AVD)

The AVD can be used to monitor the VDDA supply by comparing it to a threshold selected by
the ALS[1:0] bits in the PWR control register 1 (PWR_CR1).
The AVD is enabled by setting the AVDEN bit in PWR control register 1 (PWR_CR1).
An AVDO flag is available in the PWR control status register 1 (PWR_CSR1) to indicate
whether VDDA is higher or lower than the AVD threshold. This event is internally connected
to the EXTI and can generate an interrupt if enabled through the EXTI registers. The
pwr_avd_wkup interrupt can be generated when VDDA drops below the AVD threshold and/or
when VDDA rises above the AVD threshold depending on EXTI rising/falling edge
configuration. As an example the service routine could indicate when the VDDA supply drops
below a minimum level.

Figure 28. AVD thresholds

VDDA

AVDrise

hysteresis AVDfall

AVDO

AVDEN

SW enable SW disable

MSv40343V1

1. For thresholds and hysteresis values, please refer to the datasheets.

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6.5.5 Battery voltage thresholds

The battery voltage supply monitors the backup domain VSW level. Vsw is monitored by
comparing it with two threshold levels: VBAThigh and VBATlow. VBATH and VBATL flags in the
PWR control register 2 (PWR_CR2), indicate if VSW is higher or lower than the threshold.
The VBAT supply monitoring can be enabled/disabled via MONEN bit in PWR control
register 2 (PWR_CR2). When it is enabled, the battery voltage thresholds increase power
consumption. As an example the VSW levels monitoring could be used to trigger a tamper
event for an over or under voltage of the RTC power supply domain (available in VBAT
mode).
VBATH and VBATL are connected to RTC tamper signals (see Section 46: Real-time clock
(RTC)).
Note: Battery voltage monitoring is only available when the backup regulator is enabled (BREN bit
set in PWR control register 2 (PWR_CR2)).
When the device does not operate in VBAT mode, the battery voltage monitoring checks
VDD level. When VDD is available, VSW is connected to VDD through the internal power
switch (see Section 6.4.4: Backup domain).

Figure 29. VBAT thresholds

VBAT

VBAThigh

VBATlow

VBATH

VBATL

MSv40344V1

1. For thresholds and hysteresis values, please refer to the datasheets.

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6.5.6 Temperature thresholds

The junction temperature can be monitored by comparing it with two threshold levels,
TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR control register 2
(PWR_CR2), indicate whether the device temperature is higher or lower than the threshold.
The temperature monitoring can be enabled/disabled via MONEN bit in PWR control
register 2 (PWR_CR2). When enabled, the temperature thresholds increase power
consumption. .
The temperature thresholds are available only when the backup regulator is enabled (BREN
bit set in the PWR_CR2 register).
TEMPH and TEMPL wakeup interrupts are available on the RTC tamper signals (see
Section 46: Real-time clock (RTC)).

Figure 30. Temperature thresholds

Temperature

TEMPhigh

TEMPlow

TEMPH

TEMPL

MSv40345V1

1. For thresholds and hysteresis values, please refer to the datasheets.

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6.6 Power management

The power management block controls the VCORE supply in accordance with the system
operation modes (see Section 6.6.1).
The VCORE domain is split into the following power domains.
• D1 domain containing some peripherals and the Cortex®-M7 Core (CPU).
• D2 domain containing a large part of the peripherals.
• D3 domain containing some peripherals and the system control.
The D1, D2 and system D3 power domains can operate in one of the following operating
modes:
• DRun/Run/Run* (power ON, clock ON)
• DStop/Stop (power ON, clock OFF)
• DStandby/Standby (Power OFF, clock OFF).
The operating modes for D1 domain and D2 domain are independent. However system D3
domain power modes depend on D1 and D2 domain modes:
• For system D3 domain to operate in Stop mode, both D1 and D2 domains must be in
DStop or DStandby mode.
• For system D3 domain to operate in Standby mode, both D1 and D2 domains must be
in DStandby too.
D1, D2 and system D3 domains are supplied from a single regulator at a common VCORE
level. The VCORE supply level follows the system operating mode (Run, Stop, Standby). The
D1 domain and/or D2 domain supply can be powered down individually when the domains
are in DStandby mode.
The following voltage scaling features allow controlling the power with respect to the
required system performance (see Section 6.6.2: Voltage scaling):
• To obtain a given system performance, the corresponding voltage scaling shall be set
in accordance with the system clock frequency. To do this, configure the VOS bits to
the Run mode voltage scaling.
• To obtain the best trade-off between power consumption and exit-from-Stop mode
latency, configure the SVOS bits to Stop mode voltage scaling.

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6.6.1 Operating modes

Several system operating modes are available to tune the system according to the
performance required, i.e. when the CPU does not need to execute code and is waiting for
an external event. It is up to the user to select the operating mode that gives the best
compromise between low power consumption, short startup time and available wakeup
sources.
The operating modes allow controlling the clock distribution to the different system blocks
and powering them. The system operating mode is driven by the CPU subsystem, D2
domain and system D3 autonomous wakeup. The CPU subsystem can include multiple
domains depending on its peripheral allocation (see Section 8.5.11: Peripheral clock gating
control).
The following operating modes are available for the different system blocks (see Table 35):
• CPU subsystem modes:
– CRun
CPU and CPU subsystem peripheral(s) allocated via RCC PERxEN bits are
clocked.
– CSleep:
The CPU clocks is stalled and the CPU subsystem allocated peripheral(s) clock
operate according to RCC PERxLPEN.
– CStop:
CPU and CPU subsystem peripheral(s) clocks are stalled.
• D1 domain mode:
– DRun
The domain bus matrix is clocked. The CPU subsystem operates in CRun or
CSleep mode.
– DStop
The domain bus matrix clock is stalled.
The CPU subsystem operates in CStop mode and the PDDS_D1(a) bit selects
DStop mode.
– DStandby
The domain is powered down.
The CPU subsystem operates in CStop mode and the PDDS_D1 bit selects
DStandby mode.
• D2 domain mode:
– DRun
The domain bus matrix is clocked.
The CPU subsystem has an allocated peripheral in the D2 domain and the CPU
subsystem operates in CRun or CSleep mode.

a. The PDDS_Dn bits belong to PWR CPU control register (PWR_CPUCR).

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– DStop
The domain bus matrix clock is stalled.
The CPU subsystem has no peripherals allocated in the D2 domain and
PDDS_D2(a) bit selects DStop mode,
or
the CPU subsystem has an allocated peripheral in D2 domain, the CPU
subsystem operates in CStop mode and PDDS_D2 bit selects DStop mode.
– DStandby
The domain is powered down.
The CPU subsystem has no peripherals allocated in the D2 domain and
PDDS_D2 bit selects DStandby mode,
or
the CPU subsystem has an allocated peripheral in the D2 domain, the CPU
subsystem operates in CStop mode and PDDS_D2 bit selects DStandby mode.
• System /D3 domain modes
– Run/Run*
The system clock and D3 domain bus matrix clock are running:
- The CPU subsystem is in CRun or CSleep mode
or
- A wakeup signal is active. (i.e. System D3 autonomous mode)
The Run* mode is entered after a POR reset and a wakeup from Standby. In Run*
mode, the performance is limited and the system supply configuration shall be
programmed in PWR control register 3 (PWR_CR3). The system enters Run
mode only when the ACTVOSRDY bit in PWR control status register 1
(PWR_CSR1) is set to 1.
– Stop
The system clock and D3 domain bus matrix clock is stalled:
- The CPU subsystem is in CStop mode.
and
- all wakeup signals are inactive.
and
- At least one PDDS_Dn(a) bit for any domain select Stop mode.
– Standby
The system is powered down:
- The CPU subsystem is in CStop mode
and
- all wakeup signals are inactive.
and
- All PDDS_Dn(a) bits for all domains select Standby mode.
In Run mode, power consumption can be reduced by one of the following means:
• Lowering the system performance by slowing down the system clocks and reducing the
VCORE supply level through VOS voltage scaling bits.
• Gating the clocks to the APBx and AHBx peripherals when they are not used, through
PERxEN bits.

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Table 35. Low-power mode summary

Domain bus matrix clk

Voltage regulator

Domain supply
ON/OFF(2) ON Peripheral clk
Sys-oscillator
System Domain CPU Entry Wakeup

System clk

ON CPU clk
CRun - -

DRun(1)

ON
WFI or return

ON
CSleep from ISR or Any interrupt or event
WFE

ON

ON
Run

DStop(3) SLEEPDEEP bit

(4)
ON/OFF
+ WFI or return

ON

OFF
DStandby(3) from ISR or
WFE
Any EXTI interrupt or
DStop(3) SLEEPDEEP bit

ON
event
+ WFI or return

ON/OFF(7)

OFF
from ISR or
Stop(5)
WFE or Wakeup
DStandby(3)
source

OFF
CStop
cleared(6)

OFF

OFF
All PDDS_Dn bit WKUP pins rising or

OFF
+ SLEEPDEEP falling edge, RTC alarm
bit + WFI or (Alarm A or Alarm B),
return from ISR RTC Wakeup event, RTC
OFF

OFF
Standby(8) DStandby(3)
or WFE tamper events, RTC time
or Wakeup stamp event, external
source reset in NRST pin, IWDG
cleared(6) reset

1. The CPU subsystem has an allocated peripheral in the D2 domain and operates in CRun or CSleep mode.
2. The CPU subsystem peripherals that have a PERxLPEN bit will operate accordingly.
3. If the CPU subsystem has an allocated peripheral in the D2 domain, it must operate in CStop mode.
4. The CPU subsystem peripherals that have a PERxAMEN bit will operate accordingly.
5. All domains need to be in DStop Or DStandby.
6. When the CPU is in CStop and D3 domain in autonomous mode, the last EXTI Wakeup source is cleared.
7. When the system oscillator HSI or CSI is used, the state is controlled by HSIKERON and CSIKERON, otherwise the
system oscillator is OFF.
8. All domains are in DStandby mode.

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6.6.2 Voltage scaling

The D1, D2, and D3 domains are supplied from a single voltage regulator supporting
voltage scaling with the following features:
• Run mode voltage scaling
– VOS0: Scale 0 (VCORE boost)
– VOS1: Scale 1
– VOS2: Scale 2
– VOS3: Scale 3
• Stop mode voltage scaling
– SVOS3: Scale 3
– LP-SVOS4: Scale 4
– LP-SVOS5: Scale 5
For more details on voltage scaling values, refer to the product datasheets.
After reset, the system starts on the lowest Run mode voltage scaling (VOS3). The voltage
scaling can then be changed on-the-fly by software by programming VOS bits in PWR D3
domain control register (PWR_D3CR) according to the required system performance. When
exiting from Stop mode or Standby mode, the Run mode voltage scaling is reset to the
default VOS3 value.
Before entering Stop mode, the software can preselect the SVOS level in PWR control
register 1 (PWR_CR1). The Stop mode voltage scaling for SVOS4 and SVOS5 also sets the
voltage regulator in Low-power (LP) mode to further reduce power consumption. When
preselecting SVOS3, the use of the voltage regulator low-power mode (LP) can be selected
by LPDS register bit.

VOS0 activation/deactivation sequence

The system maximum frequency can be reached by boosting the voltage scaling level to
VOS0. This is done through the ODEN bit in the SYSCFG_PWRCR register.
The sequence to activate the VOS0 is the following:
1. Ensure that the system voltage scaling is set to VOS1 by checking the VOS bits in
PWR D3 domain control register (PWR D3 domain control register (PWR_D3CR))
2. Enable the SYSCFG clock in the RCC by setting the SYSCFGEN bit in the
RCC_APB4ENR register.
3. Enable the ODEN bit in the SYSCFG_PWRCR register.
4. Wait for VOSRDY to be set.
Once the VCORE supply has reached the required level, the system frequency can be
increased. Figure 31 shows the recommended sequence for switching VCORE from VOS1 to
VOS0 sequence.

The sequence to deactivate the VOS0 is the following:

1. Ensure that the system frequency was decreased.
2. Ensure that the SYSCFG clock is enabled in the RCC by setting the SYSCFGEN bit set
in the RCC_APB4ENR register.
3. Reset the ODEN bit in the SYSCFG_PWRCR register to disable VOS0.

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Once VOS0 is disabled, the voltage scaling can be reduced further by configuring VOS bits
in PWR D3 domain control register (PWR_D3CR) according to the required system
performance.
Note: VOS0 can be enabled only when VOS1 is programmed in PWR D3 domain control register
(PWR_D3CR) VOS bits. VOS0 deactivation must be managed by software before the
system enters low-power mode.

Figure 31. Switching VCORE from VOS1 to VOS0

ȝV

1,35 V

1,26 V

VCORE

ODEN

ACTVOSRDY

VOSRDY

MSv63819V1

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Figure 32. VCORE voltage scaling versus system power modes

Standby

POWER DOWN

Run
MAIN VOS3

reset

MAIN VOS0 MAIN VOS1 MAIN VOS2

MAIN or LP SVOS3
SW Run mode LP SVOS4
Stop mode LP SVOS5
Standby mode Stop
Wakeup

MSv40347V3

6.6.3 Power control modes

The power control block handles the VCORE supply for system Run, Stop and Standby
modes.
The system operating mode depends on the CPU subsystem modes (CRun, CSleep,
CStop), on the domain modes (DRun, DStop, DStandby), and on the system D3
autonomous wakeup:
• In Run mode, VCORE is defined by the VOS voltage scaling.
The CPU subsystem is in CRun or CSleep or an EXTI wakeup is active.
• In Stop mode, VCORE is defined by the SVOS voltage scaling.
The CPU subsystem is in CStop mode and all EXTI wakeups are inactive. The D1
domain and D2 domain are either in DStop or DStandby mode.
• In Standby mode, VCORE supply is switched off.
The CPU subsystem is in CStop mode and all EXTI wakeups are inactive. The D1
domain and D2 domain are both in DStandby mode.
The domain operating mode can depend on the CPU subsystem when peripherals are
allocated in the corresponding domain. The domain mode selection between DStop and
DStandby is configured via domain dedicated PDDS_Dn bits in PWR CPU control register
(PWR_CPUCR). The CPU can choose to keep a domain in DStop, or allow a domain to
enter DStandby mode.
If a domain is in DStandby mode, the corresponding power is switched off.

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All the domains can be configured for the system mode (Stop or Standby) through
PDDS_Dn bits in PWR CPU control register (PWR_CPUCR). The system enters Standby
only when all PDDS_Dn bits for all domains have allowed it.

Table 36. PDDS_Dn low-power mode control

PWR_CPUCR
PDDS_D1

PDDS_D2

PDDS_D3
D1 mode D2 mode D3 mode

0 DStop any Run or Stop

x
1 DStandby any any
x
0 any DStop Run or Stop
x
1 any DStandby any
at least one = 0 DStop or DStandby DStop or DStandby Stop
1 1 1 DStandby DStandby Standby

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Figure 33. Power control modes detailed state diagram

Wakeup from STANDBY RUN PDDS_D2 = 1

reset CPU sub-system having an

allocated peripheral in D2
domain

CPU CRUN or CSLEEP CPU CRUN or CSLEEP D2 CPU CRUN or CSLEEP

D2 peripheral
D1 domain DRUN peripheral D1 domain DRUN allocation D1 domain DRUN
allocation
D2 domain DSTOP D2 domain DRUN D2 domain DSTANDBY
D2 D2
C_wakeup peripheral C_wakeup peripheral C_wakeup
delocation delocation

CSTOP CSTOP CSTOP CSTOP

CPU CSTOP
EXTI wakeup active (system D3 domain autonomous mode)
D1 domain DSTOP D1 domain DSTANDBY D1 domain DSTOP D1 domain DSTANDBY
D2 domain DSTOP D2 domain DSTOP D2 domain DSTANDBY D2 domain DSTANDBY
Wakeup Wakeup Wakeup Wakeup
from from from from
STOP STOP STOP STOP

STOP Enter to STOP Enter to STOP Enter to STOP Enter to STOP

CPU CSTOP
EXTI wakeups inactive
D1 domain DSTOP D1 domain DSTANDBY D1 domain DSTOP D1 domain DSTANDBY
D2 domain DSTOP D2 domain DSTOP D2 domain DSTANDBY D2 domain DSTANDBY

Enter to
STANDBY STANDBY
D1 domain DSTANDBY
D2 domain DSTANDBY
CPU sub-system modes
SW Run mode
Domain modes Stop mode

System D3 domain modes

Standby mode
Wakeup
MSv40896V3

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After a system reset, the CPU is in CRun mode.

Power control state transitions are initiated by the following events:
• CPU going to CStop mode (state transitions in Run mode are marked in green and red)
– Green transitions: CPU wakes up as from CSleep.
– Red transitions: CPU wakes up with domain reset. The SBF_Dn is set.
• Allocating or de-locating a peripheral in a domain (state transitions in Run mode are
marked in orange and red)
– Orange transitions: the domain wakes up from DStop
– Red transitions: the domain wakes up from DStandby. The SBF_Dn is set.
• The system enters or exits from Stop mode (state transitions marked in blue)
– Blue transitions the system wakes up from Stop mode. The STOPF is set.
• The system enters or exits from Standby mode (state transitions in Stop and Standby
mode are marked in red).
– When exiting from Standby mode, the SBF is set.
When a domain exits from DStandby, the domain peripherals are reset, while the domain
SBF_Dn bit is set (state transitions causing a domain reset are marked in red).
Table 37 shows the flags that indicate from which mode the domain/system exits. The CPU
features a set of flags which can be read from PWR CPU control register (PWR_CPUCR).

Table 37. Low-power exit mode flags

SBF_D1

SBF_D2

STOPF

System
SBF

D1 domain mode D2 domain mode Comment

mode

Run DRun or DStop DRun or DStop 0 0 0 0 D1, D2 and system contents retained
D1 contents lost, D2 and system
Run DStandby DStop 1 0 0 0
contents retained
D2 contents lost, D1 and system
Run DRun or DStop DStandby 0 1 0 0
contents retained
D1 and D2 contents lost, system
Run DStandby DStandby 1 1 0 0
contents retained
D1, D2 and system contents retained,
Stop DStop DStop 0 0 0 1
clock system reset.
D1 contents lost, D2 and system
Stop DStandby DStop 1 0 0 1
contents retained, clock system reset
D2 contents lost, D1 and system
Stop DStop DStandby 0 1 0 1
contents retained, clock system reset
D1 and D2 contents lost, system
Stop DStandby DStandby 1 1 0 1
contents retained, clock system reset
Standby DStandby DStandby 0(1) 0(1) 1 0 D1, D2 and system contents lost
1. When returning from Standby, the SBF_D1 and SBF_D2 reflect the reset value.

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6.6.4 Power management examples

• Figure 34 shows VCORE voltage scaling behavior in Run mode.
• Figure 35 shows VCORE voltage scaling behavior in Stop mode.
• Figure 36 shows VCORE voltage regulator and voltage scaling behavior in Standby
mode.
• Figure 37 shows VCORE voltage scaling behavior in Run mode with D1 and D2
domains are in DStandby mode

Example of VCORE voltage scaling behavior in Run mode

Figure 34 illustrates the following system operation sequence example:
1. After reset, the system starts from HSI with VOS3.
2. The system performance is first increased to a medium-speed clock from the PLL with
voltage scaling VOS2. To do this:
a) Program the voltage scaling to VOS2.
b) Once the VCORE supply has reached the required level indicated by VOSRDY,
increase the clock frequency by enabling the PLL.
c) Once the PLL is locked, switch the system clock.
3. The system performance is then increased to high-speed clock from the PLL with
voltage scaling VOS1. To do this:
a) Program the voltage scaling to VOS1.
b) Once the VCORE supply has reached the required level indicated by VOSRDY,
increase the clock frequency.
4. The system performance is then reduced to a medium-speed clock with voltage scaling
VOS2. To do this:
a) First decrease the system frequency.
b) Then decrease the voltage scaling to VOS2.
5. The next step is to reduce the system performance to HSI clock with voltage scaling
VOS3. To do this:
a) Switch the clock to HSI.
b) Disable the PLL.
c) Decrease the voltage scaling to VOS3.
6. The system performance can then be increased to high-speed clock from the PLL. To
do this:
a) Program the voltage scaling to VOS1.
b) Once the VCORE supply has reached the required level indicated by VOSRDY,
increase the clock frequency by enabling the PLL.
c) Once the PLL is locked, switch the system clock.
When the system performance (clock frequency) is changed, VOS shall be set accordingly.
otherwise the system might be unreliable.

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Figure 34. Dynamic voltage scaling in Run mode

VOS 1

VOS 2
VCORE
VOS 3

VOS 3 2 1 2 3 1

VOSRDY

PLLxON

ck_sys

ck_hclk_d1

ck_hclk_d2

ck_hclk_d3

Wait Wait Wait Wait Wait Wait

RUN RUN RUN RUN RUN
VOSRDY PLL VOSRDY VOSRDY VOSRDY PLL

RUN from HSI Run from PLL RUN from HSI Run from PLL

MSv40350V1

1. The status of the register bits at each step is shown in blue.

Example of VCORE voltage scaling behavior in Stop mode

Figure 35 illustrates the following system operation sequence example:
1. The system is running from the PLL in high-performance mode (VOS1 voltage scaling).
2. The CPU subsystem deallocates all the peripheral in the D2 domain that will first enter
DStop mode. D2 system clock is stopped. The system still provides the high-
performance system clock, hence the voltage scaling shall stay at VOS1 level.
3. In a second step, the CPU subsystem enters CStop mode, D1 domain enters DStop
mode and the system enters Stop mode. The system clock is stopped and the
hardware lowers the voltage scaling to the software preselected SVOS4 level.
4. The CPU subsystem is then woken up. The system exits from Stop mode, the D1
domain exits from DStop mode and the CPU subsystem exits from CStop mode. The
hardware then sets the voltage scaling to VOS3 level and waits for the requested
supply level to be reached before enabling the HSI clock. Once the HSI clock is stable,
the system clock and the D1 system clock are enabled.
5. The CPU subsystem allocates a peripheral in the D2 domain. The D2 system clock is
enabled.
6. The system performance is then increased. To do this:
a) The software first sets the voltage scaling to VOS1.
b) Once the VCORE supply has reached the required level indicated by VOSRDY, the
clock frequency can be increased by enabling the PLL.
c) Once the PLL is locked, the system clock can be switched.

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Figure 35. Dynamic voltage scaling behavior with D1,

D2 and system in Stop mode

VOS 1

VOS 2
VCORE
(S)VOS 3

SVOS 4

VOS 1 3 1

SVOS 4

VOSRDY

exti_c_wkup

pwr_d1_wkup

PLLnON

ck_sys

ck_hclk_d1

ck_hclk_d2

ck_hclk_d3

D1RUN D1RUN
Wait Wait
RUN D2STOP STOP D2STOP RUN RUN
VCORE Wait VOSRDY
D3RUN D3RUN
HSI
Run from PLL Clock Stopped RUN from HSI Run from PLL

MSv40897V2

1. The status of the register bits at each step is shown in blue.

Example of VCORE voltage regulator and voltage scaling behavior

in Standby mode
Figure 36 illustrates the following system operation sequence example:
1. The system is running from the PLL in high-performance mode (VOS1 voltage scaling).
2. The CPU subsystem deallocates all the peripherals in the D2 domain that will first enter
DStandby mode.The D2 domain bus matrix clock is stopped and the power is switched
off. The system performance is unchanged hence the voltage scaling does not change.
3. The CPU subsystem then enters to CStop mode, D1 domain enters DStandby mode
and the system enters Standby mode. The system clock is stopped and the voltage
regulator switched off.
4. The system is then woken up by a wakeup source. The system exits from Standby
mode. The hardware sets the voltage scaling to the default VOS3 level and waits for
the requested supply level to be reached before enabling the default HSI oscillator.
Once the HSI clock is stable, the system clock and D1 subsystem clock are enabled.

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Since there are no allocated peripherals in the D2 domain, this domain remains in
DStop mode. The software shall then check the ACTVOSRDY is valid before changing
the system performance.
5. In a next step, increase the system performance. To do this:
a) The software first increases the voltage scaling to VOS1 level
b) Before enabling the PLL, it waits for the requested supply level to be reached by
monitoring VOSRDY bit.
c) Once the PLL is locked, the system clock can be switched.
6. The CPU subsystem puts the D2 domain in DStandby mode.

Figure 36. Dynamic Voltage Scaling D1, D2, system Standby mode

VOS 1

VOS 2
VCORE Vdd_D2
(S)VOS 3

SVOS 4
Vdd_D2
Off
VOS 1 OFF 3 1

SVOS 4 OFF 3

VOSRDY

ACTVOSRDY

exti_c_wkup

pwr_d1_wkup

PLLxON

ck_sys

ck_hclk_d1

ck_hclk_d2

ck_hclk_d3

D1RUN D1RUN D1STANDBY Wait D1RUN D1RUN D1RUN

Wait Wait
D2RUN D2STANDBY D2STANDBY RESET ACTVOS D2STOP D2STOP D2STANDBY
Wait VOSRDY PLL
D3RUN D3RUN D3STANDBY Wait RDY D3RUN D3RUN D3RUN
HSI
VCORE
Run from PLL Power down RUN from HSI Run from PLL

MSv40898V3

1. The status of the register bits at each step is shown in blue.

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Example of VCORE voltage scaling behavior in Run mode

with D1 and D2 domains in DStandby mode
Figure 37 illustrates the following system operation sequence example:
1. The system is running from the PLL with system in high performance mode (VOS1
voltage scaling).
2. The CPU subsystem deallocates all the peripherals in the D2 domain that will first enter
DStandby mode. The D2 domain bus matrix clock is stopped and its power switched
off. The system performance is unchanged hence the voltage scaling does not change.
3. The CPU subsystem then enters CStop mode and the D1 domain enters DStandby
mode. The D1 domain bus matrix clock is stopped and its power switched off. At the
same time the system enters Stop mode. The system clock is stopped and the
hardware lowers the voltage scaling to the software preselected SVOS4 level.
4. The system is then woken up by a D3 autonomous mode wakeup event. The system
exits from Stop mode. The hardware sets the voltage scaling to the default VOS3 level
and waits for the requested supply level to be reached before enabling the HSI clock.
Once the HSI clock is stable, the system clock is enabled. The system is running in D3
autonomous mode.
5. The D3 autonomous mode wakeup source is then cleared, causing the system to enter
Stop mode. The system clock is stopped and the voltage scaling is lowered to the
software preselected SVOS4 level.
6. The CPU subsystem is then woken up. The system exits from Stop mode, the D1
domain exits from DStandby mode and the CPU subsystem exits from CStop mode.
The hardware sets the voltage scaling to the default VOS3 level and waits for the
requested supply level to be reached before enabling the default HSI oscillator. Once
the HSI clock is stable, the system clock and the D1 subsystem clock are enabled. The
D2 domain remains in DStandby mode.

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Figure 37. Dynamic voltage scaling behavior with D1 and D2 in DStandby mode and
D3 in autonomous mode

VOS 1

VOS 2
VCORE
(S)VOS 3

SVOS 4
Vdd_D2 Vdd_D1 Vdd_D1 Vdd_D2
Off
VOS 1 3

SVOS 4

VOSRDY

exti_c_wkup

pwr_d1_wkup

exti_d3_wkup

pwr_d3_wkup

PLLxON

ck_sys

ck_hclk_d1

ck_hclk_d2

ck_hclk_d3

D1RUN D1STANDBY D1STANDBY D1STANDBY D1RUN

Wait Wait
RUN D2STANDBY D2STANDBY D2STANDBY D2STANDBY D2STANDBY
VCORE Wait VCORE Wait
D3RUN D3STOP D3RUN D3STOP D3RUN
HSI HSI
RUN from RUN from
RUN from PLL Clock stopped Clock stopped
HSI HSI

MSv40899V3

1. The status of the register bits at each step is shown in blue.

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6.7 Low-power modes

Several low-power modes are available to save power when the CPU does not need to
execute code (i.e. when waiting for an external event). It is up to the user application to
select the mode that gives the best compromise between low power consumption, short
startup time and available wakeup sources:
• Slowing down system clocks (see Section 8.5.6: System clock (sys_ck))
• Controlling individual peripheral clocks (see Section 8.5.11: Peripheral clock gating
control)
• Low-power modes
– CSleep (CPU clock stopped)
– CStop (CPU subsystem clock stopped)
– DStop (Domain bus matrix clock stopped)
– Stop (System clock stopped)
– DStandby (Domain powered down)
– Standby (System powered down)

6.7.1 Slowing down system clocks

In Run mode, the speed of the system clock ck_sys can be reduced. For more details refer
to Section 8.5.6: System clock (sys_ck).

6.7.2 Controlling peripheral clocks

In Run mode, the HCLKx and PCLKx for individual peripherals can be stopped by
configuring at any time PERxEN bit in RCC_C1_xxxxENR or RCC_DnxxxxENR to reduce
power consumption.
To reduce power consumption in CSleep mode, the individual peripheral clocks can be
disabled by configuring PERxLPEN bit in RCC_C1_xxxxLPENR or RCC_DnxxxxLPENR.
For the peripherals still receiving a clock in CSleep mode, their clock can be slowed down
before entering CSleep mode.

6.7.3 Entering low-power modes

CPU subsystem CSleep and CStop low-power modes are entered by the MCU when
executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions, or when the
SLEEPONEXIT bit in the Cortex®-M System Control register is set on Return from ISR.
A domain can enter DStop or DStandby low-power mode when the CPU subsystem has an
allocated peripheral in the domain and enters CStop mode, or when all D2 domain
peripherals are deallocated.
The system can enter Stop or Standby low-power mode when all EXTI wakeup sources are
cleared and the other domains are in DStop or DStandby mode.

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6.7.4 Exiting from low-power modes

The CPU subsystem exits from CSleep mode through any interrupt or event depending on
how the low-power mode was entered:
• If the WFI instruction or Return from ISR was used to enter to low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the system.
• If the WFE instruction is used to enter to low-power mode, the CPU exits from low-
power mode as soon as an event occurs. The wakeup event can be generated either
by:
– An NVIC IRQ interrupt.
When SEVONPEND = 0 in the Cortex®-M7 System Control register, the interrupt
must be enabled in the peripheral control register and in the NVIC.
When the MCU resumes from WFE, the peripheral interrupt pending bit and the
NVIC peripheral IRQ channel pending bit in the NVIC interrupt clear pending
register have to be cleared. Only NVIC interrupts with sufficient priority will wakeup
and interrupt the MCU.
When SEVONPEND = 1 in the Cortex®-M7 System Control register, the interrupt
must be enabled in the peripheral control register and optionally in the NVIC.
When the MCU resumes from WFE, the peripheral interrupt pending bit and, when
enabled, the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear
pending register) have to be cleared.
All NVIC interrupts will wakeup the MCU, even the disabled ones.
Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the
MCU.
– An event
An EXTI line must be configured in event mode. When the CPU resumes from
WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the
NVIC IRQ channel pending bit as the pending bits corresponding to the event line
is not set. It might be necessary to clear the interrupt flag in the peripheral.
The CPU subsystem exits from CStop, DStop and Stop modes by enabling an EXTI interrupt
or event depending on how the low-power mode was entered (see above).
The system can wakeup from Stop mode by enabling an EXTI wakeup, without waking up a
CPU subsystem. In this case the system will operate in D3 autonomous mode.
The CPU subsystem exits from DStandby mode by enabling an EXTI interrupt or event,
regardless on how DStandby mode was entered. Program execution restarts from CPU
local reset (such as a reset vector fetched from System configuration block (SYSCFG).
The D2 domain can exit from DStop or DStandby mode when the CPU allocates a first
peripheral in the domain.
The CPU subsystem exits from Standby mode by enabling an external reset (NRST pin), an
IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event. Program
execution restarts in the same way as after a system reset (such as boot pin sampling,
option bytes loading or reset vector fetched).

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6.7.5 CSleep mode

The CSleep mode applies only to the CPU subsystem. In CSleep mode, the CPU clock is
stopped. The CPU subsystem peripheral clocks operate according to the values of
PERxLPEN bits in RCC_C1_xxxxENR or RCC_DnxxxxENR.

Entering CSleep mode

The CSleep mode is entered according to Section 6.7.3: Entering low-power modes, when
the SLEEPDEEP bit in the Cortex®-M System Control register is cleared.
Refer to Table 38 for details on how to enter to CSleep mode.

Exiting from CSleep mode

The CSleep mode is exited according to Section 6.7.4: Exiting from low-power modes.
Refer to Table 38 for more details on how to exit from CSleep mode.

Table 38. CSleep mode

CSleep mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0 (Refer to the Cortex®-M System Control register.)
– CPU NVIC interrupts and events cleared.
Mode entry On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1 (refer to the Cortex®-M System Control register.)
– CPU NVIC interrupts and events cleared.
If WFI or return from ISR was used for entry:
– Any Interrupt enabled in NVIC: Refer to Table 145: NVIC
If WFE was used for entry and SEVONPEND = 0:
Mode exit – Any event: Refer to Section 20.5.3: EXTI CPU wakeup procedure
If WFE was used for entry and SEVONPEND = 1:
– Any Interrupt even when disabled in NVIC: refer to Table 145: NVIC or
any event: refer to Section 20.5.3: EXTI CPU wakeup procedure
Wakeup latency None

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6.7.6 CStop mode

The CStop mode applies only to the CPU subsystem. In CStop mode, the CPU clock is
stopped. Most CPU subsystem peripheral clocks are stopped too and only the CPU
subsystem peripherals having a PERxAMEN bit operate accordingly.
In CStop mode, the CPU subsystem peripherals that have a kernel clock request can still
request their kernel clock. For the peripheral that have a PERxAMEN bit, this bit shall be set
to be able to request the kernel clock.

Entering CStop mode

The CStop mode is entered according to Section 6.7.3: Entering low-power modes, when
the SLEEPDEEP bit in the Cortex®-M System Control register is set.
Refer to Table 39 for details on how to enter to CStop mode.

Exiting from CStop mode

The CStop mode is exited according to Section 6.7.4: Exiting from low-power modes.
Refer to Table 39 for more details on how to exit from CStop mode.

Table 39. CStop mode

CStop mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 1 (Refer to the Cortex®-M System Control register.)
– CPU NVIC interrupts and events cleared.
– All CPU EXTI Wakeup sources are cleared.
Mode entry On return from ISR while:
– SLEEPDEEP = 1 and
– SLEEPONEXIT = 1 (Refer to the Cortex®-M System Control register.)
– CPU NVIC interrupts and events cleared.
– All CPU EXTI Wakeup sources are cleared.
If WFI or return from ISR was used for entry:
– EXTI Interrupt enabled in NVIC: Refer to Table 145: NVIC, for peripheral
which are not stopped or powered down.
If WFE was used for entry and SEVONPEND = 0:
Mode exit – EXTI event: Refer to Section 20.5.3: EXTI CPU wakeup procedure, for
peripheral which are not stopped or powered down.
If WFE was used for entry and SEVONPEND = 1:
– EXTI Interrupt even when disabled in NVIC: refer to Table 145: NVIC or
EXTI event: refer to Section 20.5.3: EXTI CPU wakeup procedure, for
peripheral which are not stopped or powered down.
EXTI and RCC wakeup synchronization (see Section 8.4.7: Power-on and
Wakeup latency
wakeup sequences)

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6.7.7 DStop mode

D1 domain and/or D2 domain enters DStop mode only when the CPU subsystem is in
CStop mode and has allocated peripheral in the domain (see Table 40). In DStop mode the
domain bus matrix clock is stopped.
The Flash memory can enter low-power Stop mode when it is enabled through FLPS in
PWR_CR1 register. This allows a trade-off between domain DStop restart time and low
power consumption.

Table 40. DStop mode overview

D1 D2
Peripheral allocation CPU Comment
domain domain

CRun or
DRun DStop
No peripheral allocated in D2 domain CSleep
CStop DStop DStop
CRun or CPU subsystem, keep
DRun DRun
Peripheral allocated in D2 domain CSleep D2 domain active.
CStop DStop DStop

In DStop mode domain peripherals using the LSI or LSE clock and peripherals having a
kernel clock request are still able to operate.

Entering DStop mode

The DStop mode is entered according to Section 6.7.3: Entering low-power modes, when at
least one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for the domain select
Stop.
Refer to Table 41 for details on how to enter DStop mode.
If Flash memory programming is ongoing, the DStop mode entry is delayed until the
memory access is finished.
If an access to the domain bus matrix is ongoing, the DStop mode entry is delayed until the
domain bus matrix access is complete.

Exiting from DStop mode

The DStop mode is exited according to Section 6.7.4: Exiting from low-power modes.
Refer to Table 41 for more details on how to exit from DStop mode.
When exiting from DStop mode, the CPU subsystem clocks, domain(s) bus matrix clocks
and voltage scaling depend on the system mode.
• When the system did not enter Stop mode, the CPU subsystem clocks, domain(s) bus
matrix clocks and voltage scaling values are the same as when entering DStop mode.
• When the system has entered Stop mode, the CPU subsystem clocks, domain(s) bus
matrix clocks and voltage scaling are reset.

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Table 41. DStop mode

DStop mode Description

– The domain CPU subsystem enters CStop.

– The CPU subsystem has an allocated peripheral in the D2 domain and
Mode entry enters CStop.
– The CPU subsystem deallocated its last peripheral in the D2 domain.
– The PDDS_Dn bit for the domain selects Stop mode.
– The domain CPU subsystem exits from CStop mode (see Table 39)
– The CPU subsystem has an allocated peripheral in the D2 domain and
Mode exit
exits from CStop mode (see Table 39)
– The CPU subsystem allocates a first peripheral in the D2 domain.
EXTI and RCC wakeup synchronization (see Section 8.4.7: Power-on and
Wakeup latency
wakeup sequences).

6.7.8 Stop mode

The system D3 domain enters Stop mode only when the CPU subsystem is in CStop mode,
the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU control
register (PWR_CPUCR) for any domain request Stop. In Stop mode, the system clock
including a PLL and the D3 domain bus matrix clocks are stopped. When HSI or CSI is
selected, the system oscillator operates according to the HSIKERON and CSIKERON bits in
RCC_CR register. Other system oscillator sources are stopped.
In system D3 domain Stop mode, D1 domain and D2 domain are either in DStop and/or
DStandby mode.
In Stop mode, the domain peripherals that use the LSI or LSE clock, and the peripherals
that have a kernel clock request to select HSI or CSI as source, are still able to operate.
In system Stop mode, the following features can be selected to remain active by
programming individual control bits:
• Independent watchdog (IWDG)
The IWDG is started by writing to its Key register or by hardware option. Once started it
cannot be stopped except by a Reset (see Section 45.3 in Section 45: Independent
watchdog (IWDG).
• Real-time clock (RTC)
This is configured via the RTCEN bit in the RCC backup domain control register
(RCC_BDCR).
• Internal RC oscillator (LSI RC)
This is configured via the LSION bit in the RCC clock control and status register
(RCC_CSR).
• External 32.768 kHz oscillator (LSE OSC)
This is configured via the LSEON bit in the RCC backup domain control register
(RCC_BDCR).

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• Peripherals capable of running on the LSI or LSE clock.

• Peripherals having a kernel clock request.
• Internal RC oscillators (HSI and CSI)
This is configured via the HSIKERON and CSIKERON bits in the RCC clock control
and status register (RCC_CSR).
• The ADC or DAC can also consume power during Stop mode, unless they are disabled
before entering this mode. To disable them, the ADON bit in the ADC_CR2 register and
the ENx bit in the DAC_CR register must both be written to 0.
The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting from
system Stop mode (see Table 42).

Table 42. Stop mode operation

Stop mode
SVOS LPDS Voltage regulator Wake-up Latency
operation

0 Main No additional wakeup time.

SVOS3
1 LP Voltage Regulator wakeup time from LP mode.
Voltage Regulator wakeup time from LP mode + voltage
SVOS4 or
x LP level wakeup time for SVOS4 or SVOS5 level to VOS3
SVOS5
level

Entering Stop mode

The Stop mode is entered according to Section 6.7.3: Entering low-power modes, when at
least one PDDS_Dn bit n PWR CPU control register (PWR_CPUCR) for any domain
request Stop.
Refer to Table 43 for details on how to enter Stop mode.
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to a bus matrix (AXI, AHB or APB) is ongoing, the Stop mode entry is delayed
until the bus matrix access is finished.
To allow peripherals having a kernel clock request to operate in Stop mode, the system must
use SVOS3 level.
Note: Use a DSB instruction to ensure that outstanding memory transactions complete before
entering stop mode.
Before entering Stop mode, the software must ensure that VOS0 s not active.
Exiting from Stop mode
The Stop mode is exited according to Section 6.7.4: Exiting from low-power modes.
Refer to Table 43 for more details on how to exit from Stop mode.
When exiting from Stop mode, the system clock, D3 domain bus matrix clocks and voltage
scaling are reset.
STOPF status flag in PWR CPU control register (PWR_CPUCR) indicates that the system
has exited from Stop mode (see Table 37).

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Table 43. Stop mode

Stop mode Description

– When the CPU is in CStop mode and there is no active EXTI Wakeup
Mode entry source and Run_D3 = 0.
– At least one PDDS_Dn bit for any domain select Stop.
Mode exit – On a EXTI Wakeup.
System oscillator startup (when disabled).
Wakeup latency + EXTI and RCC wakeup synchronization.
+ Voltage Scaling refer to Table 42 (see Section 6.6.2: Voltage scaling)

I/O states in Stop mode

I/O pin configuration remain unchanged in Stop mode.

6.7.9 DStandby mode

Like DStop mode, DStandby mode is based on the CPU subsystem CStop mode. However
the domain VCORE supply is powered off. A domain enters DStandby mode only when the
CPU subsystem is in CStop mode if peripherals are allocated in the domain
A domain enters DStandby mode only when the CPU subsystem is in CStop mode if
peripherals are allocated in the domain and the PDDS_Dn bit in PWR CPU control register
(PWR_CPUCR) for the domain is configured accordingly. In DStandby mode, the domain is
powered down and the domain RAM and register contents are lost.

Entering DStandby mode

The DStandby mode is entered according to Section 6.7.3: Entering low-power modes,
when the PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for the Dn domain
selects Standby mode.
Refer to Table 44 for details on how to enter DStandby mode.
If Flash memory programming is ongoing, the DStandby mode entry is delayed until the
memory access is finished.
If an access to the domain bus matrix is ongoing, the DStandby mode entry is delayed until
the domain bus matrix access is finished.
Note: When the CPU sets the PDDS_D2 bit to select Standby mode, the D2 domain enters
DStandby mode (the CPU has no allocated peripherals in the D2 domain).

Exiting from DStandby mode

The DStandby mode is exited according to Section 6.7.4: Exiting from low-power modes.
Refer to Table 44 for more details on how to exit from DStandby mode.
Note: When the D2 domain is in DStandby mode and the CPU sets the domain PDDS_D2 bit to
select Stop mode, the D2 domain remains in DStandby mode. The D2 domain will only exit
DStandby when the CPU allocates a peripheral in the D2 domain.

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When exiting from DStandby mode, the domain CPU and peripherals are reset. However
the state of the CPU subsystem clocks, domain(s) bus matrix clocks and voltage scaling
depends on the system mode:
• When the system did not enter Stop mode, the CPU subsystem clocks, domain(s) bus
matrix clocks and voltage scaling are the same as when entering DStandby mode.
• When the system has entered Stop or Standby mode, the CPU subsystem clocks,
domain(s) bus matrix clocks and voltage scaling are reset.
When the D2 domain exits from DStandby mode due to the CPU subsystem (i.e when
allocating a first peripheral or when peripherals are allocated in the D2 domain and the CPU
subsystem exits from CStop mode), the CPU shall verify that the domain has exited from
DStandby mode. To ensure correct operation, it is recommended to follow the sequence
below:
1. First check that the domain bus matrix clock is available. The domain bus matrix clock
state can be checked in RCC_CR register:
– When RCC DnCKRDY = 0, the domain bus matrix clock is stalled.
– If RCC DnCKRDY = 1, the domain bus matrix clock is enabled.
2. Then wait for the domain has exited from DStandby mode. To do this, check the
SBF_Dn flag in PWR CPU control register (PWR_CPUCR). The domain is powered
and can be accessed only when SBF_Dn is cleared. Below an example of code:
Loop
write PWR SBF_Dn = 0 ; try to clear bit.
read PWR SBF_Dn
While 1 ==> loop

Table 44. DStandby mode

DStandby mode Description

– The domain CPU subsystem enters CStop.

– The CPU subsystem has an allocated peripheral in D2 domain and
enters CStop.
Mode entry – The CPU subsystem deallocated its last peripheral in the D2 domain.
– The PDDS_Dn bits for the domain select Standby mode.
– All WKUPF bits in Power Control/Status register (PWR_WKUPFR) are
cleared.
– The CPU subsystem exits from CStop mode (see Table 39)
– The CPU subsystem has an allocated peripheral in the D2 domain and
Mode exit
exits from CStop mode (see Table 39)
– The CPU subsystem allocates a first peripheral in the D2 domain.
EXTI and RCC wakeup synchronization.
Wakeup latency + Domain power up and reset.
(see Section 8.4.7: Power-on and wakeup sequences)

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6.7.10 Standby mode

The Standby mode allows achieving the lowest power consumption. Like Stop mode, it is
based on CPU subsystem CStop mode. However the VCORE supply regulator is powered
off.
The system D3 domain enters Standby mode only when the D1 and D2 domain are in
DStandby. When the system D3 domain enters Standby mode, the voltage regulator is
disabled. The complete VCORE domain is consequently powered off. The PLLs, HSI
oscillator, CSI oscillator, HSI48 and the HSE oscillator are also switched off. SRAM and
register contents are lost except for backup domain registers (RTC registers, RTC backup
register and backup RAM), and Standby circuitry (see Section 6.4.4: Backup domain).
In system Standby mode, the following features can be selected by programming individual
control bits:
• Independent watchdog (IWDG)
The IWDG is started by programming its Key register or by hardware option. Once
started, it cannot be stopped except by a reset (see Section 45.3 in Section 45:
Independent watchdog (IWDG).
• Real-time clock (RTC)
This is configured via the RTCEN bit in the backup domain control register
(RCC_BDCR).
• Internal RC oscillator (LSI RC)
This is configured by the LSION bit in the Control/status register (RCC_CSR).
• External 32.768 kHz oscillator (LSE OSC)
This is configured by the LSEON bit in the backup domain control register
(RCC_BDCR).

Entering Standby mode

The Standby mode is entered according to Section 6.7.3: Entering low-power modes, when
all PDDS_Dn bits in PWR CPU control register (PWR_CPUCR) for all domains request
Standby.
Refer to Table 46 for more details on how to enter to Standby mode.
Note: Before entering Standby mode, the software must ensure that VOS0 is not active.

Exiting from Standby mode

The Standby mode is exited according to Section 6.7.4: Exiting from low-power modes.
Refer to Table 46 for more details on how to exit from Standby mode.
The system exits from Standby mode when an external Reset (NRST pin), an IWDG Reset,
a WKUP pin event, a RTC alarm, a tamper event, or a time stamp event is detected. All
registers are reset after waking up from Standby except for power control and status
registers (PWR control register 2 (PWR_CR2), PWR control register 3 (PWR_CR3)), SBF
bit in PWR CPU control register (PWR_CPUCR), PWR wakeup flag register
(PWR_WKUPFR), and PWR wakeup enable and polarity register (PWR_WKUPEPR).
After waking up from Standby mode, the program execution restarts in the same way as
after a system reset (boot option sampling, boot vector reset fetched, etc.). The SBF status
flags in PWR CPU control register (PWR_CPUCR) registers indicate from which mode the
system has exited (see Table 45).

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Table 45. Standby and Stop flags

SBF_D2

SBF_D1

STOPF
SBF
Description

0 1 0 0 D1 domain exits from DStandby while system stayed in Run

0 1 0 1 D1 domain exits from DStandby, while system has been in or exits from Stop
1 0 0 0 D2 domain exits from DStandby while system stayed in Run
1 0 0 1 D2 domain exits from DStandby while system has been in or exits from Stop
D1 and D2 domain exit from DStandby while the system remains in Run
1 1 0 0
mode
D1 and D2 domain exit from DStandby while the system is in Stop mode or is
1 1 0 1
exiting this mode.
0 0 0 1 System has been in or exits from Stop
(1)
0 0(1) 1 0 System exits from Standby
1. When exiting from Standby the SBF_D1 and SBF_D2 reflect the reset value

Table 46. Standby mode

Standby mode Description

– The CPU subsystem is in CStop mode, and there is no active EXTI

Wakeup source and RUN_D3 = 0.
Mode entry – All PDDS_Dn bits for all domains select Standby.
– All WKUPF bits in Power Control/Status register (PWR_WKUPFR) are
cleared.
– WKUP pins rising or falling edge, RTC alarm (Alarm A and Alarm B),
Mode exit RTC wakeup, tamper event, time stamp event, external reset in NRST
pin, IWDG reset.
Wakeup latency System reset phase (see Section 8.4.2: System reset)

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance without pull, except for:
• Reset pad (still available)
• RTC_AF1 pin if configured for tamper, time stamp, RTC Alarm out, or RTC clock
calibration out
• WKUP pins (if enabled). The WKUP pin pull configuration can be defined through
WKUPPUPD register bits in PWR wakeup enable and polarity register
(PWR_WKUPEPR).

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6.7.11 Monitoring low-power modes

The devices feature state monitoring pins to monitor the CPU and Domain state transition to
low-power mode (refer to Table 47 for the list of pins and their description). The GPIO pin
corresponding to each monitoring signal has to be programmed in alternate function mode.
This feature is not available in Standby mode since these I/O pins are switched to high
impedance. It is available only on devices revision V.

Table 47. Low-power modes monitoring pin overview

Power state monitoring pins Description

CSLEEP Sleeping CPU state

CDSLEEP Deepsleep CPU state
DxPWREN Domain (Dx, x= 1 or 2) power enabled

The values of the monitoring pins reflect the state of the CPU and domains. Refer to
Table 48. for the GPIO state depending on CPU and domain state.

Table 48. GPIO state according to CPU and domain state

Domain CPU
Domainx power
CPU power state
DxPWREN state
CSLEEP CDSLEEP

1 0 0 CPU in Run mode

CPU in Sleep
1 1 0 DRun mode
mode
1 0 1 CPU in Run mode
CPU in Deepsleep
1 1 1 DStop mode
mode
0 - - -(1) DStandby mode
1. The full domain is in power off state and the CPU is powered off.

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RM0433 Power control (PWR)

6.8 PWR register description

The PWR registers can be accessed in word, half-word and byte format, unless otherwise
specified.

6.8.1 PWR control register 1 (PWR_CR1)

Address offset: 0x000
Reset value: 0xF000 C000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ALS AVDEN
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVOS Res. Res. Res. Res. FLPS DBP PLS PVDE Res. Res. Res. LPDS
rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:17 ALS: Analog voltage detector level selection
These bits select the voltage threshold detected by the AVD.
00: 1.7 V
01: 2.1 V
10: 2.5 V
11: 2.8 V
Bit 16 AVDEN: Peripheral voltage monitor on VDDA enable
0: Peripheral voltage monitor on VDDA disabled.
1: Peripheral voltage monitor on VDDA enabled
Bits 15:14 SVOS: System Stop mode voltage scaling selection
These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off
between power consumption and performance.
00: Reserved
01: SVOS5 Scale 5
10: SVOS4 Scale 4
11: SVOS3 Scale 3 (default)
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 FLPS: Flash low-power mode in DStop mode
This bit allows to obtain the best trade-off between low-power consumption and restart time
when exiting from DStop mode.
When it is set, the Flash memory enters low-power mode when D1 domain is in DStop
mode.
0: Flash memory remains in normal mode when D1 domain enters DStop (quick restart
time).
1: Flash memory enters low-power mode when D1 domain enters DStop mode (low-power
consumption).

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Power control (PWR) RM0433

Bit 8 DBP: Disable backup domain write protection

In reset state, the RCC_BDCR register, the RTC registers (including the backup registers),
BREN and MONEN bits in PWR_CR2 register, are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC, RTC Backup registers and backup SRAM disabled
1: Access to RTC, RTC Backup registers and backup SRAM enabled
Bits 7:5 PLS: Programmable voltage detector level selection
These bits select the voltage threshold detected by the PVD.
000: 1.95 V
001: 2.1 V
010: 2.25 V
011: 2.4 V
100: 2.55 V
101: 2.7 V
110: 2.85 V
111: External voltage level on PVD_IN pin, compared to internal VREFINT level.
Note: Refer to Section “Electrical characteristics” of the product datasheet for more details.
Bit 4 PVDE: Programmable voltage detector enable
0: Programmable voltage detector disabled.
1: Programmable voltage detector enabled
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 LPDS: Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power,
regardless of the setting of this bit)
0: Voltage regulator in Main mode (MR) when SVOS3 is selected for Stop mode
1: Voltage regulator in Low-power mode (LPR) when SVOS3 is selected for Stop mode

6.8.2 PWR control status register 1 (PWR_CSR1)

Address offset: 0x004
Reset value: 0x0000 4000.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AVDO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTVOSR
ACTVOS Res. Res. Res. Res. Res. Res. Res. Res. PVDO Res. Res. Res. Res.
DY
r r r

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RM0433 Power control (PWR)

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 AVDO: Analog voltage detector output on VDDA
This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the
AVDEN bit.
0: VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits.
1: VDDA is lower than the AVD threshold selected with the ALS[2:0] bits
Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset
until the AVDEN bit is set.
Bits 15:14 ACTVOS: VOS currently applied for VCORE voltage scaling selection.
These bits reflect the last VOS value applied to the voltage regulator.
Bit 13 ACTVOSRDY: Voltage levels ready bit for currently used VOS
This bit is forced by hardware to 1 when the Bypass mode is selected in PWR control
register 3 (PWR_CR3).
0: Voltage level invalid, above or below current VOS selected level.
1: Voltage level valid, at current VOS selected level.
Bits 12:5 Reserved, must be kept at reset value.
Bit 4 PVDO: Programmable voltage detect output
This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the
PVDE bit.
0: VDD or PVD_IN voltage is equal or higher than the PVD threshold selected through the
PLS[2:0] bits.
1: VDD or PVD_IN voltage is lower than the PVD threshold selected through the PLS[2:0]
bits.
Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset
until the PVDE bit is set.
Bits 3:0 Reserved, must be kept at reset value.

6.8.3 PWR control register 2 (PWR_CR2)

Address offset: 0x008
Reset value: 0x0000 0000
This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is
only reset by VSW POR and VSWRST reset.
This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the
VSW domain.
After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit
in PWR_CR1 register must be set to disable the write protection.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. TEMPH TEMPL VBATH VBATL Res. Res. Res. BRRDY
r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MONEN Res. Res. Res. BREN
rw rw

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Bits 31:24 Reserved, must be kept at reset value.

Bit 23 TEMPH: Temperature level monitoring versus high threshold
0: Temperature below high threshold level.
1: Temperature equal or above high threshold level.
Bit 22 TEMPL: Temperature level monitoring versus low threshold
0: Temperature above low threshold level.
1: Temperature equal or below low threshold level.
Bit 21 VBATH: VBAT level monitoring versus high threshold
0: VBAT level below high threshold level.
1: VBAT level equal or above high threshold level.
Bit 20 VBATL: VBAT level monitoring versus low threshold
0: VBAT level above low threshold level.
1: VBAT level equal or below low threshold level.
Bits 19:17 Reserved, must be kept at reset value.
Bit 16 BRRDY: Backup regulator ready
This bit is set by hardware to indicate that the Backup regulator is ready.
0: Backup regulator not ready.
1: Backup regulator ready.
Bits 15:5 Reserved, must be kept at reset value.
Bit 4 MONEN: VBAT and temperature monitoring enable
When set, the VBAT supply and temperature monitoring is enabled.
0: VBAT and temperature monitoring disabled.
1: VBAT and temperature monitoring enabled.
Note: VBAT and temperature monitoring are only available when the backup regulator is
enabled (BREN bit set to 1).
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 BREN: Backup regulator enable
When set, the Backup regulator (used to maintain the backup RAM content in Standby and
VBAT modes) is enabled.
If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in
Run and Stop modes. However, its content will be lost in Standby and VBAT modes.
If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set
to indicate that the data written into the SRAM will be maintained in Standby and VBAT
modes.
0: Backup regulator disabled.
1: Backup regulator enabled.

6.8.4 PWR control register 3 (PWR_CR3)

Address offset: 0x00C
Reset value: 0x0000 0006 (rev Y)
Reset value: 0x0000 0046 (rev V)
This register is reset only by POR. It is not reset by wakeup from Standby mode and by the
RESET pad.

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RM0433 Power control (PWR)

The lower byte of this register is written once after POR and shall be written before changing
VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.
Programming data corresponding to an invalid combination of LDOEN and BYPASS bits
(see Table 34) will be ignored: data will not be written, the written-once mechanism will lock
the register and any further write access will be ignored. The default supply configuration
will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go
on indicating invalid voltage levels. The system shall be power cycled before writing a new
value.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

USBREGEN
USB33RDY

USB33DEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BYPASS
SCUEN

LDOEN
VBRS

VBE

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 USB33RDY: USB supply ready.
0: USB33 supply not ready.
1: USB33 supply ready.
Bit 25 USBREGEN: USB regulator enable.
0: USB regulator disabled.
1: USB regulator enabled.
Bit 24 USB33DEN: VDD33USB voltage level detector enable.
0: VDD33USB voltage level detector disabled.
1: VDD33USB voltage level detector enabled.
Bits 23:10 Reserved, must be kept at reset value.
Bit 9 VBRS: VBAT charging resistor selection
0: Charge VBAT through a 5 kΩ resistor.
1: Charge VBAT through a 1.5 kΩ resistor.
Bit 8 VBE: VBAT charging enable
0: VBAT battery charging disabled.
1: VBAT battery charging enabled.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 SCUEN: Supply configuration update enable
0: Supply configuration update locked.
1: Single write enabled to Supply configuration (LDOEN and BYPASS)
Bit 1 LDOEN: Low drop-out regulator enable
0: Low drop-out regulator disabled.
1: Low drop-out regulator enabled (default)

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Power control (PWR) RM0433

Bit 0 BYPASS: Power management unit bypass

0: Power management unit normal operation.
1: Power management unit bypassed, voltage monitoring still active.

6.8.5 PWR CPU control register (PWR_CPUCR)

This register allows controlling CPU power.
Address offset: 0x010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PDDS_D3

PDDS_D2

PDDS_D1
RUN_D3

SBF_D2

SBF_D1

SOPFF
CSSF

SBF
Res. Res. Res. Res. Res. Res. Res.

rw rw r r r r rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 RUN_D3: Keep system D3 domain in Run mode regardless of the CPU subsystem modes
0: D3 domain follows CPU subsystem modes.
1: D3 domain remains in Run mode regardless of CPU subsystem modes.
Bit 10 Reserved, must be kept at reset value.
Bit 9 CSSF: Clear Standby and Stop flags (always read as 0)
This bit is cleared to 0 by hardware.
0: No effect.
1: STOPF, SBF, SBF_D1, and SBF_D2 flags are cleared.
Bit 8 SBF_D2: D2 domain DStandby flag
This bit is set by hardware and cleared by any system reset or by setting the CSSF bit. Once
set, this bit can be cleared only when the D2 domain is no longer in DStandby mode.
0: D2 domain has not been in DStandby mode
1: D2 domain has been in DStandby mode.
Bit 7 SBF_D1: D1 domain DStandby flag
This bit is set by hardware and cleared by any system reset or by setting the CSSF bit. Once
set, this bit can be cleared only when the D1 domain is no longer in DStandby mode.
0: D1 domain has not been in DStandby mode
1: D1 domain has been in DStandby mode.
Bit 6 SBF: System Standby flag
This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the
CSSF bit
0: System has not been in Standby mode
1: System has been in Standby mode
Bit 5 STOPF: STOP flag
This bit is set by hardware and cleared only by any reset or by setting the CSSF bit.
0: System has not been in Stop mode
1: System has been in Stop mode

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RM0433 Power control (PWR)

Bits 4:3 Reserved, must be kept at reset value.

Bit 2 PDDS_D3: System D3 domain Power Down Deepsleep.
This bit allows defining the Deepsleep mode for System D3 domain.
0: Keep Stop mode when D3 domain enters Deepsleep.
1: Allow Standby mode when D3 domain enters Deepsleep.
Bit 1 PDDS_D2: D2 domain Power Down Deepsleep.
This bit allows defining the Deepsleep mode for D2 domain.
0: Keep DStop mode when D2 domain enters Deepsleep.
1: Allow DStandby mode when D2 domain enters Deepsleep.
Bit 0 PDDS_D1: D1 domain Power Down Deepsleep selection.
This bit allows defining the Deepsleep mode for D1 domain.
0: Keep DStop mode when D1 domain enters Deepsleep.
1: Allow DStandby mode when D1 domain enters Deepsleep.

6.8.6 PWR D3 domain control register (PWR_D3CR)

This register allows controlling D3 domain power.
Address offset: 0x018
Reset value: 0x0000 4000 (Following reset VOSRDY will be read 1 by software).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VOS VOSRDY Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:14 VOS: Voltage scaling selection according to performance
These bits control the VCORE voltage level and allow to obtains the best trade-off between
power consumption and performance:
– When increasing the performance, the voltage scaling shall be changed before increasing
the system frequency.
– When decreasing performance, the system frequency shall first be decreased before
changing the voltage scaling.
00: Reserved (Scale 3 selected).
01: Scale 3 (default)
10: Scale 2
11: Scale 1
Bit 13 VOSRDY: VOS Ready bit for VCORE voltage scaling output selection.
This bit is forced by hardware to 1 when the Bypass mode is selected in PWR control
register 3 (PWR_CR3).
0: Not ready, voltage level below VOS selected level.
1: Ready, voltage level at or above VOS selected level.
Bits 12:0 Reserved, must be kept at reset value.

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Power control (PWR) RM0433

6.8.7 PWR wakeup clear register (PWR_WKUPCR)

Address offset: 0x020
Reset value: 0x0000 0000 (reset only by system reset, not reset by wakeup from Standby
mode)
5 wait states are required when writing this register (when clearing a WKUPF bit in
PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WKUPC6

WKUPC5

WKUPC4

WKUPC3

WKUPC2

WKUPC1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:6 Reserved, always read as 0.

Bits 5:0 WKUPCn:Clear Wakeup pin flag for WKUPn.
These bits are always read as 0.
0: No effect
1: Writing 1 clears the WKUPFn Wakeup pin flag (bit is cleared to 0 by hardware)

6.8.8 PWR wakeup flag register (PWR_WKUPFR)

Address offset: 0x024
Reset value: 0x0000 0000 (reset only by system reset, not reset by wakeup from Standby
mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUPF6

WKUPF5

WKUPF4

WKUPF3

WKUPF2

WKUPF1

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r r r r r

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:0 WKUPn: Wakeup pin WKUPn flag.
This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn bit in the
PWR wakeup clear register (PWR_WKUPCR).
0: No wakeup event occurred
1: A wakeup event was received from WKUPn pin

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RM0433 Power control (PWR)

6.8.9 PWR wakeup enable and polarity register (PWR_WKUPEPR)

Address offset: 0x028
Reset value: 0x0000 0000 (reset only by system reset, not reset by wakeup from Standby
mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WKUPPUPD6

WKUPPUPD5

WKUPPUPD4

WKUPPUPD3

WKUPPUPD2

WKUPPUPD1
Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WKUPEN6

WKUPEN5

WKUPEN4

WKUPEN3

WKUPEN2

WKUPEN1
WKUPP6

WKUPP5

WKUPP4

WKUPP3

WKUPP2

WKUPP1
Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 WKUPPUPD[truncate(n/2)-7): Wakeup pin pull configuration for WKUP(truncate(n/2)-7)
These bits define the I/O pad pull configuration used when WKUPEN(truncate(n/2)-7) = 1. The
associated GPIO port pull configuration shall be set to the same value or to ‘00’.
The Wakeup pin pull configuration is kept in Standby mode.
00: No pull-up
01: Pull-up
10: Pull-down
11: Reserved
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:8 WKUPPn-7: Wakeup pin polarity bit for WKUPn-7
These bits define the polarity used for event detection on WKUPn-7 external wakeup pin.
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:0 WKUPENn+1: Enable Wakeup Pin WKUPn
Each bit is set and cleared by software.
0: An event on WKUPn pin does not wakeup the system from Standby mode.
1: A rising or falling edge on WKUPn+1 pin wakes-up the system from Standby mode.
Note: An additional wakeup event is detected if WKUPn pin is enabled (by setting the WKUPENn
bit) when WKUPn pin level is already high when WKUPPn selects rising edge, or low when
WKUPPn selects falling edge.

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 0x030
0x028
0x024
0x020
0x018
0x014
0x010
0x008
0x004
0x000

0x00C
6.8.10

312/3353
Reserved
PWR_CR3
PWR_CR2
PWR_CR1

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value

PWR_CSR1

PWR_D3CR
PWR_CPUCR

PWR_WKUPFR
PWR_WKUPCR

PWR_WKUPEPR
Offset Register name
Power control (PWR)

Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
Res. Res. Res. Res. Res. Res. Res. Res. 27
WKUPPUPD6

0
0
Res. Res. Res. Res. USB33RDY Res. Res. Res.
PWR register map

26

0
0
Res. Res. Res. Res. USBREGEN Res. Res. Res. 25
WKUPPUPD5

0
0
Res. Res. Res. Res. USB33DEN Res. Res. Res. 24

0
Res. Res. Res. Res. Res. TEMPH Res. Res. 23
WKUPPUPD4

0
Res. Res. Res. Res. Res. TEMPL Res. Res. 22

0
Res. Res. Res. Res. Res. VBATH Res. Res. 21
WKUPPUPD3

0
Res. Res. Res. Res. Res. VBATL Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. 19
WKUPPUPD2
0

Res. Res. Res. Res. Res. Res. Res. 18

Reserved

RM0433 Rev 8
ALS

0 0 0
0

Res. Res. Res. Res. Res. Res. Res. 17

WKUPPUPD1
BRRDY
0

0
0
0

Res. Res. Res. Res. Res. AVDO AVDEN 16

0
0
1

Res. Res. Res. Res. Res. Res. 15

ACTVOS

Reserved

VOS

1
1
1

Res. Res. Res. Res. Res. Res.

SVOS

14

0
0
0

WKUPP6 Res. Res. VOSRDY Res. Res. Res. ACTVOSRDY Res. 13

0
WKUPP5 Res. Res. Res. Res. Res. Res. Res. Res. 12
RUN_D3

0
0
WKUPP4 Res. Res. Res. Res. Res. Res. Res. 11

0
WKUPP3 Res. Res. Res. Res. Res. Res. Res. Res. 10

0
0
0
0

WKUPP2 Res. Res. Res. CSSF VBRS Res. Res. FLPS

Table 49. Power control register map and reset values

0
0
0
0

WKUPP1 Res. Res. Res. SBF_D2 VBE Res. Res. DBP

Refer to Section 2.3 on page 129 for the register boundary addresses.
8
0
0

Res. Res. Res. Res. SBF_D1 Res. Res. Res. 7

0
0

Res. Res. Res. Res. SBF Res. Res. Res. 6

PLS

0
0
0
0
0

WKUPEN6 WKUPF6 WKUPC6 Res. STOPF Res. Res. Res. 5

0
0
0
0

0
0
WKUPEN5 WKUPF5 WKUPC5 Res. Res. Res. MONEN PVDO PVDE 4

0
0
0
WKUPEN4 WKUPF4 WKUPC4 Res. Res. Res. Res. Res. Res. 3

0
0
0
0
1

WKUPEN3 WKUPF3 WKUPC3 Res. PDDS_D3 SCUEN Res. Res. Res. 2

0
0
0
0
1

WKUPEN2 WKUPF2 WKUPC2 Res. PDDS_D2 LDOEN Res. Res. Res. 1

BREN

0
0

0
0
0
0
0

WKUPEN1 WKUPF1 WKUPC1 Res. PDDS_D1 BYPASS Res. LPDS 0

RM0433
RM0433 Low-power D3 domain application example

7 Low-power D3 domain application example

This section describes, through an example, how to use the D3 domain to implement low-
power applications.

7.1 Introduction
The first part of the description explains how the EXTI, RCC and PWR blocks interact with
each other and with the other system blocks. A detailed explanation on how the DMAMUX2
can be used to free the CPU is also provided.
The second part explains how to use the Autonomous mode to perform simple data
transfers through an example of LPUART1 transmission.
Register programming is detailed only for the blocks related to the Autonomous mode.

7.2 EXTI, RCC and PWR interconnections

Figure 38 shows the main EXTI, RCC and PWR interconnections.

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Low-power D3 domain application example RM0433

Figure 38. EXTI, RCC and PWR interconnections

FLASH_busy RCC
AhbBridge_dx_busy
...
ApbBridge_dx_busy

CPU
D1

NVIC

Peripheral
... Irq
interrupts Irq
D2

cpu_deepsleep
Peripherals
IPs
interrupt EXTI rcc_fclk_cpu

wakeup cpu_it_exti_per(0) Irq

...
cpu_it_exti_per(x) Irq

Peripherals
IPs
interrupt
Direct Event inputs
D3

wakeup
d3_it_exti_per(0) ... D3
d3_it_exti_per(n) rcc_fclk_d3
IPs
Peripherals
D3 PendClear[3:0] dmamux_evtx,
Signal
Configurable
Event inputs

lptim[5:4]_out

PWR
cpu_per_alloc_d2
Signal cpu_per_alloc_d1
exti_cpu_wkup
VSW

RTC pwr_d[1:3]_wkup
exti_d3_wkup
Signal
WKUP
D3_DEEPSLEEP d3_deepsleep

MSv41945V2

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RM0433 Low-power D3 domain application example

7.2.1 Interrupts and wakeup

Three kinds of signals are exchanged between the peripherals. They can be used to wake
up the system from Stop mode:
• Wakeup events (or asynchronous interrupts)
Some peripherals can generate interrupt events, even if their bus interface clock is not
present. These interrupt events are called wakeup events (or asynchronous interrupts).
Example: i2c1_wkup, usart1_wkup and lptim1_wkup.
• Signals
Some peripherals generate a pulse instead of an interrupt signal. These pulses are
called signals.
Examples: lptim2_out and lptim3_out.
• Interrupts
Contrary to signals, the interrupts should be cleared by a CPU or any other bus master,
either by clearing the corresponding event bit in the peripheral register or by updating
the FIFO interrupt level.
All the interrupts associated to system peripherals are directly connected to the NVIC,
except for the peripherals which are able to wake up the system from Stop mode or the
CPU from CStop. In this latter case, the interrupts, signals or wakeup events are
connected to the NVIC via the EXTI.
Example: spi1_it, tim1_brk_it and tim1_upd_it.
The interrupt and wakeup sources that require to be cleared in the peripheral itself are
connected to EXTI Direct Event inputs. The EXTI does not manage any CPU status pending
bit.
The peripherals signals are connected to EXTI Configurable Event inputs. These EXTI
inputs provide a CPU status pending bit which needs to be cleared by the application.

7.2.2 Block interactions

Interaction between EXTI and PWR blocks
The EXTI delivers wakeup requests signals (exti_c_wkup, exti_d3_wkup) to the PWR
controller. These signals are activated according to the state of the interrupts, signals or
wakeup events connected to the EXTI. These wakeup requests are used by the PWR
controller to supply the domain who needs to handle the activated wakeup event generated
by the peripherals.

Interaction between PWR and RCC blocks

The PWR block controls the VCORE supply according to the system operating mode (CRun,
CSleep or CStop). The PWR block also controls the power switches (ePODs) that delivers
VCORE supply to D1 and D2 domains.
The RCC block controls the clock generation in accordance with the system operating
mode. It is also responsible for reset generation.

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To synchronize the system mode transitions, the RCC block is tightly coupled with the PWR
controller:
• The RCC informs the PWR controller when peripherals located in the Dx domain are
allocated by the CPU (c_per_alloc_d2, c_per_alloc_d1).
• The RCC also warns the PWR block when a domain clock is activated/deactivated.
These signals are used in case of domain transition from DRun to DStop or DStandby.
In this case, the PWR controller waits until the domain clock has been gated, before
switching down this domain.
• Similarly, the PWR controller informs the RCC about the VCORE supply status of each
domain (pwr_d[1:3]_wkup). This information is used by the RCC when a domain
transition from DStop or DStandby to DRun occurs.

Interaction between EXTI and D3 domain

All the wakeup event inputs received by the EXTI from the peripherals located in D3 domain
are forwarded back to the D3 domain after system clock re-synchronization. These events
are used by the D3 domain to perform autonomous operations without activating the CPU.
The EXTI D3_PenClear[3:0] inputs received from the D3 domain are used to acknowledge
the ongoing wakeup requests generated by peripherals located in the D3 domain. The
D3_PenClear[3:0] inputs allow switching the system D3 domain from Run to Stop mode.

7.2.3 Role of DMAMUX2 in D3 domain

The DMAMUX2 implemented in the D3 domain allows chaining BDMA transfers. BDMA
requests are synchronized thanks to trigger events (dmamux2_evtx) which can be
generated when the expected amount of data has been transferred.
These events can also trigger DMAMUX2 request generators (REQ_GEN[3:0]), and thus
chain several BDMA transfers. In fact REQ_GEN[3:0] can be triggered indirectly by all the
wakeup events generated by all D3 domain peripherals.
Like LPTIM5 and LPTIM4 outputs, dmamux2_evt7 and dmamux2_evt6 events are
connected to the EXTI. They can be used to switch the D3 domain from DRun to DStop
mode when the task requested by the wakeup event is complete.

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7.3 Low-power application example based on

LPUART1 transmission
This section illustrates, through an example, the benefit of the D3 domain usage on power
consumption. To help the user program the device, only the key register settings are given
herein.
Refer to Sections Reset and clock control (RCC) and Power control (PWR) for additional
details.

7.3.1 Memory retention

The D3 domain features 64 Kbytes of SRAM (SRAM4), which can be used to retain data
while the D1 and D2 domains enter DStandby mode.
This feature can be used in several use-cases:
• to retain the application code in order to recover properly from DStandby
• to retain the data from/to a sensor when the CPU enters CStop with D1 or D2 domain in
DStandby) between two consecutive operations.
Note: SRAM4 remains available as long as the system is not in Standby mode.
If the system is in Standby mode, it is still possible to use the BKUP_SRAM. However, its
size is limited to 4 Kbytes.

7.3.2 Memory-to-peripheral transfer using LPUART1 interface

Example description
Figure 39 shows the proposed implementation. At a regular time interval given by LPTIM4,
the CPU wakes up from CStop mode (which domain is in DStandby). When the CPU is in
Run mode, it prepares the data to be transmitted via LPUART1, transfers them to SRAM4,
and goes back to CStop. The D3 domain is configured to perform data transfers via
LPUART1 and go back to Stop mode when the transfer is complete.
The LPTIM4 interface is used to wake up the system from Standby at regular time intervals.
the CPU must then perform the following operations:
1. Recover the application from the system Standby mode (RECO).
2. Process the new data to be sent via LPUART1 (PROC).
3. Transfer the data into SRAM4 (XFER).
4. Configure the DMAMUX2, the BDMA, the LPUART1, and the RCC (CFG).
5. Configure the EXTI (CFG).
6. Configure the PWR block to allow the D1 domain to go to DStandby mode (STP).
7. Set the CPU to Stop mode.
The D3 domain executes the following tasks in Autonomous mode:
1. Transfer the data from SRAM4 to LPUART1, using BDMA.
2. When the LPUART1 interface indicates that the last byte has been transferred, the D3
domain is switched to Stop mode.

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Figure 39. Timing diagram of SRAM4-to-LPUART1 transfer with BDMA and D3 domain
in Autonomous mode

lptim4_wkup

RECO
PROC
PROC

XFER
XFER
STP

STP
STRT
CFG
CPU processing

D1 State OFF DRun DStandby DRun DStandby

D3 processing MEM to LPUART1 Transfer MEM to LPUART1

System / D3
OFF Run Stop Run
State
Peripherals initialization (BDMA, DMAMUX2, PWR, LPTIM4,
STRT Power-on reset startup CFG
LPUART1, EXTI)
RECO Recover from the CStandby XFER Transfer of processed data to SRAM4
PROC Data processing STP Control of EXTI, BDMA and LPUART1 prior to go to CSTOP

MSv41946V4

Note: In the above example described in this section, the D3 domain cannot be kept in Run mode
when D1 and D2 domains are in DStop/DStandby by using the RUN_D3 bit of
PWR_CPUCR register. RUN_D3 will force the D3 domain to Run mode, but it will not be
able to go back to Stop on its own.
If the application needs to toggle the D3 domain between Stop and Run modes, then the
Run mode must be triggered by a wakeup event so that the D3 domain can clear this event
is needed.

RCC programming
In this example, the CPU sub-system also includes the peripherals of D3 domain that are
used for the data transfer, that is BDMA, DMAMUX2, LPUART1 and LPTIM4. These
peripherals must be programmed in Autonomous mode, in order to operate even when the
CPU is in CStop mode.
LPUART1 can use its own APB clock as kernel clock. Since the system will not enter Stop
mode before LPUART1 has completed data transfer, PLLx can be used to provide clocks to
the peripherals.

PWR programming
In this example, the PWR block must be programmed in order to:
• prevent system D3 domain to enter Standby mode when the data transfer is complete,
• allow the D1 domain to enter DStandby,
• define the working voltage according to system modes.
Note: D3 domain could enter Standby as well, but in this case the LPTIM4 could not be used to
wake up the system and the AWU should be used instead. In addition, everything must be
reprogrammed when the system wakes up.

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EXTI programming
The EXTI block must be configured to provide the following services:
• Keep D3 domain running when D1 domain is in DStandby. This will be done by a
software event.
• Set the device to Stop mode when the data transfer via LPUART1 is complete.
• Wake up the product from Stop when LPTIM4 time interval has elapsed.
The EXTI block is configured once before performing the first data transfer. For incoming
data transfers, the programmed configuration remains unchanged; only some events need
to be triggered or acknowledged.
Note: The CPU uses the event input number 0 to generate a software event. LPTIM4 wakeup
signal is connected to event input number 52 (direct event input).
All other event inputs must be disabled: EXTI_RTSRx_TRy = ‘0’ and
EXTI_FTSRx_TRy = ‘0’.
To generate a wakeup event for D3 domain, the CPU must write SWIER0 bit of
EXTI_SWIER1 to ‘1’.

BDMA and DMAMUX2 programming

Two BDMA channels are required to execute data transfers via LPUART1.
• A BDMA channel, such as channel 0, is used to transfer data from SRAM4 to
LPUART1, using the TXE flag.
• The second BDMA channel role is to switch the D3 domain to Stop mode. For that
purpose, DMAMUX2 request generator channel 0 (REQ_GEN0) and DMAMUX2
channel 7 synchronization block (SYNC7) are used in conjunction with BDMA channel
7.
BDMA channel 0 does not use DMAMUX2 trigger capabilities. Refer to Table 50 for
initialization details.
BDMA channel 7 uses REQ_GEN0 to generate BDMA requests. The generation of BDMA
requests is triggered by the LPUART1 transmit interrupt (lpuart1_tx_it). The LPUART1
interface generates lpuart1_tx_it interrupt when the transmit complete event is detected.
The BDMA then clears the pending interrupt by performing a write operation to the
LPUART1.
The SYNC7 block is programmed in Free-running mode. It generates a pulse on its
dmamux2_evt7 output when the BDMA request generated by the REQ_GEN0 is complete.
dmamux2_evt7 signal is used by the EXTI to switch back the D3 domain to Stop mode.
Figure 40 shows the active signal paths via DMAMUX2. The grayed blocks represent the
unused paths.

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Figure 40. BDMA and DMAMUX2 interconnection

LPUART1 DMAMUX2
dmamux_req[15:6] dmamux2_req_out0
lpuart1_tx_dma SYNC0 CH0
dmamux_req7 TC_ReqCnt_ch0
dmamux_req[4:0] BDMA
...
EXTI
dmamux_req[15:1] dmamux2_req_out7
CH7
SYNC7
dmamux_req0
REQ_GEN0

... dmamux2_evt7 D3_PendClear[1]

IT_T 22
dmamux_trg[31:0]
dmamux_sync[15:0]
lpuart1_tx_it

Msv40847V4

Table 50 explain how to program BDMA and DMAMUX2 key functions. The way errors are
handled is not described.

Table 50. BDMA and DMAMUX2 initialization sequence (DMAMUX2_INIT)

Peripherals Register content Related actions

DMAREQ_ID of DMAMUX2_C0CR = ‘10’ Selects LPUART_TX BDMA request.

SE of DMAMUX2_C0CR = ‘0’ Disables block synchronization.
DMAMUX2
EGE of DMAMUX2_C0CR = ‘0’ No event generation.
SYNC0
NBREQ of DMAMUX2_C0CR = ‘0’ Generates an event every BDMA transfer (Free-running
mode).
DMAREQ_ID of DMAMUX2_C7CR = ‘0’ Selects of REQ_GEN0 as BDMA request.
SE of DMAMUX2_C7CR = ‘0’ Disables block synchronization.
DMAMUX2
EGE of DMAMUX2_C7CR = ‘1’ Enables event generation.
SYNC7
NBREQ of DMAMUX2_C7CR = ‘0’ Generates an event every BDMA transfer (Free-running
mode).
SIG_ID of DMAMUX2_RG0CR = ‘0d24’ Selects LPUART TX interrupt as trigger.
DMAMUX2 GPOL of DMAMUX2_RG0CR = ‘0b01’ Trigger on rising edge of the event.
REQ_GEN0 GNBREQ of DMAMUX2_RG0CR = ‘0’ Generates only one BDMA request.
GE of DMAMUX2_RG0CR = ‘1’ Enables generator.

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Table 50. BDMA and DMAMUX2 initialization sequence (DMAMUX2_INIT) (continued)

Peripherals Register content Related actions

NDT bits of BDMA_CNDTR0 = DatNber Number of data to transfer.

PA of BDMA_CPAR0 = &LPUART1_TDR Address of LPUART1_TDR.
MA of BDMA_CMAR0 = &DatBuff Address of memory buffer of SRAM4.
DIR of BDMA_CCR0 = ‘1’ Read from memory.
BDMA - CIRC of BDMA_CCR0 = ‘0’ Circular mode disabled.
CH0 PINC of BDMA_CCR0 = ‘0’ Peripheral increment disabled.
MINC of BDMA_CCR0 = ‘1’ Memory increment enabled.
PSIZE of BDMA_CCR0 = ‘0’ Peripheral size = 8 bits.
MSIZE of BDMA_CCR0 = ‘1’ Memory size = 8 bits.
MEM2MEM of BDMA_CCR0 = ‘0’ Memory to memory disabled.
NDT bits of BDMA_CNDTR7 = ‘1’ Only one data transferred.
PA of BDMA_CPAR7 = &LPUART1_ICR Address of LPUART1_ICR (Interrupt Flag Clear Reg.).
MA of BDMA_CMAR7 = &DatClrTC Address of a variable located into SRAM4. This variable
must contain 0x0040 in order to clear the TC flag.
DIR of BDMA_CCR7 = ‘1’ Read from memory.
BDMA -
CIRC of BDMA_CCR7 = ‘0’ Circular mode disabled.
CH7
PINC of BDMA_CCR7 = ‘0’ Peripheral increment disabled.
MINC of BDMA_CCR7 = ‘1’ Memory increment disabled.
PSIZE of BDMA_CCR7 = 2 Peripheral size = 32 bits.
MSIZE of BDMA_CCR7 = 2 Memory size = 32 bits.
MEM2MEM of BDMA_CCR7 = ‘0’ Memory to memory disabled.

LPTIM4 programming
When LPTIM4 wakeup event occurs, the CPU reboots and D3 domain mode is also set to
Run mode.
An interrupt issued by LPTIM4 is pending on the CPU NVIC. LPTIM4 interrupt handler must
acknowledge this LPTIM4 interrupt by writing ARRMCF bit in LPTIM4_ICR register to ‘1’
(LPTIM4_Ack).

LPUART programming
In the use-case described herein, the capability of the LPUART1 to request the kernel clock
according to some events is not used.
LPUART1 is programmed so that is generates a BDMA request when its TX-FIFO is not full.
LPUART1 also generates an interrupt when the TX-FIFO and its transmit shift register are
empty. This interrupt is used to switch the D3 domain to Stop mode.
Table 51 gives the key settings concerning the handling of Stop mode for LPUART1.

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Table 51. LPUART1 Initial programming (LPUART1_INIT)

Register content Related actions

FIFOEN of LPUART1_CR1 = ‘1’ Enables FIFO. BDMA will then use TXFNF (TXFIFO Not Full) flag for generating
the BDMA requests.
TCIE of LPUART1_CR1 = ‘0’ Disables interrupt when the transmit buffer is empty.
UE of LPUART1_CR1 = ‘1’ Enables BDMA.
TE of LPUART1_CR1 = ‘1’ Enables the LPUART1.
TXE of LPUART1_CR1 = ‘1’ Enables transmission.
DMAT of LPUART1_CR3 = ‘1’ Enables the BDMA mode for transmission.

Respect the sequence described in Table 52 to enable LPUART1.

Table 52. LPUART1 start programming (LPUART1_Start)

Register content Related actions

TCCF of LPUART1_ICR = ‘1’ Clears the TC flag, to avoid immediate interrupt generation, which would clear the
D3_PendClear[1] in EXTI.
TCIE of LPUART1_CR1 = ‘1’ Enables interrupt when the transmit buffer is empty.

7.3.3 Overall description of the low-power application example based on

LPUART1 transmission
After a Power-on reset, the CPU perform the following operations:
1. Boot sequence (not described here).
2. Full initialization of RCC, PWR, EXTI, LPUART1, GPIOs, LPTIM4, DMAMUX2, BDMA
and NVIC.
Only the relevant steps of RCC, EXTI, PWR, LPUART1, BDMA and DMAMUX2
initialization related to the Autonomous mode are described herein. Refer to the
previous sections for additional details.
3. The CPU processes the data to be transferred and copies them to SRAM4.
4. The CPU generates a wakeup event (EXTI_Event) to maintain D3 in Run mode when
D1 enters DStandby.
5. The CPU enables the BDMA to start LPUART transmission and goes to Stop mode. As
it is allowed to do so, D1 domain enters DStandby while D3 remains in Run mode. The
data stored in SRAM4 are retained while the D1 domain is in DStandby mode.
6. As soon as the BDMA is enabled, it serves the request from LPUART1 in order to fill its
TX-FIFO. In parallel, serial data transmission can start.
7. When the expected amount of data has been transmitted (NDT bits of BDMA_CNDTR0
set to 0), the BDMA no longer provides data to the LPUART1. The LPUART1
generates an interrupt when the TX-FIFO and the transmit buffer are empty.
8. This interrupt triggers DMAMUX2 REQ_GEN0, thus activating a data transfer via
BDMA channel 7 (BDMA_Ch7). This transfer clears LPUART1 TC flag, and the
lpuart1_tx_it is reset to ‘0’.
9. The end of this transfer triggers a dmamux2_evt7 signal which is used to clear the
wakeup request generated by the CPU.
10. As a consequence, the D3 domain (i.e. the system) enters Stop mode and the system
clock is gated. LPTIM4 still operates since it uses ck_lsi clock.

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11. LPTIM4 lptim4_wkup interrupt wakes up the system. The device exits from Stop mode
with the HSI clock. The CPU must restore the proper clock configuration during the
warm re-boot sequence and perform the following tasks:
a) Acknowledge LPTIM4 wakeup interrupt,
b) Process the next data block and transfers them to SRAM4,
c) Generate again a wakeup event for D3 domain,
d) Start the BDMA.
e) Go back to CStop mode.
Note: The CPU does not need to initialize BDMA, DMAMUX2 and LPUART1 again.

Figure 41. Timing diagram of LPUART1 transmission with D3 domain

in Autonomous mode
DMAMUX2_INIT

LPUART1_Start

LPUART1_Start
LPUART1_INIT
LPTIM4_Start
LPTIM4_INIT

LPTIM4_Ack
BDMA_Start

BDMA_Start
EXTI_Event

EXTI_Event
Goto CStop

Goto CStop
Warm Boot
PWR_INIT

Data Proc.

Data Proc.
EXTI_INIT
RCC_INIT

NVIC init
...
...

...
...
...

...
Boot

CPU processing 6

lptim4_wkup

D1 State OFF DRun DStandby DRun DStandby

System / D3 State OFF Run Stop Run Stop

LPUART1_TXD D1 D2 D3 DN D1 D2 D3 DN
1 2
bdma_ch0

lpuart1_tx_it 5

bdma_ch7 3

(REQ_GEN0)
4
dmamux2_evt7
5
System Clock

MSv40848V4

7.3.4 Alternate implementations

More power efficient implementations are also possible. As an example the system clock
can be stopped once the data have been transferred to LPUART1 TX-FIFO, instead of
remaining activated during the whole transmission as in the example presented above. In
this case, the LPUART1 must use ck_hsi or ck_csi as kernel clock when the system
switches from Run to Stop mode. LPUART1 must be programmed to wake up D3 domain
when its TX-FIFO in almost empty. This asynchronous interrupt can be used as trigger by
the REQ_GENx of the DMAMUX2, which will perform a given number (e.g. 14) of data
transfers to LPUART1_TDR and then switch back the D3 domain to Stop mode. This
implementation is possible because the LPUART1 can request the kernel clock as long as
the TX-FIFO and transmit buffer are not empty.

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7.4 Other low-power applications

Other peripherals located in D3 domain, such as I2C4, SPI6, SAI4 or ADC3, can be used to
implement low-power applications.

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8 Reset and Clock Control (RCC)

The RCC block manages the clock and reset generation for the whole microcontroller.
The RCC block is located in the D3 domain (refer to Section 6: Power control (PWR) for a
detailed description).
The operating modes this section refers to are defined in Section 6.6.1: Operating modes of
the PWR block.

8.1 RCC main features

Reset block
• Generation of local and system reset
• Bidirectional pin reset allowing to reset the microcontroller or external devices
• WWDG reset supported

Clock generation block

• Generation and dispatching of clocks for the complete device
• 3 separate PLLs using integer or fractional ratios
• Possibility to change the PLL fractional ratios on-the-fly
• Smart clock gating to reduce power dissipation
• 2 external oscillators:
– High-speed external oscillator (HSE) supporting a wide range of crystals from 4 to
48 MHz frequency
– Low-speed external oscillator (LSE) for the 32 kHz crystals
• 4 internal oscillators
– High-speed internal oscillator (HSI)
– 48 MHz RC oscillator (HSI48)
– Low-power Internal oscillator (CSI)
– Low-speed internal oscillator (LSI)
• Buffered clock outputs for external devices
• Generation of two types of interrupts lines:
– Dedicated interrupt lines for clock security management
– One general interrupt line for other events
• Clock generation handling in Stop and Standby mode
• D3 domain Autonomous mode

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8.2 RCC block diagram

Figure 42 shows the RCC block diagram.

Figure 42. RCC Block diagram

RCC (D3)

nreset (system reset) to all circuit

NRST
blocks

perx_rst
rcc_sft_rst pwr_bor_rst
System pwr_por_rst
iwdg1_out_rst Reset
IWDG1 Control pwr_dx_wkup
PWR
wwdg1_out_rst rcc_pwd_dx_req
WWDG1 pwr_hold_ctrl

Core c_sleep
Reset rcc_c_rst Clock Manager
Control (CMU) c_deepsleep CPU

per1_ker_ckreq
PER1
VSW lse_ck ...
lsi_ck M perx_ker_ckreq
OSC32_IN To RTC/ PERx
LSE /CSS lse_ck U
OSC32_OUT hse_ck X AWU

DIV To cores and busses

System Clock
TIM1,8, rcc_ckfail_evt VDD hse_ck
System

Enabling
(SCEU)
15, 16, 17 hsi_ck rcc_bus_ck
En Clock
csi_ck rcc_c_ck
OSC_IN HSE / hse_ck Generation
(SCGU) rcc_fclk_c
CSS
OSC_OUT
hse_ck PLL1
DIVIDERS
DIVIDERS

CRS HSI48 hsi48_ck M

hsi_ck U To peripherals

Peripheral
PLL2

Enabling
(PKEU)
csi_ck X

Clock
LSI lsi_ck PLL3 rcc_perx_ker_ck
hsi_ck Peripheral rcc_perx_bus_ck
HSI
Kernel
csi_ck clock ETH_MII_TX_CLK
AHB Bus

CSI
Selection ETH_MII_RX_CLK
(PKSU) ETH_RMII_REF_CLK
USB_PHY1
I2S_CKIN
rcc_it
Register Interface and Control M
rcc_hsecss_it
DIVIDERS

EXTI U
X MCO1
rcc_lsecss_it E MCO2
S

MSv41926V4

8.3 RCC pins and internal signals

Table 53 lists the RCC inputs and output signals connected to package pins or balls.

Table 53. RCC input/output signals connected to package pins or balls

Signal
Signal name Description
type

NRST I/O System reset, can be used to provide reset to external devices
OSC32_IN I 32 kHz oscillator input
OSC32_OUT O 32 kHz oscillator output
OSC_IN I System oscillator input

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Table 53. RCC input/output signals connected to package pins or balls (continued)
Signal
Signal name Description
type

OSC_OUT O System oscillator output

MCO1 O Output clock 1 for external devices
MCO2 O Output clock 2 for external devices
I2S_CKIN I External kernel clock input for digital audio interfaces: SPI/I2S, SAI, and DFSDM
ETH_MII_TX_CLK I External TX clock provided by the Ethernet MII interface
ETH_MII_RX_CLK I External RX clock provided by the Ethernet MII interface
ETH_RMII_REF_CLK I External reference clock provided by the Ethernet RMII interface
USB_PHY1 I USB clock input provided by the external USB PHY (OTG_HS_ULPI_CK)

The RCC exchanges a lot of internal signals with all components of the product, for that
reason, the Table 53 only shows the most significant internal signals.

Table 54. RCC internal input/output signals

Signal
New Signal name Description
type

rcc_it O General interrupt request line

rcc_hsecss_it O HSE clock security failure interrupt
rcc_lsecss_it O LSE clock security failure interrupt
Event indicating that a HSE clock security failure is detected. This signal is
rcc_ckfail_evt O
connected to TIMERS
nreset I/O System reset
iwdg1_out_rst I Reset line driven by the IWDG1, indicating that a timeout occurred.
wwdg1_out_rst I Reset line driven by the WWDG1, indicating that a timeout occurred.
pwr_bor_rst I Brownout reset generated by the PWR block
pwr_por_rst I Power-on reset generated by the PWR block
pwr_vsw_rst I Power-on reset of the VSW domain generated by the PWR block
rcc_perx_rst O Reset generated by the RCC for the peripherals.
Wake-up domain request generated by the PWR. Generally used to restore the
pwr_d[3:1]_wkup I
clocks a domain when this domain exits from DStop
Low-Power request generated by the RCC. Generally used to ask to the PWR
rcc_pwd_d[3:1]_req O
to set a domain into low-power mode, when a domain is in DStop.
Signals generated by the PWR, in order to set the processor into CStop when
pwr_hold_ctrl I
exiting from system Stop mode.
c_sleep I Signal generated by the CPU, indicating if the CPU is in CRun, CSleep or
c_deepsleep I CStop.

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Table 54. RCC internal input/output signals (continued)

Signal
New Signal name Description
type

Signal generated by some peripherals in order to request the activation of their

perx_ker_ckreq I
kernel clock.
rcc_perx_ker_ck O Kernel clock signals generated by the RCC, for some peripherals.
rcc_perx_bus_ck O Bus interface clock signals generated by the RCC for peripherals.
Clocks for APB (rcc_apb_ck), AHB (rcc_ahb_ck) and AXI (rcc_axi_ck) bridges
rcc_bus_ck O
generated by the RCC.
rcc_c_ck O
Clock for the CPU, generated by the RCC.
rcc_fclk_c O

8.4 RCC reset block functional description

Several sources can generate a reset:
• An external device via NRST pin
• A failure on the supply voltage applied to VDD
• A watchdog timeout
• A software command
The reset scope depends on the source that generates the reset. Three reset categories
exist:
• Power-on/off reset
• System reset
• Local resets

8.4.1 Power-on/off reset

The power-on/off reset (pwr_por_rst) is generated by the power controller block (PWR). It
is activated when the input voltage (VDD) is below a threshold level. This is the most
complete reset since it resets the whole circuit, except the backup domain. The power-on/off
reset function can be disabled through PDR_ON pin (see Section 6.5: Power supply
supervision).
Refer to Table 55: Reset distribution summary for details.

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8.4.2 System reset

A system reset (nreset) resets all registers to their reset values unless otherwise specified
in the register description.
A system reset can be generated from one of the following sources:
• A reset from NRST pin (external reset)
• A reset from the power-on/off reset block (pwr_por_rst)
• A reset from the brownout reset block (pwr_bor_rst)
Refer to Section 6.5.2: Brownout reset (BOR) for a detailed description of the BOR
function.
• A reset from the independent watchdogs (iwdg1_out_rst)
• A software reset from the Cortex®-M7 core
It is generated via the SYSRESETREQ signal issued by the Cortex®-M7 core. This
signal is also named SFTRESET in this document.
• A reset from the window watchdogs depending on WWDG configuration
(wwdg1_out_rst)
• A reset from the low-power mode security reset, depending on option byte
configuration (lpwr[2:1]_rst)
Note: The SYSRESETREQ bit in Cortex®-M7 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the Cortex®-M7 with FPU
technical reference manual for more details (see http://infocenter.arm.com).
As shown in Figure 43, some internal sources (such as pwr_por_rst, pwr_bor_rst,
iwdg1_out_rst) perform a system reset of the circuit, which is also propagated to the NRST
pin to reset the connected external devices. The pulse generator guarantees a minimum
reset pulse duration of 20 μs for each internal reset source. In case of an external reset, the
reset pulse is generated while the NRST pin is asserted Low.
Note: It is not recommended to let the NRST pin unconnected. When it is not used, connect this
pin to ground via a 10 to 100 nFcapacitor (CR in Figure 43).

Figure 43. System reset circuit

RCC
VDD
Filter nreset (System Reset)

RPU
pwr_bor_rst
NRST
(External reset) pwr_por_rst
CR iwdg1_out_rst
Pulse generator OR
(20 μs min) wwdg1_out_rst
lpwr_rst
SFTRESET

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8.4.3 Local resets

CPU reset
The CPU can reset itself by means of the CPURST bit in RCC AHB3 reset register
(RCC_AHB3RSTR).

Domain reset
Some resets also dependent on the domain status. For example, when D1 domain exits
from DStandby, it is reset (d1_rst). The same mechanism applies to D2.
When the system exits from Standby mode, a stby_rst reset is applied. The stby_rst signal
generates a reset of the complete VCORE domain as long the VCORE voltage provided by the
internal regulator is not valid.
Table 55 gives a detailed overview of reset sources and scopes.

Table 55. Reset distribution summary

D1 Interconnect

D2 Interconnect

System Supply
D1 Peripherals

D2 Peripherals
D3 Peripherals

Backup RAM
RTC domain
D1 Debug

NRST pin
WWDG1
D1 CPU

FLASH
IWDG1

Reset
Reset name Comments
source

– Resets D1 and D2 domains, and all their

peripherals
– Resets D3 domain peripherals
Pin NRST x x x - x x x x x - - - - x
– Resets VDD domain: IWDG1, LDO...
– Debug features, Flash memory, RTC and
backup RAM are not reset
– Same as pin reset. The pin is asserted as
pwr_bor_rst x x x - x x x x x - - - - x
well.
– Same as pwr_bor_rst reset, plus:
Reset of the Flash memory digital block
pwr_por_rst x x x x x x x x x x - - x x
(including the option byte loading).
PWR Reset of the debug block
– The low-power mode security reset has
the same scope than pwr_por_rst. Refer
lpwr_rst x x x - x x x x x - - - - x to Section 8.4.5: Low-power mode
security reset (lpwr_rst) for additional
information.

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Table 55. Reset distribution summary (continued)

D1 Interconnect

D2 Interconnect

System Supply
D1 Peripherals

D2 Peripherals
D3 Peripherals

Backup RAM
RTC domain
D1 Debug

NRST pin
WWDG1
D1 CPU

FLASH
IWDG1
Reset
Reset name Comments
source

– The backup domain reset can be

triggered by software. Refer to
BDRST - - - - - - - - - - x - - -
Section 8.4.6: Backup domain reset for
additional information
– Resets D1 domain, and all its
d1_rst x x x x x - - - - - - - - - peripherals, when the domain exits
DStandby mode.
– Resets D2 domain, and all its
d2_rst - - - - - x x - - - - - - - peripherals, when the domain exits
DStandby mode.
RCC
– When the device exits Standby mode, a
reset of the complete VCORE domain is
performed as long the VCORE voltage is
stby_rst x x x x x x x x - - - - - - not valid. The VCORE is supplied by the
internal regulator.
NRST signal is not asserted.
– This reset is generated by software
through the bit located into RCC AHB3
CPURST x - - - x - - - - - - - - - reset register (RCC_AHB3RSTR).
– Resets the CPU, and the WWDG1 block
– This reset is generated by software when
writing SYSRESETREQ bit located into
CPU SFTRESET x x x - x x x x x - - - - x AIRCR register of the Cortex®-M7 core.
– Same scope as pwr_bor_rst reset.
– This reset is generated by the backup
Backup
pwr_vsw_rst - - - - - - - - - - x - - - domain when the VSW supply voltage is
domain
outside the operating range.
IWDG1 iwdg1_out_rst x x x - x x x x x - - - - x – Same as pwr_bor_rst reset.
WWDG1 wwdg1_out_rst x x x - x x x x x - - - - x – Same as pwr_bor_rst reset.

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8.4.4 Reset source identification

The CPU can identify the reset source by checking the reset flags in the RCC_RSR (or
RCC_C1_RSR) register.
The CPU can reset the flags by setting RMVF bit.
Table 56 shows how the status bits of RCC_RSR (or RCC_C1_RSR) register behaves,
according to the situation that generated the reset. For example when an IWDG1 timeout
occurs (line #10), if the CPU is reading the RCC_RSR (or RCC_C1_RSR) register during
the boot phase, both PINRSTF and IWDG1RSTF bits are set, indicating that the IWDG1
also generated a pin reset.

Table 56. Reset source identification (RCC_RSR)(1)

WWDG1RSTF

IWDG1RSTF
LPWRRSTF

BORRSTF
PORRSTF

CPURSTF
SFTRSTF

PINRSTF

D2RSTF

D1RSTF
# Situations Generating a Reset

1 Power-on reset (pwr_por_rst) 0 0 0 0 1 1 1 1 1 1

2 Pin reset (NRST) 0 0 0 0 0 1 0 0 0 1
3 Brownout reset (pwr_bor_rst) 0 0 0 0 0 1 1 0 0 1
4 System reset generated by CPU (SFTRESET) 0 0 0 1 0 1 0 0 0 1
5 CPU reset (CPURST) 0 0 0 0 0 0 0 0 0 1
6 WWDG1 reset (wwdg1_out_rst) 0 1 0 0 0 1 0 0 0 1
8 IWDG1 reset (iwdg1_out_rst) 0 0 1 0 0 1 0 0 0 1
10 D1 exits DStandby mode 0 0 0 0 0 0 0 0 1 0
11 D2 exits DStandby mode 0 0 0 0 0 0 0 1 0 0
D1 erroneously enters DStandby mode or
12 1 0 0 0 0 1 0 0 0 1
CPU erroneously enters CStop mode
1. Grayed cells highlight the register bits that are set.

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8.4.5 Low-power mode security reset (lpwr_rst)

To prevent critical applications from mistakenly enter a low-power mode, two low-power
mode security resets are available. When enabled through nRST_STOP_D1 option bytes, a
system reset is generated if the following conditions are met:
• CPU accidentally enters CStop mode
This type of reset is enabled by resetting nRST_STOP_D1 user option byte. In this
case, whenever the CPU CStop mode entry sequence is successfully executed, a
system reset is generated.
• D1 domain accidentally enters DStandby mode
This type of reset is enabled by resetting nRST_STDBY_D1 user option byte. In this
case, whenever a D1 domain DStandby mode entry sequence is successfully
executed, a system reset is generated.
LPWRRSTF bits in RCC reset status register (RCC_RSR) indicates that a low-power mode
security reset occurred (see line #12 in Table 56).
lpwr_rst is activated when a low-power mode security reset due to D1 or CPU occurred.
Refer to Section 4.4: FLASH option bytes for additional information.

8.4.6 Backup domain reset

A backup domain reset is generated when one of the following events occurs:
• A software reset, triggered by setting BDRST bit in the RCC backup domain control
register (RCC_BDCR). All RTC registers and the RCC_BDCR register are reset to their
default values. The backup RAM is not affected.
• VSW voltage is outside the operating range. All RTC registers and the RCC_BDCR
register are reset to their default values. In this case the content of the backup RAM is
no longer valid.
There are two ways to reset the backup RAM:
• through the Flash memory interface by requesting a protection level change from 1 to 0
• when a tamper event occurs.
Refer to Section 6.4.4: Backup domain section of PWR block for additional information.

8.4.7 Power-on and wakeup sequences

For detailed diagrams refer to Section 6.4.1: System supply startup in the PWR section.
The time interval between the event which exits the product from a low-power and the
moment where the CPU is able to execute code, depends on the system state and on its
configuration. Figure 44 shows the most usual examples.

Power-on wakeup sequence

The power-on wakeup sequence shown in Figure 44 gives the most significant phases of
the power-on sequence. It is the longest sequence since the circuit was not powered. Note
that this sequence remains unchanged, whatever VBAT was present or not.

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Boot from pin reset

When a pin reset occurs, VDD is still present. As a results:
• The regulator settling time is faster since the reference voltage is already stable.
• The HSI restart delay may be needed if the HSI was not enabled when the NRST
occurred, otherwise this restart delay phase is skipped.
• The Flash memory power recovery delay can also be skipped if the Flash memory was
enabled when the NRST occurred.
Note: The boot sequence is similar for pwr_bor_rst, lpwr_rst, STFxRESET, iwdg1_out_rst and
wwdg1_out_rst (if WW1RSC = ‘1’).

Boot from system Standby

When waking up from system Standby, the reference voltage is stable since VDD has not
been removed. As a result, the regulator settling time is fast. Since VCORE was not present,
the restart delay for the HSI, the Flash memory power recovery and the option byte
reloading cannot be skipped.

Restart from system Stop

When restarting from system Stop, VDD is still present. As a result, the sequence is mainly
composed of two steps:
1. Regulator settling time to reach VOS3 (default voltage)
2. HSI/CSI restart delay. This step can be skipped if HSIKERON or CSIKERON bit, in
RCC source control register (RCC_CR) is set to ‘1’.

Boot from domain DStandby

The boot sequence of a domain from domain DStandby is mainly composed of two steps:
1. The power switch settling time (the regulator is already activated).
2. The Flash memory power recovery.

Restart from domain DStop

The restart sequence of a domain from domain DStop is mainly composed of the handshake
between the RCC, EXTI and PWR blocks.

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Figure 44. Boot sequences versus system states

Power-on wake-up (with or without VBAT)

VDD > POR

REG + BandGap HSI FL_PWR FL_OPTB RUN

Time
NRST goes PAD Reset (or pwr_bor_rst, SFTRESET, iwdg1_out_rst,…)
HIGH

REG (HSI) (FL_PWR) RUN

Time

Wakeup Wake-up from system Standby

event

REG HSI FL_PWR FL_OPTB RUN

Time
Wakeup Re-start from system Stop
event

REG_VOS3 (HSI/CSI) RUN

Time

Wakeup Wake-up from Domain DStandby

event

ePOD FL_PWR RUN

Time

Wakeup Re-start from Domain DStop

event

D RUN
Time

REG + BandGap Bandgap and regulator settling time FL_PWR Flash power recovery delay RUN CPU Fetch
Delay due to handshake RCC, PWR and
REG_VOS3 REG settling time to reach the VOS3 FL_OPTB Option bytes loading delay D
EXTI

REG REG settling time ePOD Power switch delay delay HSI/CSI HSI or CSI Restart delay

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8.5 RCC clock block functional description

The RCC provides a wide choice of clock generators:
• HSI (High-speed internal oscillator) clock: ~ 8, 16, 32 or 64 MHz
• HSE (High-speed external oscillator) clock: 4 to 48 MHz
• LSE (Low-speed external oscillator) clock: 32 kHz
• LSI (Low-speed internal oscillator) clock: ~ 32 kHz
• CSI (Low-power internal oscillator) clock: ~4 MHz
• HSI48 (High-speed 48 MHz internal oscillator) clock: ~48 MHz
It offers a high flexibility for the application to select the appropriate clock for CPU and
peripherals, in particular for peripherals that require a specific clock such as Ethernet, USB
OTG-FS and HS, SPI/I2S, SAI and SDMMC.
To optimize the power consumption, each clock source can be switched ON or OFF
independently.
The RCC provides up to 3 PLLs; each of them can be configured with integer or fractional
ratios.
As shown in the Figure 45, the RCC offers 2 clock outputs (MCO1 and MCO2), with a great
flexibility on the clock selection and frequency adjustment.
The SCGU block (System Clock Generation Unit) contains several prescalers used to
configure the CPU and bus matrix clock frequencies.
The PKSU block (Peripheral Kernel clock Selection Unit) provides several dynamic switches
allowing a large choice of kernel clock distribution to peripherals.
The PKEU (Peripheral Kernel clock Enable Unit) and SCEU (System Clock Enable Unit)
blocks perform the peripheral kernel clock gating, and the bus interface/cores/bus matrix
clock gating, respectively.

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Figure 45. Top-level clock tree

RCC

VDD Domain
LSION or IWDG1 activated
lsi_ck To
LSI tempo IWDG1

VSW (Backup) RTCSRC

RTCEN
LSEON 0 0
OSC32_IN lse_ck lse_ck rcc_rtc_ck To
LSE tempo 1
OSC32_OUT lsi_ck D RTC/AWU
2
CSS hse_1M_ck
3

RTCPRE MCO1SEL

÷ 2 to 63 hsi_ck 0 MCO1PRE
lse_ck 1
hse_ck ÷ 1 to15 MCO1
2
VDD Domain pll1_q_ck 3
HSEON hsi48_ck 4
OSC_IN MCO2
tempo hse_ck
HSE MCO2SEL
OSC_OUT
CSS sys_ck 0 MCO2PRE
pll2_p_ck 1 To TPIU
HSIKERON HSIDIV hse_ck 2 ÷ 1 to15
HSION pll1_p_ck 3
hsi_ck
HSI tempo ÷1,2,4,8 csi_ck 4 hsi_ck 0
lsi_ck 5 csi_ck 1 traceclkin
hsi_ker_ck D
hse_ck 2

SCGU (System Clock

SCEU (System Clock

CSIKERON SW pll1_r_ck 3
CSION

Generation)
csi_ck

Enabling)
CSI tempo
hsi_ck To CPU,
0 busses and
HSI48ON csi_ker_ck csi_ck
1 sys_ck peripherals
CRS hse_ck D
HSI48 hsi48_ck 2
Clock pll1_p_ck 3
recovery
system CKPERSRC
hsi_ker_ck
0 pll[3:1]_q_ck
csi_ker_ck
1 per_ck
PKSU (Peripheral Kernel clock Selection)

hse_ck pll[3:2]_p_ck
2
PKEU (Peripheral Clock Enabling)

PLLSRC pll[3:2]_r_ck
hsi_ck sys_ck
0 PLL1
csi_ck ref1_ck per_ck
1 ÷ DIVM1 pll1_p_ck
hse_ck VCO DIVP1 hse_ck
2 1 to 16 pll1_q_ck To
MHz DIVN1 DIVQ1 hsi_ker_ck
peripherals
DIVR1 pll1_r_ck csi_ker_ck
FRACN1
lsi_ck
lse_ck
PLL2 hsi48_ck
ref2_ck pll2_p_ck
÷ DIVM2 DIVP2
1 to 16 VCO
MHz pll2_q_ck
DIVN2 DIVQ2
pll2_r_ck
DIVR2
FRACN2

I2S_CKIN
PLL3
ref3_ck pll3_p_ck ETH_MII_TX_CLK
÷ DIVM3 VCO DIVP3
1 to 16 ETH_MII_RX_CLK
MHz pll3_q_ck
DIVN3 DIVQ3 ETH_RMII_REF_CLK
pll3_r_ck
DIVR3
FRACN3
ulpi1_phy_ck
USB_PHY1
ulpi2_phy_ck
USB_PHY2

D The selected input can be changed on-the-fly without spurs on the output signal x Represents the selected mux input after a system reset
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8.5.1 Clock naming convention

The RCC provides clocks to the complete circuit. To avoid misunderstanding, the following
terms are used in this document:
• Peripheral clocks
The peripheral clocks are the clocks provided by the RCC to the peripherals. Two kinds
of clock are available:
– The bus interface clocks
– The kernel clocks
A peripheral receives from the RCC a bus interface clock in order to access its
registers, and thus control the peripheral operation. This clock is generally the AHB,
APB or AXI clock depending on which bus the peripheral is connected to. Some
peripherals only need a bus interface clock (e.g. RNG, TIMx).
Some peripherals also require a dedicated clock to handle the interface function. This
clock is named “kernel clock”. As an example, peripherals such as SAI have to
generate specific and accurate master clock frequencies, which require dedicated
kernel clock frequencies. Another advantage of decoupling the bus interface clock from
the specific interface needs, is that the bus clock can be changed without
reprogramming the peripheral.
• CPU clocks
The CPU clock is the clock provided to the CPU. It is derived from the system clock
(sys_ck).
• Bus matrix clocks
The bus matrix clocks are the clocks provided to the different bridges (APB, AHB or
AXI). These clocks are derived from the system clock (sys_ck).

8.5.2 Oscillators description

HSE oscillator
The HSE block can generate a clock from two possible sources:
• External crystal/ceramic resonator
• External clock source

Figure 46. HSE/LSE clock source

External clock configuration Crystal/ceramic resonators configuration

OSC32_IN OSC32_OUT OSC32_IN OSC32_OUT

OSC_IN OSC_OUT OSC_IN OSC_OUT

GPIO

External clock
source CL1 CL2
Load
capacitors

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External clock source (HSE bypass)

In this mode, an external clock source must be provided to OSC_IN pin. This mode is
selected by setting the HSEBYP and HSEON bits of the RCC source control register
(RCC_CR) to ‘1’. The external clock source (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC_IN pin.
External crystal/ceramic resonator
The oscillator is enabled by setting the HSEBYP bit to ‘0’ and HSEON bit to ‘1’.
The HSE can be used when the product requires a very accurate high-speed clock.
The associated hardware configuration is shown in Figure 46: the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and startup stabilization time. The loading capacitance values must be
adjusted according to the selected crystal or ceramic resonator. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag of the RCC source control register (RCC_CR), indicates whether the
HSE oscillator is stable or not. At startup, the hse_ck clock is not released until this bit is set
by hardware. An interrupt can be generated if enabled in the RCC clock source interrupt
enable register (RCC_CIER).
The HSE can be switched ON and OFF through the HSEON bit. Note that the HSE cannot
be switched OFF if one of the two conditions is met:
• The HSE is used directly (via software mux) as system clock
• The HSE is selected as reference clock for PLL1, with PLL1 enabled and selected to
provide the system clock (via software mux).
In that case the hardware does not allow programming the HSEON bit to ‘0’.
The HSE is automatically disabled by hardware, when the system enters Stop or Standby
mode (refer to Section 8.5.7: Handling clock generators in Stop and Standby mode for
additional information).
In addition, the HSE clock can be driven to the MCO1 and MCO2 outputs and used as clock
source for other application components.

LSE oscillator
The LSE block can generate a clock from two possible sources:
• External crystal/ceramic resonator
• External user clock
External clock source (LSE bypass)
In this mode, an external clock source must be provided to OSC32_IN pin. The input clock
can have a frequency up to 1 MHz. This mode is selected by setting the LSEBYP and
LSEON bits of RCC backup domain control register (RCC_BDCR) to ‘1’. The external clock
signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin.

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External crystal/ceramic resonator (LSE crystal)

The LSE clock is generated from a 32.768 kHz crystal or ceramic resonator. It has the
advantage to provide a low-power highly accurate clock source to the real-time clock (RTC)
for clock/calendar or other timing functions.
The LSERDY flag of the RCC backup domain control register (RCC_BDCR) indicates
whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not
released until this bit is set by hardware. An interrupt can be generated if enabled in the
RCC clock source interrupt enable register (RCC_CIER).
The LSE oscillator is switched ON and OFF using the LSEON bit. The LSE remains enabled
when the system enters Stop or Standby mode.
In addition, the LSE clock can be driven to the MCO1 output and used as clock source for
other application components.
The LSE also offers a programmable driving capability (LSEDRV[1:0]) that can be used to
modulate the amplifier driving capability. The driving capability can be changed dynamically
from high drive to medium high drive, and then to medium low drive.

HSI oscillator
The HSI block provides the default clock to the product.
The HSI is a high-speed internal RC oscillator which can be used directly as system clock,
peripheral clock, or as PLL input. A predivider allows the application to select an HSI output
frequency of 8, 16, 32 or 64 MHz. This predivider is controlled by the HSIDIV.
The HSI advantages are the following:
• Low-cost clock source since no external crystal is required
• Faster startup time than HSE (a few microseconds)
The HSI frequency, even with frequency calibration, is less accurate than an external crystal
oscillator or ceramic resonator.
The HSI can be switched ON and OFF using the HSION bit. Note that the HSI cannot be
switched OFF if one of the two conditions is met:
• The HSI is used directly (via software mux) as system clock
• The HSI is selected as reference clock for PLL1, with PLL1 enabled and selected to
provide the system clock (via software mux).
In that case the hardware does not allow programming the HSION bit to ‘0’.
Note that the HSIDIV cannot be changed if the HSI is selected as reference clock for at least
one enabled PLL (PLLxON bit set to ‘1’). In that case the hardware does not update the
HSIDIV with the new value. However it is possible to change the HSIDIV if the HSI is used
directly as system clock.
The HSIRDY flag indicates if the HSI is stable or not. At startup, the HSI output clock is not
released until this bit is set by hardware.
The HSI clock can also be used as a backup source (auxiliary clock) if the HSE fails (refer to
Section : CSS on HSE). The HSI can be disabled or not when the system enters Stop mode,
please refer to Section 8.5.7: Handling clock generators in Stop and Standby mode for
additional information.
In addition, the HSI clock can be driven to the MCO1 output and used as clock source for
other application components.

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Care must be taken when the HSI is used as kernel clock for communication peripherals,
the application must take into account the following parameters:
• the time interval between the moment where the peripheral generates a kernel clock
request and the moment where the clock is really available,
• the frequency accuracy.
Note: The HSI can remain enabled when the system is in Stop mode (see Section 8.5.7 for
additional information).
HSION, HSIRDY and HSIDIV bits are located in the RCC source control register
(RCC_CR).
HSI calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations. That is why each device is factory calibrated by STMicroelectronics to improve
accuracy (refer to the product datasheet for more information).
After a power-on reset, the factory calibration value is loaded in the HSICAL[11:0] bits.
If the application is subject to voltage or temperature variations, this may affect the RC
oscillator frequency. The user application can trim the HSI frequency using the HSITRIM
bits.
Note: HSICAL and HSITRIM bits are located in RCC internal clock source calibration register
(RCC_ICSCR). for revision Y devices and in RCC HSI configuration register
(RCC_HSICFGR) for revision V devices.

CSI oscillator
The CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
clock, or PLL input.
The CSI advantages are the following:
• Low-cost clock source since no external crystal is required
• Faster startup time than HSE (a few microseconds)
• Very low-power consumption,
The CSI provides a clock frequency of about 4 MHz, while the HSI is able to provide a clock
up to 64 MHz.
CSI frequency, even with frequency calibration, is less accurate than an external crystal
oscillator or ceramic resonator.
The CSI can be switched ON and OFF through the CSION bit. The CSIRDY flag indicates
whether the CSI is stable or not. At startup, the CSI output clock is not released until this bit
is set by hardware.
The CSI cannot be switched OFF if one of the two conditions is met:
• The CSI is used directly (via software mux) as system clock
• The CSI is selected as reference clock for PLL1, with PLL1 enabled and selected to
provide the system clock (via software mux).
In that case the hardware does not allow programming the CSION bit to ‘0’.
The CSI can be disabled or not when the system enters Stop mode (refer to Section 8.5.7:
Handling clock generators in Stop and Standby mode for additional information).

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In addition, the CSI clock can be driven to the MCO2 output and used as clock source for
other application components.
Even if the CSI settling time is faster than the HSI, care must be taken when the CSI is used
as kernel clock for communication peripherals: the application has to take into account the
following parameters:
• the time interval between the moment where the peripheral generates a kernel clock
request and the moment where the clock is really available,
• the frequency precision.
Note: CSICAL and CSITRIM bits are located into the RCC source control register (RCC_CR) or
revision Y devices and RCC CSI configuration register (RCC_CSICFGR) for revision V
devices.
CSI calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by STMicroelectronics to achieve
improve (refer to the product datasheet for more information).
After reset, the factory calibration value is loaded in the CSICAL[7:0] bits.
If the application is subject to voltage or temperature variations, this may affect the RC
oscillator frequency. The user application can trim the CSI frequency using the CSITRIM
bits.
Note: CSICAL and CSITRIM bits are located in RCC internal clock source calibration register
(RCC_ICSCR) for revision Y devices and in RCC CSI configuration register
(RCC_CSICFGR) for revision V devices.

HSI48 oscillator
The HSI48 is an RC oscillator that delivers a 48 MHz clock that can be used directly as
kernel clock for some peripherals.
The HSI48 oscillator mainly aims at providing a high precision clock to the USB peripheral
by means of a special Clock Recovery System (CRS) circuitry, which could use the USB
SOF signal, the LSE, or an external signal, to automatically adjust the oscillator frequency
on-the-fly, in very small granularity.
The HSI48 oscillator is disabled as soon as the system enters Stop or Standby mode. When
the CRS is not used, this oscillator is free running and thus subject to manufacturing
process variations. That is why each device is factory calibrated by STMicroelectronics to
achieve an accuracy of ACCHSI48 (refer to the product datasheet of the for more
information).
For more details on how to configure and use the CRS, please refer to Section 9: Clock
recovery system (CRS).
The HSI48RDY flag indicates whether the HSI48 oscillator is stable or not. At startup, the
HSI48 output clock is not released until this bit is set by hardware.
The HSI48 can be switched ON and OFF using the HSI48ON bit.
The HSI48 clock can also be driven to the MCO1 multiplexer and used as clock source for
other application components.
Note: HSI48ON and HSI48RDY bits are located in the RCC source control register (RCC_CR).

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LSI oscillator
The LSI acts as a low-power clock source that can be kept running when the system is in
Stop or Standby mode for the independent watchdog (IWDG) and Auto-Wakeup Unit
(AWU). The clock frequency is around 32 kHz. For more details, refer to the electrical
characteristics section of the datasheet.
The LSI can be switched ON and OFF using the LSION bit. The LSIRDY flag indicates
whether the LSI oscillator is stable or not. If an independent watchdog is started either by
hardware or software, the LSI is forced ON and cannot be disabled.
The LSI remains enabled when the system enters Stop or Standby mode (refer to
Section 8.5.7: Handling clock generators in Stop and Standby mode for additional
information).
At LSI startup, the clock is not provided until the hardware sets the LSIRDY bit. An interrupt
can be generated if enabled in the RCC clock source interrupt enable register (RCC_CIER).
In addition, the LSI clock can be driven to the MCO2 output and used as a clock source for
other application components.
Note: Bits LSION and LSIRDY are located into the RCC clock control and status register
(RCC_CSR).

8.5.3 Clock Security System (CSS)

CSS on HSE
The clock security system can be enabled by software via the HSECSSON bit. The
HSECSSON bit can be enabled even when the HSEON is set to ‘0’.
The CSS on HSE is enabled by the hardware when the HSE is enabled and ready, and
HSECSSON set to ‘1’.
The CSS on HSE is disabled when the HSE is disabled. As a result, this function does not
work when the system is in Stop mode.
It is not possible to clear directly the HSECSSON bit by software.
The HSECSSON bit is cleared by hardware when a system reset occurs or when the
system enters Standby mode (see Section 8.4.2: System reset).
If a failure is detected on the HSE clock, the system automatically switches to the HSI in
order to provide a safe clock. The HSE is then automatically disabled, a clock failure event
is sent to the break inputs of advanced-control timers (TIM1, TIM8, TIM15, TIM16, and
TIM17), and an interrupt is generated to inform the software about the failure (CSS interrupt:
rcc_hsecss_it), thus allowing the MCU to perform rescue operations. If the HSE output
was used as clock source for PLLs when the failure occurred, the PLLs are also disabled.
If an HSE clock failure occurs when the CSS is enabled, the CSS generates an interrupt
which causes the automatic generation of an NMI. The HSECSSF flag in RCC clock source
Interrupt flag register (RCC_CIFR) is set to ‘1’ to allow the application to identify the failure
source. The NMI routine is executed indefinitely until the HSECSSF bit is cleared. As a
consequence, the application has to clear the HSECSSF flag in the NMI ISR by setting the
HSECSSC bit in the RCC clock source interrupt clear register (RCC_CICR).

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CSS on LSE
A clock security system on the LSE oscillator can be enabled by software by programming
the LSECSSON bit in the RCC backup domain control register (RCC_BDCR).
This bit can be disabled only by hardware when the following conditions are met:
• after a pwr_vsw_rst (VSW software reset)
• or after a failure detection on LSE.
LSECSSON bit must be written after the LSE is enabled (LSEON bit set by software) and
ready (LSERDY set by hardware), and after the RTC clock has been selected through the
RTCSEL bit.
The CSS on LSE works in all modes (Run, Stop and Standby) except VBAT.
If an LSE failure is detected, the LSE clock is no more delivered to the RTC but the value of
RTCSEL, LSECSSON and LSEON bits are not changed by the hardware.
A wakeup is generated in Standby mode. In other modes an interrupt (rcc_lsecss_it) can
be sent to wake up the software. The software must then disable the LSECSSON bit, stop
the defective LSE (clear LSEON bit), and can change the RTC clock source (no clock or LSI
or HSE) through RTCSEL bits, or take any required action to secure the application.

8.5.4 Clock output generation (MCO1/MCO2)

Two micro-controller clock output (MCO) pins, MCO1 and MCO2, are available. A clock
source can be selected for each output.The selected clock can be divided thanks to
configurable prescaler (refer to Figure 45 for additional information on signal selection).
MCO1 and MCO2 outputs are controlled via MCO1PRE[3:0], MCO1[2:0], MCO2PRE[3:0]
and MCO2[2:0] located in the RCC clock configuration register (RCC_CFGR).
The GPIO port corresponding to each MCO pin, has to be programmed in alternate function
mode.
The clock provided to the MCOs outputs must not exceed the maximum pin speed (refer to
the product datasheet for information on the supported pin speed).

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8.5.5 PLL description

The RCC features three PLLs:
• A main PLL, PLL1, which is generally used to provide clocks to the CPU and to some
peripherals.
• Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for
peripherals.
The PLLs integrated into the RCC are completely independent. They offer the following
features:
• Two embedded VCOs:
– A wide-range VCO (VCOH)
– A low-frequency VCO (VCOL)
• Input frequency range:
– 1 to 2 MHz when VCOL is used
– 2 to 16 MHz when VCOH is used
• Capability to work either in integer or Fractional mode
• 13-bit Sigma-Delta modulator, allowing to fine-tune the VCO frequency by steps of 11
to 0.3 ppm.
• The Sigma-Delta modulator can be updated on-the-fly, without generating frequency
overshoots on PLLs outputs.
• Each PLL offer 3 outputs with post-dividers

Figure 47. PLL block diagram

PLLx PLLxRGE
192 to 960 MHz
2 to 16 MHz
3)'&3 LPF VCOH 0
0 vcox_ck
UHI[BFN ·DIVPx 
DIVPxEN SOO[BSBFN
 150 to 420 MHz
1 to 2 MHz
3)'&3 LPF VCOL  DIVQx
PLLxVCOSEL
·1 SOO[BTBFN
DIVQxEN
DIVNx PLLxVCOSEL
DIVRx

·«128« ·1 SOO[BUBFN

DIVRxEN

Ȉǻ0RGXODWRU

PLLxFRACEN 6+B5(* LDO 1V

FRACNx

9''$
',93[ 2ZKHQ[ DQG',93[ 1IRU[ RU

MSv39366V2

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The PLLs are controlled via RCC_PLLxDIVR, RCC_PLLxFRACR, RCC_PLLCFGR and

RCC_CR registers.
The frequency of the reference clock provided to the PLLs (refx_ck) must range from 1 to
16 MHz. The user application has to program properly the DIVMx dividers of the RCC PLL
clock source selection register (RCC_PLLCKSELR) in order to match this condition. In
addition, the PLLxRGE of the RCC PLL configuration register (RCC_PLLCFGR) field must
be set according to the reference input frequency to guarantee an optimal performance of
the PLL.
The user application can then configure the proper VCO: if the frequency of the reference
clock is lower or equal to 2 MHz, then VCOL must be selected, otherwise VCOH must be
chosen. To reduce the power consumption, it is recommended to configure the VCO output
to the lowest frequency.
DIVNx loop divider has to be programmed to achieve the expected frequency at VCO
output. In addition, the VCO output range must be respected.
The PLLs operate in integer mode when the value of SH_REG (FRACNx shadow register)
is set to ‘0’. The SH_REG is updated with the FRACNx value when PLLxFRACEN bit goes
from ‘0’ to ‘1’. The Sigma-Delta modulator is designed in order to minimize the jitter impact
while allowing very small frequency steps.
The PLLs can be enabled by setting PLLxON to ‘1’. The bits PLLxRDY indicate that the PLL
is ready (i.e. locked).
Note: Before enabling the PLLs, make sure that the reference frequency (refx_ck) provided to the
PLL is stable, so the hardware does not allow changing DIVMx when the PLLx is ON and it
is also not possible to change PLLSRC when one of the PLL is ON.
The hardware prevents writing PLL1ON to ‘0’ if the PLL1 is currently used to deliver the
system clock. There are other hardware protections on the clock generators (refer to
sections HSE oscillator, HSI oscillator and CSI oscillator).
The following PLL parameters cannot be changed once the PLL is enabled: DIVNx,
PLLxRGE, PLLxVCOSEL, DIVPx, DIVQx, DIVRx, DIVPxEN, DIVQxEN and DIVRxEN.
To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
is not used, the application shall set the enable bit (DIVyEN) as well as the corresponding
post-divider bits (DIVP, DIVQ or DIVR) to ‘0’.
If the above rules are not respected, the PLL output frequency is not guaranteed.

Output frequency computation

When the PLL is configured in integer mode (SH_REG = ‘0’), the VCO frequency (FVCO) is
given by the following expression:

F VCO = F REF_CK × DIVN

F PLL_y_CK = ( F VCO ⁄ ( DIVy + 1 ) ) with y = P, Q or R

When the PLL is configured in fractional mode (SH_REG different from ‘0’), the DIVN divider
must be initialized before enabling the PLLs. However, it is possible to change the value of
FRACNx on-the-fly without disturbing the PLL output.

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RM0433 Reset and Clock Control (RCC)

This feature can be used either to generate a specific frequency from any crystal value with
a good accuracy, or to fine-tune the frequency on-the-fly.
For each PLL, the VCO frequency is given by the following formula:

⎛ ⎞
F = F × ⎜ DIVN + FRACN
----------------------⎟
VCO ref_ck ⎝ ( 13 ) ⎠
2

Note: For PLL1, DIVP bitfield can only take odd values.
The PLLs are disabled by hardware when:
• The system enters Stop or Standby mode.
• An HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock.

PLL initialization phase

Figure 48 shows the recommended PLL initialization sequence in integer and fractional
mode. The PLLx are supposed to be disabled at the start of the initialization sequence:
1. Initialize the PLLs registers according to the required frequency.
– Set PLLxFRACEN of RCC PLL configuration register (RCC_PLLCFGR) to ‘0’ for
integer mode.
– For fractional mode, set FRACN to the required initial value (FracInitValue) and
then set PLLxFRACEN to ‘1’.
2. Once the PLLxON bit is set to ‘1’, the user application has to wait until PLLxRDY bit is
set to ‘1’. If the PLLx is in fractional mode, the PLLxFRACEN bit must not be set back
to ‘0’ as long as PLLxRDY = ‘0’.
3. Once the PLLxRDY bit is set to ‘1’, the PLLx is ready to be used.
4. If the application intends to tune the PLLx frequency on-the-fly (possible only in
fractional mode), then:
a) PLLxFRACEN must be set to ‘0’,
When PLLxFRACEN = ‘0’, the Sigma-Delta modulator is still operating with the
value latched into SH_REG.
The application must wait for 3 refx_ck clock periods (PLLxFRACEN bit
propagation delay)
b) A new value must be uploaded into PLLxFRACR (FracValue(n)).
c) PLLxFRACEN must be set to ‘1’, in order to latch the content of PLLxFRACR into
its shadow register.
The new value is considered after 3 clock periods of refx_ck (PLLxFRACEN bit
propagation delay)
Note: When the PLLxRDY goes to ‘1’, it means that the difference between the PLLx output
frequency and the target value is lower than ±2%.

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Figure 48. PLLs Initialization Flowchart

PLL enable sequence PLL enable sequence

integer mode fractional mode

Select clock source (RCC_CKSELR) Select clock source (RCC_CKSELR)

- (PLLSRC) - (PLLSRC)

Init pre-divider (RCC_CKSELR) Init pre-divider (RCC_CKSELR) Can be repeated

- DIVMx - DIVMx for each PLL

PLLx config (RCC_PLLCFGR) Init fractional value (RCC_PLLxFRACR)

- PLLxVCOSEL, PLLxRGE - FRACN= FracInitValue
- PLLxFRACEN = 0 PLLx config (RCC_PLLCFGR)
- DIVPxEN, DIVQxEN, DIVRxEN - PLLxVCOSEL, PLLxRGE
Init PLLx dividers (RCC_PLLxDIVR) - PLLxFRACEN = 1
- DIVNx, DIVPx, DIVQx, DIVRx - DIVPxEN, DIVQxEN, DIVRxEN
Init PLLx dividers (RCC_PLLxDIVR)
- DIVNx, DIVPx, DIVQx, DIVRx
Enable PLLx (RCC_CR)
- PLLxON = 1
Enable PLLx (RCC_CR)
- PLLxON = 1

No
PLLxRDY = 1 ?

No
PLLxRDY = 1 ?
Yes

Yes Ready for use in

Ready for use in integer
mode fractional mode

Disable fractional mode (RCC_PLLCFGR)

- PLLxFRACEN = 0
Init fractional value (RCC_PLLxFRACR) Value update
- FRACN= FracValue(n) on-the-fly
Enable fractional mode (RCC_PLLCFGR)
- PLLxFRACEN = 1
Ready for use in
fractional mode

MSv39367V1

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8.5.6 System clock (sys_ck)

System clock selection
After a system reset, the HSI is selected as system clock and all PLLs are switched OFF.
When a clock source is used for the system clock, it is not possible for the software to
disable the selected source via the xxxON bits.
Of course, the system clock can be stopped by the hardware when the System enters Stop
or Standby mode.
When the system is running, the user application can select the system clock (sys_ck)
among the 4 following sources:
• HSE
• HSI
• CSI
• or pll1_p_ck
This function is controlled by programming the RCC clock configuration register
(RCC_CFGR). A switch from one clock source to another occurs only if the target clock
source is ready (clock stable after startup delay or PLL locked). If a clock source that is not
yet ready is selected, the switch occurs when the clock source is ready.
The SWS status bits in the RCC clock configuration register (RCC_CFGR) indicate which
clock is currently used as system clock. The other status bits in the RCC_CR register
indicate which clock(s) is (are) ready.

System clock generation

Figure 49 shows a simplified view of the clock distribution for the CPU and busses. All the
dividers shown in the block diagram can be changed on-the-fly without generating timing
violations. This feature is a very simply solution to adapt the busses frequencies to the
application needs, thus optimizing the power consumption.
The D1CPRE divider can be used to adjust the CPU clock. However this also impacts the
clock frequency of all bus matrix and HRTIM.
In the same way, HPRE divider can be used to adjust the clock for D1 domain bus matrix,
but this also impacts the clock frequency of bus matrix of D2 and D3 domains.
Most of the prescalers are controlled via RCC_D1CFGR, RCC_D2CFGR and
RCC_D3CFGR registers.

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Figure 49. Core and bus clock generation

RCC
System Clock Generation (SCGU) D1 DOMAIN
rcc_c_ck
CPU Clocks
rcc_fclk_c

480 MHz Max

÷8 CPU Systick clock

rcc_aclk
D1CPRE (1) HPRE (1) AXI peripheral clocks

240 MHz Max

rcc_hclk3
sys_ck ÷ 1,2,4,8,…,512 ÷ 1,2,4,8,…,512 AHB3 peripheral clocks
G1 D1PPRE (1)

÷ 1,2,4,8,16 rcc_pclk3 APB3 peripheral clocks

SCEU (System Clock Enabling)

D2 DOMAIN
rcc_hclk[2:1] AHB1&2 peripheral clocks

D2PPRE1 (1)

rcc_pclk1 APB1 peripheral clocks

÷ 1,2,4,8,16

rcc_timx_ker_ck
Timers prescaler clock

D2PPRE2 (1)

rcc_pclk2 APB2 peripheral clocks

÷ 1,2,4,8,16

rcc_timy_ker_ck
Timers prescaler clock
0
sys_d1cpre_ck HRTIM prescaler clock
1
HRTIMSEL
rcc_hclk4
AHB4 peripheral clocks
rcc_fclk_d3
D3PPRE (1)

rcc_pclk4
÷ 1,2,4,8,16 APB4 peripheral clocks

D3 DOMAIN

(1) Can be changed on-the-fly x Represents the selected mux input after a system reset
MSv41929V3

This block also provides the clock for the timers (rcc_timx_ker_ck and rcc_timy_ker_ck).
The frequency of the timers clock depends on the APB prescaler corresponding to the bus
to which the timer is connected, and on TIMPRE bit. Table 57 shows how to select the timer
clock frequency.

Table 57. Ratio between clock timer and pclk

D2PPRE1 (1) Frcc_timx_ker_ck Frcc_pclk1
TIMPRE
(2) Comments
D2PPRE2 Frcc_timy_ker_ck Frcc_pclk2

0xx 0 → Frcc_hclk1 Frcc_hclk1 The timer clock is equal to the bus clock.
100 0 → Frcc_hclk1 Frcc_hclk1 / 2
101 0 → Frcc_hclk1 / 2 Frcc_hclk1 / 4 The timer clock is twice as fast as the bus
110 0 → Frcc_hclk1 / 4 Frcc_hclk1 / 8 clock.

111 0 → Frcc_hclk1 / 8 Frcc_hclk1 / 16

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RM0433 Reset and Clock Control (RCC)

Table 57. Ratio between clock timer and pclk (continued)

D2PPRE1 (1) TIMPRE Frcc_timx_ker_ck Frcc_pclk1
(2) Comments
D2PPRE2 Frcc_timy_ker_ck Frcc_pclk2

0xx 1 → Frcc_hclk1 Frcc_hclk1 The timer clock is equal to the bus clock.
The timer clock is twice as fast as the bus
100 1 → Frcc_hclk1 Frcc_hclk1 / 2
clock.
101 1 → Frcc_hclk1 Frcc_hclk1 / 4
The timer clock is 4 times faster than the bus
110 1 → Frcc_hclk1 / 2 Frcc_hclk1 / 8
clock.
111 1 → Frcc_hclk1 / 4 Frcc_hclk1 / 16
1. D2PPRE1 and D2PPRE2 belong to RCC domain 2 clock configuration register (RCC_D2CFGR).
2. TIMPRE belongs to RCC clock configuration register (RCC_CFGR).

8.5.7 Handling clock generators in Stop and Standby mode

When the whole system enters Stop mode, all the clocks (system and kernel clocks) are
stopped as well as the following clock sources:
• CSI, HSI (depending on HSIKERON, and CSIKERON bits)
• HSE
• PLL1, PLL2 and PLL3
• HSI48
The content of the RCC registers is not altered except for PLL1ON, PLL2ON, PLL3ON
HSEON and HSI48ON which are set to ‘0’.

Exiting Stop mode

When the microcontroller exits system Stop mode via a wake-up event, the application can
select which oscillator (HSI and/or CSI) will be used to restart. The STOPWUCK bit selects
the oscillator used as system clock. The STOPKERWUCK bit selects the oscillator used as
kernel clock for peripherals. The STOPKERWUCK bit is useful if after a system Stop a
peripheral needs a kernel clock generated by an oscillator different from the one used for
the system clock.
All these bits belong to the RCC clock configuration register (RCC_CFGR). Table 58 gives a
detailed description of their behavior.

Table 58. STOPWUCK and STOPKERWUCK description

Activated Distributed clocks when System
oscillator when the exits Stop mode
STOPWUCK STOPKERWUCK
system exits Stop
mode System Clock Kernel Clock

0 → HSI HSI
0 HSI
1 →
HSI and CSI HSI and/or CSI
0 →
1 CSI
1 → CSI CSI

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During Stop mode

There are two specific cases where the HSI or CSI can be enabled during system Stop
mode:
• When a dedicated peripheral requests the kernel clock:
In this case the peripheral will receive the HSI or CSI according to the kernel clock
source selected for this peripheral (via PERxSRC).
• When the bits HSIKERON or CSIKERON are set:
In this case the HSI and CSI are kept running during Stop mode but the outputs are
gated. In that way, the clock will be available immediately when the system exits Stop
mode or when a peripheral requests the kernel clock (see Table 59 for details).
HSIKERON and CSIKERON bits belong to RCC source control register (RCC_CR).
Table 59 gives a detailed description of their behavior.

Table 59. HSIKERON and CSIKERON behavior

HSIKERON HSI (CSI) state during Stop
HSI (CSI) Setting time
(CSIKERON) mode

0 → OFF tsu(HSI) (tsu(CSI)) (1)

1 → Running and Gated Immediate
1. tsu(HSI) and tsu(CSI) are the startup times of the HSI and CSI oscillators (see refer to the product datasheet
for the values of these parameters).

When the microcontroller exists system Standby mode, the HSI is selected as system and
kernel clock, the RCC registers are reset to their initial values except for the RCC_RSR (or
RCC_C1_RSR) and RCC_BDCR registers.
Note as well that the HSI and CSI outputs provide two clock paths (see Figure 45):
• one path for the system clock (hsi_ck or csi_ck)
• one path for the peripheral kernel clock (hsi_ker_ck or csi_ker_ck).
When a peripheral requests the kernel clock in system Stop mode, only the path providing
the hsi_ker_ck or csi_ker_ck is activated.
Caution: It is not guaranteed that the CPU will get automatically the same clock frequencies when
leaving CStop mode: this mainly depends on the System state. For example If the CPU
goes to CStop, while the D3 domain is kept in CRun, when the CPU exits from CStop, the
clock settings remain unchanged. If the D3 domain goes to CStop while the CPU is also in
CStop, then when the CPU exits from CStop, the CPU will operate with HSI or CSI when it
left the CStop mode.

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8.5.8 Kernel clock selection

Some peripherals are designed to work with two different clock domains that operate
asynchronously:
• a clock domain synchronous with the register and bus interface (ckg_bus_perx clock)
• and a clock domain generally synchronous with the peripheral (kernel clock).
The benefit of having peripherals supporting these two clock domains is that the user
application has more freedom to choose optimized clock frequency for the CPU, bus matrix
and for the kernel part of the peripheral.
As a consequence, the user application can change the bus frequency without
reprogramming the peripherals. As an example an on-going transfer with UART will not be
disturbed if its APB clock is changed on-the-fly.
Table 60 shows the kernel clock that the RCC can deliver to the peripherals. Each row of
Table 60 represents a MUX and the peripherals connected to its output. The columns
starting from number 5 represents the clock sources. Column 3 gives the maximum allowed
frequency at each MUX output. It is up to the user to respect these requirements.

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Reset and Clock Control (RCC)

Table 60. Kernel clock distribution overview
Maximum allowed frequency
Clock Sources
[MHz]

Domain

bus clocks (1)

Clock mux

dsi_phy_ck
USB_PHY1
hsi_ker_ck
csi_ker_ck
pll1_q_ck
pll2_p_ck
pll2_q_ck

pll3_p_ck
pll3_q_ck

I2S_CKIN
per_ck (2)
Peripherals

pll2_r_ck

pll3_r_ck

hsi48_ck

Disabled
hse_ck
sys_ck
control bits

lse_ck
lsi_ck
VOS0 VOS1 VOS2 VOS3

LTDC - 150 150 75 50 x

FMC FMCSEL 300 250 200 133 1 2 0 3

D1
QUADSPI QSPISEL 250 200 150 100 1 2 0 3
(4)
SDMMC1 250(4) 200(4) 150(4) 100
SDMMCSEL 0 1
SDMMC2 250 200 150 100
RM0433 Rev 8

DFSDM1 Aclk SAI1SEL 250 200 150 100 0 1 2 4 3

DFSDM1 clk DFSDM1SEL 250 200 150 100 1 0

FDCAN FDCANSEL 125 100 75 50 1 2 0

HDMI-CEC CECSEL 66 66 66 33 2(3) 0 1

I2C1,2,3 I2C123SEL 125 100 75 50 1 0 2 3

LPTIM1 LPTIM1SEL 125 100 75 50 1 2 0 3 4 5

TIM[8:1][17:12] - 240 200 150 100 D2 x

HRTIM - 480 400 300 200 x

RNG RNGSEL 250 200 150 100 1 0 2 3

SAI1 SAI1SEL 150 150 113 75 0 1 2 4 3

SAI2 150 150 113 75

SAI23SEL 0 1 2 4 3
SAI3 150 150 113 75
SPDIFRX SPDIFSEL 250 200 150 100 0 1 2 3

RM0433
SPI(I2S)1,2,3 SPI123SEL 200 200 150 100 0 1 2 4 3
 Table 60. Kernel clock distribution overview (continued)

RM0433
Maximum allowed frequency
Clock Sources
[MHz]

Domain

bus clocks (1)

Clock mux

dsi_phy_ck
USB_PHY1
hsi_ker_ck
csi_ker_ck
pll1_q_ck
pll2_p_ck
pll2_q_ck

pll3_p_ck
pll3_q_ck

I2S_CKIN
per_ck (2)
Peripherals

pll2_r_ck

pll3_r_ck

hsi48_ck

Disabled
hse_ck
sys_ck
control bits

lse_ck
lsi_ck
VOS0 VOS1 VOS2 VOS3

SPI4,5 SPI45SEL 125 100 75 50 1 2 0 5 3 4

SWPMI SWPSEL 125 100 75 50 0 1

USART1,6 USART16SEL 125 100 75 50 1 2 0 3 4 5

USART2,3 125 100 75 50

USART234578SEL 1 2 0 3 4 5
UART4,5,7,8 D2
USB1OTG 66 66 66 63
USBSEL 1 2 3 0
USB2OTG
RM0433 Rev 8

USB1ULPI - 60 60 60 60 x
(4)
ADC1,2, 3 ADCSEL 100 100(4) 80(4) 80(4) 0 1 2

I2C4 I2C4SEL 125 100 75 50 1 0 2 3

LPTIM2 LPTIM2SEL 125 100 75 50 1 2 0 3 4 5

LPTIM3,4,5 LPTIM345SEL 125 100 75 50 1 2 0 3 4 5

LPUART1 LPUART1SEL 125 100 75 50 D3 1 2 0 3 4 5

SAI4_A SAI4ASEL 0 1 2 4 3

Reset and Clock Control (RCC)

150 150 75 75
SAI4_B SAI4BSEL 150 150 75 75 0 1 2 4 3

SPI6 SPI6SEL 125 100 75 50 1 2 0 5 3 4

RTC/AWU(5) RTCSEL 1 VSW 3(6) 1 2 0

1. The bus clocks are the bus interface clocks to which the peripherals are connected, it can be APB, AHB or AXI clocks.
2. The per_ck clock could be hse_ck, hsi_ker_ck or csi_ker_ck according to CKPERSEL selection.
3. Clock CSI divided by 122.
4. With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even. For SDMMCx, the duty cycle shall be 50% when supporting DDR.
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5. The RTC is not functional in VBAT mode when the clock source is lsi_ck or hse_ck.
6. Clock HSE divided by RTCPRE.
Reset and Clock Control (RCC) RM0433

Figure 50 to Figure 59 provide a more detailed description of kernel clock distribution. To

simplify the drawings, the bus interface clocks (pclk, hclk) are not represented, even if they
are gated with enable signals. Refer to Section 8.5.11: Peripheral clock gating control for
more details.
To reduce the amount of switches, some peripherals share the same kernel clock source.
Nevertheless, all peripherals have their dedicated enable signal.

Peripherals dedicated to audio applications

The audio peripherals generally need specific accurate frequencies, except for SPDIFRX.
As shown in Figure 50, the kernel clock of the SAIs or SPI(I2S)s can be generated by:
• The PLL1 when the amount of active PLLs has to be reduced
• The PLL2 or 3 for optimal flexibility in frequency generation
• HSE, HSI or CSI for use-cases where the current consumption is critical
• I2S_CKIN when an external clock reference need to be used.
Note: The SPDIFRX does not require a specific frequency, but only a kernel clock frequency high
enough to make the peripheral work properly. Refer to the SPDIFRX description for more
details.
DFSDM1 can use the same clock as SAI1A. This is useful when DFSDM1 is used for audio
applications.
To improve the flexibility, SAI4 can use different clock for each sub-block.
The SPI/I2S1, 2, and 3 share the same kernel clock source (see Figure 51).

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Figure 50. Kernel clock distribution for SAIs and DFSDM

SAI4ASEL

pll1_q_ck 0
pll2_p_ck 1
pll3_p_ck 2 D
I2S_CKIN 3
SAI4AMEN
per_ck 4 sai_a_ker_ck
SAI4EN
Logic
SAI4LPEN SAI4
pll1_q_ck 0 sai_b_ker_ck
pll2_p_ck 1
pll3_p_ck 2 D
I2S_CKIN 3
per_ck 4

SAI4BSEL

SAI23SEL

pll1_q_ck 0 SAI[3:2]EN
Logic
RCC pll2_p_ck 1 SAI[3:2]LPEN
pll3_p_ck 2 D sai_A_ker_ck
I2S_CKIN 3
SAI2,3
per_ck 4
sai_b_ker_ck
DFSDM1SEL

rcc_pclk2 0
D clk
sys_ck 1

SAI1SEL DFSDMEN Logic DFSDM

DFSDMLPEN
pll1_q_ck 0
pll2_p_ck 1
pll3_p_ck 2 D Aclk
I2S_CKIN 3
per_ck 4 SAI1EN
Logic sai_A_ker_ck
SAI1LPEN
SAI1

PKSU PKEU sai_b_ker_ck

D The switch is dynamic: the transition between two inputs is glitch-free

MSv41931V3

1. X represents the selected MUX input after a system reset.

2. This figure does not show the connection of the bus interface clock to the peripherals. For details on each enable cell,
please refer to Section 8.5.11: Peripheral clock gating control.

Peripherals dedicated to control and data transfer

Peripherals such as SPIs, I2Cs, UARTs do not need a specific kernel clock frequency but a
clock fast enough to generate the correct baud rate, or the required bit clock on the serial
interface. For that purpose the source can be selected among:
• PLL1 when the amount of active PLLs has to be reduced
• PLL2 or PLL3 if better flexibility is required. As an example, this solution allows
changing the frequency bus via PLL1 without affecting the speed of some serial
interfaces.
• HSI or CSI for low-power use-cases or when the peripheral has to quickly wake up
from Stop mode (i.e. UART, I2C...).

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Note: UARTs also need the LSE clock when high baud rates are not required.

Figure 51. Kernel clock distribution for SPIs and SPI/I2S

SPDIFSEL

SPDIFRXEN Logic SPDIF-RX

pll1_q_ck 0
SPDIFRXLPEN
pll2_r_ck 1 spdifrx_ker_ck
pll3_r_ck 2 D
hsi_ker_ck 3

I2S123SEL

pll1_q_ck 0 SPI[3:1]EN Logic SPI/I2S[3:1]

pll2_p_ck 1 SPI[3:1]LPEN
pll3_p_ck spi_ker_ck
2 D
I2S_CKIN 3
per_ck 4

SPI45SEL

RCC
rcc_pclk2 0 SPI[5:4]EN
Logic SPI[5:4]
pll2_q_ck 1 SPI[5:4]LPEN
pll3_q_ck 2 D spi_ker_ck
hsi_ker_ck 3
csi_ker_ck 4
hse_ck 5

SPI6SEL

SPI6AMEN
rcc_pclk4 0 SPI6EN
Logic SPI6
pll2_q_ck 1 SPI6LPEN
pll3_q_ck 2 D spi_ker_ck
hsi_ker_ck 3
csi_ker_ck 4
hse_ck 5

PKSU PKEU

D The switch is dynamic: the transition between two inputs is glitch-free

MSv41932V2

1. X represents the selected MUX input after a system reset.

2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please
refer to Section 8.5.11: Peripheral clock gating control.

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Figure 52. Kernel clock distribution for I2Cs

I2C4SEL I2C4
I2C4AMEN
I2C4EN
Logic
rcc_pclk4 0 I2C4LPEN i2c_ker_ck_req
pll3_r_ck 1 D i2c_ker_ck
hsi_ker_ck 2
csi_ker_ck 3
RCC
I2C123SEL I2C[3:1]

I2C[3:1]EN Logic
rcc_pclk1 0 i2c_ker_ck_req
I2C[3:1]LPEN
pll3_r_ck 1 D i2c_ker_ck
hsi_ker_ck 2
csi_ker_ck 3

PKSU PKEU

D The switch is dynamic: the transition between two inputs is glitch-free

MSv41933V2

1. X represents the selected MUX input after a system reset

2. This figure does not show the connection of the bus interface clock to the peripheral, for details on each enable cell, please
refer to Section 8.5.11: Peripheral clock gating control.

Figure 53. Kernel clock distribution for UARTs, USARTs and LPUART1

USART16SEL

USART1
rcc_pclk2 0 USART1EN
Logic
pll2_q_ck 1 usart_ker_ck_req
USART1LPEN
pll3_q_ck 2 usart_ker_ck
D
hsi_ker_ck 3
csi_ker_ck 4 USART6
USART6EN
lse_ck 5 Logic
USART6LPEN usart_ker_ck_req
USART234578SEL usart_ker_ck

USART[3:2]
rcc_pclk1 0
USART[3:2]EN Logic
pll2_q_ck 1
USART[3:2]LPEN usart_ker_ck_req
pll3_q_ck 2 usart_ker_ck
D
hsi_ker_ck 3
csi_ker_ck 4 UART[5:4]
lse_ck 5 UART[5:4]EN
Logic
UART[5:4]LPEN uart_ker_ck_req
uart_ker_ck

RCC PKSU UART[8:7]

UART[8:7]EN
Logic
UART[8:7]LPEN uart_ker_ck_req
uart_ker_ck
LPUART1SEL

LPUART1AMEN LPUART1
rcc_pclk4 0 LPUART1EN
Logic
pll2_q_ck 1 LPUART1PLEN lpuart_ker_ck_req
pll3_q_ck 2 D lpuart_ker_ck
hsi_ker_ck 3
csi_ker_ck 4
lse_ck 5 PKEU

D The switch is dynamic: the transition between two inputs is glitch-free

MSv41934V2

1. X represents the selected MUX input after a system reset.

2. This figure does not show the connection of the bus interface clock to the peripheral, for details on each enable cell, please
refer to Section 8.5.11: Peripheral clock gating control.

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Figure 54. Kernel clock distribution for LTDC

RCC
PKSU PKEU
LTDCEN Logic
LTDCLPEN LTDC
ltdc_ker_ck
pll3_r_ck

MSv41935V2

1. X represents the selected MUX input after a system reset.

2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please
refer to Section 8.5.11: Peripheral clock gating control.
The FMC, QUADSPI and SDMMC1/2 can also use a clock different from the bus interface
clock for more flexibility.

Figure 55. Kernel clock distribution for SDMMC, QUADSPI and FMC

SDMMCSEL SDMMC1,2
SDMMC[2:1]EN
Logic
SDMMC[2:1]LPEN
pll1_q_ck 0 sdmmc_ker_ck
D
pll2_r_ck 1

RCC QSPISEL
QSPIEN QUADSPI
Logic
rcc_hclk3 0 QSPILPEN
pll1_q_ck 1D quadspi_ker_ck
pll2_r_ck 2
per_ck 3

FMCSEL
FMCEN FMC
Logic
rcc_hclk3 0 FMCLPEN
pll1_q_ck 1D fmc_ker_ck
pll2_r_ck 2
per_ck 3

PKSU PKEU

D The switch is dynamic: the transition between two inputs is glitch-free

MSv41936V2

1. X represents the selected MUX input after a system reset.

2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please
refer to Section 8.5.11: Peripheral clock gating control.

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Figure 56 shows the clock distribution for the USB blocks. The USB1ULPI block receives its
clock from the external PHY.
The USBxOTG blocks receive the clock for USB communications which can be selected
among different sources thanks to the MUX controlled by USBSEL.

Figure 56. Kernel clock distribution for USB (2)

USBSEL

USB1OTGEN
0 0 Logic
USB1OTGLPEN
pll1_q_ck 1
USB1OTG
pll3_q_ck 2 D
(OTB_HS1)
hsi48_ck 3

USB2OTGEN Logic
USB2OTGLPEN
RCC PKSU
USB2OTG
(OTB_HS2)

PKEU
USB1ULPI
USB1ULPIEN Logic (OTG_HS1)
USB1ULPILPEN
USB_PHY1 ck_ulpi
(OTG_HS_ULPI_CK)

D The switch is dynamic: the transition between two inputs is glitch-free

MSv41937V4

1. X represents the selected MUX input after a system reset.

2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please
refer to Section 8.5.11: Peripheral clock gating control.

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The Ethernet transmit and receive clocks shall be provided from an external Ethernet PHY.
The clock selection for the RX and TX path is controlled via the SYSCFG block.

Figure 57. Kernel clock distribution for Ethernet

RCC PKEU
ETH1
PKSU ETH1TXEN
Logic
ETH1TXLPEN
ETH_MII_TX_CLK 0
D eth_mii_tx_clk
1
FES
EPIS[2]
ETH1RXEN Logic
ETH_MII_RX_CLK/ ETH1RXLPEN
÷ 2, 20 1 eth_mii_rx_clk
ETH_RMII_REF_CLK D
0

ETH1TXEN or ETH1RXEN Logic

ETH1TXLPEN or ETH1RXLPEN
eth_rmii_ref_clk

ETH1MACEN Logic
ETH1MACLPEN
hclk_i
rcc_hclk1

D The switch is dynamic: the transition between two inputs is glitch-free

MSv41938V2

1. X represents the selected MUX input after a system reset.

2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please
refer to Section 8.5.11: Peripheral clock gating control.

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Figure 58. Kernel clock distribution for ADCs, SWPMI, RNG and FDCAN (2)
ADC3AMEN
ADCSEL
ADC3EN Logic ADC3
pll2_p_ck 0 ADC3LPEN
adc_ker_ck_input
pll3_r_ck 1 D adc_sclk (2)
per_ck 2
ADC12EN Logic
HPRE (1) ADC12
ADC12LPEN
sys_ck adc_ker_ck_input
RCC 0 adc_sclk (2)
sys_ck/2 1

SWPSEL
SWPEN Logic SWPMI
rcc_pclk1 SWPLPEN
0 swpmi_ker_ck
D
hsi_ker_ck 1

RNGSEL
RNGEN Logic RNG
hsi48_ck 0 RNGLPEN
pll1_q_ck rng_ker_ck
1 D
lse_ck 2
lsi_ck 3

FDCANSEL
FDCANEN Logic FDCAN
hse_ck 0 FDCANLPEN
pll1_q_ck fdcan_ker_ck
1 D
pll2_q_ck 2
PKEU
PKSU

D The switch is dynamic: the transition between two inputs is glitch-free

(1)
adc_sclk is equal to sys_ck when HPRE is set to 0, otherwise it corresponds to sys_ck/2
(2)
adc_sclk only available on revision V devices. MSv41939V4

1. X represents the selected MUX input after a system reset.

2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please
refer to Section 8.5.11: Peripheral clock gating control.

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Figure 59. Kernel clock distribution for LPTIMs and HDMI-CEC (2)

RCC CECSEL
CECEN HDMI-CEC
Logic
lse_ck 0 CECLPEN
lsi_ck 1 D cec_ker_ck (im)
2

csi_ker_ck ÷ 122

LPTIM1SEL

rcc_pclk1 0 LPTIM1EN LPTIM1

Logic
pll2_p_ck 1 LPTIM1LPEN
pll3_r_ck 2 CLKMUX
D
lse_ck 3
lsi_ck 4
per_ck 5

LPTIM2SEL

LPTIM2AMEN
rcc_pclk4 0 LPTIM2EN LPTIM2
Logic
pll2_p_ck 1 LPTIM2LPEN
pll3_r_ck 2 CLKMUX
D
lse_ck 3
lsi_ck 4
per_ck 5

LPTIM345SEL
LPTIM[5:3]AMEN
rcc_pclk4 0 LPTIM[5:3]EN LPTIM[5:3]
Logic
pll2_p_ck 1 LPTIM[5:3]LPEN
pll3_r_ck 2 CLKMUX
D
lse_ck 3
lsi_ck 4
per_ck 5

PKSU PKEU

D The switch is dynamic: the transition between two inputs is glitch-free

MSv41940V2

1. X represents the selected MUX input after a system reset

2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please
refer to Section 8.5.11: Peripheral clock gating control.

RTC/AWU clock
The rtc_ck clock source can be:
• the hse_1M_ck (hse_ck divided by a programmable prescaler)
• the lse_ck
• or the lsi_ck clock
The source clock is selected by programming the RTCSEL[1:0] bits in the RCC backup
domain control register (RCC_BDCR) and the RTCPRE[5:0] bits in the RCC clock
configuration register (RCC_CFGR).
This selection cannot be modified without resetting the Backup domain.
If the LSE is selected as RTC clock, the RTC will work normally even if the backup or the
VDD supply disappears.

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The LSE clock is in the Backup domain, whereas the other oscillators are not. As a
consequence:
• If LSE is selected as RTC clock, the RTC continues working even if the VDD supply is
switched OFF, provided the VBAT supply is maintained.
• If LSI is selected as the RTC clock, the AWU state is not guaranteed if the VDD supply
is powered off.
• If the HSE clock is used as RTC clock, the RTC state is not guaranteed if the VDD
supply is powered off or if the VCORE supply is powered off.
The rtc_ck clock is enabled through RTCEN bit located in the RCC backup domain control
register (RCC_BDCR).
The RTC bus interface clock (APB clock) is enabled through RTCAPBEN and
RTCAPBLPEN bits located in RCC_APB4ENR/LPENR registers.
Note: To read the RTC calendar register when the APB clock frequency is less than seven times
the RTC clock frequency (FAPB < 7 x FRTCLCK), the software must read the calendar time
and date registers twice. The data are correct if the second read access to RTC_TR gives
the same result than the first one. Otherwise a third read access must be performed.

Watchdog clocks
The RCC provides the clock for the four watchdog blocks available on the circuit. The
independent watchdog (IWDG1) is connected to the LSI. The window watchdog (WWDG1)
are connected to the APB clock.
If an independent watchdog is started by either hardware option or software access, the LSI
is forced ON and cannot be disabled. After the LSI oscillator setup delay, the clock is
provided to the IWDGs.
Caution: Before enabling the WWDG1, the application must set the WW1RSC bit to ‘1’. If the
WW1RSC remains to ‘0’, when the WWDG1 is enabled, its the behavior is not guaranteed.
The WW1RSC bit is located in RCC global control register (RCC_GCR).

Clock frequency measurement using TIMx

Most of the clock source generator frequencies can be measured by means of the input
capture of TIMx.
• Calibrating the HSI or CSI with the LSE
The primary purpose of having the LSE connected to a TIMx input capture is to be able
to accurately measure the HSI or CSI. This requires to use the HSI or CSI as system
clock source either directly or via PLL1. The number of system clock counts between
consecutive edges of the LSE signal gives a measurement of the internal clock period.
Taking advantage of the high precision of LSE crystals (typically a few tens of ppm) we
can determine the internal clock frequency with the same resolution, and trim the
source to compensate for manufacturing-process and/or temperature- and voltage-
related frequency deviations.
The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio):
the precision is therefore tightly linked to the ratio between the two clock sources. The
greater the ratio is, the more accurate the measurement is.
The HSI and CSI oscillators have dedicated user-accessible calibration bits for this
purpose (see RCC internal clock source calibration register (RCC_ICSCR)) for revision
Y devices and RCC HSI configuration register (RCC_HSICFGR)/RCC CSI
configuration register (RCC_CSICFGR) for revision V devices). When the HSI or CSI

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are used via the PLLx, the system clock can also be fine-tuned by using the fractional
divider of the PLLs.
• Calibrating the LSI with the HSI
The LSI frequency can also be measured: this is useful for applications that do not
have a crystal. The ultralow power LSI oscillator has a large manufacturing process
deviation. By measuring it versus the HSI clock source, it is possible to determine its
frequency with the precision of the HSI. The measured value can be used to have more
accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or
an IWDG timeout with an acceptable accuracy.

8.5.9 General clock concept overview

The RCC handles the distribution of the CPU, bus interface and peripheral clocks for the
system (D1, D2 and D3 domains), according to the operating mode of each function (refer to
Section 8.5.1: Clock naming convention for details on clock definitions).
For each peripheral, the application can control the activation/deactivation of its kernel and
bus interface clock. Prior to use a peripheral, the CPU has to enable it (by setting PERxEN
to ‘1’), and define if this peripheral remains active in CSleep mode (by setting PERxLPEN to
‘1’). This is called ‘allocation’ of a peripheral to the CPU (refer to Section 8.5.10: Peripheral
allocation for more details).
The peripheral allocation is used by the RCC to automatically control the clock gating
according to the CPU and domain modes, and by the PWR to control the supply voltages of
D1, D2 and D3 domains.
Figure 60 gives an example of peripheral allocation:
• The CPU enabled SDMMC1, SPI5 and SRAM1, AXISRAM, ITCM, DTCM1, DTCM2
and SRAM4 are implicitly allocated to the CPU. The group composed of the CPU, bus
matrix 1/2/3 and allocated peripherals makes up a sub-system (CPU_SS).
Note: The FLASH, AXISRAM, ITCM, DTCM1, DTCM2, SRAM4, IWGD1, IWGD2, PWR, EXTI and
RCC are common resources and are implicitly allocated to the CPU.

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Figure 60. Peripheral allocation example

D2
D1 CPU

FLITF
FLASH SDMMC1 CPU_SS SPI5

AXISRAM PER... SAI1

Bus Matrix 1

Bus Matrix 2
ITCM SRAM1
PER... I2C2

DTCM1
SRAM2
...

...
DTCM2
PER... PER... SRAM3

D3
Bus Matrix 3
DMAMUX
SRAM4
IWDG1

BDMA

PER...
PWR

EXTI
RCC

SAI4
I2C4
...

Peripherals implicitly allocated to the CPU

MSv41941V1

When the CPU enters CStop mode, the RCC automatically disables the bus interface and
kernel clocks of all the peripherals of the CPU_SS as well as the CPU clock. The PLLs, if
enabled, are not disabled by the RCC since D3 is still running.
The D3 domain can be kept in DRun mode while the CPU is in CStop mode and D1 and D2
domains are in DStop or DStandby mode. This is done by setting RUN_D3 bit in
PWR_CPUCR registers.
• If RUN_D3 is set to ‘1’, then D3 is maintained in DRun mode, independently from the
CPU modes (see PWR CPU control register (PWR_CPUCR).
• If RUN_D3 is set to ‘0’, then D3 domain enters DStop or DStandby mode when the
CPU enters CStop mode (see Table 61).
Note that the CPU can control if D1, D2 or D3 domains are allowed to enter in DStandby
when conditions are met, via bits PDDS_D1, PDDS_D2 and PDDS_D3 of PWR CPU control
register (PWR_CPUCR).
A wakeup event will be able to exit D1, D2 and D3 domains from DStandby or DStop mode.
In addition, more autonomy can be given to some peripherals located into D3 domain (refer
to Section : D3 domain Autonomous mode for details).

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D3 domain Autonomous mode

The Autonomous mode allows to deliver the peripheral clocks to peripherals located in D3,
even if the CPU is in CStop mode. When a peripheral has its autonomous bit enabled, it
receives its peripheral clocks according to D3 domain state, if the CPU is in CStop mode:
• If the D3 domain is in DRun mode, peripherals with Autonomous mode activated
receive their peripheral clocks,
• If the D3 domain is in DStop mode, no peripheral clock is provided.
The Autonomous mode does not prevent the D3 domain to enter DStop or DStandby mode.
The autonomous bits are located in RCC D3 Autonomous mode register (RCC_D3AMR).
For example, the CPU can enter CStop mode, while the SAI4 is filling the SRAM4 with data
received from an external device via BDMA. When the amount of received data is reached,
the CPU can be activated by a wakeup event. This can be done by setting the SAI4, the
BDMA, and SRAM4 in Autonomous mode, while keeping D3 in DRun mode (RUN_D3 set to
‘1’). In this example, the RCC does not switch off the PLLs as the D3 domain is always in
DRun mode.
It is possible to go a step further with power consumption reduction by combining the
Autonomous mode with the capability of some peripherals (UARTs, I2Cs) to request the
kernel clock on their own, without waking-up the CPU. For example, if the system is
expecting messages via I2C4, the whole system can be put in Stop mode. When the I2C4
peripheral detects a START bit, it will generate a “kernel clock request”. This request
enables the HSI or CSI, and a kernel clock is provided only to the requester (in our example
the I2C4). The I2C4 then decodes the incoming message. Several cases are then possible:
• If the device address of the message does not match, then I2C4 releases its “kernel
clock request” until a new START condition is detected.
• If the device address of the incoming message matches, it has to be stored into D3
local memory. I2C4 is able to generate a wakeup event on address match to switch the
D3 domain to DRun mode. The message is then transferred into memory via BDMA,
and the D3 domain go back to DStop mode without any CPU activation. Note that if the
amount of data transferred into memory reached the transfer count, the BDMA can also
generate an interrupt to wake-up the CPU.
• If the device address of the incoming message matches and the peripheral is setup to
wake up the CPU, then I2C4 generates a wakeup event to activate the CPU.
Please refer to the description of EXTI block in order see which peripheral is able to perform
a wake-up event to which domain.

Memory handling
The CPU can access all the memory areas available in the product:
• AXISRAM, ITCM, DTCM1, DTCM2 and FLASH,
• SRAM1, SRAM2 and SRAM3,
• SRAM4 and BKPRAM.
As shown in Figure 60, FLASH, AXISRAM, SRAM4, ITCM, DTCM1 and DTCM2 are
implicitly allocated to the CPU. As a result, there is no enable bit allowing the CPU to
allocate these memories.
If the CPU wants to use memories located into D2 domain (SRAM1, SRAM2 and SRAM3), it
has to enable them.

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The BKPRAM has a dedicated enable in order to gate the bus interface clock. The CPU
needs to enable the BKPRAM prior to use it.
Note: The memory interface clocks (Flash and RAM interfaces) can be stopped by software during
CSleep mode (via DxSRAMyLPEN bits).
Refer to Peripheral clock gating control and CPU and bus matrix clock gating control
sections for details on clock enabling.

System states overview

Table 61 gives an overview of the system states with respect to the D1, D2 and D3 domain
modes.
• The system remains in Run mode as long as D3 is in DRun mode. Several sub-states
of system Run exist that are not detailed here (refer Power control (PWR) for more
information).
• When the D1 domain is in DRun, the D2 domain can be in DRun, DStop or DStandby.
When the D1 domain is in DStop or DStandby, the D2 domain can no longer remain in
DRun it will switch to DStop or DStandby according to PDDS_D2 bit.
• D3 can run while D1 and D2 are in DStop/DStandby mode thanks to RUN_D3 bits of
PWR_CPUCR registers or when D3 is in Autonomous mode.
• The system remains in Stop mode as long as D3 is in DStop mode. This means
implicitly that D1 and D2 are in DStop or DStandby. As soon as D1 or D2 exits DStop or
DStandby, D3 switches to DRun mode.
• The system remains in Standby mode as long as D1, D2 and D3 are in DStandby.
• Domain states versus CPU states:
– When the D1 domain is in DRun mode, it means that its bus matrix is clocked, and
the CPU is in CRun mode.
– When the D2 domain is in DRun mode, it means that its bus matrix is clocked, and
the CPU is in CRun mode with at least a peripheral of D2 domain allocated.
– When the D1 domain is in DStop mode it means that its bus matrix is no longer
clocked, and the CPU is in CStop mode.
– When the D2 domain is in DStop mode it means that its bus matrix is no longer
clocked. This situation happens when:
- the CPU did not allocate peripherals of D2 domain,
- the CPU allocated peripherals of D2 domain, but the CPU is in CStop or
CStandby,
– When a domain is in DStandby mode, it means that the domain including its CPU
are powered down.

Table 61. System states overview

System State D1 State D2 State D3 State

DRun DRun/DStop/DStandby
Run DRun
DStop/DStandby DStop/DStandby
Stop DStop/DStandby DStop/ DStandby DStop
Standby DStandby DStandby DStandby

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8.5.10 Peripheral allocation

The CPU can allocate a peripheral and hence control its kernel and bus interface clock.
The CPU can allocate a peripheral by setting the dedicated PERxEN bit located into:
• RCC_xxxxENR registers or
• RCC_C1_xxxxENR registers.
The CPU can control the peripheral clocks gating when it is in CSleep mode via the
PERxLPEN bits located into:
• RCC_xxxxLPENR registers or
• RCC_C1_xxxxLPENR registers.
Refer to Section 8.7.1: Register mapping overview for additional information.
The peripheral allocation bits (PERxEN bits) are used by the hardware to provide the kernel
and bus interface clocks to the peripherals. However they are also used to link peripherals
to the CPU (CPU sub-system). In this way, the hardware is able to safely gate the peripheral
clocks and bus matrix clocks according to CPU states. The PWR block also uses this
information to control properly the domain states.

Clock switches and gating

• Clock switching delays
The input selected by the kernel clock switches can be changed dynamically without
generating spurs or timing violation. As a consequence, switching from the original to
the new input can only be performed if a clock is present on both inputs. If it not the
case, no clock will be provided to the peripheral. To recover from this situation, the user
has to provide a valid clock to both inputs.
During the transition from one input to another, the kernel clock provided to the
peripheral will be gated, in the worst case, during 2 clock cycles of the previously
selected clock and 2 clock cycles of the new selected clock. As shown in Figure 61,
both input clocks shall be present during transition time.

Figure 61. Kernel Clock switching

Transition
time

PERxSRC ...
1 2
in0_ck ...
PERxSRC
1 2
in1_ck ... in0_ck 0
D
rcc_perx_ker_ck in1_ck 1
Kernel clock ...
provided to
rcc_perx_ker_ck
PERx In this area ck_in0 clock can be
disabled

MSv39390V1

• Clock switching state after system reset

After system reset, PLLs, HSE, CSI and HSI48 are switched OFF. If one of these
clocks is used as input clock through the MUX, the switching does not take place.

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Indeed, switching from the original to the new input can only be performed if a clock is
present on both inputs. Otherwise, no clock is provided to the peripheral. To recover
from this situation, the user has to provide a valid clock to both inputs.
For example if pll2_q_ck is selected as kernel clock to the USART1, after system reset,
the user has to enable pll2_q_ck to switch back to rcc_pclk2 as kernel clock to
USART1.
• Clock enabling delays
In the same way, the clock gating logic synchronizes the enable command (coming
generally from a kernel clock request or PERxEN bits) with the selected clock, in order
to avoid generation of spurs.
– A maximum delay of two periods of the enabled clock may occur between the
enable command and the first rising edge of the clock. The enable command can
be the rising edge of the PERxEN bits of RCC_xxxxENR registers, or a kernel
clock request asserted by a peripheral.
– A maximum delay of 1.5 periods of the disabled clock may occur between the
disable command and the last falling edge of the clock. The disable command can
be the falling edge of the PERxEN bits of RCC_xxxxENR registers, or a kernel
clock request released by a peripheral.
Note: Both the kernel clock and the bus interface clock are affected by this re-synchronization
delay.
In addition, the clock enabling delay may strongly increase if the application is enabling
for the first time a peripheral which is not located into the same domain. This is due to
the fact that the domain where the peripheral is located could be in DStop or DStandby
mode. The domain must be switched to DRun mode before the application can use this
peripheral.
As an example, if the CPU enables a peripheral located in the D2 domain while the D2
domain is in DStop/DStandby mode, then the power controller (PWR) has first to
provide a supply voltage to D2, then the RCC has to wait for an acknowledge from the
PWR before enabling the clocks of the D2 domain. To handle properly this situation the
RCC and the PWR blocks feature four flags:
– D1CKRDY/D2CKRDY located in RCC source control register (RCC_CR)
– SBF_D1 and SBF_D2 located in PWR CPU control register (PWR_CPUCR).
The following sequence can be followed to avoid this issue:
a) Enable the peripheral clocks (i.e. allocate the peripheral) by writing the
corresponding PERxEN bit to ‘1’ in the RCC_xxxxENR register,
b) Read back the RCC_xxxxENR register to make sure that the previous write
operation is not pending into a write buffer.
c) If the peripheral is located in a different domain, perform the two next steps:
Read DxCKRDY until it is set to ‘1’.
Write SBF_Dx to zero and read-back the value, in order to check if the domain
where the peripheral is located is still in DStandby. If the corresponding bit is read
at ‘1’, it means that the domain is still in DStandby. Repeat this operation until
SBF_Dx is equal to ‘0’, then continue the other steps.
d) Perform a dummy read operation into a register of the enabled peripheral. This
operation will take at least 2 clock cycles, which is equal to the max delay of the
enable command.
e) The peripheral can then be used.

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Note: When the bus interface clock is not active, read or write accesses to the peripheral registers
are not supported. A read access will return invalid data. A write access will be ignored and
will not create any bus errors.

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8.5.11 Peripheral clock gating control

As mentioned previously, each peripheral requires a bus interface clock, named
rcc_perx_bus_ck (for peripheral ‘x’). This clock can be an APB, AHB or AXI clock,
according to which bus the peripheral is connected.
The clocks used as bus interface for peripherals located in D1 domain, could be rcc_aclk,
rcc_hclk3 or rcc_pclk3, depending on the bus connected to each peripheral. For simplicity
sake, these clocks are named rcc_bus_d1_ck.
In the same way, the signal named rcc_bus_d2_ck represents rcc_hclk1, rcc_hclk2,
rcc_pclk1 or rcc_pclk2, depending on the bus connected to each peripheral of D2 domain.
Similarly, the signal rcc_bus_d3_ck represents rcc_hclk4 or rcc_pclk4 for peripherals
located in D3.
Some peripherals (SAI, UART...) also require a dedicated clock for their communication
interface. This clock is generally asynchronous with respect to the bus interface clock. It is
named kernel clock (perx_ker_ckreq). Both clocks can be gated according to several
conditions detailed hereafter.
As shown in Figure 62, enabling the kernel and bus interface clocks of each peripheral
depends on several input signals:
• PERxEN and PERxLPEN bits
PERxEN represents the peripheral enable (allocation) bit for the CPU. The CPU can
write these bits to ‘1’ via RCC_C1_xxxxENR or RCC_xxxxENR registers.
• PERxAMEN bits
The PERxAMEN bits are belong to RCC D3 Autonomous mode register
(RCC_D3AMR).
• CPU state (c_sleep and c_deepsleep signals)
• D3 domain state (d3_deepsleep signal)
• The kernel clock request (perx_ker_ckreq) of the peripheral itself, when the feature is
available.
Refer to Section 8.5.10: Peripheral allocation for more details.

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Figure 62. Peripheral kernel clock enable logic details

SCGU rcc_bus_d1_ck SCEU

(System rcc_bus_d2_ck (System Clock Enabling Unit)
rcc_bus_d3_ck
clock generation) rcc_perx_bus_ck

sync
PERxEN

rcc_perx_bus_en
PERxLPEN
busif rcc_perx_bus_d1_en
CPU_state
Control
PERxAMEN Logic
RCC D3_state rcc_perx_bus_d3_en

PERx
PERxSRC PKEU
(Peripheral Kernel Clock Enabling)
rcc_perx_ker_ck
….

PERxEN
PERxLPEN sync
rcc_perx_ker_cpu_en
CPU_state Kernel

rcc_perx_ker_en
PKSU Control
(Peripheral kernel PERxAMEN Logic
D3_state
clock Selection) rcc_perx_ker_d3_en

perx_ker_ckreq

When the peripheral offers the feature

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Table 62 gives a detailed description of the enabling logic of the peripheral clocks for
peripherals located in D1 or D2 domain and allocated by the CPU.

Table 62. Peripheral clock enabling for D1 and D2 peripherals

rcc_perx_bus_d1_en
rcc_perx_ker_c_en
perx_ker_ckreq
PERxLPEN

PERxSRC
PERxEN

CPU State Comments

0 X X X X 0 0 No clock provided to the peripheral, because PERxEN=‘0’

Kernel and bus interface clocks are provided to the peripheral,
1 X X X CRun 1 1
because the CPU is in CRun, and PERxEN=‘1’
No clock provided to the peripheral, because the CPU is in
1 0 X X 0 0
CSleep, and PERxLPEN=‘0’
CSleep
Kernel and bus interface clocks are provided to the peripheral,
1 1 X X 1 1
because CPU is in CSleep, and PERxLPEN=‘1’
No clock provided to the peripheral because the PERxLPEN
1 0 X X 0 0
bit is set to ‘0’.
no lsi_ck
and
no lse_ck No clock provided to the peripheral because CPU is in CStop
1 1 and no X 0 0 and lse_ck or lsi_ck or hsi_ker_ck or csi_ker_ck are not
hsi_ker_ck selected.
and no
csi_ker_ck
CStop
Kernel clock is provided to the peripheral because PERxEN =
lsi_ck or 1
1 1 X (1) 0 PERxLPEN=‘1’ and lsi_ck or lse_ck are selected.
lse_ck
The bus interface clock is no provided as the CPU is in CStop
Kernel clock is provided to the peripheral because
hsi_ker_ck or req_ker_perx = ‘1’, and PERxEN = PERxLPEN=‘1’ and
1 1 1 1 0
csi_ker_ck hsi_ker_ck or csi_ker_ck are selected.
The bus interface clock is no provided as the CPU is in CStop
hsi_ker_ck or No clock provided to the peripheral because CPU is in CStop,
1 1 0 0 0
csi_ker_ck and no kernel clock request pending
1. For RNG block, the kernel clock is not delivered if the CPU to which it is allocated is in CStop mode, even if the clock
selected is lsi_ck or lse_ck.

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As a summary, we can state that the kernel clock is provided to the peripherals located on
domains D1 and D2 when the following conditions are met:
1. The CPU is in CRun mode, and the peripheral is allocated.
2. The CPU is in CSleep mode, and the peripheral is allocated with PERxLPEN = ‘1’.
3. The CPU is in CStop mode, and the peripheral is allocated with PERxLPEN = ‘1’, and
the peripheral generates a kernel clock request, and the selected clock is hsi_ker_ck
or csi_ker_ck.
4. The CPU is in CStop mode, and the peripheral is allocated with PERxLPEN = ‘1’, and
the kernel source clock of the peripheral is lse_ck or lsi_ck.
The bus interface clock will be provided to the peripherals only when conditions 1 or 2 are
met.
Table 63 gives a detailed description of the enabling logic of the kernel clock for all
peripherals located in D3.

Table 63. Peripheral clock enabling for D3 peripherals

rcc_perx_bus_d3_en
rcc_perx_ker_d3_en
perx_ker_ckreq
PERxAMEN
PERxLPEN

CPU State
PERxSRC
PERxEN

D3 State

Comments

No clock provided to the peripheral, as

0 X X X X Any Any 0 0
PERxEN=‘0’
Kernel and bus interface clocks are provided to
1 X X X X CRun 1 1 the peripheral, because the CPU is in CRun,
and PERxEN=‘1’
No clock provided to the peripheral, because
1 0 X X X 0 0
the CPU is in CSleep, and PERxLPEN=‘0’
CSleep Kernel and bus interface clocks are provided to
1 1 X X X 1 1 the peripheral, because the CPU is in CSleep,
and PERxLPEN=‘1’
DRun
As the CPU is in CStop, and PERxEN=‘1’, then
the kernel clock gating depends on D3 state
1 X 0 X X 0 0 and PERxAMEN bits.
No clock provided to the peripheral because
PERxAMEN = ‘0’.
The kernel and bus interface clocks are
CStop
provided because even if the CPU is in CStop
1 X 1 X X 1 1
mode, D3 is in DRun mode, with PERxEN and
PERxAMEN bits set to ‘1’.
not lse_ck No clock provided to the peripheral, because
1 X 1 and 0 DStop 0 0 D3 is in DStop, req_ker_perx = ‘0’, and lse_ck
not lsi_ck or lsi_ck are not selected.

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Table 63. Peripheral clock enabling for D3 peripherals (continued)

rcc_perx_bus_d3_en
rcc_perx_ker_d3_en
perx_ker_ckreq
PERxAMEN
PERxLPEN

CPU State
PERxSRC
PERxEN

D3 State
Comments

not
hsi_ker_ck
and not
csi_ker_ck No clock provided to the peripheral, because
1 X 1 1 0 0 even if req_ker_perx = ‘0’, lse_ck or lsi_ck or
and
hsi_ker_ck or csi_ker_ck are not selected.
not lse_ck
and
not lsi_ck
Kernel clock is provided to the peripheral
CStop DStop because req_ker_perx = ‘1’, and PERxEN =
hsi_ker_ck
PERxAMEN=‘1’, and the selected clock is
1 X 1 or 1 1 0 hsi_ker_ck or csi_ker_ck.
csi_ker_ck The bus interface clock is not provided as D3 is
in DStop.
Kernel clock is provided to the peripheral
because PERxEN = PERxAMEN=‘1’ and
lse_ck
lse_ck or lsi_ck are selected, while D3 is in
1 X 1 or X 1 0 STOP.
lsi_ck The bus interface clock is not provided as D3 is
in DSTOP.

As a summary, we can state that the kernel clock is provided to the peripherals of D3 if the
following conditions are met:
1. The CPU is in CRun mode, and the peripheral is allocated.
2. The CPU is in CSleep mode, and the peripheral is allocated with PERxLPEN = ‘1’.
3. The CPU is in CStop mode, and the peripheral is allocated and D3 domain is in DRun
mode with PERxAMEN = ‘1’.
4. The CPU is in CStop mode, and the peripheral is allocated, and D3 domain is in DStop
mode with PERxAMEN = ‘1’, and the peripheral is generating a kernel clock request
and the kernel clock source is hsi_ker_ck or csi_ker_ck.
5. The CPU is in CStop mode, and the peripheral is allocated, and D3 domain is in DStop
mode with PERxAMEN = ‘1’, and the kernel clock source of the peripheral is lse_ck or
lsi_ck.
The bus interface clock will be provided to the peripherals only when condition 1, 2 or 3 is
met.

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Note: When they are set to ‘1’, the autonomous bits indicate that the associated peripheral will
receive a kernel clock according to D3 state, and not according to the mode of the CPU.
Only I2C, U(S)ART and LPUART peripherals are able to request the kernel clock. This
feature gives to the peripheral the capability to transfer data with an optimal power
consumption.
The autonomous bits dedicated to some peripherals located in D3 domain allow the data
transfer with external devices without activating the CPU.
In order for the LPTIMER to operate with lse_ck or lsi_ck when the circuit is in Stop mode,
the user application has to select the lsi_ck or lse_ck input via LPTIMxSEL fields, and set
bit LPTIMxAMEN and LPTIMxLPEN to ‘1’.

8.5.12 CPU and bus matrix clock gating control

For each domain it is possible to control the activation/deactivation of the CPU clock and
bus matrix clock.
For information about convention naming, refer to Section 8.5.11: Peripheral clock gating
control.
The clocks of the CPU, AHB and AXI bridges and APB busses are enabled according to the
rules hereafter:
• The CPU clock rcc_c_ck is enabled when the CPU is in CRun mode.
• The AXI bridge clock is enabled when the CPU is in CRun mode.
• The D2 domain AHB bridges clocks are enabled when:
– The CPU is in CRun or,
– If the CPU is in CSleep with at least a peripheral (master) connected to this bus
having both its PERxEN and PERxLPEN set to ‘1’ or,
– If the CPU is in CSleep with at least an APB bus having its clock enabled.
• The D3 domain AHB bridge clock is enabled when:
– The CPU is in CRun or CSleep mode or,
– When the RUN_D3 bit is set to ‘1’, independently of CPU modes or,
– When the d3_deepsleep signal is inactive (‘0’), independently of CPU modes.
• The APB1,2,3 busses are enabled when:
– The CPU is in CRun or,
– If the CPU is in CSleep with at least a peripheral connected to this bus having both
its PERxEN and PERxLPEN set to ‘1’.
• The APB4 bus is enabled when: the D3 domain is in DRun.
As shown in the Figure 63, the enabling of the core and bus clock of each domain depends
on several input signals:
• c_sleep and c_deepsleep signals from the CPU,
• d3_sleepdeep signal,
• RCC_xxxxENR.PERxEN bits of peripherals located on D2 domain

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Figure 63. Bus clock enable logic

RCC SCEU
rcc_c_ck
run_c

SCGU
(System rcc_bus_d1_ck
clock generation)
sys_ck
rcc_bus_d2_ck

rcc_bus_d3_ck

c_deepsleep
Logic
d3_deepsleep
function
RUN_D3 of PWR_CPUCR

Logic
CPU Mode (c_sleep, c_deepsleep) function
D1

Logic
function
c_per_alloc_d2 D2

run_c is a combination of NOT c_deepsleep and NOT c_sleep

rcc_bus_dx represents the clocks for the bus matrix and the peripheral bus interface for domain x

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8.6 RCC Interrupts

The RCC provides 3 interrupt lines:
• rcc_it: a general interrupt line, providing events when the PLLs are ready, or when the
oscillators are ready.
• rcc_hsecss_it: an interrupt line dedicated to the failure detection of the HSE Clock
Security System.
• rcc_lsecss_it: an interrupt line dedicated to the failure detection of the LSE Clock
Security System.
The interrupt enable is controlled via RCC clock source interrupt enable register
(RCC_CIER), except for the HSE CSS failure. When the HSE CSS feature is enabled, it not
possible to mask the interrupt generation.
The interrupt flags can be checked via RCC clock source Interrupt flag register
(RCC_CIFR), and those flags can be cleared via RCC clock source interrupt clear register
(RCC_CICR).
Note: The interrupt flags are not relevant if the corresponding interrupt enable bit is not set.
Table 64 gives a summary of the interrupt sources, and the way to control them.

Table 64. Interrupt sources and control

Interrupt Interrupt Action to clear
Description Interrupt Line
Source enable interrupt

LSIRDYF LSI ready LSIRDYIE Set LSIRDYC to ‘1’

LSERDYF LSE ready LSERDYIE Set LSERDYC to ‘1’
HSIDRYF HSI ready HSIDRYIE Set HSIRDYC to ‘1’
HSERDYF HSE ready HSERDYIE Set HSERDYC to ‘1’
CSIRDYF CSI ready CSIRDYIE Set CSIRDYC to ‘1’
rcc_it
Set HSI48RDYC to
HSI48RDYF HSI48 ready HSI48RDYIE
‘1’
PLL1RDYF PLL1 ready PLL1RDYIE Set PLL1RDYC to ‘1’
PLL2RDYF PLL2 ready PLL2RDYIE Set PLL2RDYC to ‘1’
PLL3RDYF PLL3 ready PLL3RDYIE Set PLL3RDYC to ‘1’
(1)
LSECSSF LSE Clock security system failure LSECSSFIE Set LSECSSC to ‘1’ rcc_lsecss_it
(2)
HSECSSF HSE Clock security system failure - Set HSECSSC to ‘1’ rcc_hsecss_it
1. The security system feature must also be enabled (LSECSSON = ‘1’), in order to generate interrupts.
2. It is not possible to mask this interrupt when the security system feature is enabled (HSECSSON = ‘1’).

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8.7 RCC register description

8.7.1 Register mapping overview

Note that the control of PERxEN and PERxLPEN bits can be performed at two different
address offset:0x0D0 and 0x130. So the application can use the registers named:
• RCC_xxxxENR or RCC_C1_xxxxENR to control the PERxEN bits
• RCC_xxxxLPENR or RCC_C1_xxxxLPENR to control the PERxLPEN bits
• RCC_RSR or RCC_C1_RSR to control the reset flag status bits.
This feature is provided to insure the compatibility with other products of this family.

Figure 64 shows the RCC mapping overview.

Figure 64. RCC mapping overview

Physical register Logical register

mapping 0x1FF
mapping

RCC_C1_APB4LPENR
bank 2

…
RCC_C1_RSR
0x130

RCC_APB4LPENR RCC_APB4LPENR
bank1
…

RCC_RSR 0x0D0 RCC_RSR

RCC_APB4RSTR RCC_APB4RSTR
bank0
…

RCC_CR 0x000 RCC_CR

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8.7.2 RCC source control register (RCC_CR)

Address offset: 0x000
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

HSECSSON
PLL3RDY

PLL2RDY

PLL1RDY

HSERDY
HSEBYP
PLL3ON

PLL2ON

PLL1ON

HSEON
Res. Res. Res. Res. Res. Res.

r rw r rw r rw rs rw r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HSIDIV[1:0]
CSIKERON

HSIKERON
HSI48RDY
D2CKRDY

D1CKRDY

HSI48ON

HSIDIVF
CSIRDY

HSIRDY
CSION

HSION
Res. Res. Res.

r r r rw rw r rw r rw rw r rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 PLL3RDY: PLL3 clock ready flag
Set by hardware to indicate that the PLL3 is locked.
0: PLL3 unlocked (default after reset)
1: PLL3 locked
Bit 28 PLL3ON: PLL3 enable
Set and cleared by software to enable PLL3.
Cleared by hardware when entering Stop or Standby mode.
0: PLL3 OFF (default after reset)
1: PLL3 ON
Bit 27 PLL2RDY: PLL2 clock ready flag
Set by hardware to indicate that the PLL2 is locked.
0: PLL2 unlocked (default after reset)
1: PLL2 locked
Bit 26 PLL2ON: PLL2 enable
Set and cleared by software to enable PLL2.
Cleared by hardware when entering Stop or Standby mode.
0: PLL2 OFF (default after reset)
1: PLL2 ON
Bit 25 PLL1RDY: PLL1 clock ready flag
Set by hardware to indicate that the PLL1 is locked.
0: PLL1 unlocked (default after reset)
1: PLL1 locked
Bit 24 PLL1ON: PLL1 enable
Set and cleared by software to enable PLL1.
Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing
this bit to ‘0’, if the PLL1 output is used as the system clock.
0: PLL1 OFF (default after reset)
1: PLL1 ON
Bits 23:20 Reserved, must be kept at reset value.

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Bit 19 HSECSSON: HSE Clock Security System enable

Set by software to enable Clock Security System on HSE.
This bit is “set only” (disabled by a system reset or when the system enters in Standby mode).
When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and
disabled by hardware if an oscillator failure is detected.
0: Clock Security System on HSE OFF (Clock detector OFF) (default after reset)
1: Clock Security System on HSE ON (Clock detector ON if the HSE oscillator is
stable, OFF if not).
Bit 18 HSEBYP: HSE clock bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit, to be used by the device.
The HSEBYP bit can be written only if the HSE oscillator is disabled.
0: HSE oscillator not bypassed (default after reset)
1: HSE oscillator bypassed with an external clock
Bit 17 HSERDY: HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable.
0: HSE clock is not ready (default after reset)
1: HSE clock is ready
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE when entering Stop or Standby mode.
This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock or if the HSE is
selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to ‘1’).
0: HSE is OFF (default after reset)
1: HSE is ON
Bit 15 D2CKRDY: D2 domain clocks ready flag
Set by hardware to indicate that the D2 domain clocks are available.
0: D2 domain clocks are not available (default after reset)
1: D2 domain clocks are available
Bit 14 D1CKRDY: D1 domain clocks ready flag
Set by hardware to indicate that the D1 domain clocks (CPU, bus and peripheral) are available.
0: D1 domain clocks are not available (default after reset)
1: D1 domain clocks are available
Bit 13 HSI48RDY: HSI48 clock ready flag
Set by hardware to indicate that the HSI48 oscillator is stable.
0: HSI48 clock is not ready (default after reset)
1: HSI48 clock is ready
Bit 12 HSI48ON: HSI48 clock enable
Set by software and cleared by software or by the hardware when the system enters to Stop or
Standby mode.
0: HSI48 is OFF (default after reset)
1: HSI48 is ON
Bits 11:10 Reserved, must be kept at reset value.

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Bit 9 CSIKERON: CSI clock enable in Stop mode

Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly
available as kernel clock for some peripherals. This bit has no effect on the value of CSION.
0: no effect on CSI (default after reset)
1: CSI is forced to ON even in Stop mode
Bit 8 CSIRDY: CSI clock ready flag
Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is
enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or
by a peripheral request).
0: CSI clock is not ready (default after reset)
1: CSI clock is ready
Bit 7 CSION: CSI clock enable
Set and reset by software to enable/disable CSI clock for system and/or peripheral.
Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = ‘1’ or
STOPKERWUCK = ‘1’.
This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock or if the CSI is
selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to ‘1’).
0: CSI is OFF (default after reset)
1: CSI is ON
Bit 6 Reserved, must be kept at reset value.
Bit 5 HSIDIVF: HSI divider flag
Set and reset by hardware.
As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the
current status of the HSI divider. HSIDIVF will go immediately to ‘0’ when HSIDIV value is changed,
and will be set back to ‘1’ when the output frequency matches the value programmed into HSIDIV.
0: new division ratio not yet propagated to hsi(_ker)_ck (default after reset)
1: hsi(_ker)_ck clock frequency reflects the new HSIDIV value
Bits 4:3 HSIDIV[1:0]: HSI clock divider
Set and reset by software.
These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The
HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL
(PLLxON bit set to ‘1’). In that case, the new HSIDIV value is ignored.
00: Division by 1, hsi(_ker)_ck = 64 MHz (default after reset)
01: Division by 2, hsi(_ker)_ck = 32 MHz
10: Division by 4, hsi(_ker)_ck = 16 MHz
11: Division by 8, hsi(_ker)_ck = 8 MHz

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RM0433 Reset and Clock Control (RCC)

Bit 2 HSIRDY: HSI clock ready flag

Set by hardware to indicate that the HSI oscillator is stable.
0: HSI clock is not ready (default after reset)
1: HSI clock is ready
Bit 1 HSIKERON: High Speed Internal clock enable in Stop mode
Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly
available as kernel clock for peripherals. This bit has no effect on the value of HSION.
0: no effect on HSI (default after reset)
1: HSI is forced to ON even in Stop mode
Bit 0 HSION: High Speed Internal clock enable
Set and cleared by software.
Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = ‘0’ or
STOPKERWUCK = ‘0’.
Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a
failure of the HSE which is used as the system clock source.
This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock or if the HSI is
selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to ‘1’).
0: HSI is OFF
1: HSI is ON (default after reset)

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8.7.3 RCC internal clock source calibration register (RCC_ICSCR)

Address offset: 0x004
Reset value: 0x4000 0xxx
This register is available only on revision Y devices.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. CSITRIM[4:0] CSICAL[7:0] HSITRIM[5:4]
rw rw rw rw rw r r r r r r r r rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSITRIM[3:0] HSICAL[11:0]
rw rw rw rw r r r r r r r r r r r r

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 CSITRIM[4:0]: CSI clock trimming
Set by software to adjust calibration.
CSITRIM field is added to the engineering option bytes loaded during reset phase (flash_csi_opt) in
order to form the calibration trimming value.
CSICAL = CSITRIM + flash_csi_opt.
Note: The reset value of the field is 0x10.
Bits 25:18 CSICAL[7:0]: CSI clock calibration
Set by hardware by option byte loading during system reset nreset.
Adjusted by software through trimming bits CSITRIM.
This field represents the sum of engineering option byte calibration value and CSITRIM bits value.
Bits 17:12 HSITRIM[5:0]: HSI clock trimming
Set by software to adjust calibration.
HSITRIM field is added to the engineering option bytes loaded during reset phase (flash_hsi_opt) in
order to form the calibration trimming value.
HSICAL = HSITRIM + flash_hsi_opt.
Note: The reset value of the field is 0x20.
Bits 11:0 HSICAL[11:0]: HSI clock calibration
Set by hardware by option byte loading during system reset nreset.
Adjusted by software through trimming bits HSITRIM.
This field represents the sum of engineering option byte calibration value and HSITRIM bits value.

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RM0433 Reset and Clock Control (RCC)

8.7.4 RCC HSI configuration register (RCC_HSICFGR)

Address offset: 0x004
Reset value: 0x4000 0xxx
This register is available only on revision V devices.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. HSITRIM[6:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. HSICAL[11:0]
r r r r r r r r r r r r

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 HSITRIM[6:0]: HSI clock trimming
Set by software to adjust calibration.
HSITRIM field is added to the engineering Option Bytes loaded during reset phase
(FLASH_HSI_opt) in order to form the calibration trimming value.
HSICAL = HSITRIM + FLASH_HSI_opt.
Note: The reset value of the field is 0x40.
Bits 23:12 Reserved, must be kept at reset value.
Bits 11:0 HSICAL[11:0]: HSI clock calibration
Set by hardware by option byte loading during system reset nreset.
Adjusted by software through trimming bits HSITRIM.
This field represents the sum of engineering Option Byte calibration value and HSITRIM bits value.

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8.7.5 RCC clock recovery RC register (RCC_CRRCR)

Address offset: 0x008
Reset value: 0x0000 0xxx

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. HSI48CAL[9:0]
r

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 HSI48CAL[9:0]: Internal RC 48 MHz clock calibration
Set by hardware by option byte loading during system reset nreset.
Read-only.

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RM0433 Reset and Clock Control (RCC)

8.7.6 RCC CSI configuration register (RCC_CSICFGR)

Address offset: 0x00C
Reset value: 0x2000 00xx
This register is available only on revision V devices.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. CSITRIM[5:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CSICAL[9:0]
r r r r r r r r r r

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:24 CSITRIM[5:0]: CSI clock trimming
Set by software to adjust calibration.
CSITRIM bitfield is added to the engineering option bytes loaded during the reset phase
(FLASH_CSI_opt) in order to build the calibration trimming value.
CSICAL = CSITRIM + FLASH_CSI_opt.
Note: The reset value of this bitfield is 0x10.
Bits 23:8 Reserved, must be kept at reset value.
Bits 9:0 CSICAL[9:0]: CSI clock calibration
Set by hardware by option byte loading during system reset nreset.
Adjusted by software through trimming bits CSITRIM.
This bitfield represents the sum of the engineering option byte calibration value and CSITRIM value.

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8.7.7 RCC clock configuration register (RCC_CFGR)

Address offset: 0x010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCO2[2:0] MCO2PRE[3:0] MCO1[2:0] MCO11PRE[3:0] Res. Res.
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

STOPKERWUCK

STOPWUCK
HRTIMSEL
TIMPRE

RTCPRE[5:0] SWS[2:0] SW[2:0]

rw rw rw rw rw r rw

Bits 31:29 MCO2[2:0]: Micro-controller clock output 2

Set and cleared by software. Clock source selection may generate glitches on MCO2.
It is highly recommended to configure these bits only after reset, before enabling the external
oscillators and the PLLs.
000: System clock selected (sys_ck) (default after reset)
001: PLL2 oscillator clock selected (pll2_p_ck)
010: HSE clock selected (hse_ck)
011: PLL1 clock selected (pll1_p_ck)
100: CSI clock selected (csi_ck)
101:LSI clock selected (lsi_ck)
others: reserved
Bits 28:25 MCO2PRE[3:0]: MCO2 prescaler
Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler
may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset,
before enabling the external oscillators and the PLLs.
0000: prescaler disabled (default after reset)
0001: division by 1 (bypass)
0010: division by 2
0011: division by 3
0100: division by 4
...
1111: division by 15
Bits 24:22 MCO1[2:0]: Micro-controller clock output 1
Set and cleared by software. Clock source selection may generate glitches on MCO1.
It is highly recommended to configure these bits only after reset, before enabling the external
oscillators and the PLLs.
000: HSI clock selected (hsi_ck) (default after reset)
001: LSE oscillator clock selected (lse_ck)
010: HSE clock selected (hse_ck)
011: PLL1 clock selected (pll1_q_ck)
100: HSI48 clock selected (hsi48_ck)
others: reserved

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RM0433 Reset and Clock Control (RCC)

Bits 21:18 MCO1PRE[3:0]: MCO1 prescaler

Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler
may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset,
before enabling the external oscillators and the PLLs.
0000: prescaler disabled (default after reset)
0001: division by 1 (bypass)
0010: division by 2
0011: division by 3
0100: division by 4
...
1111: division by 15
Bits 17:16 Reserved, must be kept at reset value.
Bit 15 TIMPRE: Timers clocks prescaler selection
This bit is set and reset by software to control the clock frequency of all the timers connected to
APB1 and APB2 domains.

0: The Timers kernel clock is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,

else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
1: The Timers kernel clock is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or
4, else it is equal to 4 x Frcc_pclkx_d2
Please refer to Table 57: Ratio between clock timer and pclk
Bit 14 HRTIMSEL: High Resolution Timer clock prescaler selection
This bit is set and reset by software to control the clock frequency of high resolution the timer
(HRTIM).
0: The HRTIM prescaler clock source is the same as other timers. (default after reset)
1: The HRTIM prescaler clock source is the CPU clock (rcc_c_ck).
Bits 13:8 RTCPRE[5:0]: HSE division factor for RTC clock
Set and cleared by software to divide the HSE to generate a clock for RTC.
Caution: The software has to set these bits correctly to ensure that the clock supplied to the RTC is
lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.
000000: no clock (default after reset)
000001: no clock
000010: HSE/2
000011: HSE/3
000100: HSE/4
...
111110: HSE/62
111111: HSE/63
Bit 7 STOPKERWUCK: Kernel clock selection after a wake up from system Stop
Set and reset by software to select the Kernel wakeup clock from system Stop.
0: The HSI is selected as wake up clock from system Stop (default after reset)
1: The CSI is selected as wake up clock from system Stop
See Section 8.5.7: Handling clock generators in Stop and Standby mode for details.

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Bit 6 STOPWUCK: System clock selection after a wake up from system Stop
Set and reset by software to select the system wakeup clock from system Stop.
The selected clock is also used as emergency clock for the Clock Security System on HSE.
0: The HSI is selected as wake up clock from system Stop (default after reset)
1: The CSI is selected as wake up clock from system Stop
See Section 8.5.7: Handling clock generators in Stop and Standby mode for details.
Caution: STOPWUCK must not be modified when the Clock Security System is enabled (by
HSECSSON bit) and the system clock is HSE (SWS=”10”) or a switch on HSE is requested
(SW=”10”).
Bits 5:3 SWS[2:0]: System clock switch status
Set and reset by hardware to indicate which clock source is used as system clock.
000: HSI used as system clock (hsi_ck) (default after reset)
001: CSI used as system clock (csi_ck)
010: HSE used as system clock (hse_ck)
011: PLL1 used as system clock (pll1_p_ck)
others: Reserved
Bits 2:0 SW[2:0]: System clock switch
Set and reset by software to select system clock source (sys_ck).
Set by hardware in order to:
– force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a
system Stop mode
– force the selection of the HSI in case of failure of the HSE when used directly or indirectly
as system clock.
000: HSI selected as system clock (hsi_ck) (default after reset)
001: CSI selected as system clock (csi_ck)
010: HSE selected as system clock (hse_ck)
011: PLL1 selected as system clock (pll1_p_ck)
others: Reserved

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RM0433 Reset and Clock Control (RCC)

8.7.8 RCC domain 1 clock configuration register (RCC_D1CFGR)

Address offset: 0x018
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. D1CPRE[3:0] Res. D1PPRE[2:0] HPRE[3:0]
rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:8 D1CPRE[3:0]: D1 domain Core prescaler
Set and reset by software to control D1 domain CPU clock division factor.
Changing this division ratio has an impact on the frequency of the CPU clock, and all bus matrix
clocks.
The clocks are divided by the new prescaler factor. This factor ranges from 1 to 16 periods of the
slowest APB clock among rcc_pclk[4:1] after D1CPRE update. The application can check if the
new division factor is taken into account by reading back this register.
0xxx: sys_ck not divided (default after reset)
1000: sys_ck divided by 2
1001: sys_ck divided by 4
1010: sys_ck divided by 8
1011: sys_ck divided by 16
1100: sys_ck divided by 64
1101: sys_ck divided by 128
1110: sys_ck divided by 256
1111: sys_ck divided by 512

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Bit 7 Reserved, must be kept at reset value.

Bits 6:4 D1PPRE[2:0]: D1 domain APB3 prescaler
Set and reset by software to control the division factor of rcc_pclk3.
The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk3 after D1PPRE
write.
0xx: rcc_pclk3 = rcc_hclk3 (default after reset)
100: rcc_pclk3 = rcc_hclk3 / 2
101: rcc_pclk3 = rcc_hclk3 / 4
110: rcc_pclk3 = rcc_hclk3 / 8
111: rcc_pclk3 = rcc_hclk3 / 16
Bits 3:0 HPRE[3:0]: D1 domain AHB prescaler
Set and reset by software to control the division factor of rcc_hclk3 and rcc_aclk. Changing this
division ratio has an impact on the frequency of all bus matrix clocks.
0xxx: rcc_hclk3 = sys_d1cpre_ck (default after reset)
1000: rcc_hclk3 = sys_d1cpre_ck / 2
1001: rcc_hclk3 = sys_d1cpre_ck / 4
1010: rcc_hclk3 = sys_d1cpre_ck / 8
1011: rcc_hclk3 = sys_d1cpre_ck / 16
1100: rcc_hclk3 = sys_d1cpre_ck / 64
1101: rcc_hclk3 = sys_d1cpre_ck / 128
1110: rcc_hclk3 = sys_d1cpre_ck / 256
1111: rcc_hclk3 = sys_d1cpre_ck / 512
Note: The clocks are divided by the new prescaler factor from1 to 16 periods of the slowest APB
clock among rcc_pclk[4:1] after HPRE update.
Note: Note also that rcc_hclk3 = rcc_aclk.

Caution: Care must be taken when using the voltage scaling. Due to the propagation delay of the
new division factor, after a prescaler factor change and before lowering the VCORE voltage, this
register must be read in order to check that the new prescaler value has been taken into
account.
Depending on the clock source frequency and the voltage range, the software application
has to program a correct value in HPRE to make sure that the system frequency does not
exceed the maximum frequency.

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RM0433 Reset and Clock Control (RCC)

8.7.9 RCC domain 2 clock configuration register (RCC_D2CFGR)

Address offset: 0x01C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. D2PPRE2[2:0] Res. D2PPRE1[2:0] Res. Res. Res. Res.
rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:8 D2PPRE2[2:0]: D2 domain APB2 prescaler
Set and reset by software to control D2 domain APB2 clock division factor.
The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after D2PPRE2
write.
0xx: rcc_pclk2 = rcc_hclk1 (default after reset)
100: rcc_pclk2 = rcc_hclk1 / 2
101: rcc_pclk2 = rcc_hclk1 / 4
110: rcc_pclk2 = rcc_hclk1 / 8
111: rcc_pclk2 = rcc_hclk1 / 16
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 D2PPRE1[2:0]: D2 domain APB1 prescaler
Set and reset by software to control D2 domain APB1 clock division factor.
The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after D2PPRE1
write.
0xx: rcc_pclk1 = rcc_hclk1 (default after reset)
100: rcc_pclk1 = rcc_hclk1 / 2
101: rcc_pclk1 = rcc_hclk1 / 4
110: rcc_pclk1 = rcc_hclk1 / 8
111: rcc_pclk1 = rcc_hclk1 / 16
Bits 3:0 Reserved, must be kept at reset value.

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8.7.10 RCC domain 3 clock configuration register (RCC_D3CFGR)

Address offset: 0x020
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. D3PPRE[2:0] Res.
rw

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:4 D3PPRE[2:0]: D3 domain APB4 prescaler
Set and reset by software to control D3 domain APB4 clock division factor.
The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk4 after D3PPRE
write.
0xx: rcc_pclk4 = rcc_hclk4 (default after reset)
100: rcc_pclk4 = rcc_hclk4 / 2
101: rcc_pclk4 = rcc_hclk4 / 4
110: rcc_pclk4 = rcc_hclk4 / 8
111: rcc_pclk4 = rcc_hclk4 / 16
Bits 3:0 Reserved, must be kept at reset value.

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RM0433 Reset and Clock Control (RCC)

8.7.11 RCC PLL clock source selection register (RCC_PLLCKSELR)

Address offset: 0x028
Reset value: 0x0202 0200

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. DIVM3[5:0] Res. Res. DIVM2[5:4]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVM2[3:0] Res. Res. DIVM1[5:0] Res. Res. PLLSRC[1:0]
rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:20 DIVM3[5:0]: Prescaler for PLL3
Set and cleared by software to configure the prescaler of the PLL3.
The hardware does not allow any modification of this prescaler when PLL3 is enabled (PLL3ON =
‘1’).
In order to save power when PLL3 is not used, the value of DIVM3 must be set to ‘0’.
000000: prescaler disabled (default after reset)
000001: division by 1 (bypass)
000010: division by 2
000011: division by 3
...
100000: division by 32 (default after reset)
...
111111: division by 63
Bits 19:18 Reserved, must be kept at reset value.
Bits 17:12 DIVM2[5:0]: Prescaler for PLL2
Set and cleared by software to configure the prescaler of the PLL2.
The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ON =
‘1’).
In order to save power when PLL2 is not used, the value of DIVM2 must be set to ‘0’.
000000: prescaler disabled
000001: division by 1 (bypass)
000010: division by 2
000011: division by 3
...
100000: division by 32 (default after reset)
...
111111: division by 63
Bits 11:10 Reserved, must be kept at reset value.

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Bits 9:4 DIVM1[5:0]: Prescaler for PLL1

Set and cleared by software to configure the prescaler of the PLL1.
The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON =
‘1’).
In order to save power when PLL1 is not used, the value of DIVM1 must be set to ‘0’.
000000: prescaler disabled
000001: division by 1 (bypass)
000010: division by 2
000011: division by 3
...
100000: division by 32 (default after reset)
...
111111: division by 63
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSRC[1:0]: DIVMx and PLLs clock source selection
Set and reset by software to select the PLL clock source.
These bits can be written only when all PLLs are disabled.
In order to save power, when no PLL is used, the value of PLLSRC must be set to ‘11’.
00: HSI selected as PLL clock (hsi_ck) (default after reset)
01: CSI selected as PLL clock (csi_ck)
10: HSE selected as PLL clock (hse_ck)
11: No clock send to DIVMx divider and PLLs

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RM0433 Reset and Clock Control (RCC)

8.7.12 RCC PLL configuration register (RCC_PLLCFGR)

Address offset: 0x02C
Reset value: 0x01FF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DIVQ3EN

DIVQ2EN

DIVQ1EN
DIVR3EN

DIVR2EN

DIVR1EN
DIVP3EN

DIVP2EN

DIVP1EN
Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL3FRACEN

PLL2FRACEN

PLL1FRACEN
PLL3VCOSEL

PLL2VCOSEL

PLL1VCOSEL
Res. Res. Res. Res. PLL3RGE[[1:0] PLL2RGE[[1:0] PLL1RGE[[1:0]

rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 DIVR3EN: PLL3 DIVR divider output enable
Set and reset by software to enable the pll3_r_ck output of the PLL3.
To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used.
This bit can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’).
0: pll3_r_ck output is disabled
1: pll3_r_ck output is enabled (default after reset)
Bit 23 DIVQ3EN: PLL3 DIVQ divider output enable
Set and reset by software to enable the pll3_q_ck output of the PLL3.
To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used.
This bit can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’).
0: pll3_q_ck output is disabled
1: pll3_q_ck output is enabled (default after reset)
Bit 22 DIVP3EN: PLL3 DIVP divider output enable
Set and reset by software to enable the pll3_p_ck output of the PLL3.
This bit can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’).
To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used.
0: pll3_p_ck output is disabled
1: pll3_p_ck output is enabled (default after reset)
Bit 21 DIVR2EN: PLL2 DIVR divider output enable
Set and reset by software to enable the pll2_r_ck output of the PLL2.
To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used.
This bit can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’).
0: pll2_r_ck output is disabled
1: pll2_r_ck output is enabled (default after reset)
Bit 20 DIVQ2EN: PLL2 DIVQ divider output enable
Set and reset by software to enable the pll2_q_ck output of the PLL2.
To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used.
This bit can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’).
0: pll2_q_ck output is disabled
1: pll2_q_ck output is enabled (default after reset)

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Bit 19 DIVP2EN: PLL2 DIVP divider output enable

Set and reset by software to enable the pll2_p_ck output of the PLL2.
This bit can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’).
To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used.
0: pll2_p_ck output is disabled
1: pll2_p_ck output is enabled (default after reset)
Bit 18 DIVR1EN: PLL1 DIVR divider output enable
Set and reset by software to enable the pll1_r_ck output of the PLL1.
To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used.
This bit can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’).
0: pll1_r_ck output is disabled
1: pll1_r_ck output is enabled (default after reset)
Bit 17 DIVQ1EN: PLL1 DIVQ divider output enable
Set and reset by software to enable the pll1_q_ck output of the PLL1.
In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be
disabled.
This bit can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’).
0: pll1_q_ck output is disabled
1: pll1_q_ck output is enabled (default after reset)
Bit 16 DIVP1EN: PLL1 DIVP divider output enable
Set and reset by software to enable the pll1_p_ck output of the PLL1.
This bit can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’).
In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be
disabled.
0: pll1_p_ck output is disabled
1: pll1_p_ck output is enabled (default after reset)
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:10 PLL3RGE[1:0]: PLL3 input frequency range
Set and reset by software to select the proper reference frequency range used for PLL3.
These bits must be written before enabling the PLL3.
00: The PLL3 input (ref3_ck) clock range frequency is between 1 and 2 MHz (default after reset)
01: The PLL3 input (ref3_ck) clock range frequency is between 2 and 4 MHz
10: The PLL3 input (ref3_ck) clock range frequency is between 4 and 8 MHz
11: The PLL3 input (ref3_ck) clock range frequency is between 8 and 16 MHz
Bit 9 PLL3VCOSEL: PLL3 VCO selection
Set and reset by software to select the proper VCO frequency range used for PLL3.
This bit must be written before enabling the PLL3.
0: Wide VCO range:192 to 960 MHz (default after reset)
1: Medium VCO range:150 to 420 MHz
Bit 8 PLL3FRACEN: PLL3 fractional latch enable
Set and reset by software to latch the content of FRACN3 into the Sigma-Delta modulator.
In order to latch the FRACN3 value into the Sigma-Delta modulator, PLL3FRACEN must be set to
‘0’, then set to ‘1’: the transition 0 to 1 transfers the content of FRACN3 into the modulator. Please
refer to Section : PLL initialization phase for additional information.

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RM0433 Reset and Clock Control (RCC)

Bits 7:6 PLL2RGE[1:0]: PLL2 input frequency range

Set and reset by software to select the proper reference frequency range used for PLL2.
These bits must be written before enabling the PLL2.
00: The PLL2 input (ref2_ck) clock range frequency is between 1 and 2 MHz (default after reset)
01: The PLL2 input (ref2_ck) clock range frequency is between 2 and 4 MHz
10: The PLL2 input (ref2_ck) clock range frequency is between 4 and 8 MHz
11: The PLL2 input (ref2_ck) clock range frequency is between 8 and 16 MHz
Bit 5 PLL2VCOSEL: PLL2 VCO selection
Set and reset by software to select the proper VCO frequency range used for PLL2.
This bit must be written before enabling the PLL2.
0: Wide VCO range:192 to 960 MHz (default after reset)
1: Medium VCO range:150 to 420 MHz
Bit 4 PLL2FRACEN: PLL2 fractional latch enable
Set and reset by software to latch the content of FRACN2 into the Sigma-Delta modulator.
In order to latch the FRACN2 value into the Sigma-Delta modulator, PLL2FRACEN must be set to
‘0’, then set to ‘1’: the transition 0 to 1 transfers the content of FRACN2 into the modulator. Please
refer to Section : PLL initialization phase for additional information.
Bits 3:2 PLL1RGE[1:0]: PLL1 input frequency range
Set and reset by software to select the proper reference frequency range used for PLL1.
This bit must be written before enabling the PLL1.
00: The PLL1 input (ref1_ck) clock range frequency is between 1 and 2 MHz (default after reset)
01: The PLL1 input (ref1_ck) clock range frequency is between 2 and 4 MHz
10: The PLL1 input (ref1_ck) clock range frequency is between 4 and 8 MHz
11: The PLL1 input (ref1_ck) clock range frequency is between 8 and 16 MHz
Bit 1 PLL1VCOSEL: PLL1 VCO selection
Set and reset by software to select the proper VCO frequency range used for PLL1.
These bits must be written before enabling the PLL1.
0: Wide VCO range: 192 to 960 MHz (default after reset)
1: Medium VCO range: 150 to 420 MHz
Bit 0 PLL1FRACEN: PLL1 fractional latch enable
Set and reset by software to latch the content of FRACN1 into the Sigma-Delta modulator.
In order to latch the FRACN1 value into the Sigma-Delta modulator, PLL1FRACEN must be set to
‘0’, then set to ‘1’: the transition 0 to 1 transfers the content of FRACN1 into the modulator. Please
refer to Section : PLL initialization phase for additional information.

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8.7.13 RCC PLL1 dividers configuration register (RCC_PLL1DIVR)

Address offset: 0x030
Reset value: 0x0101 0280

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. DIVR1[6:0] Res. DIVQ1[6:0]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVP1[6:0] DIVN1[8:0]
rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 DIVR1[6:0]: PLL1 DIVR division factor
Set and reset by software to control the frequency of the pll1_r_ck clock.
These bits can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’).
0000000: pll1_r_ck = vco1_ck
0000001: pll1_r_ck = vco1_ck / 2 (default after reset)
0000010: pll1_r_ck = vco1_ck / 3
0000011: pll1_r_ck = vco1_ck / 4
...
1111111: pll1_r_ck = vco1_ck / 128
Bit 23 Reserved, must be kept at reset value.

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RM0433 Reset and Clock Control (RCC)

Bits 22:16 DIVQ1[6:0]: PLL1 DIVQ division factor

Set and reset by software to control the frequency of the pll1_q_ck clock.
These bits can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’).
0000000: pll1_q_ck = vco1_ck
0000001: pll1_q_ck = vco1_ck / 2 (default after reset)
0000010: pll1_q_ck = vco1_ck / 3
0000011: pll1_q_ck = vco1_ck / 4
...
1111111: pll1_q_ck = vco1_ck / 128
Bits 15:9 DIVP1[6:0]: PLL1 DIVP division factor
Set and reset by software to control the frequency of the pll1_p_ck clock.
These bits can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’).

Note that odd division factors are not allowed.

0000000: pll1_p_ck = vco1_ck

0000001: pll1_p_ck = vco1_ck / 2 (default after reset)
0000010: Not allowed
0000011: pll1_p_ck = vco1_ck / 4
...
1111111: pll1_p_ck = vco1_ck / 128
Bits 8:0 DIVN1[8:0]: Multiplication factor for PLL1 VCO
Set and reset by software to control the multiplication factor of the VCO.
These bits can be written only when the PLL is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’).
0x003: DIVN1 = 4
0x004: DIVN1 = 5
0x005: DIVN1 = 6
...
0x080: DIVN1 = 129 (default after reset)
...
0x1FF: DIVN1 = 512
Others: wrong configurations
Caution: The software has to set correctly these bits to insure that the VCO output frequency is
between its valid frequency range, which is:
– 192 to 836 MHz if PLL1VCOSEL = ‘0’
– 150 to 420 MHz if PLL1VCOSEL = ‘1’
–
VCO output frequency = Fref1_ck x DIVN1, when fractional value 0 has been loaded into FRACN1,
with:
– DIVN1 between 4 and 512
– The input frequency Fref1_ck between 1MHz and 16 MHz

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8.7.14 RCC PLL1 fractional divider register (RCC_PLL1FRACR)

Address offset: 0x034
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACN1[12:0] Res. Res. Res.
rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 FRACN1[12:0]: Fractional part of the multiplication factor for PLL1 VCO
Set and reset by software to control the fractional part of the multiplication factor of the VCO.
These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.
Caution: The software has to set correctly these bits to insure that the VCO output frequency is
between its valid frequency range, which is:
– 192 to 836 MHz if PLL1VCOSEL = ‘0’
– 150 to 420 MHz if PLL1VCOSEL = ‘1’

VCO output frequency = Fref1_ck x (DIVN1 + (FRACN1 / 213)), with

– DIVN1 shall be between 4 and 512
– FRACN1 can be between 0 and 213- 1
– The input frequency Fref1_ck shall be between 1 and 16 MHz.
To change the FRACN value on-the-fly even if the PLL is enabled, the application has to proceed as
follows:
– set the bit PLL1FRACEN to ‘0’,
– wait for 3 ref1_ck periods
– write the new fractional value into FRACN1,
– set the bit PLL1FRACEN to ‘1’.
where ref1_ck, ref2_ck, or ref3_ck are used depending on FRACNx bits index
Bits 2:0 Reserved, must be kept at reset value.

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RM0433 Reset and Clock Control (RCC)

8.7.15 RCC PLL2 divider configuration register (RCC_PLL2DIVR)

Address offset: 0x038
Reset value: 0x0101 0280

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVQ2[6:0]
Res. DIVR2[6:0] Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVP2[6:0] DIVN2[8:0]
rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 DIVR2[6:0]: PLL2 DIVR division factor
Set and reset by software to control the frequency of the pll2_r_ck clock.
These bits can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’).
0000000: pll2_r_ck = vco2_ck
0000001: pll2_r_ck = vco2_ck / 2 (default after reset)
0000010: pll2_r_ck = vco2_ck / 3
0000011: pll2_r_ck = vco2_ck / 4
...
1111111: pll2_r_ck = vco2_ck / 128
Bit 23 Reserved, must be kept at reset value.

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Bits 22:16 DIVQ2[6:0]: PLL2 DIVQ division factor

Set and reset by software to control the frequency of the pll2_q_ck clock.
These bits can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’).
0000000: pll2_q_ck = vco2_ck
0000001: pll2_q_ck = vco2_ck / 2 (default after reset)
0000010: pll2_q_ck = vco2_ck / 3
0000011: pll2_q_ck = vco2_ck / 4
...
1111111: pll2_q_ck = vco2_ck / 128
Bits 15:9 DIVP2[6:0]: PLL2 DIVP division factor
Set and reset by software to control the frequency of the pll2_p_ck clock.
These bits can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’).

0000000: pll2_p_ck = vco2_ck

0000001: pll2_p_ck = vco2_ck / 2 (default after reset)
0000010: pll2_p_ck = vco2_ck / 3
0000011: pll2_p_ck = vco2_ck / 4
...
1111111: pll2_p_ck = vco2_ck / 128
Bits 8:0 DIVN2[8:0]: Multiplication factor for PLL2 VCO
Set and reset by software to control the multiplication factor of the VCO.
These bits can be written only when the PLL is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’).
Caution: The software has to set correctly these bits to insure that the VCO output frequency is
between its valid frequency range, which is:
– 192 to 836 MHz if PLL2VCOSEL = ‘0’
– 150 to 420 MHz if PLL2VCOSEL = ‘1’

VCO output frequency = Fref2_ck x DIVN2, when fractional value 0 has been loaded into FRACN2,
with
– DIVN2 between 4 and 512
– The input frequency Fref2_ck between 1MHz and 16MHz

0x003: DIVN2 = 4
0x004: DIVN2 = 5
0x005: DIVN2 = 6
...
0x080: DIVN2 = 129 (default after reset)
...
0x1FF: DIVN2 = 512
Others: wrong configurations

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RM0433 Reset and Clock Control (RCC)

8.7.16 RCC PLL2 fractional divider register (RCC_PLL2FRACR)

Address offset: 0x03C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACN2[12:0] Res. Res. Res.
rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 FRACN2[12:0]: Fractional part of the multiplication factor for PLL2 VCO
Set and reset by software to control the fractional part of the multiplication factor of the VCO.
These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.
Caution: The software has to set correctly these bits to insure that the VCO output frequency is
between its valid frequency range, which is:
– 192 to 836 MHz if PLL2VCOSEL = ‘0’
– 150 to 420 MHz if PLL2VCOSEL = ‘1’

VCO output frequency = Fref2_ck x (DIVN2 + (FRACN2 / 213)), with

– DIVN2 shall be between 4 and 512
– FRACN2 can be between 0 and 213 - 1
– The input frequency Fref2_ck shall be between 1 and 16 MHz
In order to change the FRACN value on-the-fly even if the PLL is enabled, the application has to
proceed as follow:
– set the bit PLL2FRACEN to ‘0’,
– write the new fractional value into FRACN2,
– set the bit PLL2FRACEN to ‘1’.
Bits 2:0 Reserved, must be kept at reset value.

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8.7.17 RCC PLL3 divider configuration register (RCC_PLL3DIVR)

Address offset: 0x040
Reset value: 0x0101 0280

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. DIVR3[6:0] Res. DIVQ3[6:0]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVP3[6:0] DIVN3[8:0]
rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 DIVR3[6:0]: PLL3 DIVR division factor
Set and reset by software to control the frequency of the pll3_r_ck clock.
These bits can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’).
0000000: pll3_r_ck = vco3_ck
0000001: pll3_r_ck = vco3_ck / 2 (default after reset)
0000010: pll3_r_ck = vco3_ck / 3
0000011: pll3_r_ck = vco3_ck / 4
...
1111111: pll3_r_ck = vco3_ck / 128
Bit 23 Reserved, must be kept at reset value.

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RM0433 Reset and Clock Control (RCC)

Bits 22:16 DIVQ3[6:0]: PLL3 DIVQ division factor

Set and reset by software to control the frequency of the pll3_q_ck clock.
These bits can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’).
0000000: pll3_q_ck = vco3_ck
0000001: pll3_q_ck = vco3_ck / 2 (default after reset)
0000010: pll3_q_ck = vco3_ck / 3
0000011: pll3_q_ck = vco3_ck / 4
...
1111111: pll3_q_ck = vco3_ck / 128
Bits 15:9 DIVP3[6:0]: PLL3 DIVP division factor
Set and reset by software to control the frequency of the pll3_p_ck clock.
These bits can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’).

0000000: pll3_p_ck = vco3_ck

0000001: pll3_p_ck = vco3_ck / 2 (default after reset)
0000010: pll3_p_ck = vco3_ck / 3
0000011: pll3_p_ck = vco3_ck / 4
...
1111111: pll3_p_ck = vco3_ck / 128
Bits 8:0 DIVN3[7:0]: Multiplication factor for PLL3 VCO
Set and reset by software to control the multiplication factor of the VCO.
These bits can be written only when the PLL is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’).
Caution: The software has to set correctly these bits to insure that the VCO output frequency
is between its valid frequency range, which is:
– 192 to 836 MHz if PLL3VCOSEL = ‘0’
– 150 to 420 MHz if PLL3VCOSEL = ‘1’

VCO output frequency = Fref3_ck x DIVN3, when fractional value 0 has been loaded into FRACN3,
with
– DIVN3 between 4 and 512
– The input frequency Fref3_ck between 1MHz and 16MHz

0x003: DIVN3 = 4
0x004: DIVN3 = 5
0x005: DIVN3 = 6
...
0x080: DIVN3 = 129 (default after reset)
...
0x1FF: DIVN3 = 512
Others: wrong configurations

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8.7.18 RCC PLL3 fractional divider register (RCC_PLL3FRACR)

Address offset: 0x044
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACN3[12:0] Res. Res. Res.
rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 FRACN3[12:0]: Fractional part of the multiplication factor for PLL3 VCO
Set and reset by software to control the fractional part of the multiplication factor of the VCO.
These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.
Caution: The software has to set correctly these bits to insure that the VCO output frequency is
between its valid frequency range, which is:
– 192 to 836 MHz if PLL3VCOSEL = ‘0’
– 150 to 420 MHz if PLL3VCOSEL = ‘1’

VCO output frequency = Fref3_ck x (DIVN3 + (FRACN3 / 213)), with

– DIVN3 shall be between 4 and 512
– FRACN3 can be between 0 and 213 - 1
– The input frequency Fref3_ck shall be between 1 and 16 MHz
In order to change the FRACN value on-the-fly even if the PLL is enabled, the application has to
proceed as follow:
– set the bit PLL3FRACEN to ‘0’,
– write the new fractional value into FRACN3,
– set the bit PLL3FRACEN to ‘1’.
Bits 2:0 Reserved, must be kept at reset value.

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RM0433 Reset and Clock Control (RCC)

8.7.19 RCC domain 1 kernel clock configuration register

(RCC_D1CCIPR)
Address offset: 0x04C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SDMMCSEL (1)
Res. Res. CKPERSEL[1:0] (1) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. QSPISEL[1:0] (1) Res. Res. FMCSEL[1:0] (1)
rw rw

1. Changing the clock source on-the-fly is allowed and will not generate any timing violation. However the user has to make
use that both the previous and the new clock sources are present during the switching, and during the whole transition
time. Please refer to Section : Clock switches and gating.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 CKPERSEL[1:0]: per_ck clock source selection
00: hsi_ker_ck clock selected as per_ck clock (default after reset)
01: csi_ker_ck clock selected as per_ck clock
10: hse_ck clock selected as per_ck clock
11: reserved, the per_ck clock is disabled
Bits 27:17 Reserved, must be kept at reset value.
Bit 16 SDMMCSEL: SDMMC kernel clock source selection
0: pll1_q_ck clock is selected as kernel peripheral clock (default after reset)
1: pll2_r_ck clock is selected as kernel peripheral clock
Bits 15:6 Reserved, must be kept at reset value.
Bits 5:4 QSPISEL[1:0]: QUADSPI kernel clock source selection
00: rcc_hclk3 clock selected as kernel peripheral clock (default after reset)
01: pll1_q_ck clock selected as kernel peripheral clock
10: pll2_r_ck clock selected as kernel peripheral clock
11: per_ck clock selected as kernel peripheral clock
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 FMCSEL[1:0]: FMC kernel clock source selection
00: rcc_hclk3 clock selected as kernel peripheral clock (default after reset)
01: pll1_q_ck clock selected as kernel peripheral clock
10: pll2_r_ck clock selected as kernel peripheral clock
11: per_ck clock selected as kernel peripheral clock

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8.7.20 RCC domain 2 kernel clock configuration register

(RCC_D2CCIP1R)
Address offset: 0x050
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANSEL[1:0] (1)

DFSDM1SEL (1)
SWPSEL (1)

SPDIFSEL[1:0]
Res. Res. Res. Res. Res. Res. (1) Res. SPI45SEL[2:0] (1)

rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SPI123SEL[2:0] (1) Res. Res. Res. SAI23SEL[2:0] (1) Res. Res. Res. SAI1SEL[2:0] (1)
rw rw rw

1. Changing the clock source on-the-fly is allowed and will not generate any timing violation. However the user has to make
sure that both the previous and the new clock sources are present during the switching, and for the whole transition time.
Please refer to Section : Clock switches and gating.

Bit 31 SWPSEL: SWPMI kernel clock source selection

Set and reset by software.
0: pclk is selected as SWPMI kernel clock (default after reset)
1: hsi_ker_ck clock is selected as SWPMI kernel clock
Bit 30 Reserved, must be kept at reset value.
Bits 29:28 FDCANSEL: FDCAN kernel clock source selection
Set and reset by software.
00: hse_ck clock is selected as FDCAN kernel clock (default after reset)
01: pll1_q_ck clock is selected as FDCAN kernel clock
10: pll2_q_ck clock is selected as FDCAN kernel clock
11: reserved, the kernel clock is disabled
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 DFSDM1SEL: DFSDM1 kernel Clk clock source selection
Set and reset by software.
Note: the DFSDM1 Aclk Clock Source Selection is done by SAI1SEL.
0: rcc_pclk2 is selected as DFSDM1 Clk kernel clock (default after reset)
1: sys_ck clock is selected as DFSDM1 Clk kernel clock
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 SPDIFSEL[1:0]: SPDIFRX kernel clock source selection
00: pll1_q_ck clock selected as SPDIFRX kernel clock (default after reset)
01: pll2_r_ck clock selected as SPDIFRX kernel clock
10: pll3_r_ck clock selected as SPDIFRX kernel clock
11: hsi_ker_ck clock selected as SPDIFRX kernel clock
Bit 19 Reserved, must be kept at reset value.

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RM0433 Reset and Clock Control (RCC)

Bits 18:16 SPI45SEL[2:0]: SPI4 and 5 kernel clock source selection

Set and reset by software.
000: APB clock is selected as kernel clock (default after reset)
001: pll2_q_ck clock is selected as kernel clock
010: pll3_q_ck clock is selected as kernel clock
011: hsi_ker_ck clock is selected as kernel clock
100: csi_ker_ck clock is selected as kernel clock
101: hse_ck clock is selected as kernel clock
others: reserved, the kernel clock is disabled
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 SPI123SEL[2:0]: SPI/I2S1,2 and 3 kernel clock source selection
Set and reset by software.
Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to
switch to another clock. Refer to Section : Clock switches and gating for additional
information.
000: pll1_q_ck clock selected as SPI/I2S1,2 and 3 kernel clock (default after reset)
001: pll2_p_ck clock selected as SPI/I2S1,2 and 3 kernel clock
010: pll3_p_ck clock selected as SPI/I2S1,2 and 3 kernel clock
011: I2S_CKIN clock selected as SPI/I2S1,2 and 3 kernel clock
100: per_ck clock selected as SPI/I2S1,2 and 3 kernel clock
others: reserved, the kernel clock is disabled
Note: I2S_CKIN is an external clock taken from a pin.
Bits 11:9 Reserved, must be kept at reset value.

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Bits 8:6 SAI23SEL[2:0]: SAI2 and SAI3 kernel clock source selection
Set and reset by software.
Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to
switch to another clock. Refer to Section : Clock switches and gating for additional
information.
000: pll1_q_ck clock selected as SAI2 and SAI3 kernel clock (default after reset)
001: pll2_p_ck clock selected as SAI2 and SAI3 kernel clock
010: pll3_p_ck clock selected as SAI2 and SAI3 kernel clock
011: I2S_CKIN clock selected as SAI2 and SAI3 kernel clock
100: per_ck clock selected as SAI2 and SAI3 kernel clock
others: reserved, the kernel clock is disabled
Note: I2S_CKIN is an external clock taken from a pin.
Bits 5:3 Reserved, must be kept at reset value.
Bits 2:0 SAI1SEL[2:0]: SAI1 and DFSDM1 kernel Aclk clock source selection
Set and reset by software.
Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to
switch to another clock. Refer to Section : Clock switches and gating for additional
information.
Note: DFSDM1 Clock Source Selection is done by DFSDM1SEL.
000: pll1_q_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock (default after reset)
001: pll2_p_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock
010: pll3_p_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock
011: I2S_CKIN clock selected as SAI1 and DFSDM1 Aclk kernel clock
100: per_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock
others: reserved, the kernel clock is disabled
Note: I2S_CKIN is an external clock taken from a pin.

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RM0433 Reset and Clock Control (RCC)

8.7.21 RCC domain 2 kernel clock configuration register

(RCC_D2CCIP2R)
Address offset: 0x054
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. LPTIM1SEL[2:0] (1) Res. Res. Res. Res. CECSEL[1:0] (1) USBSEL[1:0] (1) Res. Res. Res. Res.
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

I2C123SEL[1:0]
Res. Res. (1) Res. Res. RNGSEL[1:0] (1) Res. Res. USART16SEL[2:0] (1) USART234578SEL[2:0] (1)

rw rw rw rw

1. Changing the clock source on-the-fly is allowed and will not generate any timing violation. However the user has to make
sure that both the previous and the new clock sources are present during the switching, and for the whole transition time.
Please refer to Section : Clock switches and gating.

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 LPTIM1SEL[2:0]: LPTIM1 kernel clock source selection
Set and reset by software.
000: rcc_pclk1 clock selected as kernel peripheral clock (default after reset)
001: pll2_p_ck clock selected as kernel peripheral clock
010: pll3_r_ck clock selected as kernel peripheral clock
011: lse_ck clock selected as kernel peripheral clock
100: lsi_ck clock selected as kernel peripheral clock
101: per_ck clock selected as kernel peripheral clock
others: reserved, the kernel clock is disabled
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:22 CECSEL[1:0]: HDMI-CEC kernel clock source selection
Set and reset by software.
00: lse_ck clock is selected as kernel clock (default after reset)
01: lsi_ck clock is selected as kernel clock
10: csi_ker_ck divided by 122 is selected as kernel clock
11: reserved, the kernel clock is disabled
Bits 21:20 USBSEL[1:0]: USBOTG 1 and 2 kernel clock source selection
Set and reset by software.
00: Disable the kernel clock (default after reset)
01: pll1_q_ck clock is selected as kernel clock
10: pll3_q_ck clock is selected as kernel clock
11: hsi48_ck clock is selected as kernel clock
Bits 19:14 Reserved, must be kept at reset value.
Bits 13:12 I2C123SEL[1:0]: I2C1,2,3 kernel clock source selection
Set and reset by software.
00: rcc_pclk1 clock is selected as kernel clock (default after reset)
01: pll3_r_ck clock is selected as kernel clock
10: hsi_ker_ck clock is selected as kernel clock
11: csi_ker_ck clock is selected as kernel clock

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Bits 11:10 Reserved, must be kept at reset value.

Bits 9:8 RNGSEL[1:0]: RNG kernel clock source selection
Set and reset by software.
00: hsi8_ck clock is selected as kernel clock (default after reset)
01: pll1_q_ck clock is selected as kernel clock
10: lse_ck clock is selected as kernel clock
11: lsi_ck clock is selected as kernel clock
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:3 USART16SEL[2:0]: USART1 and 6 kernel clock source selection
Set and reset by software.
000: rcc_pclk2 clock is selected as kernel clock (default after reset)
001: pll2_q_ck clock is selected as kernel clock
010: pll3_q_ck clock is selected as kernel clock
011: hsi_ker_ck clock is selected as kernel clock
100: csi_ker_ck clock is selected as kernel clock
101: lse_ck clock is selected as kernel clock
others: reserved, the kernel clock is disabled
Bits 2:0 USART234578SEL[2:0]: USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection
Set and reset by software.
000: rcc_pclk1 clock is selected as kernel clock (default after reset)
001: pll2_q_ck clock is selected as kernel clock
010: pll3_q_ck clock is selected as kernel clock
011: hsi_ker_ck clock is selected as kernel clock
100: csi_ker_ck clock is selected as kernel clock
101: lse_ck clock is selected as kernel clock
others: reserved, the kernel clock is disabled

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RM0433 Reset and Clock Control (RCC)

8.7.22 RCC domain 3 kernel clock configuration register

(RCC_D3CCIPR)
Address offset: 0x058
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. SPI6SEL[2:0] (1) Res. SAI4BSEL[2:0] (1) SAI4ASEL[2:0] (1) Res. Res. Res. ADCSEL[1:0] (1)
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPTIM345SEL[2:0] (1) LPTIM2SEL[2:0] (1) I2C4SEL[1:0] (1) Res. Res. Res. Res. Res. LPUART1SEL[2:0] (1)

rw rw rw rw

1. Changing the clock source on-the-fly is allowed, and will not generate any timing violation. However the user has to make
sure that both the previous and the new clock sources are present during the switching, and for the whole transition time.
Please refer to Section : Clock switches and gating.

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 SPI6SEL[2:0]: SPI6 kernel clock source selection
Set and reset by software.
000: rcc_pclk4 clock selected as kernel peripheral clock (default after reset)
001: pll2_q_ck clock selected as kernel peripheral clock
010: pll3_q_ck clock selected as kernel peripheral clock
011: hsi_ker_ck clock selected as kernel peripheral clock
100: csi_ker_ck clock selected as kernel peripheral clock
101: hse_ck clock selected as kernel peripheral clock
others: reserved, the kernel clock is disabled
Bit 27 Reserved, must be kept at reset value.
Bits 26:24 SAI4BSEL[2:0]: Sub-Block B of SAI4 kernel clock source selection
Set and reset by software.
Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to
switch to another clock. Refer to Section : Clock switches and gating for additional
information.
000: pll1_q_ck clock selected as kernel peripheral clock (default after reset)
001: pll2_p_ck clock selected as kernel peripheral clock
010: pll3_p_ck clock selected as kernel peripheral clock
011: I2S_CKIN clock selected as kernel peripheral clock
100: per_ck clock selected as kernel peripheral clock
others: reserved, the kernel clock is disabled
Note: I2S_CKIN is an external clock taken from a pin.

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Bits 23:21 SAI4ASEL[2:0]: Sub-Block A of SAI4 kernel clock source selection

Set and reset by software.
Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to
switch to another clock. Refer to Section : Clock switches and gating for additional
information.
000: pll1_q_ck clock selected as kernel peripheral clock (default after reset)
001: pll2_p_ck clock selected as kernel peripheral clock
010: pll3_p_ck clock selected as kernel peripheral clock
011: I2S_CKIN clock selected as kernel peripheral clock
100: per_ck clock selected as kernel peripheral clock
others: reserved, the kernel clock is disabled
Note: I2S_CKIN is an external clock taken from a pin.
Bits 20:18 Reserved, must be kept at reset value.
Bits 17:16 ADCSEL[1:0]: SAR ADC kernel clock source selection
Set and reset by software.
00: pll2_p_ck clock selected as kernel peripheral clock (default after reset)
01: pll3_r_ck clock selected as kernel peripheral clock
10: per_ck clock selected as kernel peripheral clock
others: reserved, the kernel clock is disabled
Bits 15:13 LPTIM345SEL[2:0]: LPTIM3,4,5 kernel clock source selection
Set and reset by software.
000: rcc_pclk4 clock selected as kernel peripheral clock (default after reset)
001: pll2_p_ck clock selected as kernel peripheral clock
010: pll3_r_ck clock selected as kernel peripheral clock
011: lse_ck clock selected as kernel peripheral clock
100: lsi_ck clock selected as kernel peripheral clock
101: per_ck clock selected as kernel peripheral clock
others: reserved, the kernel clock is disabled
Bits 12:10 LPTIM2SEL[2:0]: LPTIM2 kernel clock source selection
Set and reset by software.
000: rcc_pclk4 clock selected as kernel peripheral clock (default after reset)
001: pll2_p_ck clock selected as kernel peripheral clock
010: pll3_r_ck clock selected as kernel peripheral clock
011: lse_ck clock selected as kernel peripheral clock
100: lsi_ck clock selected as kernel peripheral clock
101: per_ck clock selected as kernel peripheral clock
others: reserved, the kernel clock is disabled

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RM0433 Reset and Clock Control (RCC)

Bits 9:8 I2C4SEL[1:0]: I2C4 kernel clock source selection

Set and reset by software.
00: rcc_pclk4 clock selected as kernel peripheral clock (default after reset)
01: pll3_r_ck clock selected as kernel peripheral clock
10: hsi_ker_ck clock selected as kernel peripheral clock
11: csi_ker_ck clock selected as kernel peripheral clock
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 LPUART1SEL[2:0]: LPUART1 kernel clock source selection
Set and reset by software.
000: rcc_pclk_d3 clock is selected as kernel peripheral clock (default after reset)
001: pll2_q_ck clock is selected as kernel peripheral clock
010: pll3_q_ck clock is selected as kernel peripheral clock
011: hsi_ker_ck clock is selected as kernel peripheral clock
100: csi_ker_ck clock is selected as kernel peripheral clock
101: lse_ck clock is selected as kernel peripheral clock
others: reserved, the kernel clock is disabled

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8.7.23 RCC clock source interrupt enable register (RCC_CIER)

Address offset: 0x060
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HSI48RDYIE
PLL3RDYIE

PLL2RDYIE

PLL1RDYIE

HSERDYIE

LSERDYIE
LSECSSIE

CSIRDYIE

HSIRDYIE

LSIRDYIE
Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 LSECSSIE: LSE clock security system Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the Clock Security System on
external 32 kHz oscillator.
0: LSE CSS interrupt disabled (default after reset)
1: LSE CSS interrupt enabled
Bit 8 PLL3RDYIE: PLL3 ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by PLL3 lock.
0: PLL3 lock interrupt disabled (default after reset)
1: PLL3 lock interrupt enabled
Bit 7 PLL2RDYIE: PLL2 ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by PLL2 lock.
0: PLL2 lock interrupt disabled (default after reset)
1: PLL2 lock interrupt enabled
Bit 6 PLL1RDYIE: PLL1 ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by PLL1 lock.
0: PLL1 lock interrupt disabled (default after reset)
1: PLL1 lock interrupt enabled
Bit 5 HSI48RDYIE: HSI48 ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization.
0: HSI48 ready interrupt disabled (default after reset)
1: HSI48 ready interrupt enabled
Bit 4 CSIRDYIE: CSI ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization.
0: CSI ready interrupt disabled (default after reset)
1: CSI ready interrupt enabled
Bit 3 HSERDYIE: HSE ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization.
0: HSE ready interrupt disabled (default after reset)
1: HSE ready interrupt enabled

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RM0433 Reset and Clock Control (RCC)

Bit 2 HSIRDYIE: HSI ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization.
0: HSI ready interrupt disabled (default after reset)
1: HSI ready interrupt enabled
Bit 1 LSERDYIE: LSE ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization.
0: LSE ready interrupt disabled (default after reset)
1: LSE ready interrupt enabled
Bit 0 LSIRDYIE: LSI ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization.
0: LSI ready interrupt disabled (default after reset)
1: LSI ready interrupt enabled

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8.7.24 RCC clock source Interrupt flag register (RCC_CIFR)

Address offset: 0x64
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HSI48RDYF
PLL3RDYF

PLL2RDYF

PLL1RDYF

HSERDYF
HSECSSF

LSERDYF
LSECSSF

CSIRDYF

HSIRDYF

LSIRDYF
Res. Res. Res. Res. Res.

r r r r r r r r r r r

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSECSSF: HSE clock security system Interrupt Flag
Reset by software by writing HSECSSC bit.
Set by hardware in case of HSE clock failure.
0: No clock security interrupt caused by HSE clock failure (default after reset)
1: Clock security interrupt caused by HSE clock failure
Bit 9 LSECSSF: LSE clock security system Interrupt Flag
Reset by software by writing LSECSSC bit.
Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set.
0: No failure detected on the external 32 kHz oscillator (default after reset)
1: A failure is detected on the external 32 kHz oscillator
Bit 8 PLL3RDYF: PLL3 ready Interrupt Flag
Reset by software by writing PLL3RDYC bit.
Set by hardware when the PLL3 locks and PLL3RDYIE is set.
0: No clock ready interrupt caused by PLL3 lock (default after reset)
1: Clock ready interrupt caused by PLL3 lock
Bit 7 PLL2RDYF: PLL2 ready Interrupt Flag
Reset by software by writing PLL2RDYC bit.
Set by hardware when the PLL2 locks and PLL2RDYIE is set.
0: No clock ready interrupt caused by PLL2 lock (default after reset)
1: Clock ready interrupt caused by PLL2 lock
Bit 6 PLL1RDYF: PLL1 ready Interrupt Flag
Reset by software by writing PLL1RDYC bit.
Set by hardware when the PLL1 locks and PLL1RDYIE is set.
0: No clock ready interrupt caused by PLL1 lock (default after reset)
1: Clock ready interrupt caused by PLL1 lock
Bit 5 HSI48RDYF: HSI48 ready Interrupt Flag
Reset by software by writing HSI48RDYC bit.
Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.
0: No clock ready interrupt caused by the HSI48 oscillator (default after reset)
1: Clock ready interrupt caused by the HSI48 oscillator

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RM0433 Reset and Clock Control (RCC)

Bit 4 CSIRDYF: CSI ready Interrupt Flag

Reset by software by writing CSIRDYC bit.
Set by hardware when the CSI clock becomes stable and CSIRDYIE is set.
0: No clock ready interrupt caused by the CSI (default after reset)
1: Clock ready interrupt caused by the CSI
Bit 3 HSERDYF: HSE ready Interrupt Flag
Reset by software by writing HSERDYC bit.
Set by hardware when the HSE clock becomes stable and HSERDYIE is set.
0: No clock ready interrupt caused by the HSE (default after reset)
1: Clock ready interrupt caused by the HSE
Bit 2 HSIRDYF: HSI ready Interrupt Flag
Reset by software by writing HSIRDYC bit.
Set by hardware when the HSI clock becomes stable and HSIRDYIE is set.
0: No clock ready interrupt caused by the HSI (default after reset)
1: Clock ready interrupt caused by the HSI
Bit 1 LSERDYF: LSE ready Interrupt Flag
Reset by software by writing LSERDYC bit.
Set by hardware when the LSE clock becomes stable and LSERDYIE is set.
0: No clock ready interrupt caused by the LSE (default after reset)
1: Clock ready interrupt caused by the LSE
Bit 0 LSIRDYF: LSI ready Interrupt Flag
Reset by software by writing LSIRDYC bit.
Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.
0: No clock ready interrupt caused by the LSI (default after reset)
1: Clock ready interrupt caused by the LSI

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8.7.25 RCC clock source interrupt clear register (RCC_CICR)

Address offset: 0x68
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HSI48RDYC
PLL3RDYC

PLL2RDYC

PLL1RDYC

HSERDYC
HSECSSC

LSERDYC
LSECSSC

CSIRDYC

HSIRDYC

LSIRDYC
Res. Res. Res. Res. Res.

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSECSSC: HSE clock security system Interrupt Clear
Set by software to clear HSECSSF.
Reset by hardware when clear done.
0: HSECSSF no effect (default after reset)
1: HSECSSF cleared
Bit 9 LSECSSC: LSE clock security system Interrupt Clear
Set by software to clear LSECSSF.
Reset by hardware when clear done.
0: LSECSSF no effect (default after reset)
1: LSECSSF cleared
Bit 8 PLL3RDYC: PLL3 ready Interrupt Clear
Set by software to clear PLL3RDYF.
Reset by hardware when clear done.
0: PLL3RDYF no effect (default after reset)
1: PLL3RDYF cleared
Bit 7 PLL2RDYC: PLL2 ready Interrupt Clear
Set by software to clear PLL2RDYF.
Reset by hardware when clear done.
0: PLL2RDYF no effect (default after reset)
1: PLL2RDYF cleared
Bit 6 PLL1RDYC: PLL1 ready Interrupt Clear
Set by software to clear PLL1RDYF.
Reset by hardware when clear done.
0: PLL1RDYF no effect (default after reset)
1: PLL1RDYF cleared
Bit 5 HSI48RDYC: HSI48 ready Interrupt Clear
Set by software to clear HSI48RDYF.
Reset by hardware when clear done.
0: HSI48RDYF no effect (default after reset)
1: HSI48RDYF cleared

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RM0433 Reset and Clock Control (RCC)

Bit 4 CSIRDYC: CSI ready Interrupt Clear

Set by software to clear CSIRDYF.
Reset by hardware when clear done.
0: CSIRDYF no effect (default after reset)
1: CSIRDYF cleared
Bit 3 HSERDYC: HSE ready Interrupt Clear
Set by software to clear HSERDYF.
Reset by hardware when clear done.
0: HSERDYF no effect (default after reset)
1: HSERDYF cleared
Bit 2 HSIRDYC: HSI ready Interrupt Clear
Set by software to clear HSIRDYF.
Reset by hardware when clear done.
0: HSIRDYF no effect (default after reset)
1: HSIRDYF cleared
Bit 1 LSERDYC: LSE ready Interrupt Clear
Set by software to clear LSERDYF.
Reset by hardware when clear done.
0: LSERDYF no effect (default after reset)
1: LSERDYF cleared
Bit 0 LSIRDYC: LSI ready Interrupt Clear
Set by software to clear LSIRDYF.
Reset by hardware when clear done.
0: LSIRDYF no effect (default after reset)
1: LSIRDYF cleared

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8.7.26 RCC backup domain control register (RCC_BDCR)

Address offset: 0x070
Reset value: 0x0000 0000, reset by Backup domain reset.
Access: 0 ≤ wait state ≤ 7, word, half-word and byte access. Wait states are inserted in case
of successive accesses to this register.
After a system reset, the RCC_BDCR register is write-protected. To modify this register, the
DBP bit in the PWR control register 1 (PWR_CR1) has to be set to ‘1’. RCC_BDCR bits are
only reset after a backup domain reset (see Section 8.4.6: Backup domain reset). Any other
internal or external reset will not have any effect on these bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BDRST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSECSSON
LSECSSD

LSERDY
LSEBYP
RTCEN

LSEON
Res. Res. Res. Res. Res. RTCSEL[1:0] Res. LSEDRV[1:0]

rw rwo r rs rw rw r rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 BDRST: Backup domain software reset
Set and reset by software.
0: Reset not activated (default after backup domain reset)
1: Resets the entire VSW domain
Bit 15 RTCEN: RTC clock enable
Set and reset by software.
0: rtc_ck clock is disabled (default after backup domain reset)
1: rtc_ck clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]:RTC clock source selection
Set by software to select the clock source for the RTC. These bits can be written only one time
(except in case of failure detection on LSE). These bits must be written before LSECSSON is
enabled. The BDRST bit can be used to reset them, then it can be written one time again.
If HSE is selected as RTC clock: this clock is lost when the system is in Stop mode or in case of a
pin reset (NRST).
00: No clock (default after backup domain reset)
01: LSE clock used as RTC clock
10: LSI clock used as RTC clock
11: HSE clock divided by RTCPRE value is used as RTC clock
Bit 7 Reserved, must be kept at reset value.

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RM0433 Reset and Clock Control (RCC)

Bit 6 LSECSSD: LSE clock security system failure detection

Set by hardware to indicate when a failure has been detected by the Clock Security System on the
external 32 kHz oscillator.
0: No failure detected on 32 kHz oscillator (default after backup domain reset)
1: Failure detected on 32 kHz oscillator
Bit 5 LSECSSON: LSE clock security system enable
Set by software to enable the Clock Security System on 32 kHz oscillator.
LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by
hardware), and after RTCSEL is selected.
Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD = ‘1’). In
that case the software must disable LSECSSON.
0: Clock Security System on 32 kHz oscillator OFF (default after backup domain reset)
1: Clock Security System on 32 kHz oscillator ON
Bits 4:3 LSEDRV[1:0]: LSE oscillator driving capability
Set by software to select the driving capability of the LSE oscillator.
00: Lowest drive (default after backup domain reset)
01: Medium low drive
10: Medium high drive
11: Highest drive

Bit 2 LSEBYP: LSE oscillator bypass

Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the
LSE is enabled (by LSEON) or ready (LSERDY = ‘1’)
0: LSE oscillator not bypassed (default after backup domain reset)
1: LSE oscillator bypassed
Bit 1 LSERDY: LSE oscillator ready
Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck
clock to fall down after LSEON has been set to ‘0’.
0: LSE oscillator not ready (default after backup domain reset)
1: LSE oscillator ready
Bit 0 LSEON: LSE oscillator enabled
Set and reset by software.
0: LSE oscillator OFF (default after backup domain reset)
1: LSE oscillator ON

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8.7.27 RCC clock control and status register (RCC_CSR)

Address offset: 0x074
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 7, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSIRDY

LSION
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LSIRDY: LSI oscillator ready
Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable.
This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to ‘0’.
This bit can be set even when LSION is not enabled if there is a request for LSI clock by the Clock
Security System on LSE or by the Low Speed Watchdog or by the RTC.
0: LSI clock is not ready (default after reset)
1: LSI clock is ready
Bit 0 LSION: LSI oscillator enable
Set and reset by software.
0: LSI is OFF (default after reset)
1: LSI is ON

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RM0433 Reset and Clock Control (RCC)

8.7.28 RCC AHB3 reset register (RCC_AHB3RSTR)

Address offset: 0x07C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SDMMC1RST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

JPGDECRST

DMA2DRST

MDMARST
QSPIRST

FMCRST

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 SDMMC1RST: SDMMC1 and SDMMC1 delay block reset
Set and reset by software.
0: does not reset SDMMC1 and SDMMC1 Delay block (default after reset)
1: resets SDMMC1 and SDMMC1 Delay block
Bit 15 Reserved, must be kept at reset value.
Bit 14 QSPIRST: QUADSPI and QUADSPI delay block reset
Set and reset by software.
0: does not reset QUADSPI and QUADSPI Delay block (default after reset)
1: resets QUADSPI and QUADSPI Delay block
Bit 13 Reserved, must be kept at reset value.
Bit 12 FMCRST: FMC block reset
Set and reset by software.
0: does not reset FMC block (default after reset)
1: resets FMC block
Bits 11:6 Reserved, must be kept at reset value.
Bit 5 JPGDECRST: JPGDEC block reset
Set and reset by software.
0: does not reset JPGDEC block (default after reset)
1: resets JPGDEC block

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Bit 4 DMA2DRST: DMA2D block reset

Set and reset by software.
0: does not reset DMA2D block (default after reset)
1: resets DMA2D block
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 MDMARST: MDMA block reset
Set and reset by software.
0: does not reset MDMA block (default after reset)
1: resets MDMA block

430/3353 RM0433 Rev 8

RM0433 Reset and Clock Control (RCC)

8.7.29 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)

Address offset: 0x080
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

USB2OTGRST

USB1OTGRST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETH1MACRST

ADC12RST

DMA2RST

DMA1RST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 USB2OTGRST: USB2OTG (OTG_HS2) block reset
Set and reset by software.
0: does not reset USB2OTG block (default after reset)
1: resets USB2OTG block
Bit 26 Reserved, must be kept at reset value.
Bit 25 USB1OTGRST: USB1OTG (OTG_HS1) block reset
Set and reset by software.
0: does not reset USB1OTG block (default after reset)
1: resets USB1OTG block
Bits 24:16 Reserved, must be kept at reset value.
Bit 15 ETH1MACRST: ETH1MAC block reset
Set and reset by software.
0: does not reset ETH1MAC block (default after reset)
1: resets ETH1MAC block
Bits 14:6 Reserved, must be kept at reset value.
Bit 5 ADC12RST: ADC1 and 2 block reset
Set and reset by software.
0: does not reset ADC1 and 2 block (default after reset)
1: resets ADC1 and 2 block

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Reset and Clock Control (RCC) RM0433

Bits 4:2 Reserved, must be kept at reset value.

Bit 1 DMA2RST: DMA2 block reset
Set and reset by software.
0: does not reset DMA2 block (default after reset)
1: resets DMA2 block
Bit 0 DMA1RST: DMA1 block reset
Set and reset by software.
0: does not reset DMA1 block (default after reset)
1: resets DMA1 block

432/3353 RM0433 Rev 8

RM0433 Reset and Clock Control (RCC)

8.7.30 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)

Address offset: 0x084
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDMMC2RST

CAMITFRST
CRYPTRST
HASHRST
RNGRST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 SDMMC2RST: SDMMC2 and SDMMC2 Delay block reset
Set and reset by software.
0: does not reset SDMMC2 and SDMMC2 Delay block (default after reset)
1: resets SDMMC2 and SDMMC2 Delay block
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 RNGRST: Random Number Generator block reset
Set and reset by software.
0: does not reset RNG block (default after reset)
1: resets RNG block
Bit 5 HASHRST: Hash block reset
Set and reset by software.
0: does not reset hash block (default after reset)
1: resets hash block
Bit 4 CRYPTRST: Cryptography block reset
Set and reset by software.
0: does not reset cryptography block (default after reset)
1: resets cryptography block
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 CAMITFRST: CAMITF block reset
Set and reset by software.
0: does not reset the CAMITF block (default after reset)
1: resets the CAMITF block

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Reset and Clock Control (RCC) RM0433

8.7.31 RCC AHB4 peripheral reset register (RCC_AHB4RSTR)

Address offset: 0x088
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

HSEMRST

BDMARST
ADC3RST

CRCRST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPIOGRST
GPIOHRST

GPIODRST

GPIOCRST
GPIOKRST

GPIOERST

GPIOBRST

GPIOARST
GPIOFRST
GPIOJRST

GPIOIRST
Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 HSEMRST: HSEM block reset
Set and reset by software.
0: does not reset the HSEM block (default after reset)
1: resets the HSEM block
Bit 24 ADC3RST: ADC3 block reset
Set and reset by software.
0: does not reset the ADC3 block (default after reset)
1: resets the ADC3 block
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 BDMARST: BDMA block reset
Set and reset by software.
0: does not reset the BDMA block (default after reset)
1: resets the BDMA block
Bit 20 Reserved, must be kept at reset value.
Bit 19 CRCRST: CRC block reset
Set and reset by software.
0: does not reset the CRC block (default after reset)
1: resets the CRC block
Bits 18:11 Reserved, must be kept at reset value.
Bit 10 GPIOKRST: GPIOK block reset
Set and reset by software.
0: does not reset the GPIOK block (default after reset)
1: resets the GPIOK block
Bit 9 GPIOJRST: GPIOJ block reset
Set and reset by software.
0: does not reset the GPIOJ block (default after reset)
1: resets the GPIOJ block

434/3353 RM0433 Rev 8

RM0433 Reset and Clock Control (RCC)

Bit 8 GPIOIRST: GPIOI block reset

Set and reset by software.
0: does not reset the GPIOI block (default after reset)
1: resets the GPIOI block
Bit 7 GPIOHRST: GPIOH block reset
Set and reset by software.
0: does not reset the GPIOH block (default after reset)
1: resets the GPIOH block
Bit 6 GPIOGRST: GPIOG block reset
Set and reset by software.
0: does not reset the GPIOG block (default after reset)
1: resets the GPIOG block
Bit 5 GPIOFRST: GPIOF block reset
Set and reset by software.
0: does not reset the GPIOF block (default after reset)
1: resets the GPIOF block
Bit 4 GPIOERST: GPIOE block reset
Set and reset by software.
0: does not reset the GPIOE block (default after reset)
1: resets the GPIOE block
Bit 3 GPIODRST: GPIOD block reset
Set and reset by software.
0: does not reset the GPIOD block (default after reset)
1: resets the GPIOD block
Bit 2 GPIOCRST: GPIOC block reset
Set and reset by software.
0: does not reset the GPIOC block (default after reset)
1: resets the GPIOC block
Bit 1 GPIOBRST: GPIOB block reset
Set and reset by software.
0: does not reset the GPIOB block (default after reset)
1: resets the GPIOB block
Bit 0 GPIOARST: GPIOA block reset
Set and reset by software.
0: does not reset the GPIOA block (default after reset)
1: resets the GPIOA block

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Reset and Clock Control (RCC) RM0433

8.7.32 RCC APB3 peripheral reset register (RCC_APB3RSTR)

Address offset: 0x08C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LTDCRST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 LTDCRST: LTDC block reset
Set and reset by software.
0: does not reset the LTDC block (default after reset)
1: resets the LTDC block
Bits 2:0 Reserved, must be kept at reset value.

436/3353 RM0433 Rev 8

RM0433 Reset and Clock Control (RCC)

8.7.33 RCC APB1 peripheral reset register (RCC_APB1LRSTR)

Address offset: 0x090
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPDIFRXRST
USART3RST

USART2RST
UART8RST

UART7RST

UART5RST

UART4RST
DAC12RST

CECRST

I2C3RST

I2C2RST

I2C1RST
Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPTIM1RST

TIM14RST

TIM13RST

TIM12RST

TIM7RST

TIM6RST

TIM5RST

TIM4RST

TIM3RST

TIM2RST
SPI3RST

SPI2RST

Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 UART8RST: UART8 block reset

Set and reset by software.
0: does not reset the UART8 block (default after reset)
1: resets the UART8 block
Bit 30 UART7RST: UART7 block reset
Set and reset by software.
0: does not reset the UART7 block (default after reset)
1: resets the UART7 block
Bit 29 DAC12RST: DAC1 and 2 Blocks Reset
Set and reset by software.
0: does not reset the DAC1 and 2 blocks (default after reset)
1: resets the DAC1 and 2 blocks
Bit 28 Reserved, must be kept at reset value.
Bit 27 CECRST: HDMI-CEC block reset
Set and reset by software.
0: does not reset the HDMI-CEC block (default after reset)
1: resets the HDMI-CEC block
Bits 26:24 Reserved, must be kept at reset value.
Bit 23 I2C3RST: I2C3 block reset
Set and reset by software.
0: does not reset the I2C3 block (default after reset)
1: resets the I2C3 block
Bit 22 I2C2RST: I2C2 block reset
Set and reset by software.
0: does not reset the I2C2 block (default after reset)
1: resets the I2C2 block

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Reset and Clock Control (RCC) RM0433

Bit 21 I2C1RST: I2C1 block reset

Set and reset by software.
0: does not reset the I2C1 block (default after reset)
1: resets the I2C1 block
Bit 20 UART5RST: UART5 block reset
Set and reset by software.
0: does not reset the UART5 block (default after reset)
1: resets the UART5 block
Bit 19 UART4RST: UART4 block reset
Set and reset by software.
0: does not reset the UART4 block (default after reset)
1: resets the UART4 block
Bit 18 USART3RST: USART3 block reset
Set and reset by software.
0: does not reset the USART3 block (default after reset)
1: resets the USART3 block
Bit 17 USART2RST: USART2 block reset
Set and reset by software.
0: does not reset the USART2 block (default after reset)
1: resets the USART2 block
Bit 16 SPDIFRXRST: SPDIFRX block reset
Set and reset by software.
0: does not reset the SPDIFRX block (default after reset)
1: resets the SPDIFRX block
Bit 15 SPI3RST: SPI3 block reset
Set and reset by software.
0: does not reset the SPI3 block (default after reset)
1: resets the SPI3 block
Bit 14 SPI2RST: SPI2 block reset
Set and reset by software.
0: does not reset the SPI2 block (default after reset)
1: resets the SPI2 block
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 LPTIM1RST: LPTIM1 block reset
Set and reset by software.
0: does not reset the LPTIM1 block (default after reset)
1: resets the LPTIM1 block
Bit 8 TIM14RST: TIM14 block reset
Set and reset by software.
0: does not reset the TIM14 block (default after reset)
1: resets the TIM14 block
Bit 7 TIM13RST: TIM13 block reset
Set and reset by software.
0: does not reset the TIM13 block (default after reset)
1: resets the TIM13 block

438/3353 RM0433 Rev 8

RM0433 Reset and Clock Control (RCC)

Bit 6 TIM12RST: TIM12 block reset

Set and reset by software.
0: does not reset the TIM12 block (default after reset)
1: resets the TIM12 block
Bit 5 TIM7RST: TIM7 block reset
Set and reset by software.
0: does not reset the TIM7 block (default after reset)
1: resets the TIM7 block
Bit 4 TIM6RST: TIM6 block reset
Set and reset by software.
0: does not reset the TIM6 block (default after reset)
1: resets the TIM6 block
Bit 3 TIM5RST: TIM5 block reset
Set and reset by software.
0: does not reset the TIM5 block (default after reset)
1: resets the TIM5 block
Bit 2 TIM4RST: TIM4 block reset
Set and reset by software.
0: does not reset the TIM4 block (default after reset)
1: resets the TIM4 block
Bit 1 TIM3RST: TIM3 block reset
Set and reset by software.
0: does not reset the TIM3 block (default after reset)
1: resets the TIM3 block
Bit 0 TIM2RST: TIM2 block reset
Set and reset by software.
0: does not reset the TIM2 block (default after reset)
1: resets the TIM2 block

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Reset and Clock Control (RCC) RM0433

8.7.34 RCC APB1 peripheral reset register (RCC_APB1HRSTR)

Address offset: 0x094
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPAMPRST
FDCANRST

MDIOSRST

SWPRST

CRSRST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 FDCANRST: FDCAN block reset
Set and reset by software.
0: does not reset the FDCAN block (default after reset)
1: resets the FDCAN block
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSRST: MDIOS block reset
Set and reset by software.
0: does not reset the MDIOS block (default after reset)
1: resets the MDIOS block
Bit 4 OPAMPRST: OPAMP block reset
Set and reset by software.
0: does not reset the OPAMP block (default after reset)
1: resets the OPAMP block
Bit 3 Reserved, must be kept at reset value.
Bit 2 SWPRST: SWPMI block reset
Set and reset by software.
0: does not reset the SWPMI block (default after reset)
1: resets the SWPMI block
Bit 1 CRSRST: Clock Recovery System reset
Set and reset by software.
0: does not reset CRS (default after reset)
1: resets CRS
Bit 0 Reserved, must be kept at reset value.

440/3353 RM0433 Rev 8

RM0433 Reset and Clock Control (RCC)

8.7.35 RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x098
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1RST
HRTIMRST

TIM17RST

TIM16RST

TIM15RST
SAI3RST

SAI2RST

SAI1RST

SPI5RST
Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USART6RST

USART1RST

TIM8RST

TIM1RST
SPI4RST

SPI1RST

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 HRTIMRST: HRTIM block reset
Set and reset by software.
0: does not reset the HRTIM block (default after reset)
1: resets the HRTIM block
Bit 28 DFSDM1RST: DFSDM1 block reset
Set and reset by software.
0: does not reset DFSDM1 block (default after reset)
1: resets DFSDM1 block
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 SAI3RST: SAI3 block reset
Set and reset by software.
0: does not reset the SAI3 block (default after reset)
1: resets the SAI3 block
Bit 23 SAI2RST: SAI2 block reset
Set and reset by software.
0: does not reset the SAI2 block (default after reset)
1: resets the SAI2 block
Bit 22 SAI1RST: SAI1 block reset
Set and reset by software.
0: does not reset the SAI1 (default after reset)
1: resets the SAI1
Bit 21 Reserved, must be kept at reset value.
Bit 20 SPI5RST: SPI5 block reset
Set and reset by software.
0: does not reset the SPI5 block (default after reset)
1: resets the SPI5 block
Bit 19 Reserved, must be kept at reset value.

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Reset and Clock Control (RCC) RM0433

Bit 18 TIM17RST: TIM17 block reset

Set and reset by software.
0: does not reset the TIM17 block (default after reset)
1: resets the TIM17 block
Bit 17 TIM16RST: TIM16 block reset
Set and reset by software.
0: does not reset the TIM16 block (default after reset)
1: resets the TIM16 block
Bit 16 TIM15RST: TIM15 block reset
Set and reset by software.
0: does not reset the TIM15 block (default after reset)
1: resets the TIM15 block
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 SPI4RST: SPI4 block reset
Set and reset by software.
0: does not reset the SPI4 block (default after reset)
1: resets the SPI4 block
Bit 12 SPI1RST: SPI1 block reset
Set and reset by software.
0: does not reset the SPI1 block (default after reset)
1: resets the SPI1 block
Bits 11:6 Reserved, must be kept at reset value.
Bit 5 USART6RST: USART6 block reset
Set and reset by software.
0: does not reset the USART6 block (default after reset)
1: resets the USART6 block
Bit 4 USART1RST: USART1 block reset
Set and reset by software.
0: does not reset the USART1 block (default after reset)
1: resets the USART1 block
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8RST: TIM8 block reset
Set and reset by software.
0: does not reset the TIM8 block (default after reset)
1: resets the TIM8 block
Bit 0 TIM1RST: TIM1 block reset
Set and reset by software.
0: does not reset the TIM1 block (default after reset)
1: resets the TIM1 block

442/3353 RM0433 Rev 8

RM0433 Reset and Clock Control (RCC)

8.7.36 RCC APB4 peripheral reset register (RCC_APB4RSTR)

Address offset: 0x09C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SAI4RST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPUART1RST
COMP12RST

SYSCFGRST
LPTIM5RST

LPTIM4RST

LPTIM3RST

LPTIM2RST
VREFRST

SPI6RST
I2C4RST
Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:22 Reserved, must be kept at reset value.
Bit 21 SAI4RST: SAI4 block reset
Set and reset by software.
0: does not reset the SAI4 block (default after reset)
1: resets the SAI4 block
Bits 20:16 Reserved, must be kept at reset value.
Bit 15 VREFRST: VREFBUF block reset
Set and reset by software.
0: does not reset the VREFBUF block (default after reset)
1: resets the VREFBUF block
Bit 14 COMP12RST: COMP12 Blocks Reset
Set and reset by software.
0: does not reset the COMP1 and 2 blocks (default after reset)
1: resets the COMP1 and 2 blocks
Bit 13 Reserved, must be kept at reset value.
Bit 12 LPTIM5RST: LPTIM5 block reset
Set and reset by software.
0: does not reset the LPTIM5 block (default after reset)
1: resets the LPTIM5 block
Bit 11 LPTIM4RST: LPTIM4 block reset
Set and reset by software.
0: does not reset the LPTIM4 block (default after reset)
1: resets the LPTIM4 block
Bit 10 LPTIM3RST: LPTIM3 block reset
Set and reset by software.
0: does not reset the LPTIM3 block (default after reset)
1: resets the LPTIM3 block

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Reset and Clock Control (RCC) RM0433

Bit 9 LPTIM2RST: LPTIM2 block reset

Set and reset by software.
0: does not reset the LPTIM2 block (default after reset)
1: resets the LPTIM2 block
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4RST: I2C4 block reset
Set and reset by software.
0: does not reset the I2C4 block (default after reset)
1: resets the I2C4 block
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6RST: SPI6 block reset
Set and reset by software.
0: does not reset the SPI6 block (default after reset)
1: resets the SPI6 block
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1RST: LPUART1 block reset
Set and reset by software.
0: does not reset the LPUART1 block (default after reset)
1: resets the LPUART1 block
Bit 2 Reserved, must be kept at reset value.
Bit 1 SYSCFGRST: SYSCFG block reset
Set and reset by software.
0: does not reset the SYSCFG block (default after reset)
1: resets the SYSCFG block
Bit 0 Reserved, must be kept at reset value.

444/3353 RM0433 Rev 8

RM0433 Reset and Clock Control (RCC)

8.7.37 RCC global control register (RCC_GCR)

Address offset: 0x0A0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WW1RSC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw1

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 WW1RSC: WWDG1 reset scope control
This bit can be set by software but is cleared by hardware during a system reset
In order to work properly, before enabling the WWDG1, this bit must be set to ‘1’.

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Reset and Clock Control (RCC) RM0433

8.7.38 RCC D3 Autonomous mode register (RCC_D3AMR)

The Autonomous mode allows providing the peripheral clocks to peripherals located in D3,
even if the CPU is in CStop mode. When a peripheral is enabled, and has its autonomous
bit enabled, it receives its peripheral clocks according to D3 domain state, if the CPU is in
CStop mode.
Address offset: 0x0A8
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKPRAMAMEN
SRAM4AMEN

ADC3AMEN

SAI4AMEN

CRCAMEN

RTCAMEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPUART1AMEN
COMP12AMEN

LPTIM5AMEN

LPTIM4AMEN

LPTIM3AMEN

LPTIM2AMEN

BDMAAMEN
VREFAMEN

SPI6AMEN
I2C4AMEN

Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 SRAM4AMEN: SRAM4 Autonomous mode enable
Set and reset by software.
0: SRAM4 clock is disabled when the CPU is in CStop (default after reset)
1: SRAM4 peripheral bus clock enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 28 BKPRAMAMEN: Backup RAM Autonomous mode enable
Set and reset by software.
0: Backup RAM clock is disabled when the CPU is in CStop (default after reset)
1: Backup RAM clock enabling is controlled by D3 domain state.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 27 Reserved, must be kept at reset value.
Bits 26:25 Reserved, must be kept at reset value.
Bit 24 ADC3AMEN: ADC3 Autonomous mode enable
Set and reset by software.
0: ADC3 peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: ADC3 peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 SAI4AMEN: SAI4 Autonomous mode enable
Set and reset by software.
0: SAI4 peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: SAI4 peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 20 Reserved, must be kept at reset value.

446/3353 RM0433 Rev 8

RM0433 Reset and Clock Control (RCC)

Bit 19 CRCAMEN: CRC Autonomous mode enable

Set and reset by software.
0: CRC peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: CRC peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bits 18:17 Reserved, must be kept at reset value.
Bit 16 RTCAMEN: RTC Autonomous mode enable
Set and reset by software.
0: RTC peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: RTC peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 15 VREFAMEN: VREF Autonomous mode enable
Set and reset by software.
0: VREF peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: VREF peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 14 COMP12AMEN: COMP12 Autonomous mode enable
Set and reset by software.
0: COMP12 peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: COMP12 peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 13 Reserved, must be kept at reset value.
Bit 12 LPTIM5AMEN: LPTIM5 Autonomous mode enable
Set and reset by software.
0: LPTIM5 peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: LPTIM5 peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 11 LPTIM4AMEN: LPTIM4 Autonomous mode enable
Set and reset by software.
0: LPTIM4 peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: LPTIM4 peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 10 LPTIM3AMEN: LPTIM3 Autonomous mode enable
Set and reset by software.
0: LPTIM3 peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: LPTIM3 peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 9 LPTIM2AMEN: LPTIM2 Autonomous mode enable
Set and reset by software.
0: LPTIM2 peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: LPTIM2 peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4AMEN: I2C4 Autonomous mode enable
Set and reset by software.
0: I2C4 peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: I2C4 peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information

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Bit 6 Reserved, must be kept at reset value.

Bit 5 SPI6AMEN: SPI6 Autonomous mode enable
Set and reset by software.
0: SPI6 peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: SPI6 peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1AMEN: LPUART1 Autonomous mode enable
Set and reset by software.
0: LPUART1 peripheral clocks are disabled when the CPU is in CStop (default after reset)
1: LPUART1 peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 BDMAAMEN: BDMA and DMAMUX Autonomous mode enable
Set and reset by software.
0: BDMA and DMAMUX peripheral clocks are disabled when the CPU is in CStop (default after
reset)
1: BDMA and DMAMUX peripheral clocks enabled when D3 domain is in DRun.
Refer to Section 8.5.11: Peripheral clock gating control for additional information

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RM0433 Reset and Clock Control (RCC)

8.7.39 RCC reset status register (RCC_RSR)

This register can be accessed via two different offset address.

Table 65. RCC_RSR address offset and reset value

Register Name Address Offset Reset Value

RCC_RSR 0x0D0
0x00FE 0000 (1)
RCC_C1_RSR 0x130
1. Reset by power-on reset only

Access: 0 ≤ wait state ≤ 7, word, half-word and byte access. Wait states are inserted in case
of successive accesses to this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WWDG1RSTF
LPWRRSTF

IWDG1RSTF

PORRSTF

BORRSTF

CPURSTF
SFTRSTF

PINRSTF

D2RSTF

D1RSTF

RMVF
Res. Res. Res. Res. Res.

r r r r r r r r r r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bit 31 Reserved, must be kept at reset value.

Bit 30 LPWRRSTF: Reset due to illegal D1 DStandby or CPU CStop flag (1)
Reset by software by writing the RMVF bit.
Set by hardware when D1 domain goes erroneously in DStandby or when CPU goes erroneously in
CStop.
0: No illegal reset occurred (default after power-on reset)
1: Illegal D1 DStandby or CPU CStop reset occurred
Bit 29 Reserved, must be kept at reset value.
Bit 28 WWDG1RSTF: Window Watchdog reset flag (1)
Reset by software by writing the RMVF bit.
Set by hardware when a window watchdog reset occurs.
0: No window watchdog reset occurred from WWDG1 (default after power-on reset)
1: window watchdog reset occurred from WWDG1
Bit 27 Reserved, must be kept at reset value.
Bit 26 IWDG1RSTF: Independent Watchdog reset flag (1)
Reset by software by writing the RMVF bit.
Set by hardware when an independent watchdog reset occurs.
0: No independent watchdog reset occurred (default after power-on reset)
1: Independent watchdog reset occurred
Bit 25 Reserved, must be kept at reset value.

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Bit 24 SFTRSTF: System reset from CPU reset flag (1)

Reset by software by writing the RMVF bit.
Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by
writing SYSRESETREQ bit of AIRCR register of the CM7.
0: No CPU software reset occurred (default after power-on reset)
1: A system reset has been generated by the CPU
Bit 23 PORRSTF: POR/PDR reset flag (1)
Reset by software by writing the RMVF bit.
Set by hardware when a POR/PDR reset occurs.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred (default after power-on reset)
Bit 22 PINRSTF: Pin reset flag (NRST) (1)
Reset by software by writing the RMVF bit.
Set by hardware when a reset from pin occurs.
0: No reset from pin occurred
1: Reset from pin occurred (default after power-on reset)
Bit 21 BORRSTF: BOR reset flag (1)
Reset by software by writing the RMVF bit.
Set by hardware when a BOR reset occurs (pwr_bor_rst).
0: No BOR reset occurred
1: BOR reset occurred (default after power-on reset)
Bit 20 D2RSTF: D2 domain power switch reset flag (1)
Reset by software by writing the RMVF bit.
Set by hardware when a D2 domain exits from DStandby or after of power-on reset. Refer to
Table 56 for details.
0: No D2 domain power switch reset occurred
1: A D2 domain power switch (ePOD2) reset occurred (default after power-on reset)
Bit 19 D1RSTF: D1 domain power switch reset flag (1)
Reset by software by writing the RMVF bit.
Set by hardware when a D1 domain exits from DStandby or after of power-on reset. Refer to
Table 56 for details.
0: No D1 domain power switch reset occurred
1: A D1 domain power switch (ePOD1) reset occurred (default after power-on reset)
Bit 18 Reserved, must be kept at reset value.
Bit 17 CPURSTF: CPU reset flag (1)
Reset by software by writing the RMVF bit.
Set by hardware every time a CPU reset occurs.
0: No CPU reset occurred
1: A CPU reset occurred (default after power-on reset)
Bit 16 RMVF: Remove reset flag
Set and reset by software to reset the value of the reset flags.
0: Reset of the reset flags not activated (default after power-on reset)
1: Reset the value of the reset flags
Bits 15:0 Reserved, must be kept at reset value.
1. Refer to Table 56: Reset source identification (RCC_RSR) for details on flag behavior.

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RM0433 Reset and Clock Control (RCC)

8.7.40 RCC AHB3 clock register (RCC_AHB3ENR)

This register can be accessed via two different offset address.

Table 66. RCC_AHB3ENR address offset and reset value

Register Name Address Offset Reset Value

RCC_AHB3ENR 0x0D4
0x0000 0000
RCC_C1_AHB3ENR 0x134

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SDMMC1EN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

JPGDECEN

DMA2DEN

MDMAEN
QSPIEN

FMCEN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 SDMMC1EN: SDMMC1 and SDMMC1 Delay Clock Enable
Set and reset by software.
0: SDMMC1 and SDMMC1 Delay clock disabled (default after reset)
1: SDMMC1 and SDMMC1 Delay clock enabled
Bit 15 Reserved, must be kept at reset value.
Bit 14 QSPIEN: QUADSPI and QUADSPI Delay Clock Enable
Set and reset by software.
0: QUADSPI and QUADSPI Delay clock disabled (default after reset)
1: QUADSPI and QUADSPI Delay clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 FMCEN: FMC Peripheral Clocks Enable
Set and reset by software.
0: FMC peripheral clocks disabled (default after reset)
1: FMC peripheral clocks enabled
The peripheral clocks of the FMC are: the kernel clock selected by FMCSEL and provided to
fmc_ker_ck input, and the rcc_hclk3 bus interface clock.
Bits 11:6 Reserved, must be kept at reset value.
Bit 5 JPGDECEN: JPGDEC Peripheral Clock Enable
Set and reset by software.
0: JPGDEC peripheral clock disabled (default after reset)
1: JPGDEC peripheral clock enabled

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Bit 4 DMA2DEN: DMA2D Peripheral Clock Enable

Set and reset by software.
0: DMA2D peripheral clock disabled (default after reset)
1: DMA2D peripheral clock enabled
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 MDMAEN: MDMA Peripheral Clock Enable
Set and reset by software.
0: MDMA peripheral clock disabled (default after reset)
1: MDMA peripheral clock enabled

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RM0433 Reset and Clock Control (RCC)

8.7.41 RCC AHB1 clock register (RCC_AHB1ENR)

This register can be accessed via two different offset address.

Table 67. RCC_AHB1ENR address offset and reset value

Register Name Address Offset Reset Value

RCC_AHB1ENR 0x0D8
0x0000 0000
RCC_C1_AHB1ENR 0x138

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USB2OTGHSULPIEN

USB1OTGHSULPIEN
USB2OTGHSEN

USB1OTGHSEN

ETH1RXEN

ETH1TXEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETH1MACEN

ADC12EN

DMA2EN

DMA1EN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 USB2OTGHSULPIEN: Enable USB_PHY2 clocks
Set and reset by software.
0: USB2ULPI PHY clocks disabled (default after reset)
1: USB2ULPI PHY clocks enabled
Bit 27 USB2OTGHSEN: USB2OTG (OTG_HS2) Peripheral Clocks Enable
Set and reset by software.
0: USB2OTG peripheral clocks disabled (default after reset)
1: USB2OTG peripheral clocks enabled
The peripheral clocks of the USB2OTG are: the kernel clock selected by USBSEL and the
rcc_hclk1 bus interface clock.
Bit 26 USB1OTGHSULPIEN: USB_PHY1 Clocks Enable
Set and reset by software.
0: USB1ULPI PHY clocks disabled (default after reset)
1: USB1ULPI PHY clocks enabled
Bit 25 USB1OTGHSEN: USB1OTG (OTG_HS1) Peripheral Clocks Enable
Set and reset by software.
0: USB1OTG peripheral clocks disabled (default after reset)
1: USB1OTG peripheral clocks enabled
The peripheral clocks of the USB1OTG are: the kernel clock selected by USBSEL and the
rcc_hclk1 bus interface clock.
Bits 24:18 Reserved, must be kept at reset value.

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Bit 17 ETH1RXEN: Ethernet Reception Clock Enable

Set and reset by software.
0: Ethernet Reception clock disabled (default after reset)
1: Ethernet Reception clock enabled
Bit 16 ETH1TXEN: Ethernet Transmission Clock Enable
Set and reset by software.
0: Ethernet Transmission clock disabled (default after reset)
1: Ethernet Transmission clock enabled
Bit 15 ETH1MACEN: Ethernet MAC bus interface Clock Enable
Set and reset by software.
0: Ethernet MAC bus interface clock disabled (default after reset)
1: Ethernet MAC bus interface clock enabled
Bits 14:6 Reserved, must be kept at reset value.
Bit 5 ADC12EN: ADC1/2 Peripheral Clocks Enable
Set and reset by software.
0: ADC1 and 2 peripheral clocks disabled (default after reset)
1: ADC1 and 2 peripheral clocks enabled
The peripheral clocks of the ADC1 and 2 are: the kernel clock selected by ADCSEL and provided to
adc_ker_ck_input, and the rcc_hclk1 bus interface clock.
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 DMA2EN: DMA2 Clock Enable
Set and reset by software.
0: DMA2 clock disabled (default after reset)
1: DMA2 clock enabled
Bit 0 DMA1EN: DMA1 Clock Enable
Set and reset by software.
0: DMA1 clock disabled (default after reset)
1: DMA1 clock enabled

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RM0433 Reset and Clock Control (RCC)

8.7.42 RCC AHB2 clock register (RCC_AHB2ENR)

This register can be accessed via two different offset address.

Table 68. RCC_AHB2ENR address offset and reset value

Register Name Address Offset Reset Value

RCC_AHB2ENR 0x0DC
0x0000 0000
RCC_C1_AHB2ENR 0x13C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRAM3EN

SRAM2EN

SRAM1EN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMC2EN

CRYPTEN
HASHEN

DCMIEN
RNGEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bit 31 SRAM3EN: SRAM3 block enable

Set and reset by software.
When set, this bit indicates that the SRAM3 is allocated by the CPU. It causes the D2 domain to
take into account also the CPU operation modes, i.e. keeping D2 domain in DRun when the CPU is
in CRun.
0: SRAM3 interface clock is disabled. (default after reset)
1: SRAM3 interface clock is enabled.
Bit 30 SRAM2EN: SRAM2 block enable
Set and reset by software.
When set, this bit indicates that the SRAM2 is allocated by the CPU. It causes the D2 domain to
take into account also the CPU operation modes, i.e. keeping D2 domain in DRun when the CPU is
in CRun.
0: SRAM2 interface clock is disabled. (default after reset)
1: SRAM2 interface clock is enabled.
Bit 29 SRAM1EN: SRAM1 block enable
Set and reset by software.
When set, this bit indicates that the SRAM1 is allocated by the CPU. It causes the D2 domain to
take into account also the CPU operation modes, i.e. keeping D2 domain in DRun when the CPU is
in CRun.
0: SRAM1 interface clock is disabled. (default after reset)
1: SRAM1 interface clock is enabled.
Bits 28:10 Reserved, must be kept at reset value.
Bit 9 SDMMC2EN: SDMMC2 and SDMMC2 delay clock enable
Set and reset by software.
0: SDMMC2 and SDMMC2 Delay clock disabled (default after reset)
1: SDMMC2 and SDMMC2 Delay clock enabled
Bits 8:7 Reserved, must be kept at reset value.

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Bit 6 RNGEN: RNG peripheral clocks enable

Set and reset by software.
0: RNG peripheral clocks disabled (default after reset)
1: RNG peripheral clocks enabled:
The peripheral clocks of the RNG are: the kernel clock selected by RNGSEL and provided to
rng_ker_ck input, and the rcc_hclk2 bus interface clock.
Bit 5 HASHEN: HASH peripheral clock enable
Set and reset by software.
0: HASH peripheral clock disabled (default after reset)
1: HASH peripheral clock enabled
Bit 4 CRYPTEN: CRYPT peripheral clock enable
Set and reset by software.
0: CRYPT peripheral clock disabled (default after reset)
1: CRYPT peripheral clock enabled
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DCMIEN: DCMI peripheral clock enable
Set and reset by software.
0: DCMI peripheral clock disabled (default after reset)
1: DCMI peripheral clock enabled

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RM0433 Reset and Clock Control (RCC)

8.7.43 RCC AHB4 clock register (RCC_AHB4ENR)

This register can be accessed via two different offset address.

Table 69. RCC_AHB4ENR address offset and reset value

Register Name Address Offset Reset Value

RCC_AHB4ENR 0x0E0
0x0000 0000
RCC_C1_AHB4ENR 0x140

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKPRAMEN

HSEMEN

BDMAEN
ADC3EN

CRCEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPIOGEN
GPIOHEN

GPIODEN

GPIOCEN
GPIOKEN

GPIOEEN

GPIOBEN

GPIOAEN
GPIOFEN
GPIOJEN

GPIOIEN

Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 BKPRAMEN: Backup RAM Clock Enable
Set and reset by software.
0: Backup RAM clock disabled (default after reset)
1: Backup RAM clock enabled
Bits 27:26 Reserved, must be kept at reset value.
Bit 25 HSEMEN: HSEM peripheral clock enable
Set and reset by software.
0: HSEM peripheral clock disabled (default after reset)
1: HSEM peripheral clock enabled
Bit 24 ADC3EN: ADC3 Peripheral Clocks Enable
Set and reset by software.
0: ADC3 peripheral clocks disabled (default after reset)
1: ADC3 peripheral clocks enabled
The peripheral clocks of the ADC3 are: the kernel clock selected by ADCSEL and provided to
adc_ker_ck_input, and the rcc_hclk4 bus interface clock.
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 BDMAEN: BDMA and DMAMUX2 Clock Enable
Set and reset by software.
0: BDMA and DMAMUX2 clock disabled (default after reset)
1: BDMA and DMAMUX2 clock enabled
Bit 20 Reserved, must be kept at reset value.

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Bit 19 CRCEN: CRC peripheral clock enable

Set and reset by software.
0: CRC peripheral clock disabled (default after reset)
1: CRC peripheral clock enabled
Bits 18:11 Reserved, must be kept at reset value.
Bit 10 GPIOKEN: GPIOK peripheral clock enable
Set and reset by software.
0: GPIOK peripheral clock disabled (default after reset)
1: GPIOK peripheral clock enabled
Bit 9 GPIOJEN: GPIOJ peripheral clock enable
Set and reset by software.
0: GPIOJ peripheral clock disabled (default after reset)
1: GPIOJ peripheral clock enabled
Bit 8 GPIOIEN: GPIOI peripheral clock enable
Set and reset by software.
0: GPIOI peripheral clock disabled (default after reset)
1: GPIOI peripheral clock enabled
Bit 7 GPIOHEN: GPIOH peripheral clock enable
Set and reset by software.
0: GPIOH peripheral clock disabled (default after reset)
1: GPIOH peripheral clock enabled
Bit 6 GPIOGEN: GPIOG peripheral clock enable
Set and reset by software.
0: GPIOG peripheral clock disabled (default after reset)
1: GPIOG peripheral clock enabled
Bit 5 GPIOFEN: GPIOF peripheral clock enable
Set and reset by software.
0: GPIOF peripheral clock disabled (default after reset)
1: GPIOF peripheral clock enabled
Bit 4 GPIOEEN: GPIOE peripheral clock enable
Set and reset by software.
0: GPIOE peripheral clock disabled (default after reset)
1: GPIOE peripheral clock enabled
Bit 3 GPIODEN: GPIOD peripheral clock enable
Set and reset by software.
0: GPIOD peripheral clock disabled (default after reset)
1: GPIOD peripheral clock enabled

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Bit 2 GPIOCEN: GPIOC peripheral clock enable

Set and reset by software.
0: GPIOC peripheral clock disabled (default after reset)
1: GPIOC peripheral clock enabled
Bit 1 GPIOBEN: GPIOB peripheral clock enable
Set and reset by software.
0: GPIOB peripheral clock disabled (default after reset)
1: GPIOB peripheral clock enabled
Bit 0 GPIOAEN: GPIOA peripheral clock enable
Set and reset by software.
0: GPIOA peripheral clock disabled (default after reset)
1: GPIOA peripheral clock enabled

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8.7.44 RCC APB3 clock register (RCC_APB3ENR)

This register can be accessed via two different offset address.

Table 70. RCC_APB3ENR address offset and reset value

Register Name Address Offset Reset Value

RCC_APB3ENR 0x0E4
0x0000 0000
RCC_C1_APB3ENR 0x144

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WWDG1EN

LTDCEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rs rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 WWDG1EN: WWDG1 Clock Enable
Set by software, and reset by hardware when a system reset occurs.
Note that in order to work properly, before enabling the WWDG1, the bit WW1RSC must be set to
‘1’.
0: WWDG1 peripheral clock disable (default after reset)
1: WWDG1 peripheral clock enabled
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 LTDCEN: LTDC peripheral clock enable
Provides the pixel clock (ltdc_ker_ck) to the LTDC block.
Set and reset by software.
0: LTDC peripheral clock disabled (default after reset)
1: LTDC peripheral clock provided to the LTDC block
Bits 2:0 Reserved, must be kept at reset value.

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RM0433 Reset and Clock Control (RCC)

8.7.45 RCC APB1 clock register (RCC_APB1LENR)

This register can be accessed via two different offset address.

Table 71. RCC_APB1ENR address offset and reset value

Register Name Address Offset Reset Value

RCC_APB1LENR 0x0E8
0x0000 0000
RCC_C1_APB1LENR 0x148

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPDIFRXEN
USART3EN

USART2EN
UART8EN

UART7EN

UART5EN

UART4EN
DAC12EN

CECEN

I2C3EN

I2C2EN

I2C1EN
Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM1EN

TIM14EN

TIM13EN

TIM12EN

TIM7EN

TIM6EN

TIM5EN

TIM4EN

TIM3EN

TIM2EN
SPI3EN

SPI2EN

Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 UART8EN: UART8 Peripheral Clocks Enable

Set and reset by software.
0: UART8 peripheral clocks disable (default after reset)
1: UART8 peripheral clocks enabled
The peripheral clocks of the UART8 are: the kernel clock selected by USART234578SEL and
provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 30 UART7EN: UART7 Peripheral Clocks Enable
Set and reset by software.
0: UART7 peripheral clocks disable (default after reset)
1: UART7 peripheral clocks enabled
The peripheral clocks of the UART7 are: the kernel clock selected by USART234578SEL and
provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 29 DAC12EN: DAC1 and 2 peripheral clock enable
Set and reset by software.
0: DAC1 and 2 peripheral clock disable (default after reset)
1: DAC1 and 2 peripheral clock enabled
Bit 28 Reserved, must be kept at reset value.
Bit 27 CECEN: HDMI-CEC peripheral clock enable
Set and reset by software.
0: HDMI-CEC peripheral clock disable (default after reset)
1: HDMI-CEC peripheral clock enabled
The peripheral clocks of the HDMI-CEC are: the kernel clock selected by CECSEL and provided to
cec_ker_ck input, and the rcc_pclk1 bus interface clock.
Bits 26:24 Reserved, must be kept at reset value.

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Bit 23 I2C3EN: I2C3 Peripheral Clocks Enable

Set and reset by software.
0: I2C3 peripheral clocks disable (default after reset)
1: I2C3 peripheral clocks enabled
The peripheral clocks of the I2C3 are: the kernel clock selected by I2C123SEL and provided to
i2c_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 22 I2C2EN: I2C2 Peripheral Clocks Enable
Set and reset by software.
0: I2C2 peripheral clocks disable (default after reset)
1: I2C2 peripheral clocks enabled
The peripheral clocks of the I2C2 are: the kernel clock selected by I2C123SEL and provided to
i2c_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 21 I2C1EN: I2C1 Peripheral Clocks Enable
Set and reset by software.
0: I2C1 peripheral clocks disable (default after reset)
1: I2C1 peripheral clocks enabled
The peripheral clocks of the I2C1 are: the kernel clock selected by I2C123SEL and provided to
i2c_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 20 UART5EN: UART5 Peripheral Clocks Enable
Set and reset by software.
0: UART5 peripheral clocks disable (default after reset)
1: UART5 peripheral clocks enabled
The peripheral clocks of the UART5 are: the kernel clock selected by USART234578SEL and
provided to uart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 19 UART4EN: UART4 Peripheral Clocks Enable
Set and reset by software.
0: UART4 peripheral clocks disable (default after reset)
1: UART4 peripheral clocks enabled
The peripheral clocks of the UART4 are: the kernel clock selected by USART234578SEL and
provided to uart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 18 USART3EN: USART3 Peripheral Clocks Enable
Set and reset by software.
0: USART3 peripheral clocks disable (default after reset)
1: USART3 peripheral clocks enabled
The peripheral clocks of the USART3 are: the kernel clock selected by USART234578SEL and
provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 17 USART2EN: USART2 Peripheral Clocks Enable
Set and reset by software.
0: USART2 peripheral clocks disable (default after reset)
1: USART2 peripheral clocks enabled
The peripheral clocks of the USART2 are: the kernel clock selected by USART234578SEL and
provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 16 SPDIFRXEN: SPDIFRX Peripheral Clocks Enable
Set and reset by software.
0: SPDIFRX peripheral clocks disable (default after reset)
1: SPDIFRX peripheral clocks enabled
The peripheral clocks of the SPDIFRX are: the kernel clock selected by SPDIFSEL and provided to
spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock.

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Bit 15 SPI3EN: SPI3 Peripheral Clocks Enable

Set and reset by software.
0: SPI3 peripheral clocks disable (default after reset)
1: SPI3 peripheral clocks enabled
The peripheral clocks of the SPI3 are: the kernel clock selected by I2S123SRC and provided to
spi_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 14 SPI2EN: SPI2 Peripheral Clocks Enable
Set and reset by software.
0: SPI2 peripheral clocks disable (default after reset)
1: SPI2 peripheral clocks enabled
The peripheral clocks of the SPI2 are: the kernel clock selected by I2S123SRC and provided to
spi_ker_ck input, and the rcc_pclk1 bus interface clock.
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 LPTIM1EN: LPTIM1 Peripheral Clocks Enable
Set and reset by software.
0: LPTIM1 peripheral clocks disable (default after reset)
1: LPTIM1 peripheral clocks enabled
The peripheral clocks of the LPTIM1 are: the kernel clock selected by LPTIM1SEL and provided to
lptim_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 8 TIM14EN: TIM14 peripheral clock enable
Set and reset by software.
0: TIM14 peripheral clock disable (default after reset)
1: TIM14 peripheral clock enabled
Bit 7 TIM13EN: TIM13 peripheral clock enable
Set and reset by software.
0: TIM13 peripheral clock disable (default after reset)
1: TIM13 peripheral clock enabled
Bit 6 TIM12EN: TIM12 peripheral clock enable
Set and reset by software.
0: TIM12 peripheral clock disable (default after reset)
1: TIM12 peripheral clock enabled
Bit 5 TIM7EN: TIM7 peripheral clock enable
Set and reset by software.
0: TIM7 peripheral clock disable (default after reset)
1: TIM7 peripheral clock enabled
Bit 4 TIM6EN: TIM6 peripheral clock enable
Set and reset by software.
0: TIM6 peripheral clock disable (default after reset)
1: TIM6 peripheral clock enabled
Bit 3 TIM5EN: TIM5 peripheral clock enable
Set and reset by software.
0: TIM5 peripheral clock disable (default after reset)
1: TIM5 peripheral clock enabled

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Bit 2 TIM4EN: TIM4 peripheral clock enable

Set and reset by software.
0: TIM4 peripheral clock disable (default after reset)
1: TIM4 peripheral clock enabled
Bit 1 TIM3EN: TIM3 peripheral clock enable
Set and reset by software.
0: TIM3 peripheral clock disable (default after reset)
1: TIM3 peripheral clock enabled
Bit 0 TIM2EN: TIM2 peripheral clock enable
Set and reset by software.
0: TIM2 peripheral clock disable (default after reset)
1: TIM2 peripheral clock enabled

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8.7.46 RCC APB1 clock register (RCC_APB1HENR)

This register can be accessed via two different offset address.

Table 72. RCC_APB1ENR address offset and reset value

Register Name Address Offset Reset Value

RCC_APB1HENR 0x0EC
0x0000 0000
RCC_C1_APB1HENR 0x14C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPAMPEN
FDCANEN

MDIOSEN

SWPEN

CRSEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 FDCANEN: FDCAN Peripheral Clocks Enable
Set and reset by software.
0: FDCAN peripheral clocks disable (default after reset)
1: FDCAN peripheral clocks enabled:
The peripheral clocks of the FDCAN are: the kernel clock selected by FDCANSEL and provided to
fdcan_ker_ck input, and the rcc_pclk1 bus interface clock.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSEN: MDIOS peripheral clock enable
Set and reset by software.
0: MDIOS peripheral clock disable (default after reset)
1: MDIOS peripheral clock enabled
Bit 4 OPAMPEN: OPAMP peripheral clock enable
Set and reset by software.
0: OPAMP peripheral clock disable (default after reset)
1: OPAMP peripheral clock enabled
Bit 3 Reserved, must be kept at reset value.

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Bit 2 SWPEN: SWPMI Peripheral Clocks Enable

Set and reset by software.
0: SWPMI peripheral clocks disable (default after reset)
1: SWPMI peripheral clocks enabled:
The peripheral clocks of the SWPMI are: the kernel clock selected by SWPSEL and provided to
swpmi_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 1 CRSEN: Clock Recovery System peripheral clock enable
Set and reset by software.
0: CRS peripheral clock disable (default after reset)
1: CRS peripheral clock enabled
Bit 0 Reserved, must be kept at reset value.

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8.7.47 RCC APB2 clock register (RCC_APB2ENR)

This register can be accessed via two different offset address.

Table 73. RCC_APB2ENR address offset and reset value

Register Name Address Offset Reset Value

RCC_APB2ENR 0x0F0
0x0000 0000
RCC_C1_APB2ENR 0x150

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1EN
HRTIMEN

TIM17EN

TIM16EN

TIM15EN
SAI3EN

SAI2EN

SAI1EN

SPI5EN
Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USART6EN

USART1EN

TIM8EN

TIM1EN
SPI4EN

SPI1EN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 HRTIMEN: HRTIM peripheral clock enable
Set and reset by software.
0: HRTIM peripheral clock disabled (default after reset)
1: HRTIM peripheral clock enabled
Bit 28 DFSDM1EN: DFSDM1 Peripheral Clocks Enable
Set and reset by software.
0: DFSDM1 peripheral clocks disabled (default after reset)
1: DFSDM1 peripheral clocks enabled
DFSDM1 peripheral clocks are: the kernel clocks selected by SAI1SEL and DFSDM1SEL and
provided to Aclk and clk inputs respectively, and the rcc_pclk2 bus interface clock.
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 SAI3EN: SAI3 Peripheral Clocks Enable
Set and reset by software.
0: SAI3 peripheral clocks disabled (default after reset)
1: SAI3 peripheral clocks enabled
The peripheral clocks of the SAI3 are: the kernel clock selected by SAI23SEL and provided to
sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.
Bit 23 SAI2EN: SAI2 Peripheral Clocks Enable
Set and reset by software.
0: SAI2 peripheral clocks disabled (default after reset)
1: SAI2 peripheral clocks enabled
The peripheral clocks of the SAI2 are: the kernel clock selected by SAI23SEL and provided to
sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.

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Bit 22 SAI1EN: SAI1 Peripheral Clocks Enable

Set and reset by software.
0: SAI1 peripheral clocks disabled (default after reset)
1: SAI1 peripheral clocks enabled:
The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to
sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.
Bit 21 Reserved, must be kept at reset value.
Bit 20 SPI5EN: SPI5 Peripheral Clocks Enable
Set and reset by software.
0: SPI5 peripheral clocks disabled (default after reset)
1: SPI5 peripheral clocks enabled:
The peripheral clocks of the SPI5 are: the kernel clock selected by SPI45SEL and provided to
spi_ker_ck input, and the rcc_pclk2 bus interface clock.
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM17 peripheral clock enable
Set and reset by software.
0: TIM17 peripheral clock disabled (default after reset)
1: TIM17 peripheral clock enabled
Bit 17 TIM16EN: TIM16 peripheral clock enable
Set and reset by software.
0: TIM16 peripheral clock disabled (default after reset)
1: TIM16 peripheral clock enabled
Bit 16 TIM15EN: TIM15 peripheral clock enable
Set and reset by software.
0: TIM15 peripheral clock disabled (default after reset)
1: TIM15 peripheral clock enabled
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 SPI4EN: SPI4 Peripheral Clocks Enable
Set and reset by software.
0: SPI4 peripheral clocks disabled (default after reset)
1: SPI4 peripheral clocks enabled:
The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to
spi_ker_ck input, and the rcc_pclk2 bus interface clock.
Bit 12 SPI1EN: SPI1 Peripheral Clocks Enable
Set and reset by software.
0: SPI1 peripheral clocks disabled (default after reset)
1: SPI1 peripheral clocks enabled:
The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to
spi_ker_ck input, and the rcc_pclk2 bus interface clock.
Bits 11:6 Reserved, must be kept at reset value.
Bit 5 USART6EN: USART6 Peripheral Clocks Enable
Set and reset by software.
0: USART6 peripheral clocks disabled (default after reset)
1: USART6 peripheral clocks enabled:
The peripheral clocks of the USART6 are: the kernel clock selected by USART16SEL and provided
to usart_ker_ck input, and the rcc_pclk2 bus interface clock.

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Bit 4 USART1EN: USART1 Peripheral Clocks Enable

Set and reset by software.
0: USART1 peripheral clocks disabled (default after reset)
1: USART1 peripheral clocks enabled:
The peripheral clocks of the USART1 are: the kernel clock selected by USART16SEL and provided
to usart_ker_ck input, and the rcc_pclk2 bus interface clock.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8EN: TIM8 peripheral clock enable
Set and reset by software.
0: TIM8 peripheral clock disabled (default after reset)
1: TIM8 peripheral clock enabled
Bit 0 TIM1EN: TIM1 peripheral clock enable
Set and reset by software.
0: TIM1 peripheral clock disabled (default after reset)
1: TIM1 peripheral clock enabled

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8.7.48 RCC APB4 clock register (RCC_APB4ENR)

This register can be accessed via two different offset address.

Table 74. RCC_APB4ENR address offset and reset value

Register Name Address Offset Reset Value

RCC_APB4ENR 0x0F4
0x0001 0000
RCC_C1_APB4ENR 0x154

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTCAPBEN
SAI4EN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPUART1EN
COMP12EN

SYSCFGEN
LPTIM5EN

LPTIM4EN

LPTIM3EN

LPTIM2EN
VREFEN

SPI6EN
I2C4EN

Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:22 Reserved, must be kept at reset value.
Bit 21 SAI4EN: SAI4 Peripheral Clocks Enable
Set and reset by software.
0: SAI4 peripheral clocks disabled (default after reset)
1: SAI4 peripheral clocks enabled
The peripheral clocks of the SAI4 are: the kernel clocks selected by SAI4ASEL and SAI4BSEL, and
provided to sai_a_ker_ck and sai_b_ker_ck inputs respectively, and the rcc_pclk4 bus interface
clock.
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 RTCAPBEN: RTC APB Clock Enable
Set and reset by software.
0: The register clock interface of the RTC (APB) is disabled
1: The register clock interface of the RTC (APB) is enabled (default after reset)
Bit 15 VREFEN: VREFBUF peripheral clock enable
Set and reset by software.
0: VREFBUF peripheral clock disabled (default after reset)
1: VREFBUF peripheral clock enabled
Bit 14 COMP12EN: COMP1/2 peripheral clock enable
Set and reset by software.
0: COMP1/2 peripheral clock disabled (default after reset)
1: COMP1/2 peripheral clock enabled
Bit 13 Reserved, must be kept at reset value.

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Bit 12 LPTIM5EN: LPTIM5 Peripheral Clocks Enable

Set and reset by software.
0: LPTIM5 peripheral clocks disabled (default after reset)
1: LPTIM5 peripheral clocks enabled
The peripheral clocks of the LPTIM5 are: the kernel clock selected by LPTIM345SEL and provided
to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 11 LPTIM4EN: LPTIM4 Peripheral Clocks Enable
Set and reset by software.
0: LPTIM4 peripheral clocks disabled (default after reset)
1: LPTIM4 peripheral clocks enabled
The peripheral clocks of the LPTIM4 are: the kernel clock selected by LPTIM345SEL and provided
to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 10 LPTIM3EN: LPTIM3 Peripheral Clocks Enable
Set and reset by software.
0: LPTIM3 peripheral clocks disabled (default after reset)
1: LPTIM3 peripheral clocks enabled
The peripheral clocks of the LPTIM3 are: the kernel clock selected by LPTIM345SEL and provided
to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 9 LPTIM2EN: LPTIM2 Peripheral Clocks Enable
Set and reset by software.
0: LPTIM2 peripheral clocks disabled (default after reset)
1: LPTIM2 peripheral clocks enabled
The peripheral clocks of the LPTIM2 are: the kernel clock selected by LPTIM2SEL and provided to
lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4EN: I2C4 Peripheral Clocks Enable
Set and reset by software.
0: I2C4 peripheral clocks disabled (default after reset)
1: I2C4 peripheral clocks enabled
The peripheral clocks of the I2C4 are: the kernel clock selected by I2C4SEL and provided to
i2c_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6EN: SPI6 Peripheral Clocks Enable
Set and reset by software.
0: SPI6 peripheral clocks disabled (default after reset)
1: SPI6 peripheral clocks enabled
The peripheral clocks of the SPI6 are: the kernel clock selected by SPI6SEL and provided to
spi_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1EN: LPUART1 Peripheral Clocks Enable
Set and reset by software.
0: LPUART1 peripheral clocks disabled (default after reset)
1: LPUART1 peripheral clocks enabled
The peripheral clocks of the LPUART1 are: the kernel clock selected by LPUART1SEL and
provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock.

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Bit 2 Reserved, must be kept at reset value.

Bit 1 SYSCFGEN: SYSCFG peripheral clock enable
Set and reset by software.
0: SYSCFG peripheral clock disabled (default after reset)
1: SYSCFG peripheral clock enabled
Bit 0 Reserved, must be kept at reset value.

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8.7.49 RCC AHB3 Sleep clock register (RCC_AHB3LPENR)

This register can be accessed via two different offset address.

Table 75. RCC_AHB3LPENR address offset and reset value

Register Name Address Offset Reset Value

RCC_AHB3LPENR 0x0FC
0xF001 5131
RCC_C1_AHB3LPENR 0x15C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXISRAMLPEN

SDMMC1LPEN
DTCM2LPEN

DTCM1LPEN
ITCMLPEN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

JPGDECLPEN

DMA2DLPEN
FLASHLPEN

MDMALPEN
QSPILPEN

FMCLPEN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw

Bit 31 AXISRAMLPEN: AXISRAM Block Clock Enable During CSleep mode

Set and reset by software.
0: AXISRAM interface clock disabled during CSleep mode
1: AXISRAM interface clock enabled during CSleep mode (default after reset)
Bit 30 ITCMLPEN: D1ITCM Block Clock Enable During CSleep mode
Set and reset by software.
0: D1 ITCM interface clock disabled during CSleep mode
1: D1 ITCM interface clock enabled during CSleep mode (default after reset)
Bit 29 DTCM2LPEN: D1 DTCM2 Block Clock Enable During CSleep mode
Set and reset by software.
0: D1 DTCM2 interface clock disabled during CSleep mode
1: D1 DTCM2 interface clock enabled during CSleep mode (default after reset)
Bit 28 D1DTCM1LPEN: D1DTCM1 Block Clock Enable During CSleep mode
Set and reset by software.
0: D1DTCM1 interface clock disabled during CSleep mode
1: D1DTCM1 interface clock enabled during CSleep mode (default after reset)
Bits 27:17 Reserved, must be kept at reset value.
Bit 16 SDMMC1LPEN: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode
Set and reset by software.
0: SDMMC1 and SDMMC1 Delay clock disabled during CSleep mode
1: SDMMC1 and SDMMC1 Delay clock enabled during CSleep mode (default after reset)
Bit 15 Reserved, must be kept at reset value.

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Bit 14 QSPILPEN: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode
Set and reset by software.
0: QUADSPI and QUADSPI Delay clock disabled during CSleep mode
1: QUADSPI and QUADSPI Delay clock enabled during CSleep mode (default after reset)
Bit 13 Reserved, must be kept at reset value.
Bit 12 FMCLPEN: FMC Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: FMC peripheral clocks disabled during CSleep mode
1: FMC peripheral clocks enabled during CSleep mode (default after reset):
The peripheral clocks of the FMC are: the kernel clock selected by FMCSEL and provided to
fmc_ker_ck input, and the rcc_hclk3 bus interface clock.
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHLPEN: Flash interface Clock Enable During CSleep Mode
Set and reset by software.
0: Flash interface clock disabled during CSleep mode
1: Flash interface clock enabled during CSleep mode (default after reset)
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 JPGDECLPEN: JPGDEC Clock Enable During CSleep Mode
Set and reset by software.
0: JPGDEC peripheral clock disabled during CSleep mode
1: JPGDEC peripheral clock enabled during CSleep mode (default after reset)
Bit 4 DMA2DLPEN: DMA2D Clock Enable During CSleep Mode
Set and reset by software.
0: DMA2D peripheral clock disabled during CSleep mode
1: DMA2D peripheral clock enabled during CSleep mode (default after reset)
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 MDMALPEN: MDMA Clock Enable During CSleep Mode
Set and reset by software.
0: MDMA peripheral clock disabled during CSleep mode
1: MDMA peripheral clock enabled during CSleep mode (default after reset)

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8.7.50 RCC AHB1 Sleep clock register (RCC_AHB1LPENR)

This register can be accessed via two different offset address.

Table 76. RCC_AHB1LPENR address offset and reset value

Register Name Address Offset Reset Value

RCC_AHB1LPENR 0x100
0x1E03 C023
RCC_C1_AHB1LPENR 0x160

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USB2OTGHSULPILPEN

USB1OTGHSULPILPEN
USB2OTGHSLPEN

USB1OTGHSLPEN

ETH1RXLPEN

ETH1TXLPEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETH1MACLPEN

ADC12LPEN

DMA2LPEN

DMA1LPEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 USB2OTGHSULPILPEN: USB_PHY1 clock enable during CSleep mode
Set and reset by software.
0: USB_PHY1 peripheral clock disabled during CSleep mode
1: USB_PHY1 peripheral clock enabled during CSleep mode (default after reset)
Note: If the application enters Sleep mode, this bit must be cleared to avoid USB communication
failure.
Bit 27 USB2OTGHSLPEN: USB2OTG (OTG_US2) peripheral clock enable during CSleep mode
Set and reset by software.
0: USB2OTG peripheral clocks disabled during CSleep mode
1: USB2OTG peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the USB2OTG are: the kernel clock selected by USBSEL and the
rcc_hclk1 bus interface clock.
Bit 26 USB1OTGHSULPILPEN: USB_PHY1 clock enable during CSleep mode
Set and reset by software.
0: USB_PHY1 peripheral clock disabled during CSleep mode
1: USB_PHY1 peripheral clock enabled during CSleep mode (default after reset)

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Bit 25 USB1OTGHSLPEN: USB1OTG (OTG_HS1) peripheral clock enable during CSleep mode
Set and reset by software.
0: USB1OTG peripheral clock disabled during CSleep mode
1: USB1OTG peripheral clock enabled during CSleep mode (default after reset)
The peripheral clocks of the USB1OTG are: the kernel clock selected by USBSEL and the
rcc_hclk1 bus interface clock.
Bits 24:18 Reserved, must be kept at reset value.
Bit 17 ETH1RXLPEN: Ethernet Reception Clock Enable During CSleep Mode
Set and reset by software.
0: Ethernet Reception clock disabled during CSleep mode
1: Ethernet Reception clock enabled during CSleep mode (default after reset)
Bit 16 ETH1TXLPEN: Ethernet Transmission Clock Enable During CSleep Mode
Set and reset by software.
0: Ethernet Transmission clock disabled during CSleep mode
1: Ethernet Transmission clock enabled during CSleep mode (default after reset)
Bit 15 ETH1MACLPEN: Ethernet MAC bus interface Clock Enable During CSleep Mode
Set and reset by software.
0: Ethernet MAC bus interface clock disabled during CSleep mode
1: Ethernet MAC bus interface clock enabled during CSleep mode (default after reset)
Bits 14:6 Reserved, must be kept at reset value.
Bit 5 ADC12LPEN: ADC1/2 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: ADC1/2 peripheral clocks disabled during CSleep mode
1: ADC1/2 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the ADC1 and 2 are: the kernel clock selected by ADCSEL and provided to
adc_ker_ck_input, and the rcc_hclk1 bus interface clock.
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 DMA2LPEN: DMA2 Clock Enable During CSleep Mode
Set and reset by software.
0: DMA2 clock disabled during CSleep mode
1: DMA2 clock enabled during CSleep mode (default after reset)
Bit 0 DMA1LPEN: DMA1 Clock Enable During CSleep Mode
Set and reset by software.
0: DMA1 clock disabled during CSleep mode
1: DMA1 clock enabled during CSleep mode (default after reset)

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8.7.51 RCC AHB2 Sleep clock register (RCC_AHB2LPENR)

This register can be accessed via two different offset address.

Table 77. RCC_AHB2LPENR address offset and reset value

Register Name Address Offset Reset Value

RCC_AHB2LPENR 0x104
0xE000 0271
RCC_C1_AHB2LPENR 0x164

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRAM3LPEN

SRAM2LPEN

SRAM1LPEN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMC2LPEN

CAMITFLPEN
CRYPTLPEN
HASHLPEN
RNGLPEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bit 31 SRAM3LPEN: SRAM3 Clock Enable During CSleep Mode

Set and reset by software.
0: SRAM3 clock disabled during CSleep mode
1: SRAM3 clock enabled during CSleep mode (default after reset)
Bit 30 SRAM2LPEN: SRAM2 Clock Enable During CSleep Mode
Set and reset by software.
0: SRAM2 clock disabled during CSleep mode
1: SRAM2 clock enabled during CSleep mode (default after reset)
Bit 29 SRAM1LPEN: SRAM1 Clock Enable During CSleep Mode
Set and reset by software.
0: SRAM1 clock disabled during CSleep mode
1: SRAM1 clock enabled during CSleep mode (default after reset)
Bits 28:10 Reserved, must be kept at reset value.
Bit 9 SDMMC2LPEN: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode
Set and reset by software.
0: SDMMC2 and SDMMC2 Delay clock disabled during CSleep mode
1: SDMMC2 and SDMMC2 Delay clock enabled during CSleep mode (default after reset)
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 RNGLPEN: RNG peripheral clock enable during CSleep mode
Set and reset by software.
0: RNG peripheral clocks disabled during CSleep mode
1: RNG peripheral clock enabled during CSleep mode (default after reset)
The peripheral clocks of the RNG are: the kernel clock selected by RNGSEL and provided to
rng_ker_ck input, and the rcc_hclk2 bus interface clock.

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Bit 5 HASHLPEN: HASH peripheral clock enable during CSleep mode

Set and reset by software.
0: HASH peripheral clock disabled during CSleep mode
1: HASH peripheral clock enabled during CSleep mode (default after reset)
Bit 4 CRYPTLPEN: CRYPT peripheral clock enable during CSleep mode
Set and reset by software.
0: CRYPT peripheral clock disabled during CSleep mode
1: CRYPT peripheral clock enabled during CSleep mode (default after reset)
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DCMILPEN: DCMI peripheral clock enable during CSleep mode
Set and reset by software.
0: DCMI peripheral clock disabled during CSleep mode
1: DCMI peripheral clock enabled during CSleep mode (default after reset)

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8.7.52 RCC AHB4 Sleep clock register (RCC_AHB4LPENR)

This register can be accessed via two different offset address.

Table 78. RCC_AHB4LPENR address offset and reset value

Register Name Address Offset Reset Value

RCC_AHB4LPENR 0x108 0x3128 07FF

RCC_C1_AHB4LPENR 0x168

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKPRAMLPEN
SRAM4LPEN

BDMALPEN
ADC3LPEN

CRCLPEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPIOGLPEN
GPIOHLPEN

GPIODLPEN

GPIOCLPEN
GPIOKLPEN

GPIOELPEN

GPIOBLPEN

GPIOALPEN
GPIOFLPEN
GPIOJLPEN

GPIOILPEN

Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 SRAM4LPEN: SRAM4 Clock Enable During CSleep Mode
Set and reset by software.
0: SRAM4 clock disabled during CSleep mode
1: SRAM4 clock enabled during CSleep mode (default after reset)
Bit 28 BKPRAMLPEN: Backup RAM Clock Enable During CSleep Mode
Set and reset by software.
0: Backup RAM clock disabled during CSleep mode
1: Backup RAM clock enabled during CSleep mode (default after reset)
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 ADC3LPEN: ADC3 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: ADC3 peripheral clocks disabled during CSleep mode
1: ADC3 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the ADC3 are: the kernel clock selected by ADCSEL and provided to
adc_ker_ck_input, and the rcc_hclk4 bus interface clock.
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 BDMALPEN: BDMA Clock Enable During CSleep Mode
Set and reset by software.
0: BDMA clock disabled during CSleep mode
1: BDMA clock enabled during CSleep mode (default after reset)
Bit 20 Reserved, must be kept at reset value.

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Bit 19 CRCLPEN: CRC peripheral clock enable during CSleep mode

Set and reset by software.
0: CRC peripheral clock disabled during CSleep mode
1: CRC peripheral clock enabled during CSleep mode (default after reset)
Bits 18:11 Reserved, must be kept at reset value.
Bit 10 GPIOKLPEN: GPIOK peripheral clock enable during CSleep mode
Set and reset by software.
0: GPIOK peripheral clock disabled during CSleep mode
1: GPIOK peripheral clock enabled during CSleep mode (default after reset)
Bit 9 GPIOJLPEN: GPIOJ peripheral clock enable during CSleep mode
Set and reset by software.
0: GPIOJ peripheral clock disabled during CSleep mode
1: GPIOJ peripheral clock enabled during CSleep mode (default after reset)
Bit 8 GPIOILPEN: GPIOI peripheral clock enable during CSleep mode
Set and reset by software.
0: GPIOI peripheral clock disabled during CSleep mode
1: GPIOI peripheral clock enabled during CSleep mode (default after reset)
Bit 7 GPIOHLPEN: GPIOH peripheral clock enable during CSleep mode
Set and reset by software.
0: GPIOH peripheral clock disabled during CSleep mode
1: GPIOH peripheral clock enabled during CSleep mode (default after reset)
Bit 6 GPIOGLPEN: GPIOG peripheral clock enable during CSleep mode
Set and reset by software.
0: GPIOG peripheral clock disabled during CSleep mode
1: GPIOG peripheral clock enabled during CSleep mode (default after reset)
Bit 5 GPIOFLPEN: GPIOF peripheral clock enable during CSleep mode
Set and reset by software.
0: GPIOF peripheral clock disabled during CSleep mode
1: GPIOF peripheral clock enabled during CSleep mode (default after reset)
Bit 4 GPIOELPEN: GPIOE peripheral clock enable during CSleep mode
Set and reset by software.
0: GPIOE peripheral clock disabled during CSleep mode
1: GPIOE peripheral clock enabled during CSleep mode (default after reset)
Bit 3 GPIODLPEN: GPIOD peripheral clock enable during CSleep mode
Set and reset by software.
0: GPIOD peripheral clock disabled during CSleep mode
1: GPIOD peripheral clock enabled during CSleep mode (default after reset)

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RM0433 Reset and Clock Control (RCC)

Bit 2 GPIOCLPEN: GPIOC peripheral clock enable during CSleep mode

Set and reset by software.
0: GPIOC peripheral clock disabled during CSleep mode
1: GPIOC peripheral clock enabled during CSleep mode (default after reset)
Bit 1 GPIOBLPEN: GPIOB peripheral clock enable during CSleep mode
Set and reset by software.
0: GPIOB peripheral clock disabled during CSleep mode
1: GPIOB peripheral clock enabled during CSleep mode (default after reset)
Bit 0 GPIOALPEN: GPIOA peripheral clock enable during CSleep mode
Set and reset by software.
0: GPIOA peripheral clock disabled during CSleep mode
1: GPIOA peripheral clock enabled during CSleep mode (default after reset)

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8.7.53 RCC APB3 Sleep clock register (RCC_APB3LPENR)

This register can be accessed via two different offset address.

Table 79. RCC_APB3LPENR address offset and reset value

Register Name Address Offset Reset Value

RCC_APB3LPENR 0x10C
0x0000 0058
RCC_C1_APB3LPENR 0x16C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WWDG1LPEN

LTDCLPEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 WWDG1LPEN: WWDG1 Clock Enable During CSleep Mode
Set and reset by software.
0: WWDG1 clock disable during CSleep mode
1: WWDG1 clock enabled during CSleep mode (default after reset)
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 LTDCLPEN: LTDC peripheral clock enable during CSleep mode
Provides the pixel clock (ltdc_ker_ck) to the LTDC block.
Set and reset by software.
0: LTDC clock disabled during CSleep mode
1: LTDC clock provided to the LTDC during CSleep mode (default after reset)
Bits 2:0 Reserved, must be kept at reset value.

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8.7.54 RCC APB1 Low Sleep clock register (RCC_APB1LLPENR)

This register can be accessed via two different offset address.

Table 80. RCC_APB1LLPENR address offset and reset value

Register Name Address Offset Reset Value

RCC_APB1LLPENR 0x110
0xE8FF CBFF
RCC_C1_APB1LLPENR 0x170

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPDIFRXLPEN
USART3LPEN

USART2LPEN
UART8LPEN

UART7LPEN

UART5LPEN

UART4LPEN
DAC12LPEN

CECLPEN

I2C3LPEN

I2C2LPEN

I2C1LPEN
Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM1LPEN

TIM14LPEN

TIM13LPEN

TIM12LPEN

TIM7LPEN

TIM6LPEN

TIM5LPEN

TIM4LPEN

TIM3LPEN

TIM2LPEN
SPI3LPEN

SPI2LPEN

Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 UART8LPEN: UART8 Peripheral Clocks Enable During CSleep Mode

Set and reset by software.
0: UART8 peripheral clocks disabled during CSleep mode
1: UART8 peripheral clocks enabled during CSleep mode (default after reset):
The peripheral clocks of the UART8 are: the kernel clock selected by USART234578SEL and
provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 30 UART7LPEN: UART7 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: UART7 peripheral clocks disabled during CSleep mode
1: UART7 peripheral clocks enabled during CSleep mode (default after reset):
The peripheral clocks of the UART7 are: the kernel clock selected by USART234578SEL and
provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 29 DAC12LPEN: DAC1/2 peripheral clock enable during CSleep mode
Set and reset by software.
0: DAC1/2 peripheral clock disabled during CSleep mode
1: DAC1/2 peripheral clock enabled during CSleep mode (default after reset)
Bit 28 Reserved, must be kept at reset value.
Bit 27 CECLPEN: HDMI-CEC Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: HDMI-CEC peripheral clocks disabled during CSleep mode
1: HDMI-CEC peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the HDMI-CEC are: the kernel clock selected by CECSEL and provided to
cec_ker_ck input, and the rcc_pclk1 bus interface clock.
Bits 26:24 Reserved, must be kept at reset value.

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Bit 23 I2C3LPEN: I2C3 Peripheral Clocks Enable During CSleep Mode

Set and reset by software.
0: I2C3 peripheral clocks disabled during CSleep mode
1: I2C3 peripheral clocks enabled during CSleep mode (default after reset):
The peripheral clocks of the I2C3 are: the kernel clock selected by I2C123SEL and provided to
i2c_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 22 I2C2LPEN: I2C2 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: I2C2 peripheral clocks disabled during CSleep mode
1: I2C2 peripheral clocks enabled during CSleep mode (default after reset):
The peripheral clocks of the I2C2 are: the kernel clock selected by I2C123SEL and provided to
i2c_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 21 I2C1LPEN: I2C1 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: I2C1 peripheral clocks disabled during CSleep mode
1: I2C1 peripheral clocks enabled during CSleep mode (default after reset):
The peripheral clocks of the I2C1 are: the kernel clock selected by I2C123SEL and provided to
i2c_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 20 UART5LPEN: UART5 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: UART5 peripheral clocks disabled during CSleep mode
1: UART5 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the UART5 are: the kernel clock selected by USART234578SEL and
provided to uart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 19 UART4LPEN: UART4 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: UART4 peripheral clocks disabled during CSleep mode
1: UART4 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the UART4 are: the kernel clock selected by USART234578SEL and
provided to uart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 18 USART3LPEN: USART3 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: USART3 peripheral clocks disabled during CSleep mode
1: USART3 peripheral clocks enabled during CSleep mode (default after reset):
The peripheral clocks of the USART3 are: the kernel clock selected by USART234578SEL and
provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 17 USART2LPEN: USART2 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: USART2 peripheral clocks disabled during CSleep mode
1: USART2 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the USART2 are: the kernel clock selected by USART234578SEL and
provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 16 SPDIFRXLPEN: SPDIFRX Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: SPDIFRX peripheral clocks disabled during CSleep mode
1: SPDIFRX peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SPDIFRX are: the kernel clock selected by SPDIFSEL and provided to
spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock.

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RM0433 Reset and Clock Control (RCC)

Bit 15 SPI3LPEN: SPI3 Peripheral Clocks Enable During CSleep Mode

Set and reset by software.
0: SPI3 peripheral clocks disabled during CSleep mode
1: SPI3 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SPI3 are: the kernel clock selected by I2S123SRC and provided to
spi_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 14 SPI2LPEN: SPI2 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: SPI2 peripheral clocks disabled during CSleep mode
1: SPI2 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SPI2 are: the kernel clock selected by I2S123SRC and provided to
spi_ker_ck input, and the rcc_pclk1 bus interface clock.
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 LPTIM1LPEN: LPTIM1 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: LPTIM1 peripheral clocks disabled during CSleep mode
1: LPTIM1 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the LPTIM1 are: the kernel clock selected by LPTIM1SEL and provided to
lptim_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 8 TIM14LPEN: TIM14 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM14 peripheral clock disabled during CSleep mode
1: TIM14 peripheral clock enabled during CSleep mode (default after reset)
Bit 7 TIM13LPEN: TIM13 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM13 peripheral clock disabled during CSleep mode
1: TIM13 peripheral clock enabled during CSleep mode (default after reset)
Bit 6 TIM12LPEN: TIM12 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM12 peripheral clock disabled during CSleep mode
1: TIM12 peripheral clock enabled during CSleep mode (default after reset)
Bit 5 TIM7LPEN: TIM7 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM7 peripheral clock disabled during CSleep mode
1: TIM7 peripheral clock enabled during CSleep mode (default after reset)
Bit 4 TIM6LPEN: TIM6 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM6 peripheral clock disabled during CSleep mode
1: TIM6 peripheral clock enabled during CSleep mode (default after reset)
Bit 3 TIM5LPEN: TIM5 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM5 peripheral clock disabled during CSleep mode
1: TIM5 peripheral clock enabled during CSleep mode (default after reset)

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Bit 2 TIM4LPEN: TIM4 peripheral clock enable during CSleep mode

Set and reset by software.
0: TIM4 peripheral clock disabled during CSleep mode
1: TIM4 peripheral clock enabled during CSleep mode (default after reset)
Bit 1 TIM3LPEN: TIM3 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM3 peripheral clock disabled during CSleep mode
1: TIM3 peripheral clock enabled during CSleep mode (default after reset)
Bit 0 TIM2LPEN: TIM2 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM2 peripheral clock disabled during CSleep mode
1: TIM2 peripheral clock enabled during CSleep mode (default after reset)

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RM0433 Reset and Clock Control (RCC)

8.7.55 RCC APB1 High Sleep clock register (RCC_APB1HLPENR)

This register can be accessed via two different offset address.

Table 81. RCC_APB1HLPENR address offset and reset value

Register Name Address Offset Reset Value

RCC_APB1HLPENR 0x114
0x0000 0136
RCC_C1_APB1HLPENR 0x174

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPAMPLPEN
FDCANLPEN

MDIOSLPEN

SWPLPEN

CRSLPEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 FDCANLPEN: FDCAN Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: FDCAN peripheral clocks disabled during CSleep mode
1: FDCAN peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the FDCAN are: the kernel clock selected by FDCANSEL and provided to
fdcan_ker_ck input, and the rcc_pclk1 bus interface clock.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSLPEN: MDIOS peripheral clock enable during CSleep mode
Set and reset by software.
0: MDIOS peripheral clock disabled during CSleep mode
1: MDIOS peripheral clock enabled during CSleep mode (default after reset)
Bit 4 OPAMPLPEN: OPAMP peripheral clock enable during CSleep mode
Set and reset by software.
0: OPAMP peripheral clock disabled during CSleep mode
1: OPAMP peripheral clock enabled during CSleep mode (default after reset)
Bit 3 Reserved, must be kept at reset value.

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Bit 2 SWPLPEN: SWPMI Peripheral Clocks Enable During CSleep Mode

Set and reset by software.
0: SWPMI peripheral clocks disabled during CSleep mode
1: SWPMI peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SWPMI are: the kernel clock selected by SWPSEL and provided to
swpmi_ker_ck input, and the rcc_pclk1 bus interface clock.
Bit 1 CRSLPEN: Clock Recovery System peripheral clock enable during CSleep mode
Set and reset by software.
0: CRS peripheral clock disabled during CSleep mode
1: CRS peripheral clock enabled during CSleep mode (default after reset)
Bit 0 Reserved, must be kept at reset value.

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8.7.56 RCC APB2 Sleep clock register (RCC_APB2LPENR)

This register can be accessed via two different offset address.

Table 82. RCC_APB2LPENR address offset and reset value

Register Name Address Offset Reset Value

RCC_APB2LPENR 0x118
0x31D7 3033
RCC_C1_APB2LPENR 0x178

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1LPEN
HRTIMLPEN

TIM17LPEN

TIM16LPEN

TIM15LPEN
SAI3LPEN

SAI2LPEN

SAI1LPEN

SPI5LPEN
Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USART6LPEN

USART1LPEN

TIM8LPEN

TIM1LPEN
SPI4LPEN

SPI1LPEN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 HRTIMLPEN: HRTIM peripheral clock enable during CSleep mode
Set and reset by software.
0: HRTIM peripheral clock disabled during CSleep mode
1: HRTIM peripheral clock enabled during CSleep mode (default after reset)
Bit 28 DFSDM1LPEN: DFSDM1 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: DFSDM1 peripheral clocks disabled during CSleep mode
1: DFSDM1 peripheral clocks enabled during CSleep mode (default after reset)
DFSDM1 peripheral clocks are: the kernel clocks selected by SAI1SEL and DFSDM1SEL and
provided to Aclk and clk inputs respectively, and the rcc_pclk2 bus interface clock.
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 SAI3LPEN: SAI3 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: SAI3 peripheral clocks disabled during CSleep mode
1: SAI3 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SAI3 are: the kernel clock selected by SAI23SEL and provided to
sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.
Bit 23 SAI2LPEN: SAI2 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: SAI2 peripheral clocks disabled during CSleep mode
1: SAI2 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SAI2 are: the kernel clock selected by SAI23SEL and provided to
sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.

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Bit 22 SAI1LPEN: SAI1 Peripheral Clocks Enable During CSleep Mode

Set and reset by software.
0: SAI1 peripheral clocks disabled during CSleep mode
1: SAI1 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to
sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.
Bit 21 Reserved, must be kept at reset value.
Bit 20 SPI5LPEN: SPI5 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: SPI5 peripheral clocks disabled during CSleep mode
1: SPI5 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SPI5 are: the kernel clock selected by SPI45SEL and provided to
spi_ker_ck input, and the rcc_pclk2 bus interface clock.
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM17LPEN: TIM17 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM17 peripheral clock disabled during CSleep mode
1: TIM17 peripheral clock enabled during CSleep mode (default after reset)
Bit 17 TIM16LPEN: TIM16 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM16 peripheral clock disabled during CSleep mode
1: TIM16 peripheral clock enabled during CSleep mode (default after reset)
Bit 16 TIM15LPEN: TIM15 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM15 peripheral clock disabled during CSleep mode
1: TIM15 peripheral clock enabled during CSleep mode (default after reset)
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 SPI4LPEN: SPI4 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: SPI4 peripheral clocks disabled during CSleep mode
1: SPI4 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to
spi_ker_ck input, and the rcc_pclk2 bus interface clock.
Bit 12 SPI1LPEN: SPI1 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: SPI1 peripheral clocks disabled during CSleep mode
1: SPI1 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to
spi_ker_ck input, and the rcc_pclk2 bus interface clock.
Bits 11:6 Reserved, must be kept at reset value.
Bit 5 USART6LPEN: USART6 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: USART6 peripheral clocks disabled during CSleep mode
1: USART6 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the USART6 are: the kernel clock selected by USART16SEL and provided
to usart_ker_ck input, and the rcc_pclk2 bus interface clock.

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Bit 4 USART1LPEN: USART1 Peripheral Clocks Enable During CSleep Mode

Set and reset by software.
0: USART1 peripheral clocks disabled during CSleep mode
1: USART1 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the USART1 are: the kernel clock selected by USART16SEL and provided
to usart_ker_ck inputs, and the rcc_pclk2 bus interface clock.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8LPEN: TIM8 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM8 peripheral clock disabled during CSleep mode
1: TIM8 peripheral clock enabled during CSleep mode (default after reset)
Bit 0 TIM1LPEN: TIM1 peripheral clock enable during CSleep mode
Set and reset by software.
0: TIM1 peripheral clock disabled during CSleep mode
1: TIM1 peripheral clock enabled during CSleep mode (default after reset)

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8.7.57 RCC APB4 Sleep clock register (RCC_APB4LPENR)

This register can be accessed via two different offset address.

Table 83. RCC_APB4LPENR address offset and reset value

Register Name Address Offset Reset Value

RCC_APB4LPENR 0x11C
0x0421 DEAA
RCC_C1_APB4LPENR 0x17C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RTCAPBLPEN
SAI4LPEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPUART1LPEN
COMP12LPEN

SYSCFGLPEN
LPTIM5LPEN

LPTIM4LPEN

LPTIM3LPEN

LPTIM2LPEN
VREFLPEN

SPI6LPEN
I2C4LPEN

Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:22 Reserved, must be kept at reset value.
Bit 21 SAI4LPEN: SAI4 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: SAI4 peripheral clocks disabled during CSleep mode
1: SAI4 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SAI4 are: the kernel clocks selected by SAI4ASEL and SAI4BSEL, and
provided to sai_a_ker_ck and sai_b_ker_ck inputs respectively, and the rcc_pclk4 bus interface
clock.
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 RTCAPBLPEN: RTC APB Clock Enable During CSleep Mode
Set and reset by software.
0: The register clock interface of the RTC (APB) is disabled during CSleep mode
1: The register clock interface of the RTC (APB) is enabled during CSleep mode (default after reset)
Bit 15 VREFLPEN: VREF peripheral clock enable during CSleep mode
Set and reset by software.
0: VREF peripheral clock disabled during CSleep mode
1: VREF peripheral clock enabled during CSleep mode (default after reset)
Bit 14 COMP12LPEN: COMP1/2 peripheral clock enable during CSleep mode
Set and reset by software.
0: COMP1/2 peripheral clock disabled during CSleep mode
1: COMP1/2 peripheral clock enabled during CSleep mode (default after reset)
Bit 13 Reserved, must be kept at reset value.

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Bit 12 LPTIM5LPEN: LPTIM5 Peripheral Clocks Enable During CSleep Mode

Set and reset by software.
0: LPTIM5 peripheral clocks disabled during CSleep mode
1: LPTIM5 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the LPTIM5 are: the kernel clock selected by LPTIM345SEL and provided
to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 11 LPTIM4LPEN: LPTIM4 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: LPTIM4 peripheral clocks disabled during CSleep mode
1: LPTIM4 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the LPTIM4 are: the kernel clock selected by LPTIM345SEL and provided
to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 10 LPTIM3LPEN: LPTIM3 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: LPTIM3 peripheral clocks disabled during CSleep mode
1: LPTIM3 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the LPTIM3 are: the kernel clock selected by LPTIM345SEL and provided
to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 9 LPTIM2LPEN: LPTIM2 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: LPTIM2 peripheral clocks disabled during CSleep mode
1: LPTIM2 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the LPTIM5 are: the kernel clock selected by LPTIM2SEL and provided to
lptim_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4LPEN: I2C4 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: I2C4 peripheral clocks disabled during CSleep mode
1: I2C4 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the I2C4 are: the kernel clock selected by I2C4SEL and provided to
i2c_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6LPEN: SPI6 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: SPI6 peripheral clocks disabled during CSleep mode
1: SPI6 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the SPI6 are: the kernel clock selected by SPI6SEL and provided to
spi_ker_ck input, and the rcc_pclk4 bus interface clock.
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1LPEN: LPUART1 Peripheral Clocks Enable During CSleep Mode
Set and reset by software.
0: LPUART1 peripheral clocks disabled during CSleep mode
1: LPUART1 peripheral clocks enabled during CSleep mode (default after reset)
The peripheral clocks of the LPUART1 are: the kernel clock selected by LPUART1SEL and
provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock.

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Bit 2 Reserved, must be kept at reset value.

Bit 1 SYSCFGLPEN: SYSCFG peripheral clock enable during CSleep mode
Set and reset by software.
0: SYSCFG peripheral clock disabled during CSleep mode
1: SYSCFG peripheral clock enabled during CSleep mode (default after reset)
Bit 0 Reserved, must be kept at reset value.

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 8.8

0x024
0x020
0x018
0x014
0x010
0x008
0x004
0x004
0x000

0x01C
0x00C
0x00C
Offset
RM0433

RCC_CR

reserved
reserved
reserved

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

RCC_CFGR
RCC_HSICFGR

RCC_CRRCR
RCC_ICSCR(1)

RCC_D3CFGR
RCC_D2CFGR
RCC_D1CFGR
Register name

RCC_CSICFGR(2)
(2)
Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. MCO2[2:0] Res. Res. Res.ì 30
Res. Res. Res. Res. PLL3RDY 29
Res. Res. Res. Res. PLL3ON 28
Res. Res. Res. Res. PLL2RDY 27
MCO2PRE[3:0]

CSITRIM[4:0]
Res. Res. Res. Res. PLL2ON 26
RCC register map

HSITRIM[6:0]
1 0 0 0 0 -

1 0 0 0 0 0
Res. Res. Res. Res. PLL1RDY 25

CSITRIM[5:0]
-

1 0 0 0 0 0
Res. Res. Res. Res. Res. 0 0 0 0 0 0 PLL1ON 24

-
Res. Res. Res. MCO1[2:0] Res. Res. Res. Res. 23
-
Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. - Res.
-
21
Res. Res. Res. Res. Res. Res. Res.
CSICAL[7:0]

MCO1PRE[3:0] 20
-

Res. Res. Res. Res. Res. Res. HSECSSON 19

-

0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res. Res. Res. Res. Res. Res. HSEBYP

RM0433 Rev 8
18
Res. Res. Res. Res. Res. Res. Res. HSERDY 17
Res. Res. Res. Res. Res. Res. Res. HSEON 16
Res. Res. Res. TIMPRE Res. Res. Res. D2CKRDY 15

Reserved
Reserved
Reserved
Res. Res. Res. HRTIMSEL Res. Res. Res. D1CKRDY 14
Res. Res. Res. Res. Res. Res. HSI48RDY 13
HSITRIM[5:0]
0 0 0 0 0 0 0 0

Res. Res. Res. Res. Res. Res. HSI48ON 12

1 0 0 0 0 0 -
Table 84. RCC register map and reset values

Res. Res. Res. Res. Res. 11

RTCPRE[5:0]
-

Res. Res. Res. Res. 10

D1CPRE[3:0]
-

Res. D2PPRE2[2:0] CSIKERON 9

-

0 0 0
0 0 0 0
Res. CSIRDY 8
-

-
0 0 0

Res. Res. Res. STOPKERWUCK CSION 7

-

STOPWUCK Res. 6
-

D3PPRE[2:0] D2PPRE1[2:0] D1PPRE[2:0] HSIDIVF 5

-

0 0 0
0 0 0
SWS[2:0] 4
HSICAL[11:0]
HSICAL[11:0]

HSIDIV[1:0]
-

Res. Res.
CSICAL[9:0]

3
HSI48CAL[9:0]
-

Res. Res. HSIRDY 2

HPRE[3:0]
-

Res. Res. SW[2:0] HSIKERON 1

-

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1

0 0 0 0 0 0 0
X X X X X X X X
X X X X X X X X X X X X

Res. Res. HSION

Reset and Clock Control (RCC)

495/3353
0

504
Reset and Clock Control (RCC) RM0433

Table 84. RCC register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
PLLSRC[1:0]
DIVM3[5:0]

DIVM2[5:0]

DIVM1[5:0]
RCC_
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
Res.

Res.
Res.
0x028 PLLCKSELR

Reset value 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0

PLL3RGE[1:0]

PLL3FRACEN

PLL2RGE[1:0]

PLL2FRACEN

PLL1RGE[1:0]

PLL1FRACEN
PLL3VCOSEL

PLL2VCOSEL

PLL1VCOSEL
DIVQ3EN

DIVQ2EN

DIVQ1EN
DIVR3EN

DIVR2EN

DIVR1EN
DIVP3EN

DIVP2EN

DIVP1EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
RCC_PLLCFGR
0x02C

Reset value 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Res.

Res.

RCC_PLL1DIVR DIVR1[6:0] DIVQ1[6:0] DIVP1[6:0] DIVN1[8:0]

0x030
Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
RCC_PLL1FRACR FRACN1[12:0]
0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.

Res.

RCC_PLL2DIVR DIVR2[6:0] DIVQ2[6:0] DIVP2[6:0] DIVN2[8:0]

0x038
Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
RCC_PLL2FRACR FRACN2[12:0]
0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.

Res.

RCC_PLL3DIVR DIVR3[6:0] DIVQ3[6:0] DIVP3[6:0] DIVN3[8:0]

0x040
Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
RCC_PLL3FRACR FRACN3[12:0]
0x044
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0
0x048 reserved Reserved
CKPERSEL[1:0]

QSPISEL[1:0]

FMCSEL[1:0]
SDMMCSEL
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

RCC_D1CCIPR
0x04C

Reset value 0 0 0 0 0 0 0
FDCANSEL[1:0]

SPI123SEL[2:0]
SPDIFSEL[1:0]

SPI45SEL[2:0]

SAI23SEL[2:0]
DFSDM1SEL

SAI1SEL[2:0]
SWPSEL
Res.

Res.
Res.
Res.

Res.
Res.

Res.

Res.

Res.
Res.
Res.

Res.
Res.
Res.

RCC_D2CCIP1R
0x050

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

496/3353 RM0433 Rev 8

 0x078
0x074
0x070
0x068
0x064
0x060
0x058
0x054

0x06C
0x05C
Offset
RM0433

reserved
reserved
reserved

RCC_CSR
RCC_CIFR
RCC_CIER

RCC_CICR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

RCC_BDCR
RCC_D3CCIPR
RCC_D2CCIP2R
Register name

Res. Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. SPI6SEL[2:0] LPTIM1SEL[2:0] 29

0 0 0
0 0 0
Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. SAI4BSEL[2:0] Res. 25
Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. 23
CECSEL[1:0]
Res. Res. Res. Res. Res. SAI4ASEL[2:0] 22

0 0 0 0 0 0
Res. Res. Res. Res. Res. 21
USBSEL[1:0]
0 0 0 0

Res. Res. Res. Res. Res. Res. 20

Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res.

RM0433 Rev 8
18
Res. Res. Res. Res. Res. Res. 17
ADCSEL[1;0]
Res. BDRST Res. Res. Res. Res. 16

0 0
Res. RTCEN Res. Res. Res. Res. 15

Reserved
Reserved
Reserved
Res. Res. Res. Res. Res. LPTIM345SEL[2:0] Res. 14
Res. Res. Res. Res. Res. 13
I2C123SEL[1:0]
0 0

Res. Res. Res. Res. Res. 12

Res. Res. Res. Res. Res. LPTIM2SEL[2:0] Res. 11
Res. Res. HSECSSC HSECSSF Res. Res. 10
Res. LSECSSC LSECSSF LSECSSIE 9
Table 84. RCC register map and reset values (continued)

RTCSEL[1:0] I2C4SEL[1:0] RNGSEL[1:0]

0 0 0 0 0 0 0 0 0 0

0 0
0 0

Res. PLL3RDYC PLL3RDYF PLL3RDYIE 8

Res. Res. PLL2RDYC PLL2RDYF PLL2RDYIE Res. Res. 7
Res. LSECSSD PLL1RDYC PLL1RDYF PLL1RDYIE Res. Res. 6
Res. LSECSSON HSI48RDYC HSI48RDYF HSI48RDYIE Res. 5
Res. CSIRDYC CSIRDYF CSIRDYIE Res. USART16SEL[2:0] 4
LSEDRV[1:0]
Res. HSERDYC HSERDYF HSERDYIE Res. 3
Res. LSEBYP HSIRDYC HSIRDYF HSIRDYIE 2
LSIRDY LSERDY LSERDYC LSERDYF LSERDYIE LPUART1SEL[2:0] USART234578SEL[2:0] 1
0 0 0

0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0

0 0
LSION LSEON LSIRDYC LSIRDYF LSIRDYIE
Reset and Clock Control (RCC)

497/3353
0

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 0x098
0x094
0x090
0x088
0x084
0x080

0x08C
0x07C
Offset

498/3353
RCC_
RCC_
RCC_
RCC_
RCC_
RCC_
RCC_
RCC_

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

APB2RSTR
APB3RSTR
AHB4RSTR
AHB2RSTR
AHB1RSTR
AHB3RSTR

APB1LRSTR

APB1HRSTR
Register name

Res. Res. UART8RST Res. Res. Res. Res. Res. 31

Res. Res. UART7RST Res. Res. Res. Res. Res. 30

0 0 0
HRTIMRST Res. DAC12RST Res. Res. Res. Res. Res. 29
Reset and Clock Control (RCC)

0 0
DFSDM1RST Res. Res. Res. Res. Res. Res. Res. 28

0
0
Res. Res. CECRST Res. Res. Res. USB2OTGRST Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. 26

0
Res. Res. Res. Res. HSEMRST Res. USB1OTGRST Res. 25

0 0
SAI3RST Res. Res. Res. ADC3RST Res. Res. Res. 24
SAI2RST Res. I2C3RST Res. Res. Res. Res. Res. 23

0 0 0
SAI1RST Res. I2C2RST Res. Res. Res. Res. Res. 22

0
Res. Res. I2C1RST Res. BDMARST Res. Res. Res. 21

0
SPI5RST Res. UART5RST Res. Res. Res. Res. Res. 20

0
Res. Res. UART4RST Res. CRCRST Res. Res. Res. 19
TIM17RST Res. USART3RST Res. Res. Res. Res. Res.

RM0433 Rev 8
18
TIM16RST Res. USART2RST Res. Res. Res. Res. Res. 17

0 0 0
0

TIM15RST Res. SPDIFRXRST Res. Res. Res. Res. SDMMC1RST 16

0

Res. Res. SPI3RST Res. Res. Res. ETH1MACRST Res. 15

0 0 0 0 0 0 0 0 0 0
0

Res. Res. SPI2RST Res. Res. Res. Res. QSPIRST 14

SPI4RST Res. Res. Res. Res. Res. Res. Res. 13

0 0
0

SPI1RST Res. Res. Res. Res. Res. Res. FMCRST 12

Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. GPIOKRST Res. Res. Res. 10
0

Res. Res. LPTIM1RST Res. GPIOJRST SDMMC2RST Res. Res. 9

Table 84. RCC register map and reset values (continued)

0
Res. FDCANRST TIM14RST Res. GPIOIRST Res. Res. Res. 8
Res. Res. TIM13RST Res. GPIOHRST Res. Res. Res. 7
Res. Res. TIM12RST Res. GPIOGRST RNGRST Res. Res. 6
0

USART6RST MDIOSRST TIM7RST Res. GPIOFRST HASHRST ADC12RST JPGDECRST 5

0 0
0 0
0 0 0
0 0

USART1RST OPAMPRST TIM6RST 0 Res. GPIOERST CRYPTRST Res. DMA2DRST 4

Res. Res. TIM5RST LTDCRST GPIODRST Res. Res. Res. 3
Res. RST TIM4RST Res. GPIOCRST Res. Res. Res. 2

0 0
TIM8RST CRSRST TIM3RST Res. GPIOBRST Res. DMA2RST Res. 1

0 0 0 0 0 0 0 0 0 0

0 0
0 0 0 0 0 0 0 0 0 0 0
0
0 0
0

TIM1RST Res. TIM2RST Res. GPIOARST CAMITFRST DMA1RST MDMARST

RM0433

0
 to
0x0A8
0x0A0

0x0D8
0x0D4
0x0D0
0x09C

0x0AC

0x0DC
0x0CC
0x0A4
Offset
RM0433

RCC_
RCC_
RCC_
RCC_

reserved
reserved

AHB2ENR
AHB1ENR
AHB3ENR
RCC_RSR
RCC_GCR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
APB4RSTR

RCC_D3AMR
Register name

SRAM3EN Res. Res. Res. Res. Res. Res. 31

0
SRAM2EN Res. Res. LPWRRSTF Res. Res. Res. 30

0 0 0
SRAM1EN Res. Res. Res. SRAM4AMEN Res. Res. 29

0
0 0
Res. USB2OTGHSULPIEN Res. WWDG1RSTF BKPRAMAMEN Res. Res. 28
Res. USB2OTGHSEN Res. Res. Res. Res. Res. 27

0
Res. USB1OTGHSULPIEN Res. IWDG1RSTF Res. Res. Res. 26

0 0 0 0
Res. USB1OTGHSEN Res. Res. Res. Res. Res. 25

0
Res. Res. Res. SFTRSTF ADC3AMEN Res. Res. 24
Res. Res. Res. PORRSTF Res. Res. Res. 23
Res. Res. Res. PINRSTF Res. Res. Res. 22

0
0

Res. Res. Res. BORRSTF SAI4AMEN Res. SAI4RST 21

Res. Res. Res. D2RSTF Res. Res. Res. 20

0 1 1 1 1 1
0
Res. Res. Res. D1RSTF CRCAMEN Res. Res. 19
Res. Res. Res. Res. Res. Res. Res.

RM0433 Rev 8
18
Res. ETH1RXEN Res. CPURSTF Res. Res. Res. 17

1 0

0
Res. ETH1TXEN SDMMC1EN RMVF RTCAMEN Res. Res. 16

0 0 0
Res. ETH1MACEN Res. Res. VREFAMEN Res. VREFRST 15

Reserved
Reserved

0
0 0 0
0 0

Res. Res. QSPIEN Res. COMP12AMEN Res. COMP12RST 14

Res. Res. Res. Res. Res. Res. Res. 13

0
Res. Res. FMCEN Res. LPTIM5AMEN Res. LPTIM5RST 12
Res. Res. Res. Res. LPTIM4AMEN Res. LPTIM4RST 11
Res. Res. Res. Res. LPTIM3AMEN Res. LPTIM3RST 10

0
0 0 0 0
0 0 0 0

SDMMC2EN Res. Res. Res. LPTIM2AMEN Res. LPTIM2RST 9

Table 84. RCC register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. 8

0
0

Res. Res. Res. Res. I2C4AMEN Res. I2C4RST 7

RNGEN Res. Res. Res. Res. Res. Res. 6

0
0
0

HASHEN ADC12EN JPGDECEN Res. SPI6AMEN Res. SPI6RST 5

0 0 0
0 0
CRYPTEN Res. DMA2DEN Res. Res. Res. Res. 4
0
0

Res. Res. Res. Res. LPUART1AMEN Res. LPUART1RST 3

Res. Res. Res. Res. Res. Res. Res. 2
0

Res. DMA2EN Res. Res. Res. Res. SYSCFGRST 1

0
0 0
0

0
0

DCMIEN DMA1EN MDMAEN Res. BDMAAMEN WW1RSC Res.

Reset and Clock Control (RCC)

499/3353
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 0x100
0x0F8
0x0F4
0x0F0
0x0E8
0x0E4
0x0E0

0x0FC
0x0EC
Offset

500/3353
RCC_
RCC_
RCC_
RCC_
RCC_
RCC_
RCC_
RCC_

reserved
APB4ENR
APB2ENR
APB3ENR
AHB4ENR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

APB1LENR

APB1HENR

AHB1LPENR
AHB3LPENR
Register name

Res. AXISRAMLPEN Res. Res. Res. UART8EN Res. Res. 31

Res. ITCMLPEN Res. Res. Res. UART7EN Res. Res. 30

0 0 0
Res. DTCM2LPEN Res. HRTIMEN Res. DAC12EN Res. Res. 29
Reset and Clock Control (RCC)

1 1 1 1
0 0
0
USB2OTGHSULPILPEN DTCM1LPEN Res. DFSDM1EN Res. Res. Res. BKPRAMEN 28

0
USB2OTGHSLPEN Res. Res. Res. Res. CECEN Res. Res. 27
USB1OTGHSULPILPEN Res. Res. Res. Res. Res. Res. Res. 26

1 1 1 1
USB1OTGHSLPEN Res. Res. Res. Res. Res. Res. HSEMEN 25
0 0

Res. Res. Res. SAI3EN Res. Res. Res. ADC3EN 24

Res. Res. Res. SAI2EN Res. I2C3EN Res. Res. 23

0 0 0
Res. Res. Res. SAI1EN Res. I2C2EN Res. Res. 22

0
0

Res. Res. SAI4EN Res. Res. I2C1EN Res. BDMAEN 21

0
Res. Res. Res. SPI5EN Res. UART5EN Res. Res. 20
0

Res. Res. Res. Res. Res. UART4EN Res. CRCEN 19

Res. Res. Res. TIM17EN Res. USART3EN Res. Res.

RM0433 Rev 8
18
ETH1RXLPEN Res. Res. TIM16EN Res. USART2EN Res. Res. 17

1
0 0 0
ETH1TXLPEN SDMMC1LPEN RTCAPBEN TIM15EN Res. SPDIFRXEN Res. Res. 16

1 1 1
ETH1MACLPEN Res. VREFEN Res. Res. SPI3EN Res. Res. 15

Reserved
0 0 0 0 0 0 0 0 0 0

1
1 0 0
Res. QSPILPEN COMP12EN Res. Res. SPI2EN Res. Res. 14
Res. Res. Res. SPI4EN Res. Res. Res. Res. 13

1
0 0
Res. FMCLPEN LPTIM5EN SPI1EN Res. Res. Res. Res. 12
Res. Res. LPTIM4EN Res. Res. Res. Res. Res. 11
Res. Res. LPTIM3EN Res. Res. Res. Res. GPIOKEN 10

0 0 0 0
Res. Res. LPTIM2EN Res. Res. LPTIM1EN Res. GPIOJEN 9
Table 84. RCC register map and reset values (continued)

1
0

Res. FLASHLPEN Res. Res. FDCANEN TIM14EN Res. GPIOIEN 8

Res. Res. I2C4EN Res. Res. TIM13EN Res. GPIOHEN 7
0

Res. Res. Reserved Res. Res. TIM12EN WWDG1EN GPIOGEN 6

1
0 0 0
ADC12LPEN JPGDECLPEN SPI6EN USART6EN MDIOSEN TIM7EN Res. GPIOFEN 5

1 1
0 0
0 0

Res. DMA2DLPEN Res. USART1EN OPAMPEN TIM6EN Res. GPIOEEN 4

0
0

Res. Res. LPUART1EN Res. Res. TIM5EN LTDCEN GPIODEN 3

Res. Res. Res. Res. SWPEN TIM4EN Res. GPIOCEN 2
0
0 0

DMA2LPEN Res. SYSCFGEN TIM8EN CRSEN TIM3EN Res. GPIOBEN 1

0 0 0 0 0 0 0 0 0 0

1 1
1
0 0
0 0 0 0 0 0 0 0 0 0 0

DMA1LPEN MDMALPEN Res. TIM1EN Res. TIM2EN Res. GPIOAEN

RM0433

0
 to
0x118
0x114
0x110

0x130
0x108
0x104

0x120
0x11C
0x10C
Offset
RM0433

RCC_
RCC_
RCC_
RCC_
RCC_
RCC_
RCC_

reserved
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

APB4LPENR
APB2LPENR
APB3LPENR
AHB4LPENR
AHB2LPENR

APB1LLPENR

APB1HLPENR
Register name

Res. Res. Res. UART8LPEN Res. Res. SRAM3LPEN 31

Res. Res. Res. UART7LPEN Res. Res. SRAM2LPEN 30

1 1 1
1 1 1
Res. HRTIMLPEN Res. DAC12LPEN Res. SRAM4LPEN SRAM1LPEN 29

1 1
1 1
Res. DFSDM1LPEN Res. Res. Res. BKPRAMLPEN Res. 28

1
Res. Res. Res. CECLPEN Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25

1
Res. SAI3LPEN Res. Res. Res. ADC3LPEN Res. 24
Res. SAI2LPEN Res. I2C3LPEN Res. Res. Res. 23

1 1 1
Res. SAI1LPEN Res. I2C2LPEN Res. Res. Res. 22

1
1
SAI4LPEN Res. Res. I2C1LPEN Res. BDMALPEN Res. 21

1
Res. SPI5LPEN Res. UART5LPEN Res. Res. Res. 20
Res. Res. Res. UART4LPEN Res. 1 CRCLPEN Res. 19
Res. Res. USART3LPEN Res. Res. Res.

RM0433 Rev 8
TIM17LPEN 18
Res. TIM16LPEN Res. USART2LPEN Res. Res. Res. 17

1 1 1
RTCAPBLPEN TIM15LPEN Res. SPDIFRXLPEN Res. Res. Res. 16
VREFLPEN Res. Res. SPI3LPEN Res. Res. Res. 15

Reserved
1 1 1 1 1 1 1 1 1 1

1 1 1
COMP12LPEN Res. Res. SPI2LPEN Res. Res. Res. 14
Res. SPI4LPEN Res. Res. Res. Res. Res. 13

1 1
LPTIM5LPEN SPI1LPEN Res. Res. Res. Res. Res. 12
LPTIM4LPEN Res. Res. Res. Res. Res. Res. 11
LPTIM3LPEN Res. Res. Res. Res. GPIOKLPEN Res. 10

1 1 1 1
1

LPTIM2LPEN Res. Res. LPTIM1LPEN Res. GPIOJLPEN SDMMC2LPEN 9

Table 84. RCC register map and reset values (continued)

1
Res. Res. FDCANLPEN TIM14LPEN Res. GPIOILPEN Res. 8

1
I2C4LPEN Res. Res. TIM13LPEN Res. GPIOHLPEN Res. 7
1

Res. Res. Res. TIM12LPEN WWDG1LPEN GPIOGLPEN RNGLPEN 6

1
SPI6LPEN USART6LPEN MDIOSLPEN TIM7LPEN Res. GPIOFLPEN HASHLPEN 5

1 1
1 1
1 1 1

Res. USART1LPEN OPAMPLPEN TIM6LPEN Res. GPIOELPEN CRYPTLPEN 4

1
1

LPUART1LPEN Res. Res. TIM5LPEN LTDCLPEN GPIODLPEN Res. 3

Res. Res. SWPLPEN TIM4LPEN Res. GPIOCLPEN Res. 2

1
SYSCFGLPEN TIM8LPEN 1 1 CRSLPEN TIM3LPEN Res. GPIOBLPEN Res. 1
1 1 1 1 1 1 1 1 1 1

1 1
1 1 1 1 1 1 1 1 1 1 1
1

Res. TIM1LPEN Res. TIM2LPEN Res. GPIOALPEN CAMITFLPEN

Reset and Clock Control (RCC)

501/3353
0

504
 0x150
0x148
0x144
0x140
0x138
0x134

0x14C
0x13C
Offset

502/3353
RCC_C1_
RCC_C1_
RCC_C1_
RCC_C1_
RCC_C1_
RCC_C1_
RCC_C1_
RCC_C1_

APB2ENR
APB3ENR
AHB4ENR
AHB2ENR
AHB1ENR
AHB3ENR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

APB1LENR

APB1HENR
Register name

Res. Res. UART8EN Res. Res. SRAM3EN Res. Res. 31

Res. Res. UART7EN Res. Res. SRAM2EN Res. Res. 30

0 0 0
0 0 0
HRTIMEN Res. DAC12EN Res. Res. SRAM1EN Res. Res. 29
Reset and Clock Control (RCC)

0 0
0
DFSDM1EN Res. Res. Res. BKPRAMEN Res. Res. Res. 28

0
Res. Res. HDMICECEN Res. Res. Res. USB2OTGHSEN Res. 27
Res. Res. Res. Res. Res. Res. USB1OTGHSULPIEN Res. 26

0 0 0
Res. Res. Res. Res. HSEMEN Res. USB1OTGHSEN Res. 25

0 0
SAI3EN Res. Res. Res. ADC3EN Res. Res. Res. 24
SAI2EN Res. I2C3EN Res. Res. Res. Res. Res. 23

0 0 0
SAI1EN Res. I2C2EN Res. Res. Res. Res. Res. 22

0
Res. Res. I2C1EN Res. BDMAEN Res. Res. Res. 21

0
SPI5EN Res. UART5EN Res. Res. Res. Res. Res. 20

0
Res. Res. UART4EN Res. CRCEN Res. Res. Res. 19
TIM17EN Res. USART3EN Res. Res. Res. Res.

RM0433 Rev 8
Res. 18
TIM16EN Res. USART2EN Res. Res. Res. ETH1RXEN Res. 17

0 0 0
0

TIM15EN Res. SPDIFRXEN Res. Res. Res. ETH1TXEN SDMMC1EN 16

0 0 0

Res. Res. SPI3EN Res. Res. Res. ETH1MACEN Res. 15

0 0 0 0 0 0 0 0 0 0
0

Res. Res. SPI2EN Res. Res. Res. Res. QSPIEN 14

SPI4EN Res. Res. Res. Res. Res. Res. Res. 13

0 0
0

SPI1EN Res. Res. Res. Res. Res. Res. FMCEN 12

Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. GPIOKEN Res. Res. Res. 10
0

Res. Res. LPTIM1EN Res. GPIOJEN SDMMC2EN Res. Res. 9

Table 84. RCC register map and reset values (continued)

0
Res. FDCANEN TIM14EN Res. GPIOIEN Res. Res. Res. 8
Res. Res. TIM13EN Res. GPIOHEN Res. Res. Res. 7

0
Res. Res. TIM12EN WWDG1EN GPIOGEN RNGEN Res. Res. 6
0

USART6EN MDIOSEN TIM7EN Res. GPIOFEN HASHEN ADC12EN JPGDECEN 5

0 0
0 0
0 0 0
0 0

USART1EN OPAMPEN TIM6EN Res. GPIOEEN CRYPTEN Res. DMA2DEN 4

0
Res. Res. TIM5EN LTDCEN GPIODEN Res. Res. Res. 3
Res. SWPEN TIM4EN Res. GPIOCEN Res. Res. Res. 2

0 0
TIM8EN CRSEN TIM3EN Res. GPIOBEN Res. DMA2EN Res. 1

0 0 0 0 0 0 0 0 0 0

0 0
0 0 0 0 0 0 0 0 0 0 0
0
0 0
0

TIM1EN Res. TIM2EN Res. GPIOAEN DCMIEN DMA1EN MDMAEN

RM0433

0
 0x170
0x168
0x164
0x160
0x154

0x158

0x16C
0x15C
Offset
RM0433

reserved

RCC_C1_
RCC_C1_
RCC_C1_
RCC_C1_
RCC_C1_
RCC_C1_
RCC_C1_
APB4ENR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

APB3LPENR
AHB4LPENR
AHB2LPENR
AHB1LPENR
AHB3LPENR

APB1LLPENR
Register name

UART8LPEN Res. Res. SRAM3LPEN Res. AXISRAMLPEN Res. 31

UART7LPEN Res. Res. SRAM2LPEN Res. ITCMLPEN Res. 30

1 1 1
1 1 1
DAC12LPEN Res. SRAM4LPEN SRAM1LPEN Res. DTCM2LPEN Res. 29

1 1
1 1 1 1
Res. Res. BKPRAMLPEN Res. Res. DTCM1LPEN Res. 28

1
CECLPEN Res. Res. Res. USB2OTGHSLPEN Res. Res. 27
Res. Res. Res. Res. USB1OTGHSULPILPEN Res. Res. 26

1 1 1
Res. Res. Res. Res. USB1OTGHSLPEN Res. Res. 25

1
Res. Res. ADC3LPEN Res. Res. Res. Res. 24
I2C3LPEN Res. Res. Res. Res. Res. Res. 23
I2C2LPEN Res. Res. Res. Res. Res. Res. 22

1
0

I2C1LPEN Res. DMA1LPEN Res. Res. Res. SAI4EN 21

UART5LPEN Res. Res. Res. Res. Res. Res. 20

1
UART4LPEN Res. CRCLPEN Res. Res. Res. Res. 19
USART3LPEN Res. Res. Res. Res. Res. Res.

RM0433 Rev 8
18
USART2LPEN Res. Res. Res. ETH1RXLPEN Res. Res. 17
1

SPDIFRXLPEN Res. Res. Res. ETH1TXLPEN SDMMC1LPEN RTCAPBEN 16

1 1 1
SPI3LPEN Res. Res. Res. ETH1MACLPEN Res. VREFEN 15
Reserved

1 1 1 1 1 1 1 1 1 1
1
1 0 0

SPI2LPEN Res. Res. Res. Res. QSPILPEN COMP12EN 14

Res. Res. Res. Res. Res. Res. Res. 13
1

Res. Res. Res. Res. Res. FMCLPEN LPTIM5EN 12

Res. Res. Res. Res. Res. Res. LPTIM4EN 11
Res. Res. GPIOKLPEN Res. Res. Res. LPTIM3EN 10

1
0 0 0 0

LPTIM1LPEN Res. GPIOJLPEN SDMMC2LPEN Res. Res. LPTIM2EN 9

Table 84. RCC register map and reset values (continued)

TIM14LPEN Res. GPIOILPEN Res. Res. FLASHLPEN Res. 8

0

TIM13LPEN Res. GPIOHLPEN Res. Res. Res. I2C4EN 7

1
TIM12LPEN WWDG1LPEN GPIOGLPEN RNGLPEN Res. Res. Res. 6
1
0

TIM7LPEN Res. GPIOFLPEN HASHLPEN ADC12LPEN JPGDECLPEN SPI6EN 5

1 1 1
1 1

TIM6LPEN Res. GPIOELPEN CRYPTLPEN Res. DMA2DLPEN Res. 4

0

1
TIM5LPEN LTDCLPEN GPIODLPEN Res. Res. Res. LPUART1EN 3
TIM4LPEN Res. GPIOCLPEN Res. Res. Res. Res. 2
0

TIM3LPEN Res. GPIOBLPEN Res. DMA2LPEN Res. SYSCFGEN 1

1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1
1
1 1
1

TIM2LPEN Res. GPIOALPEN CAMITFLPEN DMA1LPEN MDMALPEN Res.

Reset and Clock Control (RCC)

503/3353
0

504
 to
0x178
0x174

0x180
0x17C

0x1FC
Offset

504/3353
reserved
RCC_C1_
RCC_C1_
RCC_C1_

Reset value
Reset value
Reset value

APB4LPENR
APB2LPENR
APB1HLPENR
Register name

Res. Res. Res. 31

Res. Res. Res. 30
Res. HRTIMLPEN Res. 29

1. Available only on revision Y devices.

2. Available only on revision V devices.
Reset and Clock Control (RCC)

1 1
Res. DFSDM1LPEN Res. 28
Res. Res. Res. 27
Res. Res. Res. 26
Res. Res. Res. 25
Res. SA3LPEN Res. 24
Res. SAI2LPEN Res. 23

1 1 1
Res. SAI1LPEN Res. 22

1
SAI4LPEN Res. Res. 21
Res. 1 SPI5LPEN Res. 20
Res. Res. Res. 19
Res. TIM17LPEN Res.

RM0433 Rev 8
18
Res. TIM16LPEN Res. 17
1 1 1

RTCAPBLPEN TIM15LPEN Res. 16

VREFLPEN Res. Res. 15

Reserved
1 1 1
COMP12LPEN Res. Res. 14
Res. SPI4LPEN Res. 13
1 1

LPTIM5LPEN SPI1LPEN Res. 12

LPTIM4LPEN Res. Res. 11
LPTIM3LPEN Res. Res. 10
1 1 1 1

LPTIM2LPEN Res. Res. 9

Table 84. RCC register map and reset values (continued)

Refer to Section 2.3 on page 129 for the register boundary addresses.
1

Res. Res. FDCANLPEN 8

1

I2C4LPEN Res. Res. 7

Res. Res. Res. 6
1

SPI6LPEN USART6LPEN MDIOSLPEN 5

1 1
1 1

Res. USART1LPEN OPAMPLPEN 4

1

LPUART1LPEN Res. Res. 3

Res. Res. SWPLPEN 2
1
1 1

SYSCFGLPEN TIM8LPEN CRSLPEN 1

1 1

Res. TIM1LPEN Res.

RM0433

0
RM0433 Clock recovery system (CRS)

9 Clock recovery system (CRS)

9.1 Introduction
The clock recovery system (CRS) is an advanced digital controller acting on the internal
fine-granularity trimmable RC oscillator HSI48. The CRS provides powerful means to
evaluate the oscillator output frequency, based on comparison with a selectable
synchronization signal. The CRS is capable of automatic trimming adjustments based on
the measured frequency error value, while keeping the possibility of a manual trimming.
The CRS is ideally suited to provide a precise clock to the USB peripheral. In this case, the
synchronization signal can be derived from the start-of-frame (SOF) packet signalization on
the USB bus, sent by a USB host at 1 ms intervals.
The synchronization signal can also be derived from the LSE oscillator output, or generated
by user software.

9.2 CRS main features

• Selectable synchronization source with programmable prescaler and polarity:
– USB2 SOF packet reception
– LSE oscillator output
– USB1 SOF packet reception
• Possibility to generate synchronization pulses by software
• Automatic oscillator trimming capability with no need of CPU action
• Manual control option for faster startup convergence
• 16-bit frequency error counter with automatic error value capture and reload
• Programmable limit for automatic frequency error value evaluation and status reporting
• Maskable interrupts/events:
– Expected synchronization (ESYNC)
– Synchronization OK (SYNCOK)
– Synchronization warning (SYNCWARN)
– Synchronization or trimming error (ERR)

9.3 CRS implementation

Table 85. CRS features
Feature CRS1

TRIM width 6 bits

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Clock recovery system (CRS) RM0433

9.4 CRS functional description

9.4.1 CRS block diagram

Figure 65. CRS block diagram

SYNCSRC SWSYNC

OSC32_IN crs_sync1
LSE SYNC divider
OSC32_OUT crs_sync2 (/1, /2, /4,…,/128)
crs_sync0 SYNC
OTG_HS_DP
OTG_HS1
OTG_HS_DM

OTG_FS_DP
FELIM
OTG_HS2
OTG_FS_DM

crs_it

32-bit TRIM FEDIR FECAP

AHB bus

crs_pclk
crs_trim[0:5]

RCC
HSI48 hsi48_ck
16-bit counter

RELOAD
CRS
To OTG_HS1 and OTG_HS2
MSv50656V1

9.5 CRS internal signals

Table 86 gives the list of CRS internal signals.

Table 86. CRS internal input/output signals

Signal name Signal type Description

crs_it Digital output CRS interrupt

crs_pclk Digital input AHB bus clock
hsi48_ck Digital input HSI48 oscillator clock

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RM0433 Clock recovery system (CRS)

Table 86. CRS internal input/output signals (continued)

Signal name Signal type Description

crs_trim[0:5] Digital output HSI48 oscillator smooth trimming value

crs_sync0
crs_sync1 Digital input SYNC signal source selection (or OTG_HS1, or LSE, or OTG_HS2)
crs_sync2

9.5.1 Synchronization input

The CRS synchronization (SYNC) source, selectable through the CRS_CFGR register, can
be the signal from an external signal (SYNC), the LSE clock, the OTG HS1 SOF signal, or
the OTG HS2 SOF signal. This source signal also has a configurable polarity and can then
be divided by a programmable binary prescaler to obtain a synchronization signal in a
suitable frequency range (usually around 1 kHz).
For more information on the CRS synchronization source configuration, refer to
Section 9.8.2.
It is also possible to generate a synchronization event by software, by setting the SWSYNC
bit in the CRS_CR register.

9.5.2 Frequency error measurement

The frequency error counter is a 16-bit down/up counter, reloaded with the RELOAD value
on each SYNC event. .It starts counting down until it reaches the 0 value, where the ESYNC
(expected synchronization) event is generated. Then it starts counting up to the
OUTRANGE limit, where it eventually stops (if no SYNC event is received), and generates a
SYNCMISS event. The OUTRANGE limit is defined as the frequency error limit (FELIM field
of the CRS_CFGR register) multiplied by 128.
When the SYNC event is detected, the actual value of the frequency error counter and its
counting direction are stored in the FECAP (frequency error capture) field and in the FEDIR
(frequency error direction) bit of the CRS_ISR register. When the SYNC event is detected
during the down-counting phase (before reaching the 0 value), it means that the actual
frequency is lower than the target (the TRIM value must be incremented). When it is
detected during the up-counting phase, it means that the actual frequency is higher (the
TRIM value must be decremented).

RM0433 Rev 8 507/3353

516
Clock recovery system (CRS) RM0433

Figure 66. CRS counter behavior

CRS counter value

RELOAD

ESYNC

Down Up

Frequency
OUTRANGE error counter
(128 x FELIM) stopped

WARNING LIMIT
(3 x FELIM)
TOLERANCE LIMIT
(FELIM)

Trimming action: 0 +2 +1 0 -1 -2 0
CRS event: SYNCERR SYNCWARN SYNCOK SYNCWARN

SYNCMISS
MSv32122V1

9.5.3 Frequency error evaluation and automatic trimming

The measured frequency error is evaluated by comparing its value with a set of limits:
• TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register
• WARNING LIMIT, defined as 3 × FELIM value
• OUTRANGE (error limit), defined as 128 × FELIM value
The result of this comparison is used to generate the status indication and also to control the
automatic trimming which is enabled by setting the AUTOTRIMEN bit in the CRS_CR
register:
• When the frequency error is below the tolerance limit, it means that the actual trimming
value in the TRIM field is the optimal one, hence no trimming action is needed.
– SYNCOK status indicated
– TRIM value not changed in AUTOTRIM mode
• When the frequency error is below the warning limit but above or equal to the tolerance
limit, it means that some trimming action is necessary but that adjustment by one
trimming step is enough to reach the optimal TRIM value.
– SYNCOK status indicated
– TRIM value adjusted by one trimming step in AUTOTRIM mode

508/3353 RM0433 Rev 8

RM0433 Clock recovery system (CRS)

• When the frequency error is above or equal to the warning limit but below the error
limit, a stronger trimming action is necessary, and there is a risk that the optimal TRIM
value is not reached for the next period.
– SYNCWARN status indicated
– TRIM value adjusted by two trimming steps in AUTOTRIM mode
• When the frequency error is above or equal to the error limit, the frequency is out of the
trimming range. This can also happen when the SYNC input is not clean, or when
some SYNC pulse is missing (for example when one USB SOF is corrupted).
– SYNCERR or SYNCMISS status indicated
– TRIM value not changed in AUTOTRIM mode
Note: If the actual value of the TRIM field is close to its limits and the automatic trimming can force
it to overflow or underflow, the TRIM value is set to the limit, and the TRIMOVF status is
indicated.
In AUTOTRIM mode (AUTOTRIMEN bit set in the CRS_CR register) the TRIM field of
CRS_CR is adjusted by hardware and is read-only.

9.5.4 CRS initialization and configuration

RELOAD value
The RELOAD value must be selected according to the ratio between the target frequency
and the frequency of the synchronization source after prescaling. This value is decreased
by 1, to reach the expected synchronization on the 0 value. The formula is the following:
RELOAD = (fTARGET / fSYNC) - 1
The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a
synchronization signal frequency of 1 kHz (SOF signal from USB).

FELIM value
The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics
and its typical trimming step size. The optimal value corresponds to half of the trimming step
size, expressed as a number of oscillator clock ticks. The following formula can be used:
FELIM = (fTARGET / fSYNC) * STEP[%] / 100% / 2
The result must be always rounded up to the nearest integer value to obtain the best
trimming response. If frequent trimming actions are not needed in the application, the
hysteresis can be increased by slightly increasing the FELIM value.
The reset value of the FELIM field corresponds to (fTARGET / fSYNC) = 48000, and to a typical
trimming step size of 0.14%.
Note: The trimming step size depends upon the product, check the datasheet for accurate setting.
Caution: There is no hardware protection from a wrong configuration of the RELOAD and FELIM
fields, this can lead to an erratic trimming response. The expected operational mode
requires proper setup of the RELOAD value (according to the synchronization source
frequency), which is also greater than 128 * FELIM value (OUTRANGE limit).

RM0433 Rev 8 509/3353

516
Clock recovery system (CRS) RM0433

9.6 CRS low-power modes

Table 87. Effect of low-power modes on CRS
Mode Description

Sleep No effect. CRS interrupts cause the device to exit the Sleep mode.
CRS registers are frozen. The CRS stops operating until the Stop mode is exited and the
Stop
HSI48 oscillator is restarted.
Standby The CRS peripheral is powered down and must be reinitialized after exiting Standby mode.

9.7 CRS interrupts

Table 88. Interrupt control bits
Enable Clear
Interrupt event Event flag
control bit flag bit

Expected synchronization ESYNCF ESYNCIE ESYNCC

Synchronization OK SYNCOKF SYNCOKIE SYNCOKC
Synchronization warning SYNCWARNF SYNCWARNIE SYNCWARNC
Synchronization or trimming error
ERRF ERRIE ERRC
(TRIMOVF, SYNCMISS, SYNCERR)

510/3353 RM0433 Rev 8

RM0433 Clock recovery system (CRS)

9.8 CRS registers

Refer to Section 1.2 on page 101 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed only by words (32-bit).

9.8.1 CRS control register (CRS_CR)

Address offset: 0x00
Reset value: 0x0000 2000
Reset value: 0x0000 4000 (products supporting 7-bit TRIM width)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SW AUTO ESYNCI SYNC SYNC
Res. Res. TRIM[5:0] CEN Res. ERRIE
SYNC TRIMEN E WARNIE OKIE
rw rw rw rw rw rw rt_w1 rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:8 TRIM[5:0]: HSI48 oscillator smooth trimming
These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be
programmed to adjust to variations in voltage and temperature that influence the oscillator
frequency.
The default value is 32, corresponding to the middle of the trimming interval. The trimming
step is specified in the product datasheet. A higher TRIM value corresponds to a higher
output frequency.
When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only.
Bit 7 SWSYNC: Generate software SYNC event
This bit is set by software in order to generate a software SYNC event. It is automatically
cleared by hardware.
0: No action
1: A software SYNC event is generated.
Bit 6 AUTOTRIMEN: Automatic trimming enable
This bit enables the automatic hardware adjustment of TRIM bits according to the measured
frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The
TRIM value can be adjusted by hardware by one or two steps at a time, depending on the
measured frequency error value. Refer to Section 9.5.3 for more details.
0: Automatic trimming disabled, TRIM bits can be adjusted by the user.
1: Automatic trimming enabled, TRIM bits are read-only and under hardware control.
Bit 5 CEN: Frequency error counter enable
This bit enables the oscillator clock for the frequency error counter.
0: Frequency error counter disabled
1: Frequency error counter enabled
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.
Bit 4 Reserved, must be kept at reset value.

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Clock recovery system (CRS) RM0433

Bit 3 ESYNCIE: Expected SYNC interrupt enable

0: Expected SYNC (ESYNCF) interrupt disabled
1: Expected SYNC (ESYNCF) interrupt enabled
Bit 2 ERRIE: Synchronization or trimming error interrupt enable
0: Synchronization or trimming error (ERRF) interrupt disabled
1: Synchronization or trimming error (ERRF) interrupt enabled
Bit 1 SYNCWARNIE: SYNC warning interrupt enable
0: SYNC warning (SYNCWARNF) interrupt disabled
1: SYNC warning (SYNCWARNF) interrupt enabled
Bit 0 SYNCOKIE: SYNC event OK interrupt enable
0: SYNC event OK (SYNCOKF) interrupt disabled
1: SYNC event OK (SYNCOKF) interrupt enabled

9.8.2 CRS configuration register (CRS_CFGR)

This register can be written only when the frequency error counter is disabled (CEN bit is
cleared in CRS_CR). When the counter is enabled, this register is write-protected.
Address offset: 0x04
Reset value: 0x2022 BB7F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCPOL Res. SYNCSRC[1:0] Res. SYNCDIV[2:0] FELIM[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SYNCPOL: SYNC polarity selection

This bit is set and cleared by software to select the input polarity for the SYNC signal source.
0: SYNC active on rising edge (default)
1: SYNC active on falling edge
Bit 30 Reserved, must be kept at reset value.
Bits 29:28 SYNCSRC[1:0]: SYNC signal source selection
These bits are set and cleared by software to select the SYNC signal source.
00: USB2 SOF selected as SYNC signal source
01: LSE selected as SYNC signal source
10: OTG HS1 SOF selected as SYNC signal source (default)
11: Reserved
When using USB LPM (Link Power Management) and the device is in Sleep mode, the
periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
provided to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required
clock precision after waking up from Sleep mode, the LSE clock or the SYNC pin should be
used as SYNC signal.
Bit 27 Reserved, must be kept at reset value.

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RM0433 Clock recovery system (CRS)

Bits 26:24 SYNCDIV[2:0]: SYNC divider

These bits are set and cleared by software to control the division factor of the SYNC signal.
000: SYNC not divided (default)
001: SYNC divided by 2
010: SYNC divided by 4
011: SYNC divided by 8
100: SYNC divided by 16
101: SYNC divided by 32
110: SYNC divided by 64
111: SYNC divided by 128
Bits 23:16 FELIM[7:0]: Frequency error limit
FELIM contains the value to be used to evaluate the captured frequency error value latched
in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 9.5.3 for more details
about FECAP evaluation.
Bits 15:0 RELOAD[15:0]: Counter reload value
RELOAD is the value to be loaded in the frequency error counter with each SYNC event.
Refer to Section 9.5.2 for more details about counter behavior.

9.8.3 CRS interrupt and status register (CRS_ISR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECAP[15:0]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM SYNC SYNC SYNC SYNC
FEDIR Res. Res. Res. Res. Res. Res. Res. Res. ESYNCF ERRF
OVF MISS ERR WARNF OKF
r r r r r r r r

Bits 31:16 FECAP[15:0]: Frequency error capture

FECAP is the frequency error counter value latched in the time of the last SYNC event.
Refer to Section 9.5.3 for more details about FECAP usage.
Bit 15 FEDIR: Frequency error direction
FEDIR is the counting direction of the frequency error counter latched in the time of the last
SYNC event. It shows whether the actual frequency is below or above the target.
0: Up-counting direction, the actual frequency is above the target
1: Down-counting direction, the actual frequency is below the target
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 TRIMOVF: Trimming overflow or underflow
This flag is set by hardware when the automatic trimming tries to over- or under-flow the
TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is
cleared by software by setting the ERRC bit in the CRS_ICR register.
0: No trimming error signaled
1: Trimming error signaled

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Clock recovery system (CRS) RM0433

Bit 9 SYNCMISS: SYNC missed

This flag is set by hardware when the frequency error counter reaches value FELIM * 128
and no SYNC is detected, meaning either that a SYNC pulse was missed, or the frequency
error is too big (internal frequency too high) to be compensated by adjusting the TRIM value,
hence some other action must be taken. At this point, the frequency error counter is stopped
(waiting for a next SYNC), and an interrupt is generated if the ERRIE bit is set in the
CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.
0: No SYNC missed error signaled
1: SYNC missed error signaled
Bit 8 SYNCERR: SYNC error
This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the
measured frequency error is greater than or equal to FELIM * 128. This means that the
frequency error is too big (internal frequency too low) to be compensated by adjusting the
TRIM value, and that some other action has to be taken. An interrupt is generated if the
ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in
the CRS_ICR register.
0: No SYNC error signaled
1: SYNC error signaled
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 ESYNCF: Expected SYNC flag
This flag is set by hardware when the frequency error counter reached a zero value. An
interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by
software by setting the ESYNCC bit in the CRS_ICR register.
0: No expected SYNC signaled
1: Expected SYNC signaled
Bit 2 ERRF: Error flag
This flag is set by hardware in case of any synchronization or trimming error. It is the logical
OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE
bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit
in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits.
0: No synchronization or trimming error signaled
1: Synchronization or trimming error signaled
Bit 1 SYNCWARNF: SYNC warning flag
This flag is set by hardware when the measured frequency error is greater than or equal to
FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency
error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the
SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCWARNC bit in the CRS_ICR register.
0: No SYNC warning signaled
1: SYNC warning signaled
Bit 0 SYNCOKF: SYNC event OK flag
This flag is set by hardware when the measured frequency error is smaller than FELIM * 3.
This means that either no adjustment of the TRIM value is needed or that an adjustment by
one trimming step is enough to compensate the frequency error. An interrupt is generated if
the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCOKC bit in the CRS_ICR register.
0: No SYNC event OK signaled
1: SYNC event OK signaled

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RM0433 Clock recovery system (CRS)

9.8.4 CRS interrupt flag clear register (CRS_ICR)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC SYNC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ESYNCC ERRC
WARNC OKC
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 ESYNCC: Expected SYNC clear flag
Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.
Bit 2 ERRC: Error clear flag
Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
the ERRF flag in the CRS_ISR register.
Bit 1 SYNCWARNC: SYNC warning clear flag
Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.
Bit 0 SYNCOKC: SYNC event OK clear flag
Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.

9.8.5 CRS register map

Table 89. CRS register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SYNCWARNIE
AUTOTRIMEN

SYNCOKIE
SWSYNC

ESYNCIE
ERRIE
CEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

CRS_CR TRIM[5:0]
0x00

Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0
SYNCPOL

SYNC SYNC
Res.

Res.

CRS_CFGR SRC DIV FELIM[7:0] RELOAD[15:0]

0x04 [1:0] [2:0]

Reset value 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1
SYNCWARNF
SYNCMISS
SYNCERR

SYNCOKF
TRIMOVF

ESYNCF
FEDIR

ERRF
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

CRS_ISR FECAP[15:0]
0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 89. CRS register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SYNCWARNC
SYNCOKC
ESYNCC
ERRC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRS_ICR
0x0C

Reset value 0 0 0 0

Refer to Section 2.3 on page 129 for the register boundary addresses.

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RM0433 Hardware semaphore (HSEM)

10 Hardware semaphore (HSEM)

10.1 Introduction
The hardware semaphore block provides 32 (32-bit) register based semaphores.
The semaphores can be used to ensure synchronization between different processes
running on the core. The HSEM provides a non-blocking mechanism to lock semaphores in
an atomic way. The following functions are provided:
• Semaphore lock, in two ways:
– 2-step lock: by writing MASTERID and PROCID to the semaphore, followed by a
read check
– 1-step lock: by reading the MASTERID from the semaphore
• Interrupt generation when a semaphore is unlocked
– Each semaphore may generate an interrupt
• Semaphore clear protection
– A semaphore is only unlocked when MASTERID and PROCID match
• Global semaphore clear per MASTERID

10.2 Main features

The HSEM includes the following features:
• 32 (32-bit) semaphores
• 8-bit PROCID
• 4-bit MASTERID
• One interrupt line
• Lock indication

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10.3 Functional description

10.3.1 HSEM block diagram

As shown in Figure 67, the HSEM is based on three sub-blocks:
• the semaphore block containing the semaphore status and IDs
• the semaphore interface block providing AHB access to the semaphore via the
HSEM_Rx and HSEM_RLRx registers
• the interrupt interface block providing control for the interrupts via HSEM_ISR,
HSEM_IER, HSEM_MISR, and HSEM_ICR registers.

Figure 67. HSEM block diagram

HSEM Interrupt interface

32-bit AHB bus

Bus master ID
Semaphore interface

Semaphore block 1
Sem_Ints
HSEM_R0

HSEM_MISR
Semaphore 0

HSEM_ISR

HSEM_IER
HSEM_RLR0
1 hsem_int_it
hsem_hclk Sem_Ints
HSEM_R1
Semaphore 1
HSEM_RLR1

1
Sem_Ints
HSEM_Rx
Semaphore x
HSEM_RLRx HSEM_ICR

MSv41950V3

10.3.2 HSEM internal signals

Table 90. HSEM internal input/output signals

Signal name Signal type Description

AHB bus Digital input/output AHB register access bus

BusMasterID Digital input AHB bus master ID
hsem_int_it Digital output Interrupt line

10.3.3 HSEM lock procedures

There are two lock procedures, namely 2-step (write) lock and 1-step (read) lock. The two
procedures can be used concurrently.

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The semaphore is free when its LOCK bit is 0. In this case, the MASTERID and PROCID
are also 0. When the LOCK bit is 1, the semaphore is locked and the MASTERID indicates
which AHB bus master ID has locked it. The PROCID indicates which process of that AHB
bus master ID has locked the semaphore.
When write locking a semaphore, the written MASTERID must match the AHB bus master
ID , and the PROCID is written by the AHB bus master software process taking the lock.
When read locking the semaphore, the MASTERID is taken from the AHB bus master ID,
and the PROCID is forced to 0 by hardware. There is no PROCID available with read lock.

Figure 68. Procedure state diagram

WRITE (MASTERID & PROCID & LOCK = 1) WRITE (LOCK = 1)
or or
WRITE (LOCK = 0) READ LOCK WRITE (MASTERID or PROCID)
Lock

Free Locked

READ
Unlock or
READ
WRITE (MASTERID & PROCID & LOCK = 0) READ LOCK
MSv41949V3

2-step (write) lock procedure

The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
check if the lock has been successful, carried out from the HSEM_Rx register.
• Write semaphore with PROCID and MASTERID, and LOCK = 1. The MASTERID data
written by software must match the AHB bus master information, that is, a AHB bus
master ID = 1writes data MASTERID = 1.
Lock is put in place when the semaphore is free at write time.
• Read-back the semaphore
The software checks the lock status, if PROCID and MASTERID match the written
data, then the lock is confirmed.
• Else retry (the semaphore has been locked by another process).
A semaphore can only be locked when it is free.
A semaphore can be locked when the PROCID = 0.
Consecutive write attempts with LOCK = 1 to a locked semaphore are ignored.

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1-step (read) lock procedure

The 1-step procedure consists in a read to lock and check the semaphore in a single step,
carried out from the HSEM_RLRx register.
• Read lock semaphore with the AHB bus master MASTERID.
• If read MASTERID matches and PROCID = 0, then lock is put in place. If MASTERID
matches and PROCID is not 0, this means that another process from the same
MASTERID has locked the semaphore with a 2-step (write) procedure.
• Else retry (the semaphore has been locked by another process).
A semaphore can only be locked when it is free. When read locking a free semaphore,
PROCID is 0. Read locking a locked semaphore returns the MASTERID and PROCID that
locked it. All read locks, including the first one that locks the semaphore, return the
MASTERID that locks or locked the semaphore.
Note: The 1-step procedure must not be used when running multiple processes of the same AHB
bus master ID. All processes using the same semaphore read the same status. When only
one process locks the semaphore, each process of that AHB bus master ID reads the
semaphore as locked by itself with the MASTERID.

10.3.4 HSEM write/read/read lock register address

For each semaphore, two AHB register addresses are provided, separated in two banks of
32-bit semaphore registers, spaced by a 0x80 address offset.
In the first register address bank the semaphore can be written (locked/unlocked) and read
through the HSEM_Rx registers.
In the second register address bank the semaphore can be read (locked) through the
HSEM_RLRx registers.

10.3.5 HSEM unlock procedures

Unlocking a semaphore is a protected process, to prevent accidental clearing by a AHB bus
master ID or by a process not having the semaphore lock right. The procedure consists in
writing to the semaphore HSEM_Rx register with the corresponding MASTERID and
PROCID and LOCK = 0. When unlocked the semaphore, the MASTERID, and the PROCID
are all 0.
When unlocked, an interrupt may be generated to signal the event. To this end, the
semaphore interrupt must be enabled.
The unlock procedure consists in a write to the semaphore HSEM_Rx register with
matching MASTERID regardless on how the semaphore has been locked (1- or 2-step).
• Write semaphore with PROCID, MASTERID, and LOCK = 0
• If the written data matches the semaphore PROCID and MASTERID and the AHB bus
master ID , the semaphore is unlocked and an interrupt may be generated when
enabled, else write is ignored, semaphore remains locked and no interrupt is generated
(the semaphore is locked by another process or the written data does not match the
AHB bus master signaling).
Note: Different processes of the AHB bus master ID can write any PROCID value. Preventing
other processes of the AHB bus master ID from unlocking a semaphore must be ensured
by software, handling the PROCID correctly.

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RM0433 Hardware semaphore (HSEM)

10.3.6 HSEM MASTERID semaphore clear

All semaphores locked by a MASTERID can be unlocked at once by using the HSEM_CR
register. Write MASTERID and correct KEY value in HSEM_CR. All locked semaphores with
a matching MASTERID are unlocked, and may generate an interrupt when enabled.
An interrupt may be generated for the unlocked semaphore(s). To this end, the semaphore
interrupt must be enabled in the HSEM_IER register.

10.3.7 HSEM interrupts

An interrupt line hsem_int_it allows each semaphore to generate an interrupt.
An interrupt line provides the following features per semaphore:
• interrupt enable
• interrupt clear
• interrupt status
• masked interrupt status
With the interrupt enable (HSEM_IER) the semaphores affecting the interrupt line can be
enabled. Disabled (masked) semaphore interrupts do not set the masked interrupt status
MISF for that semaphore, and do not generate an interrupt on the interrupt line.
The interrupt clear (HSEM_ICR) clears the interrupt status ISF and masked interrupt status
MISF of the associated semaphore for the interrupt line.
The interrupt status (HSEM_ISR) mirrors the semaphore interrupt status ISF before the
enable.
The masked interrupt status (HSEM_MISR) only mirrors the semaphore enabled interrupt
status MISF on the interrupt line. All masked interrupt status MISF of the enabled
semaphores need to be cleared to clear the interrupt line.

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Figure 69. Interrupt state diagram

Semaphore x
locked

WRITE
(MASTERID & PROCID & LOCK = 0)

Interrupt
Semaphore x
Status = 1

No Interrupt
Semaphore x
Enabled

Yes

Interrupt
Semaphore x
MaskedStatus = 1 & Interrupt x generated

Semaphore x free
MSv41951V3

The procedure to get an interrupt when a semaphore becomes free is described hereafter.

Try to lock semaphore x

• If the semaphore lock is obtained, no interrupt is needed.
• If the semaphore lock fails:
• Clear pending semaphore x interrupt status for the interrupt line in HSEM_ICR.
Re-try to lock the semaphore x again:
– If the semaphore lock is obtained, no interrupt is needed (semaphore has been
freed between first try to lock and clear semaphore interrupt status).
– If the semaphore lock fails, enable the semaphore x interrupt in HSEM_IER.

On semaphore x free interrupt, try to lock semaphore x

• If the semaphore lock is obtained:
Disable the semaphore x interrupt in HSEM_IER.
Clear pending semaphore x interrupt status in HSEM_ICR.
• If the semaphore x lock fails:
Clear pending semaphore x interrupt status in HSEM_ICR.
Try again to lock the semaphore x:
– If the semaphore lock is obtained (semaphore has been freed between first try to
lock and semaphore interrupt status clear), disable the semaphore interrupt in
HSEM_IER.

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RM0433 Hardware semaphore (HSEM)

– If the semaphore lock fails, wait for semaphore free interrupt.

Note: An interrupt does not lock the semaphore. After an interrupt, either the AHB bus master or
the process must still perform the lock procedure to lock the semaphore.

10.3.8 AHB bus master ID verification

The HSEM allows only authorized AHB bus master ID to lock and unlock semaphores.
• The AHB bus master 2-step lock write access to the semaphore HSEM_Rx register is
checked against the valid bus master ID.
– Accesses from unauthorized AHB bus master IDs are discarded and do not lock
the semaphore.
• The AHB bus master 1-step lock read access from the semaphore HSEM_RLRx
register is checked against the valid bus master ID.
– An unauthorized AHB bus master ID read from HSEM_RLRx returns all 0.
• The semaphore unlock write access to the HSEM_CR register is checked against the
valid bus master ID. Only the valid bus master ID can write to the HSEM_CR register
and unlock any of the MASTERID semaphores.
– Accesses from unauthorized AHB bus master IDs are discarded and do not clear
the MASTERID semaphores.
Table 91 details the relation between bus master/processor and MASTERID.

Table 91. Authorized AHB bus master ID

Bus master 0 (CPU)

MASTERID = 3

Note: Accesses from unauthorized AHB bus master IDs to other registers are granted.

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10.4 HSEM registers

Registers must be accessed using word format. Byte and half-word accesses are ignored
and have no effect on the semaphores, they generate a bus error.

10.4.1 HSEM register semaphore x (HSEM_Rx)

Address offset: 0x000 + 0x4 * x (x = 0 to 31)
Reset value: 0x0000 0000
The HSEM_Rx must be used to perform a 2-step write lock, read back, and for unlocking a
semaphore. Only write accesses with authorized AHB bus master ID is granted. Write
accesses with unauthorized AHB bus master IDs are discarded.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. MASTERID[3:0] PROCID[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 LOCK: Lock indication

This bit can be written and read by software.
0: On write free semaphore (only when MASTERID and PROCID match), on read
semaphore is free.
1: On write try to lock semaphore, on read semaphore is locked.
Bits 30:13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.
Bits 11:8 MASTERID[3:0]: Semaphore MASTERID
Written by software
- When the semaphore is free and the LOCK bit is at the same time written to 1 and the
MASTERID matches the AHB bus master ID.
- When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched
MASTERID, the MASTERID is cleared to 0.
- When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not
match MASTERID, the MASTERID is not affected.
- Write when LOCK bit is already 1 (semaphore locked), the MASTERID is not affected.
- An authorized read returns the stored MASTERID value.
Bits 7:0 PROCID[7:0]: Semaphore PROCID
Written by software
-When the semaphore is free and the LOCK is written to 1, and the MASTERID matches the
AHB bus master ID, PROCID is set to the written data.
- When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched
MASTERID, the PROCID is cleared to 0.
- When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not
match MASTERID, the PROCID is not affected.
- Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected.
- An authorized read returns the stored PROCID value.

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RM0433 Hardware semaphore (HSEM)

10.4.2 HSEM read lock register semaphore x (HSEM_RLRx)

Address offset: 0x080 + 0x4 * x (x = 0 to 31)
Reset value: 0x0000 0000
Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx must be used to perform
a 1-step read lock. Only read accesses with authorized AHB bus master ID is granted. Read
accesses with unauthorized AHB bus master IDs are discarded and return 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. MASTERID[3:0] PROCID[7:0]
r r r r r r r r r r r r

Bit 31 LOCK: Lock indication

This bit is read only by software at this address.
- When the semaphore is free:
A read with a valid AHB bus master ID locks the semaphore and returns 1.
- When the semaphore is locked:
A read with a valid AHB bus master ID returns 1 (the MASTERID and PROCID reflect the
already locked semaphore information).
Bits 30:13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.
Bits 11:8 MASTERID[3:0]: Semaphore MASTERID
This field is read only by software at this address.
On a read, when the semaphore is free, the hardware sets the MASTERID to the AHB bus
master ID reading the semaphore. The MASTERID of the AHB bus master locking the
semaphore is read.
On a read when the semaphore is locked, this field returns the MASTERID of the AHB bus
master that has locked the semaphore.
Bits 7:0 PROCID[7:0]: Semaphore processor ID
This field is read only by software at this address.
- On a read when the semaphore is free:
A read with a valid AHB bus master ID locks the semaphore and hardware sets the PROCID
to 0.
- When the semaphore is locked:
A read with a valid AHB bus master ID returns the PROCID of the AHB bus master that has
locked the semaphore.

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10.4.3 HSEM interrupt enable register (HSEM_IER)

Address offset: 0x100
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISE[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISE[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 ISE[31:0]: Interrupt semaphore x enable bit (x = 0 to 31)

This bit is read and written by software.
0: Interrupt generation for semaphore x disabled (masked)
1: Interrupt generation for semaphore x enabled (not masked)

10.4.4 HSEM interrupt clear register (HSEM_ICR)

Address offset: 0x104
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISC[31:16]
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISC[15:0]
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:0 ISC[31:0]: Interrupt semaphore x clear bit (x = 0 to 31)

This bit is written by software, and is always read 0.
0: Interrupt semaphore x status ISFx and masked status MISFx not affected.
1: Interrupt semaphore x status ISFx and masked status MISFx cleared.

10.4.5 HSEM interrupt status register (HSEM_ISR)

Address offset: 0x108
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISF[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISF[15:0]
r r r r r r r r r r r r r r r r

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Bits 31:0 ISF[31:0]: Interrupt semaphore x status bit before enable (mask) (x = 0 to 31)
This bit is set by hardware, and reset only by software. This bit is cleared by software writing
the corresponding HSEM_ICR bit.
0: Interrupt semaphore x status, no interrupt pending
1: Interrupt semaphore x status, interrupt pending

10.4.6 HSEM interrupt status register (HSEM_MISR)

Address offset: 0x10C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MISF[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISF[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 MISF[31:0]: Masked interrupt semaphore x status bit after enable (mask) (x = 0 to 31)
This bit is set by hardware and read only by software. This bit is cleared by software writing
the corresponding HSEM_ICR bit. This bit is read as 0 when semaphore x status is masked
in HSEM_IER bit x.
0: interrupt semaphore x status after masking not pending
1: interrupt semaphore x status after masking pending

10.4.7 HSEM clear register (HSEM_CR)

Address offset: 0x140
Reset value: 0x0000 0000
Only write accesses with authorized AHB bus master ID are granted. Write accesses with
unauthorized AHB bus master ID are discarded.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[15:0]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. MASTERID[3:0] Res. Res. Res. Res. Res. Res. Res. Res.
w w w w

Bits 31:16 KEY[15:0]: Semaphore clear key

This field can be written by software and is always read 0.
If this key value does not match HSEM_KEYR.KEY, semaphores are not affected.
If this key value matches HSEM_KEYR.KEY, all semaphores matching the MASTERID are
cleared to the free state.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.

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Bits 11:8 MASTERID[3:0]: MASTERID of semaphores to be cleared

This field can be written by software and is always read 0.
This field indicates the MASTERID for which the semaphores are cleared when writing the
HSEM_CR.
Bits 7:0 Reserved, must be kept at reset value.

10.4.8 HSEM clear semaphore key register (HSEM_KEYR)

Address offset: 0x144
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:16 KEY[15:0]: Semaphore clear key

This field can be written and read by software.
Key value to match when clearing semaphores.
Bits 15:0 Reserved, must be kept at reset value.

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RM0433 Hardware semaphore (HSEM)

10.4.9 HSEM register map

Table 92. HSEM register map and reset values

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
LOCK MASTERID
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HSEM_R0 PROCID[7:0]
0x000 [3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0
LOCK

MASTERID
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HSEM_R1 PROCID[7:0]
0x004 [3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0

...
LOCK

MASTERID
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HSEM_R31 PROCID[7:0]
0x07C [3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0
LOCK

MASTERID
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HSEM_RLR0 PROCID
0x080 [3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0
LOCK

MASTERID
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HSEM_RLR1 PROCID[7:0]
0x084 [3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0
...
LOCK

MASTERID
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HSEM_RLR31 PROCID[7:0]
0x0FC [3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0

HSEM_IER ISE[31:0]
0x100

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HSEM_ICR ISC[31:0]
0x104

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HSEM_ISR ISF[31:0]
0x108

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HSEM_MISR MISF[31:0]
0x10C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MASTERID[3:
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

HSEM_CR KEY[15:0]
0x140 0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

HSEM_KEYR KEY[15:0]
0x144
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 129 for the register boundary addresses.

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General-purpose I/Os (GPIO) RM0433

11 General-purpose I/Os (GPIO)

11.1 Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition
all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).

11.2 GPIO main features

• Output states: push-pull or open drain + pull-up/down
• Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
• Speed selection for each I/O
• Input states: floating, pull-up/down, analog
• Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
• Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
• Analog function
• Alternate function selection registers
• Fast toggle capable of changing every two clock cycles
• Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions

11.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
• Input floating
• Input pull-up
• Input-pull-down
• Analog
• Output open-drain with pull-up or pull-down capability
• Output push-pull with pull-up or pull-down capability
• Alternate function push-pull with pull-up or pull-down capability
• Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is
to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there
is no risk of an IRQ occurring between the read and the modify access.

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RM0433 General-purpose I/Os (GPIO)

Figure 70 and Figure 71 show the basic structures of a standard and a 5-Volt tolerant I/O
port bit, respectively. Table 93 gives the possible port bit configurations.

Figure 70. Basic structure of an I/O port bit

Analog
To on-chip
peripheral Alternate function input

Input data register on/off

Read VDD
VDD
Bit set/reset registers

Protection
trigger on/off
Pull diode
up
Input driver I/O pin
Output data register

Write

Output driver VDD on/off Protection

Pull
down diode
P-MOS
VSS
Output VSS
control
N-MOS
Read/write
VSS
Push-pull,
From on-chip open-drain or
peripheral Alternate function output
disabled
Analog
ai15938

Figure 71. Basic structure of a 5-Volt tolerant I/O port bit

To on-chip Analog
peripheral
Alternate function input

on/off
Input data register

Read
VDD VDD_FT (1)

TTL Schmitt
Bit set/reset registers

Protection
trigger on/off
Pull diode
up
Input driver I/O pin
Write
Output data register

Output driver VDD on/off Pull Protection

down
diode
P-MOS
Output VSS
VSS
control
Read/write N-MOS

From on-chip VSS

Push-pull,
peripheral Alternate function output open-drain or
disabled
Analog
ai15939b

1. VDD_FT is a potential specific to 5-Volt tolerant I/Os and different from VDD.

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Table 93. Port bit configuration table(1)

MODE(i) OSPEED(i) PUPD(i)
OTYPER(i) I/O configuration
[1:0] [1:0] [1:0]

0 0 0 GP output PP
0 0 1 GP output PP + PU
0 1 0 GP output PP + PD
0 SPEED 1 1 Reserved
01
1 [1:0] 0 0 GP output OD
1 0 1 GP output OD + PU
1 1 0 GP output OD + PD
1 1 1 Reserved (GP output OD)
0 0 0 AF PP
0 0 1 AF PP + PU
0 1 0 AF PP + PD
0 SPEED 1 1 Reserved
10
1 [1:0] 0 0 AF OD
1 0 1 AF OD + PU
1 1 0 AF OD + PD
1 1 1 Reserved
x x x 0 0 Input Floating
x x x 0 1 Input PU
00
x x x 1 0 Input PD
x x x 1 1 Reserved (input floating)
x x x 0 0 Input/output Analog
x x x 0 1
11
x x x 1 0 Reserved
x x x 1 1
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.

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RM0433 General-purpose I/Os (GPIO)

11.3.1 General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in analog mode.
The debug pins are in AF pull-up/pull-down after reset:
• PA15: JTDI in pull-up
• PA14: JTCK/SWCLK in pull-down
• PA13: JTMS/SWDAT in pull-up
• PB4: NJTRST in pull-up
• PB3: JTDO in floating state
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.

11.3.2 I/O pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that
can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to
15) registers:
• After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are
configured in alternate function mode through GPIOx_MODER register.
• The specific alternate function assignments for each pin are detailed in the device
datasheet.
• Cortex-M7 with FPU EVENTOUT is mapped on AF15
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, the user has to proceed as follows:
• Debug function: after each device reset these pins are assigned as alternate function
pins immediately usable by the debugger host
• System function: MCOx pins have to be configured in alternate function mode.
• GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER
register.
• Peripheral alternate function:
– Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.
– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.

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– Configure the desired I/O as an alternate function in the GPIOx_MODER register.

• Additional functions:
– For the ADC and DAC, configure the desired I/O in analog mode in the
GPIOx_MODER register and configure the required function in the ADC and DAC
registers.
– For the additional functions like RTC_OUT, RTC_TS, RTC_TAMPx, WKUPx and
oscillators, configure the required function in the related RTC, PWR and RCC
registers. These functions have priority over the configuration in the standard
GPIO registers. For details about I/O control by the RTC, refer to Section 46.3:
RTC functional description on page 1905.
• EVENTOUT
– Configure the I/O pin used to output the core EVENTOUT signal by connecting it
to AF15.
Refer to the “Alternate function mapping” table in the device datasheet for the detailed
mapping of the alternate function I/O pins.

11.3.3 I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-
pull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pull-
up/pull-down whatever the I/O direction.

11.3.4 I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 11.4.5: GPIO port input data register (GPIOx_IDR) (x = A to K) and
Section 11.4.6: GPIO port output data register (GPIOx_ODR) (x = A to K) for the register
descriptions.

11.3.5 I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i)
resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always

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RM0433 General-purpose I/Os (GPIO)

be accessed directly. The GPIOx_BSRR register provides a way of performing atomic

bitwise handling.
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

11.3.6 GPIO locking mechanism

It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next MCU reset or peripheral reset. Each
GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The LOCK sequence (refer to Section 11.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A to K)) can only be performed using a word (32-bit long) access to the
GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same
time as the [15:0] bits.
For more details refer to LCKR register description in Section 11.4.8: GPIO port
configuration lock register (GPIOx_LCKR) (x = A to K).

11.3.7 I/O alternate function input/output

Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, the user can connect an alternate function to some other pin
as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin refer to the device datasheet.

11.3.8 External interrupt/wake-up lines

All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode.
Refer to Section 20: Extended interrupt and event controller (EXTI) and to Section 20.3:
EXTI functional description.

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11.3.9 Input configuration

When the I/O port is programmed as input:
• The output buffer is disabled
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register provides the I/O state
Figure 72 shows the input configuration of the I/O port bit.

Figure 72. Input floating / pull up / pull down configurations

Input data register

on
Read
VDD VDD
Bit set/reset registers

TTL Schmitt on/off

trigger protection
pull diode
Write up
Output data register

input driver I/O pin

on/off
output driver
pull protection
down diode
VSS VSS
Read/write

ai15940b

11.3.10 Output configuration

When the I/O port is programmed as output:
• The output buffer is enabled:
– Open drain mode: a “0” in the output register activates the N-MOS whereas a “1”
in the output register leaves the port in Hi-Z (the P-MOS is never activated)
– Push-pull mode: a “0” in the output register activates the N-MOS whereas a “1” in
the output register activates the P-MOS
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state
• A read access to the output data register gets the last written value

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RM0433 General-purpose I/Os (GPIO)

Figure 73 shows the output configuration of the I/O port bit.

Figure 73. Output configuration

Input data register

on
Read

TTL Schmitt VDD VDD

Bit set/reset registers

trigger
on/off
Write protection
Input driver diode
Output data register
pull
up
I/O pin
Output driver VDD on/off

P-MOS pull protection

Output down diode
Read/write control VSS
N-MOS VSS
Push-pull or
VSS Open-drain

ai15941b

11.3.11 I/O compensation cell

This cell is used to control the I/O commutation slew rate (tfall / trise) to reduce the I/O noise
on power supply.
The cell is split into two blocks:
• The first block provides an optimal code for the current PVT. The code stored in this
block can be read when the READY flag of the SYSCFG_CCSR is set.
• The second block controls the I/O slew rate.The user selects the code to be applied
and programs it by software.
The I/O compensation cell features 2 voltage ranges: 1.62 to 2.0 V and 2.7 to 3.6 V.

11.3.12 Alternate function configuration

When the I/O port is programmed as alternate function:
• The output buffer can be configured in open-drain or push-pull mode
• The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data)
• The Schmitt trigger input is activated
• The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state

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Figure 74 shows the alternate function configuration of the I/O port bit.

Figure 74. Alternate function configuration

To on-chip Alternate function input

peripheral

Input data register

on

Read
VDD VDD
TTL Schmitt on/off
Bit set/reset registers

trigger protection
Pull diode
Input driver up
Write
Output data register

I/O pin
Output driver VDD on/off

Pull protection
P-MOS down diode
Output
control VSS VSS
N-MOS
Read/write
VSS push-pull or
open-drain
From on-chip
peripheral Alternate function output
ai15942b

11.3.13 Analog configuration

When the I/O port is programmed as analog configuration:
• The output buffer is disabled
• The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• The weak pull-up and pull-down resistors are disabled by hardware
• Read access to the input data register gets the value “0”
Figure 75 shows the high-impedance, analog-input configuration of the I/O port bits.

Figure 75. High impedance-analog configuration

Analog
To on-chip
peripheral
Input data register

Read off
0
VDD
Bit set/reset registers

TTL Schmitt
trigger protection
Write diode
Output data register

Input driver
I/O pin

protection
diode

Read/write VSS

From on-chip Analog

peripheral
ai15943

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RM0433 General-purpose I/Os (GPIO)

Some pins/balls are directly connected to PA0_C, PA1_C, PC2_C and PC3_C ADC analog
inputs (see Figure 76): there is a direct path between Pxy_C and Pxy pins/balls, through an
analog switch (refer to Section 12.3.1: SYSCFG peripheral mode configuration register
(SYSCFG_PMCR) for details on how to configure analog switches).

Figure 76. Analog inputs connected to ADC inputs

PC2_C
PC3_C
PA0_C
PA1_C
To ADC

MODERy [1:0] in The switch default

GPIOx_MODER state depends on
(reset state: open) PxySO bit Reset
value in
To ADC SYSCFG_PMCR
Alternate Function Input
To on-chip peripherals

Input data register

VDD or
On/off VDD VDD_FT(1)
Read

Pull-up
Schmitt
Trigger On/off
Input Driver

PC2
PC3
GPIO

PA0
PA1
Pull-down
VDD On/off
Output data register
Bit Set/Reset
register

Write
OUTPUT
CONTROL VSS VSS

Read / Write
VSS
Push -Pull
Output Driver Open Drain
From on-chip peripherals Alternate Function Output
Disabled
Analog
From analog peripherals

MSv41921V3

1. VDD_FT is a potential specific to 5V tolerant I/Os. It is distinct from VDD.

11.3.14 Using the HSE or LSE oscillator pins as GPIOs

When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register) the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the OSC_IN or
OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be
used as normal GPIO.

11.3.15 Using the GPIO pins in the backup supply domain

The PC13/PC14/PC15/PI8 GPIO functionality is lost when the core supply domain is
powered off (when the device enters Standby mode). In this case, if their GPIO configuration
is not bypassed by the RTC configuration, these pins are set in an analog input mode.

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11.4 GPIO registers

For a summary of register bits, register address offsets and reset values, refer to Table 94.
The peripheral registers can be written in word, half word or byte mode.

11.4.1 GPIO port mode register (GPIOx_MODER)

(x =A to K)
Address offset:0x00
Reset value: 0xABFF FFFF for port A
Reset value: 0xFFFF FEBF for port B
Reset value: 0xFFFF FFFF for other ports

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MODER15[1:0] MODER14[1:0] MODER13[1:0] MODER12[1:0] MODER11[1:0] MODER10[1:0] MODER9[1:0] MODER8[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MODER7[1:0] MODER6[1:0] MODER5[1:0] MODER4[1:0] MODER3[1:0] MODER2[1:0] MODER1[1:0] MODER0[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MODER[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)

11.4.2 GPIO port output type register (GPIOx_OTYPER)

(x = A to K)
Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain

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RM0433 General-purpose I/Os (GPIO)

11.4.3 GPIO port output speed register (GPIOx_OSPEEDR)

(x = A to K)
Address offset: 0x08
Reset value: 0x0C00 0000 (for port A)
Reset value: 0x0000 00C0 (for port B)
Reset value: 0x0000 0000 (for other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15 OSPEEDR14 OSPEEDR13 OSPEEDR12 OSPEEDR11 OSPEEDR10 OSPEEDR9 OSPEEDR8
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7 OSPEEDR6 OSPEEDR5 OSPEEDR4 OSPEEDR3 OSPEEDR2 OSPEEDR1 OSPEEDR0
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 OSPEEDR[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: High speed
11: Very high speed
Note: Refer to the product datasheets for the values of OSPEEDRy bits versus VDD range
and external load.

11.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A to K)
Address offset: 0x0C
Reset value: 0x6400 0000 (for port A)
Reset value: 0x0000 0100 (for port B)
Reset value: 0x0000 0000 (for other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15[1:0] PUPDR14[1:0] PUPDR13[1:0] PUPDR12[1:0] PUPDR11[1:0] PUPDR10[1:0] PUPDR9[1:0] PUPDR8[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7[1:0] PUPDR6[1:0] PUPDR5[1:0] PUPDR4[1:0] PUPDR3[1:0] PUPDR2[1:0] PUPDR1[1:0] PUPDR0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PUPDR[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved

RM0433 Rev 8 541/3353

547
General-purpose I/Os (GPIO) RM0433

11.4.5 GPIO port input data register (GPIOx_IDR)

(x = A to K)
Address offset: 0x10
Reset value: 0x0000 XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 IDR[15:0]: Port x input data I/O pin y (y = 15 to 0)
These bits are read-only. They contain the input value of the corresponding I/O port.

11.4.6 GPIO port output data register (GPIOx_ODR)

(x = A to K)
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ODR[15:0]: Port output data I/O pin y (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to
the GPIOx_BSRR register (x = A..F).

542/3353 RM0433 Rev 8

RM0433 General-purpose I/Os (GPIO)

11.4.7 GPIO port bit set/reset register (GPIOx_BSRR)

(x = A to K)
Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0
w w w w w w w w w w w w w w w w

Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Resets the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Sets the corresponding ODRx bit

11.4.8 GPIO port configuration lock register (GPIOx_LCKR)

(x = A to K)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0433 Rev 8 543/3353

547
General-purpose I/Os (GPIO) RM0433

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = 1 + LCKR[15:0]
WR LCKR[16] = 0 + LCKR[15:0]
WR LCKR[16] = 1 + LCKR[15:0]
RD LCKR
RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns 1 until the next MCU reset or peripheral reset.
Bits 15:0 LCK[15:0]: Port x lock I/O pin y (y = 15 to 0)
These bits are read/write but can only be written when the LCKK bit is 0.
0: Port configuration not locked
1: Port configuration locked

11.4.9 GPIO alternate function low register (GPIOx_AFRL)

(x = A to K)
Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7[3:0] AFR6[3:0] AFR5[3:0] AFR4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3[3:0] AFR2[3:0] AFR1[3:0] AFR0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

544/3353 RM0433 Rev 8

RM0433 General-purpose I/Os (GPIO)

Bits 31:0 AFR[7:0][3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0)
These bits are written by software to configure alternate function I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

11.4.10 GPIO alternate function high register (GPIOx_AFRH)

(x = A to J)
Address offset: 0x2
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15[3:0] AFR14[3:0] AFR13[3:0] AFR12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11[3:0] AFR10[3:0] AFR9[3:0] AFR8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 AFR[15:8][3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8)
These bits are written by software to configure alternate function I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

RM0433 Rev 8 545/3353

547
 0x08
0x08
0x08
0x04
0x00
0x00
0x00

0x0C

546/3353
11.4.11

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

GPIOA_PUPDR
(where x = C..K)
GPIOx_MODER
(where x = C..K)
GPIOB_MODER
GPIOA_MODER

GPIOx_OTYPER
(where x = A to K)

GPIOx_OSPEEDR
GPIOB_OSPEEDR
GPIOA_OSPEEDR
Offset Register name

0
0
0
0
1
1
1
Res. 31
PUPDR15[1:0] OSPEEDR15[1:0] OSPEEDR15[1:0] OSPEEDR15[1:0] MODER15[1:0] MODER15[1:0] MODER15[1:0]

1
0
0
0
1
1
0
Res. 30

1
0
0
0
1
1
1
Res. 29
General-purpose I/Os (GPIO)

PUPDR14[1:0] OSPEEDR14[1:0] OSPEEDR14[1:0] OSPEEDR14[1:0] MODER14[1:0] MODER14[1:0] MODER14[1:0]

0
0
0
0
1
1
0
Res. 28

0
0
0
1
1
1
1
Res. 27
PUPDR13[1:0] OSPEEDR13[1:0] OSPEEDR13[1:0] OSPEEDR13[1:0] MODER13[1:0] MODER13[1:0] MODER13[1:0]
GPIO register map

1
0
0
1
1
1
Res. 0 26

0
0
0
0
1
1
1
Res. 25
PUPDR12[1:0] OSPEEDR12[1:0] OSPEEDR12[1:0] OSPEEDR12[1:0] MODER12[1:0] MODER12[1:0] MODER12[1:0]

0
0
0
0
1
1
1

Res. 24

0
0
0
0
1
1
1

Res. 23
PUPDR11[1:0] OSPEEDR11[1:0] OSPEEDR11[1:0] OSPEEDR11[1:0] MODER11[1:0] MODER11[1:0] MODER11[1:0]

0
0
0
0
1
1
1

Res. 22

0
0
0
0
1
1
1

Res. 21
PUPDR10[1:0] OSPEEDR10[1:0] OSPEEDR10[1:0] OSPEEDR10[1:0] MODER10[1:0] MODER10[1:0] MODER10[1:0]

0
0
0
0
1
1
1

Res. 20

0
0
0
0
1
1
1

Res. 19
PUPDR9[1:0] OSPEEDR9[1:0] OSPEEDR9[1:0] OSPEEDR9[1:0] MODER9[1:0] MODER9[1:0] MODER9[1:0]

0
0
0
0
1
1
1

Res. 18

RM0433 Rev 8
0
0
0
0
1
1
1

Res. 17
PUPDR8[1:0] OSPEEDR8[1:0] OSPEEDR8[1:0] OSPEEDR8[1:0] MODER8[1:0] MODER8[1:0] MODER8[1:0]

0
0
0
0
1
1
1

Res. 16

0
0
0
0
1
1
1

0
OT15 15
PUPDR7[1:0] OSPEEDR7[1:0] OSPEEDR7[1:0] OSPEEDR7[1:0] MODER7[1:0] MODER7[1:0] MODER7[1:0]

0
0
0
0
1
1
1

0
OT14 14

0
0
0
0
1
1
1

0
OT13 13
PUPDR6[1:0] OSPEEDR6[1:0] OSPEEDR6[1:0] OSPEEDR6[1:0] MODER6[1:0] MODER6[1:0] MODER6[1:0]

0
0
0
0
1
1
1

0
OT12 12

0
0
0
0
1
1
1

0 OT11
Table 94. GPIO register map and reset values

PUPDR5[1:0] OSPEEDR5[1:0] OSPEEDR5[1:0] OSPEEDR5[1:0] MODER5[1:0] MODER5[1:0] MODER5[1:0]

11

0
0
0
0
1
1
1

OT10 10
The following table gives the GPIO register map and reset values.

0
0
0
0
1
1
1

OT9 9
PUPDR4[1:0] OSPEEDR4[1:0] OSPEEDR4[1:0] OSPEEDR4[1:0] MODER4[1:0] MODER4[1:0] MODER4[1:0]

0
0
0
0
1
0
1

OT8 8

0
0
1
0
1
1
1

OT7 7
PUPDR3[1:0] OSPEEDR3[1:0] OSPEEDR3[1:0] OSPEEDR3[1:0] MODER3[1:0] MODER3[1:0] MODER3[1:0]

0
0
1
0
1
0
1

OT6 6
0

0
0
0
0
1
1
1

OT5 5
PUPDR2[1:0] OSPEEDR2[1:0] OSPEEDR2[1:0] OSPEEDR2[1:0] MODER2[1:0] MODER2[1:0] MODER2[1:0]
0

0
0
0
0
1
1
1

OT4 4
0

0
0
0
0
1
1
1

OT3 3
PUPDR1[1:0] OSPEEDR1[1:0] OSPEEDR1[1:0] OSPEEDR1[1:0] MODER[1:0] MODER1[1:0] MODER1[1:0]
0

0
0
0
0
1
1
1

OT2 2
0

0
0
0
0
1
1
1

OT1 1
PUPDR0[1:0] OSPEEDR0[1:0] OSPEEDR0[1:0] OSPEEDR0[1:0] MODER0[1:0] MODER0[1:0] MODER0[1:0]
0

0
0
0
0
1
1
1

OT0 0
RM0433
 0x24
0x20
0x18
0x14
0x10

0x1C
0x0C
0x0C
RM0433

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

GPIOx_IDR

GPIOx_ODR

GPIOx_AFRL

GPIOx_AFRH
GPIOx_LCKR
GPIOx_BSRR
GPIOx_PUPDR
GPIOB_PUPDR

(where x = C..K)

(where x = A to K)
(where x = A to K)
(where x = A to K)
(where x = A to K)

(where x = A..I/J/K)
(where x = A..I/J/K)
Offset Register name

0
0
0
0
0
Res. BR15 Res. Res. 31
PUPDR15[1:0] PUPDR15[1:0]

0
0
0
0
Res. BR14 Res. Res. 0 30

0
0
0
0
0
Res. BR13 Res. Res. 29
PUPDR14[1:0] PUPDR14[1:0]

AFR7[3:0]

AFR15[3:0]

0
0
0
0
0

Res. BR12 Res. Res. 28

0
0
0
0
0

Res. BR11 Res. Res. 27

PUPDR13[1:0] PUPDR13[1:0]

0
0
0
0
0

Res. BR10 Res. Res. 26

0
0
0
0
0

Res. BR9 Res. Res. 25

PUPDR12[1:0] PUPDR12[1:0]

AFR6[3:0]

AFR14[3:0]

0
0
0
0
0

Res. BR8 Res. Res. 24

0
0
0
0
0

Res. BR7 Res. Res. 23

PUPDR11[1:0] PUPDR11[1:0]

0
0
0
0
0

Res. BR6 Res. Res. 22

0
0
0
0
0

Res. BR5 Res. Res. 21

PUPDR10[1:0] PUPDR10[1:0]

AFR5[3:0]

AFR13[3:0]

0
0
0
0
0

Res. BR4 Res. Res. 20

0
0
0
0
0

Res. BR3 Res. Res. 19

PUPDR9[1:0] PUPDR9[1:0]

0
0
0
0
0

Res. BR2 Res. Res. 18

RM0433 Rev 8
0
0
0
0
0

Res. BR1 Res. Res. 17

PUPDR8[1:0] PUPDR8[1:0]

AFR4[3:0]

AFR12[3:0]

0
0
0
0
0

0
LCKK BR0 Res. Res. 16
x

0
0
0
0
0

0
0

LCK15 BS15 ODR15 IDR15 15

PUPDR7[1:0] PUPDR7[1:0]
x

0
0
0
0
0

0
0

LCK14 BS14 ODR14 IDR14 14

x

0
0
0
0
0

0
0

LCK13 BS13 ODR13 IDR13 13

PUPDR6[1:0] PUPDR6[1:0]

AFR3[3:0]

AFR11[3:0]
x

0
0
0
0
0

0
0

LCK12 BS12 ODR12 IDR12 12

x

0
0
0
0
0

0
0

LCK11 BS11 ODR11 IDR11 11

PUPDR5[1:0] PUPDR5[1:0]
x

0
0
0
0
0

0
0

LCK10 BS10 ODR10 IDR10 10

x

0
0
0
0
0

0
0

LCK9 BS9 ODR9 IDR9 9

PUPDR4[1:0] PUPDR4[1:0]
AFR2[3:0]

AFR10[3:0]
Table 94. GPIO register map and reset values (continued)

Refer to Section 2.3 on page 129 for the register boundary addresses.
x

0
0
0
0
1

0
0

LCK8 BS8 ODR8 IDR8 8

x

0
0
0
0
0

0
0

LCK7 BS7 ODR7 IDR7 7

PUPDR3[1:0] PUPDR3[1:0]
x

0
0
0
0
0

0
0

LCK6 BS6 ODR6 IDR6 6

x

0
0

0
0
0
0
0

LCK5 BS5 ODR5 IDR5 5

PUPDR2[1:0] PUPDR2[1:0]
AFR9[3:0]
AFR1[3:0]
x

0
0

0
0
0
0
0

LCK4 BS4 ODR4 IDR4 4

x

0
0

0
0
0
0
0

LCK3 BS3 ODR3 IDR3 3

PUPDR1[1:0] PUPDR1[1:0]
x

0
0

0
0
0
0
0

LCK2 BS2 ODR2 IDR2 2

x

0
0

0
0
0
0
0

LCK1 BS1 ODR1 IDR1 1

PUPDR0[1:0] PUPDR0[1:0]
AFR8[3:0]
AFR0[3:0]
x

0
0

0
0
0
0
0

LCK0 BS0 ODR0 IDR0 0

547/3353
General-purpose I/Os (GPIO)

547
System configuration controller (SYSCFG) RM0433

12 System configuration controller (SYSCFG)

12.1 Introduction
The devices feature a set of configuration registers. The objectives of this section is to
describe in details the system configuration controller.

12.2 SYSCFG main features

The system configuration controller main functions are the following:
• Analog switch configuration management
• I2C Fm+ configuration
• Selection of the Ethernet PHY interface.
• Management of the external interrupt line connection to the GPIOs
• Management of the I/O compensation cell
• Getting readout protection and Flash memory bank swap informations
• Management of boot sequences and boot addresses
• Management BOR reset level
• Management of Flash memory secured and protected sector status
• Management Flash memory write protections status
• Management of DTCM secured section status
• Management of independent watchdog behavior (hardware or software / freeze)
• Reset generation in Stop and Standby mode
• Secure mode enabling/disabling status.
On STM32H750xB devices, only the statuses of Bank 1 option bytes are applicable.

12.3 SYSCFG registers

12.3.1 SYSCFG peripheral mode configuration register (SYSCFG_PMCR)

Address offset: 0x04
Reset value: 0x0X00 0000
Note: SYSCFG_PMCR reset value depends on the package.
‘X’ corresponds to PC3, PC2, PA1 and PA0 Switch Open bit reset value (PXnSO). PXnSO
reset value is 0 when the corresponding PXn_C pin is available on the package but PXn is
not. Otherwise, it is 1.
)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. PC3SO PC2SO PA1SO PA0SO EPIS[2:0] Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw

548/3353 RM0433 Rev 8

RM0433 System configuration controller (SYSCFG)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOSTV PB9 PB8 PB7 PB6 I2C4 I2C3 I2C2 I2C1
Res. Res. Res. Res. Res. Res. BOOSTE
DDSEL FMP FMP FMP FMP FMP FMP FMP FMP

rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 PC3SO: PC3 Switch Open
This bit controls the analog switch between PC3 and PC3_C (dual pad)
0: Analog switch closed (pads are connected through the analog switch)
1: Analog switch open (2 separated pads)
Bit 26 PC2SO: PC2 Switch Open
This bit controls the analog switch between PC2 and PC2_C (dual pad)
0: Analog switch closed (pads are connected through the analog switch)
1: Analog switch open (2 separated pads)
Bit 25 PA1SO: PA1 Switch Open
This bit controls the analog switch between PA1 and PA1_C (dual pad)
0: Analog switch closed (pads are connected through the analog switch)
1: Analog switch open (2 separated pads)
Bit 24 PA0SO: PA0 Switch Open
This bit controls the analog switch between PA0 and PA0_C (dual pad)
0: Analog switch closed (pads are connected through the analog switch)
1: Analog switch open (2 separated pads)
Bits 23:21 EPIS[2:0]: Ethernet PHY Interface Selection
These bits select the Ethernet PHY interface.
000: MII
001: Reserved
010: Reserved
011: Reserved
100: RMII
101: Reserved
110: Reserved
111: Reserved
Bits 20:10 Reserved, must be kept at reset value.
Bit 9 BOOSTVDDSEL: Analog switch supply voltage selection (VDD/VDDA/booster)
To avoid current consumption due to booster activation when VDDA < 2.7 V and
VDD > 2.7 V, VDD can be selected as supply voltage for analog switches. In this
case, the BOOSTE bit should be cleared to avoid unwanted power consumption.
When both VDD < 2.7 V and VDDA < 2.7 V, the booster is still needed to obtain
full AC performances from I/O analog switches.
0: VDDA selected as analog switch supply voltage (when BOOSTE bit is cleared)
1: VDD selected as analog switch supply voltage
Note: This bit is available only on devices revision X and higher.

RM0433 Rev 8 549/3353

574
System configuration controller (SYSCFG) RM0433

Bit 8 BOOSTE: Booster Enable

This bit enables the booster to reduce the total harmonic distortion of the analog
switch when the supply voltage is lower than 2.7 V.
Activating the booster allows to guaranty the analog switch AC performance
when the supply voltage is below 2.7 V: in this case, the analog switch
performance is the same on the full voltage range.
0: Booster disabled
1: Booster enabled
Bit 7 PB9FMP: PB(9) Fm+
This bit enables I2C Fm+ on PB(9).
0: Fm+ disabled
1: Fm+ enabled
Bit 6 PB8FMP: PB(8) Fm+
This bit enables I2C Fm+ on PB(8).
0: Fm+ disabled
1: Fm+ enabled
Bit 5 PB7FMP: PB(7) Fm+
this bit enables I2C Fm+ on PB(7).
0: Fm+ disabled
1: Fm+ enabled
Bit 4 PB6FMP: PB(6) Fm+
This bit enables I2C Fm+ on PB(6).
0: Fm+ disabled
1: Fm+ enabled
Bit 3 I2C4FMP: I2C4 Fm+
This bit enables Fm+ on I2C4.
0: Fm+ disabled
1: Fm+ enabled
Bit 2 I2C3FMP: I2C3 Fm+
This bit enables Fm+ on I2C3.
0: Fm+ disabled
1: Fm+ enabled
Bit 1 I2C2FMP: I2C2 Fm+
This bit enables Fm+ on I2C2.
0: Fm+ disabled
1: Fm+ enabled
Bit 0 I2C1FMP: I2C1 Fm+
This bit enables Fm+ on I2C1.
0: Fm+ disabled
1: Fm+ enabled

550/3353 RM0433 Rev 8

RM0433 System configuration controller (SYSCFG)

12.3.2 SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)
These bits are written by software to select the source input for the EXTI input
for external interrupt / event detection.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
1001: PJ[x] pin
1010: PK[x] pin
Other configurations: reserved

12.3.3 SYSCFG external interrupt configuration register 2

(SYSCFG_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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System configuration controller (SYSCFG) RM0433

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7)
These bits are written by software to select the source input for the EXTI input for
external interrupt / event detection.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
1001: PJ[x] pin
1010: PK[x] pin
Other configurations: reserved

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RM0433 System configuration controller (SYSCFG)

12.3.4 SYSCFG external interrupt configuration register 3

(SYSCFG_EXTICR3)
Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)
These bits are written by software to select the source input for the EXTI input for
external interrupt / event detection.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
1001: PJ[x] pin
1010: PK[x] pin
Other configurations: reserved
Note: PK[11:8] are not used

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System configuration controller (SYSCFG) RM0433

12.3.5 SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)
These bits are written by software to select the source input for the EXTI input for
external interrupt / event detection.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
1001: PJ[x] pin
1010: PK[x] pin
Other configurations: reserved
Note: PK[15:12] are not used.

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RM0433 System configuration controller (SYSCFG)

12.3.6 SYSCFG configuration register (SYSCFG_CFGR)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AXI SRAML

BK RAML
SRAM1L

SRAM2L

SRAM3L

SRAM4L

FLASHL
DTCML
ITCML

CM7L

PVDL
Res. Res. Res. Res. Res.

rs rs rs rs rs rs rs rs rs rs rs

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 AXISRAML: D1 AXI-SRAM double ECC error lock bit
This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the AXI-SRAM double ECC error flag connection to TIM1/8/15/16/17 and
HRTIMER Break inputs.
0: AXI-SRAM double ECC error flag disconnected from TIM1/8/15/16/17/HRTIMER
Break inputs
1: AXI-SRAM double ECC error flag connected to TIM1/8/15/16/17/HRTIMER Break
inputs.
Bit 14 ITCML: D1 ITCM double ECC error lock bit
This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the ITCM double ECC error flag connection to TIM1/8/15/16/17 and
HRTIMER Break inputs.
0: ITCM double ECC error flag disconnected from TIM1/8/15/16/17/HRTIMER Break
inputs
1: ITCM double ECC error flag connected to TIM1/8/15/16/17/HRTIMER Break inputs
Bit 13 DTCML: D1 DTCM double ECC error lock bit
This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the DTCM double ECC error flag connection to TIM1/8/15/16/17 and
HRTIMER Break inputs.
0: DTCM double ECC error flag disconnected from TIM1/8/15/16/17/HRTIMER Break
inputs
1: DTCM double ECC error flag connected to TIM1/8/15/16/17/HRTIMER Break inputs
Bit 12 SRAM1L: D2 SRAM1 double ECC error lock bit
This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the D2 SRAM1 double ECC error flag connection to TIM1/8/15/16/17 and
HRTIMER Break inputs.
0: D2 SRAM1 double ECC error flag disconnected from TIM1/8/15/16/17/HRTIMER
Break inputs
1: D2 SRAM1 double ECC error flag connected to TIM1/8/15/16/17/HRTIMER Break
inputs

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Bit 11 SRAM2L: D2 SRAM2 double ECC error lock bit

This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the D2 SRAM2 double ECC error flag connection to TIM1/8/15/16/17 and
HRTIMER Break inputs.
0: D2 SRAM2 double ECC error flag disconnected from TIM1/8/15/16/17/HRTIMER
Break inputs
1: D2 SRAM2 double ECC error flag connected to TIM1/8/15/16/17/HRTIMER Break
inputs
Bit 10 SRAM3L: D2 SRAM3 double ECC error lock bit
This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the D2 SRAM3 double ECC error flag connection to TIM1/8/15/16/17 and
HRTIMER Break inputs.
0: D2 SRAM3 double ECC error flag disconnected from TIM1/8/15/16/17/HRTIMER
Break inputs
1: D2 SRAM3 double ECC error flag connected to TIM1/8/15/16/17/HRTIMER Break
inputs
Bit 9 SRAM4L: D3 SRAM4 double ECC error lock bit
This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the D3 SRAM4 double ECC error flag connection to TIM1/8/15/16/17 and
HRTIMER Break inputs.
0: D3 SRAM4 double ECC error flag disconnected from TIM1/8/15/16/17/HRTIMER
Break inputs
1: D3 SRAM4 double ECC error flag connected to TIM1/8/15/16/17/HRTIMER Break
inputs
Bit 8 Reserved, must be kept at reset value.
Bit 7 BKRAML: Backup SRAM double ECC error lock bit
This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the Backup SRAM double ECC error flag connection to TIM1/8/15/16/17 and
HRTIMER Break inputs.
0: Backup SRAM double ECC error flag disconnected from
TIM1/8/15/16/17/HRTIMER Break inputs
1: Backup SRAM double ECC error flag connected to TIM1/8/15/16/17/HRTIMER
Break inputs
Bit 6 CM7L: Arm® Cortex®-M7 LOCKUP (HardFault) output enable bit
This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the connection of the Arm® Cortex®-M7 LOCKUP (HardFault) output to
TIM1/8/15/16/17 and HRTIMER Break inputs.
0: Arm® Cortex®-M7 LOCKUP output disconnected from TIM1/8/15/16/17/HRTIMER
Break inputs
1: Arm® Cortex®-M7 LOCKUP output connected to TIM1/8/15/16/17/HRTIMER Break
inputs
Bits 5:4 Reserved, must be kept at reset value.

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RM0433 System configuration controller (SYSCFG)

Bit 3 FLASHL: FLASH double ECC error lock bit

This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the FLASH double ECC error flag connection to TIM1/8/15/16/17 and
HRTIMER Break inputs.
0: FLASH double ECC error flag disconnected from TIM1/8/15/16/17/HRTIMER Break
inputs
1: FLASH double ECC error flag connected to TIM1/8/15/16/17/HRTIMER Break
inputs
Bit 2 PVDL: PVD lock enable bit
This bit is set by software and cleared only by a system reset. It can be used to enable
and lock the PVD connection to TIM1/8/15/16/17 and HRTIMER Break inputs, as well
as the PVDE and PLS[2:0] in the PWR_CR1 register.
0: PVD signal disconnected from TIM1/8/15/16/17/HRTIMER Break inputs
1: PVD signal connected to TIM1/8/15/16/17/HRTIMER Break inputs
Bits 1:0 Reserved, must be kept at reset value.

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12.3.7 SYSCFG compensation cell control/status register

(SYSCFG_CCCSR)
Address offset: 0x20
Reset value: 0x0000 0000
Refer to Section 11.3.11: I/O compensation cell for a detailed description of I/O
compensation mechanism.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSLV

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. READY Res. Res. Res. Res. Res. Res. CS EN

r rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 HSLV: High-speed at low-voltage
This bit is written by software to optimize the I/O speed when the product voltage is
low.
This bit is active only if IO_HSLV user option bit is set. It must be used only if the
product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
might be destructive.
0: No I/O speed optimization
1: I/O speed optimization
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 READY: Compensation cell ready flag
This bit provides the status of the compensation cell.
0: I/O compensation cell not ready
1: I/O compensation cell ready
Note: The CSI clock is required for the compensation cell to work properly. The
compensation cell ready bit (READY) is not set if the CSI clock is not enabled.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 CS: Code selection
This bit selects the code to be applied for the I/O compensation cell.
0: Code from the cell (available in the SYSCFG_CCVR)
1: Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
Bit 0 EN: Enable
This bit enables the I/O compensation cell.
0: I/O compensation cell disabled
1: I/O compensation cell enabled

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RM0433 System configuration controller (SYSCFG)

12.3.8 SYSCFG compensation cell value register (SYSCFG_CCVR)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PCV[3:0] NCV[3:0]

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 PCV[3:0]: PMOS compensation value
This value is provided by the cell and can be used by the CPU to compute an I/O
compensation cell code for PMOS transistors. This code is applied to the I/O
compensation cell when the CS bit of the SYSCFG_CCCSR is reset.
Bits 3:0 NCV[3:0]: NMOS compensation value
This value is provided by the cell and can be used by the CPU to compute an I/O
compensation cell code for NMOS transistors. This code is applied to the I/O
compensation cell when the CS bit of the SYSCFG_CCCSR is reset.

12.3.9 SYSCFG compensation cell code register (SYSCFG_CCCR)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PCC[3:0] NCC[3:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 PCC[3:0]: PMOS compensation code
These bits are written by software to define an I/O compensation cell code for PMOS
transistors. This code is applied to the I/O compensation cell when the CS bit of the
SYSCFG_CCCSR is set.
Bits 3:0 NCC[3:0]: NMOS compensation code
These bits are written by software to define an I/O compensation cell code for NMOS
transistors. This code is applied to the I/O compensation cell when the CS bit of the
SYSCFG_CCCSR is set.

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12.3.10 SYSCFG power control register (SYSCFG_PWRCR)

Address Offset: 0x2C
Reset Value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ODEN

rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 ODEN: Overdrive enable, this bit allows to activate the LDO regulator overdrive mode.
This bit must be written only in VOS1 voltage scaling mode.
0: Overdrive mode disabled
1: Overdrive mode enabled (the LDO generates VOS0 for VCORE)
Note: VOS0 must be activated only in VOS1 mode. It must be disabled by software
before entering low-power mode (execution of WFE/WFI instruction).

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 CM4PRESENT: Arm® Cortex® -M4 core
This bit indicates that the Arm® Cortex® -M4 core is present.
0: Arm® Cortex® -M4 core not present
1: Arm® Cortex® -M4 core present
Bits 15:0 Reserved, must be kept at reset value.

12.3.11 SYSCFG package register (SYSCFG_PKGR)

Address offset: 0x124
Reset value: 0x0000 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PKG[3:0

r r r r

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RM0433 System configuration controller (SYSCFG)

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 PKG[3:0]: Package
These bits indicate the device package.
0000: LQFP100
0010: TQFP144
0101: TQFP176/UFBGA176
1000: LQFP208/TFBGA240
Other configurations: all pads enabled

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12.3.12 SYSCFG user register 0 (SYSCFG_UR0)

Address offset: 0x300
Reset value: 0x00XX 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. RDP[7:0]

r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BKS

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 RDP[7:0]: Readout protection
These bits indicate the readout protection level.
0xAA: Level 0 (no protection)
0xCC: Level 2 (Flash memory readout protected, full debug features, boot from SRAM
and boundary scan disabled)
Other configurations: Level 1 (Flash memory readout protected, limited debug
features and boundary scan enabled)
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 BKS: Bank Swap
This bit indicates Flash memory bank mapping.
0: Flash memory bank addresses are inverted
1: Flash memory banks are mapped to their original addresses

12.3.13 SYSCFG user register 2 (SYSCFG_UR2)

Address offset: 0x308
Reset value: 0xXXXX 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BOOT_ADD0[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BORH[1:0]
r r

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RM0433 System configuration controller (SYSCFG)

Bits 31:16 BOOT_ADD0[15:0]: Boot Address 0

These bits define the MSB of the core boot address when BOOT pin is low.
Bits 15:2 Reserved, must be kept at reset value.
Bits 1:0 BORH[1:0]: BOR_LVL Brownout Reset Threshold Level
These bits indicate the Brownout reset high level.
0x11: BOR Level 3
0x10: BOR Level 2
0x01: BOR Level 1
0x00: BOR OFF (Level 0)

12.3.14 SYSCFG user register 3 (SYSCFG_UR3)

Address offset: 0x30C
Reset value: 0xXXXX XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_ADD1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BOOT_ADD1[15:0]: Boot Address 1
These bits define the MSB of the core boot address when BOOT pin is high.

12.3.15 SYSCFG user register 4 (SYSCFG_UR4)

Address offset: 0x310
Reset value: 0x000X XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MEPAD_1

r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 MEPAD_1: Mass Erase Protected Area Disabled for bank 1
This bit indicates if the flash protected area (Bank 1) is affected by a mass erase.
0: When a mass erase occurs the protected area is erased
1: When a mass erase occurs the protected area is not erased
Bits 15:0 Reserved, must be kept at reset value.

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12.3.16 SYSCFG user register 5 (SYSCFG_UR5)

Address offset: 0x314
Reset value: 0x00XX 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. WRPS_1[7:0]

r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MESAD_1

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 WRPN_1[7:0]: Write protection for flash bank 1
WRPN[i] bit indicates if the sector i of the Flash memory bank 1 is protected.
0: Write protection is active on sector i
1: Write protection is not active on sector i
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 MESAD_1: Mass erase secured area disabled for bank 1
This bit indicates if the flash secured area (bank 1) is affected by a mass erase.
0: When a mass erase occurs the secured area is erased
1: When a mass erase occurs the secured area is not erased

12.3.17 SYSCFG user register 6 (SYSCFG_UR6)

Address offset: 0x318
Reset value: 0x0XXX 0XXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. PA_END_1[11:0]

r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. PA_BEG_1[11:0]

r r r r r r r r r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bits 23:16 PA_END_1[11:0]: Protected area end address for bank 1
End address for bank 1 protected area.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 PA_BEG_1[11:0]: Protected area start address for bank 1
Start address for bank 1 protected area.

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RM0433 System configuration controller (SYSCFG)

12.3.18 SYSCFG user register 7 (SYSCFG_UR7)

Address offset: 0x31C
Reset value: 0x0XXX 0XXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. SA_END_1[11:0]

r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. SA_BEG_1[11:0]

r r r r r r r r r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bits 23:16 SA_END_1[11:0]: Secured area end address for bank 1
End address for bank 1 secured area.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 SA_BEG_1[11:0]: Secured area start address for bank 1
Start address for bank 1 secured area.

12.3.19 SYSCFG user register 8 (SYSCFG_UR8)

Address offset: 0x320
Reset value: 0x000X 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MESAD_2

r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MEPAD_2

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 MESAD_2: Mass erase secured area disabled for bank 2
This bit indicates if the Flash memory secured area (Bank 2) is affected by a mass
erase.
0: When a mass erase occurs the secured area is erased
1: When a mass erase occurs the secured area is not erased
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 MEPAD_2: Mass erase protected area disabled for bank 2
This bit indicates if the Flash memory protected area (Bank 2) is affected by a mass
erase.
0: When a mass erase occurs the protected area is erased
1: When a mass erase occurs the protected area is not erased

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12.3.20 SYSCFG user register 9 (SYSCFG_UR9)

Address offset: 0x324
Reset value: 0x0XXX 00XX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. PA_BEG_2[11:0]

r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. WRPS_2[7:0]

r r r r r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 PA_BEG_2[11:0]: Protected area start address for bank 2
Start address for bank 2 protected area.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 WRPN_2[7:0]: Write protection for flash bank 2
WRPN[i] bit indicates if the sector i of the Flash memory bank 2 is protected.
0: Write protection is active on sector i
1: Write protection is not active on sector i

12.3.21 SYSCFG user register 10 (SYSCFG_UR10)

Address offset: 0x328
Reset value: 0x0XXX 0XXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. SA_BEG_2[11:0]

r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. PA_END_2[11:0]

r r r r r r r r r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 SA_BEG_2[11:0]: Secured area start address for bank 2
Start address for bank 2 secured area.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 PA_END_2[11:0]: Protected area end address for bank 2
End address for bank 2 protected area.

566/3353 RM0433 Rev 8

RM0433 System configuration controller (SYSCFG)

12.3.22 SYSCFG user register 11 (SYSCFG_UR11)

Address offset: 0x32C
Reset value: 0x000X 0XXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IWDG1M

r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. SA_END_2[11:0]

r r r r r r r r r r r r

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 IWDG1M: Independent Watchdog 1 mode
This bit indicates the control mode of the Independent Watchdog 1 (IWDG1).
0: IWDG1 controlled by hardware
1: IWDG1 controlled by software
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 SA_END_2[11:0]: Secured area end address for bank 2
End address for bank 2 secured area.

12.3.23 SYSCFG user register 12 (SYSCFG_UR12)

Address offset: 0x330
Reset value: 0x000X 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SECURE

r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 SECURE: Secure mode
This bit indicates the Secure mode status.
0: Secure mode disabled
1: Secure mode enabled
Bits 15:0 Reserved, must be kept at reset value.

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System configuration controller (SYSCFG) RM0433

12.3.24 SYSCFG user register 13 (SYSCFG_UR13)

Address offset: 0x334
Reset value: 0x000X 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. D1SBRST

rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDRS[1:0]

r r

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 D1SBRST: D1 Standby reset
This bit indicates if a reset is generated when D1 domain enters DStandby mode.
0: A reset is generated by entering D1 Standby mode
1: D1 Standby mode is entered without reset generation
Bits 15:2 Reserved, must be kept at reset value.
Bits 1:0 SDRS[1:0]: Secured DTCM RAM Size
These bits indicates the size of the secured DTCM RAM.
00: 2 Kbytes
01: 4 Kbytes
10: 8 Kbytes
11: 16 Kbytes

568/3353 RM0433 Rev 8

RM0433 System configuration controller (SYSCFG)

12.3.25 SYSCFG user register 14 (SYSCFG_UR14)

Address offset: 0x338
Reset value: 0x000X 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. D1STPRST

rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:1 Reserved, must be kept at reset value.
Bit 0 D1STPRST: D1 Stop Reset
This bit indicates if a reset is generated when D1 domain enters in DStop mode.
0: A reset is generated entering D1 Stop mode
1: D1 Stop mode is entered without reset generation

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System configuration controller (SYSCFG) RM0433

12.3.26 SYSCFG user register 15 (SYSCFG_UR15)

Address offset: 0x33C
Reset value: 0x000X 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FZIWDGS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TB

r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 FZIWDGSTB: Freeze independent watchdog in Standby mode
This bit indicates if the independent watchdog is frozen in Standby mode.
0: Independent Watchdog frozen in Standby mode
1: Independent Watchdog running in Standby mode
Bits 15:0 Reserved, must be kept at reset value.

570/3353 RM0433 Rev 8

RM0433 System configuration controller (SYSCFG)

12.3.27 SYSCFG user register 16 (SYSCFG_UR16)

Address offset: 0x340
Reset value: 0x000X 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PKP

r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FZIWDG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
STP

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 PKP: Private key programmed
This bit indicates if the device private key is programmed.
0: Private key not programmed
1: Private key programmed
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 FZIWDGSTP: Freeze independent watchdog in Stop mode
This bit indicates if the independent watchdog is frozen in Stop mode.
0: Independent Watchdog frozen in Stop mode
1: Independent Watchdog running in Stop mode

12.3.28 SYSCFG user register 17 (SYSCFG_UR17)

Address offset: 0x344
Reset value: 0x0000 000X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IO_HSLV

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 IO_HSLV: I/O high speed / low voltage
This bit indicates that the IOHSLV option bit is set.
0: Product is working on the full voltage range
1: Product is working below 2.7 V

RM0433 Rev 8 571/3353

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 0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x2C
0x0C

0x300
0x124
0x120
0x30 -

0x2FC
0x128 -

572/3353
12.3.29

EXTICR4
EXTICR3
EXTICR2
EXTICR1

Reserved
Reserved
Reserved

SYSCFG_
SYSCFG_
SYSCFG_
SYSCFG_

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

SYSCFG_UR0
SYSCFG_PKGR
SYSCFG_CCVR
SYSCFG_CCSR
SYSCFG_CFGR

SYSCFG_CCCR
SYSCFG_CCCR
SYSCFG_PMCR
Offset Register name
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PC3SO 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PC2SO 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PA1SO 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PA0SO 24
SYSCFG register maps

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
System configuration controller (SYSCFG)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. X X 1 1 0 0 0 EPIS[2:0] 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19

RDP[7:0]
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0433 Rev 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17

x x x x x x x x
0
Res. Res. Res. Res. Res. Res. HSLV Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. AXISRAML Res. 15
Reserved

Res. Res. Res. Res. Res. Res. Res. Res. ITCML Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. DTCML Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. SRAM1L Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. SRAM2L Res. 11
Table 95. SYSCFG register map and reset values

Res. Res. Res. Res. Res. Res. Res. Res. SRAM3L Res. 10

0 0 0 0 0 0 0
Res. Res. Res. Res. Res. Res. Res. Res. SRAM4L Res. 9
Res. Res. Res. Res. Res. Res. Res. Res. Res. BOOSTE 8

0
Res. Res. Res. Res. Res. READY BKRAML PB9FMP
The following table gives the SYSCFG register map and the reset values.

0 0 7
Res. Res. Res. Res. Res. Res. CM7L PB8FMP 6
Res. Res. Res. Res. Res. Res. Res. PB7FMP 5

PCV[3:0]

PCC[3:0]
Res. Res. Res. Res. Res. Res. Res. PB6FMP 4
Res. Res. Res. Res. Res. FLASHL I2C4FMP 3
0 0

Res. Res. Res. Res. Res. PVDL I2C3FMP 2

Res. Res. Res. Res. CS Res. I2C2FMP 1
NCV[3:0]

PKG[3:0]
NCC[3:0]
EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]

x
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0

0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0

Res.

X X X X
BKS Res. Res. ODEN EN I2C1FMP
EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]

0
RM0433
 0x334
0x330
0x328
0x324
0x320
0x318
0x314
0x310
0x308
0x304

0x32C
0x31C
0x30C
RM0433

Reserved

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
SYSCFG_UR2

SYSCFG_UR9
SYSCFG_UR8
SYSCFG_UR7
SYSCFG_UR6
SYSCFG_UR5
SYSCFG_UR4
SYSCFG_UR3

SYSCFG_UR11

SYSCFG_UR13
SYSCFG_UR12
SYSCFG_UR10
Offset Register name

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res.
BOOT_ADD0[15:0]

21
Res. Res. Res. Res. Res. Res. 20

PA_END_2[11:0]
PA_END_1[11:0]

SA_BEG_2[11:0]
SA_END_1[11:0]
Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. 18
WRPN_1[7:0]

RM0433 Rev 8
Res. Res. Res. Res. Res. Res. 17

X X X X X X X X X X X X
X X X X X X X X X X X X
X X X X X X X X X X X X
X X X X X X X X X X X X

X
X
X
X X X X X X X X
X
X X X X X X X X X X X X X X X X

D1SBRST SECURE IWDG1M MESAD_2 MEPAD_1 Res. 16

Res. RES. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
Reserved

Res. RES. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. RES. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. RES. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. RES. Res. Res. Res. Res. Res. 11
Res. RES. Res. Res. Res. Res. Res. 10
Res. RES. Res. Res. Res. Res. Res. 9
Res. RES. Res. Res. Res. Res. Res. 8
Table 95. SYSCFG register map and reset values (continued)

Res. RES. Res. Res. Res. Res. 7

Res. RES. Res. Res. Res. Res. 6
Res. RES. Res. Res. Res. Res. 5
BOOT_ADD1[15:0]

Res. RES. Res. Res. Res. Res. 4

PA_END_2[11:0]
PA_BEG_1[11:0]

SA_END_2[11:0]
SA_BEG_1[11:0]

Res. RES. Res. Res. Res. Res. 3

Res. RES. Res. Res. Res. Res. 2
WRPN_2[7:0]

RES. Res. Res. Res. 1

SDRS[1:0] BORH[1:0]
x

X X
X X X X X X X X X X X X
X
X X X X X X X X X X X X X X X X
X X

X X X X X X X X X X X X
X X X X X X X X
X X X X X X X X X X X X
X X X X X X X X X X X X

Res.. MEPAD_2 MESAD_1 Res. 0

System configuration controller (SYSCFG)

573/3353
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 0x344
0x340
0x338

0x33C

574/3353
Reset value
Reset value
Reset value
Reset value

SYSCFG_UR17
SYSCFG_UR16
SYSCFG_UR15
SYSCFG_UR14
Offset Register name

Res. Res. Res. Res. 31

Res. Res. Res. Res. 30
Res. Res. Res. Res. 29
Res. Res. Res. Res. 28
Res. Res. Res. Res. 27
Res. Res. Res. Res. 26
Res. Res. Res. Res. 25
Res. Res. Res. Res. 24
Res. Res. Res. Res. 23
System configuration controller (SYSCFG)

Res. Res. Res. Res. 22

Res. Res. Res. Res. 21
Res. Res. Res. Res. 20
Res. Res. Res. Res. 19
Res. Res. Res. Res. 18

RM0433 Rev 8
Res. Res. Res. Res. 17
X
X
X

RES. PKP FZIWDGSTB Res. 16

RES. RES. RES. RES. 15
RES. RES. RES. RES. 14
RES. RES. RES. RES. 13
RES. RES. RES. RES. 12
RES. RES. RES. RES. 11
RES. RES. RES. RES. 10
Refer to Section 2.3 on page 129 for the register boundary addresses. RES. RES. RES. RES. 9
RES. RES. RES. RES. 8
Table 95. SYSCFG register map and reset values (continued)

RES. RES. RES. RES. 7

RES. RES. RES. RES. 6
RES. RES. RES. RES. 5
RES. RES. RES. RES. 4
RES. RES. RES. RES. 3
RES. RES. RES. RES. 2
RES. RES. RES. RES. 1
IO_HSLV FZIWDGST
X
X
X

Res. D1STPRST 0
RM0433
RM0433 Block interconnect

13 Block interconnect

13.1 Peripheral interconnect

13.1.1 Introduction
Several peripherals have direct connections between them.
This enables autonomous communication and synchronization between peripherals, thus
saving CPU resources and power consumption.
These hardware connections remove software latency, allow the design of a predictable
system and result in a reduction of the number of pins and GPIOs.

13.1.2 Connection overview

There are several types of connections.
• Asynchronous connections (A)
The source output signal is sampled by the destination clock, leading to introduction of
a possible jitter in the latency between the source output event and the destination
event detection
• Synchronous connections (S)
Both source and destination are synchronous (they run on the same clock), and the
latency from the source to the destination is deterministic. No jitter is introduced.
• Immediate connections (I)
Either the source or the destination is an analog signal.
• Break/fault connection for TIM/HRTIM outputs (B)
The source output signal disables the timer outputs through a pure combinational logic
path, without any latency.

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Block interconnect RM0433

Table 96. Peripherals interconnect matrix (D2 domain) (1) (2)

Destination

D2 domain D3 domain

AHB4
APB1 APB2 AHB1 APB4
Source

ETHERNET
DFSDM1
LPTIM1

LPTIM2
LPTIM3
LPTIM4
LPTIM5
COMP1
COMP2
HRTIM
TIM12

TIM15
TIM16
TIM17

ADC1
ADC2

ADC3
TIM2
TIM3
TIM4
TIM5

TIM1
TIM8
DAC

CAN
CRS
TIM2 - S S - - - S - A S S S - - - S S S A S - - - - I I
TIM3 S - S S - - - - A S S - - S S S S A S - - - - I I
TIM4 S S - S S - S - - S S S - - S - S S - S - - - - - -
TIM5 - - - - S - S - - S - - - - - - - S - - - - - -
TIM6 - - - - S - - - - - - - S S S S - S - - - - - -
TIM7 - - - - S - - - - - - - S S - - - - - - - - - -
APB1

TIM13 - - - - S - - - - - - - - - - - - - - - - - - -
TIM14 - - - - S - - - - - - - - - - - - - - - - - - -
LPTIM1 - - - - - - A - - - - - - - A A A A A - - - - - -
SPDIFRX - - - - - - - - - - - - S - - - - - - - - - - - -
OPAMP - - - - - - - - - - - - - - A - - - - - - - - - -
CAN - - - A - - - - - - - - - - A - - A - - - - - - -
TIM1 S S S S - - S - - - S S - - S S S S - S - - - - I I
D2 domain

TIM8 S - S S - - S - - - - - - - S S S - S - - - - I I
TIM15 - S - - - - S - - S - - - - S S S - S - - - - I I
TIM16 - - - - - - - - - - - S - - S S - - - - - - - - - -
APB2

TIM17 - - - - - - - - - - - S - - S - - - - - - - - - -
SAI1 A - - - - - - - - - - - - - - - - - - - - A - - - -
SAI2 - - - A - - - - - - - - - - - - - - - - - - A - - -
DFSDM1 - - - - - - - - - B B B B B - - - - - - - - - - - -
HRTIM - - - - - - A - A - - - - - S - A A A A - - - - - -
ADC1 - - - - - - - - - A - - - - - A - - - - - - - - - -
ADC2 - - - - - - - - - - A - - - - A - - - - - - - - - -
ETH A A - - - - - - A - - - - - - - - - - - - - - - -
AHB1

USB1
(OTG_H A A - - A - - - - - - - - - - - - - - - - - -
S1)
USB2
(OTG_ A A - - A - - - - - - - - - - - - - - - - - -
HS2)

576/3353 RM0433 Rev 8

RM0433 Block interconnect

1. Letters in the table correspond to the type of connection described in Section 13.1.2: Connection overview
2. The “-” symbol in a gray cell means no interconnect.

Table 97. Peripherals interconnect matrix (D3 domain) (1) (2)

Destination

D2 domain D3 domain
AHB4
APB1 APB2 AHB1 APB4
Source

ETHERNET
DFSDM1
LPTIM1

LPTIM2
LPTIM3
LPTIM4
LPTIM5
HRTIM
TIM12

TIM15
TIM16
TIM17

ADC1
ADC2

ADC3
TIM2
TIM3
TIM4
TIM5

TIM1
TIM8
DAC

CAN
CRS

EXTI - - - - - - A - - - - - - - A - A A - - - - - -
LPTIM2 - - - - - - A - - - - - - - A A A A - A - A A A
LPTIM3 - - - - - - - - - - - - - - A - A A - A - - A A
LPTIM4 - - - - - - - - - - - - - - - - - - - - - A - A
APB4
D3 Domain

LPTIM5 - - - - - - - - - - - - - - - - - - - - - A A -
COMP1 A A - - - A - - - A/B A/B B B B A/B - - - - A - - -
COMP2 A A - - - A - - - A/B A/B B B B A/B - - - - A - - -
SAI4 - - - - - - - - - - - - - - - - - - - - - A - A
RTC - - - - - A - - - - - - A - - - - - - - A - - -
ADC3 - - - - - - - - - A A - - - - - - - - - - - - -
AHB4

RCC A - - - - - - A - - - A A A - - - - - - - - - -
1. Letters in the table correspond to the type of connection described in Section 13.1.2: Connection overview.
2. The “-” symbol in a gray cell means no interconnect.

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Block interconnect RM0433

Table 98. Peripherals interconnect matrix details(1)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

TIM1 TRGO ITR0 S -

APB2
TIM8 TRGO ITR1 S -
TIM3 TRGO ITR2 S -
APB1
D2 TIM4 TRGO ITR3 S -
ETH PPS ITR4 S -
AHB1 USB1 SOF ITR5 S -
USB2 SOF ITR6 S -
COMP1 comp1_out ETR1 I -
TIM2 APB1 D2
D3 APB4 COMP2 comp2_out ETR2 I -
RCC lse_ck ETR3 A -
SAI1 SAI1_FS_A ETR4 A -
D2 APB2
SAI1 SAI1_FS_B ETR5 A -
COMP1 comp1_out TI4_1 I -
COMP2 comp2_out TI4_2 I -
D3 APB4
COMP1 or comp1_out or
TI4_3 I -
COMP2(2) comp2_out
APB2 TIM1 TRGO ITR0 S -
APB1 TIM2 TRGO ITR1 S -
D2 APB2 TIM15 TRGO ITR2 S -
APB1 TIM4 TRGO ITR3 S -
AHB1 ETH PPS ITR4 S -
TIM3 APB1 D2
COMP1 comp1_out ETR1 I -
COMP1 comp1_out TI1_1 I -
D3 APB4 COMP2 comp2_out TI1_2 I -
COMP1 or comp1_out or
TI1_3 I -
COMP2(2) comp2_out
APB2 TIM1 TRGO ITR0 S -
TIM2 TRGO ITR1 S -
D2 APB1 TIM4 APB1 D2
TIM3 TRGO ITR2 S -
APB2 TIM8 TRGO ITR3 S -

578/3353 RM0433 Rev 8

RM0433 Block interconnect

Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

TIM1 TRGO ITR0 S -

APB2
TIM8 TRGO ITR1 S -
TIM3 TRGO ITR2 S -
APB1 TIM4 TRGO ITR3 S -
CAN SOC ITR6 S -
D2 USB1 SOF ITR7 TIM5 APB1 D2 S -
AHB1
USB2 SOF ITR8 S -
SAI2 SAI2_FS_A ETR1 A -
APB2
SAI2 SAI2_FS_B ETR2 A -
CAN TMP TI1_1 A -
APB1
CAN RTP TI1_2 A -
TIM4 TRGO ITR0 S -
TIM5 TRGO ITR1 S -
APB1 TIM12 APB1 D2
TIM13 OC1 ITR2 S -
D2
TIM14 OC1 ITR3 S -
USB1 SOF crs_sync2 CRS APB1 D2 A -
AHB1
USB2 SOF crs_sync3 CRS APB1 D2 A -
D3 AHB4 RCC lse_ck crs_sync1 CRS APB1 D2 A -

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Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

APB2 TIM15 TRGO ITR0 S -

TIM2 TRGO ITR1 S -
D2
APB1 TIM3 TRGO ITR2 S -
TIM4 TRGO ITR3 S -
COMP1 comp1_out ETR1 I -
D3 APB4
COMP2 comp2_out ETR2 I -
ADC1 adc1_awd1 ETR3 A -
D2 AHB1 ADC1 adc1_awd2 ETR4 A -
ADC1 adc1_awd3 ETR5 A -
ADC3 adc3_awd1 ETR6 A -
TIM1 APB2 D2
AHB4 ADC3 adc3_awd2 ETR7 A -
ADC3 adc3_awd3 ETR8 A -
D3
COMP1 comp1_out TI1_1 I -
APB4 COMP1 comp1_out BRK_1 B -
COMP2 comp2_out BRK_2 B -
dfsdm1_
D2 APB2 DFSDM1 BRK_3 B -
break0
COMP1 comp1_out BRK2_1 B -
D3 APB4
COMP2 comp2_out BRK2_2 B -
dfsdm1_
D2 APB2 DFSDM1 BRK2_3 B -
break1

580/3353 RM0433 Rev 8

RM0433 Block interconnect

Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

APB2 TIM1 TRGO ITR0 S -

TIM2 TRGO ITR1 S -
D2
APB1 TIM4 TRGO ITR2 S -
TIM5 TRGO ITR3 S -
COMP1 comp1_out ETR1 I -
D3 APB4
COMP2 comp2_out ETR2 I -
ADC2 adc2_awd1 ETR3 A -
D2 AHB1 ADC2 adc2_awd2 ETR4 A -
ADC2 adc2_awd3 ETR5 A -
ADC3 adc3_awd1 ETR6 A -
TIM8 APB2 D2
AHB4 ADC3 adc3_awd2 ETR7 A -
ADC3 adc3_awd3 ETR8 A -
D3
COMP2 comp2_out TI1_1 I -
APB4 COMP1 comp1_out BRK_1 B -
COMP2 comp2_out BRK_2 B -
dfsdm1_
D2 APB2 DFSDM1 BRK_3 B -
break2
COMP1 comp1_out BRK2_1 B -
D3 APB4
COMP2 comp2_out BRK2_2 B -
dfsdm1_
D2 APB2 DFSDM1 BRK2_3 B -
break3

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Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

APB2 TIM1 TRGO ITR0 S -

APB1 TIM3 TRGO ITR1 S -
TIM16 OC1 ITR2 S -
APB2
D2 TIM17 OC1 ITR3 S -
TIM2 CH1 TI1_1 A -
APB1 TIM3 CH1 TI1_2 A -
TIM4 CH1 TI1_3 A -
RCC lse_ck TI1_4 A -
D3 AHB4 RCC csi_ck TI1_5 TIM15 APB2 D2 A -
RCC MCO2 TI1_6 A -
TIM2 CH2 TI2_1 A -
D2 APB1 TIM3 CH2 TI2_2 A -
TIM4 CH2 TI2_3 A -
COMP1 comp1_out BRK_1 B -
D3 APB4
COMP2 comp2_out BRK_2 B -
dfsdm_
D2 APB2 DFSDM1 BRK_3 B -
break0
RCC lsi_ck TI1_1 A -
AHB4
RCC lse_ck TI1_2 A -
D3 RTC WKUP_IT TI1_3 A -
APB4 COMP1 comp1_out BRK_1 TIM16 APB2 D2 B -
COMP2 comp2_out BRK_2 B -
dfsdm_
D2 APB2 DFSDM1 BRK_3 B -
break1
spdifrx_frame_
D2 APB1 SPDIFRX TI1_1 A -
sync
RCC HSE_1MHZ TI1_2 A -
AHB4
RCC MCO1 TI1_3 A -
D3 TIM17 APB2 D2
COMP1 comp1_out BRK_1 B -
APB4
COMP2 comp2_out BRK_2 B -
dfsdm_
D2 APB2 DFSDM1 BRK_3 B -
break2

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RM0433 Block interconnect

Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

D3 APB4 COMP1 comp1_out hrtim_evt11 B -

APB2 TIM1 TRGO hrtim_evt12 B -
D2
AHB1 ADC1 adc1_awd1 hrtim_evt13 B -
D3 APB4 COMP2 OUT hrtim_evt21 B -
APB2 TIM2 TRGO hrtim_evt22 B -
AHB1 ADC1 adc1_awd2 hrtim_evt23 B -
NC NC NC hrtim_evt31 B -
APB2 TIM3 TRGO hrtim_evt32 B -
AHB1 ADC1 adc1_awd3 hrtim_evt33 B -
D2 OPAMP1 opamp1_out hrtim_evt41 B -
APB1
TIM7 TRGO hrtim_evt42 B -
AHB1 ADC2 adc2_awd1 hrtim_evt43 B -
NC NC NC hrtim_evt51 B -
APB1 LPTIM1 lptim1_out hrtim_evt52 B -
AHB1 ADC2 adc2_awd2 hrtim_evt53 B -
D3 APB4 COMP1 comp1_out hrtim_evt61 I -
HRTIM APB2 D2
APB1 TIM6 TRGO hrtim_evt62 S -
D2
AHB1 ADC2 adc2_awd3 hrtim_evt63 A -
D3 APB4 COMP2 comp2_out hrtim_evt71 I -
APB1 TIM7 TRGO hrtim_evt72 S -
hrtim_evt73 - -
NC NC NC
hrtim_evt81 - -
APB1 TIM6 TRGO hrtim_evt82 S -
CAN TTCAN_TMP hrtim_evt83 A -
D2 APB1
OPAMP1 opamp1_out hrtim_evt91 I -
APB2 TIM15 TRGO hrtim_evt92 S -
APB1 CAN TTCAN_RTP hrtim_evt93 A -
hrtim_
NC NC NC -
evt101
hrtim_
D3 APB4 LPTIM2 lptim2_out A -
evt102
hrtim_
D2 APB1 CAN TTCAN_SOC A -
evt103

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Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

hrtim_in_
COMP1 comp1_out B -
flt1
D3 APB4
hrtim_in_
COMP2 comp2_out B -
flt2
TIM16 OC hrtim_upd_en1 S -
APB2
TIM17 OC hrtim_upd_en2 S -
TIM6 TRGO hrtim_upd_en3 S -
APB1 HRTIM APB2 D2
hrtim_bm
TIM7 TRGO S -
_trg
D2
hrtim_bm
TIM16 OC S -
_ck1
APB2
hrtim_bm
TIM17 OC S -
_ck2
hrtim_bm
APB1 TIM7 TRGO S -
_ck3
rtc_alarm_a_ lptim1_ext_
RTC A -
evt trg0
rtc_alarm_b_ lptim1_ext_
RTC A -
evt trg1
lptim1_ext_
RTC rtc_tamp1_evt A -
trg2
lptim1_ext_
RTC rtc_tamp2_evt A -
trg3
lptim1_ext_
D3 APB4 RTC rtc_tamp3_evt LPTIM1 APB1 D2 A -
trg4
lptim1_ext_
COMP1 comp1_out I -
trg5
lptim1_ext_
COMP2 comp2_out I -
trg6
lptim1_in1_mu
COMP1 comp1_out I -
x1
lptim1_in2_mu
COMP2 comp2_out I -
x2

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RM0433 Block interconnect

Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

rtc_alarm_a_ lptim2_ext_trg
RTC A -
evt 0
rtc_alarm_b_ lptim2_ext_trg
RTC A -
evt 1
lptim2_ext_trg
RTC rtc_tamp1_evt A -
2
lptim2_ext_trg
RTC rtc_tamp2_evt A -
3
lptim2_ext_trg
RTC rtc_tamp3_evt A -
4
lptim2_ext_trg
D3 APB4 COMP1 comp1_out LPTIM2 APB4 D3 I -
5
lptim2_ext_trg
COMP2 comp2_out I -
6
lptim2_in1_mu
COMP1 comp1_out I -
x1
lptim2_in1_mu
COMP2 comp2_out I -
x2
COMP1 or comp1_out or lptim2_in1_mu
I -
COMP2 (2) comp2_out x3
lptim2_in2_mu
COMP2 comp2_out I -
x1
lptim3_ext_ If same kernel clock
LPTIM2 lptim2_out S
trg0 source
lptim3_ext_
NC NC - -
trg1
D3 APB4
lptim3_ext_ If same kernel clock
LPTIM4 lptim4_out S
trg2 source
lptim3_ext_ If same kernel clock
LPTIM5 lptim5_out S
trg3 source
LPTIM3 APB4 D3
lptim3_ext_
SAI1 SAI1_FS_A A -
trg4
lptim3_ext_
SAI1 SAI1_FS_B A -
trg5
D2 APB2
lptim3_in1_
SAI4 SAI4_FS_A A -
mux1
lptim3_in1_
SAI4 SAI4_FS_B A -
mux2

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Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

lptim4_ext_trg If same kernel clock

LPTIM2 lptim2_out S
0 source
lptim4_ext_trg If same kernel clock
LPTIM3 lptim3_out S
1 source
D3 APB4
lptim4_ext_trg
NC NC -
2
LPTIM4 APB4 D3
lptim4_ext_trg If same kernel clock
LPTIM5 lptim5_out S
3 source
lptim4_ext_trg
SAI2 SAI2_FS_A A -
4
D2 APB2
lptim4_ext_trg
SAI2 SAI2_FS_B A -
5
lptim5_ext_trg If same kernel clock
LPTIM2 lptim2_out S
0 source
lptim5_ext_trg If same kernel clock
LPTIM3 lptim3_out S
1 source
lptim5_ext_trg If same kernel clock
D3 APB4 LPTIM4 lptim4_out LPTIM5 APB4 D3 S
2 source
lptim5_ext_trg
SAI4 SAI4_FS_A A -
3
lptim5_ext_trg
SAI4 SAI4_FS_B A -
4

586/3353 RM0433 Rev 8

RM0433 Block interconnect

Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

dac_ch1/2_trg
APB2 TIM1 TRGO S -
0
dac_ch1/2_trg
TIM2 TRGO S -
1
dac_ch1/2_trg
TIM4 TRGO S -
02
dac_ch1/2_trg
APB1 TIM5 TRGO S -
3
dac_ch1/2_trg
TIM6 TRGO S -
4
dac_ch1/2_trg
TIM7 TRGO S -
5
D2 DAC
dac_ch1/2_trg
TIM8 TRGO channel APB1 D2 S -
6
1/channel 2
dac_ch1/2_trg
TIM15 TRGO S -
7
APB2
dac_ch1/2_trg
hrtim_dac_trg1 S -
8
HRTIM1
dac_ch1/2_trg
hrtim_dac_trg2 S -
9
dac_ch1/2_trg
LPTIM1 lptim1_out S -
10
APB1
dac_ch1/2_trg
LPTIM2 lptim2_out S -
11
dac_ch1/2_trg
D3 APB4 SYSCFG EXTI9 S -
12

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Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

TIM1 TRGO TRG0 S -

TIM1 TRGO2 TRG1 S -
APB2
TIM8 TRGO TRG2 S -
TIM8 TRGO2 TRG3 S -
TIM3 TRGO TRG4 S -
APB1
D2 TIM4 TRGO TRG5 S -
APB2 TIM16 OC1 TRG6 S -
TIM6 TRGO TRG7 S -
APB1 DFSDM1 APB2 D2
TIM7 TRGO TRG8 S -
HRTIM1 hrtim_adc_trg1 TRG9 S -
APB2
HRTIM1 hrtim_adc_trg3 TRG10 S -
SYSCFG EXTI11 TRG24 A -
D3 APB4
SYSCFG EXTI15 TRG25 A -
D2 APB1 LPTIM1 lptim1_out TRG26 A -
LPTIM2 lptim2_out TRG27 A -
D3 APB4
LPTIM3 lptim3_out TRG28 A -
TIM1 CC1 adc_ext_trg0 S -
APB2 TIM1 CC2 adc_ext_trg1 S -
TIM1 CC3 adc_ext_trg2 S -
D2 ADC1
TIM2 CC2 adc_ext_trg3 AHB1 D2 S -
/ ADC2
APB1 TIM3 TRGO adc_ext_trg4 S -
TIM4 CC4 adc_ext_trg5 S -
D3 APB4 SYSCFG EXTI11 adc_ext_trg6 A -

588/3353 RM0433 Rev 8

RM0433 Block interconnect

Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

TIM8 TRGO adc_ext_trg7 S -

TIM8 TRGO2 adc_ext_trg8 S -
APB2
TIM1 TRGO adc_ext_trg9 S -
TIM1 TRGO2 adc_ext_trg10 S -
TIM2 TRGO adc_ext_trg11 S -
APB1 TIM4 TRGO adc_ext_trg12 S -
D2
TIM6 TRGO adc_ext_trg13 ADC1 S -
AHB1 D2
APB2 TIM15 TRGO adc_ext_trg14 / ADC2 S -
APB1 TIM3 CC4 adc_ext_trg15 S -
HRTIM1 hrtim_adc_trg1 adc_ext_trg16 A -
APB2 HRTIM1 hrtim_adc_trg3 adc_ext_trg17 A -
LPTIM1 lptim1_out adc_ext_trg18 A -
LPTIM2 lptim2_out adc_ext_trg19 A -
D3 APB4
LPTIM3 lptim3_out adc_ext_trg20 A -
TIM1 TRGO adc_jext_trg0 S -
APB2
TIM1 CC4 adc_jext_trg1 S -
TIM2 TRGO adc_jext_trg2 ADC1 S -
D2 AHB1 D2
TIM2 CC1 adc_jext_trg3 / ADC2 S -
APB1
TIM3 CC4 adc_jext_trg4 S -
TIM4 TRGO adc_jext_trg5 S -

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Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

D3 APB4 SYSCFG EXTI15 adc_jext_trg6 A -

TIM8 CC4 adc_jext_trg7 S -
TIM1 TRGO2 adc_jext_trg8 S -
APB2
TIM8 TRGO adc_jext_trg9 S -
TIM8 TRGO2 adc_jext_trg10 S -
TIM3 CC3 adc_jext_trg11 S -
TIM3 TRGO adc_jext_trg12 S -
D2 APB1 ADC1
TIM3 CC1 adc_jext_trg13 AHB1 D2 S -
/ ADC2
TIM6 TRGO adc_jext_trg14 S -
TIM15 TRGO adc_jext_trg15 S -
APB2 HRTIM1 hrtim_adc_trg2 adc_jext_trg16 A -
HRTIM1 hrtim_adc_trg4 adc_jext_trg17 A -
APB1 LPTIM1 lptim1_out adc_jext_trg18 A -
LPTIM2 lptim2_out adc_jext_trg19 A -
D3 APB4
LPTIM3 lptim2_out adc_jext_trg20 A -

590/3353 RM0433 Rev 8

RM0433 Block interconnect

Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

TIM1 CC1 adc_ext_trg0 S -

APB2 TIM1 CC2 adc_ext_trg1 S -
TIM1 CC3 adc_ext_trg2 S -
D2
TIM2 CC2 adc_ext_trg3 S -
APB1 TIM3 TRGO adc_ext_trg4 S -
TIM4 CC4 adc_ext_trg5 S -
D3 APB4 SYSCFG EXTI11 adc_ext_trg6 A -
TIM8 TRGO adc_ext_trg7 S -
TIM8 TRGO2 adc_ext_trg8 S -
APB2
TIM1 TRGO adc_ext_trg9 S -
TIM1 TRGO2 adc_ext_trg10 ADC3 AHB4 D3 S -
TIM2 TRGO adc_ext_trg11 S -
APB1 TIM4 TRGO adc_ext_trg12 S -
D2
TIM6 TRGO adc_ext_trg13 S -
APB2 TIM15 TRGO adc_ext_trg14 S -
APB1 TIM3 CC4 adc_ext_trg15 S -
HRTIM1 hrtim_adc_trg1 adc_ext_trg16 A -
APB2 HRTIM1 hrtim_adc_trg3 adc_ext_trg17 A -
LPTIM1 lptim1_out adc_ext_trg18 A -
LPTIM2 lptim2_out adc_ext_trg19 A -
D3 APB4
LPTIM3 lptim3_out adc_ext_trg20 A -

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Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

TIM1 TRGO adc_jext_trg0 SI -

APB2
TIM1 CC4 adc_jext_trg1 S -
TIM2 TRGO adc_jext_trg2 S -
D2
TIM2 CC1 adc_jext_trg3 S -
APB1
TIM3 CC4 adc_jext_trg4 S -
TIM4 TRGO adc_jext_trg5 S -
D3 APB4 SYSCFG EXTI15 adc_jext_trg6 A -
TIM8 CC4 adc_jext_trg7 S -
TIM1 TRGO2 adc_jext_trg8 S -
APB2
TIM8 TRGO adc_jext_trg9 S -
TIM8 TRGO2 adc_jext_trg10 S -
ADC3 AHB4 D3
TIM3 CC3 adc_jext_trg11 S -
TIM3 TRGO adc_jext_trg12 S -
APB1
D2 TIM3 CC1 adc_jext_trg13 S -
TIM6 TRGO adc_jext_trg14 S -
TIM15 TRGO adc_jext_trg15 S -
hrtim_adc_
HRTIM1 adc_jext_trg16 A -
APB2 trg2
hrtim_adc_
HRTIM1 adc_jext_trg17 A -
trg4
APB1 LPTIM1 OUT adc_jext_trg18 A -
LPTIM2 OUT adc_jext_trg19 A -
D3 APB4
LPTIM3 OUT adc_jext_trg20 A -
TIM1 OC5 comp_blk1 I -
APB2
TIM1 OC3 comp_blk2 I -
TIM3 OC3 comp_blk3 COMP1 I -
D2 APB1 APB4 D3
TIM3 OC4 comp_blk4 / COMP2 I -
TIM8 OC5 comp_blk5 I -
APB2
TIM15 OC1 comp_blk6 I -

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Table 98. Peripherals interconnect matrix details(1) (continued)

Source Destination
Type Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

TIM2 TRGO SWT0 A -

APB1
TIM3 TRGO SWT1 A -
AHB1 ETH PPS SWT2 A -
hrtim_dac_
APB2 HRTIM1 SWT3 A -
trg1
FDCAN APB1 D2
TIM2 TRGO EVT0 A -
APB1
TIM3 TRGO EVT1 A -
D2 AHB1 ETH PPS EVT2 A -
hrtim_dac_
APB2 HRTIM1 EVT3 A -
trg1
TIM2 TRGO PTP0 A -
APB1
TIM3 TRGO PTP1 A -
hrtim_dac_ ETH AHB1 D2
APB2 HRTIM1 PTP2 A -
trg2
APB1 CAN TMP PTP3 A -
1. Letters in the table correspond to the type of connection described in Section 13.1.2: Connection overview.
2. comp1_out and comp2_out are connected to the inputs of an OR gate. The output of this OR gate is connected to the The
lptim2_in1_mux3 input.

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13.2 Wakeup from low power modes

The Extended interrupt and event controller module (EXTI) allows to wake up the system
from Stop mode and/or a CPU from CStop mode. Wakeup events are coming from
peripherals.
These events are handled by the EXTI either as Configurable events (C), or as Direct
events (D). See Type column in Table 99. Refer to Section 20: Extended interrupt and event
controller (EXTI) for further details.
Three types of peripheral output signals are connected to the EXTI input events:
• The wake up signals. These signals can be generated by the peripheral without any
bus interface clock, they are referred to as xxx_wkup in Table 99. Some peripherals do
not have this capability.
• The interrupt signals. These signals can be generated only if the peripheral bus
interface clock is running. These interrupt signals are generally directly connected to
the NVIC of CPU. They are referred to as xxx_it.
• The signals, i.e. the pulses generated by the peripheral. Once a peripheral has
generated a signal, no action (flag clearing) is required at peripheral level.
Each EXTI input event has a different wakeup capability or possible target (see Target
column in Table 99):
• CPU wakeup (CPU): the input event can be enabled to wake up the CPU
• CPU and D3 domain wakeup for autonomous Run mode (ANY): the input event can be
enabled to wake up the CPU or the D3 domain only for an autonomous Run mode
phase.

594/3353 RM0433 Rev 8

RM0433 Block interconnect

Table 99. EXTI wakeup inputs(1)

Source Destination
Type Target Comment
Domain Bus Peripheral Signal Signal Peripheral

exti0_wkup WKUP0 -
exti1_wkup WKUP1 -
exti2_wkup WKUP2 -
exti3_wkup WKUP3 -
exti4_wkup WKUP4 -
exti5_wkup WKUP5 -
exti6_wkup WKUP6 -
exti7_wkup WKUP7 -
D3 APB4 SYSCFG C ANY
exti8_wkup WKUP8 -
exti9_wkup WKUP9 -
exti10_wkup WKUP10 -
exti11_wkup WKUP11 -
exti12_wkup WKUP12 -
exti13_wkup WKUP13 -
exti14_wkup WKUP14 -
EXTI
exti15_wkup WKUP15 -
D3 AHB4 PWR pvd_avd_wkup WKUP16 C CPU -
D3 APB4 RTC ALARMS WKUP17 D CPU -
TAMPER
D3 APB4 RTC -
TIMESTAMP WKUP18 C CPU
D3 AHB4 RCC CSS_LSE -
D3 APB4 RTC WKUP WKUP19 C ANY -
D3 APB4 COMP1 comp1_out WKUP20 C ANY -
D3 APB4 COMP2 comp2_out WKUP21 C ANY -
D2 APB1 I2C1 i2c1_wkup WKUP22 C CPU -
D2 APB1 I2C2 i2c2_wkup WKUP23 D CPU -
D2 APB1 I2C3 i2c3_wkup WKUP24 D CPU -
D2 APB1 I2C4 i2c4_wkup WKUP25 D ANY -
D2 APB2 USART1 usart1_wkup WKUP26 D CPU -
D2 APB1 USART2 usart2_wkup WKUP27 D CPU -

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Table 99. EXTI wakeup inputs(1) (continued)

Source Destination
Type Target Comment
Domain Bus Peripheral Signal Signal Peripheral

D2 APB1 USART3 usart3_wkup WKUP28 D CPU -

D2 APB2 USART6 usart6_wkup WKUP29 D CPU -
D2 APB1 UART4 uart4_wkup WKUP30 D CPU -
D2 APB1 UART5 uart5_wkup WKUP31 D CPU -
D2 APB1 UART7 uart7_wkup WKUP32 D CPU -
D2 APB1 UART8 uart8_wkup WKUP33 D CPU -
D3 APB4 LPUART lpuart_rx_wkup WKUP34 D ANY -
D3 APB4 LPUART lpuart_tx_wkup WKUP35 D ANY -
D2 APB2 SPI1 spi1_wkup WKUP36 D CPU -
D2 APB1 SPI2 spi2_wkup WKUP37 D CPU -
D2 APB1 SPI3 spi3_wkup WKUP38 D CPU -
D2 APB2 SPI4 spi4_wkup WKUP39 D CPU -
D2 APB2 SPI5 spi5_wkup WKUP40 D CPU -
D3 APB4 SPI6 spi6_wkup WKUP41 EXTI D ANY -
D2 APB1 MDIOS mdios_wkup WKUP42 D CPU -
D2 AHB1 USB1 usb1_wkup WKUP43 D CPU -
D2 AHB1 USB2 usb2_wkup WKUP44 D CPU -
- - NC NC WKUP45 - - -
D2 APB1 LPTIM1 lptim1_wkup WKUP47 D CPU -
D3 APB4 LPTIM2 lptim2_wkup WKUP48 D ANY -
(2)
D3 APB4 LPTIM2 lptim2_out WKUP49 C ANY
D3 APB4 LPTIM3 lptim3_wkup WKUP50 D ANY -
(2)
D3 APB4 LPTIM3 lptim3_out WKUP51 C ANY
D3 APB4 LPTIM4 lptim4_wkup WKUP52 D ANY -
D3 APB4 LPTIM5 lptim5_wkup WKUP53 D ANY -
D2 APB1 SWPMI swpmi_wkup WKUP54 D CPU -

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Table 99. EXTI wakeup inputs(1) (continued)

Source Destination
Type Target Comment
Domain Bus Peripheral Signal Signal Peripheral

pwr_wkup1_wkup WKUP55 -
pwr_wkup2_wkup WKUP56 -
pwr_wkup3_wkup WKUP57 -
D3 AHB4 PWR D CPU
pwr_wkup4_wkup WKUP58 -
pwr_wkup5_wkup WKUP59 -
pwr_wkup6_wkup WKUP60 -
D3 AHB4 RCC rcc_it WKUP61 D CPU -
(1)
I2C4 i2c4_ev_it WKUP62 D CPU
D3 APB4
I2C4 i2c4_err_it WKUP63 D CPU (1)

(1)
D3 APB4 LPUART1 lpuart1_it WKUP64 D CPU
(1)
D3 APB4 SPI6 spi6_it WKUP64 D CPU
bdma_ch0_it WKUP66 D CPU (1)

bdma_ch1_it WKUP67 D CPU (1)

bdma_ch2_it WKUP68 D CPU (1)

(1)
bdma_ch3_it WKUP69 D CPU
D3 AHB4 BDMA
bdma_ch4_it WKUP70 D CPU (1)

bdma_ch5_it WKUP71 EXTI D CPU (1)

(1)
bdma_ch6_it WKUP72 D CPU
bdma_ch7_it WKUP73 D CPU (1)

D3 AHB4 DMAMUX2 dmamux2_it WKUP74 CPU (1)

(1)
D3 AHB4 ADC3 adc3_it WKUP75 D CPU
D3 APB4 SAI4 sai4_gbl_it WKUP76 D CPU (1)

(1)
D3 AHB4 HSEM hsem_int_it WKUP77 D CPU
- - NC NC WKUP81 - - -
(1)
D1 APB3 WWDG1 wwdg1_out_rst WKUP82 C CPU
- - NC NC WKUP83 - - -
D1 APB1 CEC cec_wkup WKUP85 C CPU -
D2 AHB1 ETH eth WKUP86 C CPU -
D3 AHB4 RCC hse_css_rcc_wkup WKUP87 D CPU -
1. The source peripheral needs its bus clock in order to generate the event. This is either PCLK4 or HCLK4 in D3 domain,
PCLK3 in D1 domain.
2. The source peripheral signal is not connected to the NVIC.

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The Extended Interrupt and Event Controller (EXTI) module event inputs able to wake up
the D3 domain for autonomous Run mode have a pending request logic that can be cleared
by 4 different input sources (Table 100). Refer to Section 20: Extended interrupt and event
controller (EXTI) for further details.

Table 100. EXTI pending requests clear inputs

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

dmamux2_evt6 d3_pendclear_in[0] -
AHB4 DMAMUX2
dmamux2_evt7 d3_pendclear_in[1] -
D3 EXTI APB4 D3
LPTIM4 lptim4_out d3_pendclear_in[2] -
APB4
LPTIM5 lptim5_out d3_pendclear_in[3] -

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13.3 DMA
In D1 domain, the MDMA allows the memory to transfer data. It can be triggered by software
or by hardware, according to the connections described in Section 13.3.1.
DMA Multiplexer in D2 domain (DMAMUX1) allows to map any peripheral DMA request to
any stream of the DMA1 or the DMA2. In addition to this, The DMAMUX provides two other
functionalities:
• It’s possible to synchronize a peripheral DMA request with a timer, with an external pin
or with a DMA transfer complete of another stream.
• DMA requests can be generated on a stream by the DMAMUX1 itself. This event can
be triggered by a timer, by an external pin event, or by a DMA transfer complete of
another stream. The number of DMA requests generated is configurable.
The connections on DMAMUX1 and DMA1/DMA2 are described in Section 17: DMA
request multiplexer (DMAMUX), Section 15: Direct memory access controller (DMA) and
Section 16: Basic direct memory access controller (BDMA).
DMA Multiplexer in D3 domain (DMAMUX2) has the same functionality of DMAMUX1, it is
connected to the basic DMA (BDMA).
The connections on DMAMUX2 and BDMA are described in Section 13.3.3: DMAMUX2,
BDMA (D3 domain). Refer to Section 13.3.3: DMAMUX2, BDMA (D3 domain) and
Section 16: Basic direct memory access controller (BDMA) for more details.

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13.3.1 MDMA (D1 domain)

Table 101. MDMA

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

DMA1 stream 0 transfer

dma1_tcif0 mdma_str0
complete
DMA1 stream 1 transfer
dma1_tcif1 mdma_str1
complete
DMA1 stream 2 transfer
dma1_tcif2 mdma_str2
complete
DMA1 stream 3 transfer
dma1_tcif3 mdma_str3
complete
D2 AHB1 DMA1
DMA1 stream 4 transfer
dma1_tcif4 mdma_str4
complete
DMA1 stream 5 transfer
dma1_tcif5 mdma_str5
complete flag
DMA1 stream 6 transfer
dma1_tcif6 mdma_str6
complete
DMA1 stream 7 transfer
dma1_tcif7 mdma_str7
complete
MDMA AXI D1 DMA2 stream 0 transfer
dma2_tcif0 mdma_str8
complete
DMA2 stream 1 transfer
dma2_tcif1 mdma_str9
complete
DMA2 stream 2 transfer
dma2_tcif2 mdma_str10
complete
DMA2 stream 3 transfer
dma2_tcif3 mdma_str11
complete
D2 AHB1 DMA2
DMA2 stream 4 transfer
dma2_tcif4 mdma_str12
complete
DMA2 stream 5 transfer
dma2_tcif5 mdma_str13
complete
DMA2 stream 6 transfer
dma2_tcif6 mdma_str14
complete
DMA2 stream 7 transfer
dma2_tcif7 mdma_str15
complete
D1 APB3 LTDC ltdc_li_it mdma_str16 LTDC line interrupt

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Table 101. MDMA (continued)

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

jpeg_ift_trg mdma_str17 JPEG input FIFO threshold

jpeg_ifnt_trg mdma_str18 JPEG input FIFO not full
JPEG output FIFO
jpeg_oft_trg mdma_str19
D1 AHB3 JPEG threshold
JPEG output FIFO not
jpeg_ofne_trg mdma_str20
empty
jpeg_oec_trg mdma_str21 JPEG end of conversion
quadspi_ft_trg mdma_str22 QUADSPI FIFO threshold
D1 AHB3 QUADSPI QUADSPI transfer
quadspi_tc_trg mdma_str23
complete
DMA2D CLUT transfer
dma2d_clut_trg mdma_str24
complete
D1 AHB3 DMA2D dma2d_tc_trg mdma_str25 MDMA AXI D1 DMA2D transfer complete
DMA2D transfer
dma2d_tw_trg mdma_str26
watermark
sdmmc1_
D1 AHB3 SDMMC1 mdma_str29 End of data
dataend_trg

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13.3.2 DMAMUX1, DMA1 and DMA2 (D2 domain)

Table 102. DMAMUX1, DMA1 and DMA2 connections(1)

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

dmamux1_req_in1
dmamux1_req_in2
dmamux1_req_in3

dmamux1 internal dmamux1_req_in4

D3 AHB4
(Request generator) NC
NC
NC
NC
D2 AHB1 ADC1 adc1_dma dmamux1_req_in9
D2 AHB1 ADC2 adc2_dma dmamux1_req_in10
tim1_ch1_dma dmamux1_req_in11
tim1_ch2_dma dmamux1_req_in12
tim1_ch3_dma dmamux1_req_in13
D2 APB2 TIM1 tim1_ch4_dma dmamux1_req_in14
tim1_up_dma dmamux1_req_in15
tim1_trig_dma dmamux1_req_in16
DMAMUX1 AHB1 D2 Requests
tim1_com_dma dmamux1_req_in17
tim2_ch1_dma dmamux1_req_in18
tim2_ch2_dma dmamux1_req_in19
D2 APB1 TIM2 tim2_ch3_dma dmamux1_req_in20
tim2_ch4_dma dmamux1_req_in21
tim2_up_dma dmamux1_req_in22
tim3_ch1_dma dmamux1_req_in23
tim3_ch2_dma dmamux1_req_in24
tim3_ch3_dma dmamux1_req_in25
D2 APB1 TIM3
tim3_ch4_dma dmamux1_req_in26
tim3_up_dma dmamux1_req_in27
tim3_trig_dma dmamux1_req_in28
tim4_ch1_dma dmamux1_req_in29
tim4_ch2_dma dmamux1_req_in30
D2 APB1 TIM4
tim4_ch3_dma dmamux1_req_in31
tim4_up_dma dmamux1_req_in32

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Table 102. DMAMUX1, DMA1 and DMA2 connections(1) (continued)

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

i2c1_rx_dma dmamux1_req_in33
D2 APB1 I2C1
i2c1_tx_dma dmamux1_req_in34
i2c2_rx_dma dmamux1_req_in35
D2 APB1 I2C2
i2c2_tx_dma dmamux1_req_in36
spi1_rx_dma dmamux1_req_in37
D2 APB2 SPI1
spi1_tx_dma dmamux1_req_in38
spi2_rx_dma dmamux1_req_in39
D2 APB1 SPI2
spi2_tx_dma dmamux1_req_in40
usart1_rx_dma dmamux1_req_in41
D2 APB2 USART1
usart1_tx_dma dmamux1_req_in42
usart2_rx_dma dmamux1_req_in43
D2 APB1 USART2
usart2_tx_dma dmamux1_req_in44
usart3_rx_dma dmamux1_req_in45
D2 APB1 USART3
usart3_tx_dma dmamux1_req_in46
tim8_ch1_dma dmamux1_req_in47
tim8_ch2_dma dmamux1_req_in48
DMAMUX1 AHB1 D2 Requests
tim8_ch3_dma dmamux1_req_in49
D2 APB2 TIM8 tim8_ch4_dma dmamux1_req_in50
tim8_up_dma dmamux1_req_in51
tim8_trig_dma dmamux1_req_in52
tim8_com_dma dmamux1_req_in53
- - NC NC NC
tim5_ch1_dma dmamux1_req_in55
tim5_ch2_dma dmamux1_req_in56
tim5_ch3_dma dmamux1_req_in57
D1 APB1 TIM3
tim5_ch4_dma dmamux1_req_in58
tim5_up_dma dmamux1_req_in59
tim5_trig_dma dmamux1_req_in60
spi3_rx_dma dmamux1_req_in61
D2 APB1 SPI3
spi3_tx_dma dmamux1_req_in62
uart4_rx_dma dmamux1_req_in63
D1 APB1 UART4
uart4_tx_dma dmamux1_req_in64

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Table 102. DMAMUX1, DMA1 and DMA2 connections(1) (continued)

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

uart5_rx_dma dmamux1_req_in65
D1 APB1 UART5
uart5_tx_dma dmamux1_req_in66
D2 APB1 DAC1 dac_ch1_dma dmamux1_req_in67
D2 APB1 DAC2 dac_ch2_dma dmamux1_req_in68
D2 APB1 TIM6 tim6_up_dma dmamux1_req_in69
D2 APB1 TIM7 tim7_up_dma dmamux1_req_in70
usart6_rx_dma dmamux1_req_in71
D2 APB2 USART6
usart6_tx_dma dmamux1_req_in72
i2c3_rx_dma dmamux1_req_in73
D2 APB1 I2C3
i2c3_tx_dma dmamux1_req_in74
D2 AHB2 DCMI dcmi_dma dmamux1_req_in75
cryp_in_dma dmamux1_req_in76
D2 AHB2 CRYP
cryp_out_dma dmamux1_req_in77
D2 AHB2 HASH hash_in_dma dmamux1_req_in78
uart7_rx_dma dmamux1_req_in79
D2 APB1 UART7 DMAMUX1 AHB1 D2 Requests
uart7_tx_dma dmamux1_req_in80
uart8_rx_dma dmamux1_req_in81
D2 APB1 UART8
uart8_tx_dma dmamux1_req_in82
spi4_rx_dma dmamux1_req_in83
D2 APB2 SPI4
spi4_tx_dma dmamux1_req_in84
spi5_rx_dma dmamux1_req_in85
D2 APB2 SPI5
spi5_tx_dma dmamux1_req_in86
sai1_a_dma dmamux1_req_in87
D2 APB2 SAI1
sai1_b_dma dmamux1_req_in88
sai2_a_dma dmamux1_req_in89
D2 APB2 SAI2
sai2_b_dma dmamux1_req_in90
swpmi_rx_dma dmamux1_req_in91
D2 APB1 SWPMI
swpmi_tx_dma dmamux1_req_in92
spdifrx_dt_dma dmamux1_req_in93
D2 APB1 SPDIFRX
spdifrx_cs_dma dmamux1_req_in94

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Table 102. DMAMUX1, DMA1 and DMA2 connections(1) (continued)

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

hrtim_dma1 dmamux1_req_in95
hrtim_dma2 dmamux1_req_in96
hrtim_dma3 dmamux1_req_in97
D2 APB2 HRTIM1
hrtim_dma4 dmamux1_req_in98
hrtim_dma5 dmamux1_req_in99
hrtim_dma6 dmamux1_req_in100
dfsdm1_dma0 dmamux1_req_in101
dfsdm1_dma1 dmamux1_req_in102
D2 APB2 DFSDM1
dfsdm1_dma2 dmamux1_req_in103
dfsdm1_dma3 dmamux1_req_in104
tim15_ch1_dma dmamux1_req_in105 DMAMUX1 AHB1 D2 Requests
tim15_up_dma dmamux1_req_in106
D2 APB2 TIM15
tim15_trig_dma dmamux1_req_in107
tim15_com_dma dmamux1_req_in108
tim16_ch1_dma dmamux1_req_in109
D2 APB2 TIM16
tim16_up_dma dmamux1_req_in110
tim17_ch1_mda dmamux1_req_in111
D2 APB2 TIM17
tim17_up_dma dmamux1_req_in112
sai3_a_dma dmamux1_req_in113
D2 APB2 SAI3
sai3_b_dma dmamux1_req_in114
D3 AHB4 ADC3 adc3_dma dmamux1_req_in115
dmamux1_evt0 dmamux1_gen0
D2 AHB1 DMAMUX1 dmamux1_evt1 dmamux1_gen1
dmamux1_evt2 dmamux1_gen2
D2 APB1 LPTIM1 lptim1_out dmamux1_gen3 Request
DMAMUX1 AHB1 D2
D2 APB1 LPTIM2 lptim2_out dmamux1_gen4 generation

D2 APB1 LPTIM3 lptim3_out dmamux1_gen5

D3 APB4 EXTI exti_exti0_it dmamux1_gen6
D2 APB1 TIM12 tim12_trgo dmamux1_gen7

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Table 102. DMAMUX1, DMA1 and DMA2 connections(1) (continued)

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

dmamux1_evt0 dmamux1_trg0
D2 AHB1 DMAMUX1 dmamux1_evt1 dmamux1_trg1
dmamux1_evt2 dmamux1_trg2
D2 APB1 LPTIM1 lptim1_out dmamux1_trg3
DMAMUX1 AHB1 D2 Triggers
D2 APB1 LPTIM2 lptim2_out dmamux1_trg4
D2 APB1 LPTIM3 lptim3_out dmamux1_trg5
D3 APB4 EXTI exti_exti0_it dmamux1_trg6
D2 APB1 TIM12 tim12_trgo dmamux1_trg7
dmamux1_req_out0 dma1_str0
dmamux1_req_out1 dma1_str1
dmamux1_req_out2 dma1_str2
dmamux1_req_out3 dma1_str3
DMA1 AHB1 D2
dmamux1_req_out4 dma1_str4
dmamux1_req_out5 dma1_str5
dmamux1_req_out6 dma1_str6
dmamux1_req_out7 dma1_str7 Requests
D2 AHB1 DMAMUX1
dmamux1_req_out8 dma2_str0 out

dmamux1_req_out9 dma2_str1
dmamux1_req_out10 dma2_str2
dmamux1_req_out11 dma2_str3
DMA2 AHB1 D2
dmamux1_req_out12 dma2_str4
dmamux1_req_out13 dma2_str5
dmamux1_req_out14 dma2_str6
dmamux1_req_out15 dma2_str7
1. The “-” symbol in grayed cells means no interconnect.

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13.3.3 DMAMUX2, BDMA (D3 domain)

Table 103. DMAMUX2 and BDMA connections

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

dmamux2_req_in1
dmamux2_req_in2
dmamux2_req_in3

dmamux2 internal dmamux2_req_in4

D3 AHB4
(Request generator) NC
NC
NC
NC
dma_rx_lpuart dmamux2_req_in9 DMAMUX2 AHB4 D3 Requests
D3 APB4 LPUART
dma_tx_lpuart dmamux2_req_in10
dma_rx_spi6 dmamux2_req_in11
D3 APB4 SPI6
dma_tx_spi6 dmamux2_req_in12
dma_rx_i2c4 dmamux2_req_in13
D2 APB1 I2C4
dma_tx_i2c4 dmamux2_req_in14
dma_a_sai4 dmamux2_req_in15
D3 APB4 SAI4
dma_b_sai4 dmamux2_req_in16
D3 APB4 ADC3 dma_adc3 dmamux2_req_in17

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Table 103. DMAMUX2 and BDMA connections (continued)

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

dmamux2_evt0 dmamux2_gen0
dmamux2_evt1 dmamux2_gen1
dmamux2_evt2 dmamux2_gen2
D3 AHB4 DMAMUX2 dmamux2_evt3 dmamux2_gen3
dmamux2_evt4 dmamux2_gen4
dmamux2_evt5 dmamux2_gen5
dmamux2_evt6 dmamux2_gen6
exti_lpuart_rx_it dmamux2_gen7
exti_lpuart_tx_it dmamux2_gen8
exti_lptim2_wkup dmamux2_gen9
exti_lptim2_out dmamux2_gen10
exti_lptim3_wkup dmamux2_gen11
exti_lptim3_out dmamux2_gen12
exti_lptim4_wkup dmamux2_gen13
D3 APB4 EXTI exti_lptim5_wkup dmamux2_gen14 Request
DMAMUX2 AHB4 D3
exti_i2c4_wkup dmamux2_gen15 generation

exti_spi6_wkup dmamux2_gen16
exti_comp1_out dmamux2_gen17
exti_comp2_out dmamux2_gen18
exti_rtc_wkup dmamux2_gen19
exti_syscfg_exti0 dmamux2_gen20
exti_syscfg_exti2 dmamux2_gen21
D3 APB4 I2C4 it_evt_i2c4 dmamux2_gen22
D3 APB4 SPI6 it_spi6 dmamux2_gen23
it_tx_lpuart1 dmamux2_gen24
D3 APB4 LPUART
it_rx_lpuart1 dmamux2_gen25
it_adc3 dmamux2_gen26
D3 AHB4 ADC3
out_awd1_adc3 dmamux2_gen27
it_ch0_bdma dmamux2_gen28
D3 AHB4 BDMA
it_ch1_bdma dmamux2_gen29

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Table 103. DMAMUX2 and BDMA connections (continued)

Source Destination
Comment
Domain Bus Peripheral Signal Signal Peripheral Bus Domain

dmamux2_evt0 dmamux2_trg0
dmamux2_evt1 dmamux2_trg1
dmamux2_evt2 dmamux2_trg2
D3 AHB4 DMAMUX2
dmamux2_evt3 dmamux2_trg3
dmamux2_evt4 dmamux2_trg4
dmamux2_evt5 dmamux2_trg5
it_exti_tx_lpuart1 dmamux2_trg6
it_exti_rx_lpuart1 dmamux2_trg7
DMAMUX2 AHB4 D3 Triggers
it_exti_out_lptim2 dmamux2_trg8
it_exti_out_lptim3 dmamux2_trg9
it_exti_wkup_i2c4 dmamux2_trg10
D3 APB4 EXTI
it_exti_wkup_spi6 dmamux2_trg11
it_exti_out_comp1 dmamux2_trg12
it_exti_wkup_rtc dmamux2_trg13
it_exti_exti0_syscfg dmamux2_trg14
it_exti_exti2_syscfg dmamux2_trg15
dmamux1_req_out0 bdma_ch0
dmamux1_req_out1 bdma_ch1
dmamux1_req_out2 bdma_ch2
dmamux1_req_out3 bdma_ch3
D3 AHB4 DMAMUX2 BDMA AHB4 D3 Requests out
dmamux1_req_out4 bdma_ch4
dmamux1_req_out5 bdma_ch5
dmamux1_req_out6 bdma_ch6
dmamux1_req_out7 bdma_ch7

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14 MDMA controller (MDMA)

14.1 MDMA introduction

The master direct memory access (MDMA) is used in order to provide high-speed data
transfer between memory and memory, or between peripherals and memory. Data can be
quickly moved by the MDMA without any CPU action. This keeps the CPU resources free
for other operations.
The MDMA controller provides a master AXI interface for main memory and peripheral
register access (system access port) and a master AHB interface only for Cortex-M7 TCM
memory access (TCM access port).
The MDMA works in conjunction with the standard DMA controllers (DMA1 or DMA2).
It offers up to 16 channels, each dedicated to manage memory access requests from one of
the DMA stream memory buffer or other peripherals (with integrated FIFO).

14.2 MDMA main features

• AXI/AHB master bus architecture, one dedicated to main memory/peripheral accesses
and one dedicated to Cortex-M7 AHBS port (only for TCM accesses).
• 16 channels
• Up to 32 hardware trigger sources
• Each channel request can be selected among any of the request sources. This
selection is software-configurable and allows several peripherals to initiate DMA
requests. The trigger selection can be automatically changed at the end of one block
transfer.
• All channels are identical and can be connected either to a standard DMA or a
peripheral request (acknowledge by data read/write) system
• Each channel also supports software trigger.
• One 256-level memory buffer, split in two 128-level first-in, first-out (FIFO), that is used
to store temporary the data to be transferred (in burst or single transfer mode), for one
or two consecutive buffers. The FIFO stores the data that are transferred during the
current channel block transfer (up to the block transfer size). The second FIFO can be
used for the next buffer to be transferred, either for the same channel or for the next
channel transfer.
• The priorities between DMA channels are software-programmable (four levels
consisting of very-high, high, medium, low) or hardware in case of equality
(for example, channel 0 has priority over channel 1)
• Independent source and destination transfer width (byte, half-word, word,
double-word): when the data widths of the source and destination are not equal, the
MDMA can pack/unpack the necessary data to optimize the bandwidth.
• The size and address increment for both source and destination can be independently
selected.

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Note: Based on this separation, some more advanced packing/unpacking operations are available
at software level. As an example, 2 x 16-bit data blocks can be interleaved together using
two MDMA channels, in the destination memory, by simply programming the two channels
with an increment step of 4 bytes and a data size of 16 bits + a start address shifted by two
between the two channels.
• Incrementing, decrementing or non incrementing/fixed addressing for source and
destination
• Data packing/unpacking is always done respecting the little endian convention: lower
address in a data entity (double-word, word, or half-word) contains always the lowest
significant byte. This is independent of the address increment/decrement mode of both
source and destination.
• Supports incremental burst transfers. The size of the burst is software-configurable,
up to 128 bytes. For larger data sizes the burst length is limited, as to respect the
maximum 128 bytes data burst size (such as 16 x 64 bits or 32 x 32 bits).
• For the TCM memory accesses, the burst access is only allowed when the increment
and data size are identical and lower than or equal to 32 bits.
• Five event flags (MDMA channel transfer complete, MDMA block transfer complete,
MDMA block repeat transfer Complete, MDMA buffer transfer Complete, MDMA
transfer error) are available and can generate interrupts.

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14.3 MDMA functional description

14.3.1 MDMA block diagram

The figure below shows the block diagram of the MDMA.

Figure 77. MDMA block diagram

64-bit AXI master

Read/
mdma_it write

system bus
requests

mdma_str0

FIFO

FIFO
Arbiter
mdma_str31 32
Read/

master AHB
32-bit TCM
write
TSEL=31

requests
TSEL=0
(programming
Slave AHB

8 8
port)

Programming
Interface
mdma_hclk

MSv41057V3

14.3.2 MDMA internal signals

The table below shows the internal MDMA signals.

Table 104. MDMA internal input/output signals

Signal name Signal type Description

mdma_hclk Digital input MDMA AHB clock

mdma_it Digital output MDMA interrupt
mdma_str[0:31] Digital input MDMA stream request

14.3.3 MDMA overview

The MDMA performs a direct memory transfer: as an AXI/AHB master, the MDMA can take
the control of the AXI/AHB bus matrix to initiate AXI/AHB transactions.

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The MDMA can carry out the following transactions:

• memory-to-memory (software triggered)
• peripheral-to-memory
• memory-to-peripheral
For the last two transaction types, the memory can also be replaced by a memory-mapped
peripheral, which has no control over the MDMA flow. When these types of transaction are
used and the request comes from a standard DMA (DMA1 or DMA2), the peripheral register
access is replaced by a memory access to the memory buffer used by this DMA.
Note: Non-incrementing/decrementing mode is not used for memory accesses.
The source and destination are simply defined by the address (peripherals being
memory-mapped also).
The AHB slave port is used to program the MDMA (it supports 8-,16-, and 32-bit accesses).
The size of the data array to be transferred for a single request is one of the following:
• buffer transfer size
• block size
• repeated block
• complete channel data (until the linked-list pointer for the channel is null)
The choice of the size is done through the TRGM[1:0] (Trigger mode) selection field.
The user must choose one of them based on the data array size available (usually in the
DMA1/2 memory buffer) and the “real time” requirements for other MDMA channels
(knowing that a buffer transfer is the minimum data aggregate to be transferred by the
MDMA without doing a new arbitration between MDMA channel requests).
For each channel, there are three key data array sizes:
• Burst size: this is the length of the data transfer which can be performed in burst mode.
This burst length defines the maximum transfer length which cannot be interrupted at
bus arbitration level and can block other masters from accessing the bus.
• Buffer transfer size: this is the length of the data array to be transferred, on a channel,
before checking for MDMA requests on other channels. This is the data array transfer
lengths which cannot be interrupted at MDMA level (from other channel requests).
• Block size: this value has two meanings which can be used together:
– main: this is length of the data block which is described in a block structure of the
MDMA linked list (corresponds to one entry in the linked list)
– selectable: when TRGM[1:0] equals 01, this is the length of the data array which is
transferred on a single MDMA request activation (for the respective channel)

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14.3.4 MDMA channel

Each MDMA channel provides an unidirectional transfer link between a source and
a destination.
Each channel can perform transfer of the following types:
• Single block transfer: one block is transferred. At the end of the block, the MDMA
channel is disabled and an end-of-channel transfer interrupt is generated.
• Repeated block transfer: a number of blocks is transferred before disabling the
channel.
• Linked-list transfer: when the transfer of the current data block (or last block in a
repeat) is completed, a new block control structure is loaded from memory and a new
block transfer is started.
The minimum amount of data to be transferred for each request (buffer size,
up to 128 bytes) is programmable. The total amount of data in a block, is programmable
up to 64 Kbytes. This value is decremented after each transfer. When this counter reaches
zero, the end of the block is reached and an action is taken based on the repeat counter
(for repeated block transfer) and/or linked-list structure value.
Note: If the block length is not a multiple of the buffer length, the last buffer transfer in the block is
shorter, covering the remaining bytes to be transferred in the current block.
If the link structure address points to a valid memory address, the MDMA reloads the whole
channel descriptor structure register contents from memory at this address. Then, a new
block transfer is then executed (on the next MDMA channel request) based on this
information.
If the link structure address is 0x0, at the end of the current/repeated block transfer, the
MDMA channel is disabled and the end-of-channel transfer interrupt is generated.

14.3.5 Source, destination and transfer modes

Both source and destination transfers can address peripherals and memories in the entire
4-Gbyte area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.
The source/destination addresses can be fixed (such as FIFO/single data register
peripherals) or incremented/decremented. The transfer can be done in single access or in
burst mode (programmable).

14.3.6 Pointer update

The source and destination memory pointers can optionally be automatically
post-incremented/decremented, or kept constant after each transfer depending on the
SINC[1:0] and DINC[1:0] bitfields in the MDMA_CxCR register.
Disabling the increment mode is useful when the peripheral source or destination data are
accessed through a single register/FIFO mode.
If the increment/decrement mode is enabled, the address of the next data transfer is the
address of the previous one incremented/decrement by 1, 2, 4 or 8 depending on the
increment size programmed in SINCOS[1:0] or DINCOS[1:0] in MDMA_CxCR.
In order to optimize the packing operation, the increment offset size and the data size are
programmable independently.

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14.3.7 MDMA buffer transfer

This is the minimum logical amount of data (up to 128 bytes) which is transferred on an
MDMA request event, on one channel.
An MDMA buffer transfer consists of a sequence of a given number of data transfers (done
as single or burst data transfers). The number of data items to be transferred and their width
(8, 16, 32, or 64 bits) are software programmable. The length of the burst used for data
transfers is also programmable, independently.
After an event requiring a data array to be transferred, the DMA/peripheral sends a request
signal to the MDMA, which serves the request depending on the channel priorities.
The request is acknowledged by writing the mask data value to the address given mask
address, when these registers are set.
If the mask address register is not set (0x00 value), the request can be reset by simply
reading/writing the data to the peripheral. In this case, if the request is done by a destination
peripheral, the write must be set as non bufferable, in order to avoid a false new MDMA
request.
The total amount of data to be transferred, on the current channel, following a MDMA
request, is determined by the TRGM[1:0] field.
If TRGM[1:0] equals 00, a single buffer is transferred, then the MDMA waits for another
request on the same channel.
Note: In this case, the hardware request for the currently active channel (data in the FIFO) is not
considered again until the end of the write phase for this channel. Even if the channel is still
active at the end of the read phase, another channel (even with lower priority) can start the
read phase. Lower priority channels can be interleaved with current channel transfer.
If TRGM[1:0] is different from 00 (multiple buffers need to be transferred), the mdma_strx for
the current channel remains active (internally memorized) until the whole transfer defined by
TRGM (block, repeated block or whole channel/linked list data) is completed.
After transferring an individual buffer, the MDMA enters in a new arbitration phase (between
new external requests and internally memorized ones). If no other higher priority, the
channel request is active, and a new buffer transfer is started for the same channel.
Note: When TRGM[1:0] is different from 00, a larger array of data is transferred for a single
request. But, as the channel arbitration is done after each buffer transfer, no higher level
MDMA requests are blocked for the more than a buffer transfer period, on any lower priority
channel.

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14.3.8 Request arbitration

An arbiter manages the MDMA channel requests based on their priority. When the MDMA is
idle and after the end of each buffer transfer, all MDMA requests (hardware or software) are
checked for all enabled channels.
Priorities are managed in two stages:
• Software: each stream priority can be configured in the MDMA_CxCR register. There
are four levels:
– Very high priority
– High priority
– Medium priority
– Low priority
• Hardware: at hardware level, the channel priority is fixed. If two requests have the
same software priority level, the channel with the lower number takes priority over the
stream with the higher number. For example, Channel 2 takes priority over Channel 4
when they have the same software priority level.

14.3.9 FIFO
A FIFO structure is used to temporarily store data coming from the source before writing
them to the destination. There is a central FIFO structure which is used for all channels.
In order to maximize data bandwidth and bus usage, the following mechanisms are used,
allowing multiple read/write operation to be executed in parallel.
• During a buffer transfer, as soon as the FIFO contains enough data for a destination
burst transfer, the write operation starts.
• When the complete data for a buffer transfer has been read into the FIFO, the
arbitration procedure is started. Following that, the next buffer data to be transferred
can be read to the FIFO.
When an active channel is disabled due to an error, during a buffer transfer, the remaining
data in the internal FIFO is discarded.

14.3.10 Block transfer

A block is a “contiguous” array of data, up to 64 Kbytes, which is transferred by successive
buffer transfers.
Each block of data is defined by the start address and the block length. When a block
transfer is completed, one of the following three actions can be executed:
• The block is part of a repeated block transfer: the block length is reloaded and new
block start address is computed (based on the information in MDMA_CxBRUR).
• It is a single block or the last block in a repeated block transfer: the next block
information is loaded from the memory (using the linked list address information,
from MDMA_CxLAR).
• It is the last block which needs to be transferred for the current MDMA channel
(MDMA_CxLAR = 0): the channel is disabled and no further MDMA requests are
accepted for this channel.

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14.3.11 Block repeat mode

The block repeat mode is used to repeat a block transfer, with different start addresses for
source and destination.
When the repeat block mode is active (repeat counter ≠ 0), at the end of the current block
transfer, the block parameters are updated (BNDT value reloaded and SAR/DAR values
updated according to BRSUM/BRDUM configuration), and the repeat counter
decremented by one.
When the repeat block counter reaches 0, this last block is treated as a single block transfer.

14.3.12 Linked-list mode

The linked-list mode allows a new MDMA configuration to be loaded (MDMA_CxTCR,
MDMA_CxBNDTR, MDMA_CxSAR, MDMA_CxDAR, MDMA_CxBRUR, MDMA_CxLAR,
MDMA_CxTBR, MDMA_CxMAR and MDMA_CxMDR registers), from the address given in
MDMA_CxLAR. This address must address a memory mapped on the AXI system bus.
Following this operation, the channel is ready to accept new requests, as defined in the
block/repeated block modes above, or continue the transfer if TRGM[1:0] = 11.
The trigger source can be automatically changed, when loading the MDMA_CxTBR value.
The TRGM and SWRM values must not be changed when TRGM[1:0] = 11.

14.3.13 MDMA transfer completion

Different events can generate an end of transfer by setting the CTCIF bit in the status
register (MDMA_CxISR):
• The MDMA_CxBNDTR counter has reached zero, the Block Repeat Counter is 0 and
the Link list pointer address is 0
• The channel is disabled before the end of transfer (by clearing the EN bit in
MDMA_CxCR) and all the remaining data have been transferred from the FIFO to the
destination

14.3.14 MDMA transfer suspension

At any time, a MDMA transfer can be suspended in order to be to be restarted later on or to
be definitively disabled before the end of the MDMA transfer.
There are two cases:
• The channel is disabled, with no later-on restart from the point where it was stopped.
There is no particular action to do, besides clearing the EN bit in the MDMA_CxCR
register to disable the channel. The stream can take time to be disabled (on going
buffer transfer is completed first). The transfer complete interrupt flag is set in order to
indicate the end of transfer. The value of the EN bit in MDMA_CxCR is now 0 to confirm
the channel interruption. The MDMA_CxNDTR register contains the number of
remaining data items when the channel was stopped. The software can then determine
how many data items have been transferred before the channel was interrupted.
• The channel is suspended before the number of remaining bytes to be transferred in
the MDMA_CxBNDTR register reaches zero. The aim is to restart the transfer later by
re-enabling the channel. The channel transfer complete interrupt flag CTCIF is set in
order to indicate the end of transfer. If the MDMA_CxBNDTR, MDMA_CxSAR and

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MDMA_CxDAR registers are not modified by software, the transfer continues when the
channel is re-enabled. CTCIF must also be reset before restarting the channel.
Note: If the completed buffer is the last of the block, the configuration registers are also updated
before disabling the channel, in order to be correctly prepared for a soft restart.
Before reprogramming the channel, the software must wait the MDMA_CTCIF register is
set, in order to guarantee that any ongoing operation has been completed.

14.3.15 Error management

The MDMA can detect the following errors and the transfer error interrupt flag (TEIF) is set:
• when a bus error occurs during a MDMA read/write access
• when an address alignment does not correspond to the data size
• when the block size is not a multiple of the data size (for source and/or destination): this
error is activated on the last transfer and the error address points to the last transfer
(which cannot be done)

14.4 MDMA interrupts

For each MDMA channel, an interrupt can be produced on the following events:
• Channel transfer completed
• Block-transfer completed
• Block-transfer repeat completed
• Buffer transfer completed
• Transfer error
Separate interrupt enable control bits are available for flexibility as shown in the table below.

Table 105. MDMA interrupt requests

Interrupt event Event flag Enable control bit

Channel transfer completed CTCIF CTCIE

Block-transfer repeat completed BTRIF BTRIE
Block-transfer completed BTIF BTIE
Buffer transfer completed TCIF TCIE
Transfer error TEIF TEIE

Note: Before setting an enable control bit to 1, the corresponding event flag must be cleared,
otherwise an interrupt may be immediately generated, if the bit is already set.
When at least one interrupt flag and the respective enable control bit are set, the channel
interrupt bit is set in the MDMA_GISR. The interrupt output is also activated. This generates
an interrupt if the respective interrupt channel is enabled in the NVIC.

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14.5 MDMA registers

The MDMA registers can be accessed in word, half-word, or byte format.

14.5.1 MDMA global interrupt status register (MDMA_GISR0)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GIF15 GIF14 GIF13 GIF12 GIF11 GIF10 GIF9 GIF8 GIF7 GIF6 GIF5 GIF4 GIF3 GIF2 GIF1 GIF0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 GIF[15:0]: Channel x global interrupt flag (x = 15 to 0)
This bitfield is set and reset by hardware. It is a logical OR of all channel x interrupt flags
(CTCIF, BTIF, BRTIF, TEIF) which are enabled in MDMA_CTCIEx, MDMA_BTIEx,
MDMA_BRTIEx, and MDMA_TEIEx.
0: No interrupt generated by channel x
1: Interrupt generated by channel x

14.5.2 MDMA channel x interrupt status register (MDMA_CxISR)

Address offset: 0x40 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TCIF BTIF BRTIF CTCIF TEIF
r r r r r

Bits 31:17 Reserved, must be kept at reset value.

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Bit 16 CRQA: Channel x request active flag

This bit is set by software writing 1 to SWRQx in MDMA_CxCR, in order to request
an MDMA transfer, and the channel x is enabled.
This bit is also set by hardware when the channel request becomes active, and the channel
is enabled. The hardware request memorized until it is served.
This bit is cleared by hardware when the channel x request is completed (after the source
write phase of the last buffer transfer due for the current request).
0: The MDMA transfer mdma_strx is inactive for channel x.
1: The MDMA transfer mdma_strx is active for channel x
Note: This bit is also reset by hardware when the channel is disabled (in case of transfer
error, or when reaching the end of the channel data transfer - repeat block = 0 and
linked list pointer null-, or by software programming the channel enable bit to 0
before that).
Bits 15:5 Reserved, must be kept at reset value.
Bit 4 TCIF: Channel x buffer transfer complete interrupt flag
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in MDMA_IFCRy.
0: No buffer transfer complete event on channel x
1: A buffer transfer complete event occurred on channel x
TC is set when a single buffer is transferred. It is activated on each channel transfer request.
This can be used as a debug feature (without interrupt), indicating that (at least) an MDMA
buffer transfer has been generated since the last flag reset.
Bit 3 BTIF: Channel x block transfer complete interrupt flag
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in MDMA_IFCRy.
0: No block transfer complete event on channel x
1: A block transfer complete event occurred on channel x.
Bit 2 BRTIF: Channel x block repeat transfer complete interrupt flag
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in MDMA_IFCRy.
0: No block repeat transfer complete event on channel x
1: A block repeat transfer complete event occurred on channel x
Bit 1 CTCIF: Channel x channel transfer complete interrupt flag
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in MDMA_IFCRy.
0: No channel transfer complete event on channel x
1: A channel transfer complete event occurred on channel x
CTC is set when the last block was transferred and the channel has been automatically
disabled.
CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
Bit 0 TEIF: Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in MDMA_IFCRy.
0: No transfer error on stream x
1: A transfer error occurred on stream x

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14.5.3 MDMA channel x interrupt flag clear register (MDMA_CxIFCR)

Address offset: 0x44 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CBRT CCTC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLTCIF CBTIF CTEIF
IF IF
w w w w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CLTCIF: Clear buffer transfer complete Interrupt flag for channel x
Writing 1 into this bit clears TCIF in MDMA_ISRy.
Bit 3 CBTIF: Channel x clear block transfer complete interrupt flag
Writing 1 into this bit clears BTIF in MDMA_ISRy.
Bit 2 CBRTIF: Channel x clear block repeat transfer complete interrupt flag
Writing 1 into this bit clears BRTIF in MDMA_ISRy.
Bit 1 CCTCIF: Clear channel transfer complete interrupt flag for channel x
Writing 1 into this bit clears CTCIF in MDMA_ISRy.
Bit 0 CTEIF: Channel x clear transfer error interrupt flag
Writing 1 into this bit clears TEIF in MDMA_ISRy.

14.5.4 MDMA channel x error status register (MDMA_CxESR)

Address offset: 0x48 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. BSE ASE TEMD TELD TED TEA[6:0]
r r r r r r r r r r r r

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 BSE: Block size error
This bit is set by hardware, when the block size is not an integer multiple of the data size
either for source or destination. TED indicates whether the problem is on the source or
destination. This bit is cleared by software writing 1 to CTEIF in MDMA_IFCRy.
0: No block size error
1: Programmed block size is not an integer multiple of the data size.

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Bit 10 ASE: Address size error

This bit is set by hardware, when the programmed address is not aligned with the data size.
TED indicates whether the problem is on the source or destination. It is cleared by software
writing 1 to CTEIF in MDMA_IFCRy.
0: No address size error
1: Programmed address is not coherent with the data size.
Bit 9 TEMD: Transfer error mask data
This bit is set by hardware, in case of a transfer error while writing the mask data. It is
cleared by software writing 1 to CTEIF in MDMA_IFCRy.
0: No mask write access error
1: The last transfer error on the channel was a related to a write of the mask data.
Bit 8 TELD: Transfer error link data
This bit is set by hardware, in case of a transfer error while reading the block link
data structure. It is cleared by software writing 1 to CTEIF in MDMA_IFCRy.
0: No link data read access error
1: The last transfer error on the channel was a related to a read of the link data structure.
Bit 7 TED: Transfer error direction
This bit is set and cleared by hardware, in case of an MDMA data transfer error.
0: The last transfer error on the channel was a related to a read access.
1: The last transfer error on the channel was a related to a write access.
Bits 6:0 TEA[6:0]: Transfer error address
These bits are set and cleared by hardware in case of an MDMA data transfer error.
They are used in conjunction with TED. This field indicates the 7 LSB bits of the address
which generated a transfer/access error.
This field can be used by software to retrieve the failing address, by adding this value
(truncated to the buffer transfer length size) to the current SAR/DAR value.
Note: The SAR/DAR current value does not reflect this last address due to the FIFO
management system. The SAR/DAR are only updated at the end of a (buffer) transfer
(of TLEN+1 bytes).
This field is not set in case of a link data error.

14.5.5 MDMA channel x control register (MDMA_CxCR)

This register is used to control the concerned channel.
Address offset: 0x4C + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. WEX HEX BEX Res. Res. Res. Res. PL[1:0] TCIE BTIE BRTIE CTCIE TEIE EN
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

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Bit 16 SWRQ: Software request

Writing 1 into this bit sets the CRQA in MDMA_ISRy, activating the request on channel x.
Note: Either the whole MDMA_CxCR register or the 8-/16-bit register at the address offset:
0x4E + 0x40 × channel number, can be used for SWRQ activation.
In case of software request, acknowledge is not generated (neither hardware signal, nor
MDMA_CxMAR write access).
Bit 15 Reserved, must be kept at reset value.
Bit 14 WEX: Word endianness exchange
This bit is set and cleared by software.
0: Little endianness preserved for words
1: Word order exchanged in double word
When this bit is set, the word order in the destination double word is reversed: higher
address word contains the data read from the lower address of the source.
If the destination is not a double word, do not care of this bit value.
Note: This bit is protected and can be written only if EN is 0.
Bit 13 HEX: Half-word endianness exchange
This bit is set and cleared by software.
0: Little endianness preserved for half words
1: half-word order exchanged in each word
When this bit is set, the half-word order in each destination word is reversed: higher address
half-word contains the data read from the lower address of the source.
If destination length is shorter than word, do not care of this bit value.
Note: This bit is protected and can be written only if EN is 0.
Bit 12 BEX: Byte endianness exchange
This bit is set and cleared by software.
0: Little endianness preserved for bytes
1: byte order exchanged in each half-word
When this bit is set, the byte order in each destination half-word is reversed: higher address
word contains the data read from the lower address of the source.
If destination is byte, do not care of this bit value.
Note: This bit is protected and can be written only if EN is 0.
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 Reserved, must be kept at reset value.
Bits 7:6 PL[1:0]: Priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
Note: These bits are protected and can be written only if EN is 0.
Bit 5 TCIE: Buffer transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled

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Bit 4 BTIE: Block transfer interrupt enable

This bit is set and cleared by software.
0: BT complete interrupt disabled
1: BT complete interrupt enabled
Bit 3 BRTIE: Block repeat transfer interrupt enable
This bit is set and cleared by software.
0: BT interrupt disabled
1: BT interrupt enabled
Bit 2 CTCIE: Channel transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
Bit 1 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 0 EN: Channel enable/flag channel ready when read low
This bit is set and cleared by software.
0: Channel disabled
1: Channel enabled
This bit can be cleared by hardware:
– on a MDMA end of transfer (stream ready to be configured)
– if a transfer error occurs on the AHB/AXI master buses (bus error/HardFault)
– if another error condition is encountered (data alignment, block/data size
incompatibility)
When this bit is reset by software, the ongoing buffer transfer (if any) is completed.
All status/configuration registers keep their current values. If the channel is re-enabled
without writing these registers, the channel continues from the point where it was interrupted.
When this bit is read as 0, the software is allowed to program the configuration registers.
It is forbidden to write these registers when the EN bit is read as 1 (writes are ignored).
Note: When this bit is reset by software, it is recommended to wait for the CTCIF = 1, in order
to ensure that any ongoing buffer transfer has been completed, before reprogramming
the channel.

14.5.6 MDMA channel x transfer configuration register (MDMA_CxTCR)

Address offset: 0x50 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000
This register is used to configure the concerned channel. In linked-list mode, at the end
of a block (single or last block in repeated block transfer mode), this register is loaded from
the memory (from address given by current LAR[31:0] + 0x00).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM SWRM TRGM[1:0] PAM[1:0] PKE TLEN[6:0] DBURST[2:1]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURS
SBURST[2:0] DINCOS[1:0] SINCOS[1:0] DSIZE[1:0] SSIZE[1:0] DINC[1:0] SINC[1:0]
T[0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0433 MDMA controller (MDMA)

Bit 31 BWM: Bufferable write mode

This bit is set and cleared by software.
0: The destination write operation is non-bufferable.
1: The destination write operation is bufferable.
Note: This bit is protected and can be written only if EN is 0.
All MDMA destination accesses are non-cacheable.
Bit 30 SWRM: Software request mode
This bit is set and cleared by software. If an hardware or software request is currently active,
the bit change is delayed until the current transfer is completed.
0: Hardware request are taken into account: the transfer is initiated as defined by TRGM
value and acknowledged by the MDMA ACKx signal. If the MDMA_CxMAR contains a valid
address, the MDMA_CxMDR value is also written at MDMA_CxMAR address.
1: Hardware request are ignored. Transfer is triggered by software writing 1 to the SWRQ bit.
Note: This bit is protected and can be written only if EN is 0.
Bits 29:28 TRGM[1:0]: Trigger mode
These bits are set and cleared by software.
00: Each MDMA request (software or hardware) triggers a buffer transfer.
01: Each MDMA request (software or hardware) triggers a block transfer.
10: Each MDMA request (software or hardware) triggers a repeated block transfer
(if the block repeat is 0, a single block is transferred).
11: Each MDMA request (software or hardware) triggers the transfer of the whole data for the
respective channel (for example linked list) until the channel reach the end and it is disabled.
Note: If TRGM is 11 for the current block, all values loaded at the end of the current block
through the linked-list mechanism must keep the same value (TRGM = 11), and the
same SWRM value, otherwise the result is undefined.
These bits are protected and can be written only if EN is 0.
Bits 27:26 PAM[1:0]: Padding/alignment mode
These bits are set and cleared by software.
00: Right aligned, padded with 0s (default). If source data is larger than destination size, only
LSB part of the source is written to the destination address. The reminder part is discarded.
01: Right aligned, sign extended
10: Left aligned (padded with 0s). if source data is larger than destination size, only MSB part
of the source is written to the destination address. The reminder part is discarded.
11: Reserved
Note: When PKE = 1 or DSIZE=SSIZE, these bits are ignored.
These bits are protected and can be written only if EN is 0.
Bit 25 PKE: Pack enable
This bit is set and cleared by software.
0: The source data is written to the destination as is. If source size is smaller than
destination, it is padded according to the PAM value. If source data size is larger than
destination one, it is truncated. The alignment is done according to the PAM[1:0] value.
1: The source data is packed/unpacked into the destination data size. All data are right
aligned, in little-endian mode.
Note: This bit is protected and can be written only if EN is 0.

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Bits 24:18 TLEN[6:0]: Buffer transfer length (number of bytes - 1)

These bits are set and cleared by software. TLEN + 1 value represents the number of bytes
to be transferred in a single transfer.
The transfer length must be a multiple of the data size (for both source and destination)
When the source/destination sizes are different and padding/truncation is used, TLEN + 1
refers to the source data array size.
Note: These bits are protected and can be written only if EN is 0.
DBURST value must be programmed in order to ensure that the burst size is lower
than the transfer size.
Bits 17:15 DBURST[2:0]: Destination burst transfer configuration
These bits are set and cleared by software.
000: Single transfer
N: burst of 2N beats
DBURST value must be programmed as to ensure that the burst size is lower than
the transfer length. If this is not ensured, the result is unpredictable.
Note: These bits are protected and can be written only if EN is 0.
When the destination bus is TCM/AHB (DBUS = 1) and DINCOS = 11 or DINC = 00 or
DINCOS ≠ DSIZE, DBURST must be programmed to 000 (single transfer), else
the result is unpredictable.
When the destination bus is system/AXI bus (DBUS = 0) and DINC = 00, DBURST
must be maximum 100 (burst of 16), else the result is unpredictable.
Bits 14:12 SBURST[2:0]: Source burst transfer configuration
These bits are set and cleared by software.
000: single transfer
N: burst of 2N beats
SBURST value must be programmed as to ensure that the burst size is lower than the
transfer length. If this is not ensured, the result is unpredictable.
Note: These bits are protected and can be written only if EN is 0.
When the source bus is TCM (SBUS = 1) and SINCOS = 11 or SINC = 00 or
SINCOS ≠SSIZE, SBURST must be programmed to 000 (single transfer), else
the result is unpredictable.
When the source bus is system/AXI bus (SBUS = 0) and SINC = 00, SBURST must be
maximum 100 (burst of 16), else the result is unpredictable.
Bits 11:10 DINCOS[1:0]: Destination increment offset size
These bits are set and cleared by software.
00: byte (8-bit)
01: half-word (16-bit)
10: word (32-bit)
11: Double-Word (64-bit) -
This bits have no meaning if bit DINC[1:0] = 00.
Note: If DINCOS < DSIZE and DINC ≠ 00, the result is unpredictable.
If destination is AHB and DBURST ≠ 000, destination address must be aligned with
DINCOS size, else the result is unpredictable.
These bits are protected and can be written only if EN = 0.

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RM0433 MDMA controller (MDMA)

Bits 9:8 SINCOS[1:0]: Source increment offset size

These bits are set and cleared by software.
00: byte (8-bit)
01: half-word (16-bit)
10: word (32-bit)
11: Double-Word (64-bit) -
This bits have no meaning if bit SINC[1:0] = 00.
Note: If SINCOS < SSIZE and SINC ≠ 00, the result is unpredictable.
If source is TCM/AHB and SBURST ≠ 000, source address must be aligned with
SINCOS size, else the result is unpredictable.
These bits are protected and can be written only if EN = 0.
Bits 7:6 DSIZE[1:0]: Destination data size
These bits are set and cleared by software.
00: Byte (8 bits)
01: Half-word (16 bits)
10: Word (32 bits)
11: Double-word (64 bits)
Note: If DINCOS < DSIZE and DINC ≠ 00, the result is unpredictable.
If a value of 11 is programmed for the TCM access/AHB port, a transfer error occurs
(TEIF bit set). DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus
(DBUS = 1).
These bits are protected and can be written only if EN = 0.
Bits 5:4 SSIZE[1:0]: Source data size
These bits are set and cleared by software.
00: Byte (8 bits)
01: Half-word (16 bits)
10: Word (32 bits)
11: Double-word (64 bits)
Note: If SINCOS < SSIZE and SINC ≠ 00, the result is unpredictable.
If a value of 11 is programmed for the TCM access/AHB port, a transfer error occurs
(TEIF bit set). SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus
(SBUS = 1).
These bits are protected and can be written only if EN is 0.
Bits 3:2 DINC[1:0]: Destination increment mode
These bits are set and cleared by software.
00: Destination address pointer is fixed.
10: Destination address pointer is incremented after each data transfer (increment is done
according to DINCOS).
11: Destination address pointer is decremented after each data transfer (increment is done
according to DINCOS).
Note: These bits are protected and can be written only if EN = 0.
When destination is AHB (DBUS = 1), DINC = 00 is forbidden.

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Bits 1:0 SINC[1:0]: Source increment mode

These bits are set and cleared by software.
00: Source address pointer is fixed.
10: Source address pointer is incremented after each data transfer (increment is done
according to SINCOS).
11: Source address pointer is decremented after each data transfer (decrement is done
according to SINCOS).
Note: These bits are protected and can be written only if EN = 0.
When source is AHB (SBUS = 1), SINC = 00 is forbidden.

14.5.7 MDMA channel x block number of data register (MDMA_CxBNDTR)

Address offset: 0x54 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000
In linked-list mode, at the end of a block (single or last block in repeated block transfer
mode), this register is loaded from the memory (from address given by current
LAR[31:0] + 0x04).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRD BRS BNDT
BRC[11:0] Res.
UM UM [16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 BRC[11:0]: Block repeat count

This field contains the number of repetitions of the current block (0 to 4095). When the
channel is enabled, this register is read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements after each complete block transfer.
Once the last block transfer has completed, this register can either stay at zero or be
reloaded automatically from memory (in linked-list mode, meaning link address valid).
Note: These bits are protected and can be written only if EN = 0.
Bit 19 BRDUM: Block repeat destination address update mode
0: At the end of a block transfer, the MDMA_DAR register is updated by adding the DUV to
the current DAR value (current destination address).
1: At the end of a block transfer, the MDMA_DAR register is updated by subtracting the DUV
from the current DAR value (current destination address).
Note: These bits are protected and can be written only if EN = 0.
Bit 18 BRSUM: Block repeat source address update mode
0: At the end of a block transfer, the MDMA_SAR register is updated by adding the SUV to
the current SAR value (current source address).
1: At the end of a block transfer, the MDMA_SAR register is updated by subtracting the SUV
from the current SAR value (current source address).
Note: These bits are protected and can be written only if EN = 0.
Bit 17 Reserved, must be kept at reset value.

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RM0433 MDMA controller (MDMA)

Bits 16:0 BNDT[16:0]: Block number of data bytes to transfer

Number of bytes to be transferred (0 up to 65536) in the current block. When the channel is
enabled, this register is read-only, indicating the remaining data items to be transmitted.
During the channel activity, this register decrements, indicating the number of data items
remaining in the current block.
Once the block transfer has completed, this register can either stay at zero or be reloaded
automatically with the previously programmed value if the channel is configured in block
repeat mode.
If the value of this register is zero, no transaction can be served even if the stream is
enabled.
Note: If the BNDT value is not an integer multiple of the TLEN + 1 value, the last transfer is
shorter and contains only the remaining data in the block.
The block size must be a multiple of the source and destination data size. If this is not
true, an error is set and the no data are written
These bits are protected and can be written only if EN = 0.

14.5.8 MDMA channel x source address register (MDMA_CxSAR)

Address offset: 0x58 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000
In linked-list mode, at the end of a block (single or last block in repeated block transfer
mode), this register is loaded from memory (from address given by current
LAR[31:0] + 0x08).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 SAR[31:0]: Source address

These bits represent the base address of the peripheral data register from/to which the data is read.
They must be aligned with the SSIZE (SAR[1:0] = 00 when SSIZE = 10), but may be unaligned with
the SINCOS.
When source is TCM/AHB, if address is not aligned with SINCOS, the access must be programmed
as single (SBURST = 000).
During the channel activity, this register is updated, reflecting the current address from which the
data is read next.
When the block repeat mode is active, when a block transfer is completed, the source address is
updated by adding/subtracting the SAU value to the current value (already updated after the last
transfer in the block).
When the linked-list mode is active, at the end of a block (repeated or not) transfer, the SAR value is
loaded from memory (from address LSA + m).
Note: These bits are write-protected and can be written only when bit EN = 0.

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14.5.9 MDMA channel x destination address register (MDMA_CxDAR)

Address offset: 0x5C + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000
In linked-list mode, at the end of a block (single or last block in repeated block transfer
mode), this register is loaded from memory (from address given by current
LAR[31:0] + 0x0C).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DAR[31:0]: Destination address

Base address of the destination address to which the data is written. Must be aligned with the DSIZE
(for example DAR[0] = 0 when DSIZE=01), but may be unaligned with the DINCOS.
When destination is AHB, if address is not aligned with DINCOS, access must be programmed as
single (DBURST = 000).
During the channel activity, this register is updated, reflecting the current address to which the data is
written next.
When the block repeat mode is active, when a block transfer is completed, the Destination address
is updated by adding/subtracting the DAU value to the current value (after the last transfer in the
block).
When the linked-list mode is active, at the end of a block (repeated or not) transfer, the DAR value is
loaded from memory (from address LSA + m).
Note: These bits are write-protected and can be written only when bit EN = 0.

14.5.10 MDMA channel x block repeat address update register

(MDMA_CxBRUR)
Address offset: 0x60 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000
In linked-list mode, at the end of a block (single or last block in repeated block transfer
mode), this register is loaded from memory (from address given by current
LAR[31:0] + 0x10).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0433 MDMA controller (MDMA)

Bits 31:16 DUV[15:0]: Destination address update value

This value is used to update (by addition or subtraction) the current destination address at the end of
a block transfer. It must be an integer multiple of DSIZE, in order to keep DAR aligned to DSIZE
(DAR[1:0] = 00 when DSIZ E =10).
If this value is 0, the next repetition of the block transfer continues to the next address.
When the block repeat mode is not active (BRC = 0), this field is ignored.
Note: These bits are write-protected and can be written only when bit EN = 0.
This field must be programmed to 0 when DINC[1:0] = 00.
Bits 15:0 SUV[15:0]: Source address update value
This value is used to update (by addition or subtraction) the current source address at the end of
a block transfer. It must be an integer multiple of SSIZE, in order to keep SAR aligned to SSIZE
(SAR[1:0] = 00 when SSIZE = 10).
If this value is 0, the next repetition of the block transfer continues from the next address.
When the block repeat mode is not active (BRC=0), this field is ignored.
Note: These bits are write-protected and can be written only when bit EN = 0.
This field must be programmed to 0 when SINC[1:0] = 00.

14.5.11 MDMA channel x link address register (MDMA_CxLAR)

Address offset: 0x64 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000
In linked-list mode, at the end of a block (single or last block in repeated block transfer
mode), this register is loaded from memory (from address given by current
LAR[31:0] + 0x14).
Note: The new value is only taken into account after all registers are updated, for the next
end of block.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw r r r

Bits 31:0 LAR[31:0]: Link address register

At the end of a (repeated) block transfer, the current channel configuration registers
(MDMA_CxTCR, MDMA_CxBNDTR, MDMA_CxSAR, MDMA_CxDAR, MDMA_CxBRUR,
MDMA_CxMAR, MDMA_CxMDR and MDMA_CxLAR itself) are loaded with the data structure found
at this address.
If the value of this register is 0, no register update takes place, the channel is disabled and CTCIF is
set, indicating the end of the transfer for this channel.
The channel configuration (LAR address) must be in the AXI address space.
LAR value must be aligned at a double-word address (LAR[2:0] = 0x0).
Note: These bits are write-protected and can be written only when bit EN = 0.

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14.5.12 MDMA channel x trigger and bus selection register

(MDMA_CxTBR)
Address offset: 0x68 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000
In linked-list mode, at the end of a block (single or last block in repeated block transfer
mode), this register is loaded from memory (from address given by current
LAR[31:0] + 0x18).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DBUS SBUS
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSEL[5:0]
rw rw rw rw rw rw

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 DBUS: Destination bus select
0: The system/AXI bus is used as destination (write operation) on channel x.
1: The AHB bus/TCM is used as destination (write operation) on channel x.
Note: This bit is protected and can be written only if EN is 0.
Bit 16 SBUS: Source bus select
0: The system/AXI bus is used as source (read operation) on channel x.
1: The AHB bus/TCM is used as source (read operation) on channel x.
Note: This bit is protected and can be written only if EN is 0.
Bits 15:6 Reserved, must be kept at reset value.
Bits 5:0 TSEL[5:0]: Trigger selection
This field selects the hardware trigger (RQ) input for channel x. The ACK is sent on the ACK output
having the same index value.
When SWRM bit is set (software request selected), this field is ignored.
Note: These bits are write-protected and can be written only when bit EN = 0.
If multiple channels are triggered by the same event (have the same TSEL value), all of them
are triggered in parallel. Only the channel with the lowest index acknowledges the request.

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RM0433 MDMA controller (MDMA)

14.5.13 MDMA channel x mask address register (MDMA_CxMAR)

Address offset: 0x70 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000
In linked-list mode, at the end of a block (single or last block in repeated block transfer
mode), this register is loaded from memory (from address given by current
LAR[31:0] + 0x20).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MAR[31:0]: Mask address

A write of the MDR value is also done to this address. This is used to clear the RQ signal generated
by the DMA2 by writing to its interrupt clear register.
If the value of this register is 0, this function is disabled.
Note: These bits are write-protected and can be written only when bit EN = 0.

14.5.14 MDMA channel x mask data register (MDMA_CxMDR)

Address offset: 0x74 + 0x40 * x, (x = 0 to 15)
Reset value: 0x0000 0000
In Linked List mode, at the end of a block (single or last block in repeated block transfer
mode), this register is loaded from memory (from address given by current
LAR[31:0] + 0x24).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MDR[31:0]: Mask data

A write of the MDR value is also done to the address defined by the MDMA_MAR register. This is
used to clear the RQ signal generated by the DMA2 by writing to its interrupt clear register.
Note: These bits are write-protected and can be written only when bit EN = 0.

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MDMA controller (MDMA) RM0433

14.5.15 MDMA register map

Table 106. MDMA register map and reset values

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
GIF15
GIF14
GIF13
GIF12

GIF10
GIF11

GIF9
GIF8
GIF7
GIF6
GIF5
GIF4
GIF3
GIF2
GIF1
GIF0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MDMA_GISR0
0x00
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x04 - 0x3C Reserved Reserved

CTCIF
BRTIF
TCIF
BTIF

TEIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x40 + 0x40 * x MDMA_CxISR
(x=0 to 15)
Reset value 0 0 0 0 0

CCTCIF
CBRTIF
CLTCIF
CBTIF

CTEIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x44 + 0x40 * x MDMA_CxIFCR
(x=0 to 15)
Reset value 0 0 0 0 0

TEMD
TELD
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSE
ASE

TED
0x48 + 0x40 * x MDMA_CxESR TEA[6:0]
(x=0 to 15)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0

PL[1:0]
SWRQ

CTCIE
BRTIE
WEX

TCIE
BTIE

TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
Res.
HEX
BEX
MDMA_CxCR

EN
0x4C + 0x40 * x
(x=0 to 15)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
DBURST

SBURST

DINCOS

SINCOS
SWRM

DSIZE
TRGM

SSIZE

DINC
BWM

SINC
PAM[

PKE
[1:0]

[2:0]

[2:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]
1:0]

0x50 + 0x40 * x MDMA_CxTCR TLEN[6:0].

(x=0 to 15)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BRDUM
BRSUM
Res.

0x54 + 0x40 * x MDMA_CxBNDTR BRC[11:0] BNDT[16:0]

(x=0 to 15)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x58 + 0x40 * x MDMA_CxSAR SAR[31:0].

(x=0 to 15) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x5C + 0x40 * x MDMA_CxDAR DAR[31:0].

(x=0 to 15) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x60 + 0x40 * x MDMA_CxBRUR DUV[15:0]. SUV[15:0].

(x=0 to 15) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x64 + 0x40 * x MDMA_CxLAR LAR[31:0].

(x=0 to 15) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DBUS
SBUS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x68 + 0x40 * x MDMA_CxTBR TSEL[5:0]

(x=0 to 15)
Reset value 0 0 0 0 0 0 0 0
0x6C+ 0x40 * x
Reserved Reserved
(x=0 to 15)

0x70 + 0x40 * x MDMA_CxMAR MAR[31:0].

(x=0 to 15) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x74 + 0x40 * x MDMA_CxMDR MDR[31:0].

(x=0 to 15) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 for the register boundary addresses.

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15 Direct memory access controller (DMA)

15.1 DMA introduction

Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory and between memory and memory. Data can be quickly moved by
DMA without any CPU action. This keeps CPU resources free for other operations.
The DMA controller combines a powerful dual AHB master bus architecture with
independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix
architecture.
The two DMA controllers (DMA1, DMA2) have 8 streams each, dedicated to managing
memory access requests from one or more peripherals.
Each DMA stream is driven by one DMAMUX1 output channel (request). Any DMAMUX1
output request can be individually programmed in order to select the DMA request source
signal, from any of the 115 available request input signals.
Refer to the Section 17.3: DMAMUX implementation for more information about the DMA
requests and streams mapping.
Each DMA controller has an arbiter for handling the priority between DMA requests.

15.2 DMA main features

The main DMA features are:
• Dual AHB master bus architecture, one dedicated to memory accesses and one
dedicated to peripheral accesses
• AHB slave programming interface supporting only 32-bit accesses
• 8 streams for each DMA controller, up to 115 channels (requests) per stream
• Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream, that can be
used in FIFO mode or direct mode:
– FIFO mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the
FIFO size
– Direct mode: each DMA request immediately initiates a transfer from/to the
memory. When it is configured in direct mode (FIFO disabled), to transfer data in
memory-to-peripheral mode, the DMA preloads only one data from the memory to
the internal FIFO to ensure an immediate data transfer as soon as a DMA request
is triggered by a peripheral.
• Each stream can be configured to be:
– a regular channel that supports peripheral-to-memory, memory-to-peripheral and
memory-to-memory transfers
– a double buffer channel that also supports double buffering on the memory side
• Priorities between DMA stream requests are software-programmable (four levels
consisting of very high, high, medium, low) or hardware in case of equality (for
example, request 0 has priority over request 1)
• Each stream also supports software trigger for memory-to-memory transfers

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• Each stream request can be selected among up to 115 possible channel requests. This
selection is software-configurable by the DMAMUX1 and allows 107 peripherals to
initiate DMA requests
• The number of data items to be transferred can be managed either by the DMA
controller or by the peripheral:
– DMA flow controller: the number of data items to be transferred is software-
programmable from 1 to 65535
– Peripheral flow controller: the number of data items to be transferred is unknown
and controlled by the source or the destination peripheral that signals the end of
the transfer by hardware
• Independent source and destination transfer width (byte, half-word, word): when the
data widths of the source and destination are not equal, the DMA automatically
packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only
available in FIFO mode
• Incrementing or non-incrementing addressing for source and destination
• Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is
software-configurable, usually equal to half the FIFO size of the peripheral
• Each stream supports circular buffer management
• 5 event flags (DMA half transfer, DMA transfer complete, DMA transfer error, DMA
FIFO error, direct mode error) logically ORed together in a single interrupt request for
each stream

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15.3 DMA functional description

15.3.1 DMA block diagram

The figure below shows the block diagram of a DMA.

Figure 78. DMA block diagram

DMA controller

AHB master
Memory port

STREAM 0

STREAM 1

STREAM 2

STREAM 3

STREAM 4

STREAM 5

STREAM 6

STREAM 7
dma_str0
dma_str1
dma_str2
From dma_str3
FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO
DMAMUX1 dma_str4 Arbitrer
Arbiter
dma_str5
dma_str6
STREAM 0

STREAM 1

STREAM 2

STREAM 3

STREAM 4

STREAM 5

STREAM 6

STREAM 7
dma_str7

AHB master
Peripheral port

dma_hclk

AHB
dma_it[0:7] AHB slave
To NVIC
dma_tcif[0:7] programming
To MDMA interface Programming port

MSv39748V3

15.3.2 DMA internal signals

The table below shows the internal DMA signals.

Table 107. DMA internal input/output signals

Signal name Signal type Description

dma_hclk Digital input DMA AHB clock

dma_it[0:7] Digital outputs DMA stream [0:7] global interrupts
dma_tcif[0:7] Digital outputs MDMA triggers
dma_str[0:7] Digital input DMA stream [0:7] requests

15.3.3 DMA overview

The DMA controller performs direct memory transfer: as an AHB master, the DMA controller
can take the control of the AHB bus matrix to initiate AHB transactions.

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The DMA controller carries out the following transactions:

• peripheral-to-memory
• memory-to-peripheral
• memory-to-memory
The DMA controller provides two AHB master ports: the AHB memory port, intended to be
connected to memories and the AHB peripheral port, intended to be connected to
peripherals. However, to allow memory-to-memory transfers, the AHB peripheral port must
also have access to the memories.
The AHB slave port is used to program the DMA controller (it supports only 32-bit
accesses).

15.3.4 DMA transactions

A DMA transaction consists of a sequence of a given number of data transfers. The number
of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software-
programmable.
Each DMA transfer consists of three operations:
• a loading from the peripheral data register or a location in memory, addressed through
the DMA_SxPAR or DMA_SxM0AR register
• a storage of the data loaded to the peripheral data register or a location in memory
addressed through the DMA_SxPAR or DMA_SxM0AR register
• a post-decrement of the DMA_SxNDTR register, containing the number of transactions
that still have to be performed
After an event, the peripheral sends a request signal to the DMA controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the
DMA controller. The peripheral releases its request as soon as it gets the Acknowledge
signal from the DMA controller. Once the request has been deasserted by the peripheral,
the DMA controller releases the Acknowledge signal. If there are more requests, the
peripheral can initiate the next transaction.

15.3.5 DMA request mapping

The DMA request mapping from peripherals to DMA streams is described in Section 17.3:
DMAMUX implementation.

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15.3.6 Arbiter
An arbiter manages the 8 DMA stream requests based on their priority for each of the two
AHB master ports (memory and peripheral ports) and launches the peripheral/memory
access sequences.
Priorities are managed in two stages:
• Software: each stream priority can be configured in the DMA_SxCR register. There are
four levels:
– Very high priority
– High priority
– Medium priority
– Low priority
• Hardware: If two requests have the same software priority level, the stream with the
lower number takes priority over the stream with the higher number. For example,
stream 2 takes priority over stream 4.

15.3.7 DMA streams

Each of the eight DMA controller streams provides a unidirectional transfer link between a
source and a destination.
Each stream can be configured to perform:
• Regular type transactions: memory-to-peripherals, peripherals-to-memory or memory-
to-memory transfers
• Double-buffer type transactions: double buffer transfers using two memory pointers for
the memory (while the DMA is reading/writing from/to a buffer, the application can
write/read to/from the other buffer).
The amount of data to be transferred (up to 65535) is programmable and related to the
source width of the peripheral that requests the DMA transfer connected to the peripheral
AHB port. The register that contains the amount of data items to be transferred is
decremented after each transaction.

15.3.8 Source, destination and transfer modes

Both source and destination transfers can address peripherals and memories in the entire
4-Gbyte area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.
The direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers
three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory
transfers.
The table below describes the corresponding source and destination addresses.

Table 108. Source and destination address

Bits DIR[1:0] of the
Direction Source address Destination address
DMA_SxCR register

00 Peripheral-to-memory DMA_SxPAR DMA_SxM0AR

01 Memory-to-peripheral DMA_SxM0AR DMA_SxPAR

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Table 108. Source and destination address (continued)

Bits DIR[1:0] of the
Direction Source address Destination address
DMA_SxCR register

10 Memory-to-memory DMA_SxPAR DMA_SxM0AR

11 Reserved - -

When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register)
is a half-word or a word, respectively, the peripheral or memory address written into the
DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word
address boundary, respectively.

Peripheral-to-memory mode
Figure 79 describes this mode.
When this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a
peripheral request occurs, the stream initiates a transfer from the source to fill the FIFO.
When the threshold level of the FIFO is reached, the contents of the FIFO are drained and
stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is 0), the threshold level
of the FIFO is not used: after each single data transfer from the peripheral to the FIFO, the
corresponding data are immediately drained and stored into the destination.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.

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Figure 79. Peripheral-to-memory mode

DMA controller DMA_SxM0AR

DMA_SxM1AR(1)

AHB memory port Memory bus

Memory
destination

dma_strx FIFO
Arbiter FIFO
level

AHB peripheral
Peripheral bus
port

Peripheral source
DMA_SxPAR

Peripheral DMA request connected to the DMA stream x

via the programmed DMAMUX
MSv41971V1

1. For double-buffer mode.

Memory-to-peripheral mode
Figure 80 describes this mode.
When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream
immediately initiates transfers from the source to entirely fill the FIFO.
Each time a peripheral request occurs, the contents of the FIFO are drained and stored into
the destination. When the level of the FIFO is lower than or equal to the predefined
threshold level, the FIFO is fully reloaded with data from the memory.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is 0), the threshold level
of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to
transfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA
transfers the preloaded value into the configured destination. It then reloads again the
empty internal FIFO with the next data to be transfer. The preloaded data size corresponds
to the value of the PSIZE bitfield in the DMA_SxCR register.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.

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Figure 80. Memory-to-peripheral mode

DMA controller DMA_SxM0AR

DMA_SxM1AR(1)

AHB memory Memory bus

port
Memory source

dma_strx FIFO FIFO

Arbiter level

AHB peripheral
Peripheral bus
port

Peripheral source
DMA_SxPAR

Peripheral DMA request connected to the DMA stream x

via the programmed DMAMUX
MSv41972V1

1. For double-buffer mode.

Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral.
This is the memory-to-memory mode, described in Figure 81.
When the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the
stream immediately starts to fill the FIFO up to the threshold level. When the threshold level
is reached, the FIFO contents are drained and stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the
DMA_SxCR register is cleared by software.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
Note: When memory-to-memory mode is used, the circular and direct modes are not allowed.

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Figure 81. Memory-to-memory mode

DMA controller DMA_SxM0AR

DMA_SxM1AR(1)

AHB memory Memory bus

port

Memory 2
destination
Arbiter FIFO
Stream enable level FIFO

AHB peripheral Peripheral bus

port

Memory 1
DMA_SxPAR source

ai15950

1. For double-buffer mode.

15.3.9 Pointer incrementation

Peripheral and memory pointers can optionally be automatically post-incremented or kept
constant after each transfer depending on the PINC and MINC bits in the DMA_SxCR
register.
Disabling the increment mode is useful when the peripheral source or destination data is
accessed through a single register.
If the increment mode is enabled, the address of the next transfer is the address of the
previous one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on
the data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register.
In order to optimize the packing operation, it is possible to fix the increment offset size for
the peripheral address whatever the size of the data transferred on the AHB peripheral port.
The PINCOS bit in the DMA_SxCR register is used to align the increment offset size with
the data size on the peripheral AHB port, or on a 32-bit address (the address is then
incremented by 4). The PINCOS bit has an impact on the AHB peripheral port only.
If the PINCOS bit is set, the address of the following transfer is the address of the previous
one incremented by 4 (automatically aligned on a 32-bit address), whatever the PSIZE
value. The AHB memory port, however, is not impacted by this operation.

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15.3.10 Circular mode

The circular mode is available to handle circular buffers and continuous data flows (e.g.
ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR
register.
When the circular mode is activated, the number of data items to be transferred is
automatically reloaded with the initial value programmed during the stream configuration
phase, and the DMA requests continue to be served.
Note: In the circular mode, it is mandatory to respect the following rule in case of a burst mode
configured for memory:
DMA_SxNDTR = Multiple of ((Mburst beat) × (Msize)/(Psize)), where:
– (Mburst beat) = 4, 8 or 16 (depending on the MBURST bits in the DMA_SxCR
register)
– ((Msize)/(Psize)) = 1, 2, 4, 1/2 or 1/4 (Msize and Psize represent the MSIZE and
PSIZE bits in the DMA_SxCR register. They are byte dependent)
– DMA_SxNDTR = Number of data items to transfer on the AHB peripheral port
For example: Mburst beat = 8 (INCR8), MSIZE = 00 (byte) and PSIZE = 01 (half-word), in
this case: DMA_SxNDTR must be a multiple of (8 × 1/2 = 4).
If this formula is not respected, the DMA behavior and data integrity are not guaranteed.
NDTR must also be a multiple of the Peripheral burst size multiplied by the peripheral data
size, otherwise this could result in a bad DMA behavior.

15.3.11 Double-buffer mode

This mode is available for all the DMA1 and DMA2 streams.
The double-buffer mode is enabled by setting the DBM bit in the DMA_SxCR register.
A double-buffer stream works as a regular (single buffer) stream with the difference that it
has two memory pointers. When the double-buffer mode is enabled, the circular mode is
automatically enabled (CIRC bit in DMA_SxCR is not relevant) and at each end of
transaction, the memory pointers are swapped.
In this mode, the DMA controller swaps from one memory target to another at each end of
transaction. This allows the software to process one memory area while the second memory
area is being filled/used by the DMA transfer. The double-buffer stream can work in both
directions (the memory can be either the source or the destination) as described in
Table 109: Source and destination address registers in double-buffer mode (DBM = 1).
Note: In double-buffer mode, it is possible to update the base address for the AHB memory port
on-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled, by respecting the
following conditions:
• When the CT bit is 0 in the DMA_SxCR register, the DMA_SxM1AR register can be
written. Attempting to write to this register while CT = 1 sets an error flag (TEIF) and the
stream is automatically disabled.
• When the CT bit is 1 in the DMA_SxCR register, the DMA_SxM0AR register can be
written. Attempting to write to this register while CT = 0, sets an error flag (TEIF) and
the stream is automatically disabled.
To avoid any error condition, it is advised to change the base address as soon as the TCIF
flag is asserted because, at this point, the targeted memory must have changed from

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memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in

accordance with one of the two above conditions.
For all the other modes (except the double-buffer mode), the memory address registers are
write-protected as soon as the stream is enabled.

Table 109. Source and destination address registers in double-buffer mode (DBM = 1)
Bits DIR[1:0] of the
Direction Source address Destination address
DMA_SxCR register

00 Peripheral-to-memory DMA_SxPAR DMA_SxM0AR / DMA_SxM1AR

01 Memory-to-peripheral DMA_SxM0AR / DMA_SxM1AR DMA_SxPAR
10 Not allowed(1)
11 Reserved - -
1. When the double-buffer mode is enabled, the circular mode is automatically enabled. Since the memory-to-memory mode
is not compatible with the circular mode, when the double-buffer mode is enabled, it is not allowed to configure the
memory-to-memory mode.

15.3.12 Programmable data width, packing/unpacking, endianness

The number of data items to be transferred has to be programmed into DMA_SxNDTR
(number of data items to transfer bit, NDT) before enabling the stream (except when the
flow controller is the peripheral, PFCTRL bit in DMA_SxCR is set).
When using the internal FIFO, the data widths of the source and destination data are
programmable through the PSIZE and MSIZE bits in the DMA_SxCR register (can be 8-,
16- or 32-bit).
When PSIZE and MSIZE are not equal:
• The data width of the number of data items to transfer, configured in the DMA_SxNDTR
register is equal to the width of the peripheral bus (configured by the PSIZE bits in the
DMA_SxCR register). For instance, in case of peripheral-to-memory, memory-to-
peripheral or memory-to-memory transfers and if the PSIZE[1:0] bits are configured for
half-word, the number of bytes to be transferred is equal to 2 × NDT.
• The DMA controller only copes with little-endian addressing for both source and
destination. This is described in Table 110: Packing/unpacking and endian behavior (bit
PINC = MINC = 1).
This packing/unpacking procedure may present a risk of data corruption when the operation
is interrupted before the data are completely packed/unpacked. So, to ensure data
coherence, the stream may be configured to generate burst transfers: in this case, each
group of transfers belonging to a burst are indivisible (refer to Section 15.3.13: Single and
burst transfers).
In direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is
not possible. In this case, it is not allowed to have different source and destination transfer
data widths: both are equal and defined by the PSIZE bits in the DMA_SxCR register.
MSIZE bits are not relevant.

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Table 110. Packing/unpacking and endian behavior (bit PINC = MINC = 1)

Number - Peripheral port address / byte lane
AHB AHB
of data Memory Memory port Peripheral
memory peripheral
items to transfer address / byte transfer
port port
transfer - number lane number PINCOS = 1 PINCOS = 0
width width
(NDT)

1 0x0 / B0[7:0] 1 0x0 / B0[7:0] 0x0 / B0[7:0]

2 0x1 / B1[7:0] 2 0x4 / B1[7:0] 0x1 / B1[7:0]
8 8 4 - 3 0x2 / B2[7:0] 3 0x8 / B2[7:0] 0x2 / B2[7:0]
4 0x3 / B3[7:0] 4 0xC / B3[7:0] 0x3 / B3[7:0]

1 0x0 / B0[7:0] 1 0x0 / B1|B0[15:0] 0x0 / B1|B0[15:0]

2 0x1 / B1[7:0] 2 0x4 / B3|B2[15:0] 0x2 / B3|B2[15:0]
8 16 2 - 3 0x2 / B2[7:0]
4 0x3 / B3[7:0]

1 0x0 / B0[7:0] 1 0x0 / 0x0 /

2 0x1 / B1[7:0] B3|B2|B1|B0[31:0] B3|B2|B1|B0[31:0]
8 32 1 - 3 0x2 / B2[7:0]
4 0x3 / B3[7:0]

1 0x0 / B1|B0[15:0] 1 0x0 / B0[7:0] 0x0 / B0[7:0]

2 0x2 / B3|B2[15:0] 2 0x4 / B1[7:0] 0x1 / B1[7:0]
16 8 4 - 3 0x8 / B2[7:0] 0x2 / B2[7:0]
4 0xC / B3[7:0] 0x3 / B3[7:0]

1 0x0 / B1|B0[15:0] 1 0x0 / B1|B0[15:0] 0x0 / B1|B0[15:0]

16 16 2 - 2 0x2 / B1|B0[15:0] 2 0x4 / B3|B2[15:0] 0x2 / B3|B2[15:0]

1 0x0 / B1|B0[15:0] 1 0x0 / 0x0 /

16 32 1 - 2 0x2 / B3|B2[15:0] B3|B2|B1|B0[31:0] B3|B2|B1|B0[31:0]

1 0x0 / B3|B2|B1|B0[31:0] 1 0x0 / B0[7:0] 0x0 / B0[7:0]

2 0x4 / B1[7:0] 0x1 / B1[7:0]
32 8 4 - 3 0x8 / B2[7:0] 0x2 / B2[7:0]
4 0xC / B3[7:0] 0x3 / B3[7:0]

1 0x0 /B3|B2|B1|B0[31:0] 1 0x0 / B1|B0[15:0] 0x0 / B1|B0[15:0]

32 16 2 - 2 0x4 / B3|B2[15:0] 0x2 / B3|B2[15:0]

1 0x0 /B3|B2|B1|B0 [31:0] 1 0x0 / 0x0 /

32 32 1 - B3|B2|B1|B0 [31:0] B3|B2|B1|B0[31:0]

Note: Peripheral port may be the source or the destination (it can also be the memory source in
the case of memory-to-memory transfer).
PSIZE, MSIZE and NDT[15:0] must be configured so as to ensure that the last transfer is
not incomplete. This can occur when the data width of the peripheral port (PSIZE bits) is
lower than the data width of the memory port (MSIZE bits). This constraint is summarized in
the table below.

Table 111. Restriction on NDT versus PSIZE and MSIZE

PSIZE[1:0] of DMA_SxCR MSIZE[1:0] of DMA_SxCR NDT[15:0] of DMA_SxNDTR

00 (8-bit) 01 (16-bit) Must be a multiple of 2.

00 (8-bit) 10 (32-bit) Must be a multiple of 4.
01 (16-bit) 10 (32-bit) Must be a multiple of 2.

15.3.13 Single and burst transfers

The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or
16 beats.

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The size of the burst is configured by software independently for the two AHB ports by using
the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.
The burst size indicates the number of beats in the burst, not the number of bytes
transferred.
To ensure data coherence, each group of transfers that form a burst are indivisible: AHB
transfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master
during the sequence of the burst transfer.
Depending on the single or burst configuration, each DMA request initiates a different
number of transfers on the AHB peripheral port:
• When the AHB peripheral port is configured for single transfers, each DMA request
generates a data transfer of a byte, half-word or word depending on the PSIZE[1:0] bits
in the DMA_SxCR register
• When the AHB peripheral port is configured for burst transfers, each DMA request
generates 4,8 or 16 beats of byte, half word or word transfers depending on the
PBURST[1:0] and PSIZE[1:0] bits in the DMA_SxCR register.
The same as above has to be considered for the AHB memory port considering the
MBURST and MSIZE bits.
In direct mode, the stream can only generate single transfers and the MBURST[1:0] and
PBURST[1:0] bits are forced by hardware.
The address pointers (DMA_SxPAR or DMA_SxM0AR registers) must be chosen so as to
ensure that all transfers within a burst block are aligned on the address boundary equal to
the size of the transfer.
The burst configuration has to be selected in order to respect the AHB protocol, where
bursts must not cross the 1 Kbyte address boundary because the minimum address space
that can be allocated to a single slave is 1 Kbyte. This means that the 1-Kbyte address
boundary must not be crossed by a burst block transfer, otherwise an AHB error is
generated, that is not reported by the DMA registers.

15.3.14 FIFO
FIFO structure
The FIFO is used to temporarily store data coming from the source before transmitting them
to the destination.
Each stream has an independent 4-word FIFO and the threshold level is software-
configurable between 1/4, 1/2, 3/4 or full.
To enable the use of the FIFO threshold level, the direct mode must be disabled by setting
the DMDIS bit in the DMA_SxFCR register.

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The structure of the FIFO differs depending on the source and destination data widths, and
is described in the figure below.

Figure 82. FIFO structure

4 words

Empty 1/4 1/2 3/4 Full

byte lane 3 B15 B 11 B7 B3
Source: byte Destination: word
byte lane 2 B14 B10 B6 B2
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 W3, W2, W1, W0
byte lane 1 B13 B9 B5 B1

byte lane 0 W3 B12 W2 B8 W1 B4 W0 B0

4 words

Empty 1/4 1/2 3/4 Full

byte lane 3 B15 B 11 B7 B3
Source: byte Destination: half-word
byte lane 2 H7 B14 H5 B10 H3 B6 H1 B2
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 H7, H6, H5, H4, H3, H2, H1, H0
byte lane 1 B13 B9 B5 B1

byte lane 0 H6 B12 H4 B8 H2 B4 H0 B0

4 words

Empty 1/4 1/2 3/4 Full

byte lane 3
Source: half-word H7 H5 H3 H1 Destination: word
byte lane 2
H7 H6 H5 H4 H3 H2 H1 H0 W3, W2, W1, W0
byte lane 1
H6 H4 H2 H0
byte lane 0 W3 W2 W1 W0

4-words

Empty 1/4 1/2 3/4 Full

byte lane 3 B15 B 11 B7 B3
Source: half-word Destination: byte
byte lane 2 H7 B14 H5 B10 H3 B6 H1 B2
H7 H6 H5 H4 H3 H2 H1 H0 B15 B14 B13 B12 B11 B10 B9 B8
byte lane 1 B13 B9 B5 B1 B7 B6 B5 B4 B3 B2 B1 B0

byte lane 0 H6 B12 H4 B8 H2 B4 H0 B0

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FIFO threshold and burst configuration

Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR
register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The
content pointed by the FIFO threshold must exactly match an integer number of memory
burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or
DMA_LISR register) is generated when the stream is enabled, then the stream is
automatically disabled. The allowed and forbidden configurations are described in the table
below. The forbidden configurations are highlighted in gray in the table.

Table 112. FIFO threshold configurations

MSIZE FIFO level MBURST = INCR4 MBURST = INCR8 MBURST = INCR16

1/4 1 burst of 4 beats Forbidden

1/2 2 bursts of 4 beats 1 burst of 8 beats Forbidden
Byte
3/4 3 bursts of 4 beats Forbidden
Full 4 bursts of 4 beats 2 bursts of 8 beats 1 burst of 16 beats
1/4 Forbidden
1/2 1 burst of 4 beats Forbidden
Half-word
3/4 Forbidden
Full 2 bursts of 4 beats 1 burst of 8 beats
Forbidden
1/4
1/2 Forbidden
Word Forbidden
3/4
Full 1 burst of 4 beats

In all cases, the burst size multiplied by the data size must not exceed the FIFO size (data
size can be: 1 (byte), 2 (half-word) or 4 (word)).
Incomplete burst transfer at the end of a DMA transfer may happen if one of the following
conditions occurs:
• For the AHB peripheral port configuration: the total number of data items (set in the
DMA_SxNDTR register) is not a multiple of the burst size multiplied by the data size.
• For the AHB memory port configuration: the number of remaining data items in the
FIFO to be transferred to the memory is not a multiple of the burst size multiplied by the
data size.
In such cases, the remaining data to be transferred is managed in single mode by the DMA,
even if a burst transaction is requested during the DMA stream configuration.
Note: When burst transfers are requested on the peripheral AHB port and the FIFO is used
(DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to
avoid permanent underrun or overrun conditions, depending on the DMA stream direction:
If (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with
PSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16.
This rule ensures that enough FIFO space at a time is free to serve the request from the
peripheral.

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FIFO flush
The FIFO can be flushed when the stream is disabled by resetting the EN bit in the
DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or
memory-to-memory transfers. If some data are still present in the FIFO when the stream is
disabled, the DMA controller continues transferring the remaining data to the destination
(even though stream is effectively disabled). When this flush is completed, the transfer
complete status bit (TCIFx) in the DMA_LISR or DMA_HISR register is set.
The remaining data counter DMA_SxNDTR keeps the value in this case to indicate how
many data items are currently available in the destination memory.
Note that during the FIFO flush operation, if the number of remaining data items in the FIFO
to be transferred to memory (in bytes) is less than the memory data width (for example 2
bytes in FIFO while MSIZE is configured to word), data is sent with the data width set in the
MSIZE bit in the DMA_SxCR register. This means that memory is written with an undesired
value. The software may read the DMA_SxNDTR register to determine the memory area
that contains the good data (start address and last address).
If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST
bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB
memory port), single transactions are generated to complete the FIFO flush.

Direct mode
By default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and
the FIFO threshold level is not used. This mode is useful when the system requires an
immediate and single transfer to or from the memory after each DMA request.
When the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-to-
peripheral mode, the DMA preloads one data from the memory to the internal FIFO to
ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.
To avoid saturating the FIFO, it is recommended to configure the corresponding stream with
a high priority.
This mode is restricted to transfers where:
• the source and destination transfer widths are equal and both defined by the
PSIZE[1:0] bits in DMA_SxCR (MSIZE[1:0] bits are not relevant)
• burst transfers are not possible (PBURST[1:0] and MBURST[1:0] bits in DMA_SxCR
are don’t care)
Direct mode must not be used when implementing memory-to-memory transfers.

15.3.15 DMA transfer completion

Different events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR
or DMA_HISR status register:
• In DMA flow controller mode:
– The DMA_SxNDTR counter has reached zero in the memory-to-peripheral mode.
– The stream is disabled before the end of transfer (by clearing the EN bit in the
DMA_SxCR register) and (when transfers are peripheral-to-memory or memory-

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to-memory) all the remaining data have been flushed from the FIFO into the
memory.
• In Peripheral flow controller mode:
– The last external burst or single request has been generated from the peripheral
and (when the DMA is operating in peripheral-to-memory mode) the remaining
data have been transferred from the FIFO into the memory
– The stream is disabled by software, and (when the DMA is operating in peripheral-
to-memory mode) the remaining data have been transferred from the FIFO into
the memory
Note: The transfer completion is dependent on the remaining data in FIFO to be transferred into
memory only in the case of peripheral-to-memory mode. This condition is not applicable in
memory-to-peripheral mode.
If the stream is configured in non-circular mode, after the end of the transfer (that is when
the number of data to be transferred reaches zero), the DMA is stopped (EN bit in
DMA_SxCR register is cleared by Hardware) and no DMA request is served unless the
software reprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR
register).

15.3.16 DMA transfer suspension

At any time, a DMA transfer can be suspended to be restarted later on or to be definitively
disabled before the end of the DMA transfer.
There are two cases:
• The stream disables the transfer with no later-on restart from the point where it was
stopped. There is no particular action to do, except to clear the EN bit in the
DMA_SxCR register to disable the stream. The stream may take time to be disabled
(ongoing transfer is completed first). The transfer complete interrupt flag (TCIF in the
DMA_LISR or DMA_HISR register) is set in order to indicate the end of transfer. The
value of the EN bit in DMA_SxCR is now 0 to confirm the stream interruption. The
DMA_SxNDTR register contains the number of remaining data items at the moment
when the stream was stopped so that the software can determine how many data items
have been transferred before the stream was interrupted.
• The stream suspends the transfer before the number of remaining data items to be
transferred in the DMA_SxNDTR register reaches 0. The aim is to restart the transfer
later by re-enabling the stream. In order to restart from the point where the transfer was
stopped, the software has to read the DMA_SxNDTR register after disabling the stream
by writing the EN bit in DMA_SxCR register (and then checking that it is at 0) to know
the number of data items already collected. Then:
– The peripheral and/or memory addresses have to be updated in order to adjust
the address pointers
– The SxNDTR register has to be updated with the remaining number of data items
to be transferred (the value read when the stream was disabled)
– The stream may then be re-enabled to restart the transfer from the point it was
stopped
Note: A transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to indicate the
end of transfer due to the stream interruption.

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15.3.17 Flow controller

The entity that controls the number of data to be transferred is known as the flow controller.
This flow controller is configured independently for each stream using the PFCTRL bit in the
DMA_SxCR register.
The flow controller can be:
• The DMA controller: in this case, the number of data items to be transferred is
programmed by software into the DMA_SxNDTR register before the DMA stream is
enabled.
• The peripheral source or destination: this is the case when the number of data items to
be transferred is unknown. The peripheral indicates by hardware to the DMA controller
when the last data are being transferred. This feature is only supported for peripherals
that are able to signal the end of the transfer.
When the peripheral flow controller is used for a given stream, the value written into the
DMA_SxNDTR has no effect on the DMA transfer. Actually, whatever the value written, it is
forced by hardware to 0xFFFF as soon as the stream is enabled, to respect the following
schemes:
• Anticipated stream interruption: EN bit in DMA_SxCR register is reset to 0 by the
software to stop the stream before the last data hardware signal (single or burst) is sent
by the peripheral. In such a case, the stream is switched off and the FIFO flush is
triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the
corresponding stream is set in the status register to indicate the DMA completion. To
know the number of data items transferred during the DMA transfer, read the
DMA_SxNDTR register and apply the following formula:
– Number_of_data_transferred = 0xFFFF – DMA_SxNDTR
• Normal stream interruption due to the reception of a last data hardware signal: the
stream is automatically interrupted when the peripheral requests the last transfer
(single or burst) and when this transfer is complete. the TCIFx flag of the corresponding
stream is set in the status register to indicate the DMA transfer completion. To know the
number of data items transferred, read the DMA_SxNDTR register and apply the same
formula as above.
• The DMA_SxNDTR register reaches 0: the TCIFx flag of the corresponding stream is
set in the status register to indicate the forced DMA transfer completion. The stream is
automatically switched off even though the last data hardware signal (single or burst)
has not been yet asserted. The already transferred data is not lost. This means that a
maximum of 65535 data items can be managed by the DMA in a single transaction,
even in peripheral flow control mode.
Note: When configured in memory-to-memory mode, the DMA is always the flow controller and
the PFCTRL bit is forced to 0 by hardware.
The circular mode is forbidden in the peripheral flow controller mode.

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15.3.18 Summary of the possible DMA configurations

The table below summarizes the different possible DMA configurations. The forbidden
configurations are highlighted in gray in the table.

Table 113. Possible DMA configurations

DMA transfer Flow Circular Transfer Direct Double-
Source Destination
mode controller mode type mode buffer mode

single Possible
DMA Possible Possible
Peripheral-to- AHB AHB burst Forbidden
memory peripheral port memory port single Possible
Peripheral Forbidden Forbidden
burst Forbidden
single Possible
DMA Possible Possible
Memory-to- AHB AHB burst Forbidden
peripheral memory port peripheral port single Possible
Peripheral Forbidden Forbidden
burst Forbidden

Memory-to- AHB AHB single

DMA only Forbidden Forbidden Forbidden
memory peripheral port memory port burst

15.3.19 Stream configuration procedure

The following sequence must be followed to configure a DMA stream x (where x is the
stream number):
1. If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register,
then read this bit in order to confirm that there is no ongoing stream operation. Writing
this bit to 0 is not immediately effective since it is actually written to 0 once all the
current transfers are finished. When the EN bit is read as 0, this means that the stream
is ready to be configured. It is therefore necessary to wait for the EN bit to be cleared
before starting any stream configuration. All the stream dedicated bits set in the status
register (DMA_LISR and DMA_HISR) from the previous data block DMA transfer must
be cleared before the stream can be re-enabled.
2. Set the peripheral port register address in the DMA_SxPAR register. The data is moved
from/ to this address to/ from the peripheral port after the peripheral event.
3. Set the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R
register in the case of a double-buffer mode). The data is written to or read from this
memory after the peripheral event.
4. Configure the total number of data items to be transferred in the DMA_SxNDTR
register. After each peripheral event or each beat of the burst, this value is
decremented.
5. Use DMAMUX1 to route a DMA request line to the DMA channel.
6. If the peripheral is intended to be the flow controller and if it supports this feature, set
the PFCTRL bit in the DMA_SxCR register.
7. Configure the stream priority using the PL[1:0] bits in the DMA_SxCR register.
8. Configure the FIFO usage (enable or disable, threshold in transmission and reception)

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9. Configure the data transfer direction, peripheral and memory incremented/fixed mode,
single or burst transactions, peripheral and memory data widths, circular mode,
double-buffer mode and interrupts after half and/or full transfer, and/or errors in the
DMA_SxCR register.
10. Activate the stream by setting the EN bit in the DMA_SxCR register.
As soon as the stream is enabled, it can serve any DMA request from the peripheral
connected to the stream.
Once half the data have been transferred on the AHB destination port, the half-transfer flag
(HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is
set. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is
generated if the transfer complete interrupt enable bit (TCIE) is set.

Warning: To switch off a peripheral connected to a DMA stream

request, it is mandatory to, first, switch off the DMA stream to
which the peripheral is connected, then to wait for EN bit = 0.
Only then can the peripheral be safely disabled.

15.3.20 Error management

The DMA controller can detect the following errors:
• Transfer error: the transfer error interrupt flag (TEIFx) is set when:
– a bus error occurs during a DMA read or a write access
– a write access is requested by software on a memory address register in
double-buffer mode whereas the stream is enabled and the current target memory
is the one impacted by the write into the memory address register (refer to
Section 15.3.11: Double-buffer mode)
• FIFO error: the FIFO error interrupt flag (FEIFx) is set if:
– a FIFO underrun condition is detected
– a FIFO overrun condition is detected (no detection in memory-to-memory mode
because requests and transfers are internally managed by the DMA)
– the stream is enabled while the FIFO threshold level is not compatible with the
size of the memory burst (refer to Table 112: FIFO threshold configurations)
• Direct mode error: the direct mode error interrupt flag (DMEIFx) can only be set in the
peripheral-to-memory mode while operating in direct mode and when the MINC bit in
the DMA_SxCR register is cleared. This flag is set when a DMA request occurs while
the previous data have not yet been fully transferred into the memory (because the
memory bus was not granted). In this case, the flag indicates that two data items were
be transferred successively to the same destination address, which could be an issue if
the destination is not able to manage this situation
In direct mode, the FIFO error flag can also be set under the following conditions:
• In the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory
bus is not granted for several peripheral requests.
• In the memory-to-peripheral mode, an underrun condition may occur if the memory bus
has not been granted before a peripheral request occurs.

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If the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO
threshold level, the faulty stream is automatically disabled through a hardware clear of its
EN bit in the corresponding stream configuration register (DMA_SxCR).
If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty
stream is not automatically disabled and it is up to the software to disable or not the stream
by resetting the EN bit in the DMA_SxCR register. This is because there is no data loss
when this kind of errors occur.
When the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR
register is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE,
FEIE, DMIE) in the DMA_SxCR or DMA_SxFCR register is set.
Note: When a FIFO overrun or underrun condition occurs, the data is not lost because the
peripheral request is not acknowledged by the stream until the overrun or underrun
condition is cleared. If this acknowledge takes too much time, the peripheral itself may
detect an overrun or underrun condition of its internal buffer and data might be lost.

15.4 DMA interrupts

For each DMA stream, an interrupt can be produced on the following events:
• Half-transfer reached
• Transfer complete
• Transfer error
• FIFO error (overrun, underrun or FIFO level error)
• Direct mode error
Separate interrupt enable control bits are available for flexibility as shown in the table below.

Table 114. DMA interrupt requests

Interrupt event Event flag Enable control bit

Half-transfer HTIF HTIE

Transfer complete TCIF TCIE
Transfer error TEIF TEIE
FIFO overrun/underrun FEIF FEIE
Direct mode error DMEIF DMEIE

Note: Before setting an enable control bit EN = 1, the corresponding event flag must be cleared,
otherwise an interrupt is immediately generated.

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15.5 DMA registers

The DMA registers have to be accessed by words (32 bits).

15.5.1 DMA low interrupt status register (DMA_LISR)

Address offset: 0x000
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMEIF DMEIF
Res. Res. Res. Res. TCIF3 HTIF3 TEIF3 Res. FEIF3 TCIF2 HTIF2 TEIF2 Res. FEIF2
3 2
r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMEIF DMEIF
Res. Res. Res. Res. TCIF1 HTIF1 TEIF1 Res. FEIF1 TCIF0 HTIF0 TEIF0 Res. FEIF0
1 0
r r r r r r r r r r

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 TCIF[3:0]: Stream x transfer complete interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_LIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x.
Bits 26, 20, 10, 4 HTIF[3:0]: Stream x half transfer interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_LIFCR register.
0: No half transfer event on stream x
1: An half transfer event occurred on stream x.
Bits 25, 19, 9, 3 TEIF[3:0]: Stream x transfer error interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_LIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x.
Bits 24, 18, 8, 2 DMEIF[3:0]: Stream x direct mode error interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_LIFCR register.
0: No direct mode error on stream x
1: A direct mode error occurred on stream x.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIF[3:0]: Stream x FIFO error interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_LIFCR register.
0: No FIFO error event on stream x
1: A FIFO error event occurred on stream x.

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15.5.2 DMA high interrupt status register (DMA_HISR)

Address offset: 0x004
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMEIF DMEIF
Res. Res. Res. Res. TCIF7 HTIF7 TEIF7 Res. FEIF7 TCIF6 HTIF6 TEIF6 Res. FEIF6
7 6
r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMEIF DMEIF
Res. Res. Res. Res. TCIF5 HTIF5 TEIF5 Res. FEIF5 TCIF4 HTIF4 TEIF4 Res. FEIF4
5 4
r r r r r r r r r r

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 TCIF[7:4]: Stream x transfer complete interrupt flag (x = 7 to 4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_HIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x.
Bits 26, 20, 10, 4 HTIF[7:4]: Stream x half transfer interrupt flag (x = 7 to 4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_HIFCR register.
0: No half transfer event on stream x
1: An half transfer event occurred on stream x.
Bits 25, 19, 9, 3 TEIF[7:4]: Stream x transfer error interrupt flag (x = 7 to 4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_HIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x.
Bits 24, 18, 8, 2 DMEIF[7:4]: Stream x direct mode error interrupt flag (x = 7 to 4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_HIFCR register.
0: No direct mode error on stream x
1: A direct mode error occurred on stream x.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIF[7:4]: Stream x FIFO error interrupt flag (x = 7 to 4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_HIFCR register.
0: No FIFO error event on stream x
1: A FIFO error event occurred on stream x.

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15.5.3 DMA low interrupt flag clear register (DMA_LIFCR)

Address offset: 0x008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDMEI CDMEI
Res. Res. Res. Res. CTCIF3 CHTIF3 CTEIF3 Res. CFEIF3 CTCIF2 CHTIF2 CTEIF2 Res. CFEIF2
F3 F2
w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDMEI CDMEI
Res. Res. Res. Res. CTCIF1 CHTIF1 CTEIF1 Res. CFEIF1 CTCIF0 CHTIF0 CTEIF0 Res. CFEIF0
F1 F0
w w w w w w w w w w

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 CTCIF[3:0]: Stream x clear transfer complete interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register.
Bits 26, 20, 10, 4 CHTIF[3:0]: Stream x clear half transfer interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register
Bits 25, 19, 9, 3 CTEIF[3:0]: Stream x clear transfer error interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register.
Bits 24, 18, 8, 2 CDMEIF[3:0]: Stream x clear direct mode error interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIF[3:0]: Stream x clear FIFO error interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register.

15.5.4 DMA high interrupt flag clear register (DMA_HIFCR)

Address offset: 0x00C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDMEI CDMEI
Res. Res. Res. Res. CTCIF7 CHTIF7 CTEIF7 Res. CFEIF7 CTCIF6 CHTIF6 CTEIF6 Res. CFEIF6
F7 F6
w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDMEI CDMEI
Res. Res. Res. Res. CTCIF5 CHTIF5 CTEIF5 Res. CFEIF5 CTCIF4 CHTIF4 CTEIF4 Res. CFEIF4
F5 F4
w w w w w w w w w w

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 CTCIF[7:4]: Stream x clear transfer complete interrupt flag (x = 7 to 4)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register.
Bits 26, 20, 10, 4 CHTIF[7:4]: Stream x clear half transfer interrupt flag (x = 7 to 4)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register.

658/3353 RM0433 Rev 8

RM0433 Direct memory access controller (DMA)

Bits 25, 19, 9, 3 CTEIF[7:4]: Stream x clear transfer error interrupt flag (x = 7 to 4)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register.
Bits 24, 18, 8, 2 CDMEIF[7:4]: Stream x clear direct mode error interrupt flag (x = 7 to 4)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIF[7:4]: Stream x clear FIFO error interrupt flag (x = 7 to 4)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register.

15.5.5 DMA stream x configuration register (DMA_SxCR)

This register is used to configure the concerned stream.
Address offset: 0x010 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRBUF
Res. Res. Res. Res. Res. Res. Res. MBURST[1:0] PBURST[1:0] CT DBM PL[1:0]
F
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINC PF
MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR[1:0] TCIE HTIE TEIE DMEIE EN
OS CTRL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:23 MBURST[1:0]: Memory burst transfer configuration
These bits are set and cleared by software.
00: Single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN = 0.
In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1.
Bits 22:21 PBURST[1:0]: Peripheral burst transfer configuration
These bits are set and cleared by software.
00: Single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN = 0.
In direct mode, these bits are forced to 0x0 by hardware.
Bit 20 TRBUFF: Enable the DMA to handle bufferable transfers
0: Bufferable transfers not enabled
1: Bufferable transfers enabled
Note: This bit must be set to 1 if the DMA stream manages UART/USART/LPUART transfers.

RM0433 Rev 8 659/3353

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Direct memory access controller (DMA) RM0433

Bit 19 CT: Current target (only in double-buffer mode)

This bit is set and cleared by hardware. It can also be written by software.
0: Current target memory is memory 0 (addressed by the DMA_SxM0AR pointer).
1: Current target memory is memory 1 (addressed by the DMA_SxM1AR pointer).
This bit can be written only if EN = 0 to indicate the target memory area of the first transfer.
Once the stream is enabled, this bit operates as a status flag indicating which memory area
is the current target.
Bit 18 DBM: Double-buffer mode
This bit is set and cleared by software.
0: No buffer switching at the end of transfer
1: Memory target switched at the end of the DMA transfer
This bit is protected and can be written only if EN = 0.
Bits 17:16 PL[1:0]: priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
These bits are protected and can be written only if EN = 0.
Bit 15 PINCOS: Peripheral increment offset size
This bit is set and cleared by software
0: The offset size for the peripheral address calculation is linked to the PSIZE.
1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment).
This bit has no meaning if bit PINC = 0.
This bit is protected and can be written only if EN = 0.
This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is
selected or if PBURST are different from 00.
Bits 14:13 MSIZE[1:0]: Memory data size
These bits are set and cleared by software.
00: Byte (8-bit)
01: Half-word (16-bit)
10: Word (32-bit)
11: Reserved
These bits are protected and can be written only if EN = 0.
In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as
EN = 1.
Bits 12:11 PSIZE[1:0]: Peripheral data size
These bits are set and cleared by software.
00: Byte (8-bit)
01: Half-word (16-bit)
10: Word (32-bit)
11: Reserved
These bits are protected and can be written only if EN = 0.
Bit 10 MINC: Memory increment mode
This bit is set and cleared by software.
0: Memory address pointer fixed
1: Memory address pointer incremented after each data transfer (increment is done
according to MSIZE)
This bit is protected and can be written only if EN = 0.

660/3353 RM0433 Rev 8

RM0433 Direct memory access controller (DMA)

Bit 9 PINC: Peripheral increment mode

This bit is set and cleared by software.
0: Peripheral address pointer fixed
1: Peripheral address pointer incremented after each data transfer (increment done
according to PSIZE)
This bit is protected and can be written only if EN = 0.
Bit 8 CIRC: Circular mode
This bit is set and cleared by software and can be cleared by hardware.
0: Circular mode disabled
1: Circular mode enabled
When the peripheral is the flow controller (bit PFCTRL = 1), and the stream is enabled
(EN = 1), then this bit is automatically forced by hardware to 0.
It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is
enabled (EN = 1).
Bits 7:6 DIR[1:0]: Data transfer direction
These bits are set and cleared by software.
00: Peripheral-to-memory
01: Memory-to-peripheral
10: Memory-to-memory
11: Reserved
These bits are protected and can be written only if EN = 0.
Bit 5 PFCTRL: Peripheral flow controller
This bit is set and cleared by software.
0: DMA is the flow controller.
1: The peripheral is the flow controller.
This bit is protected and can be written only if EN = 0.
When the memory-to-memory mode is selected (bits DIR[1:0] = 10), then this bit is
automatically forced to 0 by hardware.
Bit 4 TCIE: Transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
Bit 3 HTIE: Half transfer interrupt enable
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
Bit 2 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 1 DMEIE: Direct mode error interrupt enable
This bit is set and cleared by software.
0: DME interrupt disabled
1: DME interrupt enabled

RM0433 Rev 8 661/3353

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Direct memory access controller (DMA) RM0433

Bit 0 EN: Stream enable/flag stream ready when read low

This bit is set and cleared by software.
0: Stream disabled
1: Stream enabled
This bit is cleared by hardware:
– on a DMA end of transfer (stream ready to be configured)
– if a transfer error occurs on the AHB master buses
– when the FIFO threshold on memory AHB port is not compatible with the burst size
When this bit is read as 0, the software is allowed to program the configuration and FIFO bits
registers. It is forbidden to write these registers when the EN bit is read as 1.
Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to
the stream in DMA_LISR or DMA_HISR register must be cleared.

15.5.6 DMA stream x number of data register (DMA_SxNDTR)

Address offset: 0x014 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 NDT[15:0]: Number of data items to transfer (0 up to 65535)
This bitfield can be written only when the stream is disabled. When the stream is enabled,
this bitfield is read-only, indicating the remaining data items to be transmitted. This bitfield
decrements after each DMA transfer.
Once the transfer is completed, this bitfield can either stay at zero (when the stream is in
normal mode), or be reloaded automatically with the previously programmed value
in the following cases:
– when the stream is configured in circular mode
– when the stream is enabled again by setting EN bit to 1
If the value of this bitfield is zero, no transaction can be served even if the stream is enabled.

15.5.7 DMA stream x peripheral address register (DMA_SxPAR)

Address offset: 0x018 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

662/3353 RM0433 Rev 8

RM0433 Direct memory access controller (DMA)

Bits 31:0 PAR[31:0]: Peripheral address

Base address of the peripheral data register from/to which the data is read/written.
These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR.

15.5.8 DMA stream x memory 0 address register

(DMA_SxM0AR)
Address offset: 0x01C + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 M0A[31:0]: Memory 0 address

Base address of memory area 0 from/to which the data is read/written.
These bits are write-protected. They can be written only if:
– the stream is disabled (EN = 0 in DMA_SxCR) or
– the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR
(in double-buffer mode).

15.5.9 DMA stream x memory 1 address register

(DMA_SxM1AR)
Address offset: 0x020 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 M1A[31:0]: Memory 1 address (used in case of double-buffer mode)

Base address of memory area 1 from/to which the data is read/written.
This bitfield is used only for the double-buffer mode.
These bits are write-protected. They can be written only if:
– the stream is disabled (EN = 0 in DMA_SxCR) or
– the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR .

RM0433 Rev 8 663/3353

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Direct memory access controller (DMA) RM0433

15.5.10 DMA stream x FIFO control register (DMA_SxFCR)

Address offset: 0x024 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0021

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. FEIE Res. FS[2:0] DMDIS FTH[1:0]
rw r r r rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 FEIE: FIFO error interrupt enable
This bit is set and cleared by software.
0: FE interrupt disabled
1: FE interrupt enabled
Bit 6 Reserved, must be kept at reset value.
Bits 5:3 FS[2:0]: FIFO status
These bits are read-only.
000: 0 < fifo_level < 1/4
001: 1/4 ≤ fifo_level < 1/2
010: 1/2 ≤ fifo_level < 3/4
011: 3/4 ≤ fifo_level < full
100: FIFO is empty.
101: FIFO is full.
Others: Reserved (no meaning)
These bits are not relevant in the direct mode (DMDIS = 0).
Bit 2 DMDIS: Direct mode disable
This bit is set and cleared by software. It can be set by hardware.
0: Direct mode enabled
1: Direct mode disabled
This bit is protected and can be written only if EN = 0.
This bit is set by hardware if the memory-to-memory mode is selected (DIR = 10
in DMA_SxCR), and EN = 1 in DMA_SxCR because the direct mode is not allowed
in the memory-to-memory configuration.
Bits 1:0 FTH[1:0]: FIFO threshold selection
These bits are set and cleared by software.
00: 1/4 full FIFO
01: 1/2 full FIFO
10: 3/4 full FIFO
11: Full FIFO
These bits are not used in the direct mode when the DMIS = 0.
These bits are protected and can be written only if EN = 0.

664/3353 RM0433 Rev 8

 0x030
0x028
0x024
0x020
0x018
0x014
0x010
0x008
0x004
0x000

0x02C
0x01C
0x00C
Offset
RM0433

15.5.11

name

DMA_LISR
Register

DMA_HISR

Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

DMA_S1CR
DMA_S0CR
DMA_LIFCR

DMA_HIFCR

DMA_S1PAR
DMA_S0PAR

DMA_S0FCR

DMA_S1NDTR
DMA_S0NDTR

DMA_S0M1AR
DMA_S0M0AR

0
0
0
0
Res Res Res Res Res Res Res Res Res. 31

0
0
0
0
Res Res Res Res Res Res Res Res Res. 30

0
0
0
0
Res Res Res Res Res Res Res Res Res. 29

0
0
0
0
Res Res Res Res Res Res Res Res Res. 28

0
0
0
0
0
0
0
0

Res Res Res Res Res CTCIF7 CTCIF3 TCIF7 TCIF3 27

0
0
0
0
0
0
0
0

Res Res Res Res Res CHTIF7 CHTIF3 HTIF7 HTIF3

DMA register map

26

0
0
0
0
0
0
0
0

Res Res Res Res Res CTEIF7 TEIF3 TEIF7 TEIF3 25

0
0
0
0
0
0
0
0
0
0

Res Res Res MBURST CDMEIF7 CDMEIF3 DMEIF7 DMEIF3 24

MBURST[1:0]
[1:0]

0
0
0
0
0
0
Res Res Res Res Res Res Res. 23

0
0
0
0
0
0
0
0
0
0

Res Res Res PBURST CFEIF7 CFEIF3 FEIF7 FEIF3 22

PBURST[1:0]
[1:0]

0
0
0
0
0
0
0
0
0
0

Res Res Res CTCIF6 CTCIF2 TCIF6 TCIF2 21

0
0
0
0
0
0
0
0
0
0

Res TRBUFF Res Res TRBUFF CHTIF6 CHTIF2 HTIF6 HTIF2 20

0
0
0
0
0
0
0
0
0
0

Res CT Res Res CT CTEIF6 CTEIF2 TEIF6 TEIF2 19

0
0
0
0
0
0
0
0
0
0

Res DBM Res Res DBM CDMEIF6 CDMEIF2 DMEIF6 DMEIF2 18

0
0
0
0
0
0

RM0433 Rev 8
Res Res Res Res Res Res Res. 17
PL[1:0] PL[1:0]

0
0
0
0
0
0
0
0
0
0

Res Res Res CFEIF6 CFEIF2 FEIF6 FEIF2 16

0
0

0
0
0
0
0
0
PINCOS Res PINCOS Res Res Res Res. 15

PA[31:0]
PA[31:0]

M1A[31:0]
M0A[31:0]

0
0
0
0
0

0
0
0
Res Res Res Res Res. 14
MSIZE[1:0] MSIZE[1:0]

0
0
0
0
0

0
0
0
Res Res Res Res Res. 13

0
0
0
0
0

0
0
0

Res Res Res Res Res. 12

PSIZE[1:0] PSIZE[1:0]

0
0
0
0
0

0
0
0
0
0
0
0

Res CTCIF5 CTCIF1 TCIF5 TCIF1 11

Table 115. DMA register map and reset values

0
0
0
0
0

0
0
0
0
0
0
0

MINC Res MINC CHTIF5 CHTIF1 HTIF5 HTIF1 10

0
0
0
0
0

0
0
0
0
0
0
0

PINC Res PINC CTEIF5 CTEIF1 TEIF5 TEIF1 9

0
0
0
0
0

0
0
0
0
0
0
0

CIRC Res CIRC CDMEIF5 CDMEIF1 DMEIF5 DMEIF1 8

0
0
0
0
0

0
0
0

0
FEIE Res Res Res Res. 7
DIR[1:0] DIR[1:0]

NDT[15:0]
NDT[15:0]

0
0
0
0
0

0
0
0
0
0
0
0

Res CFEIF5 CFEIF1 FEIF5 FEIF1 6

0
0
0
0

0
0
0
0
0
0
0
0

1
PFCTRL PFCTRL CTCIF4 CTCIF0 TCIF4 TCIF0 5

0
0
0
0

0
0
0
0
0
0
0
0

0
TCIE TCIE CHTIF4 CHTIF0 HTIF4 HTIF0 4

FS[2:0]

0
0
0
0

0
0
0
0
0
0
0
0

0
HTIE HTIE CTEIF4 CTEIF0 TEIF4 TEIF0 3

0
0
0
0

0
0
0
0
0
0
0
0

0
TEIE DMDIS TEIE CDMEIF4 CDMEIF0 DMEIF4 DMEIF0 2

0
0
0
0

0
0
0
0

0
DMEIE DMEIE Res Res Res Res. 1
FTH[1:0]

0
0
0
0

0
0
0
0
0
0
0
0

1
EN EN CFEIF4 CFEIF0 FEIF4 FEIF0
Direct memory access controller (DMA)

665/3353
0

668
Direct memory access controller (DMA) RM0433

Table 115. DMA register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

DMA_S1M0AR M0A[31:0]
0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S1M1AR M1A[31:0]
0x038
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FTH[1:0]
DMDIS
FEIE
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res

Res
DMA_S1FCR FS[2:0]
0x03C

Reset value 0 1 0 0 0 0 1
MBURST[1:0]

PBURST[1:0]

MSIZE[1:0]

PSIZE[1:0]
TRBUFF

PFCTRL
PINCOS

DIR[1:0]
PL[1:0]

DMEIE
MINC

CIRC
PINC

TCIE
HTIE
TEIE
DBM
Res
Res
Res
Res
Res
Res
Res

EN
CT
DMA_S2CR
0x040

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
DMA_S2NDTR NDT[15:0]
0x044
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S2PAR PA[31:0]
0x048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S2M0AR M0A[31:0]
0x04C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S2M1AR M1A[31:0]
0x050
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FTH[1:0]
DMDIS
FEIE
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res

Res
DMA_S2FCR FS[2:0]
0x054

Reset value 0 1 0 0 0 0 1
MSIZE[1:0]

PSIZE[1:0]
MBURST

PBURST

TRBUFF

PFCTRL
PINCOS

DIR[1:0]
PL[1:0]

DMEIE
MINC

CIRC
PINC

HTIE
TCIE

TEIE
DBM
[1:0]

[1:0]
Res
Res
Res
Res
Res
Res
Res

EN
CT

DMA_S3CR
0x058

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res

DMA_S3NDTR NDT[15:0]
0x05C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S3PAR PA[31:0]
0x060
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S3M0AR M0A[31:0]
0x064
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S3M1AR M1A[31:0]
0x068
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

666/3353 RM0433 Rev 8

RM0433 Direct memory access controller (DMA)

Table 115. DMA register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

FTH[1:0]
DMDIS
FEIE
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res

Res
DMA_S3FCR FS[2:0]
0x06C

Reset value 0 1 0 0 0 0 1

MSIZE[1:0]

PSIZE[1:0]
MBURST

PBURST

TRBUFF

PFCTRL
PINCOS

DIR[1:0]
PL[1:0]

DMEIE
MINC

CIRC
PINC

HTIE
TCIE

TEIE
DBM
Res.
Res.
Res.
Res.
Res.
Res.
Res.

[1:0]

[1:0]

EN
CT
DMA_S4CR
0x070

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
DMA_S4NDTR NDT[15:0]
0x074
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S4PAR PA[31:0]
0x078
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S4M0AR M0A[31:0]
0x07C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S4M1AR M1A[31:0]
0x080
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FTH[1:0]
DMDIS
FEIE
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res

Res
DMA_S4FCR FS[2:0]
0x084

Reset value 0 1 0 0 0 0 1
MSIZE[1:0]

PSIZE[1:0]
MBURST

PBURST

TRBUFF

PFCTRL
PINCOS

DIR[1:0]
PL[1:0]

DMEIE
MINC

CIRC
PINC

TCIE
HTIE
DBM

TEIE
[1:0]

[1:0]
Res
Res
Res
Res
Res
Res
Res

EN
CT

DMA_S5CR
0x088

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res

DMA_S5NDTR NDT[15:0]
0x08C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S5PAR PA[31:0]
0x090
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S5M0AR M0A[31:0]
0x094
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S5M1AR M1A[31:0]
0x098
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTH[1:0]
DMDIS
FEIE
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res

Res

DMA_S5FCR FS[2:0]
0x09C

Reset value 0 1 0 0 0 0 1
MSIZE[1:0]

PSIZE[1:0]
MBURST

PBURST

TRBUFF

PFCTRL
PINCOS

DIR[1:0]
PL[1:0]

DMEIE
MINC

CIRC
PINC

HTIE
TCIE
DBM

TEIE
[1:0]

[1:0]
Res
Res
Res
Res
Res
Res
Res

EN
CT

DMA_S6CR
0x0A0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 115. DMA register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
DMA_S6NDTR NDT[15:0]
0x0A4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S6PAR PA[31:0]
0x0A8
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S6M0AR M0A[31:0]
0x0AC
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S6M1AR M1A[31:0]
0x0B0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FTH[1:0]
DMDIS
FEIE
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res

Res
DMA_S6FCR FS[2:0]
0x0B4

Reset value 0 1 0 0 0 0 1

MSIZE[1:0]

PSIZE[1:0]
MBURST

PBURST

TRBUFF

PFCTRL
PINCOS

DIR[1:0]
PL[1:0]

DMEIE
MINC

CIRC
PINC

HTIE
TCIE
DBM

TEIE
[1:0]

[1:0]
Res
Res
Res
Res
Res
Res
Res

EN
CT

DMA_S7CR
0x0B8

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res

DMA_S7NDTR NDT[15:0]
0x0BC
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S7PAR PA[31:0]
0x0C0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S7M0AR M0A[31:0]
0x0C4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_S7M1AR M1A[31:0]
0x0C8
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTH[1:0]
DMDIS
FEIE
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res

Res

DMA_S7FCR FS[2:0]
0x0CC

Reset value 0 1 0 0 0 0 1

Refer to Section 2.3 for the register boundary addresses.

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RM0433 Basic direct memory access controller (BDMA)

16 Basic direct memory access controller (BDMA)

16.1 Introduction
The basic direct memory access (BDMA) controller is a bus master and system peripheral.
The BDMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories, upon the control of an off-loaded CPU.
The BDMA controller features a single AHB master architecture.
There is one instance of BDMA with 8 channels.
Each channel is dedicated to managing memory access requests from one or more
peripherals. The BDMA includes an arbiter for handling the priority between DMA requests.

16.2 BDMA main features

• Single AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access to D3 domain SRAM and AHB/APB peripherals (BDMA)
• All BDMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (4 levels per channel:
very high, high, medium, low) and by hardware in case of equality (such as
request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer
management
– Programmable number of data to be transferred: 0 to 216 - 1
• Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.

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16.3 BDMA implementation

16.3.1 BDMA
BDMA is implemented with the hardware configuration parameters shown in the table
below.

Table 116. BDMA implementation

Feature BDMA

Number of channels (double-buffer) 8

16.3.2 BDMA request mapping

The BDMA controller is connected to DMA requests from the AHB/APB peripherals through
the DMAMUX peripheral.
For the mapping of the different requests, refer to the Section 17.3: DMAMUX
implementation.

16.4 BDMA functional description

16.4.1 BDMA block diagram

The BDMA block diagram is shown in the figure below.

Figure 83. BDMA block diagram

BDMA bdma_hclk

Ch 0
32-bit AHB bus

Ch 1
AHB master port
...

Ch 7

DMA_CMAR[0..7]
bdma_tcif[0..7]
DMA_CPAR[0..7]

bdma_it[0..7] Arbiter DMA_CCR[0..7]

DMA_CNDTR[0..7]
32-bit AHB bus

bdma_req[0..7]
AHB slave
configuration port

MSv39795V1

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The BDMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
BDMA target the same destination (memory or peripheral).
The BDMA controller is connected to DMA requests from the AHB/APB peripherals through
the DMAMUX peripheral.
According to its configuration through the AHB slave interface, the BDMA controller
arbitrates between the DMA channels and their associated received requests. The BDMA
controller also schedules the DMA data transfers over the single AHB port master.
The BDMA controller generates an interrupt per channel to the interrupt controller.

16.4.2 BDMA pins and internal signals

Table 117. BDMA internal input/output signals

Signal name Signal type Description

bdma_req[x] Input BDMA channel x request

bdma_ack[x] Output BDMA channel x acknowledge
bdma_it[x] Output BDMA channel x interrupt

16.4.3 BDMA transfers

The software configures the BDMA controller at channel level, in order to perform a block
transfer, composed of a sequence of AHB bus transfers.
A BDMA block transfer may be requested from a peripheral, or triggered by the software in
case of memory-to-memory transfer.
After an event, the following steps of a single BDMA transfer occur:
1. The peripheral sends a single DMA request signal to the BDMA controller.
2. The BDMA controller serves the request, depending on the priority of the channel
associated to this peripheral request.
3. As soon as the BDMA controller grants the peripheral, an acknowledge is sent to the
peripheral by the BDMA controller.
4. The peripheral releases its request as soon as it gets the acknowledge from the BDMA
controller.
5. Once the request is deasserted by the peripheral, the BDMA controller releases the
acknowledge.
The peripheral may order a further single request and initiate another single BDMA transfer.
The request/acknowledge protocol is used when a peripheral is either the source or the
destination of the transfer. For example, in case of memory-to-peripheral transfer, the
peripheral initiates the transfer by driving its single request signal to the BDMA controller.
The BDMA controller reads then a single data in the memory and writes this data to the
peripheral.

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For a given channel x, a BDMA block transfer consists of a repeated sequence of:
• a single BDMA transfer, encapsulating two AHB transfers of a single data, over the
BDMA AHB bus master:
– a single data read (byte, half-word or word) from the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first single transfer is the base address of the
peripheral or memory, and is programmed in the BDMA_CPARx or
BDMA_CM0/1ARx register.
– a single data write (byte, half-word or word) to the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first transfer is the base address of the peripheral or
memory, and is programmed in the BDMA_CPARx or BDMA_CM0/1ARx register.
• post-decrementing of the programmed BDMA_CNDTRx register
This register contains the remaining number of data items to transfer (number of AHB
‘read followed by write’ transfers).
This sequence is repeated until BDMA_CNDTRx is null.
Note: The AHB master bus source/destination address must be aligned with the programmed size
of the transferred single data to the source/destination.

16.4.4 BDMA arbitration

The BDMA arbiter manages the priority between the different channels.
When an active channel x is granted by the arbiter (hardware requested or software
triggered), a single BDMA transfer is issued (such as a AHB ‘read followed by write’ transfer
of a single data). Then, the arbiter considers again the set of active channels and selects the
one with the highest priority.
The priorities are managed in two stages:
• software: priority of each channel is configured in the BDMA_CCRx register, to one of
the four different levels:
– very high
– high
– medium
– low
• hardware: if two requests have the same software priority level, the channel with the
lowest index gets priority. For example, channel 2 gets priority over channel 4.
When a channel x is programmed for a block transfer in memory-to-memory mode,
re arbitration is considered between each single BDMA transfer of this channel x. Whenever
there is another concurrent active requested channel, the BDMA arbiter automatically
alternates and grants the other highest-priority requested channel, which may be of lower
priority than the memory-to-memory channel.

16.4.5 BDMA channels

Each channel may handle a BDMA transfer between a peripheral register located at a fixed
address, and a memory address. The amount of data items to transfer is programmable.

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The register that contains the amount of data items to transfer is decremented after each
transfer.
A DMA channel is programmed at block transfer level.

Programmable data sizes

The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory
are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the
BDMA_CCRx register.

Pointer incrementation
The peripheral and memory pointers may be automatically incremented after each transfer,
depending on the PINC and MINC bits of the BDMA_CCRx register.
If the incremented mode is enabled (PINC or MINC set to 1), the address of the next
transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data
size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed
in the BDMA_CPARx or BDMA_CM0/1ARx register. During transfers, these registers keep
the initially programmed value. The current transfer addresses (in the current internal
peripheral/memory address register) are not accessible by software.
If the channel x is configured in non-circular mode, no DMA request is served after the last
data transfer (once the number of single data to transfer reaches zero). The DMA channel
must be disabled in order to reload a new number of data items into the BDMA_CNDTRx
register.
Note: If the channel x is disabled, the BDMA registers are not reset. The DMA channel registers
(BDMA_CCRx, BDMA_CPARx and BDMA_CM0ARx) retain the initial values programmed
during the channel configuration phase.
In circular mode, after the last data transfer, the BDMA_CNDTRx register is automatically
reloaded with the initially programmed value. The current internal address registers are
reloaded with the base address values from the BDMA_CPARx and BDMA_CM0/1ARx
registers.

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Channel configuration procedure

The following sequence is needed to configure a DMA channel x:
1. Set the peripheral register address in the BDMA_CPARx register.
The data is moved from/to this address to/from the memory after the peripheral event,
or after the channel is enabled in memory-to-memory mode.
2. Set the memory address in the BDMA_CM0ARx register.
The data is written to/read from the memory after the peripheral event or after the
channel is enabled in memory-to-memory mode.
3. Configure the total number of data to transfer in the BDMA_CNDTRx register.
After each data transfer, this value is decremented.
4. Configure the parameters listed below in the BDMA_CCRx register:
– the channel priority
– the data transfer direction
– the circular mode
– the double-buffer mode
– the peripheral and memory incremented mode
– the peripheral and memory data size
– the interrupt enable at half and/or full transfer and/or transfer error
5. Activate the channel by setting the EN bit in the BDMA_CCRx register.
A channel, as soon as enabled, may serve any BDMA request from the peripheral
connected to this channel, or may start a memory-to-memory block transfer.
Note: The two last steps of the channel configuration procedure may be merged into a single
access to the BDMA_CCRx register, to configure and enable the channel.

Channel state and disabling a channel

A channel x in active state is an enabled channel (read BDMA_CCRx.EN = 1). An active
channel x is a channel that must have been enabled by the software (BDMA_CCRx.EN set
to 1) and afterwards with no occurred transfer error (BDMA_ISR.TEIFx = 0). In case there is
a transfer error, the channel is automatically disabled by hardware (BDMA_CCRx.EN = 0).
The three following use cases may happen:
• Suspend and resume a channel
This corresponds to the two following actions:
– An active channel is disabled by software (writing BDMA_CCRx.EN = 0 whereas
BDMA_CCRx.EN = 1).
– The software enables the channel again (BDMA_CCRx.EN set to 1) without
reconfiguring the other channel registers (such as BDMA_CNDTRx,
BDMA_CPARx and BDMA_CM0/1ARx).
This case is not supported by the BDMA hardware, that does not guarantee that the
remaining data transfers are performed correctly.
• Stop and abort a channel
If the application does not need any more the channel, this active channel can be
disabled by software. The channel is stopped and aborted but the BDMA_CNDTRx

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register content may not correctly reflect the remaining data transfers versus the
aborted source and destination buffer/register.
• Abort and restart a channel
This corresponds to the software sequence: disable an active channel, then
reconfigure the channel and enable it again.
This is supported by the hardware if the following conditions are met:
– The application guarantees that, when the software is disabling the channel, a
DMA data transfer is not occurring at the same time over its master port. For
example, the application can first disable the peripheral in DMA mode, in order to
ensure that there is no pending hardware DMA request from this peripheral.
– The software must operate separated write accesses to the same BDMA_CCRx
register: First disable the channel. Second reconfigure the channel for a next block
transfer including the BDMA_CCRx if a configuration change is needed. There are
read-only BDMA_CCRx register fields when BDMA_CCRx.EN=1. Finally enable
again the channel.
When a channel transfer error occurs, the EN bit of the BDMA_CCRx register is cleared by
hardware. This EN bit can not be set again by software to re-activate the channel x, until the
TEIFx bit of the BDMA_CxISR register is set.

Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)

The circular mode is available to handle circular buffers and continuous data flows (such as
ADC scan mode). This feature is enabled using the CIRC bit in the BDMA_CCRx register.
Note: The circular mode must not be used in memory-to-memory mode. Before enabling a
channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the
BDMA_CCRx register. When the circular mode is activated, the amount of data to transfer is
automatically reloaded with the initial value programmed during the channel configuration
phase, and the DMA requests continue to be served.
In order to stop a circular transfer, the software needs to stop the peripheral from generating
DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.
The software must explicitly program the BDMA_CNDTRx value before starting/enabling a
transfer, and after having stopped a circular transfer.

Memory-to-memory mode
The BDMA channels may operate without being triggered by a request from a peripheral.
This mode is called memory-to-memory mode, and is initiated by software.
If the MEM2MEM bit in the BDMA_CCRx register is set, the channel, if enabled, initiates
transfers. The transfer stops once the BDMA_CNDTRx register reaches zero.
Note: The memory-to-memory mode must not be used in circular mode. Before enabling a
channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC
bit of the BDMA_CCRx register.

Double-buffer mode (in memory-to-peripheral and peripheral-to memory

transfers)
The BDMA channels can operate in double-buffer mode.
The difference compared to a regular operation is that the BDMA controller toggles between
two memory address pointers at the end of each BDMA transfer, thus accessing two
memory areas in an alternate way. This allows the software to access one of the two

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memory areas while the BDMA controller accesses the other one. The double-buffer mode
transfer operates in both directions, so the target memory can be either the source or the
destination.
The double-buffer mode is configured by setting both the DBM and CIRC bits of the
BDMA_CCRx register.
Note: The double-buffer mode must not be used in memory-to-memory mode. Before enabling a
channel in double-buffer mode (DBM = 1), the software has to configure appropriately the
MEM2MEM bit (MEM2MEM = 0).
The steps described below allow the configuration of a BDMA channel x in double-buffer
mode:
• Set the DBM and CIRC bits and clear the MEM2MEM bit of the BDMA_CCRx register.
The circular mode is then activated for the swap mechanism to occur.
• Configure the second memory address register BDMA_CM1ARx.
• Continue with the regular channel configuration procedure, and lastly, activate the
channel by setting the EN bit of the BDMA_CCRx register. The first BDMA transfer
target memory of the corresponding BDMA channel x, is given by the CT bit of the
BDMA_CCRx register.
Note: Independently from the value of DBM bit of the BDMA_CCRx register, if CT = 1, the memory
address pointer for the BDMA transfer is defined by BDMA_CM1ARx, and not by
BDMA_CM0ARx.

Peripheral-to-peripheral mode
Any BDMA channel can operate in peripheral-to-peripheral mode:
• when the hardware request from a peripheral is selected to trigger the BDMA channel
This peripheral is the BDMA initiator and paces the data transfer from/to this peripheral
to/from a register belonging to another memory-mapped peripheral (this one being not
configured in DMA mode).
• when no peripheral request is selected and connected to the BDMA channel
The software configures a register-to-register transfer by setting the MEM2MEM bit of
the BDMA_CCRx register.

Programming transfer direction, assigning source/destination

The value of the DIR bit of the BDMA_CCRx register sets the direction of the transfer, and
consequently, it identifies the source and the destination, regardless the source/destination
type (peripheral or memory):
• DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1:
– The source attributes are defined by the BDMA_MARx register, the MSIZE[1:0]
field and MINC bit of the BDMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the source peripheral in peripheral-to-peripheral mode.
– The destination attributes are defined by the BDMA_PARx register, the
PSIZE[1:0] field and PINC bit of the BDMA_CCRx register.

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Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the destination memory in memory-to-memory mode.
• DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0:
– The source attributes are defined by the BDMA_PARx register, the PSIZE[1:0]
field and PINC bit of the BDMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the source memory in memory-to-memory mode
– The destination attributes are defined by the BDMA_MARx register, the
MSIZE[1:0] field and MINC bit of the BDMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the destination peripheral in peripheral-to-peripheral mode.

16.4.6 BDMA data width, alignment and endianness

When PSIZE[1:0] and MSIZE[1:0] are not equal, the BDMA controller performs some data
alignments as described in the table below.

Table 118. Programmable data width and endian behavior (when PINC = MINC = 1)
Source Destinat
port ion port Destination
Number Source content:
width width content:
of data address / data
(MSIZE (PSIZE address / data
items to (BDMA_CM0/1ARx DMA transfers
if if (BDMA_CPARx if
transfer if DIR = 1, else
DIR = 1, DIR = 1, DIR = 1, else
(NDT) BDMA_CPARx)
else else BDMA_CM0/1ARx)
PSIZE) MSIZE)

@0x0 / B0 1: read B0[7:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0

@0x1 / B1 2: read B1[7:0] @0x1 then write B1[7:0] @0x1 @0x1 / B1
8 8 8
@0x2 / B2 3: read B2[7:0] @0x2 then write B2[7:0] @0x2 @0x2 / B2
@0x3 / B3 4: read B3[7:0] @0x3 then write B3[7:0] @0x3 @0x3 / B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0 @0x0 / 00B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2 @0x2 / 00B1
8 16 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4 @0x4 / 00B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6 @0x6 / 00B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0 @0x0 / 000000B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4 @0x4 / 000000B1
8 32 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8 @0x8 / 000000B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC @0xC / 000000B3

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1 @0x1 / B2
16 8 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2 @0x2 / B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3 @0x3 / B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2 @0x2 / B3B2
16 16 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4 @0x4 / B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6 @0x6 / B7B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0 @0x0 / 0000B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4 @0x4 / 0000B3B2
16 32 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8 @0x8 / 0000B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC @0xC / 0000B7B6

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1 @0x1 / B4
32 8 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2 @0x2 / B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3 @0x3 / BC

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Table 118. Programmable data width and endian behavior (when PINC = MINC = 1) (continued)
Source Destinat
port ion port Destination
Number Source content:
width width content:
of data address / data
(MSIZE (PSIZE address / data
items to (BDMA_CM0/1ARx DMA transfers
if if (BDMA_CPARx if
transfer if DIR = 1, else
DIR = 1, DIR = 1, DIR = 1, else
(NDT) BDMA_CPARx)
else else BDMA_CM0/1ARx)
PSIZE) MSIZE)

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2 @0x2 / B5B4
32 16 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4 @0x4 / B9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6 @0x6 / BDBC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0 @0x0 / B3B2B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4
32 32 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC

Addressing AHB peripherals not supporting byte/half-word write transfers

When the BDMA controller initiates an AHB byte or half-word write transfer, the data are
duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]).
When the AHB slave peripheral does not support byte or half-word write transfers and does
not generate any error, the BDMA controller writes the 32 HWDATA bits as shown in the two
examples below:
• To write the half-word 0xABCD, the BDMA controller sets the HWDATA bus to
0xABCDABCD with a half-word data size (HSIZE = HalfWord in AHB master bus).
• To write the byte 0xAB, the BDMA controller sets the HWDATA bus to 0xABABABAB
with a byte data size (HSIZE = Byte in the AHB master bus).
Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into
account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB
transfer as described below:
• An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is
converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.
• An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to
an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.

16.4.7 BDMA error management

A BDMA transfer error is generated when reading from or writing to a reserved address
space. When a BDMA transfer error occurs during a BDMA read or write access, the faulty
channel x is automatically disabled through a hardware clear of its EN bit in the
corresponding BDMA_CCRx register.
The TEIFx bit of the BDMA_ISR register is set. An interrupt is then generated if the TEIE bit
of the BDMA_CCRx register is set.
The EN bit of the BDMA_CCRx register can not be set again by software (channel x re-
activated) until the TEIFx bit of the BDMA_ISR register is cleared (by setting the CTEIFx bit
of the BDMA_IFCR register).
When the software is notified with a transfer error over a channel which involves a
peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any
pending or future DMA request. Then software may normally reconfigure both BDMA and
the peripheral in DMA mode for a new transfer.

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16.5 BDMA interrupts

An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x. Separate interrupt enable bits are available for flexibility.

Table 119. BDMA interrupt requests

Interrupt
Interrupt request Interrupt event Event flag
enable bit

Half transfer on channel x HTIFx HTIEx

Transfer complete on channel x TCIFx TCIEx
Channel x interrupt
Transfer error on channel x TEIFx TEIEx
Half transfer or transfer complete or transfer error on channel x GIFx -

16.6 BDMA registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The BDMA registers have to be accessed by words (32-bit).

16.6.1 BDMA interrupt status register (BDMA_ISR)

Address offset: 0x00
Reset value: 0x0000 0000
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the BDMA_IFCR register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5 TEIF4 HTIF4 TCIF4 GIF4
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 TEIF0 HTIF0 TCIF0 GIF0
r r r r r r r r r r r r r r r r

Bit 31 TEIF7: transfer error (TE) flag for channel 7

0: no TE event
1: a TE event occurred
Bit 30 HTIF7: half transfer (HT) flag for channel 7
0: no HT event
1: a HT event occurred
Bit 29 TCIF7: transfer complete (TC) flag for channel 7
0: no TC event
1: a TC event occurred
Bit 28 GIF7: global interrupt flag for channel 7
0: no TE, HT or TC event
1: a TE, HT or TC event occurred

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Bit 27 TEIF6: transfer error (TE) flag for channel 6

0: no TE event
1: a TE event occurred
Bit 26 HTIF6: half transfer (HT) flag for channel 6
0: no HT event
1: a HT event occurred
Bit 25 TCIF6: transfer complete (TC) flag for channel 6
0: no TC event
1: a TC event occurred
Bit 24 GIF6: global interrupt flag for channel 6
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 23 TEIF5: transfer error (TE) flag for channel 5
0: no TE event
1: a TE event occurred
Bit 22 HTIF5: half transfer (HT) flag for channel 5
0: no HT event
1: a HT event occurred
Bit 21 TCIF5: transfer complete (TC) flag for channel 5
0: no TC event
1: a TC event occurred
Bit 20 GIF5: global interrupt flag for channel 5
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 19 TEIF4: transfer error (TE) flag for channel 4
0: no TE event
1: a TE event occurred
Bit 18 HTIF4: half transfer (HT) flag for channel 4
0: no HT event
1: a HT event occurred
Bit 17 TCIF4: transfer complete (TC) flag for channel 4
0: no TC event
1: a TC event occurred
Bit 16 GIF4: global interrupt flag for channel 4
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 15 TEIF3: transfer error (TE) flag for channel 3
0: no TE event
1: a TE event occurred
Bit 14 HTIF3: half transfer (HT) flag for channel 3
0: no HT event
1: a HT event occurred
Bit 13 TCIF3: transfer complete (TC) flag for channel 3
0: no TC event
1: a TC event occurred

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Bit 12 GIF3: global interrupt flag for channel 3

0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 11 TEIF2: transfer error (TE) flag for channel 2
0: no TE event
1: a TE event occurred
Bit 10 HTIF2: half transfer (HT) flag for channel 2
0: no HT event
1: a HT event occurred
Bit 9 TCIF2: transfer complete (TC) flag for channel 2
0: no TC event
1: a TC event occurred
Bit 8 GIF2: global interrupt flag for channel 2
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 7 TEIF1: transfer error (TE) flag for channel 1
0: no TE event
1: a TE event occurred
Bit 6 HTIF1: half transfer (HT) flag for channel 1
0: no HT event
1: a HT event occurred
Bit 5 TCIF1: transfer complete (TC) flag for channel 1
0: no TC event
1: a TC event occurred
Bit 4 GIF1: global interrupt flag for channel 1
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 3 TEIF0: transfer error (TE) flag for channel 0
0: no TE event
1: a TE event occurred
Bit 2 HTIF0: half transfer (HT) flag for channel 0
0: no HT event
1: a HT event occurred
Bit 1 TCIF0: transfer complete (TC) flag for channel 0
0: no TC event
1: a TC event occurred
Bit 0 GIF0: global interrupt flag for channel 0
0: no TE, HT or TC event
1: a TE, HT or TC event occurred

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16.6.2 BDMA interrupt flag clear register (BDMA_IFCR)

Address offset: 0x04
Reset value: 0x0000 0000
Setting the global clear bit CGIFx of the channel x in this BDMA_IFCR register, causes the
BDMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the BDMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this BDMA_IFCR
register, causes the BDMA hardware to clear the corresponding individual flag and the
global flag GIFx in the BDMA_ISR register, provided that none of the two other individual
flags is set.
Writing 0 into any flag clear bit has no effect.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHTIF7

CTCIF7

CHTIF6

CTCIF6

CHTIF5

CTCIF5

CHTIF4

CTCIF4
CTEIF7

CTEIF6

CTEIF5

CTEIF4
CGIF7

CGIF6

CGIF5

CGIF4
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHTIF3

CTCIF3

CHTIF2

CTCIF2

CHTIF1

CTCIF1

CHTIF0

CTCIF0
CTEIF3

CTEIF2

CTEIF1

CTEIF0
CGIF3

CGIF2

CGIF1

CGIF0
w w w w w w w w w w w w w w w w

Bit 31 CTEIF7: transfer error flag clear for channel 7

Bit 30 CHTIF7: half transfer flag clear for channel 7
Bit 29 CTCIF7: transfer complete flag clear for channel 7
Bit 28 CGIF7: global interrupt flag clear for channel 7
Bit 27 CTEIF6: transfer error flag clear for channel 6
Bit 26 CHTIF6: half transfer flag clear for channel 6
Bit 25 CTCIF6: transfer complete flag clear for channel 6
Bit 24 CGIF6: global interrupt flag clear for channel 6
Bit 23 CTEIF5: transfer error flag clear for channel 5
Bit 22 CHTIF5: half transfer flag clear for channel 5
Bit 21 CTCIF5: transfer complete flag clear for channel 5
Bit 20 CGIF5: global interrupt flag clear for channel 5
Bit 19 CTEIF4: transfer error flag clear for channel 4
Bit 18 CHTIF4: half transfer flag clear for channel 4
Bit 17 CTCIF4: transfer complete flag clear for channel 4
Bit 16 CGIF4: global interrupt flag clear for channel 4
Bit 15 CTEIF3: transfer error flag clear for channel 3
Bit 14 CHTIF3: half transfer flag clear for channel 3
Bit 13 CTCIF3: transfer complete flag clear for channel 3

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Bit 12 CGIF3: global interrupt flag clear for channel 3

Bit 11 CTEIF2: transfer error flag clear for channel 2
Bit 10 CHTIF2: half transfer flag clear for channe2
Bit 9 CTCIF2: transfer complete flag clear for channel 2
Bit 8 CGIF2: global interrupt flag clear for channel 2
Bit 7 CTEIF1: transfer error flag clear for channel 1
Bit 6 CHTIF1: half transfer flag clear for channel 1
Bit 5 CTCIF1: transfer complete flag clear for channel 1
Bit 4 CGIF1: global interrupt flag clear for channel 0
Bit 3 CTEIF0: transfer error flag clear for channel 0
Bit 2 CHTIF0: half transfer flag clear for channel 0
Bit 1 CTCIF0: transfer complete flag clear for channel 0
Bit 0 CGIF0: global interrupt flag clear for channel 0

16.6.3 BDMA channel x configuration register (BDMA_CCRx)

Address offset: 0x08 + 0x14 * x, (x = 0 to 7)
Reset value: 0x0000 0000
The register fields/bits CT, DBM, MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC,
PINC, and DIR are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM

DBM PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:17 Reserved, must be kept at reset value.

Bit 16 CT: current target memory of DMA transfer in double-buffer mode
This bit is toggled by hardware at the end of each channel transfer in double-buffer mode.
0: memory 0 (addressed by the BDMA_CM0AR pointer)
1: memory 1 (addressed by the BDMA_CM1AR pointer)
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 15 DBM: double-buffer mode
This bit must be set only in memory-to-peripheral and peripheral-to-memory transfers
(MEM2MEM=0). The CIRC bit must also be set in double buffer mode.
0: disabled (no memory address switch at the end of the BDMA transfer)
1: enabled (memory address switched at the end of the BDMA transfer)
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 14 MEM2MEM: memory-to-memory mode
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 13:12 PL[1:0]: priority level
00: low
01: medium
10: high
11: very high
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 11:10 MSIZE[1:0]: memory size
Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

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Bits 9:8 PSIZE[1:0]: peripheral size

Defines the data size of each DMA transfer to the identified peripheral.
In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 7 MINC: memory increment mode
Defines the increment mode for each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 6 PINC: peripheral increment mode
Defines the increment mode for each DMA transfer to the identified peripheral.
n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 5 CIRC: circular mode
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

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Bit 4 DIR: data transfer direction

This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
0: read from peripheral
– Source attributes are defined by PSIZE and PINC, plus the BDMA_CPARx register.
This is still valid in a memory-to-memory mode.
– Destination attributes are defined by MSIZE and MINC, plus the BDMA_CM0/1ARx
register. This is still valid in a peripheral-to-peripheral mode.
1: read from memory
– Destination attributes are defined by PSIZE and PINC, plus the BDMA_CPARx
register. This is still valid in a memory-to-memory mode.
– Source attributes are defined by MSIZE and MINC, plus the BDMA_CM0/1ARx
register. This is still valid in a peripheral-to-peripheral mode.
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 3 TEIE: transfer error interrupt enable
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 2 HTIE: half transfer interrupt enable
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 1 TCIE: transfer complete interrupt enable
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 0 EN: channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the BDMA_ISR register is cleared
(by setting the CTEIFx bit of the BDMA_IFCR register).
0: disabled
1: enabled
Note: this bit is set and cleared by software.

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16.6.4 BDMA channel x number of data to transfer register

(BDMA_CNDTRx)
Address offset: 0x0C + 0x14 * x, (x = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 NDT[15:0]: number of data to transfer (0 to 216 - 1)
This field is updated by hardware when the channel is enabled:
– It is decremented after each single BDMA ‘read followed by write’ transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the BDMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
If this field is zero, no transfer can be served whatever the channel status (enabled or not).
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

16.6.5 BDMA channel x peripheral address register (BDMA_CPARx)

Address offset: 0x10 + 0x14 * x, (x = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:0 PA[31:0]: peripheral address

It contains the base address of the peripheral data register from/to which the data is
read/written.
When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory destination address if
DIR = 1 and the memory source address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral destination address
DIR = 1 and the peripheral source address if DIR = 0.
Note: this register is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

16.6.6 BDMA channel x memory 0 address register (BDMA_CM0ARx)

Address offset: 0x14 + 0x14 * x, (x = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: peripheral address

It contains the base address of the memory from/to which the data is read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory source address if DIR = 1
and the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral source address
DIR = 1 and the peripheral destination address if DIR = 0.
Note: this register is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

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16.6.7 BDMA channel x memory 1 address register (BDMA_CM1ARx)

Address offset: 0x18 + 0x14 * x, (x = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: peripheral address

It contains the base address of the memory from/to which the data is read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory source address if DIR = 1
and the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral source address
DIR = 1 and the peripheral destination address if DIR = 0.
Note: this register is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

16.6.8 BDMA register map

The table below gives the BDMA register map and reset values.

Table 120. BDMA register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
HTIF7
TCIF7

HTIF6
TCIF6

HTIF5
TCIF5

HTIF4
TCIF4

HTIF3
TCIF3

HTIF2
TCIF2

HTIF1
TCIF1

HTIF0
TCIF0
TEIF7

TEIF6

TEIF5

TEIF4

TEIF3

TEIF2

TEIF1

TEIF0
GIF7

GIF6

GIF5

GIF4

GIF3

GIF2

GIF1

GIF0
BDMA_ISR
0x000
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CHTIF7
CTCIF7

CHTIF6
CTCIF6

CHTIF5
CTCIF5

CHTIF4
CTCIF4

CHTIF3
CTCIF3

CHTIF2
CTCIF2

CHTIF1
CTCIF1

CHTIF0
CTCIF0
CTEIF7

CTEIF6

CTEIF5

CTEIF4

CTEIF3

CTEIF2

CTEIF1

CTEIF0
CGIF7

CGIF6

CGIF5

CGIF4

CGIF3

CGIF2

CGIF1

CGIF0

BDMA_IFCR
0x004
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
DBM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT

BDMA_CCR0
0x008

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BDMA_CNDTR0 NDTR[15:0]
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CPAR0 PA[31:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM0AR0 MA[31:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM1AR0 MA[31:0]
0x018
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0433 Rev 8 689/3353

691
Basic direct memory access controller (BDMA) RM0433

Table 120. BDMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
DBM

TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT
BDMA_CCR1
0x01C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BDMA_CNDTR1 NDTR[15:0]
0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CPAR1 PA[31:0]
0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM0AR1 MA[31:0]
0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM1AR1 MA[31:0]
0x02C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
DBM

TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT
BDMA_CCR2
0x030

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BDMA_CNDTR2 NDTR[15:0]
0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CPAR2 PA[31:0]
0x038
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM0AR2 MA[31:0]
0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM1AR2 MA[31:0]
0x040
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
DBM

TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT

BDMA_CCR3
0x044

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BDMA_CNDTR3 NDTR[15:0]
0x048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CPAR3 PA[31:0]
0x04C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM0AR3 MA[31:0]
0x050
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM1AR3 MA[31:0]
0x054
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
DBM

TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT

BDMA_CCR4
0x058

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BDMA_CNDTR4 NDTR[15:0]
0x05C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CPAR4 PA[31:0]
0x060
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM0AR4 MA[31:0]
0x064
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM1AR4 MA[31:0]
0x068
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

690/3353 RM0433 Rev 8

RM0433 Basic direct memory access controller (BDMA)

Table 120. BDMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
DBM

TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT
BDMA_CCR5
0x06C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BDMA_CNDTR5 NDTR[15:0]
0x070
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CPAR5 PA[31:0]
0x074
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM0AR5 MA[31:0]
0x078
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM1AR5 MA[31:0]
0x07C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
DBM

TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT
BDMA_CCR6
0x080

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BDMA_CNDTR6 NDTR[15:0]
0x084
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CPAR6 PA[31:0]
0x088
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM0AR6 MA[31:0]
0x08C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM1AR6 MA[31:0]
0x090
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
DBM

TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT

BDMA_CCR7
0x094

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BDMA_CNDTR7 NDTR[15:0]
0x098
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CPAR7 PA[31:0]
0x09C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM0AR7 MA[31:0]
0x0A0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDMA_CM1AR7 MA[31:0]
0x0A4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 129 for the register boundary addresses.

RM0433 Rev 8 691/3353

691
DMA request multiplexer (DMAMUX) RM0433

17 DMA request multiplexer (DMAMUX)

17.1 Introduction
A peripheral indicates a request for DMA transfer by setting its DMA request signal. The
DMA request is pending until served by the DMA controller that generates a DMA
acknowledge signal, and the corresponding DMA request signal is deasserted.
In this document, the set of control signals required for the DMA request/acknowledge
protocol is not explicitly shown or described, and it is referred to as DMA request line.
The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controllers of the product. The routing function is ensured by a
programmable multi-channel DMA request line multiplexer. Each channel selects a unique
DMA request line, unconditionally or synchronously with events from its DMAMUX
synchronization inputs. The DMAMUX may also be used as a DMA request generator from
programmable events on its input trigger signals.
The number of DMAMUX instances and their main characteristics are specified in
Section 17.3.1.
The assignment of DMAMUX request multiplexer inputs to the DMA request lines from
peripherals and to the DMAMUX request generator outputs, the assignment of DMAMUX
request multiplexer outputs to DMA controller channels, and the assignment of DMAMUX
synchronizations and trigger inputs to internal and external signals depend upon product
implementation. They are detailed in Section 17.3.2.

692/3353 RM0433 Rev 8

RM0433 DMA request multiplexer (DMAMUX)

17.2 DMAMUX main features

• Up to 16-channel programmable DMA request line multiplexer output
• Up to 8-channel DMA request generator
• Up to 32 trigger inputs to DMA request generator
• Up to 16 synchronization inputs
• Per DMA request generator channel:
– DMA request trigger input selector
– DMA request counter
– Event overrun flag for selected DMA request trigger input
• Per DMA request line multiplexer channel output:
– Up to 107 input DMA request lines from peripherals
– One DMA request line output
– Synchronization input selector
– DMA request counter
– Event overrun flag for selected synchronization input
– One event output, for DMA request chaining

17.3 DMAMUX implementation

17.3.1 DMAMUX1 and DMAMUX2 instantiation

The product integrates two instances of DMA request multiplexer:
• DMAMUX1 for DMA1 and DMA2 (D2 domain)
• DMAMUX2 for BDMA (D3 domain)
DMAMUX1 and DMAMUX2are instantiated with the hardware configuration parameters
listed in the following table.

Table 121. DMAMUX1 and DMAMUX2 instantiation

Feature DMAMUX1 DMAMUX2

Number of DMAMUX output request channels 16 8

Number of DMAMUX request generator channels 8 8
Number of DMAMUX request trigger inputs 8 32
Number of DMAMUX synchronization inputs 8 16
Number of DMAMUX peripheral request inputs 107 12

17.3.2 DMAMUX1 mapping

The mapping of resources to DMAMUX1 is hardwired.
DMAMUX1 is used with DMA1 and DMA2 in D2 domain
• DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7
• DMAMUX1 channels 8 to 15 are connected to DMA2 channels 0 to 7

RM0433 Rev 8 693/3353

714
DMA request multiplexer (DMAMUX) RM0433

Table 122. DMAMUX1: assignment of multiplexer inputs to resources

DMA DMA DMA
request Resource request Resource request Resource
MUX input MUX input MUX input

1 dmamux1_req_gen0 44 usart2_tx_dma 87 sai1a_dma

2 dmamux1_req_gen1 45 usart3_rx_dma 88 sai1b_dma
3 dmamux1_req_gen2 46 usart3_tx_dma 89 sai2a_dma
4 dmamux1_req_gen3 47 TIM8_CH1 90 sai2b_dma
5 dmamux1_req_gen4 48 TIM8_CH2 91 swpmi_rx_dma
6 dmamux1_req_gen5 49 TIM8_CH3 92 swpmi_tx_dma
7 dmamux1_req_gen6 50 TIM8_CH4 93 spdifrx_dat_dma
8 dmamux1_req_gen7 51 TIM8_UP 94 spdifrx_ctrl_dma
9 adc1_dma 52 TIM8_TRIG 95 HR_REQ(1)
10 adc2_dma 53 TIM8_COM 96 HR_REQ(2)
11 TIM1_CH1 54 Reserved 97 HR_REQ(3)
12 TIM1_CH2 55 TIM5_CH1 98 HR_REQ(4)
13 TIM1_CH3 56 TIM5_CH2 99 HR_REQ(5)
14 TIM1_CH4 57 TIM5_CH3 100 HR_REQ(6)
15 TIM1_UP 58 TIM5_CH4 101 dfsdm1_dma0
16 TIM1_TRIG 59 TIM5_UP 102 dfsdm1_dma1
17 TIM1_COM 60 TIM5_TRIG 103 dfsdm1_dma2
18 TIM2_CH1 61 spi3_rx_dma 104 dfsdm1_dma3
19 TIM2_CH2 62 spi3_tx_dma 105 TIM15_CH1
20 TIM2_CH3 63 uart4_rx_dma 106 TIM15_UP
21 TIM2_CH4 64 uart4_tx_dma 107 TIM15_TRIG
22 TIM2_UP 65 uart5_rx_dma 108 TIM15_COM
23 TIM3_CH1 66 uart5_tx_dma 109 TIM16_CH1
24 TIM3_CH2 67 dac_ch1_dma 110 TIM16_UP
25 TIM3_CH3 68 dac_ch2_dma 111 TIM17_CH1
26 TIM3_CH4 69 TIM6_UP 112 TIM17_UP
27 TIM3_UP 70 TIM7_UP 113 sai3_a_dma
28 TIM3_TRIG 71 usart6_rx_dma 114 sai3_b_dma
29 TIM4_CH1 72 usart6_tx_dma 115 adc3_dma
30 TIM4_CH2 73 i2c3_rx_dma 116 Reserved
31 TIM4_CH3 74 i2c3_tx_dma 117 Reserved
32 TIM4_UP 75 dcmi_dma 118 Reserved
33 i2c1_rx_dma 76 cryp_in_dma 119 Reserved
34 i2c1_tx_dma 77 cryp_out_dma 120 Reserved
35 i2c2_rx_dma 78 hash_in_dma 121 Reserved
36 i2c2_tx_dma 79 uart7_rx_dma 122 Reserved

694/3353 RM0433 Rev 8

RM0433 DMA request multiplexer (DMAMUX)

Table 122. DMAMUX1: assignment of multiplexer inputs to resources (continued)

DMA DMA DMA
request Resource request Resource request Resource
MUX input MUX input MUX input

37 spi1_rx_dma 80 uart7_tx_dma 123 Reserved

38 spi1_tx_dma 81 uart8_rx_dma 124 Reserved
39 spi2_rx_dma 82 uart8_tx_dma 125 Reserved
40 spi2_tx_dma 83 spi4_rx_dma 126 Reserved
41 usart1_rx_dma 84 spi4_tx_dma 127 Reserved
42 usart1_tx_dma 85 spi5_rx_dma - -
43 usart2_rx_dma 86 spi5_tx_dma - -

Table 123. DMAMUX1: assignment of multiplexer inputs to resources

DMA DMA DMA
request Resource request Resource request Resource
MUX input MUX input MUX input

1 dmamux1_req_gen0 44 usart2_tx_dma 87 sai1a_dma

2 dmamux1_req_gen1 45 usart3_rx_dma 88 sai1b_dma
3 dmamux1_req_gen2 46 usart3_tx_dma 89 sai2a_dma
4 dmamux1_req_gen3 47 TIM8_CH1 90 sai2b_dma
5 dmamux1_req_gen4 48 TIM8_CH2 91 swpmi_rx_dma
6 dmamux1_req_gen5 49 TIM8_CH3 92 swpmi_tx_dma
7 dmamux1_req_gen6 50 TIM8_CH4 93 spdifrx_dat_dma
8 dmamux1_req_gen7 51 TIM8_UP 94 spdifrx_ctrl_dma
9 adc1_dma 52 TIM8_TRIG 95 HR_REQ(1)
10 adc2_dma 53 TIM8_COM 96 HR_REQ(2)
11 TIM1_CH1 54 Reserved 97 HR_REQ(3)
12 TIM1_CH2 55 TIM5_CH1 98 HR_REQ(4)
13 TIM1_CH3 56 TIM5_CH2 99 HR_REQ(5)
14 TIM1_CH4 57 TIM5_CH3 100 HR_REQ(6)
15 TIM1_UP 58 TIM5_CH4 101 dfsdm1_dma0
16 TIM1_TRIG 59 TIM5_UP 102 dfsdm1_dma1
17 TIM1_COM 60 TIM5_TRIG 103 dfsdm1_dma2
18 TIM2_CH1 61 spi3_rx_dma 104 dfsdm1_dma3
19 TIM2_CH2 62 spi3_tx_dma 105 TIM15_CH1
20 TIM2_CH3 63 uart4_rx_dma 106 TIM15_UP
21 TIM2_CH4 64 uart4_tx_dma 107 TIM15_TRIG
22 TIM2_UP 65 uart5_rx_dma 108 TIM15_COM
23 TIM3_CH1 66 uart5_tx_dma 109 TIM16_CH1
24 TIM3_CH2 67 dac_ch1_dma 110 TIM16_UP
25 TIM3_CH3 68 dac_ch2_dma 111 TIM17_CH1

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DMA request multiplexer (DMAMUX) RM0433

Table 123. DMAMUX1: assignment of multiplexer inputs to resources (continued)

DMA DMA DMA
request Resource request Resource request Resource
MUX input MUX input MUX input

26 TIM3_CH4 69 TIM6_UP 112 TIM17_UP

27 TIM3_UP 70 TIM7_UP 113 sai3_a_dma
28 TIM3_TRIG 71 usart6_rx_dma 114 sai3_b_dma
29 TIM4_CH1 72 usart6_tx_dma 115 adc3_dma
30 TIM4_CH2 73 i2c3_rx_dma 116 Reserved
31 TIM4_CH3 74 i2c3_tx_dma 117 Reserved
32 TIM4_UP 75 dcmi_dma 118 Reserved
33 i2c1_rx_dma 76 cryp_in_dma 119 Reserved
34 i2c1_tx_dma 77 cryp_out_dma 120 Reserved
35 i2c2_rx_dma 78 hash_in_dma 121 Reserved
36 i2c2_tx_dma 79 uart7_rx_dma 122 Reserved
37 spi1_rx_dma 80 uart7_tx_dma 123 Reserved
38 spi1_tx_dma 81 uart8_rx_dma 124 Reserved
39 spi2_rx_dma 82 uart8_tx_dma 125 Reserved
40 spi2_tx_dma 83 spi4_rx_dma 126 Reserved
41 usart1_rx_dma 84 spi4_tx_dma 127 Reserved
42 usart1_tx_dma 85 spi5_rx_dma - -
43 usart2_rx_dma 86 spi5_tx_dma - -

Table 124. DMAMUX1: assignment of trigger inputs to resources

Trigger input Resource Trigger input Resource

0 dmamux1_evt0 4 lptim2_out
1 dmamux1_evt1 5 lptim3_out
2 dmamux1_evt2 6 extit0
3 lptim1_out 7 TIM12_TRGO

Table 125. DMAMUX1: assignment of synchronization inputs to resources

Sync. input Resource Sync. input Resource

0 dmamux1_evt0 4 lptim2_out
1 dmamux1_evt1 5 lptim3_out
2 dmamux1_evt2 6 extit0
3 lptim1_out 7 TIM12_TRGO

17.3.3 DMAMUX2 mapping

DMAMUX2 channels 0 to 7 are connected to BDMA channels 0 to 7.

696/3353 RM0433 Rev 8

RM0433 DMA request multiplexer (DMAMUX)

Table 126. DMAMUX2: assignment of multiplexer inputs to resources

DMA request DMA request
Resource Resource
MUX input MUX input

1 dmamux2_req_gen0 17 adc3_dma
2 dmamux2_req_gen1 18 Reserved
3 dmamux2_req_gen2 19 Reserved
4 dmamux2_req_gen3 20 Reserved
5 dmamux2_req_gen4 21 Reserved
6 dmamux2_req_gen5 22 Reserved
7 dmamux2_req_gen6 23 Reserved
8 dmamux2_req_gen7 24 Reserved
9 lpuart1_rx_dma 25 Reserved
10 lpuart1_tx_dma 26 Reserved
11 spi6_rx_dma 27 Reserved
12 spi6_tx_dma 28 Reserved
13 i2c4_rx_dma 29 Reserved
14 i2c4_tx_dma 30 Reserved
15 sai4_a_dma 31 Reserved
16 sai4_b_dma 32 Reserved

Table 127. DMAMUX2: assignment of trigger inputs to resources

Trigger input Resource Trigger input Resource

0 dmamux2_evt0 16 spi6_wkup
1 dmamux2_evt1 17 Comp1_out
2 dmamux2_evt2 18 Comp2_out
3 dmamux2_evt3 19 RTC_wkup
4 dmamux2_evt4 20 Syscfg_exti0_mux
5 dmamux2_evt5 21 Syscfg_exti2_mux
6 dmamux2_evt6 22 I2c4_event_it
7 lpuart_rx_wkup 23 spi6_it
8 lpuart_tx_wkup 24 Lpuart1_it_T
9 lptim2_wkup 25 Lpuart1_it_R
10 lptim2_out 26 adc3_it
11 lptim3_wkup 27 adc3_awd1
12 lptim3_out 28 bdma_ch0_it
13 Lptim4_ait 29 bdma_ch1_it
14 Lptim5_ait 30 Reserved
15 I2c4_wkup 31 Reserved

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DMA request multiplexer (DMAMUX) RM0433

Table 128. DMAMUX2: assignment of synchronization inputs to resources

Sync input Resource Sync input Resource

0 dmamux2_evt0 16 Reserved
1 dmamux2_evt1 17 Reserved
2 dmamux2_evt2 18 Reserved
3 dmamux2_evt3 19 Reserved
4 dmamux2_evt4 20 Reserved
5 dmamux2_evt5 21 Reserved
6 lpuart1_rx_wkup 22 Reserved
7 lpuart1_tx_wkup 23 Reserved
8 Lptim2_out 24 Reserved
9 Lptim3_out 25 Reserved
10 I2c4_wkup 26 Reserved
11 spi6_wkup 27 Reserved
12 Comp1_out 28 Reserved
13 RTC_wkup 29 Reserved
14 Syscfg_exti0_mux 30 Reserved
15 Syscfg_exti2_mux 31 Reserved

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RM0433 DMA request multiplexer (DMAMUX)

17.4 DMAMUX functional description

17.4.1 DMAMUX block diagram

Figure 84 shows the DMAMUX block diagram.

Figure 84. DMAMUX block diagram

32-bit AHB bus

dmamux_hclk

DMAMUX Request multiplexer

AHB slave
interface Channel m
DMAMUX_CmCR

p Channel 1
Channel 0
DMA requests xq
re
DMAMUX_C0CR
x_

from peripherals: 1
mu

dmamux_req_inx Channel Ctrl

a

0
dm

select
n+p+2 m DMA requests
1 to DMA controllers:
0
Request generator dmamux_req_outx
n+3
Channel n n
Sync
dmamux_req_genx

DMAMUX_RGCnCR n+2 m
DMA channels
1 events:
n+1 0
dmamux_evtx
s 1 0
Channel 1 1 2
DMAMUX_RGC1CR
1
Channel 0 0
DMAMUX_RGC0CR

Interrupt
interface
t 1 0 s 1 0

Control registers Trigger inputs: Interrupt: Synchronization inputs:

dmamux_trgx dmamux_ovr_it dmamux_syncx
MSv39745V1

DMAMUX features two main sub-blocks: the request line multiplexer and the request line
generator.
The implementation assigns:
• DMAMUX request multiplexer sub-block inputs (dmamux_reqx) from peripherals
(dmamux_req_inx) and from channels of the DMAMUX request generator sub-block
(dmamux_req_genx)
• DMAMUX request outputs to channels of DMA controllers (dmamux_req_outx)
• Internal or external signals to DMA request trigger inputs (dmamux_trgx)
• Internal or external signals to synchronization inputs (dmamux_syncx)

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17.4.2 DMAMUX signals

Table 129 lists the DMAMUX signals.

Table 129. DMAMUX signals

Signal name Description

dmamux_hclk DMAMUX AHB clock

dmamux_req_inx DMAMUX DMA request line inputs from peripherals
dmamux_trgx DMAMUX DMA request triggers inputs (to request generator sub-block)
dmamux_req_genx DMAMUX request generator sub-block channels outputs
DMAMUX request multiplexer sub-block inputs (from peripheral
dmamux_reqx
requests and request generator channels)
dmamux_syncx DMAMUX synchronization inputs (to request multiplexer sub-block)
dmamux_req_outx DMAMUX requests outputs (to DMA controllers)
dmamux_evtx DMAMUX events outputs
dmamux_ovr_it DMAMUX overrun interrupts

17.4.3 DMAMUX channels

A DMAMUX channel is a request multiplexer channel that can include, depending upon the
selected input of the request multiplexer, an additional DMAMUX request generator
channel.
A DMAMUX request multiplexer channel is connected and dedicated to a single channel of
DMA controller(s).

Channel configuration procedure

Follow the sequence below to configure a DMAMUX x channel and the related DMA
channel y:
1. Set and configure completely the DMA channel y, except enabling the channel y.
2. Set and configure completely the related DMAMUX y channel.
3. Last, activate the DMA channel y by setting the EN bit in the DMA y channel register.

17.4.4 DMAMUX request line multiplexer

The DMAMUX request multiplexer with its multiple channels ensures the actual routing of
DMA request/acknowledge control signals, named DMA request lines.
Each DMA request line is connected in parallel to all the channels of the DMAMUX request
line multiplexer.
A DMA request is sourced either from the peripherals, or from the DMAMUX request
generator.
The DMAMUX request line multiplexer channel x selects the DMA request line number as
configured by the DMAREQ_ID field in the DMAMUX_CxCR register.
Note: The null value in the field DMAREQ_ID corresponds to no DMA request line selected.

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RM0433 DMA request multiplexer (DMAMUX)

Caution: A same non-null DMAREQ_ID cannot be programmed to different x and y DMAMUX

request multiplexer channels (via DMAMUX_CxCR and DMAMUX_CyCR), except when the
application guarantees that the two connected DMA channels are not simultaneously active.
On top of the DMA request selection, the synchronization mode and/or the event generation
may be configured and enabled, if required.

Synchronization mode and channel event generation

Each DMAMUX request line multiplexer channel x can be individually synchronized by
setting the synchronization enable (SE) bit in the DMAMUX_CxCR register.
DMAMUX has multiple synchronization inputs. The synchronization inputs are connected in
parallel to all the channels of the request multiplexer.
The synchronization input is selected via the SYNC_ID field in the DMAMUX_CxCR register
of a given channel x.
When a channel is in this synchronization mode, the selected input DMA request line is
propagated to the multiplexer channel output, once a programmable rising/falling edge is
detected on the selected input synchronization signal, via the SPOL[1:0] field of the
DMAMUX_CxCR register.
Additionally, internally to the DMAMUX request multiplexer, there is a programmable DMA
request counter, which can be used for the channel request output generation, and for an
event generation. An event generation on the channel x output is enabled through the EGE
bit (event generation enable) of the DMAMUX_CxCR register.
As shown in Figure 86, upon the detected edge of the synchronization input, the pending
selected input DMA request line is connected to the DMAMUX multiplexer channel x output.
Note: If a synchronization event occurs while there is no pending selected input DMA request line,
it is discarded. The following asserted input request lines is not connected to the DMAMUX
multiplexer channel output until a synchronization event occurs again.
From this point on, each time the connected DMAMUX request is served by the DMA
controller (a served request is deasserted), the DMAMUX request counter is decremented.
At its underrun, the DMA request counter is automatically loaded with the value in the
NBREQ field of the DMAMUX_CxCR register and the input DMA request line is
disconnected from the multiplexer channel x output.
Thus, the number of DMA requests transferred to the multiplexer channel x output following
a detected synchronization event, is equal to the value in the NBREQ field, plus one.
Note: The NBREQ field value can be written by software only when both synchronization enable
bit (SE) and event generation enable bit (EGE) of the corresponding multiplexer channel x
are disabled.

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Figure 85. Synchronization mode of the DMAMUX request line multiplexer channel

Selected DMA request line transferred to the output

DMA requests served

DMA request pending

Selected
dmamux_reqx
Not pending

dmamux_syncx

dmamux_req_outx

DMA request counter 4 3 2 1 0 4

dmamux_evtx

DMA request counter underrun

Synchronization event
DMA request counter auto-reload to NBREQ
Input DMA request line connected to output
Input DMA request line disconnected from output

Example: DMAMUX_CCRx configured with: NBREQ=4, SE=1, EGE=1, SPOL=01 (rising edge)

MSv41974V1

Figure 86. Event generation of the DMA request line multiplexer channel

Selected DMA request line transferred to the output

DMA request pending

Selected
dmamux_reqx Not pending

dmamux_req_outx

DMA request counter 3 2 1 0 3 2 1 0 3 2 1 0

SE

EGE

dmamux_evtx

DMA request counter reaches zero

Event is generated on the output
DMA request counter auto-reloads with NBREQ value

Example with: DMAMUX_CCRx configured with: NBREQ=3, SE=0, EGE=1

MSv41975V1

If EGE is enabled, the multiplexer channel generates a channel event, as a pulse of one
AHB clock cycle, when its DMA request counter is automatically reloaded with the value of
the programmed NBREQ field, as shown in Figure 85 and Figure 86.

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RM0433 DMA request multiplexer (DMAMUX)

Note: If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request.
Note: A synchronization event (edge) is detected if the state following the edge remains stable for
more than two AHB clock cycles.
Upon writing into DMAMUX_CxCR register, the synchronization events are masked during
three AHB clock cycles.

Synchronization overrun and interrupt

If a new synchronization event occurs before the request counter underrun (the internal
request counter programmed via the NBREQ field of the DMAMUX_CxCR register), the
synchronization overrun flag bit SOFx is set in the DMAMUX_CSR register.
Note: The request multiplexer channel x synchronization must be disabled
(DMAMUX_CxCR.SE = 0) when the use of the related channel of the DMA controller is
completed. Else, upon a new detected synchronization event, there is a synchronization
overrun due to the absence of a DMA acknowledge (that is, no served request) received
from the DMA controller.
The overrun flag SOFx is reset by setting the associated clear synchronization overrun flag
bit CSOFx in the DMAMUX_CFR register.
Setting the synchronization overrun flag generates an interrupt if the synchronization
overrun interrupt enable bit SOIE is set in the DMAMUX_CxCR register.

17.4.5 DMAMUX request generator

The DMAMUX request generator produces DMA requests following trigger events on its
DMA request trigger inputs.
The DMAMUX request generator has multiple channels. DMA request trigger inputs are
connected in parallel to all channels.
The outputs of DMAMUX request generator channels are inputs to the DMAMUX request
line multiplexer.
Each DMAMUX request generator channel x has an enable bit GE (generator enable) in the
corresponding DMAMUX_RGxCR register.
The DMA request trigger input for the DMAMUX request generator channel x is selected
through the SIG_ID (trigger signal ID) field in the corresponding DMAMUX_RGxCR register.
Trigger events on a DMA request trigger input can be rising edge, falling edge or either
edge. The active edge is selected through the GPOL (generator polarity) field in the
corresponding DMAMUX_RGxCR register.
Upon the trigger event, the corresponding generator channel starts generating DMA
requests on its output. Each time the DMAMUX generated request is served by the
connected DMA controller (a served request is deasserted), a built-in (inside the DMAMUX
request generator) DMA request counter is decremented. At its underrun, the request
generator channel stops generating DMA requests and the DMA request counter is
automatically reloaded to its programmed value upon the next trigger event.
Thus, the number of DMA requests generated after the trigger event is GNBREQ + 1.

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DMA request multiplexer (DMAMUX) RM0433

Note: The GNBREQ field value can be written by software only when the enable GE bit of the
corresponding generator channel x is disabled.
There is no hardware write protection.
A trigger event (edge) is detected if the state following the edge remains stable for more
than two AHB clock cycles.
Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three
AHB clock cycles.

Trigger overrun and interrupt

If a new DMA request trigger event occurs before the DMAMUX request generator counter
underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR
register), and if the request generator channel x was enabled via GE, then the request
trigger event overrun flag bit OFx is asserted by the hardware in the DMAMUX_RGSR
register.
Note: The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) when the
usage of the related channel of the DMA controller is completed. Else, upon a new detected
trigger event, there is a trigger overrun due to the absence of an acknowledge (that is, no
served request) received from the DMA.
The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the
DMAMUX_RGCFR register.
Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request
trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.

17.5 DMAMUX interrupts

An interrupt can be generated upon:
• a synchronization event overrun in each DMA request line multiplexer channel
• a trigger event overrun in each DMA request generator channel
For each case, per-channel in.dividual interrupt enable, status, and clear flag register bits
are available.

Table 130. DMAMUX interrupts

Interrupt signal Interrupt event Event flag Clear bit Enable bit

Synchronization event overrun

on channel x of the SOFx CSOFx SOIE
DMAMUX request line multiplexer
dmamuxovr_it
Trigger event overrun
on channel x of the OFx COFx OIE
DMAMUX request generator

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RM0433 DMA request multiplexer (DMAMUX)

17.6 DMAMUX registers

Refer to the table containing register boundary addresses for the DMAMUX1 and
DMAMUX2 base address.
DMAMUX registers may be accessed per byte (8-bit), half-word (16-bit), or word (32-bit).
The address must be aligned with the data size.

17.6.1 DMAMUX1 request line multiplexer channel x configuration register

(DMAMUX1_CxCR)
Address offset: 0x000 + 0x04 * x (x = 0 to 15)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. SYNC_ID[2:0] NBREQ[4:0] SPOL[1:0] SE
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. EGE SOIE Res. DMAREQ_ID[6:0]
rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 SYNC_ID[2:0]: Synchronization identification
Selects the synchronization input (see Table 125: DMAMUX1: assignment of synchronization
inputs to resources).
Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization
event, and/or the number of DMA requests before an output event is generated.
This field must only be written when both SE and EGE bits are low.
Bits 18:17 SPOL[1:0]: Synchronization polarity
Defines the edge polarity of the selected synchronization input:
00: No event (no synchronization, no detection).
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 SE: Synchronization enable
0: Synchronization disabled
1: Synchronization enabled
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 EGE: Event generation enable
0: Event generation disabled
1: Event generation enabled
Bit 8 SOIE: Synchronization overrun interrupt enable
0: Interrupt disabled
1: Interrupt enabled

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Bit 7 Reserved, must be kept at reset value.

Bits 6:0 DMAREQ_ID[6:0]: DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer
inputs to resources.

17.6.2 DMAMUX2 request line multiplexer channel x configuration register

(DMAMUX2_CxCR)
Address offset: 0x000 + 0x04 * x, where x = 0 to 7
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SYNC_ID[4:0] NBREQ[4:0] SPOL[1:0] SE
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. EGE SOIE Res. Res. Res. DMAREQ_ID[4:0]
rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SYNC_ID[4:0]: Synchronization identification
Selects the synchronization input (see Table 127: DMAMUX2: assignment of trigger inputs to
resources)
Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization
event, and/or the number of DMA requests before an output event is generated.
This field shall only be written when both SE and EGE bits are low.
Bits 18:17 SPOL[1:0]: Synchronization polarity
Defines the edge polarity of the selected synchronization input:
00: no event (no synchronization, no detection).
01: rising edge
10: falling edge
11: rising and falling edges
Bit 16 SE: Synchronization enable
0: synchronization disabled
1: synchronization enabled
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 EGE: Event generation enable
0: event generation disabled
1: event generation enabled
Bit 8 SOIE: Synchronization overrun interrupt enable
0: interrupt disabled
1: interrupt enabled
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DMAREQ_ID[4:0]: DMA request identification
Selects the input DMA request. (see the DMAMUX table about assignments of multiplexer
inputs to resources).

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RM0433 DMA request multiplexer (DMAMUX)

17.6.3 DMAMUX1 request line multiplexer interrupt channel status register

(DMAMUX1_CSR)
Address offset: 0x080
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOF15 SOF14 SOF13 SOF12 SOF11 SOF10 SOF9 SOF8 SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SOF[15:0]: Synchronization overrun event flag
The flag is set when a synchronization event occurs on a DMA request line multiplexer
channel x, while the DMA request counter value is lower than NBREQ.
The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
For DMAMUX2 bits 15:8 are reserved, keep them at reset value.

17.6.4 DMAMUX2 request line multiplexer interrupt channel status register

(DMAMUX2_CSR)
Address offset: 0x080
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0
r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 SOF[7:0]: Synchronization overrun event flag
The flag is set when a new synchronization event occurs on a DMA request line multiplexer
channel x before the request counter underrun (the internal request counter programmed via
the NBREQ field of the DMAMUX_CxCR register).
The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX2_CFR register.

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DMA request multiplexer (DMAMUX) RM0433

17.6.5 DMAMUX1 request line multiplexer interrupt clear flag register

(DMAMUX1_CFR)
Address offset: 0x084
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 CSOF[15:0]: Clear synchronization overrun event flag
Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR
register.

17.6.6 DMAMUX2 request line multiplexer interrupt clear flag register

(DMAMUX2_CFR)
Address offset: 0x084
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. CSOF6 CSOF6 CSOF5 CSOF4 CSOF3 CSOF2 CSOF1 CSOF0
w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 CSOF[7:0]: Clear synchronization overrun event flag
Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX2_CSR
register.

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RM0433 DMA request multiplexer (DMAMUX)

17.6.7 DMAMUX1 request generator channel x configuration register

(DMAMUX1_RGxCR)
Address offset: 0x100 + 0x04 * x (x = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. GNBREQ[4:0] GPOL[1:0] GE
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. OIE Res. Res. Res. Res. Res. SIG_ID[2:0]
rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:19 GNBREQ[4:0]: Number of DMA requests to be generated (minus 1)
Defines the number of DMA requests to be generated after a trigger event. The actual
number of generated DMA requests is GNBREQ +1.
Note: This field must be written only when GE bit is disabled.
Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity
Defines the edge polarity of the selected trigger input
00: No event, i.e. no trigger detection nor generation.
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 GE: DMA request generator channel x enable
0: DMA request generator channel x disabled
1: DMA request generator channel x enabled
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 OIE: Trigger overrun interrupt enable
0: Interrupt on a trigger overrun event occurrence is disabled
1: Interrupt on a trigger overrun event occurrence is enabled
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 SIG_ID[2:0]: Signal identification
Selects the DMA request trigger input used for the channel x of the DMA request generator

17.6.8 DMAMUX2 request generator channel x configuration register

(DMAMUX2_RGxCR)
Address offset: 0x100 + 0x04 * x (x = 0 to 7)
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. GNBREQ[4:0] GPOL[1:0] GE
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. OIE Res. Res. Res. SIG_ID[4:0]
rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:19 GNBREQ[4:0]: Number of DMA requests to be generated (minus 1)
Defines the number of DMA requests to be generated after a trigger event. The actual
number of generated DMA requests is GNBREQ+1.
Note: This field shall only be written when GE bit is disabled.
Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity
Defines the edge polarity of the selected trigger input
00: no event. I.e. none trigger detection nor generation.
01: rising edge
10: falling edge
11: rising and falling edge
Bit 16 GE: DMA request generator channel x enable
0: DMA request generator channel x disabled
1: DMA request generator channel x enabled
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 OIE: Trigger overrun interrupt enable
0: interrupt on a trigger overrun event occurrence is disabled
1: interrupt on a trigger overrun event occurrence is enabled
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 SIG_ID[4:0]: Signal identification
Selects the DMA request trigger input used for the channel x of the DMA request generator

17.6.9 DMAMUX1 request generator interrupt status register

(DMAMUX1_RGSR)
Address offset: 0x140
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0
r r r r r r r r

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RM0433 DMA request multiplexer (DMAMUX)

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 OF[7:0]: Trigger overrun event flag
The flag is set when a new trigger event occurs on DMA request generator channel x, before
the request counter underrun (the internal request counter programmed via the GNBREQ
field of the DMAMUX_RGxCR register).
The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR
register.

17.6.10 DMAMUX2 request generator interrupt status register

(DMAMUX2_RGSR)
Address offset: 0x140
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0
r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 OF[7:0]: Trigger overrun event flag
The flag is set when a new trigger event occurs on DMA request generator channel x.
The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX2_RGCFR
register.

17.6.11 DMAMUX1 request generator interrupt clear flag register

(DMAMUX1_RGCFR)
Address offset: 0x144
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. COF7 COF6 COF5 COF4 COF3 COF2 COF1 COF0
w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 COF[7:0]: Clear trigger overrun event flag
Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR
register.

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17.6.12 DMAMUX2 request generator interrupt clear flag register

(DMAMUX2_RGCFR)
Address offset: 0x144
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. COF7 COF6 COF5 COF4 COF3 COF2 COF1 COF0
r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 COF[7:0]: Clear trigger overrun event flag
Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX2_RGSR
register.

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RM0433 DMA request multiplexer (DMAMUX)

17.6.13 DMAMUX register map

The following table summarizes the DMAMUX registers and reset values. Refer to the
register boundary address table for the DMAMUX register base address.

Table 131. DMAMUX register map and reset values

Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SYNC_ID

SPOL

SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAMUX_C0CR(1)(2) NBREQ[4:0] DMAREQ_ID[6:0]

SE
0x000 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL
SYNC_ID

SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAMUX_C1CR(1)

SE
NBREQ[4:0] DMAREQ_ID[6:0]
0x004 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL
SYNC_ID

SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAMUX_C2CR(1)

SE
NBREQ[4:0] DMAREQ_ID[6:0]
0x008 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL
SYNC_ID

SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAMUX_C3CR(1) NBREQ[4:0] DMAREQ_ID[6:0]

SE
0x00C [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL
SYNC_ID

SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
(1)

SE
DMAMUX_C4CR NBREQ[4:0] DMAREQ_ID[6:0]
0x010 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID

SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C5CR(1)
SE
NBREQ[4:0] DMAREQ_ID[6:0]
0x014 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID

SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C6CR(1) NBREQ[4:0] DMAREQ_ID[6:0]

SE

0x018 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID

SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

(1)
SE

DMAMUX_C7CR NBREQ[4:0] DMAREQ_ID[6:0]

0x01C [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID
SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

(3)
SE

DMAMUX_C8CR NBREQ[4:0] DMAREQ_ID[6:0]

0x020 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID
SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C9CR(4) NBREQ[4:0] DMAREQ_ID[6:0]

SE

0x024 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID
SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C10CR(3)
SE

NBREQ[4:0] DMAREQ_ID[6:0]
0x028 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID
SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

(3)
SE

DMAMUX_C11CR NBREQ[4:0] DMAREQ_ID[6:0]

0x02C [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID
SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

(3)
SE

DMAMUX_C12CR NBREQ[4:0] DMAREQ_ID[6:0]

0x030 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID
SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C13CR(3)
SE

NBREQ[4:0] DMAREQ_ID[6:0]
0x034 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID
SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C14CR(3)
SE

NBREQ[4:0] DMAREQ_ID[6:0]
0x038 [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SYNC_ID
SOIE
EGE
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

(3)
SE

DMAMUX_C15CR NBREQ[4:0] DMAREQ_ID[6:0]

0x03C [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x040 -
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Reserved
0x07C

RM0433 Rev 8 713/3353

714
 0x144
0x140
0x144
0x140
0x108
0x104
0x100
0x084
0x080

0x10C

0x3FC
0x0FC
Offset

0x148 -
0x088 -

714/3353
Reserved
Reserved

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

DMAMUX_RGSR
DMAMUX_RGSR
DMAMUX_CFR(4)
DMAMUX_CSR(4)

DMAMUX_RG3CR
DMAMUX_RG2CR
DMAMUX_RG1CR

DMAMUX_RGCFR
DMAMUX_RGCFR
DMAMUX_RG0CR(5)
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

1. For DMAMUX2 bits 6:5 are reserved.

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

4. For DMAMUX2 bits 15:8 are reserved.

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
DMA request multiplexer (DMAMUX)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 23

2. For DMAMUX2 bits 28:24 correspond to SYNC_ID[4:0].

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 21

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 20

5. Valid for DMAMUX1. For DMAMUX2 bits 4:0 are for SIG_ID[4:0].
GNBREQ[4:0]
GNBREQ[4:0]
GNBREQ[4:0]
GNBREQ[4:0]

3. Only applies to DMAMUX1. For DMAMUX2 the word is reserved.

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 19

0
0
0
0

Res. Res. Res. Res. Res. GPOL GPOL GPOL GPOL Res. Res. Res. 18

RM0433 Rev 8
[1:0] [1:0] [1:0]

0
0
0
0

Res. Res. Res. Res. Res. [1:0] Res. Res. Res. 17

0
0
0
0

Res. Res. Res. Res. Res. GE GE GE GE Res. Res. Res. 16

0
0
0
0

Res. Res. Res. COF15 OF15 Res. Res. Res. Res. Res. CSOF15 SOF15 15

0
0
0
0

Res. Res. Res. COF14 OF14 Res. Res. Res. Res. Res. CSOF14 SOF14 14

0
0
0
0

Res. Res. Res. COF13 OF13 Res. Res. Res. Res. Res. CSOF13 SOF13 13

0
0
0
0

Res. Res. Res. COF12 OF12 Res. Res. Res. Res. Res. CSOF12 SOF12 12

0
0
0
0

Res. Res. Res. COF11 OF11 Res. Res. Res. Res. Res. CSOF11 SOF11 11
0
0
0
0

Res. Res. Res. 0 COF10 OF10 Res. Res. Res. Res. Res. CSOF10 SOF10 10
0
0
0

Res. Res. Res. COF9 OF9 Res. Res. Res. Res. Res. CSOF9 SOF9 9

Refer to Section 2.3 on page 129 for the register boundary addresses.
0
0
0
0
0
0
0
0

Res. Res. Res. COF8 OF8 OIE OIE OIE OIE Res. CSOF8 SOF8 8
Table 131. DMAMUX register map and reset values (continued)

0
0
0
0

0
0
Res. COF7 OF7 COF7 OF7 Res. Res. Res. Res. Res. CSOF7 SOF7 7
0
0
0
0

0
0

Res. COF6 OF6 COF6 OF6 Res. Res. Res. Res. Res. CSOF6 SOF6 6
0
0
0
0

0
0

Res. COF5 OF5 COF5 OF5 Res. Res. Res. Res. Res. CSOF5 SOF5 5
0
0
0
0

0
0

Res. COF4 OF4 COF4 OF4 Res. Res. Res. Res. Res. CSOF4 SOF4 4
0
0
0
0

0
0

Res. COF3 OF3 COF3 OF3 Res. Res. Res. Res. Res. CSOF3 SOF3 3
0
0
0

0
0
0
0
0
0
0

Res. COF2 OF2 COF2 OF2 Res. CSOF2 SOF2 2

0
0
0

0
0
0
0
0
0
0

Res. COF1 OF1 COF1 OF1 Res. CSOF1 SOF1 1

[2:0]
[2:0]
[2:0]
[2:0]

SIG_ID
SIG_ID
SIG_ID
SIG_ID

0
0
0
0

0
0
0
0
0
0

Res. COF0 OF0 COF0 OF0 Res. CSOF0 SOF0 0

RM0433
RM0433 Chrom-ART Accelerator controller (DMA2D)

18 Chrom-ART Accelerator controller (DMA2D)

18.1 DMA2D introduction

The Chrom-ART Accelerator (DMA2D) is a specialized DMA dedicated to image
manipulation. It can perform the following operations:
• Filling a part or the whole of a destination image with a specific color
• Copying a part or the whole of a source image into a part or the whole of a destination
image
• Copying a part or the whole of a source image into a part or the whole of a destination
image with a pixel format conversion
• Blending a part and/or two complete source images with different pixel format and copy
the result into a part or the whole of a destination image with a different color format
All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with
indexed or direct color mode, including block based YCbCr to handle JPEG decoder output.
The DMA2D has its own dedicated memories for CLUTs (color look-up tables).

18.2 DMA2D main features

The main DMA2D features are:
• Single AXI master bus architecture
• AHB slave programming interface supporting 8-,16-,32-bit accesses (except for CLUT
accesses which are 32-bit)
• User-programmable working area size
• User-programmable offset for sources and destination areas expressed in pixels or
bytes
• User-programmable sources and destination addresses on the whole memory space
• Up to two sources with blending operation
• Alpha value that can be modified (source value, fixed value, or modulated value)
• User programmable source and destination color format
• Up to 12 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct
color coding
• Block based (8x8) YCbCr support with 4:4:4, 4:2:2 and 4:2:0 chroma sub-sampling
factors
• 2 internal memories for CLUT storage in indirect color mode
• Automatic CLUT loading or CLUT programming via the CPU
• User programmable CLUT size
• Internal timer to control AXI bandwidth
• 6 operating modes: register-to-memory, memory-to-memory, memory-to-memory with
pixel format conversion, memory-to-memory with pixel format conversion and blending,
memory-to memory with pixel format conversion, blending and fixed color foreground,
and memory-to memory with pixel format conversion, blending and fixed color
background.
• Area filling with a fixed color

RM0433 Rev 8 715/3353

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Chrom-ART Accelerator controller (DMA2D) RM0433

• Copy from an area to another

• Copy with pixel format conversion between source and destination images
• Copy from two sources with independent color format and blending
• Output buffer byte swapping to support refresh of displays through parallel interface
• Abort and suspend of DMA2D operations
• Watermark interrupt on a user programmable destination line
• Interrupt generation on bus error or access conflict
• Interrupt generation on process completion

18.3 DMA2D functional description

18.3.1 General description

The DMA2D controller performs direct memory transfer. As an AXI master, it can take the
control of the AXI bus matrix to initiate AXI transactions.
The DMA2D can operate in the following modes:
• Register-to-memory
• Memory-to-memory
• Memory-to-memory with pixel format conversion
• Memory-to-memory with pixel format conversion and blending
• Memory-to-memory with pixel format conversion, blending and fixed color foreground
• Memory-to-memory with pixel format conversion, blending and fixed color background
The AHB slave port is used to program the DMA2D controller.
The block diagram of the DMA2D is shown in Figure 87.

716/3353 RM0433 Rev 8

RM0433 Chrom-ART Accelerator controller (DMA2D)

Figure 87. DMA2D block diagram

64-bit
AXI bus

FG PFC
Įmode

Color mode 8-bit Į

Į 32
dma2d_ FG 32 Į 8 X
aclk Expander
FIFO
32 RGB BLENDER OUT PFC
Color
CLUT itf 32 Į Color mode
dma2d_
32
gbl_it Red Converter OUT
256x32-bit FIFO
dma2d_ Green 32/24/16
RAM 32
clut_trg
Blue
dma2d_ BG PFC
Įmode
tc_trg
Color mode 8-bit Į
dma2d_ Į 32
BG 32 Į 8 X
tw_trg FIFO
Expander
32 RGB

CLUT itf

256x32-bit
RAM
32-bit
AHB bus

MS40430V2

18.3.2 DMA2D internal signals

The table below lists the DMA2D internal signals.

Table 132. DMA2D internal input/output signals

Signal name Signal type Description

dma2d_aclk Input 64-bit AXI bus clock

dma2d_gbl_it Output DMA2D global interrupt
dma2d_clut_trg Output CLUT transfer complete (to MDMA)
dma2d_tc_trg Output Transfer complete (to MDMA)
dma2d_tw_trg Output Transfer watermark (to MDMA)

18.3.3 DMA2D control

The DMA2D controller is configured through DMA2D_CR. The user application can perform
the following operations:
• Select the operating mode.
• Enable/disable the DMA2D interrupt.
• Start/suspend/abort ongoing data transfers.

RM0433 Rev 8 717/3353

748
Chrom-ART Accelerator controller (DMA2D) RM0433

18.3.4 DMA2D foreground and background FIFOs

The DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to
be copied and/or processed.
The FIFOs fetch the pixels according to the color format defined in their respective pixel
format converter (PFC).
They are programmed through the following control registers:
• DMA2D foreground memory address register (DMA2D_FGMAR)
• DMA2D foreground offset register (DMA2D_FGOR)
• DMA2D background memory address register (DMA2D_BGMAR)
• DMA2D background offset register (DMA2D_BGBOR)
• DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)
When the DMA2D operates in register-to-memory mode, none of the FIFOs is activated.
When the DMA2D operates in memory-to-memory mode (no pixel format conversion nor
blending operation), only the FG FIFO is activated, and acts as a buffer.
When the DMA2D operates in memory-to-memory operation with pixel format conversion
(no blending operation), the BG FIFO is not activated.

18.3.5 DMA2D foreground and background PFC

DMA2D foreground pixel format converter (PFC) and background pixel format converter
perform the pixel format conversion to generate a 32-bit per pixel value. The PFC can also
modify the alpha channel.
The first PFC stage converts the color format. The original color format of the foreground
and background pixels are configured through CM[3:0] in DMA2D_FGPFCCR and
DMA2D_BGPFCCR, respectively.
The supported input formats are given in the table below.

Table 133. Supported color mode in input

CM[3:0] Color mode

0000 ARGB8888
0001 RGB888
0010 RGB565
0011 ARGB1555
0100 ARGB4444
0101 L8
0110 AL44
0111 AL88
1000 L4
1001 A8
1010 A4
1011 YCbCr (only for foreground)

718/3353 RM0433 Rev 8

RM0433 Chrom-ART Accelerator controller (DMA2D)

The color format are coded as follows:

• Alpha value field: transparency
0xFF value corresponds to an opaque pixel and 0x00 to a transparent one.
• R field for Red
• G field for Green
• B field for Blue
• L field: luminance
This field is the index to a CLUT to retrieve the three/four RGB/ARGB components.
If the original format was direct color mode (ARGB/RGB), the extension to 8-bit per channel
is performed by copying the MSBs into the LSBs. This ensures a perfect linearity of the
conversion.
If the original format does not include an alpha channel, the alpha value is automatically
set to 0xFF (opaque).
If the original format is indirect color mode (L/AL), a CLUT is required, and each pixel format
converter is associated with a 256 entry 32-bit CLUT.
For the specific alpha mode A4 and A8, no color information is stored nor indexed. The color
to be used for the image generation is fixed and defined in DMA2D_FGCOLR for foreground
pixels, and in DMA2D_BGCOLR for background pixels.
The order of the fields in the system memory is defined in the table below.

Table 134. Data order in memory

Color mode @+3 @+2 @+1 @+0

ARGB8888 A0[7:0] R0[7:0] G0[7:0] B0[7:0]

B1[7:0] R0[7:0] G0[7:0] B0[7:0]
RGB888 G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]
RGB565 R1[4:0]G1[5:3] G1[2:0]B1[4:0] R0[4:0]G0[5:3] G0[2:0]B0[4:0]
ARGB1555 A1[0]R1[4:0]G1[4:3] G1[2:0]B1[4:0] A0[0]R0[4:0]G0[4:3] G0[2:0]B0[4:0]
ARGB4444 A1[3:0]R1[3:0] G1[3:0]B1[3:0] A0[3:0]R0[3:0] G0[3:0]B0[3:0]
L8 L3[7:0] L2[7:0] L1[7:0] L0[7:0]
AL44 A3[3:0]L3[3:0] A2[3:0]L2[3:0] A1[3:0]L1[3:0] A0[3:0]L0[3:0]
AL88 A1[7:0] L1[7:0] A0[7:0] L0[7:0]
L4 L7[3:0]L6[3:0] L5[3:0]L4[3:0] L3[3:0]L2[3:0] L1[3:0]L0[3:0]
A8 A3[7:0] A2[7:0] A1[7:0] A0[7:0]
A4 A7[3:0]A6[3:0] A5[3:0]A4[3:0] A3[3:0]A2[3:0] A1[3:0]A0[3:0]

The 24-bit RGB888 aligned on 32-bit is supported through the ARGB8888 mode.
Once the 32-bit value is generated, the alpha channel can be modified according to AM[1:0]
in DMA2D_FGPFCCR or DMA2D_BGPFCCR, as shown in Table 135.

RM0433 Rev 8 719/3353

748
Chrom-ART Accelerator controller (DMA2D) RM0433

One of the following happens for the alpha channel:

• It is kept as it is (no modification).
• It is replaced by ALPHA[7:0] value i nDMA2D_FGPFCCR/DMA2D_BGPFCCR.
• It is replaced by the original alpha value multiplied by ALPHA[7:0] in
DMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255.

Table 135. Alpha mode configuration

AM[1:0] Alpha mode

00 No modification
01 Replaced by value in DMA2D_xxPFCCR
10 Replaced by original value multiplied by the value in DMA2D_xxPFCCR / 255
11 Reserved

Note: To support the alternate format, the incoming alpha value can be inverted setting AI in
DMA2D_FGPFCCR or DMA2D_BGPFCCR. This applies also to the Alpha value stored in
the DMA2D_FGPFCCR or DMA2D_BGPFCCR, and in the CLUT.
The R and B fields can also be swapped setting RBS in DMA2D_FGPFCCR or
DMA2D_BGPFCCR. This applies also to the RGB order used in the CLUT, and in
DMA2D_FGCOLR or DMA2D_BGCOLR.

18.3.6 DMA2D foreground and background CLUT interface

The CLUT interface manages the CLUT memory access and the automatic loading of
the CLUT.
Three kinds of accesses are possible:
• CLUT read by the PFC during pixel format conversion operation
• CLUT accessed through the AHB slave port when the CPU is reading or writing data
into the CLUT
• CLUT written through the AXI master port when an automatic loading of the CLUT
is performed
The CLUT memory loading can be done in two different ways:
• Automatic loading
The following sequence must be followed to load the CLUT:
a) Program the CLUT address into DMA2D_FGCMAR (foreground CLUT) or
DMA2D_BGCMAR (background CLUT).
b) Program the CLUT size with CS[7:0] field in DMA2D_FGPFCCR (foreground
CLUT), or DMA2D_BGPFCCR (background CLUT).
c) Set START in DMA2D_FGPFCCR (foreground CLUT) or DMA2D_BGPFCCR
(background CLUT) to start the transfer. During this automatic loading process,
the CLUT is not accessible by the CPU. If a conflict occurs, a CLUT access error
interrupt is raised assuming CAEIE = 1 in DMA2D_CR.
• Manual loading
The application has to program the CLUT manually through the DMA2D AHB slave
port to which the local CLUT memory is mapped.The foreground CLUT (FGCLUT)

720/3353 RM0433 Rev 8

RM0433 Chrom-ART Accelerator controller (DMA2D)

is located at address offset 0x0400 and the background CLUT (BGCLUT) at address
offset 0x0800.
The CLUT format can be 24 or 32 bits. It is configured through CCM in DMA2D_FGPFCCR
(foreground CLUT) or DMA2D_BGPFCCR (background CLUT) as shown in table below.

Table 136. Supported CLUT color mode

CCM CLUT color mode

0 32-bit ARGB8888
1 24-bit RGB888

The way the CLUT data are organized in the system memory is specified in the table below.

Table 137. CLUT data order in memory

CLUT Color mode @+3 @+2 @+1 @+0

ARGB8888 A0[7:0] R0[7:0] G0[7:0] B0[7:0]

B1[7:0] R0[7:0] G0[7:0] B0[7:0]
RGB888 G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]

18.3.7 DMA2D blender

The DMA2D blender blends the source pixels by pair to compute the resulting pixel.
The blending is performed according to the following equation:
αFG . αBG
with αMult =
255

αOUT = αFG + αBG - αMult

CFG.αFG + CBG.αBG - CBG.αMult

COUT = with C = R or G or B
αOUT

Division is rounded to the nearest lower integer

No configuration register is required by the blender. The blender use depends on the
DMA2D operating mode defined by MODE[2:0] in DMA2D_CR.

18.3.8 DMA2D output PFC

The output PFC performs the pixel format conversion from 32 bits to the output format
defined by CM[2:0] in DMA2D_OPFCCR.

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Supported output formats are given in the table below

Table 138. Supported color mode in output

CM[2:0] Color mode

000 ARGB8888
001 RGB888
010 RGB565
011 ARGB1555
100 ARGB4444

Note: To support the alternate format, the calculated alpha value can be inverted setting AI bit in
DMA2D_OPFCCR. This applies also to the Alpha value used in DMA2D_OCOLR.
The R and B fields can also be swapped setting RBS in DMA2D_OPFCCR. This applies
also to the RGB order used in DMA2D_OCOLR.

18.3.9 DMA2D output FIFO

The output FIFO programs the pixels according to the color format defined in the output
PFC.
The destination area is defined through the following registers:
• DMA2D output memory address register (DMA2D_OMAR)
• DMA2D output offset register (DMA2D_OOR)
• DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)
If the DMA2D operates in register-to-memory mode, the configured output rectangle is filled
by the color specified in DMA2D_OCOLR which contains a fixed 32-, 24-, or 16-bit value.
The format is selected by CM[2:0] in DMA2D_OPFCCR.
The data are stored into the memory in the order defined in the table below.

Table 139. Data order in memory

Color mode @+3 @+2 @+1 @+0

ARGB8888 A0[7:0] R0[7:0] G0[7:0] B0[7:0]

B1[7:0] R0[7:0] G0[7:0] B0[7:0]
RGB888 G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]
RGB565 R1[4:0]G1[5:3] G1[2:0]B1[4:0] R0[4:0]G0[5:3] G0[2:0]B0[4:0]
ARGB1555 A1[0]R1[4:0]G1[4:3] G1[2:0]B1[4:0] A0[0]R0[4:0]G0[4:3] G0[2:0]B0[4:0]
ARGB4444 A1[3:0]R1[3:0] G1[3:0]B1[3:0] A0[3:0]R0[3:0] G0[3:0]B0[3:0]

The RGB888 aligned on 32 bits is supported through the ARGB8888 mode.

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18.3.10 DMA2D output FIFO byte reordering

The output FIFO bytes can be reordered to support display frame buffer update through a
parallel interface (F(S)MC) directly from the DMA2D.
The reordering of bytes can be done using:
• RBS bit to swap red and blue component
• SB bit to swap byte two by two in the output FIFO
When the byte swapping is activated (SB = 1 in DMA2D_OPFCR), the number of pixel per
line (PL field in DMA2D_NLR) must be even, and the output memory address (MA field
in DMA2D_OMAR) must be even. The output line offset computed in bytes (resulting from
LOM field in DMA2D_CR and LO field in DMA2D_OOR values) must also be even. If not a
configuration error is detected.

Table 140. Standard data order in memory

Color Mode @+3 @+2 @+1 @+0

B1[7:0] R0[7:0] G0[7:0] B0[7:0]

RGB888 G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]
RGB565 R1[4:0]G1[5:3] G1[2:0]B1[4:0] R0[4:0]G0[5:3] G0[2:0]B0[4:0]

16-bit mode (RGB565)

This mode is supported without byte reordering by the DMA2D.

Figure 88. Intel 8080 16-bit mode (RGB565)

16-bit Data

Data Bus D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Colors R4 R3 R2 R1 R0 G5 B4
G5 G4 G3 G2 G1 G0 B3 B2 B1 B0

64K colors

MSv42078V2

18/24-bit mode (RGB888)

This mode needs data reordering:
1. The red and the blue have to be swapped (setting the RBS bit).
2. MSB and the LSB bytes of an half-word must be swapped (setting SB bit).

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Figure 89. Intel 8080 18/24-bit mode (RGB888)

Transfer
1 2
Order
16-bit Data 16-bit Data

Data Bus D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Colors R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 R7 R6 R5 R4 R3 R2 R1 R0

16.7M colors
1st pixel 2nd pixel

MSv42079V2

Table 141. Output FIFO byte reordering steps

Steps @+3 @+2 @+1 @+0

B1[7:0] R0[7:0] G0[7:0] B0[7:0]

Original data ordering G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]
Setting the RBS bit
R1[7:0] B0[7:0] G0[7:0] R0[7:0]
Data ordering after Red and Blue
G2[7:0] R2[7:0] B1[7:0] G1[7:0]
swap (RBS set)
B3[7:0] G3[7:0] R3[7:0] B2[7:0]
Setting the SB bit
B0[7:0] R1[7:0] R0[7:0] G0[7:0]
Data ordering after byte swapping
R2[7:0] G2[7:0] G1[7:0] B1[7:0]
(SB set)
G3[7:0] B3[7:0] B2[7:0] R3[7:0]

18.3.11 DMA2D AXI master port timer

An 8-bit timer is embedded into the AXI master port to provide an optional limitation of the
bandwidth on the crossbar. This timer is clocked by the AXI clock and counts a dead time
between two consecutive accesses. This limits the bandwidth usage.
The timer enabling and dead time value are configured through DMA2D_AMPTCR.

18.3.12 DMA2D transactions

DMA2D transactions consist of a sequence of a given number of data transfers. Number of
data and width can be programmed by software.
Each DMA2D data transfer is composed of up to four steps:
1. Data loading from the memory location pointed by DMA2D_FGMAR and pixel format
conversion as defined in DMA2D_FGCR
2. Data loading from a memory location pointed by DMA2D_BGMAR and pixel format
conversion as defined in DMA2D_BGCR

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3. Blending of all retrieved pixels according to the alpha channels resulting of PFC
operation on alpha values
4. Pixel format conversion of resulting pixels according to DMA2D_OCR and
programming of data to the memory location addressed through DMA2D_OMAR

18.3.13 DMA2D configuration

Both source and destination data transfers can target peripherals and memories in the
whole 4-Gbyte memory area, at addresses ranging between 0x0000 0000 and
0xFFFF FFFF.
The DMA2D can operate in any of the following modes selected through MODE[2:0]
in DMA2D_CR:
• Register-to-memory
• Memory-to-memory
• Memory-to-memory with PFC
• Memory-to-memory with PFC and blending
• Memory-to-memory with PFC, blending and fixed FG color
• Memory-to-memory with PFC, blending and fixed BG color

Register-to-memory
The register-to-memory mode is used to fill a user defined area with a predefined color.
The color format is set in DMA2D_OPFCCR.
The DMA2D does not perform any data fetching from any source. It just writes the color
defined in DMA2D_OCOLR to the area located at the address pointed by DMA2D_OMAR
and defined in DMA2D_NLR and DMA2D_OOR.

Memory-to-memory
In memory-to-memory mode, the DMA2D does not perform any graphical data
transformation. The foreground input FIFO acts as a buffer, and data are transferred from
the source memory location defined in DMA2D_FGMAR, to the destination memory location
pointed by DMA2D_OMAR.
The color mode programmed by CM[3:0] in DMA2D_FGPFCCR defines the number of bits
per pixel for both input and output.
The size of the area to be transferred is defined by DMA2D_NLR and DMA2D_FGOR for
the source, and by DMA2D_NLR and DMA2D_OOR for the destination.

Memory-to-memory with PFC

In this mode, the DMA2D performs a pixel format conversion of the source data, and stores
them in the destination memory location.
The size of the areas to be transferred are defined by DMA2D_NLR and DMA2D_FGOR for
the source, and by DMA2D_NLR and DMA2D_OOR for the destination.
Data are fetched from the location defined in DMA2D_FGMAR, and processed by the
foreground PFC. The original pixel format is configured through DMA2D_FGPFCCR.
If the original pixel format is direct-color mode, the color channels are all expanded to 8 bits.

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If the pixel format is indirect color mode, the associated CLUT has to be loaded into the
CLUT memory.
The CLUT loading can be done automatically by following the sequence below:
1. Set the CLUT address into DMA2D_FGCMAR.
2. Set the CLUT size with CS[7:0] in DMA2D_FGPFCCR.
3. Set the CLUT format (24 or 32 bits) with CCM in DMA2D_FGPFCCR.
4. Start the CLUT loading by setting START in DMA2D_FGPFCCR.
Once the CLUT loading is complete, CTCIF flag in DMA2D_IFR is raised, and an interrupt is
generated if CTCIE is set in DMA2D_CR. The automatic CLUT loading process cannot work
in parallel with classical DMA2D transfers.
The CLUT can also be filled by the CPU or by any other master through the AHB port.
The access to the CLUT is not possible when a DMA2D transfer is ongoing, and uses the
CLUT (indirect color format).
In parallel to the color conversion process, the alpha value can be added or changed
depending on the value programmed in DMA2D_FGPFCCR. If the original image does not
have an alpha channel, a default alpha value of 0xFF is automatically added to obtain a fully
opaque pixel.
The alpha value is modified as follows according to AM[1:0] in DMA2D_FGPFCCR:
• It is unchanged.
• It is replaced by ALPHA[7:0] value in DMA2D_FGPFCCR.
• It is replaced by the original value multiplied by ALPHA[7:0] value in
DMA2D_FGPFCCR divided by 255.
The resulting 32-bit data are encoded by the output PFC into the format specified by
CM[2:0] in DMA2D_OPFCCR. The output pixel format cannot be the indirect mode since no
CLUT generation process is supported.
Processed data are written into destination memory location pointed by DMA2D_OMAR.

Memory-to-memory with PFC and blending

In this mode, two sources are fetched in the foreground and background FIFOs from the
memory locations defined by DMA2D_FGMAR and DMA2D_BGMAR respectively.
The two pixel format converters have to be configured as described in memory-to-memory
mode. Their configurations can be different as each pixel format converter is independent
and has its own CLUT memory.

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Once each pixel has been converted into 32 bits by its respective PFC, all pixels are
blended according to the equation below:
αFG . αBG
with αMult =
255

αOUT = αFG + αBG - αMult

CFG.αFG + CBG.αBG - CBG.αMult

COUT = with C = R or G or B
αOUT

Division are rounded to the nearest lower integer

The resulting 32-bit pixel value is encoded by the output PFC according to the specified
output format, and data are written into the destination memory location pointed
by DMA2D_OMAR.

Memory-to-memory with PFC, blending and fixed color FG

In this mode, only one source is fetched in the background FIFO from the memory location
defined by DMA2D_BGMAR.
The value of the foreground color is given by DMA2D_FGCOLR, and the alpha value is set
to 0xFF (opaque).
The alpha value can be replaced or modified according to AM[1:0] and ALPHA[7:0]
in DMA2D_FGPFCCR.
The two pixel format converters have to be configured as described in memory-to-memory
mode. Their configurations can be different as each pixel format converter is independent
and has its own CLUT memory
Once each pixel has been converted into 32 bits by its respective PFC, all pixels are
blended together. The resulting 32-bit pixel value is encoded by the output PFC according to
the specified output format. Data are written into the destination memory location pointed
by DMA2D_OMAR.

Memory-to-memory with PFC, blending and fixed color BG

In this mode, only open source is fetched in the foreground FIFO from the memory location
defined by DMA2D_FGMAR.
The value of the background color is given by DMA2D_BGCOLR, and the alpha value is set
to 0xFF (opaque).
The alpha value can be replaced or modified according to AM[1:0] and ALPHA[7:0]
in DMA2D_BGPFCCR.
The two pixel format converters have to be configured as described in memory-to-memory
mode. Their configurations can be different as each pixel format converter is independent
and has its own CLUT memory
Once each pixel has been converted into 32 bits by their respective PFCs, all pixels are
blended together. The resulting 32-bit pixel value is encoded by the output PFC according to
the specified output format. Data are written into the destination memory location pointed
by DMA2D_OMAR.

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Configuration error detection

The DMA2D checks that the configuration is correct before any transfer. The configuration
error interrupt flag is set by hardware when a wrong configuration is detected when a new
transfer/automatic loading starts. An interrupt is then generated if CEIE = 1 in DMA2D_CR.
The wrong configurations that can be detected are listed below:
• Foreground CLUT automatic loading: MA bits in DMA2D_FGCMAR are not aligned
with CCM in DMA2D_FGPFCCR.
• Background CLUT automatic loading: MA bits in DMA2D_BGCMAR are not aligned
with CCM in DMA2D_BGPFCCR.
• Memory transfer (except in register-to-memory and memory-to-memory with blending
and fixed color FG): MA bits in DMA2D_FGMAR are not aligned with CM
in DMA2D_FGPFCCR.
• Memory transfer (except in register-to-memory and memory-to-memory with blending
and fixed color FG): CM bits in DMA2D_FGPFCCR are invalid.
• Memory transfer (except in register-to-memory and memory-to-memory with blending
and fixed color FG): PL bits in DMA2D_NLR are odd while CM is DMA2D_FGPFCCR
is A4 or L4.
• Memory transfer (except in register-to-memory and memory-to-memory with blending
and fixed color FG): LO bits in DMA2D_FGOR are odd while CM in
DMA2D_FGPFCCR is A4 or L4, and LOM in DMA2D_CR is pixel mode.
• Memory transfer (only in blending mode, except in memory-to-memory with blending
and fixed color FG): MA bits in DMA2D_BGMAR are not aligned with the CM
in DMA2D_BGPFCCR
• Memory transfer (only in blending and blending with fixed color FG): CM bits
in DMA2D_BGPFCCR are invalid.
• Memory transfer (only in blending and blending with fixed color FG mode): PL bits
in DMA2D_NLR odd while CM inDMA2D_BGPFCCR is A4 or L4.
• Memory transfer (only in blending and blending with fixed color FG): LO bits in
DMA2D_BGOR are odd while CM inDMA2D_BGPFCCR is A4 or L4, and LOM
in DMA2D_CR is pixel mode.
• Memory transfer (except in memory-to-memory): MA bits in DMA2D_OMAR are not
aligned with CM in DMA2D_OPFCCR.
• Memory transfer (except in memory-to-memory): CM bits in DMA2D_OPFCCR
are invalid.
• Memory transfer with byte swapping: PL bits in DMA2D_NLR are odd, or MA bits in
DMA2D_OMAR are odd, or LO in bytes (resulting from LOM in DMA2D_CR and LO in
DMA2D_OOR) are odd while SB = 1 in DMA2D_OPFCCR.
• Memory transfer: NL bits in DMA2D_NLR are all zeros.
• Memory transfer: PL bits in DMA2D_NLR are all zeros.
• Memory transfer: MODE bits in DMA2D_CR are invalid.
• YCbCr format: when a CLUT loading starts setting START in DMA2D_FGPFCCR
• YCbCr format: when memory-to-memory mode is selected
• YCbCr format: when YCbCR4:4:4 is selected, and the sum of number of pixel (PL) and
line offset LO is not a multiple of 8 pixels
• YCbCr format: when YCbCr4:2:2 or YCbCr4:2:0 is selected, and the sum of number of
pixel (PL) and line offset LO is not a multiple of 16 pixels

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18.3.14 YCbCr support

The DMA2D foreground plane can support 8x8 block-based YCbCr as output by the
JPEG decoder with different chroma subsampling factors.
The memory organization follows the standard JFIF rules:
• Each of the three color components must be coded on 8-bit.
• Each component must be arranged by blocks of 8x8 (64 bytes) called MCU.
Depending of the chroma subsampling factor, the MCU must be arranged in the memory as
described in the table below.

Table 142. MCU order in memory

Sub-sampling @ @ + 64 @ + 128 @+192 @+256 @ + 320

4:4:4 Y1 Cb1 Cr1 Y2 Cb2 Cr2

4:2:2 Y1 Y2 Cb12 Cr12 Y3 Y4
4:2:0 Y1 Y2 Y3 Y4 Cb1234 Cr1234

The chroma subsampling factor is configured through CSS in DMA2D_FGPFCCR.

Once the DMA2D has started with the foreground configured in YCbCr color mode, the first
two chroma MCUs are loaded in the foreground CLUT. Once the chroma MCUs are loaded,
the DMA2D performs the loading of the Y MCU as for a classical color mode.

18.3.15 DMA2D transfer control (start, suspend, abort, and completion)

Once the DMA2D is configured, the transfer can be launched by setting START
in DMA2D_CR. Once the transfer is completed, START is automatically reset, and TCIF flag
is raised in DMA2D_ISR. An interrupt can be generated if TCIE is set in DMA2D_CR.
The user application can suspend the DMA2D at any time by setting SUSP in DMA2D_CR.
The transaction can be aborted by setting ABORT i nDMA2D_CR, or can be restarted by
resetting SUSP in DMA2D_CR.
The user application can abort at any time an ongoing transaction by setting ABORT
in DMA2D_CR. In this case, the TCIF flag is not raised.
Automatic CLUT transfers can also be aborted or suspended by using their own START bits
in DMA2D_FGPFCCR and DMA2D_BGPFCCR.

18.3.16 Watermark
A watermark can be programmed to generate an interrupt when the last pixel of a given line
has been written to the destination memory area.
The line number is defined in LW[15:0] in DMA2D_LWR.
When the last pixel of this line has been transferred, TWIF flag is raised in DMA2D_ISR,
and an interrupt is generated if TWIE is set in DMA2D_CR.

18.3.17 Error management

Two kind of errors can be triggered:
• AXI master port errors signaled by TEIF flag in DMA2D_ISR

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• Conflicts caused by CLUT access (CPU trying to access the CLUT while a CLUT
loading or a DMA2D transfer is ongoing) signaled by CAEIF flag in DMA2D_ISR
Both flags are associated to their own interrupt enable flag in DMA2D_CR to generate an
interrupt if need be (TEIE and CAEIE).

18.3.18 AXI dead time

To limit the AXI bandwidth use, a dead time between two consecutive AXI accesses can be
programmed. This feature can be enabled by setting EN in DMA2D_AMTCR.
The dead-time value is stored in DT[7:0] in DMA2D_AMTCR. This value represents the
guaranteed minimum number of cycles between two consecutive transactions on AXI bus.
The update of the dead-time value while the DMA2D is running is taken into account for the
next AXI transfer.

18.4 DMA2D interrupts

An interrupt can be generated on the following events:
• Configuration error
• CLUT transfer complete
• CLUT access error
• Transfer watermark reached
• Transfer complete
• Transfer error
Separate interrupt enable bits are available for flexibility.

Table 143. DMA2D interrupt requests

Interrupt event Event flag Enable control bit

Configuration error CEIF CEIE

CLUT transfer complete CTCIF CTCIE
CLUT access error CAEIF CAEIE
Transfer watermark TWF TWIE
Transfer complete TCIF TCIE
Transfer error TEIF TEIE

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18.5 DMA2D registers

18.5.1 DMA2D control register (DMA2D_CR)

Address offset: 0x000
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE[2:0]
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. CEIE CTCIE CAEIE TWIE TCIE TEIE Res. LOM Res. Res. Res. ABORT SUSP START
rw rw rw rw rw rw rw rs rw rs

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 MODE[2:0]: DMA2D mode
This bit is set and cleared by software. It cannot be modified while a transfer is ongoing.
000: Memory-to-memory (FG fetch only)
001: Memory-to-memory with PFC (FG fetch only with FG PFC active)
010: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
011: Register-to-memory (no FG nor BG, only output stage active)
100: Memory-to-memory with blending and fixed color FG (BG fetch only with FG and
BG PFC active)
101: Memory-to-memory with blending and fixed color BG (FG fetch only with FG and
BG PFC active)
Others: Reserved
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 CEIE: Configuration error (CE) interrupt enable
This bit is set and cleared by software.
0: CE interrupt disabled
1: CE interrupt enabled
Bit 12 CTCIE: CLUT transfer complete (CTC) interrupt enable
This bit is set and cleared by software.
0: CTC interrupt disabled
1: CTC interrupt enabled
Bit 11 CAEIE: CLUT access error (CAE) interrupt enable
This bit is set and cleared by software.
0: CAE interrupt disabled
1: CAE interrupt enabled
Bit 10 TWIE: Transfer watermark (TW) interrupt enable
This bit is set and cleared by software.
0: TW interrupt disabled
1: TW interrupt enabled
Bit 9 TCIE: Transfer complete (TC) interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled

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Bit 8 TEIE: Transfer error (TE) interrupt enable

This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 7 Reserved, must be kept at reset value.
Bit 6 LOM: Line offset mode
This bit configures how the line offset is expressed (pixels or bytes) for the foreground,
background and output.
This bit is set and cleared by software. It can not be modified while a transfer is ongoing.
0: Line offsets expressed in pixels
1: Line offsets expressed in bytes
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 ABORT: Abort
This bit can be used to abort the current transfer. This bit is set by software, and
is automatically reset by hardware when START = 0.
0: No transfer abort requested
1: Transfer abort requested
Bit 1 SUSP: Suspend
This bit can be used to suspend the current transfer. This bit is set and reset by software.
It is automatically reset by hardware when START = 0.
0: Transfer not suspended
1: Transfer suspended
Bit 0 START: Start
This bit can be used to launch the DMA2D according to parameters loaded in the various
configuration registers. This bit is automatically reset by the following events:
– at the end of the transfer
– when the data transfer is aborted by the user by setting ABORT in this register
– when a data transfer error occurs
– when the data transfer has not started due to a configuration error, or another
transfer operation already ongoing (automatic CLUT loading)

18.5.2 DMA2D interrupt status register (DMA2D_ISR)

Address offset: 0x004
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CEIF CTCIF CAEIF TWIF TCIF TEIF
r r r r r r

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Bits 31:6 Reserved, must be kept at reset value.

Bit 5 CEIF: Configuration error interrupt flag
This bit is set when START is set in DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR,
and a wrong configuration has been programmed.
Bit 4 CTCIF: CLUT transfer complete interrupt flag
This bit is set when the CLUT copy from a system memory area to the internal DMA2D
memory is complete.
Bit 3 CAEIF: CLUT access error interrupt flag
This bit is set when the CPU accesses the CLUT while the CLUT is being automatically
copied from a system memory to the internal DMA2D.
Bit 2 TWIF: Transfer watermark interrupt flag
This bit is set when the last pixel of the watermarked line has been transferred.
Bit 1 TCIF: Transfer complete interrupt flag
This bit is set when a DMA2D transfer operation is complete (data transfer only).
Bit 0 TEIF: Transfer error interrupt flag
This bit is set when an error occurs during a DMA transfer (data transfer or automatic
CLUT loading).

18.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR)

Address offset: 0x008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCTCI CAECI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CCEIF CTWIF CTCIF CTEIF
F F
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 CCEIF: Clear configuration error interrupt flag
Programming this bit to 1 clears the CEIF flag in DMA2D_ISR.
Bit 4 CCTCIF: Clear CLUT transfer complete interrupt flag
Programming this bit to 1 clears the CTCIF flag in DMA2D_ISR.
Bit 3 CAECIF: Clear CLUT access error interrupt flag
Programming this bit to 1 clears the CAEIF flag in DMA2D_ISR.
Bit 2 CTWIF: Clear transfer watermark interrupt flag
Programming this bit to 1 clears the TWIF flag in DMA2D_ISR.
Bit 1 CTCIF: Clear transfer complete interrupt flag
Programming this bit to 1 clears the TCIF flag in DMA2D_ISR.
Bit 0 CTEIF: Clear transfer error interrupt flag
Programming this bit to 1 clears the TEIF flag in DMA2D_ISR.

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18.5.4 DMA2D foreground memory address register (DMA2D_FGMAR)

Address offset: 0x00C
Reset value: 0x0000 0000
This register can only be written when data transfers are disabled. Once the data transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: Memory address, address of the data used for the foreground image
The address alignment must match the image format selected: a 32-bit per pixel format must
be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned, and a 4-bit per pixel format
must be 8-bit aligned.

18.5.5 DMA2D foreground offset register (DMA2D_FGOR)

Address offset: 0x010
Reset value: 0x0000 0000
This register can only be written when data transfers are disabled. Once the data transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LO[15:0]: Line offset
This field gives the line offset used for the foreground image, expressed:
– in pixels when LOM = 0 in DMA2D_CR. Only LO[13:0] bits are considered,
LO[15:14] bits are ignored.
– in bytes when LOM = 1
This value is used for the address generation. It is added at the end of each line to determine
the starting address of the next line.
If the image format is 4-bit per pixel, the line offset must be even.

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RM0433 Chrom-ART Accelerator controller (DMA2D)

18.5.6 DMA2D background memory address register (DMA2D_BGMAR)

Address offset: 0x014
Reset value: 0x0000 0000
This register can only be written when data transfers are disabled. Once the data transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: Memory address, address of the data used for the background image
The address alignment must match the image format selected: a 32-bit per pixel format must
be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format
must be 8-bit aligned.

18.5.7 DMA2D background offset register (DMA2D_BGOR)

Address offset: 0x018
Reset value: 0x0000 0000
This register can only be written when data transfers are disabled. Once the data transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LO[15:0]: Line offset
This field gives the line offset used for the background image, expressed:
– in pixels when LOM = 0 in DMA2D_CR. Only LO[13:0] bits are considered,
LO[15:14] bits are ignored.
– in bytes when LOM = 1
This value is used for the address generation. It is added at the end of each line to determine
the starting address of the next line.
If the image format is 4-bit per pixel, the line offset must be even.

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18.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR)

Address offset: 0x01C
Reset value: 0x0000 0000
This register can only be written when data transfers are disabled. Once the data transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA[7:0] Res. Res. RBS AI CSS[1:0] AM[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS[7:0] Res. Res. START CCM CM[3:0]
rw rw rw rw rw rw rw rw rc_w1 rw rw rw rw rw

Bits 31:24 ALPHA[7:0]: Alpha value

These bits define a fixed alpha channel value which can replace the original alpha value, or
be multiplied by the original alpha value, according to the alpha mode selected through
AM[1:0] in this register.
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 RBS: Red/Blue swap
This bit allows to swap Red and Blue to support BGR or ABGR color formats.
0: Regular mode (RGB or ARGB)
1: Swap mode (BGR or ABGR)
Bit 20 AI: Alpha inverted
This bit inverts the alpha value.
0: Regular alpha
1: Inverted alpha
Bits 19:18 CSS[1:0]: Chroma subsampling
These bits define the chroma subsampling mode for YCbCr color mode.
00: 4:4:4 (no chroma subsampling)
01: 4:2:2
10: 4:2:0
Others: Reserved
Bits 17:16 AM[1:0]: Alpha mode
These bits select the alpha channel value to be used for the foreground image.
00: No modification of the foreground image alpha channel value
01: Replace original foreground image alpha channel value by ALPHA[7: 0]
10: Replace original foreground image alpha channel value by ALPHA[7:0] multiplied with
original alpha channel value
Others: Reserved
Bits 15:8 CS[7:0]: CLUT size
These bits define the size of the CLUT used for the foreground image.
The number of CLUT entries is equal to CS[7:0] + 1.
Bits 7:6 Reserved, must be kept at reset value.

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RM0433 Chrom-ART Accelerator controller (DMA2D)

Bit 5 START: Start

This bit can be set to start the automatic loading of the CLUT. It is automatically reset:
– at the end of the transfer
– when the transfer is aborted by the user by setting ABORT in DMA2D_CR
– when a transfer error occurs
– when the transfer has not started due to a configuration error or another transfer
operation already ongoing (data transfer or automatic background CLUT transfer)
Bit 4 CCM: CLUT color mode
This bit defines the color format of the CLUT.
0: ARGB8888
1: RGB888
Bits 3:0 CM[3:0]: Color mode
These bits defines the color format of the foreground image.
0000: ARGB8888
0001: RGB888
0010: RGB565
0011: ARGB1555
0100: ARGB4444
0101: L8
0110: AL44
0111: AL88
1000: L4
1001: A8
1010: A4
1011: YCbCr
Others: Reserved

18.5.9 DMA2D foreground color register (DMA2D_FGCOLR)

Address offset: 0x020
Reset value: 0x0000 0000
This register can only be written when data transfers are disabled. Once the data transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. RED[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN[7:0] BLUE[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 RED[7:0]: Red value for the A4 or A8 mode of the foreground image
Used also for fixed color FG in memory-to-memory mode with blending and fixed color FG
(BG fetch only with FG and BG PFC active).
Bits 15:8 GREEN[7:0]: Green value for the A4 or A8 mode of the foreground image
Used also for fixed color FG in memory-to-memory mode with blending and fixed color FG
(BG fetch only with FG and BG PFC active).

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Bits 7:0 BLUE[7:0]: Blue value for the A4 or A8 mode of the foreground image
Used also for fixed color FG in memory-to-memory mode with blending and fixed color FG
(BG fetch only with FG and BG PFC active).

18.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR)

Address offset: 0x024
Reset value: 0x0000 0000
This register can only be written when data transfers are disabled. Once the data transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA[7:0] Res. Res. RBS AI Res. Res. AM[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS[7:0] Res. Res. START CCM CM[3:0]
rw rw rw rw rw rw rw rw rc_w1 rw rw rw rw rw

Bits 31:24 ALPHA[7:0]: Alpha value

These bits define a fixed alpha channel value which can replace the original alpha value, or
be multiplied with the original alpha value according to the alpha mode selected with AM[1:0].
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 RBS: Red/Blue swap
This bit allows to swap Red and Blue to support BGR or ABGR color formats.
0: Regular mode (RGB or ARGB)
1: Swap mode (BGR or ABGR)
Bit 20 AI: Alpha Inverted
This bit inverts the alpha value.
0: Regular alpha
1: Inverted alpha
Bits 19:18 Reserved, must be kept at reset value.
Bits 17:16 AM[1:0]: Alpha mode
These bits define which alpha channel value to be used for the background image.
00: No modification of the foreground image alpha channel value
01: Replace original background image alpha channel value by ALPHA[7: 0]
10: Replace original background image alpha channel value by ALPHA[7:0] multiplied with
original alpha channel value
Others: Reserved
Bits 15:8 CS[7:0]: CLUT size
These bits define the size of the CLUT used for the BG.
The number of CLUT entries is equal to CS[7:0] + 1.
Bits 7:6 Reserved, must be kept at reset value.

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RM0433 Chrom-ART Accelerator controller (DMA2D)

Bit 5 START: Start

This bit is set to start the automatic loading of the CLUT. This bit is automatically reset:
– at the end of the transfer
– when the transfer is aborted by the user by setting ABORT bit in DMA2D_CR
– when a transfer error occurs
– when the transfer has not started due to a configuration error or another transfer
operation already on going (data transfer or automatic background CLUT transfer)
Bit 4 CCM: CLUT color mode
These bits define the color format of the CLUT.
0: ARGB8888
1: RGB888
Bits 3:0 CM[3:0]: Color mode
These bits define the color format of the foreground image.
0000: ARGB8888
0001: RGB888
0010: RGB565
0011: ARGB1555
0100: ARGB4444
0101: L8
0110: AL44
0111: AL88
1000: L4
1001: A8
1010: A4
Others: Reserved

18.5.11 DMA2D background color register (DMA2D_BGCOLR)

Address offset: 0x028
Reset value: 0x0000 0000
This register can only be written when data transfers are disabled. Once the data transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. RED[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN[7:0] BLUE[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 RED[7:0]: Red value for the A4 or A8 mode of the background
Used also for fixed color BG in memory-to-memory mode with blending and fixed color BG
(FG fetch only with FG and BG PFC active).
Bits 15:8 GREEN[7:0]: Green value for the A4 or A8 mode of the background
Used also for fixed color BG in memory-to-memory mode with blending and fixed color BG
(FG fetch only with FG and BG PFC active).

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Bits 7:0 BLUE[7:0]: Blue value for the A4 or A8 mode of the background
Used also for fixed color BG in memory-to-memory mode with blending and fixed color BG
(FG fetch only with FG and BG PFC active).

18.5.12 DMA2D foreground CLUT memory address register

(DMA2D_FGCMAR)
Address offset: 0x02C
Reset value: 0x0000 0000
This register can only be written when data transfers are disabled. Once the data transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: Memory address

Address of the data used for the CLUT address dedicated to the foreground image.
If the foreground CLUT format is 32-bit, the address must be 32-bit aligned.

18.5.13 DMA2D background CLUT memory address register

(DMA2D_BGCMAR)
Address offset: 0x030
Reset value: 0x0000 0000
This register can only be written when transfers are disabled. Once the CLUT transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: Memory address

Address of the data used for the CLUT address dedicated to the background image.
If the background CLUT format is 32-bit, the address must be 32-bit aligned.

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RM0433 Chrom-ART Accelerator controller (DMA2D)

18.5.14 DMA2D output PFC control register (DMA2D_OPFCCR)

Address offset: 0x034
Reset value: 0x0000 0000
This register can only be written when transfers are disabled. Once the CLUT transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RBS AI Res. Res. Res. Res.
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. SB Res. Res. Res. Res. Res. CM[2:0]
rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 RBS: Red/Blue swap
This bit allows to swap Red and Blue to support BGR or ABGR color formats.
0: Regular mode (RGB or ARGB)
1: Swap mode (BGR or ABGR)
Bit 20 AI: Alpha Inverted
This bit inverts the alpha value.
0: Regular alpha
1: Inverted alpha
Bits 19:9 Reserved, must be kept at reset value.
Bit 8 SB: Swap bytes
When this bit is set, the bytes in the output FIFO are swapped two by two. The number of
pixels per line (PL) must be even, and the output memory address (OMAR) must be even.
0: Bytes in regular order in the output FIFO
1: Bytes swapped two by two in the output FIFO
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 CM[2:0]: Color mode
These bits define the color format of the output image.
000: ARGB8888
001: RGB888
010: RGB565
011: ARGB1555
100: ARGB4444
Others: Reserved

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18.5.15 DMA2D output color register (DMA2D_OCOLR)

Address offset: 0x038
Reset value: 0x0000 0000
The same register is used to show the color values, with different formats depending on the
color mode.
This register can only be written when transfers are disabled. Once the CLUT transfer
started, this register is read-only.
ARGB8888 or RGB888 color mode

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA[7:0] RED[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN[7:0] BLUE[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 ALPHA[7:0]: Alpha channel value of the output color in ARGB8888 mode (otherwise reserved)
Bits 23:16 RED[7:0]: Red value of the output image in ARGB8888 or RGB888 mode
Bits 15:8 GREEN[7:0]: Green value of the output image in ARGB8888 or RGB888
Bits 7:0 BLUE[7:0]: Blue value of the output image in ARGB8888 or RGB888

18.5.16 DMA2D output color register [alternate] (DMA2D_OCOLR)

Address offset: 0x038
Reset value: 0x0000 0000
The same register is used to show the color values, with different formats depending on the
color mode.
This register can only be written when transfers are disabled. Once the CLUT transfer
started, this register is read-only.
RGB565 color mode

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RED[4:0] GREEN[5:0] BLUE[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:11 RED[4:0]: Red value of the output image in RGB565 mode
Bits 10:5 GREEN[5:0]: Green value of the output image in RGB565 mode
Bits 4:0 BLUE[4:0]: Blue value of the output image in RGB565 mode

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RM0433 Chrom-ART Accelerator controller (DMA2D)

18.5.17 DMA2D output color register [alternate] (DMA2D_OCOLR)

Address offset: 0x038
Reset value: 0x0000 0000
The same register is used to show the color values, with different formats depending on the
color mode.
This register can only be written when transfers are disabled. Once the CLUT transfer
started, this register is read-only.
ARGB1555 color mode

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A RED[4:0] GREEN[4:0] BLUE[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 A: Alpha channel value of the output color in ARGB1555 mode
Bits 14:10 RED[4:0]: Red value of the output image in ARGB1555 mode
Bits 9:5 GREEN[4:0]: Green value of the output image in ARGB1555 mode
Bits 4:0 BLUE[4:0]: Blue value of the output image in ARGB1555 mode

18.5.18 DMA2D output color register [alternate] (DMA2D_OCOLR)

Address offset: 0x038
Reset value: 0x0000 0000
The same register is used to show the color values, with different formats depending on the
color mode.
This register can only be written when transfers are disabled. Once the CLUT transfer
started, this register is read-only.
ARGB4444 color mode

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALPHA[3:0] RED[3:0] GREEN[3:0] BLUE[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 ALPHA[3:0]: Alpha channel of the output color value in ARGB4444
Bits 11:8 RED[3:0]: Red value of the output image in ARGB4444 mode
Bits 7:4 GREEN[3:0]: Green value of the output image in ARGB4444 mode

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Bits 3:0 BLUE[3:0]: Blue value of the output image in ARGB4444 mode

18.5.19 DMA2D output memory address register (DMA2D_OMAR)

Address offset: 0x03C
Reset value: 0x0000 0000
This register can only be written when transfers are disabled. Once the CLUT transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: Memory address

Address of the data used for the output FIFO.
The address alignment must match the image format selected: a 32-bit per pixel format must
be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.

18.5.20 DMA2D output offset register (DMA2D_OOR)

Address offset: 0x040
Reset value: 0x0000 0000
This register can only be written when transfers are disabled. Once the CLUT transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LO[15:0]: Line offset
This field gives the line offset used for the output, expressed:
– in pixels when LOM = 0 in DMA2D_CR. Only LO[13:0] bits are considered,
LO[15:14] bits are ignored.
– in bytes when LOM = 1
This value is used for the address generation. It is added at the end of each line to determine
the starting address of the next line.

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RM0433 Chrom-ART Accelerator controller (DMA2D)

18.5.21 DMA2D number of line register (DMA2D_NLR)

Address offset: 0x044
Reset value: 0x0000 0000
This register can only be written when transfers are disabled. Once the CLUT transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. PL[13:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NL[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:16 PL[13:0]: Pixel per lines per lines of the area to be transferred
If any of the input image format is 4-bit per pixel, pixel per lines must be even.
Bits 15:0 NL[15:0]: Number of lines of the area to be transferred.

18.5.22 DMA2D line watermark register (DMA2D_LWR)

Address offset: 0x048
Reset value: 0x0000 0000
This register can only be written when transfers are disabled. Once the CLUT transfer
started, this register is read-only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LW[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LW[15:0]: Line watermark for interrupt generation
An interrupt is raised when the last pixel of the watermarked line has been transferred.

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18.5.23 DMA2D AXI master timer configuration register (DMA2D_AMTCR)

Address offset: 0x04C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DT[7:0] Res. Res. Res. Res. Res. Res. Res. EN
rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 DT[7:0]: Dead time
Dead time value in the AXI clock cycle inserted between two consecutive accesses on the
AXI master port. These bits represent the minimum guaranteed number of cycles between
two consecutive AXI accesses.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 EN: Dead-time functionality enable

18.5.24 DMA2D foreground CLUT (DMA2D_FGCLUTx)

Address offset: 0x400 + 0x4 * x, (x = 0 to 255)
Reset value: 0xXXXX XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA[7:0] RED[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN[7:0] BLUE[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 ALPHA[7:0]: Alpha

Alpha value for index {x} for the foreground
Bits 23:16 RED[7:0]: Red
Red value for index {x} for the foreground
Bits 15:8 GREEN[7:0]: Green
Green value for index {x} for the foreground
Bits 7:0 BLUE[7:0]: Blue
Blue value for index {x} for the foreground

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RM0433 Chrom-ART Accelerator controller (DMA2D)

18.5.25 DMA2D background CLUT (DMA2D_BGCLUTx)

Address offset: 0x800 + 0x4 * x, (x = 0 to 255)
Reset value: 0xXXXX XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA[7:0] RED[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN[7:0] BLUE[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 ALPHA[7:0]:Alpha

Alpha value for index {x} for the background
Bits 23:16 RED[7:0]: Red
Red value for index {x} for the background
Bits 15:8 GREEN[7:0]: Green
Green value for index {x} for the background
Bits 7:0 BLUE[7:0]: Blue
Blue value for index {x} for the background

18.5.26 DMA2D register map

Table 144. DMA2D register map and reset values

Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
MODE[2:0]

ABORT

START
CTCIE
CAEIE

SUSP
TWIE
CEIE

TCIE
TEIE

LOM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
Res.
Res.
DMA2D_CR
0x000

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0
CTCIF
CAEIF
TWIF
CEIF

TCIF
TEIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_ISR
0x004

Reset value 0 0 0 0 0 0
CCTCIF
CAECIF
CTWIF
CCEIF

CTCIF
CTEIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_IFCR
0x008

Reset value 0 0 0 0 0 0
DMA2D_FGMAR MA[31:0]
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_FGOR LO[15:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_BGMAR MA[31:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_BGOR LO[15:0]
0x018
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CSS[1:0]

AM[1:0]

START
CCM
RBS
Res.
Res.

Res.
Res.

DMA2D_FGPFCCR ALPHA[7:0] CS[7:0] CM[3:0]

AI

0x01C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0433 Rev 8 747/3353

748
Chrom-ART Accelerator controller (DMA2D) RM0433

Table 144. DMA2D register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2D_FGCOLR RED[7:0] GREEN[7:0] BLUE[7:0]
0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AM[1:0]

START
CCM
Res.
Res.

Res.
Res.

Res.
Res.
RBS
DMA2D_BGPFCCR ALPHA[7:0] CS[7:0] CM[3:0]

AI
0x024

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2D_BGCOLR RED[7:0] GREEN[7:0] BLUE[7:0]
0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_FGCMAR MA[31:0]
0x02C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_BGCMAR MA[31:0]
0x030
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RBS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
DMA2D_OPFCCR CM[2:0]

SB
AI
0x034
Reset value 0 0 0 0 0 0
DMA2D_OCOLR
ARGB8888 or ALPHA[7:0] RED[7:0] GREEN[7:0] BLUE[7:0]
0x038 RGB888 color mode

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_OCOLR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RED[4:0] GREEN[6:0] BLUE[4:0]
0x038 RGB565 color mode
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_OCOLR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ARGB1555 color A RED[4:0] GREEN[4:0] BLUE[4:0]

0x038 mode
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_OCOLR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ARGB4444 color ALPHA[3:0] RED[3:0] GREEN[3:0] BLUE[3:0]

0x038 mode
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA2D_OMAR MA[31:0]
0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_OOR LO[15:0]
0x040
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.

DMA2D_NLR PL[13:0] NL[15:0]

0x044
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_LWR LW[15:0]
0x048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA2D_AMTCR DT[7:0]
EN

0x04C
Reset value 0 0 0 0 0 0 0 0 0
0x050-
Reserved Reserved
0x3FC
0x400 + DMA2D_FGCLUTx ALPHA[7:0] RED[7:0] GREEN[7:0] BLUE[7:0]
0x4*x,
(x=0 to Reset value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
255)
0x800 + DMA2D_BGCLUTx ALPHA[7:0] RED[7:0] GREEN[7:0] BLUE[7:0]
0x4*x,
(x=0 to Reset value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
255)

Refer to Section 2.3 for the register boundary addresses.

748/3353 RM0433 Rev 8

RM0433 Nested vectored interrupt controller (NVIC)

19 Nested vectored interrupt controller (NVIC)

19.1 NVIC features

The NVIC includes the following features:
• up to 150 maskable interrupt channels for STM32H7xxx (not including the 16 interrupt
lines of Cortex®-M7 with FPU)
• 16 programmable priority levels (4 bits of interrupt priority are used)
• low-latency exception and interrupt handling
• power management control
• implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts, including the core exceptions, are managed by the NVIC.
For more information on exceptions and NVIC programming, refer to PM0253 programming
manual for Cortex®-M7.

19.1.1 SysTick calibration value register

The SysTick calibration value (SYST_CALIB) is fixed to 0x3E8. It provides a reference
timebase of 1 ms based when the SysTick clock frequency is 1 MHz. To match the 1 ms
timebase whatever the application frequency, the SysTick reload value must be
programmed as follows in the SYST_RVR register:
• The SysTick clock source is the 100 MHz CPU clock (HCLK):
reload value = ( F HCLK × SYST_CALIB ) – 1

• or the SysTick clock source is an external clock:

reload value = ( ( F HCLK ⁄ 8 ) × SYST_CALIB ) – 1

where FHCLK refers to the AHB frequency expressed in MHz.

For example, to achieve a timebase of 1 ms when the SysTick clock source is the 100 MHz
HCLK:
reload value = ( 100 × SYST_CALIB ) – 1 = 0x1869F

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Nested vectored interrupt controller (NVIC) RM0433

19.1.2 Interrupt and exception vectors

The exception vectors connected to the NVIC are the following: reset, NMI, HardFault,
MemManage, Bus Fault, UsageFault, SVCall, DebugMonitor, PendSV, SysTick.

Table 145. NVIC(1)

Priority
NVIC
Signal Acronym Description Address offset
position

- - - - Reserved 0x0000 0000

- -3 - Reset Reset 0x0000 0004
Non maskable interrupt.
The RCC Clock Security
- -2 - NMI 0x0000 0008
System (CSS) is linked to the
NMI vector.
- -1 - HardFault All classes of fault 0x0000 000C
- 0 - MemManage Memory management 0x0000 0010
Prefetch fault,
- 1 - BusFault 0x0000 0014
memory access fault
Undefined instruction or illegal
- 2 - UsageFault 0x0000 0018
state
0x0000 001C-
- - - - Reserved
0x0000 002B
System service call
- 3 - SVCall 0x0000 002C
via SWI instruction
- 4 - DebugMonitor Debug monitor 0x0000 0030
- - - - Reserved 0x0000 0034
Pendable request for system
- 5 - PendSV 0x0000 0038
service
- 6 - SysTick System tick timer 0x0000 003C
wwdg1_it 7 0 WWDG1 Window Watchdog interrupt 0x0000 0040
PVD through EXTI line
exti_pwr_pvd_wkup 8 1 PVD_PVM 0x0000 0044
detection interrupt
exti_tamp_rtc_wkup RTC_TAMP_STAMP_ RTC tamper, timestamp
9 2 0x0000 0048
lsecss_rcc_it CSS_LSE CSS LSE
RTC Wakeup interrupt through
exti_wkup_rtc_wkup 10 3 RTC_WKUP 0x0000 004C
the EXTI line
Flash memory
flash_it 11 4 FLASH 0x0000 0050
global interrupt
rcc_it 12 5 RCC RCC global interrupt 0x0000 0054
exti_exti0_wkup 13 6 EXTI0 EXTI Line 0 interrupt 0x0000 0058
exti_exti1_wkup 14 7 EXTI1 EXTI Line 1 interrupt 0x0000 005C
exti_exti2_wkup 15 8 EXTI2 EXTI Line 2 interrupt 0x0000 0060

750/3353 RM0433 Rev 8

RM0433 Nested vectored interrupt controller (NVIC)

Table 145. NVIC(1) (continued)

Priority
NVIC
Signal Acronym Description Address offset
position

exti_exti3_wkup 16 9 EXTI3 EXTI Line 3interrupt 0x0000 0064

exti_exti4_wkup 17 10 EXTI4 EXTI Line 4interrupt 0x0000 0068
DMA1 Stream0
dma1_it0 18 11 DMA_STR0 0x0000 006C
global interrupt
DMA1 Stream1
dma1_it1 19 12 DMA_STR1 0x0000 0070
global interrupt
DMA1 Stream2
dma1_it2 20 13 DMA_STR2 0x0000 0074
global interrupt
DMA1 Stream3
dma1_it3 21 14 DMA_STR3 0x0000 0078
global interrupt
DMA1 Stream4
dma1_it4 22 15 DMA_STR4 0x0000 007C
global interrupt
DMA1 Stream5
dma1_it5 23 16 DMA_STR5 0x0000 0080
global interrupt
DMA1 Stream6
dma1_it6 24 17 DMA_STR6 0x0000 0084
global interrupt
adc1_it ADC1 and ADC2
25 18 ADC1_2 0x0000 0088
adc2_it global interrupt

ttfdcan_intr0_it 26 19 FDCAN1_IT0 FDCAN1 Interrupt 0 0x0000 008C

fdcan_intr0_it 27 20 FDCAN2_IT0 FDCAN2 Interrupt 0 0x0000 0090
ttfdcan_intr1_it 28 21 FDCAN1_IT1 FDCAN1 Interrupt 1 0x0000 0094
fdcan_intr1_it 29 22 FDCAN2_IT1 FDCAN2 Interrupt 1 0x0000 0098
exti_exti5_wkup
exti_exti6_wkup
exti_exti7_wkup 30 23 EXTI9_5 EXTI Line[9:5] interrupts 0x 0000 009C
exti_exti8_wkup
exti_exti9_wkup
tim1_brk_it 31 24 TIM1_BRK TIM1 break interrupt 0x0000 00A0
tim1_upd_it 32 25 TIM1_UP TIM1 update interrupt 0x0000 00A4
TIM1 trigger and commutation
tim1_trg_it 33 26 TIM1_TRG_COM 0x0000 00A8
interrupts
TIM1 capture / compare
tim1_cc_it 34 27 TIM_CC 0x0000 00AC
interrupt
tim2_it 35 28 TIM2 TIM2 global interrupt 0x0000 00B0
tim3_it 36 29 TIM3 TIM3 global interrupt 0x0000 00B4
tim4_it 37 30 TIM4 TIM4 global interrupt 0x0000 00B8

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Nested vectored interrupt controller (NVIC) RM0433

Table 145. NVIC(1) (continued)

Priority
NVIC
Signal Acronym Description Address offset
position

i2c1_ev_it
38 31 I2C1_EV I2C1 event interrupt 0x0000 00BC
exti_i2c1_ev_wkup
i2c1_err_it 39 32 I2C1_ER I2C1 error interrupt 0x0000 00C0
i2c2_ev_it
40 33 I2C2_EV I2C2 event interrupt 0x0000 00C4
exti_i2c2_ev_wkup
i2c2_err_it 41 34 I2C2_ER I2C2 error interrupt 0x0000 00C8
spi1_it
42 35 SPI1 SPI1 global interrupt 0x0000 00CC
exti_spi1_it
spi2_it
43 36 SPI2 SPI2 global interrupt 0x0000 00D0
exti_spi2_it
usart1_gbl_it
44 37 USART1 USART1 global interrupt 0x0000 00D4
exti_usart1_wkup
usart2_gbl_it
45 38 USART2 USART2 global interrupt 0x0000 00D8
exti_usart2_wkup
usart3_gbl_it
46 39 USART3 USART3 global interrupt 0x0000 00DC
exti_usart3_wkup
exti_exti10_it
exti_exti11_wkup
exti_exti12_wkup
47 40 EXTI15_10 EXTI Line[15:10] interrupts 0x0000 00E0
exti_exti13_wkup
exti_exti14_wkup
exti_exti15_wkup
RTC alarms (A and B) through
exti_rtc_al 48 41 RTC_ALARM 0x0000 00E4
EXTI Line interrupts
- 49 42 - - 0x0000 00E8
tim8_brk_it TIM8 break and
50 43 TIM8_BRK_TIM12 0x0000 00EC
tim12_gbl_it TIM12 global interrupts

tim8_upd_it TIM8 update and

51 44 TIM8_UP_TIM13 0x0000 00F0
tim13_gbl_it TIM13 global interrupts

tim8_trg_it TIM8_TRG_COM TIM8 trigger /commutation and

52 45 0x0000 00F4
tim14_gbl_it _TIM14 TIM14 global interrupts

TIM8 capture / compare

tim8_cc_it 53 46 TIM8_CC 0x0000 00F8
interrupts

752/3353 RM0433 Rev 8

RM0433 Nested vectored interrupt controller (NVIC)

Table 145. NVIC(1) (continued)

Priority
NVIC
Signal Acronym Description Address offset
position

DMA1 Stream7
dma1_it7 54 47 DMA1_STR7 0x0000 00FC
global interrupt
fmc_gbl_it 55 48 FMC FMC global interrupt 0x0000 0100
sdmmc_it 56 49 SDMMC1 SDMMC global interrupt 0x0000 0104
tim5_gbl_it 57 50 TIM5 TIM5 global interrupt 0x0000 0108
spi3_it
58 51 SPI3 SPI3 global interrupt 0x0000 010C
exti_spi3_wkup
uart4_gbl_it
59 52 UART4 UART4 global interrupt 0x0000 0110
exti_uart4_wkup
uart5_gbl_it
60 53 UART5 UART5 global interrupt 0x0000 0114
exti_uart5_wkup
tim6_gbl_it TIM6 global interrupt
61 54 TIM6_DAC 0x0000 0118
dac_unr_it DAC underrun error interrupt
tim7_gbl_it 62 55 TIM7 TIM7 global interrupt 0x0000 011C
dma2_it0 63 56 DMA2_STR0 DMA2 Stream0 interrupt 0x0000 0120
dma2_it1 64 57 DMA2_STR1 DMA2 Stream1 interrupt 0x0000 0124
dma2_it2 65 58 DMA2_STR2 DMA2 Stream2 interrupt 0x0000 0128
dma2_it3 66 59 DMA2_STR3 DMA2 Stream3 interrupt 0x0000 012C
dma2_it4 67 60 DMA2_STR4 DMA2 Stream4 interrupt 0x0000 0130
eth_sbd_intr_it 68 61 ETH Ethernet global interrupt 0x0000 0134
Ethernet wakeup through EXTI
exti_eth_wkup 69 62 ETH_WKUP 0x0000 0138
line interrupt
fdcan_cal_it 70 63 FDCAN_CAL FDCAN calibration interrupts 0x0000 013C
Arm® Cortex®-M7 Send even
cm7_sev_it 71 64 - 0x0000 0140
interrupt
NC 72 65 - - 0x0000 0144
NC 73 66 - - 0x0000 0148
NC 74 67 - - 0x0000 014C
dma2_it5 75 68 DMA2_STR5 DMA2 Stream5 interrupt 0x0000 0150
dma2_it6 76 69 DMA2_STR6 DMA2 Stream6 interrupt 0x0000 0154
dma2_it7 77 70 DMA2_STR7 DMA2 Stream7 interrupt 0x0000 0158
usart6_gbl_it USART6 global interrupt
78 71 USART6 0x0000 015C
exti_usart6_wkup USART6 wakeup interrupt

RM0433 Rev 8 753/3353

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Nested vectored interrupt controller (NVIC) RM0433

Table 145. NVIC(1) (continued)

Priority
NVIC
Signal Acronym Description Address offset
position

i2c3_ev_it
79 72 I2C3_EV I2C3 event interrupt 0x0000 0160
exti_i2c3_ev_wkup
i2c3_err_it 80 73 I2C3_ER I2C3 error interrupt 0x0000 0164
usb1_out_it 81 74 OTG_HS_EP1_OUT OTG_HS out global interrupt 0x0000 0168
usb1_in_it 82 75 OTG_HS_EP1_IN OTG_HS in global interrupt 0x0000 016C
exti_usb1_wkup 83 76 OTG_HS_WKUP OTG_HS wakeup interrupt 0x0000 0170
usb1_gbl_it 84 77 OTG_HS OTG_HS global interrupt 0x0000 0174
dcmi_it 85 78 DCMI DCMI global interrupt 0x0000 0178
cryp_it 86 79 CRYP CRYP global interrupt 0x0000 017C
HASH and RNG
hash_rng_it 87 80 HASH_RNG 0x0000 0180
global interrupt
cpu_fpu_it 88 81 FPU CPU FPU 0x0000 0184
uart7_gbl_it
89 82 UART7 UART7 global interrupt 0x0000 0188
exti_uart7_wkup
uart8_gbl_it
90 83 UART8 UART8 global interrupt 0x0000 018C
exti_uart8_wkup
spi4_it
91 84 SPI4 SPI4 global interrupt 0x0000 0190
exti_spi4_wkup
spi5_it
92 85 SPI5 SPI5 global interrupt 0x0000 0194
exti_spi5_wkup
spi6_it
93 86 SPI6 SPI6 global interrupt 0x0000 0198
exti_spi6_wkup
sai1_it 94 87 SAI1 SAI1 global interrupt 0x0000 019C
ltdc_it 95 88 LTDC LCD-TFT global interrupt 0x0000 01A0
ltdc_err_it 96 89 LTDC_ER LCD-TFT error interrupt 0x0000 01A4
dma2d_gbl_it 97 90 DMA2D DMA2D global interrupt 0x0000 01A8
- 98 91 SAI2 SAI2 global interrupt 0x0000 01AC
quadspi_it 99 92 QUADSPI QuadSPI global interrupt 0x0000 01B0
lptim1_it
100 93 LPTIM1 LPTIM1 global interrupt 0x0000 01B4
exti_lptim_wkup
cec_it
101 94 CEC HDMI-CEC global interrupt 0x0000 01B8
exti_cec_it
i2c4_ev_it
102 95 I2C4_EV I2C4 event interrupt 0x0000 01BC
exti_i2c4_ev_it

754/3353 RM0433 Rev 8

RM0433 Nested vectored interrupt controller (NVIC)

Table 145. NVIC(1) (continued)

Priority
NVIC
Signal Acronym Description Address offset
position

i2c4_err_it 103 96 I2C4_ER I2C4 error interrupt 0x0000 01C0

spdifrx_it 104 97 SPDIF SPDIFRX global interrupt 0x0000 01C4
usb2_out_it 105 98 OTG_FS_EP1_OUT OTG_FS out global interrupt 0x0000 01C8
usb2_in_it 106 99 OTG_FS_EP1_IN OTG_FS in global interrupt 0x0000 01CC
exti_usb2_wkup 107 100 OTG_FS_WKUP OTG_FS wakeup 0x0000 01D0
usb2_gbl_it 108 101 OTG_FS OTG_FS global interrupt 0x0000 01D4
dmamux1_ovr_it 109 102 DMAMUX1_OV DMAMUX1 overrun interrupt 0x0000 01D8
hrtim1_mst_it 110 103 HRTIM1_MST HRTIM1 master timer interrupt 0x0000 01DC
hrtim1_tima_it 111 104 HRTIM1_TIMA HRTIM1 timer A interrupt 0x0000 01E0
hrtim1_timb_it 112 105 HRTIM_TIMB HRTIM1 timer B interrupt 0x0000 01E4
hrtim1_timc_it 113 106 HRTIM1_TIMC HRTIM1 timer C interrupt 0x0000 01E8
hrtim1_timd_it 114 107 HRTIM1_TIMD HRTIM1 timer D interrupt 0x0000 01EC
hrtim1_time_it 115 108 HRTIM_TIME HRTIM1 timer E interrupt 0x0000 01F0
hrtim1_fault_it 116 109 HRTIM1_FLT HRTIM1 fault interrupt 0x0000 01F4
dfsdm1_it0 117 110 DFSDM1_FLT0 DFSDM1 filter 0 interrupt 0x0000 01F8
dfsdm1_it1 118 111 DFSDM1_FLT1 DFSDM1 filter 1 interrupt 0x0000 01FC
dfsdm1_it2 119 112 DFSDM1_FLT2 DFSDM1 filter 2 interrupt 0x0000 0200
dfsdm1_it3 120 113 DFSDM1_FLT3 DFSDM1 filter 3 interrupt 0x0000 0204
sai3_gbl_it_it 121 114 SAI3 SAI3 global interrupt 0x0000 0208
swpmi_gbl_it SWPMI global interrupt
122 115 SWPMI1 0x0000 020C
exti_swpmi_wup SWPMI wakeup
tim15_gbl_it 123 116 TIM15 TIM15 global interrupt 0x0000 0210
tim16_gbl_it 124 117 TIM16 TIM16 global interrupt 0x0000 0214
tim17_gbl_it 125 118 TIM17 TIM17 global interrupt 0x0000 0218
exti_mdios_wkup 126 119 MDIOS_WKUP MDIOS wakeup 0x0000 021C
mdios_it 127 120 MDIOS MDIOS global interrupt 0x0000 0220
jpeg_it 128 121 JPEG JPEG global interrupt 0x0000 0224
mdma_it 129 122 MDMA MDMA 0x0000 0228
- 130 - - - 0x0000 022C
sdmmc2_it 131 124 SDMMC2 SDMMC global interrupt 0x0000 0230
hsem1_it 132 125 HSEM0 HSEM global interrupt 1 0x0000 0234
- 133 - - - 0x0000 0238
adc3_it 134 127 ADC3 ADC3 global interrupt 0x0000 023C

RM0433 Rev 8 755/3353

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Nested vectored interrupt controller (NVIC) RM0433

Table 145. NVIC(1) (continued)

Priority
NVIC
Signal Acronym Description Address offset
position

dmamux2_ovr_it 135 128 DMAMUX2_OVR DMAMUX2 overrun interrupt 0x0000 0240

bdma_ch0_it 136 129 BDMA_CH0 BDMA channel 0 interrupt 0x0000 0244
bdma_ch1_it 137 130 BDMA_CH1 BDMA channel 1 interrupt 0x0000 0248
bdma_ch2_it 138 131 BDMA_CH2 BDMA channel 2 interrupt 0x0000 024C
bdma_ch3_it 139 132 BDMA_CH3 BDMA channel 3 interrupt 0x0000 0250
bdma_ch4_it 140 133 BDMA_CH4 BDMA channel 4 interrupt 0x0000 0254
bdma_ch5_it 141 134 BDMA_CH5 BDMA channel 5 interrupt 0x0000 0258
bdma_ch6_it 142 135 BDMA_CH6 BDMA channel 6 interrupt 0x0000 025C
bdma_ch7_it 143 136 BDMA_CH7 BDMA channel 7 interrupt 0x0000 0260
comp_gbl_it
COMP1 and COMP2
exti_comp1_wkup 144 137 COMP 0x0000 0264
global interrupt
exti_comp2_wkup
lptim2_it
145 138 LPTIM2 LPTIM2 timer interrupt 0x0000 0268
exti_lptim2_wkup
lptim3_it
146 139 LPTIM3 LPTIM2 timer interrupt 0x0000 026C
exti_lptim3_wkup
lptim4_it
147 140 LPTIM4 LPTIM2 timer interrupt 0x0000 0270
exti_lptim4_wkup
lptim5_it
148 141 LPTIM5 LPTIM2 timer interrupt 0x0000 0274
exti_lptim5_wkup
lpuart_gbl_it
exti_lpuart_rx_it 149 142 LPUART LPUART global interrupt 0x0000 0278
exti_lpuart_tx_it
exti_d1_wwdg1_wkup 150 143 WWDG1_RST Window Watchdog interrupt 0x0000 027C
Clock Recovery System global
crs_it 151 144 CRS 0x0000 0280
interrupt
ECC diagnostic global interrupt
ramecc1_it RAMECC1
for RAMECC D1
ECC diagnostic global interrupt
ramecc2_it 152 145 RAMECC2 0x0000 0284
for RAMECC D2
ECC diagnostic global interrupt
ramecc2_it RAMECC3
for RAMECC D3
- 153 146 SAI4 SAI4 global interrupt 0x0000 0288
- 154 147 - - 0x0000 028C
- 155 148 - - 0x0000 0290

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RM0433 Nested vectored interrupt controller (NVIC)

Table 145. NVIC(1) (continued)

Priority
NVIC
Signal Acronym Description Address offset
position

exti_wkup1_wkup
exti_wkup2_wkup
exti_wkup3_wkup
156 149 WKUP WKUP0 to WKUP5 pins 0x0000 0294
exti_wkup4_wkup
exti_wkup5_wkup
exti_wkup6_wkup
1. When different signals are connected to the same NVIC interrupt line, they are OR-ed.

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Extended interrupt and event controller (EXTI) RM0433

20 Extended interrupt and event controller (EXTI)

The Extended Interrupt and event controller (EXTI) manages wakeup through configurable
and direct event inputs. It provides wakeup requests to the Power Control, and generates
interrupt requests to the CPU NVIC and to the D3 domain DMAMUX2, and events to the
CPU event input.
The EXTI wakeup requests allow the system to be woken up from Stop mode, and the CPU
to be woken up from CStop mode.
Both the interrupt request and event request generation can also be used in Run modes.

20.1 EXTI main features

The EXTI main features are the following:
• All Event inputs allow the CPU to wakeup and to generate a CPU interrupt and/or CPU
event
• Some Event inputs allow the user to wakeup the D3 domain for autonomous Run mode
and generate an interrupt to the D3 domain, i.e. the DMAMUX2
The asynchronous event inputs are classified in 2 groups:
• Configurable events (signals from I/Os or peripherals able to generate a pulse), they
have the following features:
– Selectable active trigger edge
– Interrupt pending status register bit
– Individual Interrupt and Event generation mask
– SW trigger possibility
– Configurable System D3 domain wakeup events have a D3 Pending mask and
status register and may have a D3 interrupt signal.
• Direct events (interrupt and wakeup sources from other peripherals, requiring to be
cleared in the peripheral), they feature
– Fixed rising edge active trigger
– No interrupt pending status register bit in the EXTI (the interrupt pending status is
provided by the peripheral generating the event)
– Individual Interrupt and Event generation mask
– No SW trigger possibility
– Direct system D3 domain wakeup events have a D3 Pending mask and status
register and may have a D3 interrupt signal

20.2 EXTI block diagram

As shown in Figure 90, the EXTI consists of a Register block accessed via an APB
interface, an Event input Trigger block, and a Masking block.
The Register block contains all EXTI registers.
The Event input trigger block provides Event input edge triggering logic.

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RM0433 Extended interrupt and event controller (EXTI)

The Masking block provides the Event input distribution to the different wakeup, interrupt
and event outputs, and their masking.

Figure 90. EXTI block diagram

APB interface
Registers

Configurable event(x) cpu_it_exti_per(x)

nvic(n)
cpu_event CPU
Peripherals

rxev
Event events exti_cpu_wkup
trigger Masking
PWR
Direct event(x) exti_d3_wkup

d3_it_exti_per(x)
d3_pendclear_in[3:0] D3

EXTI

MSv41947V1

20.2.1 EXTI connections between peripherals, CPU, and D3 domain

The peripherals able to generate wakeup events when the system is in Stop mode or the
CPU is in CStop mode are connected to an EXTI Configurable event input or Direct Event
input:
• Peripheral signals that generate a pulse are connected to an EXTI Configurable Event
input. For these events the EXTI provides a CPU status pending bit that has to be
cleared.
• Peripheral Interrupt and Wakeup sources that have to be cleared in the peripheral are
connected to an EXTI Direct Event input. There is no CPU status pending bit within the
EXTI. The Interrupt or Wakeup is cleared by the CPU in the peripheral.
The Event inputs able to wakeup D3 for autonomous Run mode are provided with a D3
domain pending request function, that has to be cleared. This clearing request is taken care
of by the signal selected by the Pending clear selection.
The CPU interrupts are connected to their respective CPU NVIC, and, similarly, the CPU
event is connected to the CPU rxev input.
The EXTI Wakeup signals are connected to the PWR block, and are used to wakeup the D3
domain and/or the CPU.
The D3 domain interrupts allow the system to trigger events for D3 domain autonomous
Run mode operation.

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20.3 EXTI functional description

Depending on the EXTI Event input type and wakeup target(s), different logic
implementations are used. The applicable features are controlled from register bits:
• Active trigger edge enable, by EXTI rising trigger selection register (EXTI_RTSR1),
EXTI rising trigger selection register (EXTI_RTSR2), EXTI rising trigger selection
register (EXTI_RTSR3), and EXTI falling trigger selection register (EXTI_FTSR1),
EXTI falling trigger selection register (EXTI_FTSR2), EXTI falling trigger selection
register (EXTI_FTSR3)
• Software trigger, by EXTI software interrupt event register (EXTI_SWIER1), EXTI
software interrupt event register (EXTI_SWIER2), EXTI software interrupt event
register (EXTI_SWIER3)
• CPU Interrupt enable, by EXTI interrupt mask register (EXTI_CPUIMR1), EXTI
interrupt mask register (EXTI_CPUIMR2), EXTI interrupt mask register
(EXTI_CPUIMR3)
• CPU Event enable, by EXTI event mask register (EXTI_CPUEMR1), EXTI event mask
register (EXTI_CPUEMR2), EXTI event mask register (EXTI_CPUEMR3)
• D3 domain wakeup pending, by EXTI D3 pending mask register (EXTI_D3PMR1),
EXTI D3 pending mask register (EXTI_D3PMR2), EXTI D3 pending mask register
(EXTI_D3PMR3)

Table 146. EXTI Event input configurations and register control(1)

EXTI_CPUEMR
EXTI_CPUIMR

EXTI_D3PMR
EXTI_SWIER
EXTI_RTSR

EXTI_FTSR

Event input Wakeup Logic

type target(s) implementation

Configurable
CPU event input, CPU -
wakeup logic
Configurable X X X X X
Configurable
Any(2) event input, Any X
wakeup logic
Direct event
CPU input, CPU -
wakeup logic
Direct - - - X X
Direct event
Any(2) input, Any X
wakeup logic
1. X indicates that functionality is available.
2. Waking-up D3 domain for autonomous Run mode, and/or CPU.

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RM0433 Extended interrupt and event controller (EXTI)

20.3.1 EXTI Configurable event input CPU wakeup

Figure 92 is a detailed representation of the logic associated with Configurable Event inputs
which will always wake up the CPU.

Figure 91. Configurable event triggering logic CPU wakeup

Peripheral interface
APB
interface

Software Falling Rising CPU CPU CPU

interrupt trigger trigger Event Interrupt Pending
event selection selection mask mask request
register register register register register register rcc_fclk_cpu

cpu_it_exti_per(x)
rcc_fclk_cpu

CPU
Asynchronous
Delay

Rising Edge
edge detection
detect Pulse
circuit
Configurable rst generator
Event input(x)

cpu_event
CPU Event(x)

Other CPU Events

ck_sys

d3_wakeup cpu_wakeup
CPU Wakeup(x)

Synch
Other CPU
Wakeups
D3 Wakeup(x)
Other D3 Wakeups
EXTI
MSv41948V1

The Software interrupt event register allows the system to trigger Configurable events by
software, writing the EXTI software interrupt event register (EXTI_SWIER1), the EXTI
software interrupt event register (EXTI_SWIER2), or the EXTI software interrupt event
register (EXTI_SWIER3) register bit.
The rising edge EXTI rising trigger selection register (EXTI_RTSR1), EXTI rising trigger
selection register (EXTI_RTSR2), EXTI rising trigger selection register (EXTI_RTSR3), and
falling edge EXTI falling trigger selection register (EXTI_FTSR1), EXTI falling trigger
selection register (EXTI_FTSR2), EXTI falling trigger selection register (EXTI_FTSR3)
selection registers allow the system to enable and select the Configurable event active
trigger edge or both edges.
The devices feature dedicated interrupt mask registers, namely EXTI interrupt mask register
(EXTI_CPUIMR1) and EXTI interrupt mask register (EXTI_CPUIMR2), EXTI interrupt mask
register (EXTI_CPUIMR3), and EXTI pending register (EXTI_CPUPR1), EXTI pending
register (EXTI_CPUPR2), EXTI pending register (EXTI_CPUPR3) for Configurable events
pending request registers. The CPU pending register will only be set for an unmasked CPU
interrupt. Each event provides a individual CPU interrupt to the CPU NVIC. The
Configurable events interrupts need to be acknowledged by software in the EXTI_CPUPR
register.

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The devices feature dedicated event mask registers, i.e. EXTI event mask register
(EXTI_CPUEMR1), EXTI event mask register (EXTI_CPUEMR2), and EXTI event mask
register (EXTI_CPUEMR3). The enabled event then generates an event on the CPU. All
events for a CPU are OR-ed together into a single CPU event signal. The CPU Pending
register (EXTI_CPUPR) will not be set for an unmasked CPU event.
When a CPU interrupt or CPU event is enabled, the Asynchronous edge detection circuit is
reset by the clocked Delay and Rising edge detect pulse generator. This guarantees that the
CPU clock is woken up before the Asynchronous edge detection circuit is reset.
Note: A detected Configurable event, enabled by the CPU, is only cleared when the CPU wakes
up.

20.3.2 EXTI configurable event input Any wakeup

Figure 92 is a detailed representation of the logic associated with Configurable Event inputs
that can wakeup D3 domain for autonomous Run mode and/or CPU (“Any” target). It
provides the same functionality as the Configurable event input CPU wakeup, with
additional functionality to wake up the D3 domain independently.
When all CPU interrupts and CPU events are disabled, the Asynchronous edge detection
circuit is reset by the D3 domain clocked Delay and Rising edge detect pulse generator.
This guarantees that the D3 domain clock is woken up before the Asynchronous edge
detection circuit is reset.

Table 147. Configurable Event input Asynchronous Edge detector reset

EXTI_C1EMR
EXTI_C1IMR

Asynchronous Edge detector reset by

Both = 0 D3 domain clock rising edge detect pulse generator

At least one = 1 CPU clock rising edge detect pulse generator

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RM0433 Extended interrupt and event controller (EXTI)

Figure 92. Configurable event triggering logic Any wakeup

Peripheral interface
APB
interface

cpu_it_exti_per(x)
Software Falling Rising CPU CPU CPU D3

rcc_fclk_cpu
interrupt trigger trigger Event Interrupt Pending Pending
event selection selection mask mask request mask
register register register register register register register

rcc_fclk_cpu

CPU
Asynchronous
Delay
Other CPU Events

cpu_event
Rising Edge
edge detection
detect Pulse
circuit
Configurable rst generator

d3_it_aiec_per(x) d3_pendclear(x)
Event CPU Event(x)
input(x) 1
ck_fclk_d3
0 D3
D3 Domain Pending
Delay

Rising Edge request

detect Pulse
generator ck_fclk_d3

ck_sys

d3_wakeup cpu_wakeup
Other CPU

Synch
Wakeups
CPU Wakeup(x)

D3 Wakeup(x)
Other D3 Wakeups
EXTI
MSv41953V2

The event triggering logic for “Any” target has additional D3 Pending mask register EXTI D3
pending mask register (EXTI_D3PMR1), EXTI D3 pending mask register (EXTI_D3PMR2),
EXTI D3 pending mask register (EXTI_D3PMR3)and D3 Pending request logic. The D3
Pending request logic will only be set for unmasked D3 Pending events. The D3 Pending
request logic keeps the D3 domain in Run mode until the D3 Pending request logic is
cleared by the selected D3 domain pendclear source.

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Extended interrupt and event controller (EXTI) RM0433

20.3.3 EXTI direct event input CPU wakeup

Figure 93 is a detailed representation of the logic associated with Direct Event inputs waking
up the CPU.
Direct events only provide CPU interrupt enable and CPU event enable functionality.

Figure 93. Direct event triggering logic CPU Wakeup

Peripheral interface
APB
interface

CPU CPU

cpu_it_exti_per(x)
Event mask register Interrupt mask register
1)
rcc_fclk_cpu
ck_sys
Synch
Delay rcc_fclk_cpu

CPU

cpu_event
Other CPU Events
Rising Edge
Asynchronous detect
Pulse generator CPU Event(x)
Rising edge
Direct Event detection circuit
input(x) rst

Failing edge
detect
Pulse generator
ck_sys
ck_sys

d3_wakeup cpu_wakeup
Other CPU Synch
Wakeups
CPU Wakeup(x)

D3 Wakeup(x)
Other D3 Wakeups
EXTI
MSv41954V1

1. The CPU interrupt for asynchronous Direct Event inputs (peripheral Wakeup signals) is synchronized with the CPU clock.
The synchronous Direct Event inputs (peripheral interrupt signals), after the asynchronous edge detection, are directly sent
to the CPU interrupt without resynchronization.

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RM0433 Extended interrupt and event controller (EXTI)

20.3.4 EXTI direct event input Any wakeup

Figure 94 is a detailed representation of the logic associated with Direct Event inputs waking
up D3 domain for autonomous Run mode and/or CPU, (“Any” target). It provides the same
functionality as the Direct event input CPU wakeup, plus additional functionality to wakeup
the D3 domain independently.

Figure 94. Direct event triggering logic Any Wakeup

Peripheral interface

d3_pendclear(x)
APB
interface

CPU CPU D3
Event mask register Interrupt mask register Pending mask register

cpu_it_exti_per(x)
ck_fclk_d3(1) ck_fclk_d3(1)

Synch D3
Pending
(1)
rcc_fclk_cpu request
ck_sys

d3_it_exti_per(x)
Synch
Delay rcc_fclk_cpu

CPU
Direct Event Rising Edge
CPU Event(x)
Asynchronous detect

cpu_event
input(x)
Rising edge Pulse generator
detection circuit Other CPU Events
rst
d3_pending

ck_sys
Failing edge

d3_wakeup cpu_wakeup
detect Other CPU
Synch

Pulse generator Wakeups

CPU Wakeup(x)
ck_sys
Other D3 Wakeups

EXTI D3 Wakeup(x)

MSv41955V1

1. The CPU interrupt and D3 domain interrupt for asynchronous Direct Event inputs (peripheral Wakeup signals) are
synchronized, respectively, with the CPU clock and the D3 domain clock. The synchronous Direct Event inputs (peripheral
interrupt signals), after the asynchronous edge detection, are directly sent to the CPU interrupt and the D3 domain interrupt
without resynchronization in the EXTI.

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20.3.5 EXTI D3 pending request clear selection

Event inputs able to wake up D3 domain for autonomous Run mode have D3 Pending
request logic that can be cleared by the selected D3 pendclear source. For each D3
Pending request a D3 domain pendclear source can be selected from four different inputs.
Figure 95 is a detailed representation of the logic selecting the D3 pendclear source.

Figure 95. D3 domain Pending request clear logic

APB interface
Peripheral interface

D3
pending clear
selection register

Event(x) d3_pendclear_in[0] (DMA_ch6_evt)

D3 d3_pendclear_in[1] (DMA_ch7_evt)
d3_pendclear(x)
pending d3_pendclear_in[2] (LPTIM4 out)
request
d3_pendclear_in[3] (LPTIM5 out)

EXTI
MS40541V2

The D3 Pending request clear selection registers EXTI D3 pending clear selection register
low (EXTI_D3PCR1L), EXTI D3 pending clear selection register high (EXTI_D3PCR1H),
EXTI D3 pending clear selection register low (EXTI_D3PCR2L), EXTI D3 pending clear
selection register high (EXTI_D3PCR2H), EXTI D3 pending clear selection register low
(EXTI_D3PCR3L) and EXTI D3 pending clear selection register high (EXTI_D3PCR3H)
allow the system to select the source to reset the D3 Pending request.

20.4 EXTI event input mapping

For the sixteen GPIO Event inputs the associated IOPORT pin has to be selected in the
SYSCFG register SYSCFG_EXTICRn. The same pin from each IOPORT maps to the
corresponding EXTI Event input.
The wakeup capabilities of each Event input are detailed in Table 148. An Event input can
either wake up the CPU, and in the case of “Any” can also wake up D3 domain for
autonomous Run mode.
The EXTI Event inputs with a connection to the CPU NVIC are indicated in the Connection
to NVIC column. For the EXTI events not having a connection to the NVIC, the peripheral
interrupt is directly connected to the NVIC in parallel with the connection to the EXTI.
All EXTI Event inputs are OR-ed together and connected to the CPU event input (rxev).

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RM0433 Extended interrupt and event controller (EXTI)

Table 148. EXTI Event input mapping

Event input Source Event input type Wakeup target(s) Connection to NVIC

0 - 15 EXTI[15:0] Configurable Any Yes

(1)
16 PVD and AVD Configurable CPU only Yes
17 RTC alarms Configurable CPU only Yes
RTC tamper, RTC timestamp,
18 Configurable CPU only Yes
RCC LSECSS(2)
19 RTC wakeup timer Configurable Any Yes
20 COMP1 Configurable Any Yes
21 COMP2 Configurable Any Yes
22 I2C1 wakeup Direct CPU only Yes
23 I2C2 wakeup Direct CPU only Yes
24 I2C3 wakeup Direct CPU only Yes
25 I2C4 wakeup Direct Any Yes
26 USART1 wakeup Direct CPU only Yes
27 USART2 wakeup Direct CPU only Yes
28 USART3 wakeup Direct CPU only Yes
29 USART6 wakeup Direct CPU only Yes
30 UART4 wakeup Direct CPU only Yes
31 UART5 wakeup Direct CPU only Yes
32 UART7 wakeup Direct CPU only Yes
33 UART8 wakeup Direct CPU only Yes
34 LPUART1 RX wakeup Direct Any Yes
35 LPUART1 TX wakeup Direct Any Yes
36 SPI1 wakeup Direct CPU only Yes
37 SPI2 wakeup Direct CPU only Yes
38 SPI3 wakeup Direct CPU only Yes
39 SPI4 wakeup Direct CPU only Yes
40 SPI5 wakeup Direct CPU only Yes
41 SPI6 wakeup Direct Any Yes
42 MDIO wakeup Direct CPU only Yes
43 USB1 wakeup Direct CPU only Yes
44 USB2 wakeup Direct CPU only Yes
45 Reserved - - -
46 Reserved - - -
47 LPTIM1 wakeup Direct CPU only Yes
48 LPTIM2 wakeup Direct Any Yes

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Table 148. EXTI Event input mapping (continued)

Event input Source Event input type Wakeup target(s) Connection to NVIC

49 LPTIM2 output Configurable Any No(3)

50 LPTIM3 wakeup Direct Any Yes
51 LPTIM3 output Configurable Any No(3)
52 LPTIM4 wakeup Direct Any Yes
53 LPTIM5 wakeup Direct Any Yes
54 SWPMI wakeup Direct CPU only Yes
(4)
55 WKUP1 Direct CPU only Yes
56(4) WKUP2 Direct CPU only Yes
(4)
57 WKUP3 Direct CPU only Yes
58(4) WKUP4 Direct CPU only Yes
59(4) WKUP5 Direct CPU only Yes
(4)
60 WKUP6 Direct CPU only Yes
61 RCC interrupt Direct CPU only No(5)
62 I2C4 Event interrupt Direct CPU only No(5)
63 I2C4 Error interrupt Direct CPU only No(5)
64 LPUART1 global Interrupt Direct CPU only No(5)
65 SPI6 interrupt Direct CPU only No(5)
66 BDMA CH0 interrupt Direct CPU only No(5)
67 BDMA CH1 interrupt Direct CPU only No(5)
68 BDMA CH2 interrupt Direct CPU only No(5)
69 BDMA CH3 interrupt Direct CPU only No(5)
70 BDMA CH4 interrupt Direct CPU only No(5)
71 BDMA CH5 interrupt Direct CPU only No(5)
72 BDMA CH6 interrupt Direct CPU only No(5)
73 BDMA CH7 interrupt Direct CPU only No(5)
74 DMAMUX2 interrupt Direct CPU only No(5)
75 ADC3 interrupt Direct CPU only No(5)
76 SAI4 interrupt Direct CPU only No(5)
77 Reserved - - -
78 Reserved - - -
79 Reserved - - -
80 Reserved - - -
81 Reserved - - -
82 Reserved - - -
83 Reserved - - -

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RM0433 Extended interrupt and event controller (EXTI)

Table 148. EXTI Event input mapping (continued)

Event input Source Event input type Wakeup target(s) Connection to NVIC

84 Reserved - - -
85 HDMI-CEC wakeup Configurable CPU only Yes
86 ETHERNET wakeup Configurable CPU only Yes
87 HSECSS interrupt Direct CPU only No(5)
88 Reserved - - -
1. PVD and AVD signals are OR-ed together on the same EXTI event input.
2. RTC Tamper, RTC timestamp and RCC LSECSS signals are OR-ed together on the same EXTI event input.
3. Not available on CPU NVIC, to be used for system wakeup only or CPU event input (rxev).
4. Signals of WKUP1 to WKUP6 correspond to WKUPn pin+1.
5. Available on CPU NVIC directly from the peripheral

20.5 EXTI functional behavior

The Direct event inputs are enabled in the respective peripheral generating the event. The
Configurable events are enabled by enabling at least one of the trigger edges.
When in Stop mode an event will always wake up the D3 domain. In system Run and Stop
modes an event will always generate an associated D3 domain interrupt. An event will only
wake up the CPU when the event associated CPU interrupt is unmasked and/or the CPU
event is unmasked.

Table 149. Masking functionality

CPU CPU
Configurable
event inputs D3 domain
Interrupt enable Event enable
PRx bits of wakeup
MRx bits of MRx bits of Interrupt Event Wakeup
EXTI_CPUPR
EXTI_CPUIMR EXTI_CPUEMR

0 0 No Masked Masked Masked Yes(1) / Masked(2)

0 1 No Masked Yes Yes Yes
1 0 Status latched Yes Masked Yes Yes
1 1 Status latched Yes Yes Yes Yes
1. Only for Event inputs that allow the system to wakeup D3 domain for autonomous Run mode (Any target).
2. For Event inputs that will always wake up CPU.

For Configurable event inputs, when the enabled edge(s) occur on the event input, an event
request is generated. When the associated CPU interrupt is unmasked, the corresponding
pending PRx bit in EXTI_CPUPR is set and the CPU interrupt signal is activated.
EXTI_CPUPR PRx pending bit shall be cleared by software writing it to ‘1’. This will clear the
CPU interrupt.
For Direct event inputs, when enabled in the associated peripheral, an event request is
generated on the rising edge only. There is no corresponding CPU pending bit. When the
associated CPU interrupt is unmasked the corresponding CPU interrupt signal is activated.

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The CPU event has to be unmasked to generate an event. When the enabled edge(s) occur
on the Event input a CPU event pulse is generated. There is no CPU Event pending bit.
Both a CPU interrupt and a CPU event may be enabled on the same Event input. They will
both trigger the same Event input condition(s).
For the Configurable Event inputs an event input request can be generated by software
when writing a ‘1’ in the software interrupt/event register EXTI_SWIER.
Whenever an Event input is enabled and a CPU interrupt and/or CPU event is unmasked,
the Event input will also generate a D3 domain wakeup next to the CPU wakeup.
Some Event inputs are able to wakeup the D3 domain autonomous Run mode, in this case
the CPU interrupt and CPU event are masked, preventing the CPU to be woken up. Two D3
domain autonomous Run mode wakeup mechanisms are supported:
• D3 domain wakeup without pending (EXTI_D3PMR = 0)
– On a Configurable Event input this mechanism will wake up D3 domain and clear
the D3 domain wakeup signal automatically after the Delay + Rising Edge detect
Pulse generator.
– On a Direct Event input this mechanism will wake up D3 domain and clear the D3
domain wakeup signal after the Direct Event input signal is cleared.
• D3 domain wakeup with pending (EXTI_D3PMR = 1)
– On a Configurable Event input this mechanism will wake up D3 domain and clear
the D3 domain wakeup signal after the Delay + Rising Edge detect Pulse
generator and when the D3 Pending request is cleared.
– On a Direct Event input this mechanism will wake up D3 domain and clear the D3
domain wakeup signal after the Direct Event input signal is cleared and when the
D3 Pending request is cleared.

20.5.1 EXTI CPU interrupt procedure

• Unmask the Event input interrupt by setting the corresponding mask bits in the
EXTI_CPUIMR register.
• For Configurable Event inputs, enable the event input by setting either one or both the
corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
• Enable the associated interrupt source in the CPU NVIC or use the SEVONPEND, so
that an interrupt coming from the CPU interrupt signal is detectable by the CPU after a
WFI/WFE instruction.
– For Configurable event inputs the associated EXTI pending bit needs to be
cleared.

20.5.2 EXTI CPU event procedure

• Unmask the Event input by setting the corresponding mask bits of the EXTI_CPUEMR
register.
• For Configurable Event inputs, enable the event input by setting either one or both the
corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
• The CPU event signal is detected by the CPU after a WFE instruction.
– For Configurable event inputs there is no EXTI pending bit to clear.

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RM0433 Extended interrupt and event controller (EXTI)

20.5.3 EXTI CPU wakeup procedure

• Unmask the Event input by setting at least one of the corresponding mask bits in the
EXTI_CPUIMR and/or EXTI_CPUEMR registers. The CPU wakeup is generated at the
same time as the unmasked CPU interrupt and/or CPU event.
• For Configurable Event inputs, enable the event input by setting either one or both the
corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
• Direct Events will automatically generate a CPU wakeup.

20.5.4 EXTI D3 domain wakeup for autonomous Run mode procedure

• Mask the Event input for waking up the CPU, by clearing both the corresponding mask
bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers.
• For Configurable Event inputs, enable the event input by setting either one or both the
corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
• Direct Events will automatically generate a D3 domain wakeup.
• Select the D3 domain wakeup mechanism in EXTI_D3PMR.
– When D3 domain wakeup without pending (EXTI_PMR = 0) is selected, the
Wakeup will be cleared automatically following the clearing of the Event input.
– When D3 domain wakeup with pending (EXTI_PMR = 1) is selected the Wakeup
needs to be cleared by a selected D3 domain pendclear source.
A pending D3 domain wakeup signal can also be cleared by FW clearing the
associated EXTI_D3PMR register bit.
• After the D3 domain wakeup a D3 domain interrupt is generated.
– Configurable Event inputs will generate a pulse on D3 domain interrupt.
– Direct Event inputs will activate the D3 domain interrupt until the event input is
cleared in the peripheral.

20.5.5 EXTI software interrupt/event trigger procedure

Any of the Configurable Event inputs can be triggered from the software interrupt/event
register (the associated CPU interrupt and/or CPU event shall be enabled by their
respective procedure).
• Enable the Event input by setting at least one of the corresponding edge trigger bits in
the EXTI_RTSR and/or EXTI_FTSR registers.
• Unmask the software interrupt/event trigger by setting at least one of the corresponding
mask bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers.
• Trigger the software interrupt/event by writing “1” to the corresponding bit in the
EXTI_SWIER register.
• The Event input may be disabled by clearing the EXTI_RTSR and EXTI_FTSR register
bits.
Note: An edge on the Configurable event input will also trigger an interrupt/event.
A software trigger can be used to set the D3 Pending request logic, keeping the D3 domain
in Run until the D3 Pending request logic is cleared.

RM0433 Rev 8 771/3353

789
Extended interrupt and event controller (EXTI) RM0433

20.6 EXTI registers

Every register can only be accessed with 32-bit (word). A byte or half-word cannot be read
or written.

20.6.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR21 TR20 TR19 TR18 TR17 TR16
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 TRx: Rising trigger event configuration bit of Configurable Event input x.(1)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
If a rising edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be
set.
Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a
trigger.

20.6.2 EXTI falling trigger selection register (EXTI_FTSR1)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR21 TR20 TR19 TR18 TR17 TR16
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 TRx: Falling trigger event configuration bit of Configurable Event input x.(1)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
If a falling edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be
set.
Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a
trigger.

772/3353 RM0433 Rev 8

RM0433 Extended interrupt and event controller (EXTI)

20.6.3 EXTI software interrupt event register (EXTI_SWIER1)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER SWIER SWIER SWIER SWIER SWIER
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
21 20 19 18 17 16
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 SWIERx: Software interrupt on line x
Will alway return 0 when read.
0: Writing 0 has no effect.
1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW.

20.6.4 EXTI D3 pending mask register (EXTI_D3PMR1)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. MR25 Res. Res. Res. MR21 MR20 MR19 Res. Res. Res.
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 MRx: D3 Pending Mask on Event input x
0: D3 Pending request from Line x is masked. Writing this bit to 0 will also clear the D3
Pending request.
1: D3 Pending request from Line x is unmasked. The D3 domain pending signal when
triggered will keep D3 domain wakeup active until cleared.
Bits 24:22 Reserved, must be kept at reset value.

RM0433 Rev 8 773/3353

789
Extended interrupt and event controller (EXTI) RM0433

Bits 21:19 MRx: D3 Pending Mask on Event input x

0: D3 Pending request from Line x is masked. Writing this bit to 0 will also clear the D3
Pending request.
1: D3 Pending request from Line x is unmasked. The D3 domain pending signal when
triggered will keep D3 domain wakeup active until cleared.
Bits 18:16 Reserved, must be kept at reset value.
Bits 15:0 MRx: D3 Pending Mask on Event input x
0: D3 Pending request from Line x is masked. Writing this bit to 0 will also clear the D3
Pending request.
1: D3 Pending request from Line x is unmasked. The D3 domain pending signal when
triggered will keep D3 domain wakeup active until cleared.

20.6.5 EXTI D3 pending clear selection register low (EXTI_D3PCR1L)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 PCS9 PCS8

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PCSx: D3 Pending request clear input signal selection on Event input x = truncate (n/2)
00: DMA ch6 event selected as D3 domain pendclear source
01: DMA ch7 event selected as D3 domain pendclear source
10: LPTIM4 out selected as D3 domain pendclear source
11: LPTIM5 out selected as D3 domain pendclear source

20.6.6 EXTI D3 pending clear selection register high (EXTI_D3PCR1H)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PCS25 Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. PCS21 PCS20 PCS19 Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw

774/3353 RM0433 Rev 8

RM0433 Extended interrupt and event controller (EXTI)

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 PCSx: D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2)
00: DMA ch6 event selected as D3 domain pendclear source
01: DMA ch7 event selected as D3 domain pendclear source
10: LPTIM4 out selected as D3 domain pendclear source
11: LPTIM5 out selected as D3 domain pendclear source
Bits 17:12 Reserved, must be kept at reset value.
Bits 11:6 PCSx: D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2)
00: DMA ch6 event selected as D3 domain pendclear source
01: DMA ch7 event selected as D3 domain pendclear source
10: LPTIM4 out selected as D3 domain pendclear source
11: LPTIM5 out selected as D3 domain pendclear source
Bits 5:0 Reserved, must be kept at reset value.

20.6.7 EXTI rising trigger selection register (EXTI_RTSR2)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR51 Res. TR49 Res.
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 TRx: Rising trigger event configuration bit of Configurable Event input x+32.(1)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Bit 18 Reserved, must be kept at reset value.
Bit 17 TRx: Rising trigger event configuration bit of Configurable Event input x+32.(1)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Bits 16:0 Reserved, must be kept at reset value.
1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
If a rising edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be
set.
Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a
trigger.

RM0433 Rev 8 775/3353

789
Extended interrupt and event controller (EXTI) RM0433

20.6.8 EXTI falling trigger selection register (EXTI_FTSR2)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR51 Res. TR49 Res.
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 TRx: Falling trigger event configuration bit of Configurable Event input x+32.(1)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
Bit 18 Reserved, must be kept at reset value.
Bit 17 TRx: Falling trigger event configuration bit of Configurable Event input x+32.(1)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
Bits 16:0 Reserved, must be kept at reset value.
1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
If a falling edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be
set.
Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a
trigger.

20.6.9 EXTI software interrupt event register (EXTI_SWIER2)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER SWIER
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
51 49
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 SWIERx: Software interrupt on line x+32
Will alway return 0 when read.
0: Writing 0 has no effect.
1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW.

776/3353 RM0433 Rev 8

RM0433 Extended interrupt and event controller (EXTI)

Bit 18 Reserved, must be kept at reset value.

Bit 17 SWIERx: Software interrupt on line x+32
Will alway return 0 when read.
0: Writing 0 has no effect.
1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW.
Bits 16:0 Reserved, must be kept at reset value.

20.6.10 EXTI D3 pending mask register (EXTI_D3PMR2)

Address offset: 0x2C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MR53 MR52 MR51 MR50 MR49 MR48
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. MR41 Res. Res. Res. Res. Res. MR35 MR34 Res. Res.

rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:16 MRx: D3 Pending Mask on Event input x+32
0: D3 Pending request from Line x+32 is masked. Writing this bit to 0 will also clear the D3
Pending request.
1: D3 Pending request from Line x+32 is unmasked. The D3 domain pending signal when
triggered will keep D3 domain wakeup active until cleared.
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 MRx: D3 Pending Mask on Event input x+32
0: D3 Pending request from Line x+32 is masked. Writing this bit to 0 will also clear the D3
Pending request.
1: D3 Pending request from Line x+32 is unmasked. The D3 domain pending signal when
triggered will keep D3 domain wakeup active until cleared.
Bits 8:4 Reserved, must be kept at reset value.
Bits 3:2 MRx: D3 Pending Mask on Event input x+32
0: D3 Pending request from Line x+32 is masked. Writing this bit to 0 will also clear the D3
Pending request.
1: D3 Pending request from Line x+32 is unmasked. The D3 domain pending signal when
triggered will keep D3 domain wakeup active until cleared.
Bits 1:0 Reserved, must be kept at reset value.

RM0433 Rev 8 777/3353

789
Extended interrupt and event controller (EXTI) RM0433

20.6.11 EXTI D3 pending clear selection register low (EXTI_D3PCR2L)

Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PCS41 Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PCS35 PCS34 Res. Res. Res. Res.

rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 PCSx: D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2)
00: DMA ch6 event selected as D3 domain pendclear source
01: DMA ch7 event selected as D3 domain pendclear source
10: LPTIM4 out selected as D3 domain pendclear source
11: LPTIM5 out selected as D3 domain pendclear source
Bits 17:8 Reserved, must be kept at reset value.
Bits 7:4 PCSx: D3 Pending request clear input signal selection on Event input x= truncate ((n+64)/2)
00: DMA ch6 event selected as D3 domain pendclear source
01: DMA ch7 event selected as D3 domain pendclear source
10: LPTIM4 out selected as D3 domain pendclear source
11: LPTIM5 out selected as D3 domain pendclear source
Bits 3:0 Reserved, must be kept at reset value.

20.6.12 EXTI D3 pending clear selection register high (EXTI_D3PCR2H)

Address offset: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. PCS53 PCS52 PCS51 PCS50 PCS49 PCS48

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 PCSx: D3 Pending request clear input signal selection on Event input x= truncate ((n+96)/2)
00: DMA ch6 event selected as D3 domain pendclear source
01: DMA ch7 event selected as D3 domain pendclear source
10: LPTIM4 out selected as D3 domain pendclear source
11: LPTIM5 out selected as D3 domain pendclear source

778/3353 RM0433 Rev 8

RM0433 Extended interrupt and event controller (EXTI)

20.6.13 EXTI rising trigger selection register (EXTI_RTSR3)

Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. TR86 TR85 TR84 Res. TR82 Res. Res.
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:20 TRx: Rising trigger event configuration bit of Configurable Event input x+64.(1)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Bit 19 Reserved, must be kept at reset value.
Bit 18 TRx: Rising trigger event configuration bit of Configurable Event input x+64.(1)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Bits 17:0 Reserved, must be kept at reset value.
1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
If a rising edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be
set.
Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a
trigger.

20.6.14 EXTI falling trigger selection register (EXTI_FTSR3)

Address offset: 0x44
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. TR86 TR85 TR84 Res. TR82 Res. Res.
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:20 TRx: Falling trigger event configuration bit of Configurable Event input x+64.(1)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line

RM0433 Rev 8 779/3353

789
Extended interrupt and event controller (EXTI) RM0433

Bit 19 Reserved, must be kept at reset value.

Bit 18 TRx: Falling trigger event configuration bit of Configurable Event input x+64.(1)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
Bits 17:0 Reserved, must be kept at reset value.
1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
If a falling edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be
set.
Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a
trigger.

20.6.15 EXTI software interrupt event register (EXTI_SWIER3)

Address offset: 0x48
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER SWIER SWIER SWIER
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
86 85 84 82
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:20 SWIERx: Software interrupt on line x+64
Will alway return 0 when read.
0: Writing 0 has no effect.
1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW.
Bit 19 Reserved, must be kept at reset value.
Bit 18 SWIERx: Software interrupt on line x+64
Will alway return 0 when read.
0: Writing 0 has no effect.
1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW.
Bits 17:0 Reserved, must be kept at reset value.

20.6.16 EXTI D3 pending mask register (EXTI_D3PMR3)

Address offset: 0x4C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. MR88 Res. Res. Res. Res. Res. Res. Res. Res.
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

780/3353 RM0433 Rev 8

RM0433 Extended interrupt and event controller (EXTI)

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 MRx: D3 Pending Mask on Event input x+64
0: D3 Pending request from Line x+64 is masked. Writing this bit to 0 will also clear the D3
Pending request.
1: D3 Pending request from Line x+64 is unmasked. The D3 domain pending signal when
triggered will keep D3 domain wakeup active until cleared.
Bits 23:0 Reserved, must be kept at reset value.

20.6.17 EXTI D3 pending clear selection register low (EXTI_D3PCR3L)

Address offset: 0x50
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:0 Reserved, must be kept at reset value.

20.6.18 EXTI D3 pending clear selection register high (EXTI_D3PCR3H)

Address offset: 0x54
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PCS88

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:16 PCSx: D3 Pending request clear input signal selection on Event input x= truncate
((n+160)/2)
00: DMA ch6 event selected as D3 domain pendclear source
01: DMA ch7 event selected as D3 domain pendclear source
10: LPTIM4 out selected as D3 domain pendclear source
11: LPTIM5 out selected as D3 domain pendclear source
Bits 15:0 Reserved, must be kept at reset value.

RM0433 Rev 8 781/3353

789
Extended interrupt and event controller (EXTI) RM0433

20.6.19 EXTI interrupt mask register (EXTI_CPUIMR1)

Address offset: 0x80
Reset value: 0xFFC0 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31 MR30 MR29 MR28 MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 MRx: CPU interrupt Mask on Direct Event input x(1)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
Bits 21:0 MRx: CPU interrupt Mask on Configurable Event input x (2)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
1. The reset value for Direct Event inputs is set to ‘1’ in order to enable the interrupt by default.
2. The reset value for Configurable Event inputs is set to ‘0’ in order to disable the interrupt by default.

20.6.20 EXTI event mask register (EXTI_CPUEMR1)

Address offset: 0x84
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31 MR30 MR29 MR28 MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MRx: CPU Event mask on Event input x

0: Event request from Line x is masked
1: Event request from Line x is unmasked

782/3353 RM0433 Rev 8

RM0433 Extended interrupt and event controller (EXTI)

20.6.21 EXTI pending register (EXTI_CPUPR1)

Address offset: 0x88
Reset value: undefined

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR21 PR21 PR19 PR18 PR17 PR16
rc1 rc1 rc1 rc1 rc1 rc1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0

rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 PRx: Configurable event inputs x Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.

20.6.22 EXTI interrupt mask register (EXTI_CPUIMR2)

Address offset: 0x90
Reset value: 0xFFF5 FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR63 MR62 MR61 MR60 MR59 MR58 MR57 MR56 MR55 MR54 MR53 MR52 MR51 MR50 MR49 MR48
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MR47 MR46 Res. MR44 MR43 MR42 MR41 MR40 MR39 MR38 MR37 MR36 MR35 MR34 MR33 MR32

rw rw 1 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 MRx: CPU Interrupt Mask on Direct Event input x+32(1)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
Bit 19 MRx: CPU interrupt Mask on Configurable Event input x+32 (2)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
Bit 18 MRx: CPU Interrupt Mask on Direct Event input x+32 (1)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
Bit 17 MRx: CPU interrupt Mask on Configurable Event input x+32 (2)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked

RM0433 Rev 8 783/3353

789
Extended interrupt and event controller (EXTI) RM0433

Bits 16:14 MRx: CPU Interrupt Mask on Direct Event input x+32 (1)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
Bit 13 Reserved, must be kept at reset value (1).
Bits 12:0 MRx: CPU Interrupt Mask on Direct Event input x+32 (1)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
1. The reset value for Direct Event inputs is set to ‘1’ in order to enable the interrupt by default.
2. The reset value for Configurable Event inputs is set to ‘0’ in order to disable the interrupt by default.

20.6.23 EXTI event mask register (EXTI_CPUEMR2)

Address offset: 0x94
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR63 MR62 MR61 MR60 MR59 MR58 MR57 MR56 MR55 MR54 MR53 MR52 MR51 MR50 MR49 MR48
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MR47 MR46 Res. MR44 MR43 MR42 MR41 MR40 MR39 MR38 MR37 MR36 MR35 MR34 MR33 MR32

rw rw 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 MRx: CPU Event mask on Event input x+32

0: Event request from Line x is masked
1: Event request from Line x is unmasked
Bit 13 Reserved, must be kept at reset value.
Bits 12:0 MRx: CPU Event mask on Event input x+32
0: Event request from Line x is masked
1: Event request from Line x is unmasked

20.6.24 EXTI pending register (EXTI_CPUPR2)

Address offset: 0x98
Reset value: undefined

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR51 Res. PR49 Res.
rc1 rc1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

784/3353 RM0433 Rev 8

RM0433 Extended interrupt and event controller (EXTI)

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 PRx: Configurable event inputs x+32 Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.
Bit 18 Reserved, must be kept at reset value.
Bit 17 PRx: Configurable event inputs x+32 Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.
Bits 16:0 Reserved, must be kept at reset value.

20.6.25 EXTI interrupt mask register (EXTI_CPUIMR3)

Address offset: 0xA0
Reset value: 0x018B FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. MR88 MR87 MR86 MR85 MR84 Res. MR82 Res. MR80
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MR79 MR78 MR77 MR76 MR75 MR74 MR73 MR72 MR71 MR70 MR69 MR68 MR67 MR66 MR65 MR64

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:23 MRx: CPU Interrupt Mask on Direct Event input x+64 (1)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
Bits 22:20 MRx: CPU interrupt Mask on Configurable Event input x+64 (2)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
Bit 19 Reserved, must be kept at reset value (1).
Bit 18 MRx: CPU interrupt Mask on Configurable Event input x+64 (2)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
Bit 17 Reserved, must be kept at reset value (1).
Bits 16:0 MRx: CPU Interrupt Mask on Direct Event input x+64 (1)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is unmasked
1. The reset value for Direct Event inputs is set to ‘1’ in order to enable the interrupt by default.
2. The reset value for Configurable Event inputs is set to ‘0’ in order to disable the interrupt by default.

RM0433 Rev 8 785/3353

789
Extended interrupt and event controller (EXTI) RM0433

20.6.26 EXTI event mask register (EXTI_CPUEMR3)

Address offset: 0xA4
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. MR88 MR87 MR86 MR85 MR84 Res. MR82 Res. MR80
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MR79 MR78 MR77 MR76 MR75 MR74 MR73 MR72 MR71 MR70 MR69 MR68 MR67 MR66 MR65 MR64

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:0 MRx: CPU Event mask on Event input x+64
0: Event request from Line x is masked
1: Event request from Line x is unmasked

20.6.27 EXTI pending register (EXTI_CPUPR3)

Address offset: 0xA8
Reset value: undefined

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PR86 PR85 PR84 Res. PR82 Res. Res.
rc1 rc1 rc1 rc1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:20 PRx: Configurable event inputs x+64 Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.
Bit 19 Reserved, must be kept at reset value.
Bit 18 PRx: Configurable event inputs x+64 Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.
Bits 17:0 Reserved, must be kept at reset value.

786/3353 RM0433 Rev 8

 0x40
0x34
0x30
0x28
0x24
0x20
0x14
0x10
0x08
0x04
0x00

0x2C
0x0C
Offset
RM0433

20.6.28

name
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

EXTI_FTSR2
EXTI_FTSR1

EXTI_RTSR3
EXTI_RTSR2
EXTI_RTSR1

EXTI_SWIER2
EXTI_SWIER1

EXTI_D3PMR2
EXTI_D3PMR1

EXTI_D3PCR2L
EXTI_D3PCR1L

EXTI_D3PCR2H
EXTI_D3PCR1H
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
PCS[15]

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
PCS[14]

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
PCS[13]

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
EXTI register map

0
0
Res. Res. Res. Res. Res. Res. Res. Res. MR[25] Res. Res. Res. 25
PCS[12]

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
PCS[11]

0
0
TR[86] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0
0
0
0

TR[85] Res. Res. Res. Res. Res. Res. 21

PCS[10]

0
0
0
0
0
0
0

TR[84] Res. Res. Res. Res. Res. Res. 20

0
0
0
0

0
0

0
0
0
0
0

Res. Res. SWIER[51] TR[51] TR[51]

MR[21:19]
PCS[41] PCS[25] PCS[9]
19

0
0
0
0

0
0
0
0

TR[82] Res. Res. Res. Res. Res. 18

MR[53:48]
0
0
0

0
0
0
0
0

Res. Res. Res. SWIER[49] TR[49] TR[49] Res. Res.

RM0433 Rev 8
PCS[8]
17

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 15

PCS[7]

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 14

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 13

PCS[6]
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 12

0

0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. 11
PCS[53] PCS[21] PCS[5]
0

0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. 10
TR[21:0]
TR[21:0]

0
0
0
0
0
0

0
Res. Res. MR[41] Res. Res. Res.
SWIER[21:0]

PCS[52] PCS[20] PCS[4]

9
The following table gives the EXTI register map and the reset values.

0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. 8

0
0

0
0
0
0
0

0
Res. Res. Res. Res. Res. 7
MR[15:0]

PCS[51] PCS[35] PCS[19] PCS[3]

0
0

0
0
0
0
0

0
Res. Res. Res. Res. Res. 6

0
0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. 5
PCS[50] PCS[34] PCS[2]

0
0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. 4
Table 150. Asynchronous interrupt/event controller register map and reset values

0
0
0
0
0
0

Res. Res. MR[35] Res. Res. Res. Res. 3

PCS[49] PCS[1]
0

0
0
0
0
0

0
Res. Res. MR[34] Res. Res. Res. Res. 2
0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. Res. 1
PCS[48] PCS[0]
0
0
0
0
0

0
Res. Res. Res. Res. Res. Res. Res.

787/3353
0
Extended interrupt and event controller (EXTI)

789
 0x98
0x94
0x90
0x88
0x84
0x80
0x54
0x50
0x48
0x44

0xA4
0xA0
0x7C
0x4C

0x58-
Offset

788/3353
name

Reserved
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
EXTI_FTSR3

EXTI_SWIER3

EXTI_CPUPR2
EXTI_CPUPR1
EXTI_D3PMR3

EXTI_CPUIMR3
EXTI_CPUIMR2
EXTI_CPUIMR1
EXTI_D3PCR3L

EXTI_D3PCR3H

EXTI_CPUEMR3
EXTI_CPUEMR2
EXTI_CPUEMR1

0
1
0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
1
0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
1
0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
1
0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
1
0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
1
0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26

MR[31:22]

0
1
0
1
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

MR[63:52]
0

0
1
0
1
0
1
MR[88] Res. Res. Res. Res. MR[88] Res. Res. 24

0
1
0
1
0
1
MR[87] Res. Res. Res. Res. Res. Res. Res. 23
0
0

0
0
0
1
0
1
MR[86] Res. Res. Res. Res. Res. SWIER[86] TR[86] 22

MR[63:46]
0
0

0
0
0
1
0
0
0
MR[85] Res. Res. Res. Res. SWIER[85] TR[85]

MR[88:84]
21
Extended interrupt and event controller (EXTI)

0
0

0
0
0
1
0
0
0
MR[84] Res. Res. Res. Res. SWIER[84] TR[84] 20

0
0
0
0
0
0
Res. Res. PR[51] MR[51] Res. Res. Res. Res. Res. 19
0
0

0
0
0
1
0
0
0
MR[82] MR[82] Res. MR[50] Res. Res. Res. SWIER[82] TR[82] 18

0
0
0
0
0
0
0
Res. Res. PR[49] MR[49] Res. Res. Res. Res.

RM0433 Rev 8
PCS[88]
17

0
1
0
1
0
0

0
0
Res. Res. Res. Res. Res. 16

0
1
0
1
0
0
0
Res. Res. Res. Res. Res. Res. 15

MR[31:0]

0
1
0
1
0
0
0
Res. Res. Res. Res. Res. Res.

MR[48:46]
14

0
1
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. 13

0
1
0
1
0
0
0
Res. Res. Res. Res. Res. Res. 12

0
1
0
1
0
0
0
Res. Res. Res. Res. Res. Res. 11

0
1
0
1
0
0
Res. 0 Res. Res. Res. Res. Res. 10

PR[21:0]
MR[21:0]

0
1
0
1
0
0
0
Res. Res. Res. Res. Res. Res. 9

0
1
0
1
0
0
0

Res. Res. Res. Res. Res. Res. 8

0
1
0
1
0
0
0

Res. Res. Res. Res. Res. Res.

MR[80:64]
MR[80:64]
7

0
1
0
1
0
0
0

Res. Res. Res. Res. Res. Res. 6

0
1
0
1
0
0
0

Res. Res. Res. Res. Res. Res.

MR[44:32]
MR[44:32]
5

0
1
0
1
0
0
0

Res. Res. Res. Res. Res. Res. 4

0
1
0
1
0
0
0

Res. Res. Res. Res. Res. Res. 3

0
1
0
1
0
0
0

Res. Res. Res. Res. Res. Res. 2

0
1
0
1
0
0
0

Res. Res. Res. Res. Res. Res. 1

Table 150. Asynchronous interrupt/event controller register map and reset values (continued)

0
1
0
1
0
0
0

Res. Res. Res. Res. Res. Res.

RM0433

0
 0xA8

0xBC
0xAC-
Offset
RM0433

name

Reserved
Register

Reset value
EXTI_CPUPR3
Res. Res. 31
Res. Res. 30
Res. Res. 29
Res. Res. 28
Res. Res. 27
Res. Res. 26
Res. Res. 25
Res. Res. 24
Res. Res. 23
0

Res. PR[86] 22
0

Res. PR[85] 21
0

Res. PR[84] 20
Res. Res. 19
0

Res. PR[82] 18
Res. Res.

RM0433 Rev 8
17
Res. Res. 16
Res. Res. 15
Res. Res. 14
Res. Res. 13
Res. Res. 12
Res. Res. 11
Res. Res. 10
Res. Res. 9
Res. Res.
Refer to Section 2.3 on page 129 for the register boundary addresses.

8
Res. Res. 7
Res. Res. 6
Res. Res. 5
Res. Res. 4
Res. Res. 3
Res. Res. 2
Res. Res. 1
Table 150. Asynchronous interrupt/event controller register map and reset values (continued)

Res. Res.

789/3353
0
Extended interrupt and event controller (EXTI)

789
Cyclic redundancy check calculation unit (CRC) RM0433

21 Cyclic redundancy check calculation unit (CRC)

21.1 Introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16-
or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.

21.2 CRC main features

• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
• Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32
bits)
• Handles 8-,16-, 32-bit data size
• Programmable CRC initial value
• Single input/output 32-bit data register
• Input buffer to avoid bus stall during calculation
• CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
• General-purpose 8-bit register (can be used for temporary storage)
• Reversibility option on I/O data
• Accessed through AHB slave peripheral by 32-bit words only, with the exception of
CRC_DR register that can be accessed by words, right-aligned half-words and right-
aligned bytes

790/3353 RM0433 Rev 8

RM0433 Cyclic redundancy check calculation unit (CRC)

21.3 CRC functional description

21.3.1 CRC block diagram

Figure 96. CRC calculation unit block diagram

32-bit AHB bus

read access write access 32-bit accesses

Data register Data register

crc_hclk
(output) (input)
CRC_INIT

CRC_CR
CRC computation
CRC_POL

CRC_IDR

MS19882V3

21.3.2 CRC internal signals

Table 151. CRC internal input/output signals

Signal name Signal type Description

crc_hclk Digital input AHB clock

21.3.3 CRC operation

The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).
Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. For the other registers only 32-bit accesses are allowed.
The duration of the computation depends on data width:
• 4 AHB clock cycles for 32 bits
• 2 AHB clock cycles for 16 bits
• 1 AHB clock cycles for 8 bits
An input buffer allows a second data to be immediately written without waiting for any wait
states due to the previous CRC calculation.

RM0433 Rev 8 791/3353

796
Cyclic redundancy check calculation unit (CRC) RM0433

The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.
The input data can be reversed to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.
For example, 0x1A2B3C4D input data are used for CRC calculation as:
• 0x58D43CB2 with bit-reversal done by byte
• 0xD458B23C with bit-reversal done by half-word
• 0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level. For example, 0x11223344 output data are converted to
0x22CC4488.
The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.

Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the
polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the
POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.
Note: The type of an even polynomial is X+X2+..+Xn, while the type of an odd polynomial is
1+X+X2+..+Xn.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the
CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can
not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the
application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.

792/3353 RM0433 Rev 8

RM0433 Cyclic redundancy check calculation unit (CRC)

21.4 CRC registers

The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned
bytes. For the other registers only 32-bit accesses are allowed.

21.4.1 CRC data register (CRC_DR)

Address offset: 0x00
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DR[31:0]: Data register bits

This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the correct
value.

21.4.2 CRC independent data register (CRC_IDR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IDR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IDR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IDR[31:0]: General-purpose 32-bit data register bits

These bits can be used as a temporary storage location for four bytes.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register

RM0433 Rev 8 793/3353

796
Cyclic redundancy check calculation unit (CRC) RM0433

21.4.3 CRC control register (CRC_CR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_
Res. Res. Res. Res. Res. Res. Res. Res. REV_IN[1:0] POLYSIZE[1:0] Res. Res. RESET
OUT
rw rw rw rw rw rs

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
This bitfield controls the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
Bits 4:3 POLYSIZE[1:0]: Polynomial size
These bits control the size of the polynomial.
00: 32 bit polynomial
01: 16 bit polynomial
10: 8 bit polynomial
11: 7 bit polynomial
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the
value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by
hardware

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21.4.4 CRC initial value (CRC_INIT)

Address offset: 0x10
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CRC_INIT[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_INIT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value

This register is used to write the CRC initial value.

21.4.5 CRC polynomial (CRC_POL)

Address offset: 0x14
Reset value: 0x04C1 1DB7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

POL[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

POL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 POL[31:0]: Programmable polynomial

This register is used to write the coefficients of the polynomial to be used for CRC
calculation.
If the polynomial size is less than 32 bits, the least significant bits have to be used to program
the correct value.

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21.4.6 CRC register map

Table 152. CRC register map and reset values

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

CRC_DR DR[31:0]
0x00
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CRC_IDR IDR[31:0]
0x04
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POLYSIZE[1:0]
REV_IN[1:0]
REV_OUT

RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
CRC_CR
0x08

Reset value 0 0 0 0 0 0

CRC_INIT CRC_INIT[31:0]
0x10
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CRC_POL POL[31:0]
0x14
Reset value 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1

Refer to Section 2.3 on page 129 for the register boundary addresses.

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22 Flexible memory controller (FMC)

The flexible memory controller (FMC) includes three memory controllers:

• The NOR/PSRAM memory controller
• The NAND memory controller
• The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

22.1 FMC main features

The FMC functional block makes the interface with: synchronous and asynchronous static
memories, SDRAM memories, and NAND flash memory. Its main purposes are:
• to translate AXI transactions into the appropriate external device protocol
• to meet the access time requirements of the external memory devices
All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique Chip Select. The FMC performs
only one access at a time to an external device.
The main features of the FMC are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM (4 memory banks)
– NAND flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• Burst mode support for faster access to synchronous devices such as NOR flash
memory, PSRAM and SDRAM)
• Programmable continuous clock output for asynchronous and synchronous accesses
• 8-,16- or 32-bit wide data bus
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write enable and byte lane select outputs for use with PSRAM, SRAM and SDRAM
devices
• External asynchronous wait control
• Write FIFO with 16 x32-bit depth
The Write FIFO is common to all memory controllers and consists of:
– a Write Data FIFO which stores the data to be written to the memory
– a Write Address FIFO which stores the address (up to 28 bits) plus the data size
(up to 2 bits). When operating in Burst mode, only the start address is stored
except when crossing a page boundary (for PSRAM and SDRAM). In this case,
the burst is broken into two FIFO entries.
• Cacheable Read FIFO with 6 x64-bit depth (6 x14-bit address tag) for SDRAM
controller.
At startup the FMC pins must be configured by the user application. The FMC I/O pins which
are not used by the application can be used for other purposes.

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The FMC registers that define the external device type and associated characteristics are
set at boot time and do not change until the next reset or power-up. However, only a few bits
can be changed on-the-fly:
• ECCEN and PBKEN bits in the FMC_PCR register
• IFS, IRS and ILS bits in the FMC_SR register
• MODE[2:0], CTB1/CTB2, NRFS and MRD bits in the FMC_SDCMR register
• REIE and CRE bits in the FMC_SDRTR register.
Follow the below sequence to modify parameters while the FMC is enabled:
1. First disable the FMC to prevent further accesses to any memory controller while the
register is modified.
2. Update all required configurations.
3. Enable the FMC again.
When the SDRAM controller is used, if the SDCLK Clock ratio or refresh rate has to be
modified after initialization phase, the following procedure must be followed.
1. Put the SDRAM device in Self-refresh mode.
2. Disable the FMC by resetting the FMCEN bit in the FMC_BCR1 register.
3. Update the required parameters.
4. Enable the FMC once all parameters have been updated.
5. Then, send the Clock Configuration Enable command to exit Self-fresh mode.

22.2 FMC block diagram

The FMC consists of the following main blocks:
• The NOR flash/PSRAM/SRAM controller
• The NAND controller
• The SDRAM controller
• The AXI interface
• The AHB interface (including the FMC configuration registers)
The block diagram is shown in the figure below.

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Figure 97. FMC block diagram

fmc_it to NVIC

FMC_NL (or NADV) NOR/PSRAM

FMC_CLK signals
NOR/PSRAM
NOR / SRAM shared
memory FMC_NBL[3:0]
signals
controller
FMC_A[25:0]
Shared signals
FMC_D[31:0]
fmc_hclk
AXI/AHB FMC_NE[4:1]
interface &
FMC_NOE NOR / PSRAM / SRAM
fmc_ker_ck Configuration
registers FMC_NWE shared signals
FMC_NWAIT

NAND flash
memory FMC_NCE
32-bit AHB bus

controller NAND signals

FMC_INT
64-bit AXI bus

FMC_SDCLK
FMC_SDNWE
SDRAM FMC_SDCKE[1:0]
SDRAM signals
controller FMC_SDNE[1:0]
FMC_NRAS
FMC_NCAS

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22.3 FMC internal signals

Table 153 gives the list of FMC internal signals. FMC pins (or external signals) are
described in Section 22.7.1: External memory interface signals.

Table 153. FMC pins

Names Signal type Description

fmc_it Digital output FMC interrupt

fmc_ker_ck Digital input FMC kernel clock
fmc_hclk Digital input FMC interface clock

22.4 AHB interface

The AHB slave interface allows internal CPUs to configure the FMC registers.
The AHB clock (fmc_hclk) is the reference clock for the FMC register accesses.

22.5 AXI interface

The AXI slave interface allows internal CPUs and other bus master peripherals to access
the external memories.
AXI transactions are translated into the external device protocol. As the AXI data bus is 64-
bit wide, the AXI transactions might be split into several consecutive 32-, 16- or 8-bit
accesses according to data size accesses. The FMC Chip Select (FMC_NEx) does not
toggle between consecutive accesses except in case of accesses in mode D when the
Extended mode is enabled.
The FMC generates an AXI slave error when one of the following conditions is met:
• Reading or writing to an FMC bank (Bank 1 to 4) which is not enabled.
• Reading or writing to the NOR flash bank while the FACCEN bit is reset in the
FMC_BCRx register.
• Writing to a write protected SDRAM bank (WP bit set in the FMC_SDCRx register).
• Violation of the SDRAM address range (access to reserved address range)
• Attempting to read/write access from/to SDRAM bank when it is not yet initialized
The FMC generates an AXI decoder error when ADDR[31:28] address bits are not
supported by the FMC bank base address following the BMAP[1:0] bits configuration.
The kernel clock for the FMC is the asynchronous fmc_ker_ck clock (refer to Section 8:
Reset and Clock Control (RCC) for fmc_ker_ck clock source selection).

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22.5.1 Supported memories and transactions

General transaction rules
The requested AXI transaction data size can be 8-, 16-, 32- or 64-bit wide whereas the
accessed external device has a fixed data width. The best performance is always achieved
with aligned AXI transactions whose size matches the external device data width.
When AXI transaction data size is different from the device data width, the result depends
on the following factors:
• AXI transaction data size is greater than the device data width:
– Read/Write transactions: the FMC splits the AXI transaction into smaller
consecutive accesses matching the external device data width.
• AXI transaction data size is smaller than the external device data width and the device
supports byte selection (SRAM, PSRAM, SDRAM):
– Write transactions, the FMC manages the transaction using the byte lane signals.
– Read transactions, the FMC returns all bytes according to the external device data
width. The useless bytes are discarded by the system.
• AXI transaction data size is smaller than the external device data width and the device
does not support byte selection (NOR and NAND flash memories):
– Write transactions: the FMC writes some irrelevant bytes which may corrupt the
external device
– Read transactions: the FMC returns all bytes according to the external device data
width. The useless bytes are discarded by the system.
Caution: Address alignment
• Read transactions with unaligned addresses (such as half-word starting at an odd
address) are not supported by the FMC.
• Write transactions with unaligned addresses
Their support depends on byte selection availability on the external device:
– If the device does not support byte selection (NOR and NAND flash memories),
narrow write transactions and/or unaligned write transaction are not supported
since the FMC would write irrelevant bytes and corrupt the external device.

Wrap support for NOR flash/PSRAM and SDRAM

The synchronous memories must be configured in Linear burst mode of undefined length as
not all masters can issue wrap transactions.
If a master generates a wrap transaction:
• The read is split into two linear burst transactions.
• The write is split into two linear burst transactions if the write FIFO is enabled and into
several linear burst transactions if the write FIFO is disabled.

Configuration registers
The FMC can be configured through a set of registers. Refer to Section 22.7.6, for a
detailed description of the NOR flash/PSRAM controller registers. Refer to Section 22.8.7,
for a detailed description of the NAND flash registers and to Section 22.9.5 for a detailed
description of the SDRAM controller registers.

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22.6 External device address mapping

From the FMC point of view, the external memory is divided into fixed-size banks of
256 Mbytes each (see Figure 98):
• Bank 1 is used to address up to 4 NOR flash memory or PSRAM devices. This bank is
split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows:
– Bank 1 - NOR/PSRAM 1
– Bank 1 - NOR/PSRAM 2
– Bank 1 - NOR/PSRAM 3
– Bank 1 - NOR/PSRAM 4
• Bank 2 is used for SDRAM device, SDRAM bank 1 or SDRAM bank 2 depending on
BMAP bits configuration.
• Bank 3 is used to address NAND flash memory devices.The MPU memory attribute for
this space must be reconfigured by software to Device.
• Bank 5 and 6 are used to address SDRAM devices (1 device per bank).
For each bank the type of memory to be used can be configured by the user application
through the Configuration register.

Figure 98. FMC memory banks (default mapping)

Supported
Address Bank
memory type
0x6000 0000
NOR/PSRAM/
Bank 1
SRAM
4 x 64 MB
0x6FFF FFFF
0x7000 0000
SDRAM Bank
1 4 x 64 MB
0x7FFF FFFF
0x8000 0000
Bank 3 NAND Flash
4 x 64 MB memory
0x8FFF FFFF
0x9000 0000
Bank 4
Not used by FMC

0x9FFF FFFF
0xC000 0000
SDRAM Bank 1
4 x 64 MB
0xCFFF FFFF SDRAM

0xD000 0000
SDRAM Bank 2
4 x 64 MB
0xDFFF FFFF
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The FMC bank mapping can be modified through the BMAP[1:0] bits in the FMC_BCR1
register. Table 154 shows the configuration to swap the NOR/PSRAM bank with SDRAM
banks or remap the SDRAM bank2, thus allowing to access the SDRAM banks at two
different address mapping.

Table 154. FMC bank mapping options

BMAP[1:0]=01
BMAP[1:0]=10
BMAP[1:0]=00 NOR/PSRAM and
Start -End address SDRAM bank 2
(Default mapping) SDRAM banks
remapped
swapped
0x6000 0000 - 0x6FFF FFFF NOR/PSRAM bank SDRAM bank1 NOR/PSRAM bank
0x7000 0000 - 0x7FFF FFFF SDRAM bank1 SDRAM bank2 SDRAM bank2
0x8000 0000 - 0x8FFF FFFF NAND bank NAND bank NAND bank
0x9000 0000 - 0x9FFF FFFF Not used by FMC
0xC000 0000 - 0xCFFF FFFF SDRAM bank1 NOR/PSRAM bank SDRAM bank1
0xD000 0000 - 0xDFFF FFFF SDRAM bank2 SDRAM bank2 SDRAM bank2

22.6.1 NOR/PSRAM address mapping

ADDR[27:26] bits are used to select one of the four memory banks as shown in Table 155.

Table 155. NOR/PSRAM bank selection

ADDR[27:26](1) Selected bank

00 Bank 1 - NOR/PSRAM 1
01 Bank 1 - NOR/PSRAM 2
10 Bank 1 - NOR/PSRAM 3
11 Bank 1 - NOR/PSRAM 4
1. ADDR are internal address lines that are translated to external memory.

The ADDR[25:0] bits contain the external memory address. Since ADDR is a byte address
whereas the memory is addressed at word level, the address actually issued to the memory
varies according to the memory data width, as shown in the following table.

Table 156. NOR/PSRAM External memory address

Memory width(1) Data address issued to the memory Maximum memory capacity (bits)

8-bit ADDR[25:0] 64 Mbytes x 8 = 512 Mbit

16-bit ADDR[25:1] >> 1 64 Mbytes/2 x 16 = 512 Mbit
32-bit ADDR[25:2] >> 2 64 Mbytes/4 x 32 = 512 Mbit
1. In case of a 16-bit external memory width, the FMC will internally use ADDR[25:1] to generate the address
for external memory FMC_A[24:0]. In case of a 32-bit memory width, the FMC will internally use
ADDR[25:2] to generate the external address.
Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0].

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22.6.2 NAND flash memory address mapping

The NAND bank is divided into memory areas as indicated in Table 157.

Table 157. NAND memory mapping and timing registers

Start address End address FMC bank Memory space Timing register

0x8800 0000 0x8BFF FFFF Attribute FMC_PATT (0x8C)

Bank 3 - NAND flash
0x8000 0000 0x83FF FFFF Common FMC_PMEM (0x88)

For NAND flash memory, the common and attribute memory spaces are subdivided into
three sections (see in Table 158 below) located in the lower 256 Kbytes:
• Data section (first 64 Kbytes in the common/attribute memory space)
• Command section (second 64 Kbytes in the common / attribute memory space)
• Address section (next 128 Kbytes in the common / attribute memory space)

Table 158. NAND bank selection

Section name ADDR[17:16] Address range

Address section 1X 0x020000-0x03FFFF

Command section 01 0x010000-0x01FFFF
Data section 00 0x000000-0x0FFFF

The application software uses the 3 sections to access the NAND flash memory:
• To send a command to NAND flash memory, the software must write the command
value to any memory location in the command section.
• To specify the NAND flash address that must be read or written, the software must
write the address value to any memory location in the address section. Since an
address can be 4 or 5 bytes long (depending on the actual memory size), several
consecutive write operations to the address section are required to specify the full
address.
• To read or write data, the software reads or writes the data from/to any memory
location in the data section.
Since the NAND flash memory automatically increments addresses, there is no need to
increment the address of the data section to access consecutive memory locations.

22.6.3 SDRAM address mapping

Two SDRAM banks are available as indicated in Table 159.

Table 159. SDRAM bank selection

Selected bank Control register Timing register

SDRAM Bank1 FMC_SDCR1 FMC_SDTR1

SDRAM Bank2 FMC_SDCR2 FMC_SDTR2

Table 160 shows SDRAM mapping for a 13-bit row and an 11-bit column configuration.

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Table 160. SDRAM address mapping

Maximum
Column
Memory width(1) Internal bank Row address memory capacity
address(2)
(Mbytes)

64 Mbytes:
8-bit ADDR[25:24] ADDR[23:11] ADDR[10:0]
4 x 8K x 2K
128 Mbytes:
16-bit ADDR[26:25] ADDR[24:12] ADDR[11:1]
4 x 8K x 2K x 2
256 Mbytes:
32-bit ADDR[27:26] ADDR[25:13] ADDR[12:2]
4 x 8K x 2K x 4
1. When interfacing with a 16-bit memory, the FMC internally uses the ADDR[11:1] internal address lines to
generate the external address. When interfacing with a 32-bit memory, the FMC internally uses
ADDR[12:2] lines to generate the external address. Whatever the memory width, FMC_A[0] has to be
connected to the external memory address A[0].
2. The AutoPrecharge is not supported. FMC_A[10] must be connected to the external memory address A[10]
but it will be always driven low.

The ADDR[27:0] bits are translated into an external SDRAM address depending on the
SDRAM controller configuration:
• Data size:8, 16 or 32 bits
• Row size:11, 12 or 13 bits
• Column size: 8, 9, 10 or 11 bits
• Number of internal banks: two or four internal banks
The following tables show the SDRAM address mapping versus the SDRAM controller
configuration.

Table 161. SDRAM address mapping with 8-bit data bus width(1)(2)
)

ADDR(Internal Address Lines)

Row size
configuratio
1 1 1 1 1 1 1 1
n 27 26 25 24 23 22 21 20 11 10 9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2

Bank
Res. Row[10:0] Column[7:0]
[1:0]
Bank
Res. Row[10:0] Column[8:0]
11-bit row size [1:0]
configuration Bank
Res. Row[10:0] Column[9:0]
[1:0]
Bank
Res. Row[10:0] Column[10:0]
[1:0]

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Table 161. SDRAM address mapping with 8-bit data bus width(1)(2) (continued)
ADDR(Internal Address Lines)
Row size
configuratio
1 1 1 1 1 1 1 1
n 27 26 25 24 23 22 21 20 11 10 9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2

Bank
Res. Row[11:0] Column[7:0]
[1:0]
Bank
12-bit row Res. Row[11:0] Column[8:0]
[1:0]
size
configuration Bank
Res. Row[11:0] Column[9:0]
[1:0]
Bank
Res. Row[11:0] Column[10:0]
[1:0]
Bank
Res. Row[12:0] Column[7:0]
[1:0]
Bank
13-bit row Res. Row[12:0] Column[8:0]
[1:0]
size
configuration Bank
Res. Row[12:0] Column[9:0]
[1:0]
Bank
Res. Row[12:0] Column[10:0]
[1:0]
1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.
2. Access to Reserved (Res.) address range generates an AXI slave error.

Table 162. SDRAM address mapping with 16-bit data bus width(1)(2)
ADDR(address Lines)

Row size
Configuration
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1

0
Bank BM0
Res. Row[10:0] Column[7:0] (3)
[1:0]
Bank
11-bit row size Res. Row[10:0] Column[8:0] BM0
[1:0]
configuration Bank
Res. Row[10:0] Column[9:0] BM0
[1:0]
Bank
Res. Row[10:0] Column[10:0] BM0
[1:0]
Bank
Res. Row[11:0] Column[7:0] BM0
[1:0]
Bank
12-bit row size Res. Row[11:0] Column[8:0] BM0
[1:0]
configuration Bank
Res. Row[11:0] Column[9:0] BM0
[1:0]
Bank
Res. Row[11:0] Column[10:0] BM0
[1:0]

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Table 162. SDRAM address mapping with 16-bit data bus width(1)(2)
ADDR(address Lines)

Row size
Configuration
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1

0
Bank
Res. Row[12:0] Column[7:0] BM0
[1:0]
Bank
13-bit row size Res. Row[12:0] Column[8:0] BM0
[1:0]
configuration Bank
Res. Row[12:0] Column[9:0] BM0
[1:0]
Re Bank
Row[12:0] Column[10:0] BM0
s. [1:0]
1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.
2. Access to Reserved space (Res.) generates an AXI Slave error.
3. BM0: is the byte mask for 16-bit access.

Table 163. SDRAM address mapping with 32-bit data bus width(1)(2)
ADDR(address Lines)

Row size
configuration
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Bank BM[1:0
Res. Row[10:0] Column[7:0]
[1:0] ](3)
Bank
11-bit row size Res. Row[10:0] Column[8:0] BM[1:0
[1:0]
configuration Bank
Res. Row[10:0] Column[9:0] BM[1:0
[1:0]
Bank
Res. Row[10:0] Column[10:0] BM[1:0
[1:0]
Bank
Res. Row[11:0] Column[7:0] BM[1:0
[1:0]
Bank
12-bit row size Res. Row[11:0] Column[8:0] BM[1:0
[1:0]
configuration Bank
Res. Row[11:0] Column[9:0] BM[1:0
[1:0]
Bank
Res. Row[11:0] Column[10:0] BM[1:0
[1:0]
Bank
Res. Row[12:0] Column[7:0] BM[1:0
[1:0]
Bank
13-bit row size Res. Row[12:0] Column[8:0] BM[1:0
[1:0]
configuration Bank
Res. Row[12:0] Column[9:0] BM[1:0
[1:0]
Bank
Row[12:0] Column[10:0] BM[1:0
[1:0]
1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.
2. Access to Reserved space (Res.) generates an AXI slave error.
3. BM[1:0]: is the byte mask for 32-bit access.

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22.7 NOR flash/PSRAM controller

The FMC generates the appropriate signal timings to drive the following types of memories:
• Asynchronous SRAM and ROM
– 8 bits
– 16 bits
– 32 bits
• PSRAM (Cellular RAM)
– Asynchronous mode
– Burst mode for synchronous accesses with configurable option to split burst
access when crossing boundary page for CRAM 1.5.
– Multiplexed or non-multiplexed
• NOR flash memory
– Asynchronous mode
– Burst mode for synchronous accesses
– Multiplexed or non-multiplexed
The FMC outputs a unique Chip Select signal, NE[4:1], per bank. All the other signals
(addresses, data and control) are shared.
The FMC supports a wide range of devices through a programmable timings among which:
• Programmable wait states (up to 15)
• Programmable bus turnaround cycles (up to 15)
• Programmable output enable and write enable delays (up to 15)
• Independent read and write timings and protocol to support the widest variety of
memories and timings
• Programmable continuous clock (FMC_CLK) output.
The FMC output Clock (FMC_CLK) is a sub-multiple of the fmc_ker_ck clock. It can be
delivered to the selected external device either during synchronous accesses only or during
asynchronous and synchronous accesses depending on the CCKEN bit configuration in the
FMC_BCR1 register:
• If the CCLKEN bit is reset, the FMC generates the clock (FMC_CLK) only during
synchronous accesses (Read/write transactions).
• If the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous
and synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must
be configured in Synchronous mode (see Section 22.7.6: NOR/PSRAM controller
registers). Since the same clock is used for all synchronous memories, when a
continuous output clock is generated and synchronous accesses are performed, the
AXI data size has to be the same as the memory data width (MWID) otherwise the
FMC_CLK frequency will be changed depending on AXI data transaction (refer to
Section 22.7.5: Synchronous transactions for FMC_CLK divider ratio formula).
The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through
dedicated registers (see Section 22.7.6: NOR/PSRAM controller registers).
The programmable memory parameters include access times (see Table 164) and support
for wait management (for PSRAM and NOR flash memory accessed in Burst mode).

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Table 164. Programmable NOR/PSRAM access parameters

Parameter Function Access mode Unit Min. Max.

Address Duration of the address FMC clock cycle

Asynchronous 0 15
setup setup phase (fmc_ker_ck)
Duration of the address hold Asynchronous, FMC clock cycle
Address hold 1 15
phase muxed I/Os (fmc_ker_ck)
Duration of the data setup FMC clock cycle
Data setup Asynchronous 1 256
phase (fmc_ker_ck)
Duration of the bus Asynchronous and FMC clock cycle
Bust turn 0 15
turnaround phase synchronous read (fmc_ker_ck)
Number of FMC clock cycles
Clock divide FMC clock cycle
(fmc_ker_ck) to build one Synchronous 2 16
ratio (fmc_ker_ck)
memory clock cycle (CLK)
Number of clock cycles to Memory clock
Data latency issue to the memory before Synchronous cycle 2 17
the first data of the burst (fmc_ker_ck)

22.7.1 External memory interface signals

Table 165, Table 166 and Table 167 list the signals that are typically used to interface with
NOR flash memory, SRAM and PSRAM.
Note: The prefix “N” identifies the signals which are active low.

NOR flash memory, non-multiplexed I/Os

Table 165. Non-multiplexed I/O NOR flash memory

FMC pin name I/O Function

CLK O Clock (for synchronous access)

A[25:0] O Address bus
D[31:0] I/O Bidirectional data bus
NE[x] O Chip Select, x = 1..4
NOE O Output enable
NWE O Write enable
Latch enable (this signal is called address
NL(=NADV) O
valid, NADV, by some NOR flash devices)
NWAIT I NOR flash wait input signal to the FMC

The maximum capacity is 512 Mbits (26 address lines).

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NOR flash memory, 16-bit multiplexed I/Os

Table 166. 16-bit multiplexed I/O NOR flash memory

FMC pin name I/O Function

CLK O Clock (for synchronous access)

A[25:16] O Address bus
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
AD[15:0] I/O
A[15:0] and data D[15:0] are multiplexed on the databus)
NE[x] O Chip Select, x = 1..4
NOE O Output enable
NWE O Write enable
Latch enable (this signal is called address valid, NADV, by some NOR
NL(=NADV) O
flash devices)
NWAIT I NOR flash wait input signal to the FMC

The maximum capacity is 512 Mbits.

PSRAM/SRAM, non-multiplexed I/Os

Table 167. Non-multiplexed I/Os PSRAM/SRAM

FMC pin name I/O Function

CLK O Clock (only for PSRAM synchronous access)

A[25:0] O Address bus
D[31:0] I/O Data bidirectional bus
NE[x] O Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
NOE O Output enable
NWE O Write enable
NL(= NADV) O Address valid only for PSRAM input (memory signal name: NADV)
NWAIT I PSRAM wait input signal to the FMC
NBL[3:0] O Byte lane output. Byte 0 to Byte 3 control (Upper and lower byte enable)

The maximum capacity is 512 Mbits.

PSRAM, 16-bit multiplexed I/Os

Table 168. 16-Bit multiplexed I/O PSRAM

FMC pin name I/O Function

CLK O Clock (for synchronous access)

A[25:16] O Address bus
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
AD[15:0] I/O
A[15:0] and data D[15:0] are multiplexed on the databus)

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Table 168. 16-Bit multiplexed I/O PSRAM (continued)

FMC pin name I/O Function

NE[x] O Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
NOE O Output enable
NWE O Write enable
NL(= NADV) O Address valid PSRAM input (memory signal name: NADV)
NWAIT I PSRAM wait input signal to the FMC
NBL[1:0] O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

The maximum capacity is 512 Mbits (26 address lines).

22.7.2 Supported memories and transactions

Table 169 below shows an example of the supported devices, access modes and
transactions when the memory data bus is 16-bit wide for NOR flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in
this example.

Table 169. NOR flash/PSRAM: Example of supported memories

and transactions(1)
Allowed/
AXI data Memory
Device Mode R/W not Comments
size data size
allowed

Asynchronous R 8 16 Y
Asynchronous W 8 16 N
Asynchronous R 16 16 Y
Asynchronous W 16 16 Y
Asynchronous R 32 16 Y Split into 2 FMC accesses
NOR flash
(muxed I/Os Asynchronous W 32 16 Y Split into 2 FMC accesses
and non- Asynchronous R 64 16 Y Split into 4 FMC accesses
multiplexed
I/Os) Asynchronous W 64 16 Y Split into 4 FMC accesses
Asynchronous
R - 16 N Mode is not supported
page
Synchronous R 8 16 N
Synchronous R 16 16 Y
Synchronous R 32/64 16 Y

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Table 169. NOR flash/PSRAM: Example of supported memories

and transactions(1) (continued)
Allowed/
AXI data Memory
Device Mode R/W not Comments
size data size
allowed

Asynchronous R 8 16 Y
Asynchronous W 8 16 Y Use of byte lanes NBL[1:0]
Asynchronous R 16 16 Y
Asynchronous W 16 16 Y
Asynchronous R 32 16 Y Split into 2 FMC accesses
Asynchronous W 32 16 Y Split into 2 FMC accesses
PSRAM
(multiplexed Asynchronous R 64 16 Y Split into 4 FMC accesses
I/Os and non- Asynchronous W 64 16 Y Split into 4 FMC accesses
multiplexed
I/Os) Asynchronous
R - 16 N Mode is not supported
page
Synchronous R 8 16 N
Synchronous R 16 16 Y
Synchronous R 32/64 16 Y
Synchronous W 8 16 Y Use of byte lanes NBL[1:0]
Synchronous W 16/32/64 16 Y
Asynchronous R 8/16 16 Y
Asynchronous W 8/16 16 Y Use of byte lanes NBL[1:0]
Asynchronous R 32 16 Y Split into 2 FMC accesses
SRAM and Split into 2 FMC accesses
ROM Asynchronous W 32 16 Y
Use of byte lanes NBL[1:0]
Asynchronous R 64 16 Y Split into 4 FMC accesses
Split into 4 FMC accesses
Asynchronous W 64 16 Y
Use of byte lanes NBL[1:0]
1. NBL[1:0] are also driven by AXI write strobes.

22.7.3 General timing rules

Signal synchronization is performed as follows:
• All controller output signals change on the rising edge of the fmc_ker_ck clock.
• In Synchronous read and write modes, all output signals change on the rising edge of
fmc_ker_ck clock. Whatever the CLKDIV value, all outputs change as follows:
– NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FMC_CLK clock.
– NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FMC_CLK clock.

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22.7.4 NOR flash/PSRAM controller asynchronous transactions

Asynchronous transactions on static memories (NOR flash memory, PSRAM, SRAM) are
performed as follows:
• Signals are synchronized by the internal clock. This clock is not issued to the memory.
• The FMC always samples the data before deasserting the Chip Select signal. This
guarantees that the memory data hold timing constraint is met (minimum Chip Enable
high to data transition is usually 0 ns)
• If the Extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to
four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D
modes for read and write operations. For example, read operation can be performed in
mode A and write in mode B.
• If the Extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the
FMC can operate in Mode1 or Mode2 as follows:
– Mode 1 is the default mode when SRAM/PSRAM memory type is selected
(MTYP = 0x0 or 0x01 in the FMC_BCRx register)
– Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in
the FMC_BCRx register).

Mode 1 - SRAM/PSRAM (CRAM)

The next figures show the read and write transactions for the supported modes followed by
the required configuration of FMC_BCRx, and FMC_BTRx/FMC_BWTRx registers.

Figure 99. Mode 1 read access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

High
NWE

Data bus data driven

by memory

ADDSET DATAST
fmc_ker_ck cycles fmc_ker_ck cycles
MSv40369V2

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Figure 100. Mode 1 write access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE
1 fmc_ker_ck

NWE

Data bus data driven by FSMC

ADDSET (DATAST + 1)
fmc_ker_ck cycles fmc_ker_ck cycles

MSv40370V2

The fmc_ker_ck cycle at the end of the write transaction helps guarantee the address and
data hold time after the NWE rising edge. Due to the presence of this fmc_ker_ck cycle, the
DATAST value must be greater than zero (DATAST > 0).

Table 170. FMC_BCRx bitfields (mode 1)

Bit
Bit name Value to set
number

31 FMCEN 0x1
30:26 Reserved 0x000
25:24 BMAP As needed
23:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
15 ASYNCWAIT
0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0

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Table 170. FMC_BCRx bitfields (mode 1) (continued)

Bit
Bit name Value to set
number

9 WAITPOL Meaningful only if bit 15 is 1

8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN Don’t care
5:4 MWID As needed
3:2 MTYP As needed, exclude 0x2 (NOR flash memory)
1 MUXE 0x0
0 MBKEN 0x1

Table 171. FMC_BTRx bitfields (mode 1)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD Don’t care
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
Duration of the second access phase (DATAST+1 fmc_ker_ck cycles
15:8 DATAST
for write accesses, DATAST fmc_ker_ck cycles for read accesses).
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET fmc_ker_ck cycles).
3:0 ADDSET
Minimum value for ADDSET is 0.

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Mode A - SRAM/PSRAM (CRAM) OE toggling

Figure 101. Mode A read access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

NWE
High

Data bus data driven

by memory

ADDSET DATAST
fmc_ker_ck cycles fmc_ker_ck cycles

MSv40371V2

1. NBL[3:0] are driven low during the read access

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Figure 102. Mode A write access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

1 fmc_ker_ck
NWE

Data bus data driven by FMC

ADDSET (DATAST + 1)
fmc_ker_ck cycles fmc_ker_ck cycles

MSv40372V3

The differences compared with Mode1 are the toggling of NOE and the independent read
and write timings.

Table 172. FMC_BCRx bitfields (mode A)

Bit
Bit name Value to set
number

31 FMCEN 0x1
30:26 Reserved 0x000
25:24 BMAP As needed
23:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
15 ASYNCWAIT
0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0

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Table 172. FMC_BCRx bitfields (mode A) (continued)

Bit
Bit name Value to set
number

9 WAITPOL Meaningful only if bit 15 is 1

8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN Don’t care
5:4 MWID As needed
3:2 MTYP As needed, exclude 0x2 (NOR flash memory)
1 MUXEN 0x0
0 MBKEN 0x1

Table 173. FMC_BTRx bitfields (mode A)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
Duration of the second access phase (DATAST fmc_ker_ck cycles) for
15:8 DATAST
read accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET fmc_ker_ck cycles) for
3:0 ADDSET read accesses.
Minimum value for ADDSET is 0.

Table 174. FMC_BWTRx bitfields (mode A)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
Duration of the second access phase (DATAST fmc_ker_ck cycles) for
15:8 DATAST
write accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET fmc_ker_ck cycles) for
3:0 ADDSET write accesses.
Minimum value for ADDSET is 0.

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Mode 2/B - NOR flash

Figure 103. Mode 2 and mode B read access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

High
NWE

Data bus data driven

by memory

ADDSET DATAST
fmc_ker_ck cycles fmc_ker_ck cycles

MSv40373V2

Figure 104. Mode 2 write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

1 fmc_ker_ck
NWE

Data bus data driven by FSMC

ADDSET (DATAST + 1)
fmc_ker_ck cycles fmc_ker_ck cycles
MSv40374V2

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Figure 105. Mode B write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

1 fmc_ker_ck
NWE

Data bus data driven by FSMC

ADDSET (DATAST + 1)
fmc_ker_ck cycles fmc_ker_ck cycles
MSv40375V2

The differences with Mode1 are the toggling of NWE and the independent read and write
timings when extended mode is set (mode B).

Table 175. FMC_BCRx bitfields (mode 2/B)

Bit
Bit name Value to set
number

31 FMCEN 0x1
30:26 Reserved 0x000
25:24 BMAP As needed
23:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
15 ASYNCWAIT
0.
14 EXTMOD 0x1 for mode B, 0x0 for mode 2
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0

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Table 175. FMC_BCRx bitfields (mode 2/B) (continued)

Bit
Bit name Value to set
number

9 WAITPOL Meaningful only if bit 15 is 1

8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
5:4 MWID As needed
3:2 MTYP 0x2 (NOR flash memory)
1 MUXEN 0x0
0 MBKEN 0x1

Table 176. FMC_BTRx bitfields (mode 2/B)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x1 if Extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
Duration of the access second phase (DATAST fmc_ker_ck cycles)
15:8 DATAST
for read accesses.
7:4 ADDHLD Don’t care
Duration of the access first phase (ADDSET fmc_ker_ck cycles) for
3:0 ADDSET
read accesses. Minimum value for ADDSET is 0.

Table 177. FMC_BWTRx bitfields (mode 2/B)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x1 if Extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
Duration of the access second phase (DATAST fmc_ker_ck cycles)
15:8 DATAST
for write accesses.
7:4 ADDHLD Don’t care
Duration of the access first phase (ADDSET fmc_ker_ck cycles) for
3:0 ADDSET
write accesses. Minimum value for ADDSET is 0.

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Note: The FMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its
content is don’t care.

Mode C - NOR flash - OE toggling

Figure 106. Mode C read access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE
High

Data bus data driven

by memory

ADDSET DATAST
fmc_ker_ck cycles fmc_ker_ck cycles
MSv40376V2

Figure 107. Mode C write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

1 fmc_ker_ck

NWE

Data bus data driven by FSMC

ADDSET (DATAST + 1)
fmc_ker_ck cycles fmc_ker_ck cycles
MSv40377V2

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The differences compared with Mode1 are the toggling of NOE and the independent read
and write timings.

Table 178. FMC_BCRx bitfields (mode C)

Bit No. Bit name Value to set

31 FMCEN 0x1
30:26 Reserved 0x000
25:24 BMAP As needed
23:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
5:4 MWID As needed
3:2 MTYP 0x02 (NOR flash memory)
1 MUXEN 0x0
0 MBKEN 0x1

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Table 179. FMC_BTRx bitfields (mode C)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x2
27:24 DATLAT 0x0
23:20 CLKDIV 0x0
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
Duration of the second access phase (DATAST fmc_ker_ck cycles)
15:8 DATAST
for read accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET fmc_ker_ck cycles) for
3:0 ADDSET
read accesses. Minimum value for ADDSET is 0.

Table 180. FMC_BWTRx bitfields (mode C)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x2
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
Duration of the second access phase (DATAST fmc_ker_ck cycles)
15:8 DATAST
for write accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET fmc_ker_ck cycles) for
3:0 ADDSET
write accesses. Minimum value for ADDSET is 0.

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Mode D - asynchronous access with extended address

Figure 108. Mode D read access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

High
NWE

Data bus data driven

by memory
ADDSET ADDHLD DATAST
fmc_ker_ck fmc_ker_ck fmc_ker_ck

MSv40378V2

Figure 109. Mode D write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE
1 fmc_ker_ck

NWE

Data bus Data driven

by FMC
ADDSET ADDHLD (DATAST+1)

fmc_ker_ck fmc_ker_ck fmc_ker_ck

MSv40379V3

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The differences with Mode1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.

Table 181. FMC_BCRx bitfields (mode D)

Bit No. Bit name Value to set

31 FMCEN 0x1
30:26 Reserved 0x000
25:24 BMAP As needed
23:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep
15 ASYNCWAIT
at 0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN Set according to memory support
5:4 MWID As needed
3:2 MTYP As needed
1 MUXEN 0x0
0 MBKEN 0x1

Table 182. FMC_BTRx bitfields (mode D)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x3
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
Duration of the second access phase (DATAST fmc_ker_ck cycles) for
15:8 DATAST
read accesses.

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Table 182. FMC_BTRx bitfields (mode D) (continued)

Bit number Bit name Value to set

Duration of the middle phase of the read access (ADDHLD

7:4 ADDHLD
fmc_ker_ck cycles)
Duration of the first access phase (ADDSET fmc_ker_ck cycles) for
3:0 ADDSET
read accesses. Minimum value for ADDSET is 1.

Table 183. FMC_BWTRx bitfields (mode D)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x3
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
Duration of the second access phase (DATAST + 1 fmc_ker_ck
15:8 DATAST
cycles) for write accesses.
Duration of the middle phase of the write access (ADDHLD
7:4 ADDHLD
fmc_ker_ck cycles)
Duration of the first access phase (ADDSET fmc_ker_ck cycles) for
3:0 ADDSET
write accesses. Minimum value for ADDSET is 1.

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Muxed mode - multiplexed asynchronous access to NOR flash memory

Figure 110. Muxed read access waveforms

Memory transaction

A[25:16]

NADV

NEx

NOE

NWE
High

AD[15:0] data driven

Lower address by memory

ADDSET DATAST
fmc_ker_ck cycles fmc_ker_ck cycles
ADDHLD
fmc_ker_ck cycles MSv40380V2

Figure 111. Muxed write access waveforms

Memory transaction

A[25:16]

NADV

NEx

NOE

1 fmc_ker_ck
NWE

AD[15:0] Lower address data driven by FSMC

ADDSET (DATAST + 1)
fmc_ker_ck cycles fmc_ker_ck cycles
ADDHLD
fmc_ker_ck cycles
MSv40381V2

The difference with Mode D is the drive of the lower address byte(s) on the data bus.

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Table 184. FMC_BCRx bitfields (Muxed mode)

Bit No. Bit name Value to set

31 FMCEN 0x1
30:26 Reserved 0x000
25:24 BMAP As needed
23:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
15 ASYNCWAIT
0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
5:4 MWID As needed
3:2 MTYP 0x2 (NOR flash memory)
1 MUXEN 0x1
0 MBKEN 0x1

Table 185. FMC_BTRx bitfields (Muxed mode)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
Duration of the second access phase (DATAST fmc_ker_ck cycles for
15:8 DATAST read accesses and DATAST+1 fmc_ker_ck cycles for write
accesses).

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Table 185. FMC_BTRx bitfields (Muxed mode) (continued)

Bit number Bit name Value to set

Duration of the middle phase of the access (ADDHLD fmc_ker_ck

7:4 ADDHLD
cycles).
Duration of the first access phase (ADDSET fmc_ker_ck cycles).
3:0 ADDSET
Minimum value for ADDSET is 1.

WAIT management in asynchronous accesses

If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase must be programmed so that WAIT can be detected 4 fmc_ker_ck
cycles before the end of the memory transaction. The following cases must be considered:
1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles:
DATAST ≥ ( 4 × fmc_ker_ck ) + max_wait_assertion_time

2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
max_wait_assertion_time > address_phase + hold_phase

then:

DATAST ≥ ( 4 × fmc_ker_ck ) + ( max_wait_assertion_time – address_phase – hold_phase )

otherwise

DATAST ≥ ( 4 × fmc_ker_ck )

where max_wait_assertion_time is the maximum time taken by the memory to assert

the WAIT signal once NEx/NOE/NWE is low.
Figure 112 and Figure 113 show the number of fmc_ker_ck clock cycles that are added to the
memory access phase after WAIT is released by the asynchronous memory (independently
of the above cases).

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RM0433 Flexible memory controller (FMC)

Figure 112. Asynchronous wait during a read access waveforms

Memory transaction

A[25:0]

address phase data setup phase

NEx

NWAIT don’t care don’t care

NOE

Data bus data driven by memory

4 fmc_ker_ck

MSv40382V2

1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

Figure 113. Asynchronous wait during a write access waveforms

Memory transaction

A[25:0]

address phase data setup phase

NEx

NWAIT don’t care don’t care

1 fmc_ker_ck

NWE

Data bus data driven by FSMC

3 fmc_ker_ck
MSv40383V2

1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

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22.7.5 Synchronous transactions

The memory clock, FMC_CLK, is a sub-multiple of fmc_ker_ck. It depends on the value of
CLKDIV and the MWID/ AXI data size, following the formula given below:

FMC_CLK divider ratio = max (CLKDIV + 1,MWID ( AXI data size ))

If MWID is 16 or 8-bit, the FMC_CLK divider ratio is always defined by the programmed
CLKDIV value.
If MWID is 32-bit, the FMC_CLK divider ratio depends also on AXI data size.
Example:
• If CLKDIV=1, MWID = 32 bits, AXI data size=8 bits, FMC_CLK=fmc_ker_ck/4.
• If CLKDIV=1, MWID = 16 bits, AXI data size=8 bits, FMC_CLK=fmc_ker_ck/2.
NOR flash memories specify a minimum time from NADV assertion to FMC_CLK high. To
meet this constraint, the FMC does not issue the clock to the memory during the first internal
clock cycle of the synchronous access (before NADV assertion). This guarantees that the
rising edge of the memory clock occurs in the middle of the NADV low pulse.
For some PSRAM memories which must be configured to Synchronous mode, during the
BCR register writing, the memory attribute space must be configured to device or strongly-
ordered. Once PSRAM BCR register is configured, the memory attribute of PSRAM address
space can be programmed to cacheable.

Data latency versus NOR memory latency

The data latency is the number of cycles to wait before sampling the data. The DATLAT
value must be consistent with the latency value specified in the NOR flash configuration
register. The FMC does not include the clock cycle when NADV is low in the data latency
count.
Caution: Some NOR flash memories include the NADV Low cycle in the data latency count, so that
the exact relation between the NOR flash latency and the FMC DATLAT parameter can be
either:
• NOR flash latency = (DATLAT + 2) FMC_CLK clock cycles
• or NOR flash latency = (DATLAT + 3) FMC_CLK clock cycles
Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can
be set to its minimum value. As a result, the FMC samples the data and waits long enough
to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and
real data are processed.
Other memories do not assert NWAIT during latency. In this case the latency must be set
correctly for both the FMC and the memory, otherwise invalid data are mistaken for good
data, or valid data are lost in the initial phase of the memory access.

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RM0433 Flexible memory controller (FMC)

Single-burst transfer
When the selected bank is configured in Burst mode for synchronous accesses, if for
example a single-burst transaction is requested on 16-bit memories, the FMC performs a
burst transaction of length 1 (if the AXI transfer is 16 bits), or length 2 (if the AXI transfer is
32 bits) and deassert the Chip Select signal when the last data is strobed.
Such transfers are not the most efficient in terms of cycles compared to asynchronous read
operations. Nevertheless, a random asynchronous access would first require to re-program
the memory access mode, which would altogether last longer.

Cross boundary page for Cellular RAM 1.5

Cellular RAM 1.5 does not allow burst access to cross the page boundary. The FMC allows
to split automatically the burst access when the memory page size is reached by configuring
the CPSIZE bits in the FMC_BCR1 register following the memory page size.

Wait management
For synchronous NOR flash memories, NWAIT is evaluated after the programmed latency
period, which corresponds to (DATLAT+2) FMC_CLK clock cycles.
If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait
states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when
WAITPOL = 1).
When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1)
or on the next clock edge (bit WAITCFG = 0).
During wait-state insertion via the NWAIT signal, the controller continues to send clock
pulses to the memory, keeping the Chip Select and output enable signals valid. It does not
consider the data as valid.
In Burst mode, there are two timing configurations for the NOR flash NWAIT signal:
• The flash memory asserts the NWAIT signal one data cycle before the wait state
(default after reset).
• The flash memory asserts the NWAIT signal during the wait state
The FMC supports both NOR flash wait state configurations, for each Chip Select, thanks to
the WAITCFG bit in the FMC_BCRx registers (x = 0..3).

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Figure 114. Wait configuration waveforms

Memory transaction = burst of 4 half words

fmc_ker_ck

FMC_CLK

A[25:16] addr[25:16]

NADV

NWAIT
(WAITCFG = 0)

NWAIT
(WAITCFG = 1)
inserted wait state

A/D[15:0] addr[15:0] data data data

MSv40384V2

Figure 115. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)
Memory transaction = burst of 4 half words

fmc_ker_ck

FMC_CLK

A[25:16] addr[25:16]

NEx

NOE

NWE High

NADV

NWAIT
(WAITCFG=0)
(DATLAT + 2) inserted wait state
fmc_ker_ck
Addr[15:0] cycles data data data data
A/D[15:0]

1 1
clock clock Data strobes
Data strobes
cycle cycle MSv40385V2

1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM)
access, they are held low.

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RM0433 Flexible memory controller (FMC)

Table 186. FMC_BCRx bitfields (Synchronous multiplexed read mode)

Bit No. Bit name Value to set

31 MC 0x1
30:26 Reserved 0x000
25:24 BMAP As needed
23:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW No effect on synchronous read
18:16 CPSIZE As needed. (0x1 when using CRAM 1.5)
15 ASYNCWAIT 0x0
14 EXTMOD 0x0
to be set to 1 if the memory supports this feature, to be kept at 0
13 WAITEN
otherwise
12 WREN no effect on synchronous read
11 WAITCFG to be set according to memory
10 Reserved 0x0
9 WAITPOL to be set according to memory
8 BURSTEN 0x1
7 Reserved 0x1
6 FACCEN Set according to memory support (NOR flash memory)
5:4 MWID As needed
3:2 MTYP 0x1 or 0x2
1 MUXEN As needed
0 MBKEN 0x1

Table 187. FMC_BTRx bitfields (Synchronous multiplexed read mode)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x0
27:24 DATLAT Data latency
27:24 DATLAT Data latency
0x0 to get CLK = fmc_ker_ck (Not supported)
23:20 CLKDIV 0x1 to get CLK = 2 × fmc_ker_ck
..
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
15:8 DATAST Don’t care

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Table 187. FMC_BTRx bitfields (Synchronous multiplexed read mode) (continued)

Bit number Bit name Value to set

7:4 ADDHLD Don’t care

3:0 ADDSET Don’t care

Figure 116. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

Memory transaction = burst of 2 half words

fmc_ker_ck

FMC_CLK

A[25:16] addr[25:16]

NEx

Hi-Z
NOE

NWE

NADV

NWAIT
(WAITCFG = 0)
(DATLAT + 2) inserted wait state
fmc_ker_ck cycles
A/D[15:0] Addr[15:0] data data

1 clock 1 clock
cycle cycle MSv40386V2

1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed
to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.

Table 188. FMC_BCRx bitfields (Synchronous multiplexed write mode)

Bit No. Bit name Value to set

31 FMCEN 0x1
30:26 Reserved 0x000
25:24 BMAP As needed
23:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW No effect on synchronous read

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Table 188. FMC_BCRx bitfields (Synchronous multiplexed write mode) (continued)

Bit No. Bit name Value to set

18:16 CPSIZE As needed. (0x1 when using CRAM 1.5)

15 ASYNCWAIT 0x0
14 EXTMOD 0x0
to be set to 1 if the memory supports this feature, to be kept at 0
13 WAITEN
otherwise.
12 WREN 0x1
11 WAITCFG 0x0
10 Reserved 0x0
9 WAITPOL to be set according to memory
8 BURSTEN no effect on synchronous write
7 Reserved 0x1
6 FACCEN Set according to memory support
5:4 MWID As needed
3:2 MTYP 0x1
1 MUXEN As needed
0 MBKEN 0x1

Table 189. FMC_BTRx bitfields (Synchronous multiplexed write mode)

Bit number Bit name Value to set

31:30 Reserved 0x0

29:28 ACCMOD 0x0
27:24 DATLAT Data latency
0x0 to get CLK = fmc_ker_ck (not supported)
23:20 CLKDIV
0x1 to get CLK = 2 × fmc_ker_ck
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN fmc_ker_ck)
15:8 DATAST Don’t care
7:4 ADDHLD Don’t care
3:0 ADDSET Don’t care

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22.7.6 NOR/PSRAM controller registers

SRAM/NOR-flash chip-select control registers for bank x (FMC_BCRx)
Address offset: 8 * (x - 1), (x = 1 to 4)
Reset value: 0x0000 30DB, 0x0000 30D2, Block 3: 0x0000 30D2, 0x0000 30D2
This register contains the control information of each memory bank, used for SRAMs,
PSRAM and NOR flash memories.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CBURSTRW
CCLKEN
FMCEN

WFDIS
Res.

Res.

Res.

Res.

Res.

Res.

Res.
BMAP[1:0] CPSIZE[2:0]

rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT

BURSTEN
WAITCFG

WAITPOL
EXTMOD

FACCEN
WAITEN

MUXEN

MBKEN
WREN

MTYP
MWID
Res.

Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 FMCEN: FMC Enable

This bit enables/disables the FMC.
0: Disable the FMC
1: Enable the FMC
Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through
the FMC_BCR1 register.
Bits 30:26 Reserved, must be kept at reset value.
Bits 25:24 BMAP[1:0]: FMC bank mapping
These bits allow different remap or swap of the FMC NOR/PSRAM and SDRAM banks (refer
to Table 154).
00: Default mapping (refer to Figure 98 and Table 154).
01: NOR/PSRAM bank and SDRAM bank 1/bank2 are swapped.
10: SDRAM Bank2 remapped on FMC bank2 and still accessible at default mapping
11: Reserved.
Note: The BMAP bits of the FMC_BCR2..4 registers are don’t care. It is only enabled through
the FMC_BCR1 register.
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 WFDIS: Write FIFO Disable
This bit disables the Write FIFO used by the FMC.
0: Write FIFO enabled (Default after reset)
1: Write FIFO disabled
Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through
the FMC_BCR1 register.

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Bit 20 CCLKEN: Continuous Clock Enable

This bit enables the FMC_CLK clock output to external memory devices.
0: The FMC_CLK is only generated during the synchronous memory access (read/write
transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the
FMC_BCRx register (default after reset).
1: The FMC_CLK is generated continuously during asynchronous and synchronous access.
The FMC_CLK clock is activated when the CCLKEN is set.
Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through
the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate
the FMC_CLK continuous clock.
If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the
FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care.
If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories
connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value
in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)
Bit 19 CBURSTRW: Write burst enable
For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during
write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the
FMC_BCRx register.
0: Write operations are always performed in Asynchronous mode
1: Write operations are performed in Synchronous mode.
Bits 18:16 CPSIZE[2:0]: CRAM Page Size
These are used for Cellular RAM 1.5 which does not allow burst access to cross the address
boundaries between pages. When these bits are configured, the FMC splits automatically the
burst access when the memory page size is reached (refer to memory datasheet for page
size).
000: No burst split when crossing page boundary (default after reset).
001: 128 bytes
010: 256 bytes
100: 1024 bytes
Other configuration: reserved.
Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers
This bit enables/disables the FMC to use the wait signal even during an asynchronous
protocol.
0: NWAIT signal is not taken in to account when running an asynchronous protocol (default
after reset)
1: NWAIT signal is taken in to account when running an asynchronous protocol
Bit 14 EXTMOD: Extended mode enable.
This bit enables the FMC to program the write timings for asynchronous accesses inside the
FMC_BWTR register, thus resulting in different timings for read and write operations.
0: values inside FMC_BWTR register are not taken into account (default after reset)
1: values inside FMC_BWTR register are taken into account
Note: When the Extended mode is disabled, the FMC can operate in Mode1 or Mode2 as
follows:
– Mode 1 is the default mode when the SRAM/PSRAM memory type is selected
(MTYP =0x0 or 0x01)
– Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).

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Bit 13 WAITEN: Wait enable bit

This bit enables/disables wait-state insertion via the NWAIT signal when accessing the
memory in Synchronous mode.
0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the
programmed flash latency period)
1: NWAIT signal is enabled (its level is taken into account after the programmed latency
period to insert wait states if asserted) (default after reset)
Bit 12 WREN: Write enable bit
This bit indicates whether write operations are enabled/disabled in the bank by the FMC:
0: Write operations are disabled in the bank by the FMC, an AXI slave error is reported
1: Write operations are enabled for the bank by the FMC (default after reset).
Bit 11 WAITCFG: Wait timing configuration
The NWAIT signal indicates whether the data from the memory are valid or if a wait state
must be inserted when accessing the memory in Synchronous mode. This configuration bit
determines if NWAIT is asserted by the memory one clock cycle before the wait state or
during the wait state:
0: NWAIT signal is active one data cycle before wait state (default after reset)
1: NWAIT signal is active during wait state (not used for PSRAM).
Bit 10 Reserved, must be kept at reset value.
Bit 9 WAITPOL: Wait signal polarity bit
This bit defines the polarity of the wait signal from memory used for either in Synchronous or
Asynchronous mode:
0: NWAIT active low (default after reset)
1: NWAIT active high.
Bit 8 BURSTEN: Burst enable bit
This bit enables/disables synchronous accesses during read operations. It is valid only for
synchronous memories operating in Burst mode:
0: Burst mode disabled (default after reset). Read accesses are performed in Asynchronous
mode
1: Burst mode enable. Read accesses are performed in Synchronous mode.
Bit 7 Reserved, must be kept at reset value.
Bit 6 FACCEN: Flash access enable
This bit enables NOR flash memory access operations.
0: Corresponding NOR flash memory access is disabled
1: Corresponding NOR flash memory access is enabled (default after reset)
Bits 5:4 MWID[1:0]: Memory data bus width
Defines the external memory device width, valid for all type of memories.
00: 8 bits
01: 16 bits (default after reset)
10: 32 bits
11: reserved

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RM0433 Flexible memory controller (FMC)

Bits 3:2 MTYP[1:0]: Memory type

These bits define the type of external memory attached to the corresponding memory bank:
00: SRAM (default after reset for Bank 2...4)
01: PSRAM (CRAM)
10: NOR flash/OneNAND flash (default after reset for Bank 1)
11: reserved
Bit 1 MUXEN: Address/data multiplexing enable bit
When this bit is set, the address and data values are multiplexed on the data bus, valid only
with NOR and PSRAM memories:
0: Address/Data non-multiplexed
1: Address/Data multiplexed on databus (default after reset)
Bit 0 MBKEN: Memory bank enable bit
This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled.
Accessing a disabled bank causes an ERROR on AXI bus.
0: Corresponding memory bank is disabled
1: Corresponding memory bank is enabled

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SRAM/NOR-flash chip-select timing registers for bank x (FMC_BTRx)

Address offset: 0x04 + 8 * (x - 1), (x = 1 to 4)
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank, used for SRAMs,
PSRAM and NOR flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then
this register is partitioned for write and read access, that is, 2 registers are available: one to
configure read accesses (this register) and one to configure write accesses (FMC_BWTRx
registers).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. ACCMOD DATLAT CLKDIV BUSTURN

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST ADDHLD ADDSET
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 ACCMOD[1:0]: Access mode
These bits specify the Asynchronous access modes as shown in the timing diagrams. They
are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
00: access mode A
01: access mode B
10: access mode C
11: access mode D
Bits 27:24 DATLAT[3:0]: (see note below bit descriptions): Data latency for synchronous memory
For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits
set), these bits define the number of memory clock cycles (+2) to issue to the memory before
reading/writing the first data:
This timing parameter is not expressed in fmc_ker_ck periods, but in FMC_CLK periods.
For asynchronous access, this value is don't care.
0000: Data latency of 2 FMC_CLK clock cycles for first burst access
1111: Data latency of 17 FMC_CLK clock cycles for first burst access (default value after
reset)
Bits 23:20 CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal)
These bits define the period of FMC_CLK clock output signal, expressed in number of
fmc_ker_ck cycles:
0000: Reserved
0001: FMC_CLK period = 2 × fmc_ker_ck periods
0010: FMC_CLK period = 3 × fmc_ker_ck periods
1111: FMC_CLK period = 16 × fmc_ker_ck periods (default value after reset)
In asynchronous NOR flash, SRAM or PSRAM accesses, this value is don’t care.
Note: Refer to Section 22.7.5: Synchronous transactions for FMC_CLK divider ratio formula)

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Bits 19:16 BUSTURN: Bus turnaround phase duration

These bits are written by software to add a delay at the end of a write-to-read (and read-to-
write) transaction. This delay allows to match the minimum time between consecutive
transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory
to free the data bus after a read access (tEHQZ). The programmed bus turnaround delay is
inserted between an asynchronous read (muxed or mode D) or write transaction and any
other asynchronous /synchronous read or write to or from a static bank. The bank can be the
same or different in case of read, in case of write the bank can be different except for muxed
or mode D.
In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is
fixed
as follows:
• The bus turnaround delay is not inserted between two consecutive asynchronous write
transfers to the same static memory bank except for muxed and D modes.
• There is a bus turnaround delay of 1 FMC clock cycle between:
–Two consecutive asynchronous read transfers to the same static memory bank except for
muxed and D modes.
–An asynchronous read to an asynchronous or synchronous write to any static bank or
dynamic bank except for muxed and D modes.
–An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank.
• There is a bus turnaround delay of 2 FMC clock cycle between:
–Two consecutive synchronous writes (burst or single) to the same bank.
–A synchronous write (burst or single) access and an asynchronous write or read transfer
to or from static memory bank (the bank can be the same or different for the case of
read.
–Two consecutive synchronous reads (burst or single) followed by any
synchronous/asynchronous read or write from/to another static memory bank.
• There is a bus turnaround delay of 3 FMC clock cycle between:
–Two consecutive synchronous writes (burst or single) to different static bank.
–A synchronous write (burst or single) access and a synchronous read from the same or a
different bank.

0000: BUSTURN phase duration = 0 fmc_ker_ck clock cycle added

...
1111: BUSTURN phase duration = 15 x fmc_ker_ck clock cycles added (default value after
reset)
Bits 15:8 DATAST: Data-phase duration
These bits are written by software to define the duration of the data phase (refer to Figure 99
to Figure 111), used in asynchronous accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × fmc_ker_ck clock cycles
0000 0010: DATAST phase duration = 2 × fmc_ker_ck clock cycles
...
1111 1111: DATAST phase duration = 255 × fmc_ker_ck clock cycles (default value after
reset)
For each memory type and access mode data-phase duration, please refer to the respective
figure (Figure 99 to Figure 111).
Example: Mode1, write access, DATAST = 1: Data-phase duration = DATAST+1 =
1 x fmc_ker_ck clock cycles.
Note: In synchronous accesses, this value is don’t care.

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Bits 7:4 ADDHLD: Address-hold phase duration

These bits are written by software to define the duration of the address hold phase (refer to
Figure 99 to Figure 111), used in mode D or multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration =1 × fmc_ker_ck clock cycle
0010: ADDHLD phase duration = 2 × fmc_ker_ck clock cycle
...
1111: ADDHLD phase duration = 15 × fmc_ker_ck clock cycles (default value after reset)
For each access mode address-hold phase duration, please refer to the respective figure
(Figure 99 to Figure 111).
Note: In synchronous accesses, this value is not used, the address hold phase is always 1
memory clock period duration.
Bits 3:0 ADDSET: Address setup phase duration
These bits are written by software to define the duration of the address setup phase (refer to
Figure 99 to Figure 111), used in SRAMs, ROMs and asynchronous NOR flash:
0000: ADDSET phase duration = 0 × fmc_ker_ck clock cycle
...
1111: ADDSET phase duration = 15 × fmc_ker_ck clock cycles (default value after reset)
For each access mode address setup phase duration, please refer to the respective figure
(refer to Figure 99 to Figure 111).
Note: In synchronous accesses, this value is don’t care.
In Muxed mode or mode D, the minimum value for ADDSET is 1.
In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.

Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to extend the latency as
needed.
On PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency
phase soon and starts sampling NWAIT from memory, then starts to read or write when the
memory is ready.
This method can be used also with the latest generation of synchronous flash memories that
issue the NWAIT signal, unlike older flash memories (check the datasheet of the specific
flash memory being used).

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SRAM/NOR-flash write timing registers for bank x (FMC_BWTRx)

Address offset: 0x104 + 8 * (x - 1), (x = 1 to 4)
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank. It is used for SRAMs,
PSRAMs and NOR flash memories. When the EXTMOD bit is set in the FMC_BCRx
register, then this register is active for write access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. ACCMOD Res. Res. Res. Res. Res. Res. Res. Res. BUSTURN

rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST ADDHLD ADDSET[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 ACCMOD: Access mode.
These bits specify the asynchronous access modes as shown in the next timing diagrams.These
bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
00: access mode A
01: access mode B
10: access mode C
11: access mode D
Bits 27:20 Reserved, must be kept at reset value.
Bits 19:16 BUSTURN: Bus turnaround phase duration
These bits are written by software to add a delay at the end of a write transaction to match the
minimum time between consecutive transactions (tEHEL from ENx high to ENx low):
(BUSTRUN + 1) fmc_ker_ck period ≥ tEHELmin.
The programmed bus turnaround delay is inserted between an asynchronous write transfer and
any other asynchronous /synchronous read or write transfer to or from a static bank. The bank can
be the same or different in case of read, in case of write the bank can be different expect for muxed
or mode D.
In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as
follows:
• The bus turnaround delay is not inserted between two consecutive asynchronous write transfers
to the same static memory bank except for muxed and D modes.
• There is a bus turnaround delay of 2 FMC clock cycle between:
–Two consecutive synchronous writes (burst or single) to the same bank.
–A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or
from static memory bank.
• There is a bus turnaround delay of 3 FMC clock cycle between:
–Two consecutive synchronous writes (burst or single) to different static bank.
–A synchronous write (burst or single) transfer and a synchronous read from the same or a
different bank.

0000: BUSTURN phase duration = 0 fmc_ker_ck clock cycle added

...
1111: BUSTURN phase duration = 15 fmc_ker_ck clock cycles added (default value after reset)

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Bits 15:8 DATAST: Data-phase duration.

These bits are written by software to define the duration of the data phase (refer to Figure 99 to
Figure 111), used in asynchronous SRAM, PSRAM and NOR flash memory accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × fmc_ker_ck clock cycles
0000 0010: DATAST phase duration = 2 × fmc_ker_ck clock cycles
...
1111 1111: DATAST phase duration = 255 × fmc_ker_ck clock cycles (default value after reset)
Bits 7:4 ADDHLD: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 99 to Figure 111), used in asynchronous multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration = 1 × fmc_ker_ck clock cycle
0010: ADDHLD phase duration = 2 × fmc_ker_ck clock cycle
...
1111: ADDHLD phase duration = 15 × fmc_ker_ck clock cycles (default value after reset)
Note: In synchronous NOR flash accesses, this value is not used, the address hold phase is always
1 flash clock period duration.
Bits 3:0 ADDSET: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in fmc_ker_ck
cycles (refer to Figure 99 to Figure 111), used in asynchronous accesses:
0000: ADDSET phase duration = 0 × fmc_ker_ck clock cycle
...
1111: ADDSET phase duration = 15 × fmc_ker_ck clock cycles (default value after reset)
Note: In synchronous accesses, this value is not used, the address setup phase is always 1 flash
clock period duration. In muxed mode, the minimum ADDSET value is 1.

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22.8 NAND flash controller

The FMC generates the appropriate signal timings to drive 8- and 16-bit NAND flash
memories.
The NAND bank is configured through dedicated registers (Section 22.8.7). The
programmable memory parameters include access timings (shown in Table 190) and ECC
configuration.

Table 190. Programmable NAND flash access parameters

Parameter Function Access mode Unit Min. Max.

Number of clock cycles

Memory setup (fmc_ker_ck) required to set up the AHB clock cycle
Read/Write 1 255
time address before the command (fmc_ker_ck)
assertion
Minimum duration (in fmc_ker_ck
AHB clock cycle
Memory wait clock cycles) of the command Read/Write 2 255
(fmc_ker_ck)
assertion
Number of clock cycles
(fmc_ker_ck) during which the
address must be held (as well as AHB clock cycle
Memory hold Read/Write 1 254
the data if a write access is (fmc_ker_ck)
performed) after the command
deassertion
Number of clock cycles
Memory
(fmc_ker_ck) during which the data AHB clock cycle
databus high- Write 0 254
bus is kept in high-Z state after a (fmc_ker_ck)
Z
write access has started

22.8.1 External memory interface signals

The following tables list the signals that are typically used to interface NAND flash
memories.
Note: The prefix “N” identifies the signals which are active low.

8-bit NAND flash memory

t

Table 191. 8-bit NAND flash memory

FMC pin name I/O Function

A[17] O NAND flash address latch enable (ALE) signal

A[16] O NAND flash command latch enable (CLE) signal
D[7:0] I/O 8-bit multiplexed, bidirectional address/data bus
NCE O Chip Select
NOE(= NRE) O Output enable (memory signal name: read enable, NRE)
NWE O Write enable
NWAIT/INT I NAND flash ready/busy input signal to the FMC

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Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.

16-bit NAND flash memory

Table 192. 16-bit NAND flash memory

FMC pin name I/O Function

A[17] O NAND flash address latch enable (ALE) signal

A[16] O NAND flash command latch enable (CLE) signal
D[15:0] I/O 16-bit multiplexed, bidirectional address/data bus
NCE O Chip Select
NOE(= NRE) O Output enable (memory signal name: read enable, NRE)
NWE O Write enable
NWAIT/INT I NAND flash ready/busy input signal to the FMC

Note: Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.

22.8.2 NAND flash supported memories and transactions

Table 193 shows the supported devices, access modes and transactions. Transactions not
allowed (or not supported) by the NAND flash controller are shown in gray.

Table 193. Supported memories and transactions

AXI data Memory Allowed/
Device Mode R/W Comments
size data size not allowed

Asynchronous R 8 8 Y -
Asynchronous W 8 8 Y -
Asynchronous R 16 8 Y Split into 2 FMC accesses
Asynchronous W 16 8 Y Split into 2 FMC accesses
NAND 8-bit
Asynchronous R 32 8 Y Split into 4 FMC accesses
Asynchronous W 32 8 Y Split into 4 FMC accesses
Asynchronous R 32 8 Y Split into 8 FMC accesses
Asynchronous W 32 8 Y Split into 8 FMC accesses

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Table 193. Supported memories and transactions (continued)

AXI data Memory Allowed/
Device Mode R/W Comments
size data size not allowed

Asynchronous R 8 16 Y -
Asynchronous W 8 16 N -
Asynchronous R 16 16 Y -
Asynchronous W 16 16 Y -
NAND 16-bit
Asynchronous R 32 16 Y Split into 2 FMC accesses
Asynchronous W 32 16 Y Split into 2 FMC accesses
Asynchronous R 32 16 Y Split into 4 FMC accesses
Asynchronous W 32 16 Y Split into 4 FMC accesses

22.8.3 Timing diagrams for NAND flash memories

The NAND flash memory bank is managed through a set of registers:
• Control register: FMC_PCR
• Interrupt status register: FMC_SR
• ECC register: FMC_ECCR
• Timing register for Common memory space: FMC_PMEM
• Timing register for Attribute memory space: FMC_PATT
Each timing configuration register contains three parameters used to define the number of
fmc_ker_ck cycles for the three phases of any NAND flash access, plus one parameter that
defines the timing to start driving the data bus when a write access is performed. Figure 117
shows the timing parameter definitions for common memory accesses, knowing that
Attribute memory space access timings are similar.

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Figure 117. NAND flash controller waveforms for common memory access

fmc_ker_ck

A[25:0]

NCEx

NREG, High
NIOW,
NIOR MEMxSET + 1
MEMxWAIT + 1 MEMxHOLD
NWE,
NOE(1)
MEMxHIZ
write_data

read_data Valid

MSv40387V2

1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.
2. For write accesses, the hold phase delay is (MEMHOLD) fmc_ker_ck cycles and for read access is
(MEMHOLD + 1) fmc_ker_ck cycles.

22.8.4 NAND flash operations

The command latch enable (CLE) and address latch enable (ALE) signals of the NAND
flash memory device are driven by address signals from the FMC. This means that to send
a command or an address to the NAND flash memory, the CPU has to perform a write to a
specific address in its memory space.
A typical page read operation from the NAND flash device requires the following steps:
1. Program and enable the corresponding memory bank by configuring the FMC_PCR
and FMC_PMEM (and for some devices, FMC_PATT, see Section 22.8.5: NAND flash
prewait feature) registers according to the characteristics of the NAND flash memory
(PWID bits for the data bus width of the NAND flash memory, PWAITEN = 0 or 1 as
needed, see Section 22.6.2: NAND flash memory address mapping for timing
configuration).
2. The CPU performs a byte write to the common memory space, with data byte equal to
one flash command byte (for example 0x00 for Samsung NAND flash devices). The LE
input of the NAND flash memory is active during the write strobe (low pulse on NWE),
thus the written byte is interpreted as a command by the NAND flash memory. Once
the command is latched by the memory device, it does not need to be written again for
the following page read operations.
3. The CPU can send the start address (STARTAD) for a read operation by writing four
bytes (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9],
STARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND flash memories) in
the common memory or attribute space. The ALE input of the NAND flash device is
active during the write strobe (low pulse on NWE), thus the written bytes are
interpreted as the start address for read operations. Using the attribute memory space
makes it possible to use a different timing configuration of the FMC, which can be used

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to implement the prewait functionality needed by some NAND flash memories (see
details in Section 22.8.5: NAND flash prewait feature).
4. The controller waits for the NAND flash memory to be ready (R/NB signal high), before
starting a new access to the same or another memory bank. While waiting, the
controller holds the NCE signal active (low).
5. The CPU can then perform byte read operations from the common memory space to
read the NAND flash page (data field + Spare field) byte by byte.
6. The next NAND flash page can be read without any CPU command or address write
operation. This can be done in three different ways:
– by simply performing the operation described in step 5
– a new random address can be accessed by restarting the operation at step 3
– a new command can be sent to the NAND flash device by restarting at step 2

22.8.5 NAND flash prewait feature

Some NAND flash devices require that, after writing the last part of the address, the
controller waits for the R/NB signal to go low. (see Figure 118).

Figure 118. Access to non ‘CE don’t care’ NAND-flash

1. CPU wrote byte 0x00 at address 0x7001 0000.

2. CPU wrote byte A7~A0 at address 0x7002 0000.
3. CPU wrote byte A16~A9 at address 0x7002 0000.
4. CPU wrote byte A24~A17 at address 0x7002 0000.
5. CPU wrote byte A25 at address 0x8802 0000: FMC performs a write access using FMC_PATT2 timing
definition, where ATTHOLD ≥ 7 (providing that (7+1) × fmc_ker_ck = 112 ns > tWB max). This guarantees
that NCE remains low until R/NB goes low and high again (only requested for NAND flash memories where
NCE is not don’t care).

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When this function is required, it can be performed by programming the MEMHOLD value to
meet the tWB timing. However, any CPU read access to NAND flash memory has a hold
delay of (MEMHOLD + 1) fmc_ker_ck cycles, and any CPU write access has a hold delay of
(MEMHOLD) fmc_ker_ck cycles that is inserted between the rising edge of the NWE signal
and the next access.
To cope with this timing constraint, the attribute memory space can be used by
programming its timing register with an ATTHOLD value that meets the tWB timing, and by
keeping the MEMHOLD value at its minimum value. The CPU must then use the common
memory space for all NAND flash read and write accesses, except when writing the last
address byte to the NAND flash device, where the CPU must write to the attribute memory
space.

22.8.6 Computation of the error correction code (ECC)

in NAND flash memory
The FMC includes an error correction code computation hardware block. It reduces the host
CPU workload when processing the ECC by software.The ECC block is associated with
NAND bank.
The ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit
error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read or written from/to the
NAND flash memory. It is based on the Hamming coding algorithm and consists in
calculating the row and column parity.
The ECC modules monitor the NAND flash data bus and read/write signals (NCE and NWE)
each time the NAND flash memory bank is active.
The ECC operates as follows:
• When accessing NAND flash bank, the data present on the D[15:0] bus is latched and
used for ECC computation.
• When accessing any other address in NAND flash memory, the ECC logic is idle, and
does not perform any operation. As a result, write operations to define commands or
addresses to the NAND flash memory are not taken into account for ECC computation.
Once the desired number of bytes has been read/written from/to the NAND flash memory by
the host CPU, the FMC_ECCR registers must be read to retrieve the computed value. Once
read, they should be cleared by resetting the ECCEN bit to ‘0’. To compute a new data
block, the ECCEN bit must be set to one in the FMC_PCR registers.
Execute below the sequence to perform an ECC computation:
1. Enable the ECCEN bit in the FMC_PCR register.
2. Write data to the NAND flash memory page. While the NAND page is written, the ECC
block computes the ECC value.
3. Wait until the ECC code is ready (FIFO empty).
4. Read the ECC value available in the FMC_ECCR register and store it in a variable.
5. Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back
the written data from the NAND page. While the NAND page is read, the ECC block
computes the ECC value.
6. Read the new ECC value available in the FMC_ECCR register.
7. If the two ECC values are the same, no correction is required, otherwise there is an
ECC error and the software correction routine returns information on whether the error
can be corrected or not.

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22.8.7 NAND flash controller registers

NAND flash control registers (FMC_PCR)
Address offset: 0x80
Reset value: 0x0000 0018

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
ECCPS TAR3

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWAITEN
ECCEN

PBKEN
Res.

Res.

Res.

Res.
TAR2 TAR1 TAR0 TCLR PWID

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:17 ECCPS: ECC page size.
These bits define the page size for the extended ECC:
000: 256 bytes
001: 512 bytes
010: 1024 bytes
011: 2048 bytes
100: 4096 bytes
101: 8192 bytes
Bits 16:13 TAR: ALE to RE delay.
These bits set time from ALE low to RE low in number of fmc_ker_ck clock cycles.
Time is: t_ar = (TAR + SET + 2) × tfmc_ker_ck where tfmc_ker_ck is the FMC clock period
0000: 1 x fmc_ker_ck cycle (default)
1111: 16 x fmc_ker_ck cycles
Note: Set is MEMSET or ATTSET according to the addressed space.
Bits 12:9 TCLR: CLE to RE delay.
These bits set time from CLE low to RE low in number of fmc_ker_ck clock cycles. The time
is give by the following formula:
t_clr = (TCLR + SET + 2) × tfmc_ker_ck where tfmc_ker_ck is the fmc_ker_ck clock period
0000: 1 x fmc_ker_ck cycle (default)
1111: 16 x fmc_ker_ck cycles
Note: Set is MEMSET or ATTSET according to the addressed space.
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 ECCEN: ECC computation logic enable bit
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
Bits 5:4 PWID: Data bus width.
These bits define the external memory device width.
00: 8 bits
01: 16 bits (default after reset).
10: reserved.
11: reserved.

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Bit 3 Reserved, must be kept at reset value.

Bit 2 PBKEN: NAND flash memory bank enable bit.
This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR
on AXI bus
0: Corresponding memory bank is disabled (default after reset)
1: Corresponding memory bank is enabled
Bit 1 PWAITEN: Wait feature enable bit.
This bit enables the Wait feature for the NAND flash memory bank:
0: disabled
1: enabled
Bit 0 Reserved, must be kept at reset value.

FIFO status and interrupt register (FMC_SR)

Address offset: 0x84
Reset value: 0x0000 0040
This register contains information about the FIFO status and interrupt. The FMC features a
FIFO that is used when writing to memories to transfer up to 16 words of data.
This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals
other than the FMC, while the FMC is draining its FIFO into the memory. One of these
register bits indicates the status of the FIFO, for ECC purposes.
The ECC is calculated while the data are written to the memory. To read the correct ECC,
the software must consequently wait until the FIFO is empty.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. FEMPT IFEN ILEN IREN IFS ILS IRS

r rw rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 FEMPT: FIFO empty.
Read-only bit that provides the status of the FIFO
0: FIFO not empty
1: FIFO empty
Bit 5 IFEN: Interrupt falling edge detection enable bit
0: Interrupt falling edge detection request disabled
1: Interrupt falling edge detection request enabled
Bit 4 ILEN: Interrupt high-level detection enable bit
0: Interrupt high-level detection request disabled
1: Interrupt high-level detection request enabled
Bit 3 IREN: Interrupt rising edge detection enable bit
0: Interrupt rising edge detection request disabled
1: Interrupt rising edge detection request enabled

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Bit 2 IFS: Interrupt falling edge status

The flag is set by hardware and reset by software.
0: No interrupt falling edge occurred
1: Interrupt falling edge occurred
Note: If this bit is written by software to 1 it will be set.
Bit 1 ILS: Interrupt high-level status
The flag is set by hardware and reset by software.
0: No Interrupt high-level occurred
1: Interrupt high-level occurred
Bit 0 IRS: Interrupt rising edge status
The flag is set by hardware and reset by software.
0: No interrupt rising edge occurred
1: Interrupt rising edge occurred
Note: If this bit is written by software to 1 it will be set.

Common memory space timing register (FMC_PMEM)

Address offset: Address: 0x88
Reset value: 0xFCFC FCFC
The FMC_PMEM read/write register contains the timing information for NAND flash memory
bank. This information is used to access either the common memory space of the NAND
flash for command, address write access and data read/write access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ MEMHOLD
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT MEMSET
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 MEMHIZ: Common memory x data bus Hi-Z time

These bits define the number of fmc_ker_ck clock cycles during which the data bus is kept
Hi-Z after the start of a NAND flash write access to common memory space. This is only
valid for write transactions:
0000 0000: 0 x fmc_ker_ck cycle
1111 1110: 254 x fmc_ker_ck cycles
1111 1111: reserved.
Bits 23:16 MEMHOLD: Common memory hold time
These bits define the number of fmc_ker_ck clock cycles for write accesses and
fmc_ker_ck+1 clock cycles for read accesses during which the address is held (and data for
write accesses) after the command is deasserted (NWE, NOE), for NAND flash read or write
access to common memory space:
0000 0000: reserved.
0000 0001: 1 fmc_ker_ck cycle for write access / 3 fmc_ker_ck cycle for read access
1111 1110: 254 fmc_ker_ck cycles for write access / 257 fmc_ker_ck cycles for read access
1111 1111: reserved.

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Bits 15:8 MEMWAIT: Common memory wait time

These bits define the minimum number of fmc_ker_ck (+1) clock cycles to assert the
command (NWE, NOE), for NAND flash read or write access to common memory space.
The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at
the end of the programmed value of fmc_ker_ck:
0000 0000: reserved
0000 0001: x fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1110: 255 x fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: reserved.
Bits 7:0 MEMSET: Common memory x setup time
These bits define the number of fmc_ker_ck (+1) clock cycles to set up the address before
the command assertion (NWE, NOE), for NAND flash read or write access to common
memory space:
0000 0000: fmc_ker_ck cycles
1111 1110: 255 x fmc_ker_ck cycles
1111 1111: reserved

Attribute memory space timing registers (FMC_PATT)

Address offset: 0x8C
Reset value: 0xFCFC FCFC
The FMC_PATT read/write register contains the timing information for NAND flash memory
bank. It is used for 8-bit accesses to the attribute memory space of the NAND flash for the
last address write access if the timing must differ from that of previous accesses (for
Ready/Busy management, refer to Section 22.8.5: NAND flash prewait feature).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ ATTHOLD
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT ATTSET
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 ATTHIZ: Attribute memory data bus Hi-Z time

These bits define the number of fmc_ker_ck clock cycles during which the data bus is kept in
Hi-Z after the start of a NAND flash write access to attribute memory space on socket. Only
valid for writ transaction:
0000 0000: 0 x fmc_ker_ck cycle
1111 1110: 254 x fmc_ker_ck cycles
1111 1111: reserved.
Bits 23:16 ATTHOLD: Attribute memory hold time
These bits define the number of fmc_ker_ck clock cycles during which the address is held
(and data for write access) after the command deassertion (NWE, NOE), for NAND flash
read or write access to attribute memory space:
0000 0000: reserved
0000 0001: 1 x fmc_ker_ck cycle
1111 1110: 254 x fmc_ker_ck cycles
1111 1111: reserved.

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Bits 15:8 ATTWAIT: Attribute memory wait time

These bits define the minimum number of x fmc_ker_ck (+1) clock cycles to assert the
command (NWE, NOE), for NAND flash read or write access to attribute memory space.
The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at
the end of the programmed value of fmc_ker_ck:
0000 0000: reserved
0000 0001: 2 x fmc_ker_ck cycles (+ wait cycle introduced by deassertion of NWAIT)
1111 1110: 255 x fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: reserved.
Bits 7:0 ATTSET: Attribute memory setup time
These bits define the number of fmc_ker_ck (+1) clock cycles to set up address before the
command assertion (NWE, NOE), for NAND flash read or write access to attribute memory
space:
0000 0000: 1 x fmc_ker_ck cycle
1111 1110: 255 x fmc_ker_ck cycles
1111 1111: reserved.

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ECC result registers (FMC_ECCR)

Address offset: 0x94
Reset value: 0x0000 0000
This register contain the current error correction code value computed by the ECC
computation modules of the FMC NAND controller. When the CPU reads/writes the data
from a NAND flash memory page at the correct address (refer to Section 22.8.6:
Computation of the error correction code (ECC) in NAND flash memory), the data
read/written from/to the NAND flash memory are processed automatically by the ECC
computation module. When X bytes have been read (according to the ECCPS field in the
FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC
registers. It then verifies if these computed parity data are the same as the parity value
recorded in the spare area, to determine whether a page is valid, and, to correct it
otherwise. The FMC_ECCR register should be cleared after being read by setting the
ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to ’1’.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 ECC[31:0]: ECC result

This field contains the value computed by the ECC computation logic. Table 194 describes
the contents of these bitfields.

Table 194. ECC result relevant bits

ECCPS[2:0] Page size in bytes ECC bits

000 256 ECC[21:0]

001 512 ECC[23:0]
010 1024 ECC[25:0]
011 2048 ECC[27:0]
100 4096 ECC[29:0]
101 8192 ECC[31:0]

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22.9 SDRAM controller

22.9.1 SDRAM controller main features

The main features of the SDRAM controller are the following:
• Two SDRAM banks with independent configuration
• 8-bit, 16-bit, 32-bit data bus width
• 13-bits Address Row, 11-bits Address Column, 4 internal banks: 4x16Mx32bit
(256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB)
• Word, half-word, byte access
• SDRAM clock can be fmc_ker_ck/2 or fmc_ker_ck/3
• Automatic row and bank boundary management
• Multibank ping-pong access
• Programmable timing parameters
• Automatic Refresh operation with programmable Refresh rate
• Self-refresh mode
• Power-down mode
• SDRAM power-up initialization by software
• CAS latency of 1,2,3
• Cacheable Read FIFO with depth of 6 lines x32-bit (6 x14-bit address tag)

22.9.2 SDRAM External memory interface signals

At startup, the SDRAM I/O pins used to interface the FMC SDRAM controller with the
external SDRAM devices must configured by the user application. The SDRAM controller
I/O pins which are not used by the application, can be used for other purposes.

Table 195. SDRAM signals

I/O
SDRAM signal Description Alternate function
type

SDCLK O SDRAM clock -

SDCKE0: SDRAM Bank 1 Clock Enable
SDCKE[1:0] O -
SDCKE1: SDRAM Bank 2 Clock Enable
SDNE0: SDRAM Bank 1 Chip Enable
SDNE[1:0] O -
SDNE1: SDRAM Bank 2 Chip Enable
A[12:0] O Address FMC_A[12:0]
D[31:0] I/O Bidirectional data bus FMC_D[31:0]
BA[1:0] O Bank Address FMC_A[15:14]
NRAS O Row Address Strobe -
NCAS O Column Address Strobe -
SDNWE O Write Enable -
Output Byte Mask for write accesses
NBL[3:0] O FMC_NBL[3:0]
(memory signal name: DQM[3:0]

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22.9.3 SDRAM controller functional description

All SDRAM controller outputs (signals, address and data) change on the falling edge of the
memory clock (FMC_SDCLK).

SDRAM initialization
The initialization sequence is managed by software. If the two banks are used, the
initialization sequence must be generated simultaneously to Bank 1and Bank 2 by setting
the Target Bank bits CTB1 and CTB2 in the FMC_SDCMR register:
1. Program the memory device features into the FMC_SDCRx register. The SDRAM
clock frequency, RBURST and RPIPE must be programmed in the FMC_SDCR1
register.
2. Program the memory device timing into the FMC_SDTRx register. The TRP and TRC
timings must be programmed in the FMC_SDTR1 register.
3. Set MODE bits to ‘001’ and configure the Target Bank bits (CTB1 and/or CTB2) in the
FMC_SDCMR register to start delivering the clock to the memory (SDCKE is driven
high).
4. Wait during the prescribed delay period. Typical delay is around 100 μs (refer to the
SDRAM datasheet for the required delay after power-up).
5. Set MODE bits to ‘010’ and configure the Target Bank bits (CTB1 and/or CTB2) in the
FMC_SDCMR register to issue a “Precharge All” command.
6. Set MODE bits to ‘011’, and configure the Target Bank bits (CTB1 and/or CTB2) as well
as the number of consecutive Auto-refresh commands (NRFS) in the FMC_SDCMR
register. Refer to the SDRAM datasheet for the number of Auto-refresh commands that
should be issued. Typical number is 8.
7. Configure the MRD field, set the MODE bits to ‘100’, and configure the Target Bank bits
(CTB1 and/or CTB2) in the FMC_SDCMR register to issue a “Load Mode Register”
command and program the SDRAM device. In particular the Burst Length (BL) has to
be set to ‘1’) and the CAS latency has to be selected. If the Mode Register is not the
same for both SDRAM banks, this step has to be repeated twice, once for each bank
and the Target Bank bits set accordingly. For mobile SDRAM devices, the MRD field is
also used to configure the extended mode register while issuing the Load Mode
Register”
8. Program the refresh rate in the FMC_SDRTR register
The refresh rate corresponds to the delay between refresh cycles. Its value must be
adapted to SDRAM devices.
At this stage the SDRAM device is ready to accept commands. If a system reset occurs
during an ongoing SDRAM access, the data bus might still be driven by the SDRAM device.
Therefor the SDRAM device must be first reinitialized after reset before issuing any new
access by the NOR flash/PSRAM/SRAM or NAND flash controller.
Note: If two SDRAM devices are connected to the FMC, all the accesses performed at the same
time to both devices by the Command Mode register (Load Mode Register command) are
issued using the timing parameters configured for SDRAM Bank 1 (TMRD andTRAS
timings) in the FMC_SDTR1 register.

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SDRAM controller write cycle

The SDRAM controller accepts single and burst write requests and translates them into
single memory accesses. In both cases, the SDRAM controller keeps track of the active row
for each bank to be able to perform consecutive write accesses to different banks (Multibank
ping-pong access).
Before performing any write access, the SDRAM bank write protection must be disabled by
clearing the WP bit in the FMC_SDCRx register.

Figure 119. Burst write SDRAM access waveforms

TRCD = 3

SDNE

SDCLK

A[12:0] Row n Cola Colb Colc Cold Cole Colf Cog Colh Coli Colj Colk Coll

NRAS

NCAS

SDNWE

DATA[31:0] Dna Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl

MS30448V3

The SDRAM controller always checks the next access.

• If the next access is in the same row or in another active row, the write operation is
carried out,
• if the next access targets another row (not active), the SDRAM controller generates a
precharge command, activates the new row and initiates a write command.

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SDRAM controller read cycle

The SDRAM controller accepts single and burst read requests and translates them into
single memory accesses. In both cases, the SDRAM controller keeps track of the active row
in each bank to be able to perform consecutive read accesses in different banks (Multibank
ping-pong access).

Figure 120. Burst read SDRAM access

TRCD = 3 CAS latency = 2

SDNE

SDCLK

A[12:0] Row n Cola Colb Colc Cold Cole Colf

NRAS

NCAS

NWE

DATA[31:0] Dna Dnb Dnc Dnd Dne Dnf

MS30449V3

The FMC SDRAM controller features a Cacheable read FIFO (6 lines x 32 bits). It is used to
store data read in advance during the CAS latency period (up to 3 memory clock cycles,
programmed FMC_SDCRx) and during the RPIPE delay when set to 2xfmc_ker_ck clock
cycles as configured in FMC_SDCR1) following this formula: CAS Latency + 1 + (RPIPE
DIV2). The RBURST bit must be set in the FMC_SDCR1 register to anticipate the next read
access.
Examples:
• CAS=3, RPIPE= 2xfmc_ker_ck. In this case, 5 data (not committed) are stored in the
FIFO (4 data during CAS latency and 1 data during RPIPE delay)
• CAS=3, RPIPE= 1xfmc_ker_ck. In this case, 4 data (not committed) are stored in the
FIFO (4 data during CAS latency)
The read FIFO features a 14-bit address tag to each line to identify its content: 11 bits for the
column address, 2 bits to select the internal bank and the active row, and 1 bit to select the
SDRAM device
When the end of the row is reached in advance during an burst read transaction, the data
read in advance (not committed) are not stored in the read FIFO. For single read access,
data are correctly stored in the FIFO.

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Each time a read request occurs, the SDRAM controller checks:

• If the address matches one of the address tags, data are directly read from the FIFO
and the corresponding address tag/ line content is cleared and the remaining data in
the FIFO are compacted to avoid empty lines.
• Otherwise, a new read command is issued to the memory and the FIFO is updated with
new data. If the FIFO is full, the older data are lost.

Figure 121. Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0)

1st Read access: Requested data is not in the FIFO

FMC SDRAM Controller

read request@0x00 SDRAM

AXI Master Data 1 Device
(CAS = 1)

@0x04 Data 2
6 lines FIFO @0x08 Data 3
Data stored in FIFO
... ...
in advance during
Add. Tag read FIFO the CAS latency period

2nd Read access : Requested data was previously stored in the FIFO

Address matches with

one of the address tags FMC SDRAM Controller

read request@0x04 SDRAM

AXI Master Data 2 Device
(CAS = 1)

@0x04 Data 2
6 lines FIFO @0x08 Data 3
... ...
Data read from FIFO
Add. Tag read FIFO

MS30445V2

During a write access or a Precharge command, the read FIFO is flushed and ready to be
filled with new data.
After the first read request, if the current access was not performed to a row boundary, the
SDRAM controller anticipates the next read access during the CAS latency period and the
RPIPE delay (if configured). This is done by incrementing the memory address. The
following condition must be met:
• RBURST control bit should be set to ‘1’ in the FMC_SDCR1 register.

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The address management depends on the next AXI request:

• Next request is sequential (Burst access)
In this case, the SDRAM controller increments the address.
• Next request is not sequential
– If the new read request targets the same row or another active row, the new
address is passed to the memory and the master is stalled for the CAS latency
period, waiting for the new data from memory.
– If the new read request does not target an active row, the SDRAM controller
generates a Precharge command, activates the new row, and initiates a read
command.
If the RBURST is reset, the read FIFO is not used.

Row and bank boundary management

When a read or write access crosses a row boundary, if the next read or write access is
sequential and the current access was performed to a row boundary, the SDRAM controller
executes the following operations:
1. Precharge of the active row,
2. Activation of the new row
3. Start of a read/write command.
At a row boundary, the automatic activation of the next row is supported for all columns and
data bus width configurations.
If necessary, the SDRAM controller inserts additional clock cycles between the following
commands:
• Between Precharge and Active commands to match TRP parameter (only if the next
access is in a different row in the same bank),
• Between Active and Read commands to match the TRCD parameter.
These parameters are defined into the FMC_SDTRx register.
Refer to Figure 119 and Figure 120 for read and burst write access crossing a row
boundary.

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Figure 122. Read access crossing row boundary

TRP = 3 TRCD = 3 CAS latency = 2

SDNE

SDCLK
Row n

A[12:0] Col a Row n +1 Col a Col b

NRAS

NCAS

NWE

Data[31:0] Dna Dn+1 a

Precharge Activate Row Read Command

MS30446V2

Figure 123. Write access crossing row boundary

TRP = 3 TRCD = 3

SDNE

SDCLK

A[12:0] Cna Colb Row n+1 Cola Colb

NRAS

NCAS

NWE

Data[31:0] Dna Dnb Dn+1a Dn+1b

Precharge Activate Row Write command

MS30447V2

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If the next access is sequential and the current access crosses a bank boundary, the
SDRAM controller activates the first row in the next bank and initiates a new read/write
command. Two cases are possible:
• If the current bank is not the last one, the active row in the new bank must be
precharged.At a bank boundary, the automatic activation of the next row is supported
for all rows/columns and data bus width configuration.
• If the current bank is the last one, the automatic activation of the next row is supported
only when addressing 13-bit rows, 11-bit columns, 4 internal banks and 32-bit data bus
SDRAM devices. Otherwise, the SDRAM address range is violated and an AXI slave
error is generated.
• In case of 13-bit row address, 11-bit column address, 4 internal banks and bus width
32-bit SDRAM memories, at boundary bank, the SDRAM controller continues to
read/write from the second SDRAM device (assuming it has been initialized):
a) The SDRAM controller activates the first row (after precharging the active row, if
there is already an active row in the first internal bank, and initiates a new
read/write command.
b) If the first row is already activated, the SDRAM controller just initiates a read/write
command.
SDRAM controller refresh cycle
The Auto-refresh command is used to refresh the SDRAM device content. The SDRAM
controller periodically issues auto-refresh commands. An internal counter is loaded with the
COUNT value in the register FMC_SDRTR. This value defines the number of memory clock
cycles between the refresh cycles (refresh rate). When this counter reaches zero, an
internal pulse is generated.
If a memory access is ongoing, the auto-refresh request is delayed. However, if the memory
access and the auto-refresh requests are generated simultaneously, the auto-refresh
request takes precedence.
If the memory access occurs during an auto-refresh operation, the request is buffered and
processed when the auto-refresh is complete.
If a new auto-refresh request occurs while the previous one was not served, the RE
(Refresh Error) bit is set in the Status register. An Interrupt is generated if it has been
enabled (REIE = ‘1’).
If SDRAM lines are not in idle state (not all row are closed), the SDRAM controller generates
a PALL (Precharge ALL) command before the auto-refresh.
If the Auto-refresh command is generated by the FMC_SDCMR Command Mode register
(Mode bits = ‘011’), a PALL command (Mode bits =’ 010’) must be issued first.

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22.9.4 Low-power modes

Two low-power modes are available:
• Self-refresh mode
The auto-refresh cycles are performed by the SDRAM device itself to retain data
without external clocking.
• Power-down mode
The auto-refresh cycles are performed by the SDRAM controller.

Self-refresh mode
This mode is selected by setting the MODE bits to ‘101’ and by configuring the Target Bank
bits (CTB1 and/or CTB2) in the FMC_SDCMR register.
The SDRAM clock stops running after a TRAS delay and the internal refresh timer stops
counting only if one of the following conditions is met:
• A Self-refresh command is issued to both devices
• One of the devices is not activated (SDRAM bank is not initialized).
Before entering Self-Refresh mode, the SDRAM controller automatically issues a PALL
command.
If the Write data FIFO is not empty, all data are sent to the memory before activating the
Self-refresh mode and the BUSY status flag remains set.
In Self-refresh mode, all SDRAM device inputs become don’t care except for SDCKE which
remains low.
The SDRAM device must remain in Self-refresh mode for a minimum period of time of
TRAS and can remain in Self-refresh mode for an indefinite period beyond that. To
guarantee this minimum period, the BUSY status flag remains high after the Self-refresh
activation during a TRAS delay.
As soon as an SDRAM device is selected, the SDRAM controller generates a sequence of
commands to exit from Self-refresh mode. After the memory access, the selected device
remains in Normal mode.
To exit from Self-refresh, the MODE bits must be set to ‘000’ (Normal mode) and the Target
Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.

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Figure 124. Self-refresh mode

T0 T1 T2 Tn+1 T0+1 T0+2

SDCLK

tRAS(min)

SDCKE

COMMAND AUTO NOP or COMMAND AUTO

PRECHARGE NOP
REFRESH INHERIT REFRESH

DOM/
DOML/DOMU

A0- A9
A11, A12

A10 ALL
BANKS

Data[31:0] Hi-Z
tRP tXSR
Precharge all Exit Self-refresh mode
Enter Self-refresh mode
active banks (restart refresh timebase)
CLK stable prior to existing
Self-refresh mode
MS30450V1

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Power-down mode
This mode is selected by setting the MODE bits to ‘110’ and by configuring the Target Bank
bits (CTB1 and/or CTB2) in the FMC_SDCMR register.

Figure 125. Power-down mode

SDCLK

SDCKE

COMMAND NOP NOP ACTIVE

tRCD
All banks idle Input buffers gated off
tRAS
Enter Power-down Exit Power-down tRC

MS30451V1

If the Write data FIFO is not empty, all data are sent to the memory before activating the
Power-down mode.
As soon as an SDRAM device is selected, the SDRAM controller exits from the Power-down
mode. After the memory access, the selected SDRAM device remains in Normal mode.
During Power-down mode, all SDRAM device input and output buffers are deactivated
except for the SDCKE which remains low.
The SDRAM device cannot remain in Power-down mode longer than the refresh period and
cannot perform the Auto-refresh cycles by itself. Therefore, the SDRAM controller carries
out the refresh operation by executing the operations below:
1. Exit from Power-down mode and drive the SDCKE high
2. Generate the PALL command only if a row was active during Power-down mode
3. Generate the auto-refresh command
4. Drive SDCKE low again to return to Power-down mode.
To exit from Power-down mode, the MODE bits must be set to ‘000’ (Normal mode) and the
Target Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.

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22.9.5 SDRAM controller registers

SDRAM Control registers for SDRAM memory bank x (FMC_SDCRx)
Address offset: 0x140+ 4* (x - 1), (x = 1 to 2)
Reset value: 0x0000 02D0
This register contains the control parameters for each SDRAM memory bank

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDCLK[1:0]
RPIPE[1:0]

MWID[1:0]
RBURST

CAS[1:0]

NR[1:0]

NC[1:0]
Res.

WP

NB
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:13 RPIPE[1:0]: Read pipe
These bits define the delay, in fmc_ker_ck clock cycles, for reading data after CAS latency.
00: No fmc_ker_ck clock cycle delay
01: One fmc_ker_ck clock cycle delay
10: Two fmc_ker_ck clock cycle delay
11: reserved.
Note: The corresponding bits in the FMC_SDCR2 register is read only.
Bit 12 RBURST: Burst read
This bit enables Burst read mode. The SDRAM controller anticipates the next read commands
during the CAS latency and stores data in the Read FIFO.
0: single read requests are not managed as bursts
1: single read requests are always managed as bursts
Note: The corresponding bit in the FMC_SDCR2 register is read only.
Bits 11:10 SDCLK[1:0]: SDRAM clock configuration
These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock
before changing the frequency. In this case the SDRAM must be re-initialized.
00: SDCLK clock disabled
01: Reserved
10: SDCLK period = 2 x fmc_ker_ck periods
11: SDCLK period = 3 x fmc_ker_ck periods
Note: The corresponding bits in the FMC_SDCR2 register is read only.
Bit 9 WP: Write protection
This bit enables Write mode access to the SDRAM bank.
0: Write accesses allowed
1: Write accesses ignored

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Bits 8:7 CAS[1:0]: CAS Latency

This bits sets the SDRAM CAS latency in number of memory clock cycles
00: reserved.
01: 1 cycle
10: 2 cycles
11: 3 cycles
Bit 6 NB: Number of internal banks
This bit sets the number of internal banks.
0: Two internal Banks
1: Four internal Banks
Bits 5:4 MWID[1:0]: Memory data bus width.
These bits define the memory device width.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved.
Bits 3:2 NR[1:0]: Number of row address bits
These bits define the number of bits of a row address.
00: 11 bit
01: 12 bits
10: 13 bits
11: reserved.
Bits 1:0 NC[1:0]: Number of column address bits
These bits define the number of bits of a column address.
00: 8 bits
01: 9 bits
10: 10 bits
11: 11 bits.

Note: Before modifying the RBURST or RPIPE settings or disabling the SDCLK clock, the user
must first send a PALL command to make sure ongoing operations are complete.

SDRAM Timing registers for SDRAM memory bank x (FMC_SDTRx)

Address offset: 0x148 + 4 * (x - 1), (x = 1 to 2)
Reset value: 0x0FFF FFFF
This register contains the timing parameters of each SDRAM bank

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. TRCD TRP TWR

rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRC TRAS TXSR TMRD
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 TRCD[3:0]: Row to column delay
These bits define the delay between the Activate command and a Read/Write command in number
of memory clock cycles.
0000: 1 cycle.
0001: 2 cycles
....
1111: 16 cycles
Bits 23:20 TRP[3:0]: Row precharge delay
These bits define the delay between a Precharge command and another command in number of
memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two
SDRAM devices are used, the TRP must be programmed with the timing of the slowest device.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: The corresponding bits in the FMC_SDTR2 register are don’t care.
Bits 19:16 TWR[3:0]: Recovery delay
These bits define the delay between a Write and a Precharge command in number of memory clock
cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM
datasheet, and to guarantee that:
TWR ≥ TRAS - TRCD and TWR ≥ TRC - TRCD - TRP
Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be
programmed to 0x1.
If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed
with the same TWR timing corresponding to the slowest SDRAM device.
If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the
not used bank.
Bits 15:12 TRC[3:0]: Row cycle delay
These bits define the delay between the Refresh command and the Activate command, as well as
the delay between two consecutive Refresh commands. It is expressed in number of memory clock
cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are
used, the TRC must be programmed with the timings of the slowest device.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM
device datasheet.
Note: The corresponding bits in the FMC_SDTR2 register are don’t care.

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Bits 11:8 TRAS[3:0]: Self refresh time

These bits define the minimum Self-refresh period in number of memory clock cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Bits 7:4 TXSR[3:0]: Exit Self-refresh delay
These bits define the delay from releasing the Self-refresh command to issuing the Activate
command in number of memory clock cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed
with the same TXSR timing corresponding to the slowest SDRAM device.
Bits 3:0 TMRD[3:0]: Load Mode Register to Active
These bits define the delay between a Load Mode Register command and an Active or Refresh
command in number of memory clock cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles

Note: If two SDRAM devices are connected, all the accesses performed simultaneously to both
devices by the Command Mode register (Load Mode Register command) are issued using
the timing parameters configured for Bank 1 (TMRD and TRAS timings) in the FMC_SDTR1
register.
The TRP and TRC timings are only configured in the FMC_SDTR1 register. If two SDRAM
devices are used, the TRP and TRC timings must be programmed with the timings of the
slowest device.

SDRAM Command mode register (FMC_SDCMR)

Address offset: 0x150
Reset value: 0x0000 0000
This register contains the command issued when the SDRAM device is accessed. This
register is used to initialize the SDRAM device, and to activate the Self-refresh and the
Power-down modes. As soon as the MODE field is written, the command will be issued only
to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register
is the same for both SDRAM banks.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. MRD

rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MRD NRFS CTB1 CTB2 MODE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

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Bits 22:9 MRD[13:0]: Mode Register definition

This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed
using the Load Mode Register command. The MRD[13:0] bits are also used to program the
extended mode register for mobile SDRAM.
Bits 8:5 NRFS[3:0]: Number of Auto-refresh
These bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’.
0000: 1 Auto-refresh cycle
0001: 2 Auto-refresh cycles
....
1110: 15 Auto-refresh cycles
1111: 16 Auto-refresh cycles
Bit 4 CTB1: Command Target Bank 1
This bit indicates whether the command will be issued to SDRAM Bank 1 or not.
0: Command not issued to SDRAM Bank 1
1: Command issued to SDRAM Bank 1
Bit 3 CTB2: Command Target Bank 2
This bit indicates whether the command will be issued to SDRAM Bank 2 or not.
0: Command not issued to SDRAM Bank 2
1: Command issued to SDRAM Bank 2
Bits 2:0 MODE[2:0]: Command mode
These bits define the command issued to the SDRAM device.
000: Normal Mode
001: Clock Configuration Enable
010: PALL (“All Bank Precharge”) command
011: Auto-refresh command
100: Load Mode Register
101: Self-refresh command
110: Power-down command
111: Reserved
Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be
set otherwise the command will be ignored.
Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued
simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will
be ignored.
Note: If only one SDRAM bank is used and a command is issued with it’s associated CTB bit set, the
other CTB bit of the unused bank must be kept to 0.

SDRAM refresh timer register (FMC_SDRTR)

Address offset: 0x154
Reset value: 0x0000 0000
This register sets the refresh rate in number of SDCLK clock cycles between the refresh
cycles by configuring the Refresh Timer Count value.
Refresh rate = ( COUNT + 1 ) × SDRAM clock frequency

COUNT = ( SDRAM refresh period ⁄ Number of rows ) – 20

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RM0433 Flexible memory controller (FMC)

Below an example of refresh rate calculation:

Refresh rate = 64 ms ⁄ ( 8196rows ) = 7.81μs

where 64 ms is the SDRAM refresh period.

7.81μs × 60MHz = 468.6

The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to
obtain a safe margin if an internal refresh request occurs when a read request has been
accepted. It corresponds to a COUNT value of ‘0000111000000’ (448).
This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This
timer generates a refresh pulse when zero is reached. The COUNT value must be set at
least to 41 SDRAM clock cycles.
As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value
programmed in the register is ’0’, no refresh is carried out. This register must not be
reprogrammed after the initialization procedure to avoid modifying the refresh rate.
Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.
If a memory access is in progress, the Auto-refresh request is delayed. However, if the
memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh
takes precedence. If the memory access occurs during a refresh operation, the request is
buffered to be processed when the refresh is complete.
This register is common to SDRAM bank 1 and bank 2.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. REIE COUNT CRE

rw rw rw rw rw rw rw rw rw rw rw rw rw rw w

Bits 31: 15 Reserved, must be kept at reset value.

Bit 14 REIE: RES Interrupt Enable
0: Interrupt is disabled
1: An Interrupt is generated if RE = 1
Bits 13:1 COUNT[12:0]: Refresh Timer Count
This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory
clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29).
Refresh rate = (COUNT + 1) x SDRAM frequency clock
COUNT = (SDRAM refresh period / Number of rows) - 20
Bit 0 CRE: Clear Refresh error flag
This bit is used to clear the Refresh Error Flag (RE) in the Status Register.
0: no effect
1: Refresh Error flag is cleared

Note: The programmed COUNT value must not be equal to the sum of the following timings:
TWR+TRP+TRC+TRCD+4 memory clock cycles .

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878
Flexible memory controller (FMC) RM0433

SDRAM Status register (FMC_SDSR)

Address offset: 0x158
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MODES2

MODES1
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

RE
r r r r r

Bits 31:5 Reserved, must be kept at reset value.

Bits 4:3 MODES2: Status Mode for Bank 2
These bits define the Status Mode of SDRAM Bank 2.
00: Normal Mode
01: Self-refresh mode
10: Power-down mode
Bits 2:1 MODES1: Status Mode for Bank 1
These bits define the Status Mode of SDRAM Bank 1.
00: Normal Mode
01: Self-refresh mode
10: Power-down mode
Bit 0 RE: Refresh error flag
0: No refresh error has been detected
1: A refresh error has been detected
An interrupt is generated if REIE = 1 and RE = 1

22.9.6 FMC register map

The following table summarizes the FMC registers.

Table 196. FMC register map

Register name
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0

reset value
ASYNCWAIT ASYNCWAIT
CBURSTRW CBURSTRW

CPSIZE[2:0]
BMAP[1:0]

BURSTEN
WAITCFG

WAITPOL
EXTMOD
CCLKEN

FACCEN
WAITEN

MUXEN
MBKEN
FMCEN

WFDIS

WREN

MTYP
MWID
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.

0x00 FMC_BCR1
BURSTEN
WAITCFG

WAITPOL
EXTMOD

FACCEN
WAITEN

MUXEN
MBKEN
WREN

CPSIZE MWID MTYP

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.

FMC_BCR2
0x08 [2:0] [1:0] [1:0]

Reset value 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0
ASYNCWAIT
CBURSTRW

BURSTEN
WAITCFG

WAITPOL
EXTMOD

FACCEN
WAITEN

MUXEN
MBKEN
WREN

CPSIZE MWID MTYP

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.

FMC_BCR3
0x10 [2:0] [1:0] [1:0]

Reset value 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0

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RM0433 Flexible memory controller (FMC)

Table 196. FMC register map (continued)

Register name
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
reset value

ASYNCWAIT
CBURSTRW

BURSTEN
WAITCFG

WAITPOL
EXTMOD

FACCEN
WAITEN

MUXEN
MBKEN
WREN
CPSIZE MWID MTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
FMC_BCR4
0x18 [2:0] [1:0] [1:0]

Reset value 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0
ACCM
Res.
Res.

FMC_BTR1 DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0x04 OD[1:0]
Reset value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ACCM
Res.
Res.

FMC_BTR2 DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0x0C OD[1:0]
Reset value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ACCM
Res.
Res.

FMC_BTR3 DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0x14 OD[1:0]
Reset value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ACCM
Res.
Res.

FMC_BTR4 DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0x1C OD[1:0]
Reset value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ACCM
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

FMC_BWTR1 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0x104 OD[1:0]
Reset value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ACCM
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

FMC_BWTR2 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0x10C OD[1:0]
Reset value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ACCM
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

FMC_BWTR3 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0x114 OD[1:0]
Reset value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ACCM
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

FMC_BWTR4 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0x11C OD[1:0]
Reset value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PWAITEN
ECCEN

PBKEN
ECCPS PWID
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
FMC_PCR TAR[3:0] TCLR[3:0]
0x80 [2:0] [1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
FEMPT

IREN
IFEN
ILEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

IRS
FMC_SR IFS
ILS
0x84
Reset value 1 0 0 0 0 0 0
FMC_PMEM MEMHIZx[7:0] MEMHOLDx[7:0] MEMWAITx[7:0] MEMSETx[7:0]
0x88
Reset value 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0
FMC_PATT ATTHIZ[7:0] ATTHOLD[7:0] ATTWAIT[7:0] ATTSET[7:0]
0x8C
Reset value 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0
FMC_ECCR ECC[31:0]
0x94
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RBURST

RPIPE[ SDCLK CAS MWID

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

FMC_SDCR1 WP NB NR[1:0] NC
0x140 1:0] [1:0] [1:0] [1:0]

Reset value 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0
RBURST

RPIPE SDCLK CAS MWID

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

FMC_SDCR2 WP NB NR[1:0] NC
0x144 [1:0] [1:0] [1:0] [1:0]

Reset value 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0
Res.
Res.
Res.
Res.

FMC_SDTR1 TRCD[3:0] TRP[3:0] TWR[3:0] TRC[3:0] TRAS[3:0] TXSR[3:0] TMRD[3:0]

0x148
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

RM0433 Rev 8 877/3353

878
Flexible memory controller (FMC) RM0433

Table 196. FMC register map (continued)

Register name
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
reset value

Res.
Res.
Res.
Res.
FMC_SDTR2 TRCD[3:0] TRP[3:0] TWR[3:0] TRC[3:0] TRAS[3:0] TXSR[3:0] TMRD[3:0]
0x14C
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CTB1
CTB2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_SDCMR MRD NRFS[3:0] MODE[2:0]
0x150
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

REIE

CRE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_SDRTR COUNT[12:0]
0x154
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODES2[1:0]

MODES1[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_SDSR

RE
0x158

Reset value 0 0 0 0 0

Refer to Section 2.3 on page 129 for the register boundary addresses.

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RM0433 Quad-SPI interface (QUADSPI)

23 Quad-SPI interface (QUADSPI)

23.1 Introduction
The QUADSPI is a specialized communication interface targeting single, dual- or quad-SPI
flash memories. It can operate in any of the three following modes:
• indirect mode: all the operations are performed using the QUADSPI registers.
• automatic status-polling mode: the external flash memory status register is periodically
read and an interrupt can be generated in case of flag setting.
• memory-mapped mode: the external flash memory is mapped to the device address
space and is seen by the system as if it was an internal memory.
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
Quad-SPI flash memories are accessed simultaneously.

23.2 QUADSPI main features

• Three functional modes: indirect, automatic status-polling, and memory-mapped
• Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two
flash memories in parallel
• SDR and DDR support
• Fully programmable opcode for both indirect and memory-mapped modes
• Fully programmable frame format for both indirect and memory-mapped modes
• Integrated FIFO for reception and transmission
• 8-, 16-, and 32-bit data accesses allowed
• MDMA trigger generation for FIFO threshold and transfer complete
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error

23.3 QUADSPI functional description

23.3.1 QUADSPI block diagram

Figure 126. QUADSPI block diagram when dual-flash mode is disabled

32-bit
QUADSPI
AHB bus Clock
Registers /
control management
SPI FLASH
quadspi_ker_ck
CLK
quadspi_hclk CLK
BK1_IO0/SO
quadspi_it Q0/SI
BK1_IO1/SI
quadspi_ft_trg Q1/SO
BK1_IO2
quadspi_tc_trg FIFO Shift register Q2/WP
BK1_IO3
64-bit
Q3/HOLD
BK1_NCS
AXI bus CS

MSv43724V3

RM0433 Rev 8 879/3353

906
Quad-SPI interface (QUADSPI) RM0433

Figure 127. QUADSPI block diagram when dual-flash mode is enabled

QUADSPI
32-bit Registers / Clock
AHB bus control management
SPI FLASH 1
CLK
quadspi_ker_ck CLK
BK1_IO0/SO
Q0/SI
quadspi_hclk BK1_IO1/SI
Q1/SO
BK1_IO2
quadspi_it Q2/WP
BK1_IO3
Q3/HOLD
quadspi_ft_trg BK1_NCS
CS
quadspi_tc_trg
Shift register SPI FLASH 2

64-bit FIFO CLK

BK2_IO0/SO
AXI bus Q0/SI
BK2_IO1/SI
Q1/SO
BK2_IO2
Q2/WP
BK2_IO3
Q3/HOLD
BK2_NCS
CS
MSv43725V3

23.3.2 QUADSPI pins and internal signals

The table below lists the QUADSPI internal signals.

Table 197. QUADSPI internal signals

Signal name Signal type Description

quadspi_ker_ck Digital input QUADSPI kernel clock

quadspi_hclk Digital input QUADSPI register interface clock
quadspi_it Digital output QUADSPI global interrupt
quadspi_ft_trg Digital output QUADSPI FIFO threshold trigger for MDMA
quadspi_tc_trg Digital output QUADSPI transfer complete trigger for MDMA

The table below lists the QUADSPI pins, six for interfacing with a single flash memory, or 10
to 11 for interfacing with two flash memories (FLASH 1 and FLASH 2) in dual-flash mode.

Table 198. QUADSPI pins

Signal name Signal type Description

CLK Digital output Clock to FLASH 1 and FLASH 2

BK1_IO0/SO Digital input/output Bidirectional I/O in dual/quad modes or serial output in single mode, for FLASH 1
BK1_IO1/SI Digital input/output Bidirectional I/O in dual/quad modes or serial input in single mode, for FLASH 1
BK1_IO2 Digital input/output Bidirectional I/O in quad mode, for FLASH 1
BK1_IO3 Digital input/output Bidirectional I/O in quad mode, for FLASH 1
BK2_IO0/SO Digital input/output Bidirectional I/O in dual/quad modes or serial output in single mode, for FLASH 2

880/3353 RM0433 Rev 8

RM0433 Quad-SPI interface (QUADSPI)

Table 198. QUADSPI pins (continued)

Signal name Signal type Description

BK2_IO1/SI Digital input/output Bidirectional I/O in dual/quad modes or serial input in single mode, for FLASH 2
BK2_IO2 Digital input/output Bidirectional I/O in quad mode, for FLASH 2
BK2_IO3 Digital input/output Bidirectional I/O in quad mode, for FLASH 2
Chip select (active low) for FLASH 1. Can also be used for FLASH 2 if QUADSPI
BK1_NCS Digital output
is always used in dual-flash mode.
Chip select (active low) for FLASH 2. Can also be used for FLASH 1 if QUADSPI
BK2_NCS Digital output
is always used in dual-flash mode.

23.3.3 QUADSPI command sequence

The QUADSPI communicates with the flash memory using commands. Each command can
include five phases: instruction, address, alternate byte, dummy, data. Any of these phases
can be configured to be skipped, but at least one of the instruction, address, alternate byte,
or data phase must be present.
NCS falls before the start of each command and rises again after each command finishes.

Figure 128. Example of read command in quad-SPI mode

Instruction Address Alt. Dummy Data

NCS
SCLK
IO0 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 4 0 4 0

IO1 5 1 5 1 5 1 5 1 5 1 5 1

IO2 6 2 6 2 6 2 6 2 6 2 6 2

IO3 7 3 7 3 7 3 7 3 7 3 7 3
A23-16 A15-8 A7-0 M7-0 Byte 1 Byte 2

I/O switch from output to input

MS35317V2

Instruction phase
During this phase, an 8-bit instruction, configured in INSTRUCTION bitfield of
QUADSPI_CCR[7:0] register, is sent to the flash memory, specifying the type of operation to
be performed.
Most flash memories can receive instructions only one bit at a time from the IO0/SO signal
(single-SPI mode), the instruction phase can optionally send 2 bits at a time (over IO0/IO1 in
dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI mode). This can be
configured using the IMODE[1:0] bitfield of QUADSPI_CCR[9:8] register.
When IMODE = 00, the instruction phase is skipped, and the command sequence starts
with the address phase, if present.

Address phase
In the address phase, 1-4 bytes are sent to the flash memory to indicate the address of
the operation. The number of address bytes to be sent is configured in the ADSIZE[1:0]
bitfield of QUADSPI_CCR[13:12] register. In indirect and automatic status-polling modes,

RM0433 Rev 8 881/3353

906
Quad-SPI interface (QUADSPI) RM0433

address bytes to be sent are specified in the ADDRESS[31:0] bitfield of QUADSPI_AR

register, while in memory-mapped mode, the address is given directly via the AXI (from the
Cortex or from a DMA).
The address phase can send 1 bit at a time (over SO in single-SPI mode), 2 bits at a time
(over IO0/IO1 in dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI
mode). This can be configured using the ADMODE[1:0] bitfield of QUADSPI_CCR[11:10]
register.
When ADMODE = 00, the address phase is skipped, and the command sequence proceeds
directly to the next phase, if any.

Alternate-byte phase
In the alternate-byte phase, 1-4 bytes are sent to the flash memory, generally to control the
mode of operation. The number of alternate bytes to be sent is configured in the [1:0] bitfield
of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR
register.
The alternate-bytes phase can send 1 bit at a time (over SO in single-SPI mode), 2 bits at a
time (over IO0/IO1 in dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI
mode). This can be configured using the ABMODE[1:0] bitfield of QUADSPI_CCR[15:14]
register.
When ABMODE = 00, the alternate-byte phase is skipped, and the command sequence
proceeds directly to the next phase, if any.
There may be times when only a single nibble needs to be sent during the alternate-byte
phase rather than a full byte, such as when the dual-mode is used and only two cycles are
used for the alternate bytes. In this case, the firmware can use quad-mode (ABMODE = 11)
and send a byte with bits 7 and 3 of ALTERNATE set to 1 (keeping the IO3 line high), and
bits 6 and 2 set to 0 (keeping the IO2 line low). In this case, the upper two bits of the nibble
to be sent are placed in bits 4:3 of ALTERNATE, while the lower two bits are placed in bits
1 and 0. For example, if the nibble 2 (0010) is to be sent over IO0/IO1, then ALTERNATE
must be set to 0x8A (1000_1010).

Dummy-cycle phase
In the dummy-cycle phase, 1-31 cycles are given without any data being sent or received,
in order to give time to the flash memory to prepare for the data phase when higher clock
frequencies are used. The number of cycles given during this phase is specified in
the DCYC[4:0] bitfield of QUADSPI_CCR[22:18] register. In both SDR and DDR modes, the
duration is specified as a number of full CLK cycles.
When DCYC is zero, the dummy-cycles phase is skipped, and the command sequence
proceeds directly to the data phase, if present.
The operating mode of the dummy-cycles phase is determined by DMODE.
In order to assure enough “turn-around” time for changing data signals from output mode to
input mode, there must be at least one dummy cycle when using dual or quad mode to
receive data from the flash memory.

Data phase
During the data phase, any number of bytes can be sent to, or received from the flash
memory.

882/3353 RM0433 Rev 8

RM0433 Quad-SPI interface (QUADSPI)

In indirect and automatic status-polling modes, the number of bytes to be sent/received is

specified in the QUADSPI_DLR register.
In indirect-write mode the data to be sent to the flash memory must be written to the
QUADSPI_DR register. In indirect-read mode the data received from the flash memory is
obtained by reading the QUADSPI_DR register.
In memory-mapped mode, the data which is read is sent back directly over the AXI to
the Cortex or to a DMA.
The data phase can send/receive 1 bit at a time (over SO/SI in single-SPI mode), 2 bits at a
time (over IO0/IO1 in dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI
mode). This can be configured using the ABMODE[1:0] bitfield of QUADSPI_CCR[15:14]
register.
When DMODE = 00, the data phase is skipped, and the command sequence finishes
immediately by raising NCS. This configuration must only be used in only indirect write
mode.

23.3.4 QUADSPI signal interface protocol modes

Single-SPI mode
This legacy SPI mode allows just one single bit to be sent/received serially. In this mode,
data are sent to the flash memory over the SO signal (whose I/O shared with IO0). Data
received from the flash memory arrive via SI (whose I/O shared with IO1).
The different phases can each be configured separately to use this mode by setting the
IMODE/ADMODE/ABMODE/DMODE fields (in QUADSPI_CCR) to 01.
In each phase which is configured in single-SPI mode:
• IO0 (SO) is in output mode.
• IO1 (SI) is in input mode (high impedance).
• IO2 is in output mode and forced to 0.
• IO3 is in output mode and forced to 1 (to deactivate the “hold” function).
This is the case even for the dummy phase if DMODE = 01.

Dual-SPI mode
In dual-SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.
The different phases can each be configured separately to use dual-SPI mode by setting the
IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 10.
In each phase which is configured in dual-SPI mode:
• IO0/IO1 are at high-impedance (input) during the data phase for read operations, and
outputs in all other cases.
• IO2 is in output mode and forced to 0.
• IO3 is in output mode and forced to 1.
In the dummy phase when DMODE = 01, IO0/IO1 are always high-impedance.

Quad-SPI mode
In quad-SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3
signals.

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The different phases can each be configured separately to use quad-SPI mode by setting
the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 11.
In each phase which is configured in this mode, IO0/IO1/IO2/IO3 are all are at
high-impedance (input) during the data phase for read operations, and outputs in all other
cases.
In the dummy phase when DMODE = 11, IO0/IO1/IO2/IO3 are all high-impedance.
IO2 and IO3 are used only in quad-SPI mode. If none of the phases are configured to use
quad-SPI mode, then the pins corresponding to IO2 and IO3 can be used for other functions
even while the QUADSPI is active.

SDR mode
By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in
single-data rate (SDR) mode.
In SDR mode, when the QUADSPI drives IO0/SO, IO1, IO2, IO3 signals, these signals
transition only with the falling edge of CLK.
When receiving data in SDR mode, the QUADSPI assumes that flash memories also send
the data using CLK falling edge. By default (when SSHIFT = 0), the signals are sampled
using the following (rising) edge of CLK.

DDR mode
When the DDRM bit (QUADSPI_CCR[31]) is set to 1, the QUADSPI operates in
double-data rate (DDR) mode.
In DDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals in the
address/alternate-byte/data phases, a bit is sent on each of CLK falling and rising edges.
The instruction phase is not affected by DDRM. The instruction is always sent using CLK
falling edge.
When receiving data in DDR mode, the QUADSPI assumes that flash memories also send
the data using both CLK rising and falling edges. When DDRM = 1, the firmware must clear
SSHIFT (bit 4 of QUADSPI_CR). Thus, the signals are sampled one half of a CLK cycle
later (on the following, opposite edge).

Figure 129. Example of a DDR command in quad-SPI mode

Instruction Address Alt. Dummy Data

NCS
SCLK
IO0 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 4 0 4 0

IO1 5 4 5 4 5 4 5 4 5 4 5 4

IO2 6 2 6 2 6 2 6 2 6 2 6 2

IO3 7 3 7 3 7 3 7 3 7 3 7 3
A23-16A15-8 A7-0 M7-0 Byte1Byte2

I/O switch from output to input

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Dual-flash mode
When the DFM bit (bit 6 of QUADSPI_CR) is 1, the QUADSPI is in dual-flash mode, where
two external quad-SPI flash memories (FLASH 1 and FLASH 2) are used in order to
send/receive 8 bits (or 16 bits in DDR mode) every cycle, effectively doubling the throughput
as well as the capacity.
Each of the flash memories uses the same CLK and optionally the same NCS signals, but
each have separate IO0, IO1, IO2, and IO3 signals.
The dual-flash mode can be used in conjunction with single-, dual-, and quad-SPI modes,
as well as with either SDR or DDR mode.
The flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), must reflect the
total flash memory capacity, which is double the size of one individual component.
If address X is even, then the byte which the QUADSPI gives for address X is the byte at the
address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the
byte at the address X/2 of FLASH 2. In other words, bytes at even addresses are all stored
in FLASH 1 and bytes at odd addresses are all stored in FLASH 2.
When reading the flash memories status registers in dual-flash mode, twice as many bytes
must be read compared to doing the same read in single-flash mode. This means that if
each flash memory gives 8 valid bits after the instruction for fetching the status register, then
the QUADSPI must be configured with a data length of 2 bytes (16 bits), and the QUADSPI
receives one byte from each flash memory. If each flash memory gives a status of 16 bits,
then the QUADSPI must be configured to read 4 bytes to get all the status bits of both flash
memories in dual-flash mode. The least-significant byte of the result (in the data register) is
the least-significant byte of FLASH 1 status register, while the next byte is the least-
significant byte of FLASH 2 status register. Then, the third byte of the data register is
FLASH 1 second byte, while the forth byte is FLASH 2 second byte (in the case that the
flash memories have 16-bit status registers).
An even number of bytes must always be accessed in dual-flash mode. For this reason,
bit 0 of the data length bitfield (QUADSPI_DLR[0]) is stuck at 1 when DFM = 1.
In dual-flash mode, the behavior of FLASH 1 interface signals are basically the same as in
normal mode. FLASH 2 interface signals have exactly the same waveforms as FLASH 1
during the instruction, address, alternate-byte, and dummy-cycles phases. In other words,
each flash memory always receives the same instruction and the same address. Then,
during the data phase, the BK1_IOx and BK2_IOx buses are both transferring data in
parallel, but the data that are sent to (or received from) FLASH 1 are distinct from those
of FLASH 2.

23.3.5 QUADSPI indirect mode

When in indirect mode, commands are started by writing to QUADSPI registers, and data
are transferred by writing or reading the data register, in the same way as for other
communication peripherals.
When FMODE = 00 (QUADSPI_CCR[27:26]), the QUADSPI is in indirect-write mode,
where bytes are sent to the flash memory during the data phase. Data are provided by
writing to the data register (QUADSPI_DR).
When FMODE = 01, the QUADSPI is in indirect-read mode, where bytes are received from
the flash memory during the data phase. Data are recovered by reading QUADSPI_DR.

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The number of bytes to be read/written is specified in the data length register

(QUADSPI_DLR). If QUADSPI_DLR = 0xFFFF_FFFF (all 1s), then the data length is
considered undefined and the QUADSPI simply continues to transfer data until the end of
flash memory (as defined by FSIZE) is reached. If no bytes are to be transferred, DMODE
(QUADSPI_CCR[25:24]) must be set to 00.
If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4-Gbyte
flash memory), then in this special case, transfers continue indefinitely, stopping only after
an abort request or after the QUADSPI is disabled. After the last memory address is read (at
address 0xFFFF_FFFF), reading continues with address = 0x0000_0000.
When the programmed number of bytes to be transmitted or received is reached, TCF is set
and an interrupt is generated if TCIE = 1. In the case of undefined number of data, the TCF
is set when the limit of the external SPI memory is reached according to the flash memory
size defined in QUADSPI_CR.

Triggering the start of a command

Essentially, a command starts as soon as firmware gives the last information that is
necessary for this command. Depending on the QUADSPI configuration, there are three
different ways to trigger the start of a command in indirect mode. The commands starts
immediately:
• after a write is performed to INSTRUCTION[7:0] (QUADSPI_CCR), if no address is
necessary (when ADMODE = 00) and if no data needs to be provided by the firmware
(when FMODE = 01 or DMODE = 00)
• after a write is performed to ADDRESS[31:0] (QUADSPI_AR), if an address is
necessary (when ADMODE ≠ 00) and if no data needs to be provided by the firmware
(when FMODE = 01 or DMODE = 00)
• after a write is performed to DATA[31:0] (QUADSPI_DR), if data needs to be provided
by the firmware (when FMODE = 00 and DMODE != 00)
Writes to the alternate byte register (QUADSPI_ABR) never trigger the communication start.
If alternate bytes are required, they must be programmed before.
As soon as a command is started, BUSY (bit 5 of QUADSPI_SR) is automatically set.

FIFO and data management

In indirect mode, data go through a 32-byte FIFO which is internal to the QUADSPI.
FLEVEL[5:0] (QUADSPI_SR[13:8]) indicates how many bytes are currently being held in
the FIFO.
In indirect-write mode (FMODE = 00), the firmware adds data to the FIFO when it writes
QUADSPI_DR. Word writes add 4 bytes to the FIFO, halfword writes add 2 bytes, and byte
writes add only 1 byte. If the firmware adds too many bytes to the FIFO (more than is
indicated by DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write
operation (when TCF is set).
Byte/halfword accesses to QUADSPI_DR must be done only to the least significant
byte/halfword of the 32-bit register.
FTHRES[4:0] is used to define a FIFO threshold. When the threshold is reached, FTF (FIFO
threshold flag) is set. In indirect-read mode, FTF is set when the number of valid bytes to be
read from the FIFO is above the threshold. FTF is also set if there are data in the FIFO after
the last byte is read from the flash memory, regardless of the FTHRES setting.

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In indirect-write mode, FTF is set when the number of empty bytes in the FIFO is above the
threshold.
If FTIE = 1, there is an interrupt when FTF is set. FTF is cleared by hardware as soon as the
threshold condition is no longer true (after enough data is transferred by the CPU or DMA).
In indirect-read mode when the FIFO becomes full, the QUADSPI temporarily stops reading
bytes from the flash memory to avoid an overrun. The reading of the flash memory does not
restart until 4 bytes become vacant in the FIFO (when FLEVEL ≤ 11). Thus, when
FTHRES ≥ 13, the application must take care to read enough bytes to assure that the
QUADSPI starts retrieving data from the flash memory again. Otherwise, the FTF flag stays
at 0 as long as 11 < FLEVEL < FTHRES.

23.3.6 QUADSPI automatic status-polling mode

In automatic status-polling mode, the QUADSPI periodically starts a command to read
a defined number of status bytes (up to 4). The received bytes can be masked to isolate
some status bits and an interrupt can be generated when the selected bits have
a defined value.
Accesses to the flash memory begin in the same way as in indirect-read mode: if no address
is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is written.
Otherwise, if an address is required, the first access begins when QUADSPI_AR is written.
BUSY goes high at this point and stays high even between the periodic accesses.
The contents of MASK[31:0] (QUADSPI_PSMAR) are used to mask the data from the flash
memory in automatic status-polling mode. If MASK[n] = 0, then bit n of the result is masked
and not considered. If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n]
(QUADSPI_PSMAR), then there is a match for bit n.
If the polling match mode bit (PMM, bit 23 of QUADSPI_CR) is 0, then “AND” match mode is
activated. This means status match flag (SMF) is set only when there is a match on all of the
unmasked bits.
If PMM = 1, then “OR” match mode is activated. This means SMF is set if there is a match
on any of the unmasked bits.
An interrupt is called when SMF is set if SMIE = 1.
If the automatic status-polling mode stop (APMS) bit is set, the operation stops and BUSY
goes to 0 as soon as a match is detected. Otherwise, BUSY stays at 1, and the periodic
accesses continue until there is an abort or the QUADSPI is disabled (EN = 0).
The data register (QUADSPI_DR) contains the latest received status bytes (the FIFO is
deactivated). The content of the data register is not affected by the masking used in the
matching logic. The FTF status bit is set as soon as a new reading of the status is complete,
and FTF is cleared as soon as the data is read.

23.3.7 QUADSPI memory-mapped mode

When configured in memory-mapped mode, the external SPI device is seen as an internal
memory.
It is forbidden to access the quad-SPI flash bank area before having properly configured
and enabled the QUADSPI peripheral.
No more than 256 Mbytes can addressed even if the flash memory capacity is larger.

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If an access is made to an address outside of the range defined by FSIZE but still within the
256-Mbyte range, then a bus error is given. The effect of this error depends on the bus
master that attempted the access:
• If it is the Cortex CPU, bus fault exception is generated when enabled (or an HardFault
exception when bus fault is disabled).
• If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is
automatically disabled.
Byte, halfword, and word access types are all supported.
Support for execute in place (XIP) operation is implemented, where the QUADSPI
anticipates the next access and load in advance the byte at the following address. If the
subsequent access is indeed made at a continuous address, the access is completed faster
since the value is already prefetched.
By default, the QUADSPI never stops its prefetch operation, keeping the previous read
operation active with NCS maintained low, even if no access to the flash memory occurs for
a long time. Since flash memories tend to consume more when NCS is held low,
the application may want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR)
so that NCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have
elapsed without any access since when the FIFO becomes full with prefetch data.
BUSY goes high as soon as the first memory-mapped access occurs. Because of the
prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the
peripheral is disabled.

23.3.8 QUADSPI free-running clock mode

When configured in free-running clock mode, the QUADSPI continuously outputs the clock
for test and calibration purposes.
The free-running clock mode is entered as soon as the FRCM bit is set in the
QUADSPI_CCR register. It is exited by setting the ABORT bit of the QUADSPI_CR.
When the QUADSPI operates in free-running clock mode:
• the clock is running continuously
• NCS stays high (external device deselected)
• data lines are released (High-Z)
• the BUSY flag of QUADSPI_SR is set

23.3.9 QUADSPI flash memory configuration

The device configuration register (QUADSPI_DCR) can be used to specify the
characteristics of the external SPI flash memory.
The FSIZE[4:0] bitfield defines the size of external memory using the following formula:
Number of bytes in flash memory = 2[FSIZE+1]
FSIZE+1 is effectively the number of address bits required to address the flash memory.
The flash memory capacity can be up to 4 Gbytes (addressed using 32 bits) in indirect
mode, but the addressable space in memory-mapped mode is limited to 256 Mbytes.
If DFM = 1, FSIZE indicates the total capacity of the two flash memories together.
When the QUADSPI executes two commands, one immediately after the other, it raises
NCS high between the two commands for only one CLK cycle by default. If the flash

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memory requires more time between commands, the CSHT bitfield can be used to specify
the minimum number of CLK cycles (up to 8) that NCS must remain high.
The clock mode (CKMODE) bit indicates the CLK signal logic level in between commands
(when NCS = 1).

23.3.10 QUADSPI delayed data sampling

By default, the QUADSPI samples the data driven by the flash memory one half of
a CLK cycle after the flash memory drives the signal.
In case of external signal delays, it may be beneficial to sample the data later.
Using SSHIFT (bit 4 of QUADSPI_CR), the sampling of the data can be shifted by half of
a CLK cycle.
Clock shifting is not supported in DDR mode: SSHIFT must be clear when DDRM bit is set.

23.3.11 QUADSPI configuration

The QUADSPI configuration is done in two phases:
1. QUADSPI peripheral configuration
2. QUADSPI flash memory configuration
Once configured and enabled, the QUADSPI can be used in one of its three operating
modes: indirect, automatic status-polling, or memory-mapped mode.

QUADSPI configuration
The QUADSPI is configured using QUADSPI_CR. The user must configure the clock
prescaler division factor and the sample shifting settings for the incoming data.
The DDR mode can be set through the DDRM bit. When setting the quad-SPI interface in
DDR mode, the internal divider of kernel clock must be set with a division ratio of two or
more. Once enabled, the address and the alternate bytes are sent on both clock edges, and
the data are sent/received on both clock edges. Regardless of the DDRM bit setting,
instructions are always sent in SDR mode.
The FIFO level for either MDMA trigger generation or interrupt generation is programmed in
the FTHRES bits.
If a timeout counter is needed, the TCEN bit can be set and the timeout value programmed
in the QUADSPI_LPTR register.
The dual-flash mode can be activated by setting DFM to 1.

QUADSPI flash memory configuration

The parameters related to the targeted external flash memory are configured through the
QUADSPI_DCR register.The user must program the flash memory size in the FSIZE bits,
the chip-select minimum high time in CSHT bits, and the functional mode (Mode 0 or
Mode 3) in the MODE bit.

23.3.12 QUADSPI use

The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]).

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Indirect mode
When FMODE is programmed to 00, the indirect-write mode is selected and data can be
sent to the flash memory. With FMODE = 01, the indirect-read mode is selected where data
can be read from the flash memory.
When the QUADSPI is used in indirect mode, the frames are constructed in the following
way:
1. Specify a number of data bytes to read or write in QUADSPI_DLR.
2. Specify the frame format, mode and instruction code in QUADSPI_CCR.
3. Specify optional alternate byte to be sent right after the address phase
in QUADSPI_ABR.
4. Specify the operating mode in QUADSPI_CR.
5. Specify the targeted address in QUADSPI_AR.
6. Read/write the data from/to the FIFO through QUADSPI_DR.
When writing QUADSPI_CR, the user specifies the following settings:
• enable bit (EN) set to 1
• timeout counter enable bit (TCEN)
• sample shift setting (SSHIFT)
• FIFO threshold level (FTRHES) to indicate when the FTF flag must be set
• interrupt enables
• automatic status-polling mode parameters: match mode and stop mode (valid when
FMODE = 11)
• clock prescaler
When writing QUADSPI_CCR, the user specifies the following parameters:
• instruction byte through INSTRUCTION bits
• the way the instruction has to be sent through the IMODE bits (1/2/4 lines)
• the way the address has to be sent through the ADMODE bits (None/1/2/4 lines)
• address size (8/16/24/32-bit) through ADSIZE bits
• the way the alternate bytes have to be sent through the ABMODE (None/1/2/4 lines)
• alternate bytes number (1/2/3/4) through the ABSIZE bits
• presence or not of dummy bytes through the DBMODE bit
• number of dummy bytes through the DCYC bits
• the way data have to be sent/received (none/1/2/4 lines) through DMODE bits
If neither QUADSPI_AR nor QUADSPI_DR need to be updated for a particular command,
then the command sequence starts as soon as QUADSPI_CCR is written. This is the case
when both ADMODE and DMODE are 00, or if just ADMODE = 00 when in indirect read
mode (FMODE = 01).
When an address is required (ADMODE is not 00) and the data register does not need to be
written (when FMODE = 01 or DMODE = 00), the command sequence starts as soon as the
address is updated with a write to QUADSPI_AR.
In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is
triggered by a write in the FIFO through QUADSPI_DR.

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Automatic status-polling mode

This mode is enabled setting the FMODE bitfield (QUADSPI_CCR[27:26]) to 10. In this
mode, the programmed frame is sent and the data retrieved periodically.
The maximum amount of data read in each frame is 4 bytes. If more data is requested in
QUADSPI_DLR, it is ignored and only 4 bytes are read.
The periodicity is specified in the QUADSPI_PISR register.
Once the status data is retrieved, it can internally be processed:
• to set the status match flag and generate an interrupt if enabled
• to stop automatically the periodic retrieving of the status bytes
The received value can be masked with the value stored in QUADSPI_PSMKR and ORed
or ANDed with the value stored in QUADSPI_PSMAR.
In case of match, the status match flag is set and an interrupt is generated if enabled, and
the QUADSPI can be automatically stopped if the AMPS bit is set.
In any case, the latest retrieved value is available in QUADSPI_DR.

Memory-mapped mode
In memory-mapped mode, the external flash memory is seen as an internal memory but
with some latency during accesses. Only read operations are allowed to the external flash
memory in this mode.
The memory-mapped mode is entered by setting FMODE to 11 in QUADSPI_CCR.
The programmed instruction and frame is sent when a master is accessing
the memory-mapped space.
The FIFO is used as a prefetch buffer to anticipate linear reads. Any access to
QUADSPI_DR in this mode returns zero.
QUADSPI_DLR has no meaning in memory-mapped mode.

23.3.13 Sending the instruction only once

Some flash memories (for example: Winbound) provide a mode where an instruction must
be sent only with the first command sequence, while subsequent commands start directly
with the address. One can take advantage of such a feature using the SIOO bit
(QUADSPI_CCR[28]).
SIOO is valid for all functional modes (indirect, automatic status-polling, and
memory-mapped). If the SIOO bit is set, the instruction is sent only for the first command
following a write to QUADSPI_CCR. Subsequent command sequences skip the instruction
phase, until there is a write to QUADSPI_CCR.
SIOO has no effect when IMODE = 00 (no instruction).

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23.3.14 QUADSPI error management

An error can be generated in the following case:
• In indirect mode or automatic status-polling mode when a wrong address is
programmed in QUADSPI_AR (according to the flash memory size defined by
FSIZE[4:0] in the QUADSPI_DCR), TEF is set and an interrupt is generated if enabled.
Also in indirect mode, if the address plus the data length exceeds the flash memory
size, TEF is set as soon as the access is triggered.
• In memory-mapped mode, when an out-of-range access is done by a master or when
the QUADSPI is disabled, a bus error is generated as a response to the faulty bus
master request.
When a master is accessing the memory mapped space while the memory-mapped
mode is disabled, a bus error is generated as a response to the faulty bus master
request.

23.3.15 QUADSPI busy bit and abort functionality

Once the QUADSPI starts an operation with the flash memory, the BUSY bit is automatically
set in QUADSPI_SR.
In indirect mode, BUSY is reset once the QUADSPI has completed the requested command
sequence, and the FIFO is empty.
In automatic status-polling mode, BUSY goes low only after the last periodic access is
complete, due to a match when APMS = 1, or due to an abort.
After the first access in memory-mapped mode, BUSY goes low only on a timeout event or
on an abort.
Any operation can be aborted by setting the ABORT bit in QUADSPI_CR. Once the abort is
completed, BUSY and ABORT are automatically reset, and the FIFO is flushed.
Note: Some flash memories may misbehave if a write operation to a status registers is aborted.

23.3.16 NCS behavior

By default, NCS is high, deselecting the external flash memory. NCS falls before an
operation begins and rises as soon as it finishes.
When CKMODE = 0 (“mode0”, where CLK stays low when no operation is in progress),
NCS falls one CLK cycle before an operation first rising CLK edge, and NCS rises one CLK
cycle after the operation final rising CLK edge, as shown in the figure below.

Figure 130. NCS when CKMODE = 0 (T = CLK period)

T T

NCS

SCLK

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When CKMODE=1 (“mode3”, where CLK goes high when no operation is in progress) and
DDRM=0 (SDR mode), NCS still falls one CLK cycle before an operation first rising CLK
edge, and NCS rises one CLK cycle after the operation final rising CLK edge, as shown in
the figure below.

Figure 131. NCS when CKMODE = 1 in SDR mode (T = CLK period)

T T

NCS

SCLK

MS35320V2

When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), NCS falls one CLK cycle
before an operation first rising CLK edge, and NCS rises one CLK cycle after the operation
final active rising CLK edge, as shown in the figure below. Because DDR operations must
finish with a falling edge, CLK is low when NCS rises, and CLK rises back up one half of a
CLK cycle afterwards.

Figure 132. NCS when CKMODE = 1 in DDR mode (T = CLK period)

T T T/2

NCS

SCLK

MS35321V2

When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation,
the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs
when an operation is stalled, NCS rises just after the abort is requested and then CLK rises
one half of a CLK cycle later, as shown in Figure 133.

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Figure 133. NCS when CKMODE = 1 with an abort (T = CLK period)

T Clock stalled T/2

NCS

SCLK

Abort

MS35322V2

When not in dual-flash mode (DFM = 0) and FSEL = 0 (default value), only FLASH 1 is
accessed. Thus BK2_NCS stays high, if FSEL = 1, only FLASH 2 is accessed and
BK1_NCS stays high. In dual-flash mode, BK2_NCS behaves exactly the same as
BK1_NCS. Thus, if there is a FLASH 2 and if the application is dual-flash mode only, then
BK1_NCS signal can be used for FLASH 2 as well, and the pin devoted to BK2_NCS can be
used for other functions.

23.4 QUADSPI interrupts

An interrupt can be produced on the following events:
• Timeout
• Status match
• FIFO threshold
• Transfer complete
• Transfer error
Separate interrupt enable bits are available for flexibility.

Table 199. QUADSPI interrupt requests

Interrupt event Event flag Enable control bit

Timeout TOF TOIE

Status match SMF SMIE
FIFO threshold FTF FTIE
Transfer complete TCF TCIE
Transfer error TEF TEIE

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23.5 QUADSPI registers

23.5.1 QUADSPI control register (QUADSPI_CR)

Address offset: 0x000
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESCALER[7:0] PMM APMS Res. TOIE SMIE FTIE TCIE TEIE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSHIF
Res. Res. Res. FTHRES[4:0] FSEL DFM Res. TCEN Res. ABORT EN
T
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 PRESCALER[7:0]: Clock prescaler

This bitfield defines the scaler factor for generating CLK based on the quadspi_ker_ck clock
(value+1).
0: FCLK = Fquadspi_ker_ck, quadspi_ker_ck clock used directly as QUADSPI CLK (prescaler
bypassed)
1: FCLK = Fquadspi_ker_ck/2
2: FCLK = Fquadspi_ker_ck/3
...
255: FCLK = Fquadspi_ker_ck/256
For odd clock division factors, CLK duty cycle is not 50%. The clock signal remains low one
cycle longer than it stays high.
When setting quad-SPI interface in DDR mode, the prescaler must be set with a division ratio
of two or more.
Note: This bitfield can be modified only when BUSY = 0.
Bit 23 PMM: Polling match mode
This bit indicates which method must be used for determining a “match” during automatic
status-polling mode.
0: AND match mode. SMF is set if all the unmasked bits received from the flash memory
match the corresponding bits in the match register.
1: OR match mode. SMF is set if any one of the unmasked bits received from the flash
memory matches its corresponding bit in the match register.
Note: This bit can be modified only when BUSY = 0.
Bit 22 APMS: Automatic status-polling mode stop
This bit determines if automatic status-polling is stopped after a match.
0: Automatic status-polling mode is stopped only by abort or by disabling the QUADSPI.
1: Automatic status-polling mode stops as soon as there is a match.
Note: This bit can be modified only when BUSY = 0.
Bit 21 Reserved, must be kept at reset value.
Bit 20 TOIE: Timeout interrupt enable
This bit enables the timeout interrupt.
0: Interrupt disabled
1: Interrupt enabled

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Bit 19 SMIE: Status match interrupt enable

This bit enables the status match interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 18 FTIE: FIFO threshold interrupt enable
This bit enables the FIFO threshold interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 17 TCIE: Transfer complete interrupt enable
This bit enables the transfer complete interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 16 TEIE: Transfer error interrupt enable
This bit enables the transfer error interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 FTHRES[4:0]: FIFO threshold level
This bitfield defines, in indirect mode, the threshold number of bytes in the FIFO that causes
the FIFO threshold flag (bit FTF in register QUADSPI_SR) to be set.
0: In indirect-write mode (FMODE = 00), FTF is set if there are one or more free bytes
location left in the FIF,O or indirect-read mode (FMODE = 01), FTF is set if there are one or
more valid bytes that can be read from the FIFO.
1: In indirect-write mode (FMODE = 00), FTF is set if there are two or more free bytes
location left in the FIFO, or indirect-read mode (FMODE = 01), FTF is set if there are two or
more valid bytes that can be read from the FIFO
...
31: In indirect-write mode (FMODE = 00), FTF is set if there are 32 free bytes location left in
the FIFO, or indirect-read mode (FMODE = 01), FTF is set if there are 32 valid bytes that can
be read from the FIFO.
Bit 7 FSEL: Flash memory selection
This bit selects the flash memory to be addressed in single-flash mode (when DFM = 0).
0: FLASH 1 selected
1: FLASH 2 selected
Note: This bit can be modified only when BUSY = 0. This bit is ignored when DFM = 1.
Bit 6 DFM: Dual-flash mode
This bit activates dual-flash mode, where two external flash memories are used
simultaneously to double throughput and capacity.
0: Dual-flash mode disabled
1: Dual-flash mode enabled
Note: This bit can be modified only when BUSY = 0.
Bit 5 Reserved, must be kept at reset value.

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RM0433 Quad-SPI interface (QUADSPI)

Bit 4 SSHIFT: Sample shift

By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the flash
memory. This bit allows the data to be sampled later in order to account for external signal
delays.
0: No shift
1: 1/2 cycle shift
The firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1).
Note: This bitfield can be modified only when BUSY = 0.
Bit 3 TCEN: Timeout counter enable
This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this
bit causes the NCS to be released (and thus reduces consumption) if there has not been an
access after a certain amount of time, where this time is defined by TIMEOUT[15:0]
(QUADSPI_LPTR). This bit enables the timeout counter.
By default, the QUADSPI never stops its prefetch operation, keeping the previous read
operation active with NCS maintained low, even if no access to the flash memory occurs for a
long time. Since flash memories tend to consume more when NCS is held low, the
application may want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so
that NCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have
elapsed without an access since when the FIFO becomes full with prefetch data.
0: Timeout counter is disabled, and thus the NCS remains active indefinitely after an access
in memory-mapped mode.
1: Timeout counter is enabled, and thus the NCS is released in memory-mapped mode after
TIMEOUT[15:0] cycles of flash memory inactivity.
Note: This bit can be modified only when BUSY = 0.
Bit 2 Reserved, must be kept at reset value.
Bit 1 ABORT: Abort request
This bit aborts the ongoing command sequence. It is automatically reset once the abort is
complete. This bit stops the current transfer.
In automatic status-polling or memory-mapped mode, this bit also reset APM or DM bit.
0: No abort requested
1: Abort requested
Bit 0 EN: QUADSPI enable
0: QUADSPI disabled
1: QUADSPI enabled

23.5.2 QUADSPI device configuration register (QUADSPI_DCR)

Address offset: 0x004
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FSIZE[4:0]
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKMO
Res. Res. Res. Res. Res. CSHT[2:0] Res. Res. Res. Res. Res. Res. Res.
DE
rw rw rw rw

Bits 31:21 Reserved, must be kept at reset value.

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Bits 20:16 FSIZE[4:0]: Flash memory size

This bitfield defines the size of external memory using the following formula:
Number of bytes in flash memory = 2[FSIZE+1]
FSIZE+1 is effectively the number of address bits required to address the flash memory.
The flash memory capacity can be up to 4 Gbytes (addressed using 32 bits) in indirect mode,
but the addressable space in memory-mapped mode is limited to 256 Mbytes.
If DFM = 1, FSIZE indicates the total capacity of the two flash memories together.
Note: This bitfield can be modified only when BUSY = 0.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:8 CSHT[2:0]: Chip select high time
CSHT+1 defines the minimum number of CLK cycles which the chip select (NCS) must
remain high between commands issued to the flash memory.
0: NCS stays high for at least 1 cycle between flash memory commands
1: NCS stays high for at least 2 cycles between flash memory commands
...
7: NCS stays high for at least 8 cycles between flash memory commands
Note: This bitfield can be modified only when BUSY = 0.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 CKMODE: Mode 0/mode 3
This bit indicates the level that CLK takes between commands (when NCS = 1).
0: CLK must stay low while NCS is high (chip select released). This is referred to as mode 0.
1: CLK must stay high while NCS is high (chip select released). This is referred to as mode 3.
Note: This bitfield can be modified only when BUSY = 0.

23.5.3 QUADSPI status register (QUADSPI_SR)

Address offset: 0x008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. FLEVEL[5:0] Res. Res. BUSY TOF SMF FTF TCF TEF
r r r r r r r r r r r r

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:8 FLEVEL[5:0]: FIFO level
This bitfield gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0
when the FIFO is empty, and 32 when it is full. In memory-mapped mode and in automatic
status-polling mode, FLEVEL is zero.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 BUSY: Busy
This bit is set when an operation is on going. This bit clears automatically when the operation
with the flash memory is finished and the FIFO is empty.
Bit 4 TOF: Timeout flag
This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.

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RM0433 Quad-SPI interface (QUADSPI)

Bit 3 SMF: Status match flag

This bit is set in automatic status-polling mode when the unmasked received data matches
the corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1 to
CSMF.
Bit 2 FTF: FIFO threshold flag
In indirect mode, this bit is set when the FIFO threshold is reached, or if there is any data left
in the FIFO after reads from the flash memory are complete. It is cleared automatically as
soon as threshold condition is no longer true.
In automatic status-polling mode this bit is set every time the status register is read, and the
bit is cleared when the data register is read.
Bit 1 TCF: Transfer complete flag
This bit is set in indirect mode when the programmed number of data is transferred or in any
mode when the transfer is aborted.It is cleared by writing 1 to CTCF.
Bit 0 TEF: Transfer error flag
This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It
is cleared by writing 1 to CTEF.

23.5.4 QUADSPI flag clear register (QUADSPI_FCR)

Address offset: 0x00C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTOF CSMF Res. CTCF CTEF
w w w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CTOF: Clear timeout flag
Writing 1 clears the TOF flag in QUADSPI_SR.
Bit 3 CSMF: Clear status match flag
Writing 1 clears the SMF flag in QUADSPI_SR.
Bit 2 Reserved, must be kept at reset value.
Bit 1 CTCF: Clear transfer complete flag
Writing 1 clears the TCF flag in QUADSPI_SR.
Bit 0 CTEF: Clear transfer error flag
Writing 1 clears the TEF flag in QUADSPI_SR.

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23.5.5 QUADSPI data length register (QUADSPI_DLR)

Address offset: 0x010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DL[31:0]: Data length

Number of data to be retrieved (value+1) in indirect and automatic status-polling modes.
A value no greater than 3 (indicating 4 bytes) must be used for automatic status-polling
mode.
All 1s in indirect mode means undefined length, where the QUADSPI continues until the end
of memory, as defined by FSIZE.
0x0000_0000: 1 byte is to be transferred
0x0000_0001: 2 bytes are to be transferred
0x0000_0002: 3 bytes are to be transferred
0x0000_0003: 4 bytes are to be transferred
...
0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred
0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred
0xFFFF_FFFF: undefined length -- all bytes until the end of flash memory (as defined by
FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F.
DL[0] is stuck at 1 in dual-flash mode (DFM = 1) even when 0 is written to this bit, thus
assuring that each access transfers an even number of bytes.
This bitfield has no effect when in memory-mapped mode (FMODE = 10).
Note: This bitfield can be written only when BUSY = 0.

23.5.6 QUADSPI communication configuration register (QUADSPI_CCR)

Address offset: 0x014
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DDRM DHHC FRCM SIOO FMODE[1:0] DMODE[1:0] Res. DCYC[4:0] ABSIZE[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABMODE[1:0] ADSIZE[1:0] ADMODE[1:0] IMODE[1:0] INSTRUCTION[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 DDRM: Double data rate mode

This bit sets the DDR mode for the address, alternate byte and data phase:
0: DDR mode disabled
1: DDR mode enabled
Note: This bit can be written only when BUSY = 0.

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RM0433 Quad-SPI interface (QUADSPI)

Bit 30 DHHC: DDR hold

This bit delays the data output by 1/4 of the QUADSPI output clock cycle in DDR mode:
0: Data output delayed using analog delay
1: Data output delayed by 1/4 of a QUADSPI output clock cycle
This feature is only active in DDR mode.
Note: This bit can be written only when BUSY = 0.
PRESCALER > 0 is mandatory when DHHC = 1.
Bit 29 FRCM: Free-running clock mode
When this bit is set, the QUADSPI enters free-running clock mode regardless of FMODE bits.
0: Normal mode
1: Free-running clock mode
Note: This bit can be written only when BUSY = 0.
Bit 28 SIOO: Send instruction only once mode
This bit has no effect when IMODE = 00.See Section 23.3.13 for more details.
0: Instruction sent on every transaction
1: Instruction sent only for the first command
Note: This bit can be written only when BUSY = 0.
Bits 27:26 FMODE[1:0]: Functional mode
This bitfield defines the QUADSPI functional mode of operation.
00: Indirect-write mode
01: Indirect-read mode
10: Automatic status-polling mode
11: Memory-mapped mode
Note: This bitfield can be written only when BUSY = 0.
Bits 25:24 DMODE[1:0]: Data mode
This bitfield defines the data phase mode of operation:
00: No data
01: Data on a single line
10: Data on two lines
11: Data on four lines
This bitfield also determines the dummy phase mode of operation.
Note: This bitfield can be written only when BUSY = 0.
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 DCYC[4:0]: Number of dummy cycles
This bitfield defines the duration of the dummy phase. In both SDR and DDR modes,
it specifies a number of CLK cycles (0-31).
Note: This bitfield can be written only when BUSY = 0.
Bits 17:16 ABSIZE[1:0]: Alternate-byte size
This bit defines the size of alternate bytes.
00: 8-bit alternate byte
01: 16-bit alternate bytes
10: 24-bit alternate bytes
11: 32-bit alternate bytes
Note: This bitfield can be written only when BUSY = 0.

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Bits 15:14 ABMODE[1:0]: Alternate byte mode

This bitfield defines the alternate-byte phase mode of operation.
00: No alternate bytes
01: Alternate bytes on a single line
10: Alternate bytes on two lines
11: Alternate bytes on four lines
Note: This bitfield can be written only when BUSY = 0.
Bits 13:12 ADSIZE[1:0]: Address size
This bit defines address size:
00: 8-bit address
01: 16-bit address
10: 24-bit address
11: 32-bit address
Note: This bitfield can be written only when BUSY = 0.
Bits 11:10 ADMODE[1:0]: Address mode
This bitfield defines the address phase mode of operation.
00: No address
01: Address on a single line
10: Address on two lines
11: Address on four lines
Note: This bitfield can be written only when BUSY = 0.
Bits 9:8 IMODE[1:0]: Instruction mode
This bitfield defines the instruction phase mode of operation.
00: No instruction
01: Instruction on a single line
10: Instruction on two lines
11: Instruction on four lines
Note: This bitfield can be written only when BUSY = 0.
Bits 7:0 INSTRUCTION[7:0]: Instruction
Instruction to be sent to the external SPI device.
Note: This bitfield can be written only when BUSY = 0.

23.5.7 QUADSPI address register (QUADSPI_AR)

Address offset: 0x018
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0433 Quad-SPI interface (QUADSPI)

Bits 31:0 ADDRESS[31:0]: Address

This bitfield contains the address to be sent to the external flash memory.
Writes to this bitfield are ignored when BUSY = 1 or when FMODE = 11 (memory-mapped
mode).
In dual flash mode, ADDRESS[0] is automatically stuck to 0 as the address must
always be even

23.5.8 QUADSPI alternate-byte register (QUADSPI_ABR)

Address offset: 0x01C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 ALTERNATE[31:0]: Alternate bytes

Optional data to be send to the external SPI device right after the address.
Note: This bitfield can be written only when BUSY = 0.

23.5.9 QUADSPI data register (QUADSPI_DR)

Address offset: 0x020
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:0 DATA[31:0]: Data

Data to be sent/received to/from the external SPI device.
In indirect write mode, data written to this register is stored on the FIFO before it is sent to the
flash memory during the data phase. If the FIFO is too full, a write operation is stalled until
the FIFO has enough space to accept the amount of data being written.
In indirect read mode, reading this register gives (via the FIFO) the data which was received
from the flash memory. If the FIFO does not have as many bytes as requested by the read
operation and if BUSY=1, the read operation is stalled until enough data is present or until
the transfer is complete, whichever happens first.
In automatic status-polling mode, this register contains the last data read from the flash
memory (without masking).
Word, halfword, and byte accesses to this register are supported. In indirect write mode, a
byte write adds 1 byte to the FIFO, a halfword write 2, and a word write 4. Similarly, in indirect
read mode, a byte read removes 1 byte from the FIFO, a halfword read 2, and a word read 4.
Accesses in indirect mode must be aligned to the bottom of this register: a byte read must
read DATA[7:0] and a halfword read must read DATA[15:0].

23.5.10 QUADSPI polling status mask register (QUADSPI_PSMKR)

Address offset: 0x024
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MASK[31:0]: Status mask

Mask to be applied to the status bytes received in automatic status-polling mode.
For bit n:
0: Bit n of the data received in automatic status-polling mode is masked and its value is not
considered in the matching logic
1: Bit n of the data received in automatic status-polling mode is unmasked and its value is
considered in the matching logic
Note: This bitfield can be written only when BUSY = 0.

23.5.11 QUADSPI polling status match register (QUADSPI_PSMAR)

Address offset: 0x028
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0433 Quad-SPI interface (QUADSPI)

Bits 31:0 MATCH[31:0]: Status match

Value to be compared with the masked status register to get a match.
Note: This bitfield can be written only when BUSY = 0.

23.5.12 QUADSPI polling interval register (QUADSPI_PIR)

Address offset: 0x02C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 INTERVAL[15:0]: Polling interval
Number of CLK cycles between two read during automatic status-polling phases.
Note: This bitfield can be written only when BUSY = 0.

23.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR)

Address offset: 0x030
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 TIMEOUT[15:0]: Timeout period
After each access in memory-mapped mode, the QUADSPI prefetches the subsequent bytes
and holds these bytes in the FIFO. This bitfield indicates how many CLK cycles the
QUADSPI waits after the FIFO becomes full until it raises NCS, putting the flash memory in a
lower-consumption state.
Note: This bitfield can be written only when BUSY = 0.

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23.5.14 QUADSPI register map

Table 200. QUADSPI register map and reset values

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

SSHIFT

ABORT
APMS

TCEN
FSEL
SMIE
PMM

TOIE

TCIE
TEIE

DFM
FTIE
Res.

Res.
Res.
Res.

Res.

Res.
QUADSPI_CR PRESCALER[7:0] FTHRES[4:0]

EN
0x000

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CKMODE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
QUADSPI_DCR FSIZE[4:0] CSHT
0x004

Reset value 0 0 0 0 0 0 0 0 0

SMF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
BUS
TOF

TCF
QUADSPI_SR FLEVEL[5:0]

TEF
FTF
0x008
Reset value 0 0 0 0 0 0 0 0 0 0 0 0

CSMF
CTOF

CTCF
CTEF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
QUADSPI_FCR
0x00C
Reset value 0 0 0 0
QUADSPI_DLR DL[31:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADMODE
ABMODE
DMODE
FMODE

ADSIZE
ABSIZE

IMODE
DDRM
DHHC
FRCM
SIOO

Res.
[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]
QUADSPI_CCR DCYC[4:0] INSTRUCTION[7:0]
0x014

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QUADSPI_AR ADDRESS[31:0]
0x018
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QUADSPI_ABR ALTERNATE[31:0]
0x01C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QUADSPI_DR DATA[31:0]
0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QUADSPI_
MASK[31:0]
0x024 PSMKR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QUADSPI_
MATCH[31:0]
0x028 PSMAR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

QUADSPI_PIR INTERVAL[15:0]
0x02C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QUADSPI_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

TIMEOUT[15:0]
0x030 LPTR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 for the register boundary addresses.

906/3353 RM0433 Rev 8

RM0433 Delay block (DLYB)

24 Delay block (DLYB)

24.1 Introduction
The delay block (DLYB) is used to generate an output clock that is dephased from the input
clock. The phase of the output clock must be programmed by the user application. The
output clock is then used to clock the data received by another peripheral such as an
SDMMC or Quad-SPI interface.
The delay is voltage- and temperature-dependent, that may require the application to re-
configure and recenter the output clock phase with the receive data.

24.2 DLYB main features

The delay block has the following features:
• Input clock frequency ranging from 25 MHz to the maximum frequency supported by
the communication interface (see datasheet)
• Up to 12 oversampling phases.

24.3 DLYB functional description

24.3.1 DLYB diagram

The delay block includes the following sub-blocks (shown in the figure below):
• register interface block providing AHB access to the DLYB registers
• delay line supporting the unit delays
• delay line length sampling
• output clock selection multiplexer

Figure 134. DLYB block diagram

32-bit AHB bus

dlyb_hclk
Delay block (DLYB)
REGISTER
INTERFACE
DELAY LINE
UNIT

dlyb_in_ck Unit Unit Unit Unit Unit

Delay Delay Delay Delay Delay DEN
0 1 2 3 11 SAMPLER

SEN
0
LENGTH

1
2
LNG
3

11
LNGF

0 1 2 3 4 12 SEL
MUX
CLOCK OUT MUX
dlyb_out_ck

MSv37830V2

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Delay block (DLYB) RM0433

24.3.2 DLYB pins and internal signals

Table 201 lists the DLYB internal signals.

Table 201. DLYB internal input/output signals

Signal name Signal type Description

dlyb_hclk Digital input Delay block register interface clock

dlyb_in_ck Digital input Delay block input clock
dlyb_out_ck Digital output Delay block output clock

24.3.3 General description

The delay block is enabled by setting the DEN bit in the DLYB control register (DLYB_CR).
The length sampler is enabled through the SEN bit in DLYB_CR register.
When the delay block is enabled, the delay added by a unit delay is defined by the
UNIT[6:0] field in the DLYB configuration register (DLYB_CFGR).
Note: UNIT[6:0] can be programmed only when the output clock is disabled (SEN = 1).
When the delay block is enabled, the output clock phase is selected through the SEL[3:0]
field in DLYB_CFGR register.
Note: SEL can be programmed only when the output clock is disabled (SEN = 1).
The output clock can be de-phased over one input clock period by configuring the delay line
length to span one period. The delay line length can be configured by enabling the length
sampler through the SEN bit, that gives access to the delay line length (LNG[11:0]) and
length valid flag (LNGF) in DLYB_CFGR.
If an output clock delay smaller than one input clock period is needed the delay line length
can be reduced. This allows a smaller unit delay providing higher resolution.
Once the delay line length is configured, a dephased output clock can be selected by the
output clock multiplexer. This is done through SEL[3:0]. The output clock is only available on
the selected phase when SEN is set to 0.
The table below gives a summary of the delay block control.

Table 202. Delay block control

DEN SEN UNIT SEL LNG LNGF Output clock

Don’t
0 0 Don’t care Don’t care Don’t care Enabled (= Input clock)
care
x 1 Unit delay Output clock phase Length Length flag Disabled
Don’t
1 0 Unit delay(1) Output clock phase(2) Don’t care Enabled (= selected phase)
care
1. The unit delay can only be changed when SEN = 1.
2. The output clock phase can only be changed when SEN = 1.

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RM0433 Delay block (DLYB)

24.3.4 Delay line length configuration procedure

LNG[11:0] is used to determine the delay line length with respect to the input clock period.
The length must be configured so that one full input clock period is covered by the delay line
length.
Note that despite the delay line has 12 unit delay elements, the following procedure
description returns a length between 0 and 10, as the upper delay output value is used to
ensure that the delay is calibrated over one full input clock cycle. Depending on the clock
frequency and UNIT value, unit delay element 10 may also be truncated from the clock
cycle length.
A clock input (free running clock) must be present during the whole tuning procedure.
To configure the delay line length to one period of the Input clock, follow the sequence
below:
1. Enable the delay block by setting DEN bit to 1.
2. Enable the length sampling by setting SEN bit to 1.
3. Enable all delay cells by setting SEL[3:0] to 12.
4. For UNIT[6:0] = 0 to 127 (this step must be repeated until the delay line length is
configured):
a) Update the UNIT[6:0] value and wait till the length flag LNGF is set to 1.
b) Read LNG[11:0].
If (LNG[10:0] > 0) and (LNG[11] or LNG[10] = 0), the delay line length is configured to
one input clock period.
5. Determine how many unit delays (N) span one input clock period: for N = 0 to 10, if
LNG[N] = 1, the number of unit delays spanning the input clock period = N.
6. Disable the length sampling by clearing SEN to 0.
If an output clock delay smaller than one input clock period is needed the delay line length
can be reduced smaller than one input clock period. This allows a smaller unit delay,
providing a higher resolution spanning a shorter time interval.

24.3.5 Output clock phase configuration procedure

When the delay line length is configured to one input clock period, the output clock phase
can be selected between the unit delays spanning one Input clock period.
Follow the steps below to select the output clock phase:
1. Disable the output clock and enable the access to the phase selection SEL[3:0] bits by
setting SEN bit to 1.
2. Program SEL[3:0] with the desired output clock phase value.
3. Enable the output clock on the selected phase by clearing SEN to 0.
SDMMC use case:
The delay block is used in conjunction with SDMMC interface variable delay. For correct
sampling point tuning the delay value must cover a whole SDMMC_CK clock period. After
having tuned the delay line length the individual delays are used in the sampling point tuning
to find the optimal sampling point.

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Delay block (DLYB) RM0433

24.4 DLYB registers

All registers can be accessed in word, half-word and byte access.

24.4.1 DLYB control register (DLYB_CR)

Address offset: 0x000
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SEN DEN
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 SEN: Sampler length enable bit
0: Sampler length and register access to UNIT[6:0] and SEL[3:0] disabled, output clock
enabled.
1: Sampler length and register access to UNIT[6:0] and SEL[3:0] enabled, output clock
disabled.
Bit 0 DEN: Delay block enable bit
0: DLYB disabled.
1: DLYB enabled.

24.4.2 DLYB configuration register (DLYB_CFGR)

Address offset: 0x004
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LNGF

Res. Res. Res. LNG[11:0]

r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. UNIT[6:0] Res. Res. Res. Res. SEL[3:0]
rw rw rw rw rw rw rw rw rw rw rw

Bit 31 LNGF: Length valid flag

This flag indicates when the delay line length value contained in LNG[11:0] is valid after
UNIT[6:0] bits changed.
0: Length value in LNG is not valid.
1: Length value in LNG is valid.
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 LNG[11:0]: Delay line length value
These bits reflect the 12 unit delay values sampled at the rising edge of the input clock.
The value is only valid when LNGF = 1.

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RM0433 Delay block (DLYB)

Bit 15 Reserved, must be kept at reset value.

Bits 14:8 UNIT[6:0]: Delay of a unit delay cell.
These bits can only be written when SEN = 1.
Unit delay = initial delay + UNIT[6:0] x delay step
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 SEL[3:0]: Phase for the output clock.
These bits can only be written when SEN = 1.
Output clock phase = input clock + SEL[3:0] x unit delay

24.4.3 DLYB register map

Table 203. DLYB register map and reset values

Register
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

DEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SEN
DLYB_CR
0x000
Reset value 0 0
LNGF
Res
Res
Res

Res

Res
Res
Res
Res
DLYB_CFGR LNG UNIT SEL
0x004
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 129 for the register boundary addresses.

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Analog-to-digital converters (ADC) RM0433

25 Analog-to-digital converters (ADC)

25.1 Introduction
This section describes the ADC implementation:
• ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master).
• ADC3 is instantiated separately.
Each ADC consists of a 16-bit successive approximation analog-to-digital converter.
Each ADC has up to 20 multiplexed channels. A/D conversion of the various channels can
be performed in single, continuous, scan or discontinuous mode. The result of the ADC is
stored in a left-aligned or right-aligned 32-bit data register.
The ADCs are mapped on the AHB bus to allow fast data handling.
The analog watchdog features allow the application to detect if the input voltage goes
outside the user-defined high or low thresholds.
A built-in hardware oversampler allows to improve analog performances while off-loading
the related computational burden from the CPU.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.

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RM0433 Analog-to-digital converters (ADC)

25.2 ADC main features

• High-performance features
– Up to 2x ADCs which can operate in dual mode
– 16, 14, 12, 10 or 8-bit configurable resolution
– ADC conversion time is independent from the AHB bus clock frequency
– Faster conversion time by lowering resolution
– Can manage Single-ended or differential inputs (programmable per channels)
– AHB slave bus interface to allow fast data handling
– Self-calibration (both offset and linearity)
– Channel-wise programmable sampling time
– Up to four injected channels (analog inputs assignment to regular or injected
channels is fully configurable)
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching
– Data alignment with in-built data coherency
– Data can be managed by GP-DMA for regular channel conversions with FIFO
– Data can be routed to DFSDM for post processing
– 4 dedicated data registers for the injected channels
• Oversampler
– 32-bit data register
– Oversampling ratio adjustable from 2 to 1024x
– Programmable data right and left shift
• Low-power features
– Speed adaptive low-power mode to reduce ADC consumption when operating at
low frequency
– Allows slow bus frequency application while keeping optimum ADC performance
– Provides automatic control to avoid ADC overrun in low AHB bus clock frequency
application (auto-delayed mode)
• Each ADC features an external analog input channel
– Up to 6 fast channels from dedicated GPIO pads
– Up to 14 slow channels from dedicated GPIO pads
• In addition, there are 5 internal dedicated channels
– Internal reference voltage (VREFINT)
– Internal temperature sensor (VSENSE)
– VBAT monitoring channel (VBAT/4)
– Connection to DAC internal channels
• Start-of-conversion can be initiated:
– by software for both regular and injected conversions
– by hardware triggers with configurable polarity (internal timers events or GPIO
input events) for both regular and injected conversions
• Conversion modes
– Each ADC can convert a single channel or can scan a sequence of channels

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– Single mode converts selected inputs once per trigger

– Continuous mode converts selected inputs continuously
– Discontinuous mode
• Dual ADC mode for ADC1 and 2
• Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular
or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or
3 or overrun events
• 3 analog watchdogs per ADC
• ADC input range: VREF– ≤ VIN ≤ VREF+
Figure 135 shows the block diagram of one ADC.

25.3 ADC implementation

Table 204. ADC features
ADC modes/features ADC1 ADC2 ADC3

Dual mode X (coupled together) -

DFSDM interface X X X
Extended sample time option (SMPPLUS control) - - -
LDO voltage regulator status X(1) X(1) X(1)
1. Available only on devices revision V.

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RM0433 Analog-to-digital converters (ADC)

25.4 ADC functional description

25.4.1 ADC block diagram

Figure 135 shows the ADC block diagram and Table 205 gives the ADC pin description.

Figure 135. ADC block diagram

Analog
supply VREF+
(VDDA)

ADRDY
EOSMP
adc_it
EOC
EOS
OVR
BOOST JEOC
DEEPPWD RDATA[31:0]

AHB
slave
JAUTO JEOS
JQOVF
JL[1:0], JSQx To internal digital circuit JDATA1[31:0] AWDx
L[3:0], SQx JDATA2[31:0]
ADVREGEN REG. JDATA3[31:0]
CONT JDATA4[31:0] AHB
DIFSEL[19:0] interface
AHB adc_dma
interface adc_dat
[15:0]
ADEN/ADDIS Bias & Ref
ADCAL
ADCALDIF Oversampler DMNGT[1:0] adc_ker_ck
VINPy Input DAMDF[1:0]
ADCx_INPy selection & VIN SAR ADC adc_hclk
VINNy scan control
ADCx_INNy CONVERTED ROVSM
analog input adc_sclk
channels DATA
SMPx[2:0] TROVS
sampling time
BOOST start
Start & Stop OVSS[3:0]
Control
OSVR[9:0]
AUTDLY LINCALRD OVRMOD
auto delayed S/W trigger YW6..1 overrun mode JOVSE
ADSTART CALFACT_D
[10:0] ALIGN
start conv left/right ROVSE
CALFACT_S
ADSTP RES[2:0],
stop conv [10:0]
16,14,12,10,8 bits RSHIFT4..1
LINCALFACT
[30:0] OFFSETy[25:0] LSHIFT[3:0]
Oversampling
adc_ext_trg0 OFFSETy_CH[4:0] options
adc_ext_trg1 h/w SSATE
trigger
....... DISCEN
EXTEN[1:0] DISCNU[:0]
trigger enable Discontinuous Analog watchdog 1,2,3
....... and edge selection
mode
AWD1 adc_awd1
EXTi mapped at AWD2 adc_awd2
product level EXTSEL[4:0] AWD3 adc_awd3
trigger selection
JADSTART
JADSTP
S/W trigger
AWD1EN
JAWD1EN
adc_jext_trg0 H/W AWD1SGL
adc_jext_trg1 trigger
JDISCEN AWD1CH[4:0]
JEXTEN[1:0] JDISCNUM[2:0] LTR1[25:0]
....... trigger enable JQDIS HTR1[25:0]
and edge selection
JQM
Injced Context AWD2CH[19:0]
.......
Queue Mode LTR2[25:0]
JEXTi mapped at HTR2[25:0]
product level AWD3CH[19:0]
JEXTSEL[4:0]
trigger selection LTR3[25:0]
HTR3[25:0]

VREF- MSv62479V2

1. adc_sclk is available only on devices revision V.

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Analog-to-digital converters (ADC) RM0433

25.4.2 ADC pins and internal signals

Table 205. ADC input/output pins

Name Signal type Description

Input, analog reference The higher/positive reference voltage for the

VREF+
positive ADC.
VDDA Input, analog supply Analog power supply equal VDDA
Input, analog reference The lower/negative reference voltage for the
VREF-
negative ADC.
VSSA Input, analog supply ground Ground for analog power supply equal to VSS
Up to 20 analog input channels (x = ADC
number= 1 to 3):
ADCx_INPy
– ADCx_INP[0:5] fast channels
– ADCx_INP[6:19] slow channels
External analog inputs
Up to 20 analog input channels (x = ADC
number= 1 to 3):
ADCx_INNy
– ADCx_INN[0:5] fast channels
– ADCx_INN[6:19] slow channels

Table 206. ADC internal input/output signals

Signal
Internal signal name Description
type

Positive input analog channels for each ADC, connected

Analog
VINP[y] either to ADCx_INPi external channels or to internal
inputs
channels.
Analog Negative input analog channels for each ADC, connected
VINN[y]
inputs either to VREF- or to ADCx_INNi external channels
Up to 21 external trigger inputs for the regular
conversions (can be connected to on-chip timers).
adc_ext_trgy Inputs
These inputs are shared between the ADC master and
the ADC slave.
Up to 21 external trigger inputs for the injected
conversions (can be connected to on-chip timers).
adc_jext_trgy Inputs
These inputs are shared between the ADC master and
the ADC slave.
adc_awd1
Internal analog watchdog output signal connected to on-
adc_awd2 Outputs
chip timers. (x = Analog watchdog number 1,2,3)
adc_awd3
adc_it Output ADC interrupt
adc_hclk Input AHB clock
adc_sclk Input ADC synchronous clock input from RCC
adc_ker_ck_input Input ADC kernel clock input from RCC
adc_dma Output ADC DMA requests
adc_dat[15:0] Outputs ADC data outputs

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RM0433 Analog-to-digital converters (ADC)

Table 207. ADC interconnection

Signal name Source/destination

VSENSE (output voltage from internal temperature

ADC3 VINP[18]
sensor)
VREFINT (output voltage from internal reference
ADC3 VINP[19]
voltage)
ADC3 VINP[17] VBAT/4 (external battery voltage supply voltage)
ADC2 VINP[16] dac1_out1
ADC2 VINP[17] dac1_out2
adc_dat[15:0] dfsdm_dat_adc[15:0]

25.4.3 ADC clocks

Dual clock domain architecture (revision V devices)
The dual clock-domain architecture means that the ADC clock is independent from the AHB
bus clock.
The input clock is the same for all ADCs and can be selected between two different clock
sources (see Figure 136: ADC Clock scheme):
1. The ADC clock can be a specific clock source, named adc_ker_ck_input which is
independent and asynchronous with the AHB clock.
It can be configured in the RCC (refer to RCC Section for more information on how to
generate the ADC clock (adc_ker_ck_input) dedicated clock).
To select this scheme, CKMODE[1:0] bits of the ADCx_CCR register must be reset.
2. The ADC clock can be derived from the system clock or system clock divided by two
(adc_sclk). In this mode, a programmable divider factor can be selected (/1, 2 or 4
according to bits CKMODE[1:0]).
To select this scheme, CKMODE[1:0] bits of the ADCx_CCR register must be different
from “00”. adc_sclk is equal to sys_ck when HPRE is set to 0, otherwise it corresponds
to sys_ck/2.
In both case, the clock divider factor of 2 is applied to the clock provided to the ADC analog
block (fadc_ker_ck).
Option 1) has the advantage of reaching the maximum ADC clock frequency whatever the
AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio:
1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits
PRESC[3:0] in the ADCx_CCR register.
Option 2) has the advantage of using the system without additional PLL. In addition, when
adc_sclk is twice faster than the adc_hclk clock, the latency between the trigger and the
start of conversion is fixed. This can be useful when the ADC is triggered by a timer and if
the application requires that the ADC is precisely triggered without any uncertainty
(otherwise, an uncertainty of the trigger instant is added by the resynchronizations between
the two clock domains).
The clock configured through CKMODE[1:0] bits must be compliant with the analog ADC
operating frequency specified in the product datasheet.

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Note: adc_sclk is the system clock or system clock divided by two: when the AHB prescaler is set
to 1 (HPRE[3:0] = 0XXX in RCC_CFGR register), adc_sclk is equal to sys_ck, otherwise
adc_sclk corresponds to sys_ck/2.

Figure 136. ADC Clock scheme

RCC ADC1, ADC2 or ADC3

(Reset and
clock adc_hclk
controller) AHB interface

Bits CKMODE[1:0]
of ADCx_CCR

Fadc_ker_ck x 2
Analog ADC1 or ADC3

Fadc_ker_ck
(master)
adc_sclk /1 or /2 or /4 Others
adc_ker_ck_ /2 Analog ADC2
input /1, 2, 4, 6, 8, 10, (slave)
12, 16, 32, 64, 00
128, 256

Bits PREC[3:0] Bits CKMODE[1:0]

of ADCx_CCR of ADCx_CCR

MSv62429V3

1. Refer to the RCC section to see how adc_hclk and adc_ker_ck_input can be generated.

Dual clock domain architecture (revision Y devices)

The dual clock-domain architecture means that the ADC clock is independent from the AHB
bus clock.
The input clock is the same for the all ADCs and can be selected between two different
clock sources (see Figure 137: ADC clock scheme):
1. The ADC clock can be a specific clock source, named adc_ker_ck_input which is
independent and asynchronous with the AHB clock.
It can be configured in the RCC (refer to RCC Section for more information on how to
generate the ADC clock (adc_ker_ck_input) dedicated clock).
To select this scheme, CKMODE[1:0] bits of the ADCx_CCR register must be reset.
2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by
a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be
selected (/1, 2 or 4 according to bits CKMODE[1:0]).
To select this scheme, CKMODE[1:0] bits of the ADCx_CCR register must be different
from “00”.
Note: For option 2), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB
prescaler is set to 1 (HPRE[3:0] = 0XXX in RCC_CFGR register, corresponding to a clock
duty cycle of 50 %).
Option 1) has the advantage of reaching the maximum ADC clock frequency whatever the
AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio:
1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits
PRESC[3:0] in the ADCx_CCR register.

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RM0433 Analog-to-digital converters (ADC)

Option 2) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).
The clock configured through CKMODE[1:0] bits must be compliant with the operating
frequency specified in the product datasheet.

Figure 137. ADC clock scheme

RCC ADC1, ADC2 or ADC3

(Reset and
clock adc_hclk
controller) AHB interface

Bits CKMODE[1:0]
of ADCx_CCR
Analog ADC1 or ADC3
(master)
/1 or /2 or /4 Others
Analog ADC2
adc_ker_ck_ (slave)
/1, 2, 4, 6, 8, 10, Fadc_ker_ck
input 00
12, 16, 32, 64,
128, 256

Bits PREC[3:0] Bits CKMODE[1:0]

of ADCx_CCR of ADCx_CCR

MSv62428V1

1. Refer to the RCC section to see how adc_hclk and adc_ker_ck_input can be generated.

Clock ratio constraint between ADC clock and AHB clock

There are generally no constraints to be respected for the ratio between the ADC clock and
the AHB clock except if some injected channels are programmed. In this case, it is
mandatory to respect the following ratio:
• Fadc_hclk ≥ Fadc_ker_ck / 4 if the resolution of all channels are 16-bit, 14-bit,12-bit or 10-
bit
• Fadc_hclk ≥ Fadc_ker_ck / 3 if there are some channels with resolutions equal to 8-bit (and
none with lower resolutions)

Constraints between ADC clocks

When several ADC interfaces are used simultaneously, it is mandatory to use the same
clock source from the RCC block without prescaler ratio, for all ADC interfaces.

BOOST control
The ADC Boost mode can be controlled through the BOOST bit in the ADC_CR register.
This bit must be set according to the ADC clock setting. Refer to the ADC_CR register
description.

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Analog-to-digital converters (ADC) RM0433

25.4.4 ADC1/2/3 connectivity

ADC1 and ADC2 are tightly coupled and share some external channels as described in the
following figures.
ADC3 is instantiated separately, but some inputs are shared with ADC1 and ADC2.

Figure 138. ADC1 connectivity

ADC1
Channel selection
ADC12_INP0, VINP[0]
ADC12_INN1 VINN[0] Fast channel
VSSA
VINP[1]
ADC12_INP1
VINN[1] Fast channel
VINP[2]
ADC1_INP2
VINN[2] Fast channel
VINP[3]
ADC12_INP3
VINN[3] Fast channel
VINP[4]
ADC12_INP4
VINN[4] Fast channel
VINP[5]
ADC12_INP5
VINN[5] Fast channel
ADC1_INP6, VINP[6]
ADC1_INN2 VINN[6] Slow channel
VSSA
ADC12_INP7, VINP[7] VREF+
ADC12_INN3 VINN[7] Slow channel
VSSA
ADC12_INP8, VINP[8] VINP
ADC12_INN4 VINN[8] Slow channel
VSSA SAR
ADC12_INP9, VINP[9]
ADC1
ADC12_INN5 VINN[9] Slow channel VINN
VSSA
VINP[10]
ADC123_INP10
VINN[10] Slow channel
ADC123_INP11, VINP[11] VREF-
ADC123_INN10 VINN[11] Slow channel
ADC123_INP12, VINP[12]
ADC123_INN11 VINN[12] Slow channel
ADC12_INP13, VINP[13]
ADC12_INN12 VINN[13] Slow channel
VSSA
VINP[14]
ADC12_INP14
VINN[14] Slow channel
VSSA
VINP[15]
ADC12_INP15
VINN[15] Slow channel
VSSA
VINP[16]
ADC1_INP16
VINN[16] Slow channel
ADC1_INP17, VINP[17]
ADC1_INN16 VINN[17] Slow channel
VSSA
VINP[18]
ADC12_INP18
VINN[18] Slow channel
ADC12_INP19, VINP[19]
ADC12_INN18 VINN[19] Slow channel
VSSA

MSv41018V3

1. ADCx_INNy signal can only be used when the corresponding ADC input channel is configured as
differential mode.

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RM0433 Analog-to-digital converters (ADC)

Figure 139. ADC2 connectivity

ADC2
Channel selection
ADC12_INP0, VINP[0]
ADC12_INN1 VINN[0] Fast channel
VSSA
VINP[1]
ADC12_INP1
VINN[1] Fast channel
VINP[2]
ADC2_INP2
VINN[2] Fast channel
VINP[3]
ADC12_INP3
VINN[3] Fast channel
VINP[4]
ADC12_INP4
VINN[4] Fast channel
VINP[5]
ADC12_INP5
VINN[5] Fast channel
ADC2_INP6, VINP[6]
ADC2_INN2 VINN[6] Slow channel
VSSA
ADC12_INP7, VINP[7] VREF+
ADC12_INN3 VINN[7] Slow channel
VSSA
ADC12_INP8, VINP[8] VINP
ADC12_INN4 VINN[8] Slow channel
VSSA SAR
ADC12_INP9, VINP[9]
ADC2
ADC12_INN5 VINN[9] Slow channel VINN
VSSA
VINP[10]
ADC123_INP10
VINN[10] Slow channel
ADC123_INP11, VINP[11] VREF-
ADC123_INN10 VINN[11] Slow channel
ADC123_INP12, VINP[12]
ADC123_INN11 VINN[12] Slow channel
ADC12_INP13, VINP[13]
ADC12_INN12 VINN[13] Slow channel
VSSA
VINP[14]
ADC12_INP14
VINN[14] Slow channel
VSSA
VINP[15]
ADC12_INP15
VINN[15] Slow channel
VSSA
VINP[16]
dac_out1
VINN[16] Slow channel
VSSA
VINP[17]
dac_out2
VINN[17] Slow channel
VSSA
VINP[18]
ADC12_INP18
VINN[18] Slow channel
ADC12_INP19, VINP[19]
ADC12_INN18 VINN[19] Slow channel
VSSA

MSv41019V4

1. ADCx_INNy signal can only be used when the corresponding ADC input channel is configured as
differential mode.

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Analog-to-digital converters (ADC) RM0433

Figure 140. ADC3 connectivity

ADC3
Channel selection
ADC3_INP0, VINP[0]
ADC3_INN1 VINN[0] Fast channel
VSSA
VINP[1]
ADC3_INP1
VINN[1] Fast channel
VINP[2]
ADC3_INP2
VINN[2] Fast channel
VINP[3]
ADC3_INP3
VINN[3] Fast channel
VINP[4]
ADC3_INP4
VINN[4] Fast channel
VINP[5]
ADC3_INP5
VINN[5] Fast channel
ADC3_INP6, VINP[6]
ADC3_INN2 VINN[6] Slow channel
VSSA
ADC3_INP7, VINP[7] VREF+
ADC3_INN3 VINN[7] Slow channel
VSSA
ADC3_INP8, VINP[8] VINP
ADC3_INN4 VINN[8] Slow channel
VSSA SAR
ADC3_INP9, VINP[9]
ADC3
ADC3_INN5 VINN[9] Slow channel VINN
VSSA
VINP[10]
ADC123_INP10
VINN[10] Slow channel
ADC123_INP11, VINP[11] VREF-
ADC123_INN10 VINN[11] Slow channel
ADC123_INP12, VINP[12]
ADC123_INN11 VINN[12] Slow channel
VSSA
VINP[13]
ADC3_INP13
VINN[13] Slow channel
ADC3_INP14, VINP[14]
ADC3_INN13 VINN[14] Slow channel
ADC3_INP15, VINP[15]
ADC3_INN14 VINN[15] Slow channel
ADC3_INP16, VINP[16]
ADC3_INN15 VINN[16] Slow channel
VSSA
VINP[17]
VBAT/4
VINN[17] Slow channel
VSSA
VINP[18]
VSENSE
VINN[18] Slow channel
VSSA
VINP[19]
VREFINT
VINN[19] Slow channel
VSSA

MSv41020V4

1. ADCx_INNy signal can only be used when the corresponding ADC input channel is configured as
differential mode.

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RM0433 Analog-to-digital converters (ADC)

25.4.5 Slave AHB interface

The ADCs implement an AHB slave port for control/status register and data access. The
features of the AHB interface are listed below:
• Word (32-bit) accesses
• Single cycle response
• Response to all read/write accesses to the registers with zero wait states.
The AHB slave interface does not support split/retry requests, and never generates AHB
errors.

25.4.6 ADC deep-power-down mode (DEEPPWD) and ADC voltage regulator

(ADVREGEN)
By default, the ADC is in deep-power-down mode where its supply is internally switched off
to reduce the leakage currents (the reset state of bit DEEPPWD is 1 in the ADC_CR
register).
To start ADC operations, it is first needed to exit deep-power-down mode by clearing bit
DEEPPWD=0.
Then, it is mandatory to enable the ADC internal voltage regulator by setting the bit
ADVREGEN=1 into ADC_CR register. The software must wait for the startup time of the
ADC voltage regulator (TADCVREG_STUP) before launching a calibration or enabling the
ADC. This delay must be implemented by software.
The LDO status can be verified by checking the LDORDY bit in ADC_ISR register (refer to
Section 25.3: ADC implementation for the availability of the LDO regulator status).
For the startup time of the ADC voltage regulator, refer to device datasheet for
TADCVREG_STUP parameter.
After ADC operations are complete, the ADC can be disabled (ADEN=0). It is possible to
save power by also disabling the ADC voltage regulator. This is done by writing bit
ADVREGEN=0.
Then, to save more power by reducing the leakage currents, it is also possible to re-enter in
ADC deep-power-down mode by setting bit DEEPPWD=1 into ADC_CR register. This is
particularly interesting before entering Stop mode.
Note: Writing DEEPPWD=1 automatically disables the ADC voltage regulator and bit ADVREGEN
is automatically cleared.
Note: When the internal voltage regulator is disabled (ADVREGEN=0), the internal analog
calibration is kept.
In ADC deep-power-down mode (DEEPPWD=1), the internal analog calibration is lost and it
is necessary to either relaunch a calibration or apply again the calibration factor which was
previously saved (refer to Section 25.4.8: Calibration (ADCAL, ADCALDIF, ADCALLIN,
ADC_CALFACT)).

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25.4.7 Single-ended and differential input channels

Channels can be configured to be either single-ended input or differential input by writing
into bits DIFSEL[19:0] in the ADC_DIFSEL register. This configuration must be written while
the ADC is disabled (ADEN=0).
In single-ended input mode, the analog voltage to be converted for channel “i” is the
difference between the external voltage VINP[i] (positive input) and VREF- (negative input).
In differential input mode, the analog voltage to be converted for channel “i” is the difference
between the external voltage VINP[i] (positive input) and VINN[i] (negative input).
The output data for the differential mode is an unsigned data. When VINP[i] equals VREF-,
VINN[i] equals VREF+ and the output data is 0x0000 (16-bit resolution mode). When VINP[i]
equals VREF+, VINN[i] equals VREF- and the output data is 0xFFFF.

ADC_Full_Scale V INP – V INN

Converted value = -------------------------------------------- × 1 + ------------------------------------
2 V REF+

When ADC is configured as differential mode, both input should be biased at VREF+ / 2
voltage.
The input signal are supposed to be differential (common mode voltage should be fixed).
For a complete description of how the input channels are connected for each ADC, refer to
Section 25.4.4: ADC1/2/3 connectivity.
Caution: When configuring the channel “i” in differential input mode, its negative input voltage is
connected to VINN[i]. As a consequence, channel “i+n”, which is connected to VINN[i], should
not be converted at same time by different ADCs. Some channels are shared between
ADC1/ADC2: this can make the channel on the other ADC unusable.

25.4.8 Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT)

Each ADC provides an automatic calibration procedure which drives all the calibration
sequence including the power-on/off sequence of the ADC. During the procedure, the ADC
calculates a calibration factor which is 11-bits of offset or 160-bits of linearity and which is
applied internally to the ADC until the next ADC power-off. During the calibration procedure,
the application must not use the ADC and must wait until calibration is complete.
The calibration is preliminary to any ADC operation. It removes the systematic errors which
may vary from chip to chip and allows to compensate offset and linearity deviation.
The calibration factor for the offset to be applied for single-ended input conversions is
different from the factor to be applied for differential input conversions:
• Write ADCALDIF=0 before launching a calibration which will be applied for single-
ended input conversions.
• Write ADCALDIF=1 before launching a calibration which will be applied for differential
input conversions.

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RM0433 Analog-to-digital converters (ADC)

The linearity correction must be done once only, regardless of single / differential
configuration.
• Write ADCALLIN=1 before launching a calibration which will run the linearity calibration
same time as the offset calibration.
• Write ADCALLIN=0 before launching a calibration which will not run the linearity
calibration but only the offset calibration.
The calibration is then initiated by software by setting bit ADCAL=1. It can be initiated only
when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the calibration
sequence. It is then cleared by hardware as soon the calibration completes. At this time, the
associated calibration factor is stored internally in the analog ADC and also in the bits
CALFACT_S[10:0] or CALFACT_D[10:0] of ADC_CALFACT register (depending on single-
ended or differential input calibration). The 160-bit linearity calibration factor can be
accessed using the ADC_CALFACT2 register with ADEN set to 1.
The internal analog calibration is kept if the ADC is disabled (ADEN=0). However, if the ADC
is disabled for extended periods, it is recommended that a new offset calibration cycle is run
before enabling again the ADC.
The internal analog calibration is lost each time the power of the ADC is removed (example,
when the product enters in STANDBY or VBAT mode). In this case, to avoid spending time
recalibrating the ADC, it is possible to re-write the calibration factor into the ADC_CALFACT
and ADC_CALFACT2 register without recalibrating, supposing that the software has
previously saved the calibration factor delivered during the previous calibration.
The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and
ADSTART=0 and JADSTART=0). Then, at the next start of conversion, the calibration factor
will automatically be injected into the analog ADC. This loading is transparent and does not
add any cycle latency to the start of the conversion. It is recommended to recalibrate when
VREF+ voltage changed more than 10%.
Refer to the datasheets for the clock cycle requirement for both linear and offset calibration.

Software procedure to calibrate the ADC

1. Ensure DEEPPWD=0, ADVREGEN=1 and verify that the ADC voltage regulator
startup time has elapsed by checking the LDORDY bit in ADC_ISR (refer to
Section 25.3: ADC implementation for the availability of the LDO regulator status).
2. Ensure that ADEN=0.
3. Select the input mode for this calibration by setting ADCALDIF=0 (Single-ended input)
or ADCALDIF=1 (Differential input). Select if Linearity calibration enable or not by
ADCALLIN=1(enabled) or ADCALLIN=0(disabled).
4. Set ADCAL=1.
5. Wait until ADCAL=0.
6. The offset calibration factor can be read from ADC_CALFACT register.
7. The linearity calibration factor can be read from ADC_CALFACT2 register, following the
procedure described in Section : Linearity calibration reading procedure (ADEN must
be set to 1 prior to accessing ADC_CALFACT2 register).

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Analog-to-digital converters (ADC) RM0433

Figure 141. ADC calibration

ADCALDIF 0: Single-ended input 1: Differential input

ADCALLIN 0: Linear calibrarion disable 1: Linear calibration enable

tCAB
ADCAL

ADC State OFF Startup Calibrate OFF

CALFACT_x[10:0] 0x000 Calibration factor

LINCALFACT Calibration factor
0x00000000000000000000
[159:0]

by S/W by H/W Indicative timings

MSv41021V1

Software procedure to re-inject a calibration factor into the ADC

1. Ensure ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no
conversion is ongoing).
2. Write CALFACT_S and CALFACT_D with the new offset calibration factors.
3. Write LINCALFACT bits with the new linearity calibration factors, following the
procedure described in Section : Linearity calibration writing procedure.
4. When a conversion is launched, the calibration factor will be injected into the analog
ADC only if the internal analog calibration factor differs from the one stored in bits
CALFACT_S for single-ended input channel or bits CALFACT_D for differential input
channel.

Figure 142. Updating the ADC offset calibration factor

ADC state Ready (not converting) Converting channel Ready Converting channel
(Single ended) (Single ended)
Updating calibration
Internal
calibration factor[10:0] F1 F2

Start conversion
(hardware or sofware)
WRITE
ADC_CALFACT

CALFACT_S[10:0] F2

by s/w by h/w
MSv41022V1

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RM0433 Analog-to-digital converters (ADC)

Calibrating single-ended and differential analog inputs with a single ADC

If the ADC is supposed to convert both differential and single-ended inputs, two calibrations
must be performed, one with ADCALDIF=0 and one with ADCALDIF=1. The procedure is
the following:
1. Disable the ADC.
2. Calibrate the ADC in single-ended input mode (with ADCALDIF=0) and Linearity
calibration enable (with ADCALLIN=1). This updates the registers CALFACT_S[10:0]
and LINCALFACT[159:0].
3. Calibrate the ADC in Differential input modes (with ADCALDIF=1) and Linearity
calibration disable (with ADCALLIN=0). This updates the register CALFACT_D[10:0].
4. Enable the ADC, configure the channels and launch the conversions. Each time there
is a switch from a single-ended to a differential inputs channel (and vice-versa), the
calibration will automatically be injected into the analog ADC.

Figure 143. Mixing single-ended and differential channels

Trigger event

ADC state RDY CONV CH 1 RDY CONV CH2 RDY CONV CH3 RDY CONV CH4
Single ended (Differential (Differential (Single inputs
inputs channel) inputs channel) inputs channel) channel)
Internal calibration
factor[10:0] F2 F3 F2

CALFACT_S[10:0] F2

CALFACT_D[10:0] F3

MSv41023V1

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Linearity calibration reading procedure

Once the calibration is done (ADCAL bit cleared by hardware) with ADCALLIN=1, the 160-
bit linearity correction factor can be read using the ADC_CALFACT2 30-bit registers (6 read
accesses are necessary).
The six LINCALRDYW1..6 control/status bits in ADC_CR are set when the calibration is
complete. When ADEN is set to 1, clearing one of these bits launches the transfer of part of
the linearity factor into the LINCALFACT[29:0] of the ADC_CALFACT2 register. The bit will
be reset by hardware when the ADC_CALFACT2 register can be read (software must poll
the bit until it is cleared). The complete procedure is as following:
1. Ensure DEEPPWD=0, ADVREGEN=1 and that the ADC voltage regulator startup time
has elapsed by checking the LDORDY bit in ADC_ISR (refer to Section 25.3: ADC
implementation for the availability of the LDO regulator status).
2. Set ADEN = 1 and wait until ADRDY=1.
3. Clear LINCALRDYW6 bit (Linearity calibration ready Word 6).
4. Poll LINCALRDYW6 bit until returned value is zero, indicating linearity correction
bits[159:150] are available in ADC_CALFACT2[29:0].
5. Read ADC_CALFACT2[29:0].
6. Clear LINCALRDYW5 bit.
7. Poll LINCALRDYW5 bit until returned value is zero, indicating linearity correction
bits[149:120] are available in ADC_CALFACT2[29:0].
8. Read ADC_CALFACT2[29:0].
9. Clear LINCALRDYW4 bit.
10. Poll LINCALRDYW4 bit until returned value is zero, indicating linearity correction
bits[119:90] are available in ADC_CALFACT2[29:0].
11. Read ADC_CALFACT2[29:0].
12. Clear LINCALRDYW3 bit.
13. Poll LINCALRDYW3 bit until returned value is zero, indicating linearity correction
bits[89:60] are available in ADC_CALFACT2[29:0].
14. Read ADC_CALFACT2[29:0].
15. Clear LINCALRDYW2 bit.
16. Poll LINCALRDYW2 bit until returned value is zero, indicating linearity correction
bits[59:30] are available in ADC_CALFACT2[29:0].
17. Read ADC_CALFACT2[29:0].
18. Clear LINCALRDYW1 bit.
19. Poll LINCALRDYW1 bit until returned value is zero, indicating linearity correction
bits[29:0] are available in ADC_CALFACT2[29:0].
20. Read ADC_CALFACT2[29:0].
Note: The software is allowed to toggle a single LINCALRDYWx bit at once (other bits left
unchanged), otherwise causing unexpected behavior.
The software can access the linearity calibration factor by writing LINCALRDYW1..6 bits
only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion
is ongoing).

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RM0433 Analog-to-digital converters (ADC)

Linearity calibration writing procedure

The six LINCALRDYW1..6 control/status bits in ADC_CR are reset when the calibration has
not yet been done or a new linearity calibration factor have been rewritten. It is possible to
force directly a linearity calibration factor or re-inject it using the following procedure:
1. Ensure DEEPPWD=0, ADVREGEN=1 and that ADC voltage regulator startup time has
elapsed by checking the LDORDY bit in ADC_ISR (refer to Section 25.3: ADC
implementation for the availability of the LDO regulator status).
2. Set ADEN = 1 and wait until ADRDY=1.
3. Write ADC_CALFACT2[9:0] with previously saved linearity correction factor
bits[159:150].
4. Set LINCALRDYW6 bit.
5. Poll LINCALRDYW6 bit until returned value is one, indicating linearity correction
bits[159:150] have been effectively written.
6. Write ADC_CALFACT2[29:0] with previously saved linearity correction factor
bits[149:120].
7. Set LINCALRDYW5 bit.
8. Poll LINCALRDYW5 bit until returned value is one, indicating linearity correction
bits[149:120] have been effectively written.
9. Write ADC_CALFACT2[29:0] with previously saved linearity correction factor
bits[119:90].
10. Set LINCALRDYW4 bit.
11. Poll LINCALRDYW4 bit until returned value is one, indicating linearity correction
bits[119:90] have been effectively written.
12. Write ADC_CALFACT2[29:0] with previously saved linearity correction factor
bits[89:60].
13. Set LINCALRDYW3 bit.
14. Poll LINCALRDYW3 bit until returned value is one, indicating linearity correction
bits[89:60] have been effectively written.
15. Write ADC_CALFACT2[29:0] with previously saved linearity correction factor
bits[59:30].
16. Set LINCALRDYW2 bit.
17. Poll LINCALRDYW2 bit until returned value is one, indicating linearity correction
bits[59:30] have been effectively written.
18. Write ADC_CALFACT2[29:0] with previously saved linearity correction factor bits[29:0].
19. Set LINCALRDYW1 bit.
20. Poll LINCALRDYW1 bit until returned value is one, indicating linearity correction
bits[29:0] have been effectively written.
Note: The software is allowed to toggle a single LINCALRDYWx bit at once (other bits left
unchanged), otherwise causing unexpected behavior.
The software is allowed to update the linearity calibration factor by writing
LINCALRDYW1..6 bits only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC
enabled and no conversion is ongoing).

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25.4.9 ADC on-off control (ADEN, ADDIS, ADRDY)

First of all, follow the procedure explained in Section 25.4.6: ADC deep-power-down mode
(DEEPPWD) and ADC voltage regulator (ADVREGEN)).
Once DEEPPWD = 0 and ADVREGEN = 1, the ADC can be enabled and the ADC needs a
stabilization time of tSTAB before it starts converting accurately, as shown in Figure 144. Two
control bits enable or disable the ADC:
• ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for
operation.
• ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by
hardware as soon as the analog ADC is effectively disabled.
Regular conversion can then start either by setting ADSTART=1 (refer to Section 25.4.19:
Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN))
or when an external trigger event occurs, if triggers are enabled.
Injected conversions start by setting JADSTART=1 or when an external injected trigger
event occurs, if injected triggers are enabled.

Software procedure to enable the ADC

1. Clear the ADRDY bit in the ADC_ISR register by writing ‘1’.
2. Set ADEN=1.
3. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done
using the associated interrupt (setting ADRDYIE=1).
4. Clear the ADRDY bit in the ADC_ISR register by writing ‘1’ (optional).

Software procedure to disable the ADC

1. Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is
ongoing. If required, stop any regular and injected conversion ongoing by setting
ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0.
2. Set ADDIS=1.
3. If required by the application, wait until ADEN=0, until the analog ADC is effectively
disabled (ADDIS will automatically be reset once ADEN=0).

Figure 144. Enabling / Disabling the ADC

ADEN
tSTAB

ADRDY

ADDIS

ADC REQ
state OFF Startup RDY Converting CH RDY OFF
-OF

by S/W by H/W
MSv30264V2

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RM0433 Analog-to-digital converters (ADC)

25.4.10 Constraints when writing the ADC control bits

The software can write the RCC control bits to configure and enable the ADC clock (refer to
RCC Section), the control bits DIFSEL in the ADC_DIFSEL register, ADCx_CCR register
and the control bits ADCAL and ADEN in the ADC_CR register, only if the ADC is disabled
(ADEN must be equal to 0).
The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of
the ADC_CR register only if the ADC is enabled and there is no pending request to disable
the ADC (ADEN must be equal to 1 and ADDIS to 0).
For all the other control bits of the ADC_CFGR, ADC_SMPRy, ADC_TRy, ADC_SQRy,
ADC_JDRy, ADC_OFRy and ADC_IER registers:
• For control bits related to configuration of regular conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion
ongoing (ADSTART must be equal to 0).
• For control bits related to configuration of injected conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no injected
conversion ongoing (JADSTART must be equal to 0).
The software can write ADSTP or JADSTP control bits in the ADC_CR register only if the
ADC is enabled and eventually converting and if there is no pending request to disable the
ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0).
The software can write the register ADC_JSQR at any time, when the ADC is enabled
(ADEN=1).
The software is allowed to write the ADC_JSQR register only when JADSTART is cleared to
0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in
ADC_CFGR register).
Note: There is no hardware protection to prevent these forbidden write accesses and ADC
behavior may become in an unknown state. To recover from this situation, the ADC must be
disabled (clear ADEN=0 as well as all the bits of ADC_CR register).

25.4.11 Channel selection (SQRx, JSQRx)

There are up to 20 multiplexed channels per ADC:
• 6 fast analog inputs coming from Analog PADs and GPIO pads (ADCx_INP/INN[0..5])
• Up to 14 slow analog inputs coming from GPIO pads (ADCx_INP/INN[6..19]).
• The ADCs are connected to 5 internal analog inputs:
– the internal temperature sensor (VSENSE)
– the internal reference voltage (VREFINT)
– the VBAT monitoring channel (VBAT/4)
– DAC internal channels
Refer to Table ADC interconnection in Section 25.4.2: ADC pins and internal signals for the
connection of the above internal analog inputs to external ADC pins or internal signals.
It is possible to organize the conversions in two groups: regular and injected. A group
consists of a sequence of conversions that can be done on any channel and in any order.
For instance, it is possible to implement the conversion sequence in the following order:

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Analog-to-digital converters (ADC) RM0433

ADCx_INP/INN3, ADCx_INP/INN8, ADCx_INP/INN2, ADCx_INP/INN2, ADCx_INP/INN0,

ADCx_INP/INN2, ADCx_INP/INN2, ADCx_INP/INN15.
• A regular group is composed of up to 16 conversions. The regular channels and their
order in the conversion sequence must be selected in the ADC_SQRy registers. The
total number of conversions in the regular group must be written in the L[3:0] bits in the
ADC_SQR1 register.
• An injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADC_JSQR register.
The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADC_JSQR register.
ADC_SQRy registers must not be modified while regular conversions can occur. For this,
the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to
Section 25.4.18: Stopping an ongoing conversion (ADSTP, JADSTP)).
The software is allowed to modify on-the-fly the ADC_JSQR register when JADSTART is set
to 1 only when the context queue is enabled (JQDIS=0 in ADC_CFGR register).

Temperature sensor, VREFINT and VBAT internal channels

The internal reference voltage (VREFINT), the temperature sensor (VSENSE), and the VBAT
channel are connected to ADC internal channels. Refer to Table ADC interconnection in
Section 25.4.2: ADC pins and internal signals for details.
Note: To convert one of the internal analog channels, enable the corresponding analog sources by
programming VREFEN, TSEN and VBATEN bits in the ADCx_CCR registers.

25.4.12 Channel preselection register (ADC_PCSEL)

For each channel selected through SQRx or JSQRx, the corresponding ADC_PCSEL bit
must be previously configured.
This ADC_PCSEL bit controls the analog switch integrated in the I/O level. The ADC input
MUX selects the ADC input according to the SQRx and JSQRx with very high speed, the
analog switch integrated in the IO cannot react as fast as ADC mux does. To avoid the delay
on analog switch control on IO, it is necessary to pre select the input channels which will be
selected in the SQRx, JSQRx.
The selection is based on the VINP[i] of each ADC input. If ADC1 converts the
ADC123_INP2(VINP[2]) as differential mode, ADC123_INP6(VINP[6]) also needs to be
selected in ADC_PCSEL.
Some I/Os are connected to several VINP[i] of the ADCx. The control inputs of the analog
switch are ORed with the corresponding ADC_PCSEL register bits.

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25.4.13 Channel-wise programmable sampling time (SMPR1, SMPR2)

Before starting a conversion, the ADC must establish a direct connection between the
voltage source under measurement and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the embedded
capacitor to the input voltage level.
Each channel can be sampled with a different sampling time which is programmable using
the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. It is therefore possible to
select among the following sampling time values:
• SMP = 000: 1.5 ADC clock cycles
• SMP = 001: 2.5 ADC clock cycles
• SMP = 010: 8.5 ADC clock cycles
• SMP = 011: 16.5 ADC clock cycles
• SMP = 100: 32.5 ADC clock cycles
• SMP = 101: 64.5 ADC clock cycles
• SMP = 110: 387.5 ADC clock cycles
• SMP = 111: 810.5 ADC clock cycles
The total conversion time is calculated as follows:
TCONV = Sampling time + 7.5 ADC clock cycles
Example:
With Fadc_ker_ck = 24 MHz and a sampling time of 1.5 ADC clock cycles (14-bit mode):
TCONV = (1.5 + 7.5) ADC clock cycles = 9 ADC clock cycles = 0.375 µs (14 bit mode for
fast channels)
The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for
regular conversion).

Constraints on the sampling time for fast and slow channels

For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time
as specified in the ADC characteristics section of the datasheets.

I/O analog switch voltage booster

The resistance of the I/O analog switches increases when the VDDA voltage is too low. The
sampling time must consequently be adapted accordingly (refer to the device datasheet for
the corresponding electrical characteristics). This resistance can be minimized at low VDDA
voltage by enabling an internal voltage booster through the BOOSTE bit of the
SYSCFG_PMCR register.

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25.4.14 Single conversion mode (CONT=0)

In Single conversion mode, the ADC performs once all the conversions of the channels.
This mode is started with the CONT bit at 0 by either:
• Setting the ADSTART bit in the ADC_CR register (for a regular channel, with software
trigger selected)
• Setting the JADSTART bit in the ADC_CR register (for an injected channel, with
software trigger selected)
• External hardware trigger event (for a regular or injected channel)
ADSTART bit or JADSTART bit must be set before triggering an external event.
Inside the regular sequence, after each conversion is complete:
• The converted data are stored into the 32-bit ADC_DR register
• The EOC (end of regular conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
Inside the injected sequence, after each conversion is complete:
• The converted data are stored into one of the four 32-bit ADC_JDRy registers
• The JEOC (end of injected conversion) flag is set
• An interrupt is generated if the JEOCIE bit is set
After the regular sequence is complete:
• The EOS (end of regular sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
After the injected sequence is complete:
• The JEOS (end of injected sequence) flag is set
• An interrupt is generated if the JEOSIE bit is set
Then the ADC stops until a new external regular or injected trigger occurs or until bit
ADSTART or JADSTART is set again.
Note: To convert a single channel, program a sequence with a length of 1.

25.4.15 Continuous conversion mode (CONT=1)

This mode applies to regular channels only.
In continuous conversion mode, when a software or hardware regular trigger event occurs,
the ADC performs once all the regular conversions of the channels and then automatically
re-starts and continuously converts each conversions of the sequence. This mode is started
with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the
ADC_CR register.
Inside the regular sequence, after each conversion is complete:
• The converted data are stored into the 32-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set

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Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note: To convert a single channel, program a sequence with a length of 1.
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both DISCEN=1 and CONT=1.
Injected channels cannot be converted continuously. The only exception is when an injected
channel is configured to be converted automatically after regular channels in continuous
mode (using JAUTO bit), refer to Auto-injection mode section).

25.4.16 Starting conversions (ADSTART, JADSTART)

Software starts ADC regular conversions by setting ADSTART=1.
When ADSTART is set, the conversion starts:
• Immediately: if EXTEN = 0x0 (software trigger)
• At the next active edge of the selected regular hardware trigger: if EXTEN /= 0x0
Software starts ADC injected conversions by setting JADSTART=1.
When JADSTART is set, the conversion starts:
• Immediately, if JEXTEN = 0x0 (software trigger)
• At the next active edge of the selected injected hardware trigger: if JEXTEN /= 0x0
Note: In auto-injection mode (JAUTO=1), use ADSTART bit to start the regular conversions
followed by the auto-injected conversions (JADSTART must be kept cleared).
ADSTART and JADSTART also provide information on whether any ADC operation is
currently ongoing. It is possible to re-configure the ADC while ADSTART=0 and
JADSTART=0 are both true, indicating that the ADC is idle.
ADSTART is cleared by hardware:
• In single mode with software trigger (CONT=0, EXTEN=0x0)
– at any end of conversion sequence (EOS =1)
• In discontinuous mode with software trigger (CONT=0, DISCEN=1, EXTEN=0x0)
– at end of conversion (EOC=1)
• In all other cases (CONT=x, EXTEN=x)
– after execution of the ADSTP procedure asserted by the software.
Note: In continuous mode (CONT=1), ADSTART is not cleared by hardware with the assertion of
EOS because the sequence is automatically relaunched.
When a hardware trigger is selected in single mode (CONT=0 and EXTEN /=0x00),
ADSTART is not cleared by hardware with the assertion of EOS to help the software which
does not need to reset ADSTART again for the next hardware trigger event. This ensures
that no further hardware triggers are missed.
JADSTART is cleared by hardware:
• in single mode with software injected trigger (JEXTEN=0x0)
– at any end of injected conversion sequence (JEOS assertion) or at any end of
sub-group processing if JDISCEN=1
• in all cases (JEXTEN=x)
– after execution of the JADSTP procedure asserted by the software.

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Note: When the software trigger is selected, ADSTART bit should not be set if the EOC flag is still
high.

25.4.17 Timing
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:

TCONV= TSMPL + TSAR = [1.5 |min + 7.5 |14bit] x Tadc_ker_ck

TCONV = TSMPL + TSAR = 62.5 ns |min + 312.5 ns |14bit = 375.0 ns (for Fadc_ker_ck = 24 MHz)

Figure 145. Analog to digital conversion time

ADC state RDY Sampling Ch(N) Converting Ch(N) Sampling Ch(N+1)

Analog channel Ch(N) Ch(N+1)

Internal S/H Sample AIN(N) Hold AIN(N) Sample AIN(N+1)

tSMPL(1) tSAR(2)
Set by
ADSTART SW
Set by Cleared
EOSMP SW by SW
Set by Cleared
SW by SW
EOC

ADC_DR Data N-1 Data N

Indicative timings
MS30532V1

1. TSMPL depends on SMP[2:0]

2. TSAR depends on RES[2:0]

25.4.18 Stopping an ongoing conversion (ADSTP, JADSTP)

The software can decide to stop regular conversions ongoing by setting ADSTP=1 and
injected conversions ongoing by setting JADSTP=1.
Stopping conversions will reset the ongoing ADC operation. Then the ADC can be
reconfigured (ex: changing the channel selection or the trigger) ready for a new operation.
Note that it is possible to stop injected conversions while regular conversions are still
operating and vice-versa. This allows, for instance, re-configuration of the injected
conversion sequence and triggers while regular conversions are still operating (and vice-
versa).
When the ADSTP bit is set by software, any ongoing regular conversion is aborted with
partial result discarded (ADC_DR register is not updated with the current conversion).
When the JADSTP bit is set by software, any ongoing injected conversion is aborted with
partial result discarded (ADC_JDRy register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that relaunching the ADC would re-
start a new sequence).

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Once this procedure is complete, bits ADSTP/ADSTART (in case of regular conversion), or
JADSTP/JADSTART (in case of injected conversion) are cleared by hardware and the
software must poll ADSTART (or JADSTART) until the bit is reset before assuming the ADC
is completely stopped.
Note: In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (JADSTP must not be used).

Figure 146. Stopping ongoing regular conversions

Trigger Trigger

ADC state Sample Convert Sample

RDY RDY C RDY
Ch(N-1) Ch(N-1) Ch(N)

JADSTART

Cleared Cleared
ADSTART by SW REGULAR CONVERSIONS ongoing by HW
(software is not allowed to configure regular conversions selection and triggers)

Cleared Cleared
ADSTP by SW by HW

ADC_DR Data N-2 Data N-1

MS30533V1

Figure 147. Stopping ongoing regular and injected conversions

Regular trigger Injected trigger Regular trigger

Sample Convert Sample

ADC state RDY
Ch(N-1) Ch(N-1)
RDY
Ch(M)
C RDY Sampl RDY

Set by Cleared
JADSTART SW INJECTED CONVERSIONS ongoing by HW
(software is not allowed to configure injected conversions selection and triggers)
Set by Cleared
JADSTP SW by HW

ADC_JDR DATA M-1

Set by Cleared
ADSTART SW REGULAR CONVERSIONS ongoing by HW
(software is not allowed to configure regular conversions selection and triggers)
Set by Cleared
ADSTP SW by HW

ADC_DR DATA N-2 DATA N-1

MS30534V1

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25.4.19 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,

JEXTSEL, JEXTEN)
A conversion or a sequence of conversions can be triggered either by software or by an
external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular
conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then
external events are able to trigger a conversion with the selected polarity.
When the Injected Queue is enabled (bit JQDIS=0), injected software triggers are not
possible.
The regular trigger selection is effective once software has set bit ADSTART=1 and the
injected trigger selection is effective once software has set bit JADSTART=1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
• If bit ADSTART=0, any regular hardware triggers which occur are ignored.
• If bit JADSTART=0, any injected hardware triggers which occur are ignored.
Table 208 provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values
and the trigger polarity.

Table 208. Configuring the trigger polarity for regular external triggers
EXTEN[1:0] Source

00 Hardware Trigger detection disabled, software trigger detection enabled

01 Hardware Trigger with detection on the rising edge
10 Hardware Trigger with detection on the falling edge
11 Hardware Trigger with detection on both the rising and falling edges

Note: The polarity of the regular trigger cannot be changed on-the-fly.

Table 209. Configuring the trigger polarity for injected external triggers
JEXTEN[1:0] Source

– If JQDIS=1 (Queue disabled): Hardware trigger detection disabled, software

00 trigger detection enabled
– If JQDIS=0 (Queue enabled), Hardware and software trigger detection disabled
01 Hardware Trigger with detection on the rising edge
10 Hardware Trigger with detection on the falling edge
11 Hardware Trigger with detection on both the rising and falling edges

Note: The polarity of the injected trigger can be anticipated and changed on-the-fly when the
queue is enabled (JQDIS=0). Refer to Section 25.4.22: Queue of context for injected
conversions.
The EXTSEL[4:0] and JEXTSEL[4:0] control bits select which out of 21 possible events can
trigger conversion for the regular and injected groups.
A regular group conversion can be interrupted by an injected trigger.

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Note: The regular trigger selection cannot be changed on-the-fly.

The injected trigger selection can be anticipated and changed on-the-fly. Refer to
Section 25.4.22: Queue of context for injected conversions on page 944
Each ADC master shares the same input triggers with its ADC slave as described in
Figure 148.

Figure 148. Triggers are shared between ADC master and ADC slave

ADC MASTER
adc_ext0_trg
EXTi mapped at
adc_ext1_trg External regular trigger
product level ....... .......
adc_ext31_trg

EXTSEL[4:0]

External injected trigger

JEXTSEL[4:0]

ADC SLAVE

External regular trigger

EXTSEL[4:0]
adc_jext0_trg
JEXTi mapped at adc_jext1_trg
External injected trigger
product level ....... .......
adc_jext31_trg
JEXTSEL[4:0]
MSv41035V2

Table 210 and Table 211 give all the possible external triggers of the three ADCs for regular
and injected conversion.

Table 210. ADC1, ADC2 and ADC3 - External triggers for regular channels
Name Source Type EXTSEL[4:0]

adc_ext_trg0 tim1_oc1 Internal signal from on-chip timers 00000

adc_ext_trg1 tim1_oc2 Internal signal from on-chip timers 00001
adc_ext_trg2 tim1_oc3 Internal signal from on-chip timers 00010
adc_ext_trg3 tim2_oc2 Internal signal from on-chip timers 00011
adc_ext_trg4 tim3_trgo Internal signal from on-chip timers 00100
adc_ext_trg5 tim4_oc4 Internal signal from on-chip timers 00101
adc_ext_trg6 exti11 External pin 00110
adc_ext_trg7 tim8_trgo Internal signal from on-chip timers 00111
adc_ext_trg8 tim8_trgo2 Internal signal from on-chip timers 01000
adc_ext_trg9 tim1_trgo Internal signal from on-chip timers 01001

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Table 210. ADC1, ADC2 and ADC3 - External triggers for regular channels (continued)
Name Source Type EXTSEL[4:0]

adc_ext_trg10 tim1_trgo2 Internal signal from on-chip timers 01010

adc_ext_trg11 tim2_trgo Internal signal from on-chip timers 01011
adc_ext_trg12 tim4_trgo Internal signal from on-chip timers 01100
adc_ext_trg13 tim6_trgo Internal signal from on-chip timers 01101
adc_ext_trg14 tim15_trgo Internal signal from on-chip timers 01110
adc_ext_trg15 tim3_oc4 Internal signal from on-chip timers 01111
adc_ext_trg16 hrtim1_adctrg1 Internal signal from on-chip timers 10000
adc_ext_trg17 hrtim1_adctrg3 Internal signal from on-chip timers 10001
adc_ext_trg18 lptim1_out Internal signal from on-chip timers 10010
adc_ext_trg19 lptim2_out Internal signal from on-chip timers 10011
adc_ext_trg20 lptim3_out Internal signal from on-chip timers 10100
adc_ext_trg21 Reserved - 10101
adc_ext_trg22 Reserved - 10110
adc_ext_trg23 Reserved - 10111
adc_ext_trg24 Reserved - 11000
adc_ext_trg25 Reserved - 11001
adc_ext_trg26 Reserved - 11010
adc_ext_trg27 Reserved - 11011
adc_ext_trg28 Reserved - 11100
adc_ext_trg29 Reserved - 11101
adc_ext_trg30 Reserved - 11110
adc_ext_trg31 Reserved - 11111

Table 211. ADC1, ADC2 and ADC3 - External triggers for injected channels
Name Source Type JEXTSEL[4:0]

adc_jext_trg0 tim1_trgo Internal signal from on-chip timers 00000

adc_jext_trg1 tim1_oc4 Internal signal from on-chip timers 00001
adc_jext_trg2 tim2_trgo Internal signal from on-chip timers 00010
adc_jext_trg3 tim2_oc1 Internal signal from on-chip timers 00011
adc_jext_trg4 tim3_oc4 Internal signal from on-chip timers 00100
adc_jext_trg5 tim4_trgo Internal signal from on-chip timers 00101
adc_jext_trg6 exti15 External pin 00110
adc_jext_trg7 tim8_oc4 Internal signal from on-chip timers 00111
adc_jext_trg8 tim1_trgo2 Internal signal from on-chip timers 01000
adc_jext_trg9 tim8_trgo Internal signal from on-chip timers 01001

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Table 211. ADC1, ADC2 and ADC3 - External triggers for injected channels (continued)
Name Source Type JEXTSEL[4:0]

adc_jext_trg10 tim8_trgo2 Internal signal from on-chip timers 01010

adc_jext_trg11 tim3_oc3 Internal signal from on-chip timers 01011
adc_jext_trg12 tim3_trgo Internal signal from on-chip timers 01100
adc_jext_trg13 tim3_oc1 Internal signal from on-chip timers 01101
adc_jext_trg14 tim6_trgo Internal signal from on-chip timers 01110
adc_jext_trg15 tim15_trgo Internal signal from on-chip timers 01111
adc_jext_trg16 hrtim1_adctrg2 Internal signal from on-chip timers 10000
adc_jext_trg17 hrtim1_adctrg4 Internal signal from on-chip timers 10001
adc_jext_trg18 lptim1_out Internal signal from on-chip timers 10010
adc_jext_trg19 lptim2_out Internal signal from on-chip timers 10011
adc_jext_trg20 lptim3_out Internal signal from on-chip timers 10100
adc_jext_trg21 Reserved - 10101
adc_jext_trg22 Reserved - 10110
adc_jext_trg23 Reserved - 10111
adc_jext_trg24 Reserved - 11000
adc_jext_trg25 Reserved - 11001
adc_jext_trg26 Reserved - 11010
adc_jext_trg27 Reserved - 11011
adc_jext_trg28 Reserved - 11100
adc_jext_trg29 Reserved - 11101
adc_jext_trg30 Reserved - 11110
adc_jext_trg31 Reserved - 11111

25.4.20 Injected channel management

Triggered injection mode
To use triggered injection, the JAUTO bit in the ADC_CFGR register must be cleared.
1. Start the conversion of a group of regular channels either by an external trigger or by
setting the ADSTART bit in the ADC_CR register.
2. If an external injected trigger occurs, or if the JADSTART bit in the ADC_CR register is
set during the conversion of a regular group of channels, the current conversion is
reset and the injected channel sequence switches are launched (all the injected
channels are converted once).
3. Then, the regular conversion of the regular group of channels is resumed from the last
interrupted regular conversion.
4. If a regular event occurs during an injected conversion, the injected conversion is not
interrupted but the regular sequence is executed at the end of the injected sequence.
Figure 149 shows the corresponding timing diagram.

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Note: When using triggered injection, one must ensure that the interval between trigger events is
longer than the injection sequence. For instance, if the sequence length is 20 ADC clock
cycles (that is two conversions with a sampling time of 1.5 clock periods), the minimum
interval between triggers must be 21 ADC clock cycles.

Auto-injection mode
If the JAUTO bit in the ADC_CFGR register is set, then the channels in the injected group
are automatically converted after the regular group of channels. This can be used to convert
a sequence of up to 20 conversions programmed in the ADC_SQRy and ADC_JSQR
registers.
In this mode, the ADSTART bit in the ADC_CR register must be set to start regular
conversions, followed by injected conversions (JADSTART must be kept cleared). Setting
the ADSTP bit aborts both regular and injected conversions (JADSTP bit must not be used).
In this mode, external trigger on injected channels must be disabled.
If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected
channels are continuously converted.
Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously.
When the DMA is used for exporting regular sequencer’s data in JAUTO mode, it is
necessary to program it in circular mode (CIRC bit set in DMA_CCRx register). If the CIRC
bit is reset (single-shot mode), the JAUTO sequence will be stopped upon DMA Transfer
Complete event.

Figure 149. Injected conversion latency

adc_ker_ck

Injection event

Reset ADC

(1)
max. latency
SOC

MSv43771V1

1. The maximum latency value can be found in the electrical characteristics of the device datasheet.

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25.4.21 Discontinuous mode (DISCEN, DISCNUM, JDISCEN)

Regular group mode
This mode is enabled by setting the DISCEN bit in the ADC_CFGR register.
It is used to convert a short sequence (sub-group) of n conversions (n ≤ 8) that is part of the
sequence of conversions selected in the ADC_SQRy registers. The value of n is specified
by writing to the DISCNUM[2:0] bits in the ADC_CFGR register.
When an external trigger occurs, it starts the next n conversions selected in the ADC_SQR
registers until all the conversions in the sequence are done. The total sequence length is
defined by the L[3:0] bits in the ADC_SQR1 register.
Example:
• DISCEN=1, n=3, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10, 11
– 1st trigger: channels converted are 1, 2, 3 (an EOC event is generated at each
conversion).
– 2nd trigger: channels converted are 6, 7, 8 (an EOC event is generated at each
conversion).
– 3rd trigger: channels converted are 9, 10, 11 (an EOC event is generated at each
conversion) and an EOS event is generated after the conversion of channel 11.
– 4th trigger: channels converted are 1, 2, 3 (an EOC event is generated at each
conversion).
– ...
• DISCEN=0, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10,11
– 1st trigger: the complete sequence is converted: channel 1, then 2, 3, 6, 7, 8, 9, 10
and 11. Each conversion generates an EOC event and the last one also generates
an EOS event.
– all the next trigger events will relaunch the complete sequence.
Note: When a regular group is converted in discontinuous mode, no rollover occurs (the last
subgroup of the sequence can have less than n conversions).
When all subgroups are converted, the next trigger starts the conversion of the first
subgroup. In the example above, the 4th trigger reconverts the channels 1, 2 and 3 in the
1st subgroup.
It is not possible to have both discontinuous mode and continuous mode enabled. In this
case (if DISCEN=1, CONT=1), the ADC behaves as if continuous mode was disabled.

Injected group mode

This mode is enabled by setting the JDISCEN bit in the ADC_CFGR register. It converts the
sequence selected in the ADC_JSQR register, channel by channel, after an external
injected trigger event. This is equivalent to discontinuous mode for regular channels where
‘n’ is fixed to 1.
When an external trigger occurs, it starts the next channel conversions selected in the
ADC_JSQR registers until all the conversions in the sequence are done. The total sequence
length is defined by the JL[1:0] bits in the ADC_JSQR register.

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Example:
• JDISCEN=1, channels to be converted = 1, 2, 3
– 1st trigger: channel 1 converted (a JEOC event is generated)
– 2nd trigger: channel 2 converted (a JEOC event is generated)
– 3rd trigger: channel 3 converted and a JEOC event + a JEOS event are generated
– ...
Note: When all injected channels have been converted, the next trigger starts the conversion of
the first injected channel. In the example above, the 4th trigger reconverts the 1st injected
channel 1.
It is not possible to use both auto-injected mode and discontinuous mode simultaneously:
the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

25.4.22 Queue of context for injected conversions

A queue of context is implemented to anticipate up to 2 contexts for the next injected
sequence of conversions. JQDIS bit of ADC_CFGR register must be reset to enable this
feature. Only hardware-triggered conversions are possible when the context queue is
enabled.
This context consists of:
• Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL[4:0] in
ADC_JSQR register)
• Definition of the injected sequence (bits JSQx[4:0] and JL[1:0] in ADC_JSQR register)
All the parameters of the context are defined into a single register ADC_JSQR and this
register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of
parameters:
• The ADC_JSQR register can be written at any moment even when injected
conversions are ongoing.
• Each data written into the JSQR register is stored into the Queue of context.
• At the beginning, the Queue is empty and the first write access into the JSQR register
immediately changes the context and the ADC is ready to receive injected triggers.
• Once an injected sequence is complete, the Queue is consumed and the context
changes according to the next JSQR parameters stored in the Queue. This new
context is applied for the next injected sequence of conversions.
• A Queue overflow occurs when writing into register JSQR while the Queue is full. This
overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the
write access of JSQR register which has created the overflow is ignored and the queue
of context is unchanged. An interrupt can be generated if bit JQOVFIE is set.
• Two possible behaviors are possible when the Queue becomes empty, depending on
the value of the control bit JQM of register ADC_CFGR:
– If JQM=0, the Queue is empty just after enabling the ADC, but then it can never be
empty during run operations: the Queue always maintains the last active context
and any further valid start of injected sequence will be served according to the last
active context.
– If JQM=1, the Queue can be empty after the end of an injected sequence or if the
Queue is flushed. When this occurs, there is no more context in the queue and

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RM0433 Analog-to-digital converters (ADC)

hardware triggers are disabled. Therefore, any further hardware injected triggers
are ignored until the software re-writes a new injected context into JSQR register.
• Reading JSQR register returns the current JSQR context which is active at that
moment. When the JSQR context is empty, JSQR is read as 0x0000.
• The Queue is flushed when stopping injected conversions by setting JADSTP=1 or
when disabling the ADC by setting ADDIS=1:
– If JQM=0, the Queue is maintained with the last active context.
– If JQM=1, the Queue becomes empty and triggers are ignored.
Note: When configured in discontinuous mode (bit JDISCEN=1), only the last trigger of the
injected sequence changes the context and consumes the Queue.The 1st trigger only
consumes the queue but others are still valid triggers as shown by the discontinuous mode
example below (length = 3 for both contexts):
• 1st trigger, discontinuous. Sequence 1: context 1 consumed, 1st conversion carried out
• 2nd trigger, disc. Sequence 1: 2nd conversion.
• 3rd trigger, discontinuous. Sequence 1: 3rd conversion.
• 4th trigger, discontinuous. Sequence 2: context 2 consumed, 1st conversion carried out.
• 5th trigger, discontinuous. Sequence 2: 2nd conversion.
• 6th trigger, discontinuous. Sequence 2: 3rd conversion.
Note: When queue of context enabled (bit JQDIS=0), only hardware trigger can be used.

Behavior when changing the trigger or sequence context

The Figure 150 and Figure 151 show the behavior of the context Queue when changing the
sequence or the triggers.

Figure 150. Example of JSQR queue of context (sequence change)

P1 P2 P3

Write JSQR

JSQR queue EMPTY P1 P1,P2 P2 P2,P3 P3

Trigger 1
ADC J context
EMPTY P1 P2 P3
(returned by reading
JQSR)
ADC state RDY Conversion1 Conversion2 Conversion3 RDY Conversion1 RDY

MS30536V2

1. Parameters:
P1: sequence of 3 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 4 conversions, hardware trigger 1

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Figure 151. Example of JSQR queue of context (trigger change)

P1 P2 P3

Write JSQR

JSQR queue EMPTY P1 P1,P2 P2 P2,P3 P3

Ignored

Trigger 1

Ignored
Trigger 2
ADC J context
EMPTY P1 P2 P3
(returned by reading
JQSR)
ADC state RDY Conversion1 Conversion2 RDY Conversion1 RDY

MS30537V2

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 4 conversions, hardware trigger 1

Queue of context: Behavior when a queue overflow occurs

The Figure 152 and Figure 153 show the behavior of the context Queue if an overflow
occurs before or during a conversion.

Figure 152. Example of JSQR queue of context with overflow before conversion
P1 P2 P3 => Overflow, P4
ignored
Write JSQR

JSQR
EMPTY P1 P1, P2 P2 P2, P4
queue
Cleared by SW
JQOVF

Trigger 1

Trigger 2

ADC
J context
EMPTY P1 P2
(returned by
reading JQSR)

ADC state RDY Conversion1 Conversion2 RDY Conversion1

JEOS

MS30538V2

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 3 conversions, hardware trigger 1
P4: sequence of 4 conversions, hardware trigger 1

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RM0433 Analog-to-digital converters (ADC)

Figure 153. Example of JSQR queue of context with overflow during conversion

P1 P2 P3 => Overflow, P4
ignored
Write JSQR

JSQR
EMPTY P1 P1, P2 P2 P2, P4
queue
Cleared by SW
JQOVF

Trigger 1

Trigger 2
ADC
J context
(returned by EMPTY P1 P2
reading JQSR)

ADC state RDY Conversion1 Conversion2 RDY Conversion1

JEOS

MS30539V2

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 3 conversions, hardware trigger 1
P4: sequence of 4 conversions, hardware trigger 1
It is recommended to manage the queue overflows as described below:
• After each P context write into JSQR register, flag JQOVF shows if the write has been
ignored or not (an interrupt can be generated).
• Avoid Queue overflows by writing the third context (P3) only once the flag JEOS of the
previous context P2 has been set. This ensures that the previous context has been
consumed and that the queue is not full.

Queue of context: Behavior when the queue becomes empty

Figure 154 and Figure 155 show the behavior of the context Queue when the Queue
becomes empty in both cases JQM=0 or 1.

Figure 154. Example of JSQR queue of context with empty queue (case JQM=0)

Queue not empty

The queue is not empty
(P3 maintained)
and maintains P2 because JQM=0
P1 P2 P3

Write JSQR

EMPTY P1 P1, P2 P2 P3
JSQR queue

Trigger 1

ADC J context
(returned by EMPTY P1 P2 P3
reading JQSR)

ADC state RDY Conversion1 RDY Conversion1 RDY Conversion1 RDY Conversion1 RDY Conv

MS30540V3

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

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Note: When writing P3, the context changes immediately. However, because of internal
resynchronization, there is a latency and if a trigger occurs just after or before writing P3, it
can happen that the conversion is launched considering the context P2. To avoid this
situation, the user must ensure that there is no ADC trigger happening when writing a new
context that applies immediately.

Figure 155. Example of JSQR queue of context with empty queue (case JQM=1)

Queue becomes empty

and triggers are ignored
P1 P2 because JQM=1 P3
Write JSQR

JSQR
EMPTY P1 P1,P2 P2 EMPTY P3 EMPTY
queue
Ignored Ignored
Trigger 1
ADC
J context EMPTY P1 P2 EMPTY (0x0000) P3 EMPTY
(returned by reading JQSR)
ADC state RDY Conversion1 RDY Conversion1 RDY Conversion1 RDY

MS30541V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Flushing the queue of context

The figures below show the behavior of the context Queue in various situations when the
queue is flushed.

Figure 156. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs during an ongoing conversion.

Queue is flushed and maintains

P1 P2 the last active context P3
(P2 is lost)
Write JSQR

JSQR queue EMPTY P1 P1, P2 P1 P3

Set Reset
JADSTP by S/W by H/W
JADSTART Reset
by H/W Set
by S/W
Trigger 1

ADC J context EMPTY P1 P3

(returned by reading JSQR)

ADC state RDY STP RDY Conversion1 RDY

MS30544V2

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

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Figure 157. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs.
Queue is flushed and maintains
P1 P2 the last active context P3
(P2 is lost)
Write JSQR
JSQR
queue EMPTY P1 P1, P2 P1 P1, P3 P3
Set Reset
JADSTP by S/W by H/W
JADSTART Reset
by H/W Set
by S/W
Trigger 1

ADC J
context EMPTY P1 P3
(returned by reading JSQR)

ADC state RDY Conv1 STP RDY Conversion1 RDY Conversion1 RDY
(Aborted)
MS30543V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 158. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs outside an ongoing conversion

P1 P2 the last active context P3

(P2 is lost)
Write JSQR

JSQR queue EMPTY P1 P1, P2 P1 P3

Set Reset
JADSTP by S/W by H/W
JADSTART Reset
by H/W Set
by S/W
Trigger 1

ADC J context EMPTY P1 P3

(returned byreading JSQR)

ADC state RDY STP RDY Conversion1 RDY

MS30544V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

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Figure 159. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1)

Queue is flushed and
becomes empty (P2 is lost)
P1 P2 P3
Write JSQR

JSQR queue EMPTY P1 P1, P2 EMPTY P3 EMPTY

Set Reset
by S/W by H/W
JADSTP
JADSTART
Reset Set
by H/W by S/W
Ignored
Trigger 1

ADC J context EMPTY P1 EMPTY (0x0000) P3 EMPTY

(returned by reading JSQR)

ADC state RDY Conv1 STP RDY Conversion1 RDY

(Aborted)
MS30545V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 160. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0)

Queue is flushed and maintains

the last active context
(P2 which was not consumed is lost)

JSQR queue P1, P2 P1

Set Reset
ADDIS by S/W by H/W

ADC J context P1
(returned by reading JSQR)

ADC state RDY REQ-OFF OFF

MS30546V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

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RM0433 Analog-to-digital converters (ADC)

Figure 161. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1)

Queue is flushed and beomes empty

(JSQR is read as 0x0000)

JSQR queue P1, P2 EMPTY

Set Reset
ADDIS by S/W by H/W

ADC J context P1 EMPTY (0x0000)

(returned by reading JSQR)

ADC state RDY REQ-OFF OFF

MS30547V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Queue of context: Starting the ADC with an empty queue

The following procedure must be followed to start ADC operation with an empty queue, in
case the first context is not known at the time the ADC is initialized. This procedure is only
applicable when JQM bit is reset:
5. Write a dummy JSQR with JEXTEN not equal to 0 (otherwise triggering a software
conversion)
6. Set JADSTART
7. Set JADSTP
8. Wait until JADSTART is reset
9. Set JADSTART.

Disabling the queue

It is possible to disable the queue by setting bit JQDIS=1 into the ADC_CFGR register.

Queue of context: Programming of the register ADC_JSQR

When the injected conversion queue of context is enabled (JQDIS=0), the ADC_JSQR must
be programmed at one register write access. As JL[1:0] register define the number of the
injected sequence, corresponding JSQ1 to JSQ4 must be written at same time. If
ADC_JSQR is reprogrammed before the injected conversion start, reprogrammed data is
put on the queue. When queue of context is empty, ADC_JSQR read back as 0x0000.
Register access should not use the ‘read modify write’ sequence.
When ADC_JSQR is programmed when already 2 contexts are queued, it will raise JQOVF
flag and generate the interrupt.

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25.4.23 Programmable resolution (RES) - fast conversion mode

It is possible to perform faster conversion by reducing the ADC resolution.
The resolution can be configured to be either 16, 14, 12, 10, 8 bits by programming the
control bits RES[1:0]. Figure 166, Figure 167, Figure 168 and Figure 169 show the
conversion result format with respect to the resolution as well as to the data alignment.
Lower resolution allows faster conversion time for applications where high-data precision is
not required. It reduces the conversion time spent by the successive approximation steps
according to Table 212.

Table 212. TSAR timings depending on resolution

Tadc_ker_ck (ADC clock Tadc_ker_ck (ns)
TSAR (ns) at
RES TSAR cycles) at
Fadc_ker_ck=24
[2:0] (ADC clock cycles) (with Sampling Time= Fadc_ker_ck=24
MHz
1.5 ADC clock cycles) MHz

16 bits 8.5 ADC clock cycles 354.2 10 ADC clock cycles 416.7
14 bits 7.5 ADC clock cycles 312.5 9 ADC clock cycles 375
12 bits 6.5 ADC clock cycles 270.8 8 ADC clock cycles 333.3
10 bits 5.5 ADC clock cycles 229.2 7 ADC clock cycles 291.7
8 bits 4.5 ADC clock cycles 187.5 6 ADC clock cycles 250.0

25.4.24 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)

The ADC notifies the application for each end of regular conversion (EOC) event and each
injected conversion (JEOC) event.
The ADC sets the EOC flag as soon as a new regular conversion data is available in the
ADC_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by
the software either by writing 1 to it or by reading ADC_DR.
The ADC sets the JEOC flag as soon as a new injected conversion data is available in one
of the ADC_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is
cleared by the software either by writing 1 to it or by reading the corresponding ADC_JDRy
register.
The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for
regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt
can be generated if bit EOSMPIE is set.

25.4.25 End of conversion sequence (EOS, JEOS)

The ADC notifies the application for each end of regular sequence (EOS) and for each end
of injected sequence (JEOS) event.
The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is
available in the ADC_DR register. An interrupt can be generated if bit EOSIE is set. EOS
flag is cleared by the software either by writing 1 to it.
The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is
complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the
software either by writing 1 to it.

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25.4.26 Timing diagrams example (single/continuous modes,

hardware/software triggers)

Figure 162. Single conversions of a sequence, software trigger

ADSTART(1)

EOC

EOS

ADC state(2) RDY CH1 CH9 CH10 CH17 RDY CH1 CH9 CH10 CH17 RDY

D1 D9 D10 D17 D1 D9 D10 D17

ADC_DR

by SW by HW Indicative timings

MS30549V1

1. EXTEN=0x0, CONT=0
2. Channels selected = 1,9, 10, 17; AUTDLY=0.

Figure 163. Continuous conversion of a sequence, software trigger

ADCSTART(1)

EOC

EOS

ADSTP
ADC state(2) READY CH1 CH9 CH10 CH17 CH1 CH9 CH10 STP READY CH1 CH9

ADC_DR D1 D9 D10 D17 D1 D9 D1

by SW by HW Indicative timings

MS30550V1

1. EXTEN=0x0, CONT=1
2. Channels selected = 1,9, 10, 17; AUTDLY=0.

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Figure 164. Single conversions of a sequence, hardware trigger

ADSTART

EOC

EOS

TRGX(1)

ADC state(2) RDY CH1 CH2 CH3 CH4 READY CH1 CH2 CH3 CH4 RDY

ADC_DR D1 D2 D3 D4 D1 D2 D3 D4

by s/w by h/w triggered ignored Indicative timings

MS31013V2

1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0

2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

Figure 165. Continuous conversions of a sequence, hardware trigger

ADSTART

EOC

EOS

ADSTP

TRGx(1)

ADC(2) RDY CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 STOP RDY

ADC_DR D1 D2 D3 D4 D1 D2 D3 D4

by s/w by h/w triggered ignored Not in scale timings

MS31014V2

1. TRGx is selected as trigger source, EXTEN = 10, CONT = 1

2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

25.4.27 Data management

Data register, data alignment and offset (ADC_DR, ADC_JDRy, OFFSETy,
OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE)

Data and alignment

At the end of each regular conversion channel (when EOC event occurs), the result of the
converted data is stored into the ADC_DR data register which is 32 bits wide.
At the end of each injected conversion channel (when JEOC event occurs), the result of the
converted data is stored into the corresponding ADC_JDRy data register which is 32 bits
wide.
The OVSS[3:0] and LSHIFT[3:0] bitfields in the ADC_CFGR2 register selects the alignment
of the data stored after conversion. Data can be right- or left-aligned as shown in
Figure 166, Figure 167, Figure 168 and Figure 169.
Note: The data can be re-aligned in normal and in oversampling mode.

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RM0433 Analog-to-digital converters (ADC)

Offset
An offset y (y=1, 2, 3, 4) can be applied to a channel by programming a value different from
0 in OFFSETy[25:0] bitfield into ADC_OFRy register. The channel to which the offset will be
applied is programmed into the bits OFFSETy_CH[4:0] of ADC_OFRy register. In this case,
the converted value is decreased by the user-defined offset written in the bits
OFFSETy[25:0]. The result may be a negative value so the read data is signed and the
SEXT bit represents the extended sign value.
The offset value should be lower than the max conversion value (ex. 16bit mode, offset
value max is 0xFFFF).
The offset correction is also supported in oversampling mode. For the oversampling mode,
offset is subtracted before OVSS right shift applied.
Table 213 describes how the comparison is performed for all the possible resolutions for
analog watchdog 1, 2, 3.

Table 213. Offset computation versus data resolution

Subtraction between raw
converted data and offset:
Resolution
(bits Raw Result Comments
RES[2:0]) converted
Offset
Data, left
aligned

signed 27-bit
16 bits DATA[15:0] OFFSET[25:0] -
data
signed 27-bit The user must configure OFFSET[1:0]
14 bits DATA[15:2],00 OFFSET[25:0]
data to 00
DATA[15:4],00 signed 27-bit The user must configure OFFSET[3:0]
12 bits OFFSET[25:0]
00 data to 0000
DATA[15:6],00 signed 27-bit The user must configure OFFSET[5:0]
10 bits OFFSET[25:0]
0000 data to 000000
DATA[15:8],00 signed 27-bit The user must configure OFFSET[7:0]
8 bits OFFSET[25:0]
0000 data to 00000000

When reading data from ADC_DR (regular channel) or from ADC_JDRy (injected channel,
y=1,2,3,4), the offset compensation is disabled when ADC_OFRy [25:0] bitfield is reset.
Otherwise, the offset for ADC_OFRy[30:26] channel is enabled.
Figure 166, Figure 167, Figure 168 and Figure 169 show alignments for signed and
unsigned data together with corresponding OVSS and LSHIFT values.

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Figure 166. Right alignment (offset disabled, unsigned value)

31 23 15 7 0

16-bit data 0000 D15..D0

31 23 15 7 0

12-bit data 0000 0 D11..D0

31 23 15 7 0

8-bit data 0000 00 D7..D0

31 23 15 7 0
16-bit data
00 0 D25..D0 OVSS = 0000
OSR=1024

31 23 15 7 0
16-bit data
0000 D15..D0 OVSS = 1011
OSR=1024

MSv41024V1

Figure 167. Right alignment (offset enabled, signed value)

31 23 15 7 0
Signed 32-bit
16-bit data SEXT D15..D0
format

31 23 15 7 0
SSATE = 1
Signed 16-bit
16-bit data SEXT D14..D0 OR
format
RSHIFT1..4 =1

31 23 15 7 0

12-bit data SEXT D11..D0

31 23 15 7 0

8-bit data SEXT D7..D0

31 23 15 7 0
SSATE = 1
Signed 8-bit
8-bit data SEXT D6..D0 OR
format
RSHIFT1..4 =1

31 23 15 7 0
16-bit data
SEXT D25..D0 OVSS = 0000
OSR=1024
MSv41025V1

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RM0433 Analog-to-digital converters (ADC)

Figure 168. Left alignment (offset disabled, unsigned value)

31 23 15 7 0

16-bit data 0000 D15..D0 LSHIFT = 0

31 23 15 7 0

12-bit data 0000 D11..D0 0 LSHIFT = 4

31 23 15 7 0

8-bit data 0000 00 D7..D0 LSHIFT = 0

31 23 15 7 0
16-bit data
D25..D0 0 LSHIFT = 6
OSR=1024
MSv41026V1

Figure 169. Left alignment (offset enabled, signed value)

31 23 15 7 0
Signed 32-bit
16-bit data S D15..D0 0 LSHIFT = 15
format

31 23 15 7 0
Signed 16-bit
16-bit data SEXT D14..D0 SATEN = 1
format

31 23 15 7 0
Signed 16-bit
12-bit data SEXT D11..D0 0 LSHIFT = 3
format

31 23 15 7 0
Signed 16-bit
8-bit data SEXT D7..D0 0 LSHIFT = 7
format

31 23 15 7 0
SSATE = 1
Signed 8-bit
8-bit data SEXT D6..D0 OR
format
RSHIFT1..4 = 1

31 23 15 7 0
16-bit data Signed 32-bit
S D25..D0 0 LSHIFT = 5
OSR=1024 format

MSv41027V2

16-bit and 8-bit signed format management: RSHIFTx,SSATE

The offset correction sign-extends the data format, resulting in an unsigned 16-bit
conversion being extended to 17-bit signed format, for instance.
Three options are offered for formatting 8-bit and 16-bit conversion results.

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For each offset correction channel 1 to 4, a RSHIFT1..4 bit in the ADC_CFGR2 register
allows to have the result right-shifted 1-bit and have it fitting a standard 8 or 16-bit format.
Another option is to have the result saturated to the 16-bit and 8-bit signed formats, for the
following cases only: RES[2:0] = 000 (16-bit format) and RES[2:0] = 111 (8-bit format).
This mode is enabled with the SSATE bit in the ADC_OFRy register.
The table below summarizes the 3 available use case for 16-bit format.

Table 214. 16-bit data formats

Data range
SSATE RSHIFTx Format
(offset = 0x8000)

Sign-extended 17-bit significant data

0 0 0x00007FFF - 0x FFFF8000
SEXT[31:16] DATA[15:0]
Sign-extended right-shifted 16-bit significant
0 1 data 0x3FFF - 0xC000
SEXT[31:15] DATA[14:0]
Sign-extended saturated 16-bit significant data
1 0 7FFF - 0x8000
SEXT[31:15] DATA[14:0]
1 1 Reserved -

Numerical examples are given in Table 215 with 3 different offset values.

Table 215. Numerical examples for 16-bit format (bold indicates saturation)
Result Result Result
Raw conversion
Offset value SSATE = 0 SSATE = 0 SSATE = 1
result
RSHIFT = 0 RSHIFT = 1 RSHIFT = 0

0xFFFF 0x0000 7FFF 3FFF 7FFF

0x8000 0x8000 0x0000 0000 0 0
0x0000 0xFFFF 8000 C000 8000
0xFFFF 0x0000 7FDF 3FEF 7FDF
0x8000 0x8020 0xFFFF FFE0 FFF0 FFE0
0x0000 0xFFFF 7FE0 BFF0 8000
0xFFFF 0x0000 800F 4007 7FFF
0x8000 0x7FF0 0x0000 0010 8 0010
0x0000 0xFFFF 8010 C008 8010

When oversampling mode is active, the SSATE and RSHIFT1..4 bits are not supported.

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RM0433 Analog-to-digital converters (ADC)

ADC overrun (OVR, OVRMOD)

The overrun flag (OVR) notifies of a buffer overrun event when the regular converted data
has not been read (by the CPU or the DMA) before ADC_DR FIFO (eight stages) is
overflowed.
The OVR flag is set when a new conversion completes while ADC_CR register FIFO was
full. An interrupt is generated if OVRIE bit is set to 1.
When an overrun condition occurs, the ADC is still operating and can continue to convert
unless the software decides to stop and reset the sequence by setting ADSTP to 1.
OVR flag is cleared by software by writing 1 to it.
Data can be configured to be preserved or overwritten when an overrun event occurs by
programming the OVRMOD control bit of the ADC_CFGR register:
• OVRMOD = 0
The overrun event preserves the data register from being overwritten: the old data is
maintained up to ADC_DR FIFO depth (8 data) and the new conversion is discarded
and lost. If OVR remains at 1, any further conversion is be performed but the resulting
data is also dicarded.
• OVRMOD = 1
The data register is overwritten with the last conversion result and the previous unread
data is lost. In this mode, ADC_DR FIFO is disabled. If OVR remains at 1, any further
conversion is performed normally and the ADC_DR register always contains the latest
converted data.

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Figure 170. Example of overrun (OVRMOD = 0)

ADSTART

EOC

OVR

ADSTP

TRGx

ADC state RDY CH1 CH2 CH3 CH4 --- CH11 CH12 CH13 STOP RDY

ADC_DR read
access

ADC_DR D1 D2 D3 D4

D4 D5

ADC_DR
(FIFO_DATA) D9 D10

D10 na D12

by s/w by h/w triggered Indicative timings

MSv69549V1

Figure 171. Example of overrun (OVRMOD = 1)

ADSTART

EOC

OVR

ADSTP

TRGx

ADC state RDY CH1 CH2 CH3 CH4 CH5 CH6 CH7 STOP RDY
Overun
ADC_DR read access

ADC_DR
D1 D2 D3 D4 D5 D6
(OVRMOD =1)

by s/w by h/w triggered Indicative timings

MSv65301V1

Note: There is no overrun detection on the injected channels since there is a dedicated data
register for each of the four injected channels.

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RM0433 Analog-to-digital converters (ADC)

Managing a sequence of conversion without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by the
software. In this case the software must use the EOC flag and its associated interrupt to
handle each data. Each time a conversion is complete, EOC is set and the ADC_DR
register can be read. OVRMOD should be configured to 0 to manage overrun events or
FIFO overflows as errors.

Managing conversions without using the DMA and without overrun

It may be useful to let the ADC convert one or more channels without reading the data each
time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be
configured to 1 and OVR flag should be ignored by the software. An overrun event will not
prevent the ADC from continuing to convert and the ADC_DR register will always contain
the latest conversion.

Managing conversions using the DMA

Since converted channel values are stored into a unique data register, it is useful to use
DMA for conversion of more than one channel. This avoids the loss of the data already
stored in the ADC_DR register.
When the DMA mode is enabled (DMNGT bit = 01 or 11 in the ADC_CFGR register in single
ADC mode or MDMA different from 0b00 in dual ADC mode), a DMA request is generated
after each conversion of a channel. This allows the transfer of the converted data from the
ADC_DR register to the destination location selected by the software.
Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to Section : ADC overrun (OVR, OVRMOD)).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMNGT of the ADC_CFGR register in single ADC mode, or with bit
DAMDF of the ADCx_CCR register in dual ADC mode:
• DMA one shot mode (DMNGT bit = 01).
This mode is suitable when the DMA is programmed to transfer a fixed number of data.
• DMA circular mode (DMNGT bit = 11)
This mode is suitable when programming the DMA in circular mode.

DMA one shot mode (DMNGT=01)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available and stops generating DMA requests once the DMA has reached the last DMA
transfer (when a transfer complete interrupt occurs - refer to DMA section) even if a
conversion has been started again.

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When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
• The content of the ADC data register is frozen.
• Any ongoing conversion is aborted with partial result discarded.
• No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
• Scan sequence is stopped and reset.
• The DMA is stopped.

DMA circular mode (DMNGT=11)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available in the data register, even if the DMA has reached the last DMA transfer. This
allows configuring the DMA in circular mode to handle a continuous analog input data
stream.

DMA with FIFO

The output data register has eight-stage FIFO. Two different DMA requests are generated
parallel. When a data is available, “SREQ single request” generated, when 4 data are
available, “BREQ burst request” generated. DMA2 can be programmed either single
transfer mode or incremental burst mode(4 beats), according to this mode, correct request
line is selected by the DMA2. Please refer to the DMA2 chapter for further information.

25.4.28 Managing conversions using the DFSDM

The ADC conversion results can be transferred directly to the Digital Filter for Sigma Delta
Modulators (DFSDM).
In this case, the DMNGT[1:0] bits must be set to 10.
The ADC transfers 16 least significant bits of the regular data register data to the DFSDM,
which in turns will reset the EOC flag once the transfer is effective.
The data format must be 16-bit signed:
ADC_DR[31:16] = don’t care
ADC_DR[15] = sign
ADC_DR[14:0] = data
Any value above 16-bit signed format will be truncated.

25.4.29 Dynamic low-power features

Auto-delayed conversion mode (AUTDLY)
The ADC implements an auto-delayed conversion mode controlled by the AUTDLY
configuration bit. Auto-delayed conversions are useful to simplify the software as well as to
optimize performance of an application clocked at low frequency where there would be risk
of encountering an ADC overrun.

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When AUTDLY=1, a new conversion can start only if all the previous data of the same group
has been treated:
• For a regular conversion: once the ADC_DR register has been read or if the EOC bit
has been cleared (see Figure 172).
• For an injected conversion: when the JEOS bit has been cleared (see Figure 173).
This is a way to automatically adapt the speed of the ADC to the speed of the system which
will read the data.
The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after
each sequence of injected conversions (whatever JDISCEN=0 or 1).
Note: There is no delay inserted between each conversions of the injected sequence, except after
the last one.
During a conversion, a hardware trigger event (for the same group of conversions) occurring
during this delay is ignored.
Note: This is not true for software triggers where it remains possible during this delay to set the
bits ADSTART or JADSTART to re-start a conversion: it is up to the software to read the
data before launching a new conversion.
No delay is inserted between conversions of different groups (a regular conversion followed
by an injected conversion or conversely):
• If an injected trigger occurs during the automatic delay of a regular conversion, the
injected conversion starts immediately (see Figure 173).
• Once the injected sequence is complete, the ADC waits for the delay (if not ended) of
the previous regular conversion before launching a new regular conversion (see
Figure 175).
The behavior is slightly different in auto-injected mode (JAUTO=1) where a new regular
conversion can start only when the automatic delay of the previous injected sequence of
conversion has ended (when JEOS has been cleared). This is to ensure that the software
can read all the data of a given sequence before starting a new sequence (see Figure 176).
To stop a conversion in continuous auto-injection mode combined with autodelay mode
(JAUTO=1, CONT=1 and AUTDLY=1), follow the following procedure:
1. Wait until JEOS=1 (no more conversions are restarted)
2. Clear JEOS,
3. Set ADSTP=1
4. Read the regular data.
If this procedure is not respected, a new regular sequence can re-start if JEOS is cleared
after ADSTP has been set.
In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already
ongoing regular sequence or during the delay that follows the last regular conversion of the
sequence. It is however considered pending if it occurs after this delay, even if it occurs
during an injected sequence of the delay that follows it. The conversion then starts at the
end of the delay of the injected sequence.
In AUTDLY mode, a hardware injected trigger event is ignored if it occurs during an already
ongoing injected sequence or during the delay that follows the last injected conversion of
the sequence.

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Figure 172. AUTDLY=1, regular conversion in continuous mode, software trigger

ADSTART (1)

EOC

EOS

ADSTP
ADC_DR read access

ADC state RDY CH1 DLY CH2 DLY CH3 DLY CH1 DLY STOP RDY

ADC_DR D1 D2 D3 D1

by SW by HW
Indicative timings

MS31020V1

1. AUTDLY=1
2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, CHANNELS = 1,2,3
3. Injected configuration DISABLED

Figure 173. AUTDLY=1, regular HW conversions interrupted by injected conversions

(DISCEN=0; JDISCEN=0)

Not ignored
Ignored (occurs during injected sequence)
Regular
trigger
ADC state RDY CH1 DLY CH2 DLY CH5 CH6 CH3 DLY CH1 DLY CH2
regular regular injected regular injected regular regular
DLY (CH1) DLY (CH2) DLY (CH3) DLY (CH1)

EOC
EOS
ADC_DR
read access
ADC_DR D1 D2 D3 D1
Injected Ignored
trigger
DLY (inj)
JEOS
ADC_JDR1 D5

ADC_JDR2 D6

by s/w by h/w Indicative timings

MS31021V2

1. AUTDLY=1
2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6

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Figure 174. AUTDLY=1, regular HW conversions interrupted by injected conversions

(DISCEN=1, JDISCEN=1)

Ignored Not ignored (occurs during

injected sequence)
Regular trigger
ADC state RDY CH1 DLY RDY CH2 DLY RDY CH5 RDY CH6 CH3 DLY RDY CH1 DLY RDY CH2
regular regular injected injected regular regular regular
DLY (CH1) DLY (CH2) DLY (CH3) DLY (CH1)

EOC
EOS
ADC_DR
read access
ADC_DR D1 D2 D3 D1
Ignored Ignored
Injected trigger
DLY (inj)
JEOS
ADC_JDR1 D5

ADC_JDR2 D6

by SW by HW Indicative timings

MS31022V1

1. AUTDLY=1
2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3.
3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=1, CHANNELS = 5,6

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Figure 175. AUTDLY=1, regular continuous conversions interrupted by injected conversions

ADSTART(1)
ADC
RDY CH1 DLY CH2 DLY CH5 CH6 DLY CH3 DLY CH1
state
regular regular injected injected regular
DLY (CH1) DLY (CH2) regular
DLY (CH3)

EOC
EOS
ADC_DR read
access
ADC_DR D1 D2 D3
Ignored
Injected
trigger
DLY (inj)
JEOS
ADC_JDR1 D5
ADC_JDR2 D6

by s/w by h/w Indicative timings

MS31023V3

1. AUTDLY=1
2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6

Figure 176. AUTDLY=1 in auto- injected mode (JAUTO=1)

ADSTART(1) No delay

ADC state RDY CH1 DLY (CH1) CH2 CH5 CH6 DLY (inj) CH3 DLY CH1
regular regular injected injected regular regular
EOC
EOS
ADC_DR read access

ADC_DR D1 D2 D3
JEOS
ADC_JDR1 D5

ADC_JDR2 D6

by s/w by h/w Indicative timings

MS31024V4

1. AUTDLY=1
2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2
3. Injected configuration: JAUTO=1, CHANNELS = 5,6

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RM0433 Analog-to-digital converters (ADC)

25.4.30 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,

AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)
The three AWD analog watchdogs monitor whether some channels remain within a
configured voltage range (window).

Figure 177. Analog watchdog guarded area

Analog voltage
Higher threshold HTR
Guarded area
Lower threshold LTR
ai16048

AWDx flag and interrupt

An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDyIE in the
ADC_IER register (x=1,2,3).
AWDy (y=1,2,3) flag is cleared by software by writing 1 to it.
The ADC conversion result is compared to the lower and higher thresholds before
alignment.
Description of analog watchdog 1
The AWD analog watchdog 1 is enabled by setting the AWD1EN bit in the ADC_CFGR
register. This watchdog monitors whether either one selected channel or all enabled
channels(1) remain within a configured voltage range (window).
Table 216 shows how the ADC_CFGRy registers should be configured to enable the analog
watchdog on one or more channels.

Table 216. Analog watchdog channel selection

Channels guarded by the analog
AWD1SGL bit AWD1EN bit JAWD1EN bit
watchdog

None x 0 0
All injected channels 0 0 1
All regular channels 0 1 0
All regular and injected channels 0 1 1
(1)
Single injected channel 1 0 1
Single(1) regular channel 1 1 0
(1)
Single regular or injected channel 1 1 1
1. Selected by the AWDyCH[4:0] bits. The channels must also be programmed to be converted in the
appropriate regular or injected sequence.

The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold.

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These thresholds are programmed in bits HTR1[25:0] of the ADC_HTR1 register and
LTR1[25:0] of the ADC_LTR1 register for the analog watchdog 1.
The threshold can be up to 26-bits (16-bit resolution with oversampling, OSVR[9:0]=1024).
When converting data with a resolution of less than 16 bits (according to bits RES[2:0]), the
LSBs of the programmed thresholds must be kept cleared, the internal comparison being
performed on the full 16-bit converted data (left aligned to the half-word boundary).
Table 217 describes how the comparison is performed for all the possible resolutions for
analog watchdog 1,2,3.

Table 217. Analog watchdog 1,2,3 comparison

Analog watchdog comparison
between:
Resolution
(bit Comments
Raw converted
RES[2:0])
data, left Thresholds
aligned(1)

LTR1[25:0] and
16 bits DATA[15:0] -
HTR1[25:0]
LTR1[25:0] and User must configure LTR1[1:0] and
14 bits DATA[15:2],00
HTR1[25:0] HTR1[1:0] to 00
LTR1[25:0] and User must configure LTR1[3:0] and
12 bits DATA[15:4],0000
HTR1[25:0] HTR1[3:0] to 0000
DATA[15:6],00000 LTR1[25:0] and User must configure LTR1[5:0] and
10 bits
0 HTR1[25:0] HTR1[5:0] to 000000
DATA[15:8],00000 LTR1[25:0] and User must configure LTR1[7:0] and
8 bits
000 HTR1[25:0] HTR1[7:0] to 00000000
1. The watchdog comparison is performed on the raw converted data before any alignment cal-
culation and before applying any offsets (the data which is compared is not signed).

Description of analog watchdog 2 and 3

The second and third analog watchdogs are more flexible and can guard several selected
channels by programming the corresponding bits in AWDCHy[19:0] (y=2,3).
The corresponding watchdog is enabled when any bit of AWDCHy[19:0] (y=2,3) is set.
The threshold can be up to 26-bits (16-bit resolution with oversampling, OSVR[9:0]=1024)
and are programmed with the ADC_HTR2, ADC_LTR2, ADC_LTR3, and ADC_HTR3
registers.
When converting data with a resolution of less than 16 bits (according to bits RES[2:0]), the
LSBs of the programmed thresholds must be kept cleared, the internal comparison being
performed on the full 16-bit converted data (left aligned to the half-word boundary).

ADCx_AWDy_OUT signal output generation

Each analog watchdog is associated to an internal hardware signal ADCx_AWDy_OUT
(x=ADC number, y=watchdog number) which is directly connected to the ETR input
(external trigger) of some on-chip timers. Refer to the on-chip timers section to understand
how to select the ADCx_AWDy_OUT signal as ETR.

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ADCx_AWDy_OUT is activated when the associated analog watchdog is enabled:

• ADCx_AWDy_OUT is set when a guarded conversion is outside the programmed
thresholds.
• ADCx_AWDy_OUT is reset after the end of the next guarded conversion which is
inside the programmed thresholds (It remains at 1 if the next guarded conversions are
still outside the programmed thresholds).
• ADCx_AWDy_OUT is also reset when disabling the ADC (when setting ADDIS=1).
Note that stopping regular or injected conversions (setting ADSTP=1 or JADSTP=1)
has no influence on the generation of ADCy_AWDx_OUT.
Note: AWDx flag is set by hardware and reset by software: AWDy flag has no influence on the
generation of ADCx_AWDy_OUT (ex: ADCy_AWDy_OUT can toggle while AWDx flag
remains at 1 if the software did not clear the flag).

Figure 178. ADCy_AWDx_OUT signal generation (on all regular channels)

ADC
RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
STATE
inside outside inside outside outside outside inside
EOC FLAG

AWDx FLAG cleared cleared cleared cleared

by S/W by S/W by S/W by S/W

ADCy_AWDx_OUT

- Converting regular channels 1,2,3,4,5,6,7

- Regular channels 1,2,3,4,5,6,7 are all guarded

MS31025V1

Figure 179. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW)

ADC
RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
STATE
inside outside inside outside outside outside inside
EOC FLAG

not cleared by S/W

AWDx FLAG

ADCy_AWDx_OUT

- Converting regular channels 1,2,3,4,5,6,7

- Regular channels 1,2,3,4,5,6,7 are all guarded

MS31026V1

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Figure 180. ADCy_AWDx_OUT signal generation (on a single regular channel)

ADC
Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2
STATE
outside inside outside outside
EOC FLAG

EOS FLAG

AWDx FLAG cleared cleared

by S/W by S/W

ADCy_AWDx_OUT

- Converting regular channels 1 and 2

- Only channel 1 is guarded
MS31027V1

Figure 181. ADCy_AWDx_OUT signal generation (on all injected channels)

ADC
RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion Conversion Conversion
STATE
inside outside inside outside outside outside inside
JEOS FLAG

cleared cleared cleared cleared

AWDx FLAG by S/W
by S/W by S/W by S/W

ADCy_AWDx_OUT

- Converting the injected channels 1, 2, 3, 4

- All injected channels 1, 2, 3, 4 are guarded

MS31028V1

25.4.31 Oversampler
The oversampling unit performs data preprocessing to offload the CPU. It is able to handle
multiple conversions and average them into a single data with increased data width, up to
26-bit (16-bit values and OSVR[9:0] = 1024).
It provides a result with the following form, where N and M can be adjusted:

n = N–1
1
Result = ----- ×
M ∑ Conversion(t n)
n=0

It allows to perform by hardware the following functions: averaging, data rate reduction,
SNR improvement, basic filtering.

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The oversampling ratio N is defined using the OSVR[9:0] bits in the ADC_CFGR2 register,
and can range from 2x to 1024x. The division coefficient M consists of a right bit shift up to
10 bits, and is defined using the OVSS[3:0] bits in the ADC_CFGR2 register.
The summation unit can yield a result up to 26 bits (1024 x 16-bit results), which can be left
or right shifted. When right shifting is selected, it is rounded to the nearest value using the
least significant bits left apart by the shifting, before being transferred into the ADC_DR data
register.
The Table 182 gives a numerical example of the processing, from a raw 26-bit accumulated
data to the final 16-bit result.

Figure 182. 16-bit result oversampling with 10-bits right shift and rouding

31 23 15 7 0
16-bit data
0 D25..D0 OVSS[3:0]=0
OSVR=1024
Right shifting and rounding

31 23 15 7 0
16-bit data
0 D15..D0 OVSS[3:0]=1010
OSVR=1024

31 23 15 7 0
16-bit data
0 0x3FFE258 OVSS[3:0]=0
OSVR=1024
Right shifting and rounding

31 23 15 7 0
16-bit data
0 0xFFF9 OVSS[3:0]=1010
OSVR=1024

MSv41028V2

There are no changes for conversion timings in oversampled mode: the sample time is
maintained equal during the whole oversampling sequence. A new data is provided every N
conversions, with an equivalent delay equal to N x TCONV = N x (tSMPL + tSAR). The flags are
set as follow:
• the end of the sampling phase (EOSMP) is set after each sampling phase
• the end of conversion (EOC) occurs once every N conversions, when the oversampled
result is available
• the end of sequence (EOS) occurs once the sequence of oversampled data is
completed (i.e. after N x sequence length conversions total)

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Single ADC operating modes support when oversampling

In oversampling mode, most of the ADC operating modes are maintained:
• Single or continuous mode conversions
• ADC conversions start either by software or with triggers
• ADC stop during a conversion (abort)
• Data read via CPU or DMA with overrun detection
• Low-power modes (AUTDLY)
• Programmable resolution: in this case, the reduced conversion values (as per RES[2:0]
bits in ADC_CFGR register) are accumulated, truncated, rounded and shifted in the
same way as 16-bit conversions are
Note: The alignment mode is not available when working with oversampled data. The data are
always provided right-aligned.

Analog watchdog
The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the
following difference:
• the RES[2:0] bits are ignored, comparison is always done on using the full 26-bit values
HTRx[25:0] and LTRx[25:0]
• the comparison is performed on the oversampled accumulated value before shifting
Note: Care must be taken when using high shifting values, this will reduce the comparison range.
For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data right-
aligned, the effective analog watchdog comparison can only be performed on 8 bits. The
comparison is done between ADC_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8]
must be kept reset.

Triggered mode
The averager can also be used for basic filtering purpose. Although not a very powerful filter
(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject
constant parasitic frequencies (typically coming from the mains or from a switched mode
power supply). For this purpose, a specific discontinuous mode can be enabled with
TROVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a
user and independent from the conversion time itself.
The Figure 183 below shows how conversions are started in response to triggers during
discontinuous mode.
If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1.

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Figure 183. Triggered regular oversampling mode (TROVS bit = 1)

Trigger Trigger
CONT=0
DISCEN = 1
TROVS = 0
Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3

EOC flag set

Trigger Trigger Trigger Trigger Trigger Trigger Trigger

CONT=0
DISCEN = 1
TROVS = 1
Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(N)0 Ch(N)1 Ch(N)2

EOC flag set

MS34455V2

Injected and regular sequencer management when oversampling

In oversampling mode, it is possible to have differentiated behavior for injected and regular
sequencers. The oversampling can be enabled for both sequencers with some limitations if
they have to be used simultaneously (this is related to a unique accumulation unit).

Oversampling regular channels only

The regular oversampling mode bit ROVSM defines how the regular oversampling
sequence is resumed if it is interrupted by injected conversion:
• in continued mode, the accumulation re-starts from the last valid data (prior to the
conversion abort request due to the injected trigger). This ensures that oversampling
will be completed whatever the injection frequency (providing at least one regular
conversion can be completed between triggers);
• in resumed mode, the accumulation re-starts from 0 (previous conversions results are
ignored). This mode allows to guarantee that all data used for oversampling were
converted back-to-back within a single timeslot. Care must be taken to have a injection
trigger period above the oversampling period length. If this condition is not respected,
the oversampling cannot be completed and the regular sequencer will be blocked.
The Figure 184 gives examples for a 4x oversampling ratio.

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Figure 184. Regular oversampling modes (4x ratio)

Oversampling Oversampling
stopped continued

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(M)0 Ch(M)1 Ch(M)1 Ch(M)2 Ch(M)3 Ch(O)0
Abort
Trigger

Injected channels Ch(J) Ch(K)

JEOC

Continued mode: ROVSE = 1, JOVSE = 0, ROVSM = 0, TROVS = X

Oversampling Oversampling
aborted resumed

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(M)0 Ch(M)1 Ch(M)0 Ch(M)1 Ch(M)2 Ch(M)3
Abort
Trigger

Injected channels Ch(J) Ch(K)

JEOC

Resumed mode: ROVSE = 1, JOVSE = 0, ROVSM = 1, TROVS = X

MS34456V1

Oversampling Injected channels only

The Injected oversampling mode bit JOVSE enables oversampling solely for conversions in
the injected sequencer.

Oversampling regular and Injected channels

It is possible to have both ROVSE and JOVSE bits set. In this case, the regular
oversampling mode is forced to resumed mode (ROVSM bit ignored), as represented on
Figure 185 below.

Figure 185. Regular and injected oversampling modes used simultaneously

Oversampling Oversampling
aborted resumed

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(M)0 Ch(M)1 Ch(M)0 Ch(M)1
Abort
Trigger

Injected channels Ch(J)0 Ch(J)1 Ch(J)2 Ch(J)3

JEOC

ROVSE = 1, JOVSE = 1, ROVSM = 1, TROVS = 0

MS34457V2

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Triggered regular oversampling with injected conversions

It is possible to have triggered regular mode with injected conversions. In this case, the
injected mode oversampling mode must be disabled, and the ROVSM bit is ignored
(resumed mode is forced). The JOVSE bit must be reset. The behavior is represented on
Figure 186 below.

Figure 186. Triggered regular oversampling with injection

Oversampling
resumed

Trigger Trigger Trigger Trigger Trigger

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)0 Ch(N)1

Abort Resumed
Trigger

Injected channels Ch(J) Ch(K)

ROVSE = 1, JOVSE = 0, ROVSM = 1, TROVS = 1

MS34458V4

Auto-injected mode
It is possible to oversample auto-injected sequences and have all conversions results stored
in registers to save a DMA resource. This mode is available only with both regular and
injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations
are not supported. The ROVSM bit is ignored in auto-injected mode. The Figure 187 below
shows how the conversions are sequenced.

Figure 187. Oversampling in auto-injected mode

Regular channels N0 N1 N2 N3 N0 N1 N2 N3

Injected channels I0 I1 I2 I3 J0 J1 J2 J3 K0 K1 K2 K3 L0 L1 L2 L3

JAUTO =1, ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0

MS34459V1

It is possible to have also the triggered mode enabled, using the TROVS bit. In this case,
the ADC must be configured as following: JAUTO=1, DISCEN=0, JDISCEN=0, ROVSE=1,
JOVSE=1 and TROVSE=1.

Dual ADC modes support when oversampling

It is possible to have oversampling enabled when working in dual ADC configuration, for the
injected simultaneous mode and regular simultaneous mode. In this case, the two ADCs
must be programmed with the very same settings (including oversampling).
All other dual ADC modes are not supported when either regular or injected oversampling is
enabled (ROVSE = 1 or JOVSE = 1).

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Combined modes summary

The Table 218 below summarizes all combinations, including modes not supported.

Table 218. Oversampler operating modes summary

Oversampler
Regular Over- Injected Over- mode Triggered
sampling sampling ROVSM Regular mode Comment
ROVSE JOVSE 0 = continued TROVS
1 = resumed

1 0 0 0 Regular continued mode

1 0 0 1 Not supported
1 0 1 0 Regular resumed mode
Triggered regular resumed
1 0 1 1
mode
1 1 0 X Not supported
Injected and regular resumed
1 1 1 0
mode
1 1 1 1 Not supported
0 1 X X Injected oversampling

25.4.32 Dual ADC modes

In devices with two ADCs or more, dual ADC modes can be used (see Figure 188):
• ADC1 and ADC2 can be used together in dual mode (ADC1 is master)
In dual ADC mode the start of conversion is triggered alternately or simultaneously by the
ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in
the ADCx_CCR register.
Four possible modes are implemented:
• Injected simultaneous mode
• Regular simultaneous mode
• Interleaved mode
• Alternate trigger mode
It is also possible to use these modes combined in the following ways:
• Injected simultaneous mode + Regular simultaneous mode
• Regular simultaneous mode + Alternate trigger mode
• Injected simultaneous mode + Interleaved mode
In dual ADC mode (when bits DUAL[4:0] in ADCx_CCR register are not equal to zero), the
bits CONT, AUTDLY, DISCEN, DISCNUM[2:0], JDISCEN, JQM, JAUTO of the ADC_CFGR
register are shared between the master and slave ADC: the bits in the slave ADC are
always equal to the corresponding bits of the master ADC.
To start a conversion in dual mode, the user must program the bits EXTEN, EXTSEL,
JEXTEN, JEXTSEL of the master ADC only, to configure a software or hardware trigger,

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and a regular or injected trigger. (the bits EXTEN[1:0] and JEXTEN[1:0] of the slave ADC
are don’t care).
In regular simultaneous or interleaved modes: once the user sets bit ADSTART or bit
ADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically
set. However, bit ADSTART or bit ADSTP of the slave ADC is not necessary cleared at the
same time as the master ADC bit.
In injected simultaneous or alternate trigger modes: once the user sets bit JADSTART or bit
JADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically
set. However, bit JADSTART or bit JADSTP of the slave ADC is not necessary cleared at
the same time as the master ADC bit.
In dual ADC mode, the converted data of the master and slave ADC can be read in parallel,
by reading the ADC common data register (ADCx_CDR). The status bits can be also read in
parallel by reading the dual-mode status register (ADCx_CSR).

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Figure 188. Dual ADC block diagram(1)

Regular data register

(32-bits)

Injected data registers

Internal analog inputs (4 x32-bits)
Regular

Address/data bus
channels
Slave ADC
Injected
channels

ADCx_INP0, Internal triggers

ADCx_INN0
ADCx_INP2, GPIO Regular data register
ADCx_INN2 ports (32-bits)

ADCx_INP19, Injected data registers

ADCx_INN19 (4 x32-bits)
Regular
channels
Internal analog inputs
Injected
channels

Dual mode
control

Start trigger mux.

(regular group)

Master ADC

Start trigger mux.

(injected group)

MSv41029V2

1. External triggers also exist on slave ADC but are not shown for the purposes of this diagram.
2. The ADC common data register (ADCx_CDR) contains both the master and slave ADC regular converted data.

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Injected simultaneous mode

This mode is selected by programming bits DUAL[4:0]=00101
This mode converts an injected group of channels. The external trigger source comes from
the injected group multiplexer of the master ADC (selected by the JEXTSEL[4:0] bits in the
ADC_JSQR register).
Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the
two ADCs when converting the same channel).
In simultaneous mode, one must convert sequences with the same length and inside a
sequence, the N-th conversion in master ans slave must be configured with the same
sampling time.
Regular conversions can be performed on one or all ADCs. In that case, they are
independent of each other and are interrupted when an injected event occurs. They are
resumed at the end of the injected conversion group.
• At the end of injected sequence of conversion event (JEOS) on the master ADC, the
converted data is stored into the master ADC_JDRy registers and a JEOS interrupt is
generated (if enabled)
• At the end of injected sequence of conversion event (JEOS) on the slave ADC, the
converted data is stored into the slave ADC_JDRy registers and a JEOS interrupt is
generated (if enabled)
• If the duration of the master injected sequence is equal to the duration of the slave
injected one (like in Figure 189), it is possible for the software to enable only one of the
two JEOS interrupt (ex: master JEOS) and read both converted data (from master
ADC_JDRy and slave ADC_JDRy registers).

Figure 189. Injected simultaneous mode on 4 channels: dual ADC mode

MASTER ADC CH1 CH2 CH3 CH4

SLAVE ADC CH15 CH14 CH13 CH12

Trigger
Sampling End of injected sequence on
MASTER and SLAVE ADC
Conversion

MS31900V1

If JDISCEN=1, each simultaneous conversion of the injected sequence requires an injected

trigger event to occur.
This mode can be combined with AUTDLY mode:
• Once a simultaneous injected sequence of conversions has ended, a new injected
trigger event is accepted only if both JEOS bits of the master and the slave ADC have
been cleared (delay phase). Any new injected trigger events occurring during the
ongoing injected sequence and the associated delay phase are ignored.
• Once a regular sequence of conversions of the master ADC has ended, a new regular
trigger event of the master ADC is accepted only if the master data register (ADC_DR)
has been read. Any new regular trigger events occurring for the master ADC during the
ongoing regular sequence and the associated delay phases are ignored.
There is the same behavior for regular sequences occurring on the slave ADC.

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Regular simultaneous mode with independent injected

This mode is selected by programming bits DUAL[4:0] = 00110.
This mode is performed on a regular group of channels. The external trigger source comes
from the regular group multiplexer of the master ADC (selected by the EXTSEL[4:0] bits in
the ADC_CFGR register). A simultaneous trigger is provided to the slave ADC.
In this mode, independent injected conversions are supported. An injection request (either
on master or on the slave) will abort the current simultaneous conversions, which are re-
started once the injected conversion is completed.
Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the
two ADCs when converting the same channel).
In regular simultaneous mode, one must convert sequences with the same length and
inside a sequence, the N-th conversion in master ans slave must be configured with the
same sampling time.
Software is notified by interrupts when it can read the data:
• At the end of each conversion event (EOC) on the master ADC, a master EOC interrupt
is generated (if EOCIE is enabled) and software can read the ADC_DR of the master
ADC.
• At the end of each conversion event (EOC) on the slave ADC, a slave EOC interrupt is
generated (if EOCIE is enabled) and software can read the ADC_DR of the slave ADC.
• If the duration of the master regular sequence is equal to the duration of the slave one
(like in Figure 190), it is possible for the software to enable only one of the two EOC
interrupt (ex: master EOC) and read both converted data from the Common Data
register (ADCx_CDR).
It is also possible to read the regular data using the DMA. Two methods are possible:
• Using two DMA channels (one for the master and one for the slave). In this case bits
DAMDF[1:0] must be kept cleared.
– Configure the DMA master ADC channel to read ADC_DR from the master. DMA
requests are generated at each EOC event of the master ADC.
– Configure the DMA slave ADC channel to read ADC_DR from the slave. DMA
requests are generated at each EOC event of the slave ADC.
• Configuring Dual ADC mode data format DAMDF[1:0] bits, which leaves one DMA
channel free for other uses:
– Configure DAMDF[1:0]=0b10 or 0b11 (depending on resolution).
– A single DMA channel is used (the one of the master). Configure the DMA master
ADC channel to read the common ADC register (ADCx_CDR)
– A single DMA request is generated each time both master and slave EOC events
have occurred. At that time, the slave ADC converted data is available in the
upper half-word of the ADCx_CDR 32-bit register and the master ADC converted
data is available in the lower half-word of ADCx_CDR register.
– both EOC flags are cleared when the DMA reads the ADCx_CDR register.
Note: When DAMDF[1:0]=0b10 or 0b11, the user must program the same number of conversions
in the master’s sequence as in the slave’s sequence. Otherwise, the remaining conversions
will not generate a DMA request.

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Figure 190. Regular simultaneous mode on 16 channels: dual ADC mode

MASTER ADC CH1 CH2 CH3 CH4 ... CH16

SLAVE ADC CH16 CH14 CH13 CH12 ... CH1

Trigger End of regular sequence on

Sampling MASTER and SLAVE ADC

Conversion
ai16054b

If DISCEN=1 then each “n” simultaneous conversions of the regular sequence require a
regular trigger event to occur (“n” is defined by DISCNUM).
This mode can be combined with AUTDLY mode:
• Once a simultaneous conversion of the sequence has ended, the next conversion in
the sequence is started only if the common data register, ADCx_CDR (or the regular
data register of the master ADC) has been read (delay phase).
• Once a simultaneous regular sequence of conversions has ended, a new regular
trigger event is accepted only if the common data register (ADCx_CDR) has been read
(delay phase). Any new regular trigger events occurring during the ongoing regular
sequence and the associated delay phases are ignored.
It is possible to use the DMA to handle data in regular simultaneous mode combined with
AUTDLY mode, assuming that multi-DMA mode is used: bits DAMDF must be set to 0b10 or
0b11.
When regular simultaneous mode is combined with AUTDLY mode, it is mandatory for the
user to ensure that:
• The number of conversions in the master’s sequence is equal to the number of
conversions in the slave’s.
• For each simultaneous conversions of the sequence, the length of the conversion of
the slave ADC is inferior to the length of the conversion of the master ADC. Note that
the length of the sequence depends on the number of channels to convert and the
sampling time and the resolution of each channels.
Note: This combination of regular simultaneous mode and AUTDLY mode is restricted to the use
case when only regular channels are programmed: it is forbidden to program injected
channels in this combined mode.

Interleaved mode with independent injected

This mode is selected by programming bits DUAL[4:0] = 00111.
This mode can be started only on a regular group (usually one channel). The external
trigger source comes from the regular channel multiplexer of the master ADC.
After an external trigger occurs:
• The master ADC starts immediately.
• The slave ADC starts after a delay of several ADC clock cycles after the sampling
phase of the master ADC has complete.
The minimum delay which separates 2 conversions in interleaved mode is configured in the
DELAY bits in the ADCx_CCR register. This delay starts to count after the end of the
sampling phase of the master conversion. This way, an ADC cannot start a conversion if the

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complementary ADC is still sampling its input (only one ADC can sample the input signal at
a given time).
• The minimum possible DELAY is 1 to ensure that there is at least one cycle time
between the opening of the analog switch of the master ADC sampling phase and the
closing of the analog switch of the slave ADC sampling phase.
• The maximum DELAY is equal to the number of cycles corresponding to the selected
resolution. However the user must properly calculate this delay to ensure that an ADC
does not start a conversion while the other ADC is still sampling its input.
If the CONT bit is set on both master and slave ADCs, the selected regular channels of both
ADCs are continuously converted.
The software is notified by interrupts when it can read the data at the end of each
conversion event (EOC) on the slave ADC. A slave and master EOC interrupts are
generated (if EOCIE is enabled) and the software can read the ADC_DR of the slave/master
ADC.
Note: It is possible to enable only the EOC interrupt of the slave and read the common data
register (ADCx_CDR). But in this case, the user must ensure that the duration of the
conversions are compatible to ensure that inside the sequence, a master conversion is
always followed by a slave conversion before a new master conversion restarts. It is
recommended to use the MDMA mode.
It is also possible to have the regular data transferred by DMA. In this case, individual DMA
requests on each ADC cannot be used and it is mandatory to use the MDMA mode, as
following:
• Configure DAMDF[1:0]=0b10 or 0b11 (depending on resolution).
• A single DMA channel is used (the one of the master). Configure the DMA master ADC
channel to read the common ADC register (ADCx_CDR).
• A single DMA request is generated each time both master and slave EOC events have
occurred. At that time, the slave ADC converted data is available in the upper half-word
of the ADCx_CDR 32-bit register and the master ADC converted data is available in the
lower half-word of ADCx_CCR register.
• Both EOC flags are cleared when the DMA reads the ADCx_CCR register.

Figure 191. Interleaved mode on 1 channel in continuous conversion mode: dual ADC
mode

MASTER ADC CH1 CH1

SLAVE ADC CH1 CH1

Trigger

End of conversion on master and

3.5 ADCCLK 3.5 ADCCLK slave ADC
cycles cycles
Sampling

Conversion

MSv41030V2

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Figure 192. Interleaved mode on 1 channel in single conversion mode: dual ADC
mode

MASTER ADC CH1 CH1

SLAVE ADC CH1 CH1

Trigger

3.5 ADCCLK End of conversion on 3.5 ADCCLK End of conversion on

cycles master and slave ADC cycles master and slave ADC

Sampling

Conversion

MSv41031V2

If DISCEN=1, each “n” simultaneous conversions (“n” is defined by DISCNUM) of the

regular sequence require a regular trigger event to occur.
In this mode, injected conversions are supported. When injection is done (either on master
or on slave), both the master and the slave regular conversions are aborted and the
sequence is re-started from the master (see Figure 193 below).

Figure 193. Interleaved conversion with injection

Injected trigger Resume (always on master)

CH11

ADC1 (master) CH1 CH1 CH1 CH1 CH1 CH1

ADC2 (slave) CH2 CH2 CH2 CH2 CH2 CH0

read read conversions read read

Legend: CDR CDR aborted CDR CDR

Sampling Conversion
MS34460V1

Alternate trigger mode

This mode is selected by programming bits DUAL[4:0] = 01001.
This mode can be started only on an injected group. The source of external trigger comes
from the injected group multiplexer of the master ADC.
This mode is only possible when selecting hardware triggers: JEXTEN must not be 0x0.

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Injected discontinuous mode disabled (JDISCEN=0 for both ADC)

1. When the 1st trigger occurs, all injected master ADC channels in the group are
converted.
2. When the 2nd trigger occurs, all injected slave ADC channels in the group are
converted.
3. And so on.
A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in
the group have been converted.
A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the
group have been converted.
JEOC interrupts, if enabled, can also be generated after each injected conversion.
If another external trigger occurs after all injected channels in the group have been
converted then the alternate trigger process restarts by converting the injected channels of
the master ADC in the group.

Figure 194. Alternate trigger: injected group of each ADC

JEOC on JEOC on JEOC,JEOS on

1st trigger master ADC master ADC master ADC

MASTER ADC
SLAVE ADC

2nd trigger JEOC on JEOC on JEOC, JEOS

slave ADC slave ADC on slave ADC

JEOC on JEOC on JEOC,JEOS on

3rd trigger master ADC master ADC master ADC

MASTER ADC
SLAVE ADC

4th trigger
JEOC on JEOC on JEOC, JEOS
Sampling slave ADC slave ADC on slave ADC
Conversion
ai16059-m

Note: Regular conversions can be enabled on one or all ADCs. In this case the regular
conversions are independent of each other. A regular conversion is interrupted when the
ADC has to perform an injected conversion. It is resumed when the injected conversion is
finished.
The time interval between 2 trigger events must be greater than or equal to 1 ADC clock
period. The minimum time interval between 2 trigger events that start conversions on the
same ADC is the same as in the single ADC mode.

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Injected discontinuous mode enabled (JDISCEN=1 for both ADC)

If the injected discontinuous mode is enabled for both master and slave ADCs:
• When the 1st trigger occurs, the first injected channel of the master ADC is converted.
• When the 2nd trigger occurs, the first injected channel of the slave ADC is converted.
• And so on.
A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in
the group have been converted.
A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the
group have been converted.
JEOC interrupts, if enabled, can also be generated after each injected conversions.
If another external trigger occurs after all injected channels in the group have been
converted then the alternate trigger process restarts.

Figure 195. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode

1st trigger 3rd trigger 5th trigger 7th trigger

JEOC on JEOC on JEOC on JEOC, JEOS on
master ADC master ADC master ADC master ADC

MASTER ADC
SLAVE ADC

JEOC on JEOC on JEOC on JEOC, JEOS on

master ADC master ADC master ADC master ADC
Sampling 2nd trigger 4th trigger 6th trigger 8th trigger
Conversion
ai16060V2-m

Combined regular/injected simultaneous mode

This mode is selected by programming bits DUAL[4:0] = 00001.
It is possible to interrupt the simultaneous conversion of a regular group to start the
simultaneous conversion of an injected group.
Note: The sequences must be converted with the same length, the N-th conversion in master and
slave mode must be configured with the same sampling time inside a given sequence, or
the interval between triggers has to be longer than the long conversion time of the 2
sequences. If the above conditions are not respected, the ADC with the shortest sequence
may restart while the ADC with the longest sequence is completing the previous
conversions.

Combined regular simultaneous + alternate trigger mode

This mode is selected by programming bits DUAL[4:0]=00010.
It is possible to interrupt the simultaneous conversion of a regular group to start the alternate
trigger conversion of an injected group. Figure 196 shows the behavior of an alternate
trigger interrupting a simultaneous regular conversion.
The injected alternate conversion is immediately started after the injected event. If a regular
conversion is already running, in order to ensure synchronization after the injected

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conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed
synchronously at the end of the injected conversion.
Note: The sequences must be converted with the same length, the N-th conversion in master and
slave mode must be configured with the same sampling time inside a given sequence, or
the interval between triggers has to be longer than the long conversion time of the 2
sequences. If the above conditions are not respected, the ADC with the shortest sequence
may restart while the ADC with the longest sequence is completing the previous
conversions.

Figure 196. Alternate + regular simultaneous

1st trigger

ADC MASTER reg CH1 CH2 CH3 CH3 CH4 CH4 CH5
ADC MASTER inj CH1

ADC SLAVE reg CH4 CH6 CH7 CH7 CH8 CH8 CH9
ADC SLAVE inj CH1
synchronization not lost

2nd trigger
ai16062V2-m

If a trigger occurs during an injected conversion that has interrupted a regular conversion,
the alternate trigger is served. Figure 197 shows the behavior in this case (note that the 6th
trigger is ignored because the associated alternate conversion is not complete).

Figure 197. Case of trigger occurring during injected conversion

1st trigger 3rd trigger 5th trigger

ADC MASTER reg CH1 CH2 CH3 CH3 CH4 CH4 CH5 CH5 CH6
ADC MASTER inj CH14 CH14 CH14

ADC SLAVE reg CH7 CH8 CH9 CH9 CH10 CH10 CH11 CH11 CH12
ADC SLAVE inj CH15 CH15

2nd trigger 4th trigger 6th trigger

(ignored)
ai16063V2

Combined injected simultaneous plus interleaved

This mode is selected by programming bits DUAL[4:0]=00011.
It is possible to interrupt an interleaved conversion with a simultaneous injected event.
In this case the interleaved conversion is interrupted immediately and the simultaneous
injected conversion starts. At the end of the injected sequence the interleaved conversion is
resumed. When the interleaved regular conversion resumes, the first regular conversion
which is performed is alway the master’s one. Figure 198, Figure 199 and Figure 200 show
the behavior using an example.
Caution: In this mode, it is mandatory to use the Common Data Register to read the regular data with
a single read access. On the contrary, master-slave data coherency is not guaranteed.

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Figure 198. Interleaved single channel CH0 with injected sequence CH11, CH12

ADC1 (master) CH0 CH0 CH0 Conversions CH0 CH0 CH0

aborted
ADC2 (slave) CH0 CH0 CH0 CH0 CH0 CH0

read read CH11 CH11 read read

CDR CDR CDR CDR
CH12 CH12

Legend:
Injected trigger Resume
(always restart with the master)
Sampling Conversion
MS34461V1

Figure 199. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first

ADC1 (master) CH1 CH1 CH1 Conversions CH1 CH1 CH1

aborted
ADC2 (slave) CH2 CH2 CH2 CH2 CH2 CH2

read read CH11 CH11 read read

CDR CDR CDR CDR
CH12 CH12

Legend:
Injected trigger Resume
(always restart with the master)
Sampling Conversion
MS34462V1

Figure 200. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first

ADC1 (master) CH1 CH1 CH1 Conversions CH1 CH1 CH1

aborted
ADC2 (slave) CH2 CH2 CH2 CH2 CH2 CH2

read read CH11 CH11 read read

CDR CDR CDR CDR
CH12 CH12

Legend:
Injected trigger Resume
(always restart with the master)
Sampling Conversion
MS34463V2

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DMA requests in dual ADC mode

In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for
the slave) to transfer the data, like in single mode (refer to Figure 201: DMA Requests in
regular simultaneous mode when DAMDF=0b00).

Figure 201. DMA Requests in regular simultaneous mode when DAMDF=0b00

Trigger Trigger

ADC Master regular CH1 CH1

ADC Master EOC

ADC Slave regular CH2 CH2

ADC Slave EOC

DMA request from ADC Master

DMA reads Master DMA reads Mater

ADC_DR ADC_DR

DMA request from ADC Slave

DMA reads Slave DMA reads Slave

ADC_DR ADC_DR
Configuration where each sequence contains only one conversion
MSv31032V2

In simultaneous regular and interleaved modes, it is also possible to save one DMA channel
and transfer both data using a single DMA channel. For this DAMDF bits must be configured
in the ADCx_CCR register:
• DAMDF=0b10, 32-bit format: A single DMA request is generated alternatively when
either the master or slave EOC events have occurred. At that time, the data items are
alternatively available in the ADCx_CDR2 32-bit register. This mode is used in
interleaved mode and in regular simultaneous mode when resolution is above 16-bit.
Example:
Interleaved dual mode: a DMA request is generated each time a new 32-bit data is
available:
1st DMA request: ADCx_CDR2[31:0] = MST_ADC_DR[31:0]
2nd DMA request: ADCx_CDR2[31:0] = SLV_ADC_DR[31:0]
• DAMDF=0b10, 16-bit format: A single DMA request is generated each time both
master and slave EOC events have occurred. At that time, two data items are available
and the 32-bit register ADCx_CDR contains the two half-words representing two ADC-

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converted data items. The slave ADC data take the upper half-word and the master
ADC data take the lower half-word.
This mode is used in interleaved mode and in regular simultaneous mode when
resolution is ranging from 10 to 16-bit. Any value above 16-bit in the master or the
slave converter will be truncated to the least 16 significant bits.
Example:
Interleaved dual mode: a DMA request is generated each time 2 data items are
available:
1st DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] | MST_ADC_DR[15:0]
2nd DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] |
MST_ADC_DR[15:0]

Figure 202. DMA requests in regular simultaneous mode when DAMDF=0b10

Trigger Trigger Trigger Trigger

ADC Master regular CH1 CH1 CH1 CH1

ADC Master EOC

CH2 CH2 CH2 CH2

ADC Slave regular

ADC Slave EOC

DMA request from

ADC Master
DMA request from
ADC Slave

Configuration where each sequence contains only one conversion

MSv31033V3

Figure 203. DMA requests in interleaved mode when DAMDF=0b10

Trigger Trigger Trigger Trigger Trigger

CH1 CH1 CH1 CH1 CH1

ADC Master regular

ADC Master EOC Delay Delay Delay Delay Delay

ADC Slave regular

CH2 CH2 CH2 CH2 CH2
ADC Slave EOC

DMA request from

ADC Master
DMA request from
ADC Slave

Configuration where each sequence contains only one conversion

MSv31034V2

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Note: When using Multiple-ADC mode, the user must take care to configure properly the duration
of the master and slave conversions so that a DMA request is generated and served for
reading both data (master + slave) before a new conversion is available.
• DAMDF=0b11: This mode is similar to the DAMDF=0b10. The only differences are that
on each DMA request (two data items are available), two bytes representing two ADC
converted data items are transferred as a half-word.
This mode is used in interleaved and regular simultaneous mode when the result is 8-
bit. A new DMA request is issued when 4 new 8-bit values are available.
Example:
Interleaved dual mode: a DMA request is generated each time 4 data items are
available (t0, t1,... are corresponding to the consecutive sampling instants)
1st DMA request:
ADCx_CDR[7:0] = MST_ADC_DR[7:0]t0
ADCx_CDR[15:8] = SLV_ADC_DR[7:0]t0
ADCx_CDR[23:16] = MST_ADC_DR[7:0]t1
ADCx_CDR[31:24] = SLV_ADC_DR[7:0]t1

2nd DMA request:

ADCx_CDR[7:0] = MST_ADC_DR[7:0]t2
ADCx_CDR[15:8] = SLV_ADC_DR[7:0]t2
ADCx_CDR[23:16] = MST_ADC_DR[7:0]t3
ADCx_CDR[31:24] = SLV_ADC_DR[7:0]t3

Overrun detection
In dual ADC mode (when DUAL[4:0] is not equal to b00000), if an overrun is detected on
one of the ADCs, the DMA requests are no longer issued to ensure that all the data
transferred to the RAM are valid (this behavior occurs whatever the DAMDF configuration).
It may happen that the EOC bit corresponding to one ADC remains set because the data
register of this ADC contains valid data.

DMA one shot mode/ DMA circular mode when Multiple-ADC mode is selected
When DAMDF mode is selected (0b10 or 0b11), bit DMNGT[1:0]=0b10 in the master ADC’s
ADCx_CCR register must also be configured to select between DMA one shot mode and
circular mode, as explained in section Section : Managing conversions using the DMA.

Stopping the conversions in dual ADC modes

The user must set the control bits ADSTP/JADSTP of the master ADC to stop the
conversions of both ADC in dual ADC mode. The other ADSTP control bit of the slave ADC
has no effect in dual ADC mode.
Once both ADC are effectively stopped, the bits ADSTART/JADSTART of the master and
slave ADCs are both cleared by hardware.

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DFSDM mode in dual ADC mode interleaved mode

In dual ADC interleaved modes, the ADC conversion results can be transferred directly to
the Digital Filter for Sigma Delta Modulators (DFSDM).
This mode is enabled by setting the bits DMNGT[1:0] = 0b10 in the master ADC’s
ADC_CFGR register.
The ADC transfers alternatively the 16 least significant bits of the regular data register from
the master and the slave converter to a single channel of the DFSDM.
The data format must be 16-bit signed:
ADC_DR[31:16] = 0x0000
ADC_DR[15] = sign
ADC_DR[14:0] = data
Any value above 16-bit signed format in any converter will be truncated.

DFSDM mode in dual ADC simultaneous mode

The dual mode is not required to use DFSDM in dual ADC simultaneous mode since
conversion data will be treated by each individual channel. Single mode with same trigger
source results in simultaneous conversion with DFSDM interface.

25.4.33 Temperature sensor

The temperature sensor can measure the junction temperature (TJ) of the device in the –40
to 125 °C temperature range.
The temperature sensor is internally connected to an ADC internal channel which is used to
convert the sensor’s output voltage to a digital value (refer to Table ADC interconnection in
Section 25.4.2: ADC pins and internal signals). The sampling time for the temperature
sensor’s analog pin must be greater than the stabilization time specified in the product
datasheet.
When not in use, the sensor can be put in power-down mode.
Figure 204 shows the block diagram of the temperature sensor.

Figure 204. Temperature sensor channel block diagram

TSEN control bit

Address/data bus

converted
data

ADCx

Temperature VSENSE
sensor ADC input

MSv41034V6

Note: The TSEN bit must be set to enable the conversion of the corresponding ADC internal
channel (temperature sensor, VSENSE).

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Reading the temperature

To use the sensor:
1. Select the ADC input channels (with the appropriate sampling time).
2. Program with the appropriate sampling time (refer to electrical characteristics section of
the device datasheet).
3. Set the TSEN bit in the ADCx_CCR register to wake up the temperature sensor from
power-down mode.
4. Start the ADC conversion.
5. Read the resulting VSENSE data in the ADC data register.
6. Calculate the actual temperature using the following formula:

TS_CAL2_TEMP – TS_CAL1_TEMP
Temperature ( in °C ) = -------------------------------------------------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + TS_CAL1_TEMP
TS_CAL2 – TS_CAL1

Where:
• TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP
• TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP
• TS_DATA is the actual temperature sensor output value converted by ADC
Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2
calibration points.
Note: The sensor has a startup time after waking from power-down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADEN and SENSEEN bits should be set at the same time.

25.4.34 VBAT supply monitoring

The VBATEN bit of the ADCx_CCR register is used to switch to the battery voltage. As the
VBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the
VBAT pin is internally connected to a bridge divider by 4. This bridge is automatically enabled
when VBATEN is set, to connect VBAT/4 to an ADC input channel (refer to Table ADC
interconnection in Section 25.4.2: ADC pins and internal signals).
As a consequence, the converted digital value is one fourth of the VBAT voltage. To prevent
any unwanted consumption on the battery, it is recommended to enable the bridge divider
only when needed, for ADC conversion.
Refer to the electrical characteristics of the device datasheet for the sampling time value to
be applied when converting the VBAT/4 voltage.
Figure 205 shows the block diagram of the VBAT sensing feature.

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Figure 205. VBAT channel block diagram

VBAT

VBATEN control bit

Address/data bus
ADCx

VBAT/4
ADC input

MSv41032V4

Note: The VBATEN bit in ADCx_CCR must be configured to enable the conversion of the
corresponding ADC internal channel.

25.4.35 Monitoring the internal voltage reference

The internal voltage reference can be monitored to have a reference point for evaluating the
ADC VREF+ voltage level.
The internal voltage reference is internally connected to an ADC input channel (refer to
Table ADC interconnection in Section 25.4.2: ADC pins and internal signals).
The sampling time for this channel must be greater than the stabilization time specified in
the product datasheet.
Figure 205 shows the block diagram of the VREFINT sensing feature.

Figure 206. VREFINT channel block diagram

VREFEN control bit ADCx

Internal power
block
VREFINT
ADC input

MSv41033V5

Note: The VREFEN bit of the ADCx_CCR register must be configured to enable the conversion of
the corresponding ADC internal channel (VREFINT).

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Calculating the actual VDDA voltage using the internal reference voltage
The power supply voltage applied to the device may be subject to variations or not precisely
known. When VDDA is connected to VREF+, it is possible to compute the actual VDDA voltage
using the embedded internal reference voltage (VREFINT). VREFINT and its calibration data
acquired by the ADC during the manufacturing process at VDDA = 3.3 V can be used to
evaluate the actual VDDA voltage level.
The following formula gives the actual VDDA voltage supplying the device:
VREF+ = 3.3 V x VREFINT_CAL / VREFINT_DATA
Where:
• VREFINT_CAL is the VREFINT calibration value
• VREFINT_DATA is the actual VREFINT output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between VREF+ and
the voltage applied on the converted channel.
For most applications VDDA value is unknown and ADC converted values are right-aligned.
In this case, it is necessary to convert this ratio into a voltage independent from VDDA:
V REF+
V CHANNELx = ------------------------------------- × ADC_DATA
FULL_SCALE

By replacing VREF+ by the formula provided above, the absolute voltage value is given by
the following formula
V × VREFINT_CAL × ADC_DATA-
V CHANNELx = 3.3
----------------------------------------------------------------------------------------------------
VREFINT_DATA × FULL_SCALE

For applications where VDDA is known and ADC converted values are right-aligned, the
absolute voltage value can be obtained by using the following formula:
V DDA
V CHANNELx = ------------------------------------- × ADC_DATA
FULL_SCALE

Where:
– VREFINT_CAL is the VREFINT calibration value
– ADC_DATA is the value measured by the ADC on channel x (right-aligned)
– VREFINT_DATA is the actual VREFINT output value converted by the ADC
– FULL_SCALE is the maximum digital value of the ADC output. For example with
16-bit resolution, it will be 216 - 1 = 65535 or with 8-bit resolution, 28 - 1 = 255.
Note: If ADC measurements are done using an output format other than 16-bit right-aligned, all
the parameters must first be converted to a compatible format before the calculation is
done.

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25.5 ADC interrupts

For each ADC, an interrupt can be generated:
• After ADC power-up, when the ADC is ready (flag ADRDY)
• On the end of any conversion for regular groups (flag EOC)
• On the end of a sequence of conversion for regular groups (flag EOS)
• On the end of any conversion for injected groups (flag JEOC)
• On the end of a sequence of conversion for injected groups (flag JEOS)
• When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3)
• When the end of sampling phase occurs (flag EOSMP)
• When the data overrun occurs (OVR flag)
• When the injected sequence context queue overflows (flag JQOVF)
Separate interrupt enable bits are available for flexibility.

Table 219. ADC interrupts per each ADC

Interrupt event Event flag Enable control bit

ADC ready ADRDY ADRDYIE

End of conversion of a regular group EOC EOCIE
End of sequence of conversions of a regular group EOS EOSIE
End of conversion of a injected group JEOC JEOCIE
End of sequence of conversions of an injected group JEOS JEOSIE
Analog watchdog 1 status bit is set AWD1 AWD1IE
Analog watchdog 2 status bit is set AWD2 AWD2IE
Analog watchdog 3 status bit is set AWD3 AWD3IE
End of sampling phase EOSMP EOSMPIE
Overrun OVR OVRIE
Injected context queue overflows JQOVF JQOVFIE

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25.6 ADC registers (for each ADC)

Refer to Section 1.2 on page 101 for a list of abbreviations used in register descriptions.

25.6.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDOR
Res. Res. Res. Res. JQOVF AWD3 AWD2 AWD1 JEOS JEOC OVR EOS EOC EOSMP ADRDY
DY
r rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 LDORDY: ADC LDO output voltage ready bit
This bit is set and cleared by hardware. It indicates that the ADC internal LDO output is ready and
that the ADC can be enabled or calibrated.
0: ADC LDO voltage regulator disabled
1: ADC LDO voltage regulator enabled
Note: Refer to Section 25.3: ADC implementation for the availability of the LDO regulator.
Bit 11 Reserved, must be kept at reset value.
Bit 10 JQOVF: Injected context queue overflow
This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared
by software writing 1 to it. Refer to Section 25.4.22: Queue of context for injected conversions for
more information.
0: No injected context queue overflow occurred (or the flag event was already acknowledged and
cleared by software)
1: Injected context queue overflow has occurred
Bit 9 AWD3: Analog watchdog 3 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it.
0: No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 3 event occurred
Bit 8 AWD2: Analog watchdog 2 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it.
0: No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 2 event occurred

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Bit 7 AWD1: Analog watchdog 1 flag

This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it.
0: No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 1 event occurred
Bit 6 JEOS: Injected channel end of sequence flag
This bit is set by hardware at the end of the conversions of all injected channels in the group. It is
cleared by software writing 1 to it.
0: Injected conversion sequence not complete (or the flag event was already acknowledged and
cleared by software)
1: Injected conversions complete
Bit 5 JEOC: Injected channel end of conversion flag
This bit is set by hardware at the end of each injected conversion of a channel when a new data is
available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by
reading the corresponding ADC_JDRy register
0: Injected channel conversion not complete (or the flag event was already acknowledged and
cleared by software)
1: Injected channel conversion complete
Bit 4 OVR: ADC overrun
This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new
conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to
it.
0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun has occurred
Bit 3 EOS: End of regular sequence flag
This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is
cleared by software writing 1 to it.
0: Regular Conversions sequence not complete (or the flag event was already acknowledged and
cleared by software)
1: Regular Conversions sequence complete

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Bit 2 EOC: End of conversion flag

This bit is set by hardware at the end of each regular conversion of a channel when a new data is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register
0: Regular channel conversion not complete (or the flag event was already acknowledged and
cleared by software)
1: Regular channel conversion complete
Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion of any channel (only for regular channels), at the
end of the sampling phase.
0: not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC
reaches a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion

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25.6.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF AWD3 AWD2 AWD1 EOSMP ADRDY
Res. Res. Res. Res. Res. JEOSIE JEOCIE OVRIE EOSIE EOCIE
IE IE IE IE IE IE
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVFIE: Injected context queue overflow interrupt enable
This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow
interrupt.
0: Injected Context Queue Overflow interrupt disabled
1: Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit
is set.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
Bit 9 AWD3IE: Analog watchdog 3 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.
0: Analog watchdog 3 interrupt disabled
1: Analog watchdog 3 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 8 AWD2IE: Analog watchdog 2 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.
0: Analog watchdog 2 interrupt disabled
1: Analog watchdog 2 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 7 AWD1IE: Analog watchdog 1 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt.
0: Analog watchdog 1 interrupt disabled
1: Analog watchdog 1 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 6 JEOSIE: End of injected sequence of conversions interrupt enable
This bit is set and cleared by software to enable/disable the end of injected sequence of conversions
interrupt.
0: JEOS interrupt disabled
1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).

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Bit 5 JEOCIE: End of injected conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt.
0: JEOC interrupt disabled.
1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
Note: The software is allowed to write this bit only when JADSTART is cleared to 0 (no injected
conversion is ongoing).
Bit 4 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular
conversion.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 3 EOSIE: End of regular sequence of conversions interrupt enable
This bit is set and cleared by software to enable/disable the end of regular sequence of conversions
interrupt.
0: EOS interrupt disabled
1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 2 EOCIE: End of regular conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt.
0: EOC interrupt disabled.
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable for regular conversions
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for
regular conversions.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

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25.6.3 ADC control register (ADC_CR)

Address offset: 0x08
Reset value: 0x2000 0000

Devices revision Y

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINCA LINCA LINCA
ADCA ADCA DEEP ADVREG LINCAL LINCAL LINCAL ADCAL
LRDY LRDY LRDY Res. Res. Res. Res. Res.
L LDIF PWD EN RDYW3 RDYW2 RDYW1 LIN
W6 W5 W4
rs rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADST ADSTA
Res. Res. Res. Res. Res. Res. Res. BOOST Res. Res. JADSTP ADSTP ADDIS ADEN
ART RT
rw rs rs rs rs rs rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to
determine if this calibration applies for single-ended or differential inputs mode.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.
Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN=0.
The software is allowed to update the calibration factor by writing ADC_CALFACT only when
ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)
Bit 30 ADCALDIF: Differential mode for calibration
This bit is set and cleared by software to configure the single-ended or differential inputs mode for
the calibration.
0: Writing ADCAL will launch a calibration in Single-ended inputs Mode.
1: Writing ADCAL will launch a calibration in Differential inputs Mode.
Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating
(ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 29 DEEPPWD: Deep-power-down enable
This bit is set and cleared by software to put the ADC in deep-power-down mode.
0: ADC not in deep-power down
1: ADC in deep-power-down (default reset state)
Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL=0,
JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 28 ADVREGEN: ADC voltage regulator enable
This bits is set by software to enable the ADC voltage regulator.
Before performing any operation such as launching a calibration or enabling the ADC, the ADC
voltage regulator must first be enabled and the software must wait for the regulator start-up time.
0: ADC Voltage regulator disabled
1: ADC Voltage regulator enabled.
For more details about the ADC voltage regulator enable and disable sequences, refer to
Section 25.4.6: ADC deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN).
The software can program this bitfield only when the ADC is disabled (ADCAL=0, JADSTART=0,
ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

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Bit 27 LINCALRDYW6: Linearity calibration ready Word 6

This control / status bit allows to read/write the 6th linearity calibration factor.
When the linearity calibration is complete, this bit is set. A bit clear will launch the transfer of the
linearity factor 6 into the LINCALFACT[29:0] of the ADC_CALFACT2 register. The bit will be reset by
hardware when the ADC_CALFACT2 register can be read (software must poll the bit until it is
cleared).
When the LINCALRDYW6 bit is reset, a new linearity factor 6 value can be written into the
LINCALFACT[29:0] of the ADC_CALFACT2 register. A bit set will launch the linearity factor 6 update
and the bit will be effectively set by hardware once the update will be done (software must poll the bit
until it is set to indicate the write is effective).
Note: ADC_CALFACT2[29:10] contains 0. ADC_CALFACT2[9:0] corresponds linearity correction
factor bits[159:150].
The software is allowed to toggle this bit only if the LINCALRDYW5, LINCALRDYW4,
LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged, see chapter
25.4.8: Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT) for details.
The software is allowed to update the linearity calibration factor by writing LINCALRDYWx only
when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is
ongoing)
Bit 26 LINCALRDYW5: Linearity calibration ready Word 5
Refer to LINCALRDYW6 description.
Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[149:120].
The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5,
LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged.
Bit 25 LINCALRDYW4: Linearity calibration ready Word 4
Refer to LINCALRDYW6 description.
Note: ADC_CALFACT2[29:0] correspond linearity correction factor bits[119:90].
The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5,
LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged.
Bit 24 LINCALRDYW3: Linearity calibration ready Word 3
Refer to LINCALRDYW6 description.
Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[89:60].
The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5,
LINCALRDYW4, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged.
Bit 23 LINCALRDYW2: Linearity calibration ready Word 2
Refer to LINCALRDYW6 description.
Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[59:30].
The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5,
LINCALRDYW4, LINCALRDYW3 and LINCALRDYW1 bits are left unchanged.
Bit 22 LINCALRDYW1: Linearity calibration ready Word 1
Refer to LINCALRDYW6 description.
Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[29:0].
The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5,
LINCALRDYW4, LINCALRDYW3 and LINCALRDYW2 bits are left unchanged.
Bits 21:17 Reserved, must be kept at reset value.

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Bit 16 ADCALLIN: Linearity calibration

This bit is set and cleared by software to enable the Linearity calibration.
0: Writing ADCAL will launch a calibration without the Linearity calibration.
1: Writing ADCAL will launch a calibration with he Linearity calibration.
Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating
(ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 BOOST: Boost mode control
This bit is set and cleared by software to enable/disable the Boost mode.
0: Boost mode off. Used when ADC clock < 20 MHz to save power at lower clock frequency.
1: Boost mode on. Must be used when ADC clock > 20 MHz.
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the bit
BOOST of the slave ADC is no more writable and its content must be equal to the master ADC
BOOST bit.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 JADSTP: ADC stop of injected conversion command
This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC injected
sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected
conversions (JADSTART command).
0: No ADC stop injected conversion command ongoing
1: Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in
progress.
Note: The software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is
enabled and eventually converting an injected conversion and there is no pending request to
disable the ADC).
In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (do not use JADSTP)
Bit 4 ADSTP: ADC stop of regular conversion command
This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC regular
sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular
conversions (ADSTART command).
0: No ADC stop regular conversion command ongoing
1: Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in
progress.
Note: The software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled
and eventually converting a regular conversion and there is no pending request to disable the
ADC).
In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (do not use JADSTP).
In dual ADC regular simultaneous mode and interleaved mode, the bit ADSTP of the master
ADC must be used to stop regular conversions. The other ADSTP bit is inactive.

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Bit 3 JADSTART: ADC start of injected conversion

This bit is set by software to start ADC conversion of injected channels. Depending on the
configuration bits JEXTEN, a conversion will start immediately (software trigger configuration) or
once an injected hardware trigger event occurs (hardware trigger configuration).
It is cleared by hardware:
– in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the
assertion of the End of Injected Conversion Sequence (JEOS) flag.
– in all cases: after the execution of the JADSTP command, at the same time that JADSTP is
cleared by hardware.
0: No ADC injected conversion is ongoing.
1: Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually
converting an injected channel.
Note: The software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled
and there is no pending request to disable the ADC).
In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting
bit ADSTART (JADSTART must be kept cleared)

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RM0433 Analog-to-digital converters (ADC)

Bit 2 ADSTART: ADC start of regular conversion

This bit is set by software to start ADC conversion of regular channels. Depending on the
configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once
a regular hardware trigger event occurs (hardware trigger configuration).
It is cleared by hardware:
– in single conversion mode (CONT=0, DISCEN=0) when software trigger is selected
(EXTEN=0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag.
– In discontinuous conversion mode (CONT=0, DISCEN=1), when the software trigger is
selected (EXTEN=0x0): at the end of conversion (EOC) flag.
– in all other cases: after the execution of the ADSTP command, at the same time that
ADSTP is cleared by hardware.
0: No ADC regular conversion is ongoing.
1: Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually
converting a regular channel.
Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled
and there is no pending request to disable the ADC)
In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting
bit ADSTART (JADSTART must be kept cleared)
Bit 1 ADDIS: ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state
(OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at
this time).
0: no ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: The software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and
JADSTART=0 (which ensures that no conversion is ongoing)
Bit 0 ADEN: ADC enable control
This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the
flag ADRDY has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for bit ADVREGEN
which must be 1 (and the software must have wait for the startup time of the voltage regulator)

Devices revision V

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINCA LINCA LINCA
ADCA ADCA DEEP ADVREG LINCAL LINCAL LINCAL ADCAL
LRDY LRDY LRDY Res. Res. Res. Res. Res.
L LDIF PWD EN RDYW3 RDYW2 RDYW1 LIN
W6 W5 W4
rs rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADST ADSTA
Res. Res. Res. Res. Res. Res. BOOST[1:0] Res. Res. JADSTP ADSTP ADDIS ADEN
ART RT
rw rw rs rs rs rs rs rs

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Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to
determine if this calibration applies for single-ended or differential inputs mode.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.
Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN=0.
The software is allowed to update the calibration factor by writing ADC_CALFACT only when
ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)
Bit 30 ADCALDIF: Differential mode for calibration
This bit is set and cleared by software to configure the single-ended or differential inputs mode for
the calibration.
0: Writing ADCAL will launch a calibration in Single-ended inputs Mode.
1: Writing ADCAL will launch a calibration in Differential inputs Mode.
Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating
(ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 29 DEEPPWD: Deep-power-down enable
This bit is set and cleared by software to put the ADC in deep-power-down mode.
0: ADC not in deep-power down
1: ADC in deep-power-down (default reset state)
Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL=0,
JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 28 ADVREGEN: ADC voltage regulator enable
This bits is set by software to enable the ADC voltage regulator.
Before performing any operation such as launching a calibration or enabling the ADC, the ADC
voltage regulator must first be enabled and the software must wait for the regulator start-up time.
0: ADC Voltage regulator disabled
1: ADC Voltage regulator enabled.
For more details about the ADC voltage regulator enable and disable sequences, refer to
Section 25.4.6: ADC deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN).
The software can program this bitfield only when the ADC is disabled (ADCAL=0, JADSTART=0,
ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 27 LINCALRDYW6: Linearity calibration ready Word 6
This control / status bit allows to read/write the 6th linearity calibration factor.
When the linearity calibration is complete, this bit is set. A bit clear will launch the transfer of the
linearity factor 6 into the LINCALFACT[29:0] of the ADC_CALFACT2 register. The bit will be reset by
hardware when the ADC_CALFACT2 register can be read (software must poll the bit until it is
cleared).
When the LINCALRDYW6 bit is reset, a new linearity factor 6 value can be written into the
LINCALFACT[29:0] of the ADC_CALFACT2 register. A bit set will launch the linearity factor 6 update
and the bit will be effectively set by hardware once the update will be done (software must poll the bit
until it is set to indicate the write is effective).
Note: ADC_CALFACT2[29:10] contains 0. ADC_CALFACT2[9:0] corresponds linearity correction
factor bits[159:150].
The software is allowed to toggle this bit only if the LINCALRDYW5, LINCALRDYW4,
LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged, see chapter
25.4.8: Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT) for details.
The software is allowed to update the linearity calibration factor by writing LINCALRDYWx only
when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is
ongoing)

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RM0433 Analog-to-digital converters (ADC)

Bit 26 LINCALRDYW5: Linearity calibration ready Word 5

Refer to LINCALRDYW6 description.
Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[149:120].
The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5,
LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged.
Bit 25 LINCALRDYW4: Linearity calibration ready Word 4
Refer to LINCALRDYW6 description.
Note: ADC_CALFACT2[29:0] correspond linearity correction factor bits[119:90].
The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5,
LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged.
Bit 24 LINCALRDYW3: Linearity calibration ready Word 3
Refer to LINCALRDYW6 description.
Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[89:60].
The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5,
LINCALRDYW4, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged.
Bit 23 LINCALRDYW2: Linearity calibration ready Word 2
Refer to LINCALRDYW6 description.
Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[59:30].
The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5,
LINCALRDYW4, LINCALRDYW3 and LINCALRDYW1 bits are left unchanged.
Bit 22 LINCALRDYW1: Linearity calibration ready Word 1
Refer to LINCALRDYW6 description.
Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[29:0].
The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5,
LINCALRDYW4, LINCALRDYW3 and LINCALRDYW2 bits are left unchanged.
Bits 21:17 Reserved, must be kept at reset value.
Bit 16 ADCALLIN: Linearity calibration
This bit is set and cleared by software to enable the Linearity calibration.
0: Writing ADCAL will launch a calibration without the Linearity calibration.
1: Writing ADCAL will launch a calibration with he Linearity calibration.
Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating
(ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 BOOST[1:0]: Boost mode control
This bitfield is set and cleared by software to enable/disable the Boost mode.
00: used when ADC clock ≤ 6.25 MHz
01: used when 6.25 MHz < ADC clock frequency ≤ 12.5 MHz
10: used when 12.5 MHz < ADC clock ≤ 25.0 MHz
11: used when 25.0 MHz < ADC clock ≤ 50.0 MHz
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the
BOOST bitfield of the slave ADC is no more writable and its content must be equal to the
master ADC BOOST bitfield.
Bits 7:6 Reserved, must be kept at reset value.

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Bit 5 JADSTP: ADC stop of injected conversion command

This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC injected
sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected
conversions (JADSTART command).
0: No ADC stop injected conversion command ongoing
1: Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in
progress.
Note: The software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is
enabled and eventually converting an injected conversion and there is no pending request to
disable the ADC).
In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (do not use JADSTP)
Bit 4 ADSTP: ADC stop of regular conversion command
This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC regular
sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular
conversions (ADSTART command).
0: No ADC stop regular conversion command ongoing
1: Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in
progress.
Note: The software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled
and eventually converting a regular conversion and there is no pending request to disable the
ADC).
In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (do not use JADSTP).
In dual ADC regular simultaneous mode and interleaved mode, the bit ADSTP of the master
ADC must be used to stop regular conversions. The other ADSTP bit is inactive.
Bit 3 JADSTART: ADC start of injected conversion
This bit is set by software to start ADC conversion of injected channels. Depending on the
configuration bits JEXTEN, a conversion will start immediately (software trigger configuration) or
once an injected hardware trigger event occurs (hardware trigger configuration).
It is cleared by hardware:
– in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the
assertion of the End of Injected Conversion Sequence (JEOS) flag.
– in all cases: after the execution of the JADSTP command, at the same time that JADSTP is
cleared by hardware.
0: No ADC injected conversion is ongoing.
1: Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually
converting an injected channel.
Note: The software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled
and there is no pending request to disable the ADC).
In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting
bit ADSTART (JADSTART must be kept cleared)

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RM0433 Analog-to-digital converters (ADC)

Bit 2 ADSTART: ADC start of regular conversion

This bit is set by software to start ADC conversion of regular channels. Depending on the
configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once
a regular hardware trigger event occurs (hardware trigger configuration).
It is cleared by hardware:
– in single conversion mode (CONT=0, DISCEN=0) when software trigger is selected
(EXTEN=0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag.
– In discontinuous conversion mode (CONT=0, DISCEN=1), when the software trigger is
selected (EXTEN=0x0): at the end of conversion (EOC) flag.
– in all other cases: after the execution of the ADSTP command, at the same time that
ADSTP is cleared by hardware.
0: No ADC regular conversion is ongoing.
1: Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually
converting a regular channel.
Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled
and there is no pending request to disable the ADC)
In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting
bit ADSTART (JADSTART must be kept cleared)
Bit 1 ADDIS: ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state
(OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at
this time).
0: no ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: The software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and
JADSTART=0 (which ensures that no conversion is ongoing)
Bit 0 ADEN: ADC enable control
This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the
flag ADRDY has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for bit ADVREGEN
which must be 1 (and the software must have wait for the startup time of the voltage regulator)

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25.6.4 ADC configuration register (ADC_CFGR)

Address offset: 0x0C
Reset value: 0x8000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JAWD1 AWD1E AWD1S JDISCE DISCE
JQDIS AWD1CH[4:0] JAUTO JQM DISCNUM[2:0]
EN N GL N N
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUT OVR
Res. CONT EXTEN[1:0] EXTSEL[4:0] RES[2:0] DMNGT[1:0]
DLY MOD
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 JQDIS: Injected Queue disable

These bits are set and cleared by software to disable the Injected Queue mechanism:
0: Injected Queue enabled
1: Injected Queue disabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no regular nor injected conversion is ongoing).
A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is
cleared.
Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection
These bits are set and cleared by software. They select the input channel to be guarded by the
analog watchdog.
00000: ADC analog input channel-0 monitored by AWD1
00001: ADC analog input channel-1 monitored by AWD1
.....
10010: ADC analog input channel-19 monitored by AWD1
others: Reserved, must not be used
Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers.
The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 25 JAUTO: Automatic injected group conversion
This bit is set and cleared by software to enable/disable automatic injected group conversion after
regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no regular nor injected conversion is ongoing).
When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit
JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the
master ADC.
Bit 24 JAWD1EN: Analog watchdog 1 enable on injected channels
This bit is set and cleared by software
0: Analog watchdog 1 disabled on injected channels
1: Analog watchdog 1 enabled on injected channels
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).

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RM0433 Analog-to-digital converters (ADC)

Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels

This bit is set and cleared by software
0: Analog watchdog 1 disabled on regular channels
1: Analog watchdog 1 enabled on regular channels
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 22 AWD1SGL: Enable the watchdog 1 on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel identified by
the AWD1CH[4:0] bits or on all the channels
0: Analog watchdog 1 enabled on all channels
1: Analog watchdog 1 enabled on a single channel
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 21 JQM: JSQR queue mode
This bit is set and cleared by software.
It defines how an empty Queue is managed.
0: JSQR Mode 0: The Queue is never empty and maintains the last written configuration into JSQR.
1: JSQR Mode 1: The Queue can be empty and when this occurs, the software and hardware
triggers of the injected sequence are both internally disabled just after the completion of the last valid
injected sequence.
Refer to Section 25.4.22: Queue of context for injected conversions for more information.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit
JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master
ADC.
Bit 20 JDISCEN: Discontinuous mode on injected channels
This bit is set and cleared by software to enable/disable discontinuous mode on the injected
channels of a group.
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the
bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the bit
JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of
the master ADC.
Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count
These bits are written by software to define the number of regular channels to be converted in
discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
...
111: 8 channels
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bits
DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits
DISCNUM[2:0] of the master ADC.

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Bit 16 DISCEN: Discontinuous mode for regular channels

This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels.
0: Discontinuous mode for regular channels disabled
1: Discontinuous mode for regular channels enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both DISCEN=1 and CONT=1.
It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the
bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit
DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the
master ADC.
Bit 15 Reserved, must be kept at reset value.
Bit 14 AUTDLY: Delayed conversion mode
This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode..
0: Auto-delayed conversion mode off
1: Auto-delayed conversion mode on
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit
AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the
master ADC.
Bit 13 CONT: Single / continuous conversion mode for regular conversions
This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both DISCEN=1 and CONT=1.
The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit
CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the
master ADC.
Bit 12 OVRMOD: Overrun Mode
This bit is set and cleared by software and configure the way data overrun is managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection for regular channels
These bits are set and cleared by software to select the external trigger polarity and enable the
trigger of a regular group.
00: Hardware trigger detection disabled (conversions can be launched by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).

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RM0433 Analog-to-digital converters (ADC)

Bits 9:5 EXTSEL[4:0]: External trigger selection for regular group

These bits select the external event used to trigger the start of conversion of a regular group:
00000: Event 0
00001: Event 1
00010: Event 2
00011: Event 3
00100: Event 4
00101: Event 5
00110: Event 6
00111: Event 7
...
11111: Event 31
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bits 4:2 RES[2:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
000: 16 bits
001: 14 bits (for devices revision Y), 14 bits in legacy mode (for devices revision V, not optimized
power consumption)
101: 14 bits (for devices revision V)
010: 12 bits (for devices revision Y), 12 bits in legacy mode (for devices revision V, not optimized
power consumption)
110: 12 bits (for devices revision V)
011: 10 bits
100: 8 bits (for devices revision Y)
111: 8 bits (for devices revision V)
Others: Reserved, must not be used.
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 1:0 DMNGT[1:0]: Data Management configuration
This bit is set and cleared by software to select how ADC interface output data are managed.
00: Regular conversion data stored in DR only
01: DMA One Shot Mode selected
10: DFSDM mode selected
11: DMA Circular Mode selected
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
In dual-ADC modes, this bit is not relevant and replaced by control bit DAMDF of the
ADCx_CCR register.

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25.6.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LSHIFT[3:0] Res. Res. OSVR[9:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSHIF RSHIF RSHIF RSHIF
Res. ROVSM TROVS OVSS[3:0] Res. Res. Res. JOVSE ROVSE
T4 T3 T2 T1
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 LSHIFT[3:0]: Left shift factor

This bitfield is set and cleared by software to define the left shifting applied to the final result with or
without oversampling.
0000: No left shift
0001: Shift left 1-bit
0010: Shift left 2-bits
0011: Shift left 3-bits
0100: Shift left 4-bits
0101: Shift left 5-bits
0110: Shift left 6-bits
0111: Shift left 7-bits
1000: Shift left 8-bits
1001: Shift left 9-bits
1010: Shift left 10-bits
1011: Shift left 11-bits
1100: Shift left 12-bits
1101: Shift left 13-bits
1110: Shift left 14-bits
1111: Shift left 15-bits
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 27:26 Reserved, must be kept at reset value.
Bits 25:16 OSVR[9:0]: Oversampling ratio
This bitfield is set and cleared by software to define the oversampling ratio.
0: 1x (no oversampling)
1: 2x
2: 3x
...
1023: 1024x
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 15 Reserved, must be kept at reset value.
Bit 14 RSHIFT4: Right-shift data after Offset 4 correction
Refer to RSHIFT1 description.

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RM0433 Analog-to-digital converters (ADC)

Bit 13 RSHIFT3: Right-shift data after Offset 3 correction

Refer to RSHIFT1 description
Bit 12 RSHIFT2: Right-shift data after Offset 2 correction
Refer to RSHIFT1 description
Bit 11 RSHIFT1: Right-shift data after Offset 1 correction
This bitfield is set and cleared by software to right-shift 1-bit data after offset1 correction. This bit can
only be used for 8-bit and 16-bit data format (see Section : Data register, data alignment and offset
(ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details).
0: Right-shifting disabled
1: Data is right-shifted 1-bit.
Bit 10 ROVSM: Regular Oversampling mode
This bit is set and cleared by software to select the regular oversampling mode.
0: Continued mode: When injected conversions are triggered, the oversampling is temporary
stopped and continued after the injection sequence (oversampling buffer is maintained during
injected sequence)
1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted
and resumed from start after the injection sequence (oversampling buffer is zeroed by injected
sequence start)
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 9 TROVS: Triggered Regular Oversampling
This bit is set and cleared by software to enable triggered oversampling
0: All oversampled conversions for a channel are done consecutively following a trigger
1: Each oversampled conversion for a channel needs a new trigger
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 8:5 OVSS[3:0]: Oversampling right shift
This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling
result.
0000: No right shift
0001: Shift right 1-bit
0010: Shift right 2-bits
0011: Shift right 3-bits
0100: Shift right 4-bits
0101: Shift right 5-bits
0110: Shift right 6-bits
0111: Shift right 7-bits
1000: Shift right 8-bits
1001: Shift right 9-bits
1010: Shift right 10-bits
1011: Shift right 11-bits
Others: Reserved, must not be used.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).

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Bits 4:2 Reserved, must be kept at reset value.

Bit 1 JOVSE: Injected Oversampling Enable
This bit is set and cleared by software to enable injected oversampling.
0: Injected Oversampling disabled
1: Injected Oversampling enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing)
Bit 0 ROVSE: Regular Oversampling Enable
This bit is set and cleared by software to enable regular oversampling.
0: Regular Oversampling disabled
1: Regular Oversampling enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing)

25.6.6 ADC sample time register 1 (ADC_SMPR1)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5[0] SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:0 SMPx[2:0]: Channel x sampling time selection (x = 9 to 0)
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
000: 1.5 ADC clock cycles
001: 2.5 ADC clock cycles
010: 8.5 ADC clock cycles
011: 16.5 ADC clock cycles
100: 32.5 ADC clock cycles
101: 64.5 ADC clock cycles
110: 387.5 ADC clock cycles
111: 810.5 ADC clock cycles
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).

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RM0433 Analog-to-digital converters (ADC)

25.6.7 ADC sample time register 2 (ADC_SMPR2)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. SMP19[2:0] SMP18[2:0] SMP17[2:0] SMP16[2:0] SMP15[2:1]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15[0] SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:0 SMPx[2:0]: Channel x sampling time selection (x = 19 to 10)
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
000: 1.5 ADC clock cycles
001: 2.5 ADC clock cycles
010: 8.5 ADC clock cycles
011: 16.5 ADC clock cycles
100: 32.5 ADC clock cycles
101: 64.5 ADC clock cycles
110: 387.5 ADC clock cycles
111: 810.5 ADC clock cycles
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).

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25.6.8 ADC channel preselection register (ADC_PCSEL)

Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PCSEL1 PCSEL1 PCSEL1 PCSEL1

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
9 8 7 6

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCSE PCSE PCSE PCSE PCSE PCSE PCSEL PCSEL PCSEL PCSEL PCSEL PCSEL
PCSEL3 PCSEL2 PCSEL1 PCSEL0
L15 L14 L13 L12 L11 L10 9 8 7 6 5 4

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 PCSEL[19:0] :Channel x (VINP[i]) pre selection (x = 0 to 19)
These bits are written by software to pre select the input channel at IO instance to be
converted.
0: Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with
this channel shows wrong result.
1: Input Channel x (Vinp x) is pre selected for conversion
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).

25.6.9 ADC watchdog threshold register 1 (ADC_LTR1)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. LTR1[25:16]

rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LTR1[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 LTR1[25:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 1.
Refer to Section 25.4.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

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RM0433 Analog-to-digital converters (ADC)

25.6.10 ADC watchdog threshold register 1 (ADC_HTR1)

Address offset: 0x24
Reset value: 0x03FF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. HTR1[25:16]

rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HTR1[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 HTR1[25:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 1.
Refer to Section 25.4.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

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25.6.11 ADC regular sequence register 1 (ADC_SQR1)

Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SQ4[4:0] Res. SQ3[4:0] Res. SQ2[4]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2[3:0] Res. SQ1[4:0] Res. Res. L[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 4th in the
regular conversion sequence.
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 3rd in the
regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 2nd in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 11 Reserved, must be kept at reset value.
Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 1st in the
regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bits 5:4 Reserved, must be kept at reset value.
Bits 3:0 L[3:0]: Regular channel sequence length
These bits are written by software to define the total number of conversions in the regular
channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
...
1111: 16 conversions
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

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RM0433 Analog-to-digital converters (ADC)

25.6.12 ADC regular sequence register 2 (ADC_SQR2)

Address offset: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SQ9[4:0] Res. SQ8[4:0] Res. SQ7[4]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7[3:0] Res. SQ6[4:0] Res. SQ5[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 9th in the
regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 8th in the
regular conversion sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 7th in the
regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 11 Reserved, must be kept at reset value.
Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 6th in the
regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 5th in the
regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

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25.6.13 ADC regular sequence register 3 (ADC_SQR3)

Address offset: 0x38
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SQ14[4:0] Res. SQ13[4:0] Res. SQ12[4]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12[3:0] Res. SQ11[4:0] Res. SQ10[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 14th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 13th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 12th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 11 Reserved, must be kept at reset value.
Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 11th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 10th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

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RM0433 Analog-to-digital converters (ADC)

25.6.14 ADC regular sequence register 4 (ADC_SQR4)

Address offset: 0x3C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. SQ16[4:0] Res. SQ15[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 16th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence
These bits are written by software with the channel number (0..19) assigned as the 15th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

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25.6.15 ADC regular Data Register (ADC_DR)

Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RDATA[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RDATA[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 RDATA[31:0]: Regular Data converted

These bits are read-only. They contain the conversion result from the last converted regular channel.
The data are left- or right-aligned as described in Section 25.4.27: Data management.

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RM0433 Analog-to-digital converters (ADC)

25.6.16 ADC injected sequence register (ADC_JSQR)

Address offset: 0x4C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4[4:0] Res. JSQ3[4:0] Res. JSQ2[4:1]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2[0] Res. JSQ1[4:0] JEXTEN[1:0] JEXTSEL[4:0] JL[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 JSQ4[4:0]: 4th conversion in the injected sequence

These bits are written by software with the channel number (0..19) assigned as the 4th in the
injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no
injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in
ADC_CFGR register).
Bit 26 Reserved, must be kept at reset value.
Bits 25:21 JSQ3[4:0]: 3rd conversion in the injected sequence
These bits are written by software with the channel number (0..19) assigned as the 3rd in the
injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no
injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in
ADC_CFGR register).
Bit 20 Reserved, must be kept at reset value.
Bits 19:15 JSQ2[4:0]: 2nd conversion in the injected sequence
These bits are written by software with the channel number (0..19) assigned as the 2nd in
the injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no
injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in
ADC_CFGR register).
Bit 14 Reserved, must be kept at reset value.
Bits 13:9 JSQ1[4:0]: 1st conversion in the injected sequence
These bits are written by software with the channel number (0..19) assigned as the 1st in the
injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no
injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in
ADC_CFGR register).

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Bits 8:7 JEXTEN[1:0]: External trigger enable and polarity selection for injected channels
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger of an injected group.
00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled and
If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be
launched by software
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no
injected conversion is ongoing).
If JQM=1 and if the Queue of Context becomes empty, the software and hardware
triggers of the injected sequence are both internally disabled (refer to Section 25.4.22:
Queue of context for injected conversions)
Bits 6:2 JEXTSEL[4:0]: External trigger selection for injected group
These bits select the external event used to trigger the start of conversion of an injected
group:
00000: Event 0
00001: Event 1
00010: Event 2
00011: Event 3
00100: Event 4
00101: Event 5
00110: Event 6
00111: Event 7
...
11111: Event 31:
Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no
injected conversion is ongoing).
Bits 1:0 JL[1:0]: Injected channel sequence length
These bits are written by software to define the total number of conversions in the injected
channel conversion sequence.
00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no
injected conversion is ongoing).

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RM0433 Analog-to-digital converters (ADC)

25.6.17 ADC injected channel y offset register (ADC_OFRy)

Address offset: 0x60 + 0x04 * (y-1), (y = 1 to 4)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE OFFSET_CH[4:0] OFFSET[25:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SSATE: Signed saturation Enable

This bit is written by software to enable or disable the Signed saturation feature.
This bit can be enabled only for 8-bit and 16-bit data format (see Section : Data register, data
alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT,
RSHIFT, SSATE) for details).
0: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit
signed format).
1: Offset is subtracted and result is saturated to maintain result size.
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
Bits 30:26 OFFSET_CH[4:0]: Channel selection for the Data offset y
These bits are written by software to define the channel to which the offset programmed into
bits OFFSETy[25:0] will apply.
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
Bits 25:0 OFFSET[25:0]: Data offset y for the channel programmed into bits OFFSETy_CH[4:0]
These bits are written by software to define the offset y to be subtracted from the raw
converted data when converting a channel (can be regular or injected). The channel to which
applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion
result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi
registers (injected conversion).
When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled.
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
If several offset (OFFSETy) point to the same channel, only the offset with the lowest x
value is considered for the subtraction.
Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is
subtracted when converting channel 4.

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25.6.18 ADC injected channel y data register (ADC_JDRy)

Address offset: 0x80 + 0x04 * (y-1), (y= 1 to 4)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 JDATA[31:0]: Injected data

These bits are read-only. They contain the conversion result from injected channel y. The
data are left -or right-aligned as described in Section 25.4.27: Data management.

25.6.19 ADC analog watchdog 2 configuration register

(ADC_AWD2CR)
Address offset: 0xA0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD2CH[19:16]

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWD2CH[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 AWD2CH[19:0]: Analog watchdog 2 channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by the analog watchdog 2.
AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2
AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2
When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled
Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers.
The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

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RM0433 Analog-to-digital converters (ADC)

25.6.20 ADC analog watchdog 3 configuration register

(ADC_AWD3CR)
Address offset: 0xA4
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3CH[19:16]

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWD3CH[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 AWD3CH[19:0]: Analog watchdog 3 channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by the analog watchdog 3.
AWD3CH[i] = 0: ADC analog input channel-i is not monitored by AWD3
AWD3CH[i] = 1: ADC analog input channel-i is monitored by AWD3
When AWD3CH[19:0] = 000..0, the analog Watchdog 3 is disabled
Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers.
The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

25.6.21 ADC watchdog lower threshold register 2 (ADC_LTR2)

Address offset: 0xB0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. LTR2[25:16]

rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LTR2[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 LTR2[25:0]: Analog watchdog 2 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 2.
Refer to Section 25.4.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy).
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

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25.6.22 ADC watchdog higher threshold register 2 (ADC_HTR2)

Address offset: 0xB4
Reset value: 0x03FF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. HTR2[25:16]

rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HTR2[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 HTR2[25:0]: Analog watchdog 2 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 2.
Refer to Section 25.4.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy).
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

25.6.23 ADC watchdog lower threshold register 3 (ADC_LTR3)

Address offset: 0xB8
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. LTR3[25:16]

rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LTR3[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 LTR3[25:0]: Analog watchdog 3 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 3.
Refer to Section 25.4.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

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RM0433 Analog-to-digital converters (ADC)

25.6.24 ADC watchdog higher threshold register 3 (ADC_HTR3)

Address offset: 0xBC
Reset value: 0x03FF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. HTR3[25:16]

rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HTR3[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 HTR3[25:0]: Analog watchdog 3 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 3.
Refer to Section 25.4.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

25.6.25 ADC differential mode selection register (ADC_DIFSEL)

Address offset: 0xC0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DIFSEL[19:16]

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIFSEL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 DIFSEL[19:0]: Differential mode for channels 19 to 0
These bits are set and cleared by software. They allow to select if a channel is configured as single
ended or differential mode.
DIFSEL[i] = 0: ADC analog input channel-i is configured in single ended mode
DIFSEL[i] = 1: ADC analog input channel-i is configured in differential mode
Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0,
JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

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25.6.26 ADC calibration factors register (ADC_CALFACT)

Address offset: 0xC4
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. CALFACT_D[10:0]

rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. CALFACT_S[10:0]

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:16 CALFACT_D[10:0]: Calibration Factors in differential mode
These bits are written by hardware or by software.
Once a differential inputs calibration is complete, they are updated by hardware with the calibration
factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new differential
conversion is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0
(ADC is enabled and no calibration is ongoing and no conversion is ongoing).
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 CALFACT_S[10:0]: Calibration Factors In Single-Ended mode
These bits are written by hardware or by software.
Once a single-ended inputs calibration is complete, they are updated by hardware with the
calibration factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new single-ended
conversion is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0
(ADC is enabled and no calibration is ongoing and no conversion is ongoing).

25.6.27 ADC calibration factor register 2 (ADC_CALFACT2)

Address offset: 0xC8
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. LINCALFACT[29:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LINCALFACT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0433 Analog-to-digital converters (ADC)

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:0 LINCALFACT[29:0]: Linearity Calibration Factor
These bits are written by hardware or by software.
They hold 30-bit out of the 160-bit linearity calibration factor.
Once a single-ended inputs calibration is complete, they are updated by hardware with the
calibration factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new single-ended
calibration is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0
(ADC is enabled and no calibration is ongoing and no conversion is ongoing).

25.7 ADC common registers

These registers define the control and status registers common to master and slave ADCs:

25.7.1 ADC x common status register (ADCx_CSR) (x=1/2 or 3)

Address offset: 0x00
Reset value: 0x0000 0000
The address offset is relative to the master ADC base address + 0x300.
This register provides an image of the status bits of the different ADCs. Nevertheless it is
read-only and does not allow to clear the different status bits. Instead each status bit must
be cleared by writing 0 to it in the corresponding ADC_ISR register.
ADC1 and ADC2 are controlled by the same interface, while ADC3 is controlled separately.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQOVF_ AWD3_ AWD2_ AWD1_ JEOS_ JEOC_ OVR_ EOS_ EOC_ EOSMP_ ADRDY_
Res. Res. Res. Res. Res.
SLV SLV SLV SLV SLV SLV SLV SLV SLV SLV SLV
r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF_ AWD3_ AWD2_ AWD1_ JEOS_ JEOC_ OVR_ EOS_ EOC_ EOSMP_ ADRDY_
Res. Res. Res. Res. Res.
MST MST MST MST MST MST MST MST MST MST MST
r r r r r r r r r r r

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC
This bit is a copy of the JQOVF bit in the corresponding ADCx+1_ISR register.
Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC
This bit is a copy of the AWD3 bit in the corresponding ADCx+1_ISR register.
Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC
This bit is a copy of the AWD2 bit in the corresponding ADCx+1_ISR register.
Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC
This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register.

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Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC

This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register.
Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC
This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register.
Bit 20 OVR_SLV: Overrun flag of the slave ADC
This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register.
Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC
This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register.
Bit 18 EOC_SLV: End of regular conversion of the slave ADC
This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register.
Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC
This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register.
Bit 16 ADRDY_SLV: Slave ADC ready
This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register.
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC
This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC
This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC
This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC
This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
Bit 6 JEOS_MST: End of injected sequence flag of the master ADC
This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
Bit 5 JEOC_MST: End of injected conversion flag of the master ADC
This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
Bit 4 OVR_MST: Overrun flag of the master ADC
This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
Bit 3 EOS_MST: End of regular sequence flag of the master ADC
This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
Bit 2 EOC_MST: End of regular conversion of the master ADC
This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC
This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
Bit 0 ADRDY_MST: Master ADC ready
This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.

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RM0433 Analog-to-digital converters (ADC)

25.7.2 ADC x common control register (ADCx_CCR) (x=1/2 or 3)

Address offset: 0x08
Reset value: 0x0000 0000
The address offset is relative to the master ADC base address + 0x300.
ADC1 and ADC2 are controlled by the same interface, while ADC3 is controlled separately.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. VBATEN TSEN VREFEN PRESC[3:0] CKMODE[1:0]
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAMDF[1:0] Res. Res. DELAY[3:0] Res. Res. Res. DUAL[4:0]
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 VBATEN: VBAT enable
This bit is set and cleared by software to control VBAT channel.
0: VBAT channel disabled
1: VBAT channel enabled
Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 23 TSEN: Temperature sensor voltage enable
This bit is set and cleared by software to control VSENSE channel.
0: Temperature sensor channel disabled
1: Temperature sensor channel enabled
Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 22 VREFEN: VREFINT enable
This bit is set and cleared by software to enable/disable the VREFINT channel.
0: VREFINT channel disabled
1: VREFINT channel enabled
Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

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Bits 21:18 PRESC[3:0]: ADC prescaler

These bits are set and cleared by software to select the frequency of the clock to the ADC.
The clock is common for all the ADCs.
0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
Others: Reserved, must not be used
Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The ADC prescaler
value is applied only when CKMODE[1:0] = 0b00.
Bits 17:16 CKMODE[1:0]: ADC clock mode
These bits are set and cleared by software to define the ADC clock scheme (which is
common to both master and slave ADCs):
Devices revision Y:
00: CK_ADCx (x=1 to 3) (Asynchronous clock mode), generated at product level (refer to
Section Reset and Clock Control (RCC))
01: adc_hclk/1 (Synchronous clock mode). This configuration must be enabled only if the
AHB clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system
clock has a 50% duty cycle.
10: adc_hclk/2 (Synchronous clock mode)
11: adc_hclk/4 (Synchronous clock mode)
In synchronous clock mode, there is no jitter in the delay from a timer trigger to the start of
conversion.

Devices revision V:
00: CK_ADCx (x=1 to 23) (Asynchronous clock mode), generated at product level (refer to
Section Reset and Clock Control (RCC))
01: adc_sclk/1 (Synchronous clock mode).
10: adc_sclk/2 (Synchronous clock mode)
11: adc_sclk/4 (Synchronous clock mode)
Whatever CKMODE[1:0] settings, an additional divider factor of 2 is applied to the clock
delivered to the analog ADC block.
In synchronous clock mode, when adc_ker_ck = 2 x adc_hclk, there is no jitter in the delay
from a timer trigger to the start of a conversion.
Note: The software is allowed to write these bits only when the ADCs are disabled
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

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RM0433 Analog-to-digital converters (ADC)

Bits 15:14 DAMDF[1:0]: Dual ADC Mode Data Format

This bit-field is set and cleared by software. It specifies the data format in the common data
register ADCx_CDR.
00: Dual ADC mode without data packing (ADCx_CDR and ADCx_CDR2 registers not
used).
01: Reserved.
10: Data formatting mode for 32 down to 10-bit resolution
11: Data formatting mode for 8-bit resolution
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bits 13:12 Reserved, must be kept at reset value.
Bits 11:8 DELAY[3:0]: Delay between 2 sampling phases
These bits are set and cleared by software. These bits are used in dual interleaved modes.
Refer to Table 220 for the value of ADC resolution versus DELAY bits values.
Note: The software is allowed to write these bits only when the ADCs are disabled
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DUAL[4:0]: Dual ADC mode selection
These bits are written by software to select the operating mode.
All the ADCs are independent:
00000: Independent mode
The configurations 00001 to 01001 correspond to the following operating modes: Dual
mode, master and slave ADCs working together:
00001: Combined regular simultaneous + injected simultaneous mode
00010: Combined regular simultaneous + alternate trigger mode
00011: Combined Interleaved mode + injected simultaneous mode
00100: Reserved.
00101: Injected simultaneous mode only
00110: Regular simultaneous mode only
00111: Interleaved mode only
01001: Alternate trigger mode only
All other combinations are reserved and must not be programmed

Note: The software is allowed to write these bits only when the ADCs are disabled
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Table 220. DELAY bits versus ADC resolution

16-bit 14-bit 12-bit 10-bit 8-bit
DELAY bits
resolution resolution resolution resolution resolution

0000 1.5 * Tadc_ker_ck 1.5 * Tadc_ker_ck 1.5 * Tadc_ker_ck 1.5 * Tadc_ker_ck 1.5 * Tadc_ker_ck
0001 2.5 * Tadc_ker_ck 2.5 * Tadc_ker_ck 2.5 * Tadc_ker_ck 2.5 * Tadc_ker_ck 2.5 * Tadc_ker_ck
0010 3.5 * Tadc_ker_ck 3.5 * Tadc_ker_ck 3.5 * Tadc_ker_ck 3.5 * Tadc_ker_ck 3.5 * Tadc_ker_ck
0011 4.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck
0100 5.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck
0101 6.5 * Tadc_ker_ck 6.5 * Tadc_ker_ck 6.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck
0110 7.5 * Tadc_ker_ck 7.5 * Tadc_ker_ck 6.5 * Tadc_ker_c 5.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck

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Table 220. DELAY bits versus ADC resolution (continued)

16-bit 14-bit 12-bit 10-bit 8-bit
DELAY bits
resolution resolution resolution resolution resolution

0111 8.5 * Tadc_ker_ck 7.5 * Tadc_ker_ck 6.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck
1000 8.5 * Tadc_ker_ck 7.5 * Tadc_ker_ck 6.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck
others:
reserved - - - - -

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RM0433 Analog-to-digital converters (ADC)

25.7.3 ADC x common regular data register for dual mode

(ADCx_CDR) (x=1/2 or 3)
Address offset: 0x0C
Reset value: 0x0000 0000
The address offset is relative to the master ADC base address + 0x300.
ADC1 and ADC2 are controlled by the same interface, while ADC3 is controlled separately.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV[15:0]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC

In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 25.4.32:
Dual ADC modes.
The data alignment is applied as described in Section : Data register, data alignment and
offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE))
Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC.
In dual mode, these bits contain the regular data of the master ADC. Refer to
Section 25.4.32: Dual ADC modes.
The data alignment is applied as described in Section : Data register, data alignment and
offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE))
In MDMA=0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains
MST_ADC_DR[7:0].

25.7.4 ADC x common regular data register for 32-bit dual mode
(ADCx_CDR2) (x=1/2 or 3)
Address offset: 0x10
Reset value: 0x0000 0000
The address offset is relative to the master ADC base address + 0x300.
ADC1 and ADC2 are controlled by the same interface, while ADC3 is controlled separately.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RDATA_ALT[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RDATA_ALT[15:0]

r r r r r r r r r r r r r r r r

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Bits 31:0 RDATA_ALT[31:0]: Regular data of the master/slave alternated ADCs

In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave
ADC. Refer to Section 25.4.32: Dual ADC modes.
The data alignment is applied as described in Section : Data register, data alignment and offset
(ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE).

25.8 ADC register map

The following table summarizes the ADC registers.

Table 221. ADC global register map

Offset Register

0x000 - 0x0D0 Master ADC1 or Master ADC3

0x0D4 - 0x0FC Reserved
0x100 - 0x1D0 Slave ADC2
0x1D4 - 0x2FC Reserved
0x300 - 0x310 Master and slave ADC common registers (ADC1/2 or ADC3)

Table 222. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC)
Register name
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
reset value
LDORDY

EOSMP
ADRDY
JQOVF
AWD3
AWD2
AWD1

JEOC
JEOS

OVR

EOC
EOS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

ADC_ISR
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

EOSMPIE
ADRDYIE
JQOVFIE
AWD3IE
AWD2IE
AWD1IE

JEOCIE
JEOSIE

OVRIE

EOCIE
EOSIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_IER
0x04

Reset value 0 0 0 0 0 0 0 0 0 0 0
LINCALRDYW6
LINCALRDYW5
LINCALRDYW4
LINCALRDYW3
LINCALRDYW2
LINCALRDYW1

BOOST[1:0](1)
ADVREGEN

JADSTART
DEEPPWD
ADCALDIF

ADCALLIN

ADSTART
JADSTP
ADCAL

ADSTP

ADDIS
ADEN
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

ADC_CR
0x08

Reset value 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXTEN[1:0]
AWD1SGL
JAWD1EN

OVRMOD
JDISCEN
AWD1EN

AUTDLY
DISCEN

DMN
JAUTO
JQDIS.

CONT

DISCNUM EXTSEL RES

JQM

Res.

ADC_CFGR AWD1CH[4:0] GT
0x0C [2:0] [4:0] [2:0]
[1:0]

Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSHIFT4
RSHIFT3
RSHIFT2
RSHIFT1
ROVSM

ROVSE
TROVS

JOVSE
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.

ADC_CFGR2 OSVR[9:0] OVSS[3:0]

0x10

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.

ADC_SMPR1 SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:0] SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0]
0x14
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0433 Analog-to-digital converters (ADC)

Table 222. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) (continued)
Register name
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
reset value

SMP19 SMP18 SMP17 SMP16 SMP15 SMP14 SMP13 SMP12 SMP11 SMP10
Res.
Res.
ADC_SMPR2
0x18 [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCSEL19
PCSEL18
PCSEL17
PCSEL16
PCSEL15
PCSEL14
PCSEL13
PCSEL12

PCSEL10
PCSEL11

PCSEL9
PCSEL8
PCSEL7
PCSEL6
PCSEL5
PCSEL4
PCSEL3
PCSEL2
PCSEL1
PCSEL0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_PCSEL
0x1C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
ADC_LTR1 LTR1[25:0]
0x20
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.

ADC_HTR1 HTR1[25:0]
0x24
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0x28 Reserved Res.
0x2C Reserved Res.
Res.
Res.
Res.

Res.

Res.

Res.

Res.
Res.
ADC_SQR1 SQ4[4:0] SQ3[4:0] SQ2[4:0] SQ1[4:0] L[3:0]
0x30
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.

Res.

Res.

Res.

Res.
ADC_SQR2 SQ9[4:0] SQ8[4:0] SQ7[4:0] SQ6[4:0] SQ5[4:0]
0x34
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.

Res.

Res.

Res.

Res.
ADC_SQR3 SQ14[4:0] SQ13[4:0] SQ12[4:0] SQ11[4:0] SQ10[4:0]
0x38
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
ADC_SQR4 SQ16[4:0] SQ15[4:0]
0x3C
Reset value 0 0 0 0 0 0 0 0 0 0
ADC_DR RDATA[31:0]
0x40
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x44-
Reserved Res.
0x48
JEXTEN[1:0]
Res.

Res.

Res.

ADC_JSQR JSQ4[4:0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] JEXTSEL[4:0] JL[1:0]

0x4C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x50-
Reserved Res.
0x5C
OFFSET1_CH[4:0]

OFFSET1[25:0]
SSATE

ADC_OFR1
0x60

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFFSET2_CH[4:0]

OFFSET2[25:0]
SSATE

ADC_OFR2
0x64

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Analog-to-digital converters (ADC) RM0433

Table 222. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) (continued)
Register name
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
reset value

OFFSET3_CH[4:0]

OFFSET3[25:0]
SSATE
ADC_OFR3
0x68

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFFSET4_CH[4:0]

OFFSET4[25:0]
SSATE

ADC_OFR4
0x6C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x70-
Reserved Res.
0x7C
ADC_JDR1 JDATA1[31:0]
0x80
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC_JDR2 JDATA2[31:0]
0x84
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC_JDR3 JDATA3[31:0]
0x88
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC_JDR4 JDATA4[31:0]
0x8C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x8C-
Reserved Res.
0x9C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_AWD2CR AWD2CH[19:0]
0xA0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_AWD3CR AWD3CH[19:0]
0xA4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0xA8-
Reserved
0xAC
Res.
Res.
Res.
Res.
Res.
Res.

ADC_LTR2 LTR2[25:0]
0xB0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.

ADC_HTR2 HTR2[25:0]
0xB4
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Res.
Res.
Res.
Res.
Res.
Res.

ADC_LTR3 LTR3[25:0]
0xB8
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.

ADC_HTR3 HTR3[25:0]
0xBC
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_DIFSEL DIFSEL[19:0]
0xC0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.

ADC_CALFACT CALFACT_D[10:0] CALFACT_S[10:0]

0xC4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC_
Res.
Res.

LINCALFACT[29:0]
0xC8 CALFACT2
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0433 Analog-to-digital converters (ADC)

Table 222. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) (continued)
Register name
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
reset value

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0xCC -
Reserved
0xD0

1. Revision Y devices feature only one BOOST bit.

Table 223. ADC register map and reset values (master and slave ADC
common registers) offset =0x300)
Register name
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
reset value

EOSMP_MST
ADRDY_MST
JQOVF_MST
EOSMP_SLV
ADRDY_SLV
JQOVF_SLV

AWD3_MST
AWD2_MST
AWD1_MST

JEOC_MST
JEOS_MST
AWD3_SLV
AWD2_SLV
AWD1_SLV

JEOC_SLV
JEOS_SLV

OVR_MST

EOC_MST
EOS_MST
OVR_SLV

EOC_SLV
EOS_SLV
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
ADCx_CSR
0x00

slave ADC2 master ADC1

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x04 Reserved Res.
CKMODE[1:0]

DAMDF[1:0]
VREFEN
VBATEN
TSEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
Res.
Res.
ADCx_CCR PRESC[3:0] DELAY[3:0] DUAL[4:0]
0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCx_CDR RDATA_SLV[15:0] RDATA_MST[15:0]
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCx_CDR2 RDATA_ALT[31:0]
0x10
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 129 for the register boundary addresses.

RM0433 Rev 8 1043/3353

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Digital-to-analog converter (DAC) RM0433

26 Digital-to-analog converter (DAC)

26.1 Introduction
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller.
In 12-bit mode, the data can be left- or right-aligned. The DAC features two output channels,
each with its own converter. In dual DAC channel mode, conversions can be done
independently or simultaneously when both channels are grouped together for synchronous
update operations. An input reference pin, VREF+ (shared with others analog peripherals) is
available for better resolution. An internal reference can also be set on the same input.
Refer to voltage reference buffer (VREFBUF) section.
The DACx_OUTy pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to obtain a high drive output current. An individual
calibration can be applied on each DAC output channel. The DAC output channels support
a low power mode, the Sample and hold mode.

26.2 DAC main features

The DAC main features are the following (see Figure 207: Dual-channel DAC block
diagram)
• One DAC interface, maximum two output channels
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave and Triangular-wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• External triggers for conversion
• DAC output channel buffered/unbuffered modes
• Buffer offset calibration
• Each DAC output can be disconnected from the DACx_OUTy output pin
• DAC output connection to on-chip peripherals
• Sample and hold mode for low power operation in Stop mode
• Input voltage reference from VREF+ pin or internal VREFBUF reference
Figure 207 shows the block diagram of a DAC channel and Table 225 gives the pin
description.

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RM0433 Digital-to-analog converter (DAC)

26.3 DAC implementation

Table 224. DAC features
DAC features DAC1

Dual channel X
Output buffer X
I/O connection DAC1_OUT1 on PA4, DAC1_OUT2 on PA5
Maximum sampling time 1 Msps
Autonomous mode -
VREF+ pin X

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Digital-to-analog converter (DAC) RM0433

26.4 DAC functional description

26.4.1 DAC block diagram

Figure 207. Dual-channel DAC block diagram

VDDA

Offset
calibration
dac_ch1_trg1 OTRIM1[4:0]
bits
TRIG

DACx_OUT1
MODE1 bits
dac_ch1_trg15
Buffer
TSEL1 DAC 1
[3:0] DOR1
converter 1
bits
12-bit
dac_ch1_dma

dac_unr_it
dac_pclk Control registers
& logic Channel1 Sample & Hold registers
TSAMPLE1 dac_out1
dac_hold THOLD1
_ck DAC channel 1 TREFRESH1

VREF+
32-bit APB
bus

Offset
calibration
Control registers OTRIM2[4:0]
& logic Channel2 bits
dac_ch2_dma

DACx_OUT2
MODE2 bits
DAC Buffer
DOR2 converter 2 2
TSEL2
[3:0] bits 12-bit
dac_ch2_trg1
TRIG
dac_ch2_trg15
Sample & Hold registers
TSAMPLE2
dac_hold dac_out2
THOLD2
_ck TREFRESH2
DAC channel 2
VSSA
MSv45318V9

1. MODEx bits in the DAC_MCR control the output mode and allow switching between the Normal mode in
buffer/unbuffered configuration and the Sample and hold mode.
2. Refer to Section 26.3: DAC implementation for channel2 availability.

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RM0433 Digital-to-analog converter (DAC)

26.4.2 DAC pins and internal signals

The DAC includes:
• Up to two output channels
• The DACx_OUTy can be disconnected from the output pin and used as an ordinary
GPIO
• The dac_outx can use an internal pin connection to on-chip peripherals such as
comparator, operational amplifier and ADC (if available).
• DAC output channel buffered or non buffered
• Sample and hold block and registers operational in Stop mode, using the LSI clock
source (dac_hold_ck) for static conversion.
The DAC includes up to two separate output channels. Each output channel can be
connected to on-chip peripherals such as comparator, operational amplifier and ADC (if
available). In this case, the DAC output channel can be disconnected from the DACx_OUTy
output pin and the corresponding GPIO can be used for another purpose.
The DAC output can be buffered or not. The Sample and hold block and its associated
registers can run in Stop mode using the LSI clock source (dac_hold_ck).

Table 225. DAC input/output pins

Pin name Signal type Remarks

Input, analog reference The higher/positive reference voltage for the DAC,
VREF+
positive VREF+ ≤ VDDAmax (refer to datasheet)
VDDA Input, analog supply Analog power supply
VSSA Input, analog supply ground Ground for analog power supply
DACx_OUTy Analog output signal DACx channely analog output

Table 226. DAC internal input/output signals

Internal signal name Signal type Description

dac_ch1_dma Bidirectional DAC channel1 DMA request/acknowledge

dac_ch2_dma Bidirectional DAC channel2 DMA request/acknowledge
dac_ch1_trgx (x = 1 to 15) Inputs DAC channel1 trigger inputs
dac_ch2_trgx (x = 1 to 15) Inputs DAC channel2 trigger inputs
dac_unr_it Output DAC underrun interrupt
dac_pclk Input DAC peripheral clock
dac_hold_ck Input DAC low-power clock used in Sample and hold mode
dac_out1 Analog output DAC channel1 output for on-chip peripherals
dac_out2 Analog output DAC channel2 output for on-chip peripherals

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Digital-to-analog converter (DAC) RM0433

Table 227. DAC interconnection

Signal name Source Source type

dac_hold_ck ck_lsi (selected in the RCC) LSI clock selected in the RCC
dac_chx_trg1 (x = 1, 2) tim1_trgo Internal signal from on-chip timers
dac_chx_trg2 (x = 1, 2) tim2_trgo Internal signal from on-chip timers
dac_chx_trg3 (x = 1, 2) tim4_trgo Internal signal from on-chip timers
dac_chx_trg4 (x = 1, 2) tim5_trgo Internal signal from on-chip timers
dac_chx_trg5 (x = 1, 2) tim6_trgo Internal signal from on-chip timers
dac_chx_trg6 (x = 1, 2) tim7_trgo Internal signal from on-chip timers
dac_chx_trg7 (x = 1, 2) tim8_trgo Internal signal from on-chip timers
dac_chx_trg8 (x = 1, 2) tim15_trgo Internal signal from on-chip timers
dac_chx_trg9 (x = 1, 2) hrtim1_dactrg1 Internal signal from on-chip timers
dac_chx_trg10 (x = 1, 2) hrtim1_dactrg2 Internal signal from on-chip timers
dac_chx_trg11 (x = 1, 2) lptim1_out Internal signal from on-chip timers
dac_chx_trg12 (x = 1, 2) lptim2_out Internal signal from on-chip timers
dac_chx_trg13 (x = 1, 2) exti9 External pin

26.4.3 DAC channel enable

Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR
register. The DAC channel is then enabled after a tWAKEUP startup time.
Note: The ENx bit enables the analog DAC channelx only. The DAC channelx digital interface is
enabled even if the ENx bit is reset.

26.4.4 DAC data format

Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
• Single DAC channel
There are three possibilities:
– 8-bit right alignment: the software has to load data into the DAC_DHR8Rx[7:0] bits
(stored into the DHRx[11:4] bits)
– 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4]
bits (stored into the DHRx[11:0] bits)
– 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0]
bits (stored into the DHRx[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHRx (data holding registerx, which are internal non-memory-
mapped registers). The DHRx register is then loaded into the DORx register either
automatically, by software trigger or by an external event trigger.

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RM0433 Digital-to-analog converter (DAC)

Figure 208. Data registers in single DAC channel mode

31 24 15 7 0
8-bit right aligned

12-bit left aligned

12-bit right aligned

ai14710b
• Dual DAC channels (when available)
There are three possibilities:
– 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD
[7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded
into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)
– 12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD
[15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be
loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)
– 12-bit right alignment: data for DAC channel1 to be loaded into the
DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC
channel2 to be loaded into the DAC_DHR12RD [27:16] bits (stored into the
DHR2[11:0] bits)
Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted
and stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-
mapped registers). The DHR1 and DHR2 registers are then loaded into the DAC_DOR1
and DOR2 registers, respectively, either automatically, by software trigger or by an external
event trigger.

Figure 209. Data registers in dual DAC channel mode

31 24 15 7 0
8-bit right aligned

12-bit left aligned

12-bit right aligned

ai14709b

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Digital-to-analog converter (DAC) RM0433

26.4.5 DAC conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write operation to DAC_DHR8Rx,
DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD).
Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one dac_pclk clock cycle, if no hardware trigger is selected (TENx bit in
DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in
DAC_CR register is set) and a trigger occurs, the transfer is performed three dac_pclk clock
cycles after the trigger signal.
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time tSETTLING that depends on the power supply voltage and the
analog output load.

Figure 210. Timing diagram for conversion with trigger disabled TEN = 0

Bus clock

DHR 0x1AC

Output voltage available on

DOR 0x1AC DAC_OUT pin
tSETTLING

MSv45319V2

26.4.6 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+.
The analog output voltages on each DAC channel pin are determined by the following
equation:
DOR
DACoutput = V REF × --------------
4096

26.4.7 DAC trigger selection

If the TENx control bit is set, the conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[3:0] control bits determine which out of 16 pos-
sible events triggers the conversion as shown in TSELx[3:0] bits of the DAC_CR register.
These events can be either the software trigger or hardware triggers. Refer to the intercon-
nection table in Section 26.4.2: DAC pins and internal signals.
Each time a DAC interface detects a rising edge on the selected trigger source (refer to the
table below), the last data stored into the DAC_DHRx register are transferred into the
DAC_DORx register. The DAC_DORx register is updated three dac_pclk cycles after the
trigger occurs.

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RM0433 Digital-to-analog converter (DAC)

If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
Note: TSELx[3:0] bit cannot be changed when the ENx bit is set.
When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DORx register takes only one dac_pclk clock cycle.

26.4.8 DMA requests

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC
channel DMA requests.
When an external trigger (but not a software trigger) occurs while the DMAENx bit is set, the
value of the DAC_DHRx register is transferred into the DAC_DORx register when the
transfer is complete, and a DMA request is generated.
In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one
DMA request is needed, only the corresponding DMAENx bit must be set. In this way, the
application can manage both DAC channels in dual mode by using one DMA request and a
unique DMA channel.
As DAC_DHRx to DAC_DORx data transfer occurred before the DMA request, the very first
data has to be written to the DAC_DHRx before the first trigger event occurs.

DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgment for the first external trigger is received (first request), then no new request
is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set,
reporting the error condition. The DAC channelx continues to convert old data.
The software must clear the DMAUDRx flag by writing 1, clear the DMAEN bit of the used
DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly.
The software must modify the DAC trigger conversion frequency or lighten the DMA
workload to avoid a new DMA underrun. Finally, the DAC conversion can be resumed
by enabling both DMA data transfer and conversion trigger.
For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit
in the DAC_CR register is enabled.

26.4.9 Noise generation

In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift
register) is available. DAC noise generation is selected by setting WAVEx[1:0] to 01. The
preloaded value in LFSR is 0xAAA. This register is updated three dac_pclk clock cycles
after each trigger event, following a specific calculation algorithm.

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Figure 211. DAC LFSR register calculation algorithm

XOR

X6 X4 X X0
X 12
11 10 9 8 7 6 5 4 3 2 1 0

12

NOR

ai14713c

The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in
the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this
value is then transferred into the DAC_DORx register.
If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 212. DAC conversion (SW trigger enabled) with LFSR wave generation

dac_pclk

DHR 0x00

DOR 0xAAA 0xD55

SWTRIG

MS45320V1

Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.

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26.4.10 Triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected by setting WAVEx[1:0] to 10”. The amplitude is
configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter
is incremented three dac_pclk clock cycles after each trigger event. The value of this
counter is then added to the DAC_DHRx register without overflow and the sum is
transferred into the DAC_DORx register. The triangle counter is incremented as long as it is
less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured
amplitude is reached, the counter is decremented down to 0, then incremented again and so
on.
It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.

Figure 213. DAC triangle wave generation

MAMPx[3:0] max amplitude

+ DAC_DHRx base value

De
n
tio

c
re
ta
en

m
en
em

ta
cr

tio
In

n
DAC_DHRx base value
0

ai14715c

Figure 214. DAC conversion (SW trigger enabled) with triangle wave generation

dac_pclk

DHR 0xABE

DOR 0xABE 0xABF 0xAC0

SWTRIG

MS45321V1

Note: The DAC trigger must be enabled for triangle wave generation by setting the TENx bit in the
DAC_CR register.
The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot
be changed.

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26.4.11 DAC channel modes

Each DAC channel can be configured in Normal mode or Sample and hold mode. The
output buffer can be enabled to obtain a high drive capability. Before enabling output buffer,
the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded
after reset) and can be adjusted by software during application operation.

Normal mode
In Normal mode, there are four combinations, by changing the buffer state and by changing
the DACx_OUTy pin interconnections.
To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:
• 000: DAC is connected to the external pin
• 001: DAC is connected to external pin and to on-chip peripherals
To disable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:
• 010: DAC is connected to the external pin
• 011: DAC is connected to on-chip peripherals

Sample and hold mode

In Sample and hold mode, the DAC core converts data on a triggered conversion, and then
holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer
are completely turned off between samples and the DAC output is tri-stated, therefore
reducing the overall power consumption. A stabilization period, which value depends on the
buffer state, is required before each new conversion.
In this mode, the DAC core and all corresponding logic and registers are driven by the LSI
low-speed clock (dac_hold_ck) in addition to the dac_pclk clock, allowing using the DAC
channels in deep low power modes such as Stop mode.
The LSI low-speed clock (dac_hold_ck) must not be stopped when the Sample and hold
mode is enabled.
The sample/hold mode operations can be divided into 3 phases:
1. Sample phase: the sample/hold element is charged to the desired voltage. The
charging time depends on capacitor value (internal or external, selected by the user).
The sampling time is configured with the TSAMPLEx[9:0] bits in DAC_SHSRx register.
During the write of the TSAMPLEx[9:0] bits, the BWSTx bit in DAC_SR register is set to
1 to synchronize between both clocks domains (APB and low speed clock) and
allowing the software to change the value of sample phase during the DAC channel
operation
2. Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are
turned off, to reduce the current consumption. The hold time is configured with the
THOLDx[9:0] bits in DAC_SHHR register
3. Refresh phase: the refresh time is configured with the TREFRESHx[7:0] bits in
DAC_SHRR register

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The timings for the three phases above are in units of LSI clock periods. As an example, to
configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs
assuming LSI ~32 KHz is selected:
12 cycles are required for sample phase: TSAMPLEx[9:0] = 11,
62 cycles are required for hold phase: THOLDx[9:0] = 62,
and 4 cycles are required for refresh period: TREFRESHx[7:0] = 4.
In this example, the power consumption is reduced by almost a factor of 15 versus Normal
modes.
The formulas to compute the right sample and refresh timings are described in the table
below, the Hold time depends on the leakage current.

Table 228. Sample and refresh timings

Buffer
State
tSAMP(1)(2) tREFRESH(2)(3)

Enable 7 μs + (10*RBON*CSH) 7 μs + (RBON*CSH)*ln(2*NLSB)

Disable 3 μs + (10*RBOFF*CSH) 3 μs + (RBOFF*CSH)*ln(2*NLSB)
1. In the above formula the settling to the desired code value with ½ LSB or accuracy requires 10 constant
time for 12 bits resolution. For 8 bits resolution, the settling time is 7 constant time.
2. CSH is the capacitor in Sample and hold mode.
3. The tolerated voltage drop during the hold phase “Vd” is represented by the number of LSBs after the
capacitor discharging with the output leakage current. The settling back to the desired value with ½ LSB
error accuracy requires ln(2*Nlsb) constant time of the DAC.

Example of the sample and refresh time calculation with output buffer on
The values used in the example below are provided as indication only. Refer to the product
datasheet for product data.
CSH = 100 nF
VDDA = 3.0 V
Sampling phase:
tSAMP = 7 μs + (10 * 2000 * 100 * 10-9) = 2.007 ms
(where RBON = 2 kΩ)
Refresh phase:
tREFRESH = 7 μs + (2000 * 100 * 10-9) * ln(2*10) = 606.1 μs
(where NLSB = 10 (10 LSB drop during the hold phase)
Hold phase:
Dv = ileak * thold / CSH = 0.0073 V (10 LSB of 12bit at 3 V)
ileak = 150 nA (worst case on the IO leakage on all the temperature range)
thold = 0.0073 * 100 * 10-9 / (150 * 10-9) = 4.867 ms

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Figure 215. DAC Sample and hold mode phase diagram

V1
Vd
V2

t
Sampling phase Hold phase Refresh Sampling phase
dac_hold phase
_ck

t
DAC

ON ON ON
MSv45340V3

Like in Normal mode, the Sample and hold mode has different configurations.
To enable the output buffer, MODEx[2:0] bits in DAC_MCR register must be set to:
• 100: DAC is connected to the external pin
• 101: DAC is connected to external pin and to on chip peripherals
To disabled the output buffer, MODEx[2:0] bits in DAC_MCR register must be set to:
• 110: DAC is connected to external pin and to on chip peripherals
• 111: DAC is connected to on chip peripherals
When MODEx[2:0] bits are equal to 111, an internal capacitor, CLint, holds the voltage
output of the DAC core and then drive it to on-chip peripherals.
All Sample and hold phases are interruptible, and any change in DAC_DHRx immediately
triggers a new sample phase.

Table 229. Channel output modes summary

MODEx[2:0] Mode Buffer Output connections

0 0 0 Connected to external pin

Enabled Connected to external pin and to on chip-peripherals (such as
0 0 1
Normal mode comparators)
0 1 0 Connected to external pin
Disabled
0 1 1 Connected to on chip peripherals (such as comparators)

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Table 229. Channel output modes summary (continued)

MODEx[2:0] Mode Buffer Output connections

1 0 0 Connected to external pin

Enabled Connected to external pin and to on chip peripherals (such as
1 0 1
Sample and comparators)
hold mode Connected to external pin and to on chip peripherals (such as
1 1 0
Disabled comparators)
1 1 1 Connected to on chip peripherals (such as comparators)

26.4.12 DAC channel buffer calibration

The transfer function for an N-bit digital-to-analog converter (DAC) is:

V = ( ( D ⁄ 2N ) × G × V )+V
out ref OS
Where VOUT is the analog output, D is the digital input, G is the gain, Vref is the nominal full-
scale voltage, and Vos is the offset voltage. For an ideal DAC channel, G = 1 and Vos = 0.
Due to output buffer characteristics, the voltage offset may differ from part-to-part and
introduce an absolute offset error on the analog output. To compensate the Vos, a calibration
is required by a trimming technique.
The calibration is only valid when the DAC channelx is operating with buffer enabled
(MODEx[2:0] = 0b000 or 0b001 or 0b100 or 0b101). if applied in other modes when the
buffer is off, it has no effect. During the calibration:
• The buffer output is disconnected from the pin internal/external connections and put in
tristate mode (HiZ).
• The buffer acts as a comparator to sense the middle-code value 0x800 and compare it
to VREF+/2 signal through an internal bridge, then toggle its output signal to 0 or 1
depending on the comparison result (CAL_FLAGx bit).
Two calibration techniques are provided:
• Factory trimming (default setting)
The DAC buffer offset is factory trimmed. The default value of OTRIMx[4:0] bits in
DAC_CCR register is the factory trimming value and it is loaded once DAC digital
interface is reset.
• User trimming
The user trimming can be done when the operating conditions differs from nominal
factory trimming conditions and in particular when VDDA voltage, temperature, VREF+
values change and can be done at any point during application by software.
Note: Refer to the datasheet for more details of the Nominal factory trimming conditions
In addition, when VDD is removed (example the device enters in STANDBY or VBAT modes)
the calibration is required.
The steps to perform a user trimming calibration are as below:

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1. If the DAC channel is active, write 0 to ENx bit in DAC_CR to disable the channel.
2. Select a mode where the buffer is enabled, by writing to DAC_MCR register,
MODEx[2:0] = 0b000 or 0b001 or 0b100 or 0b101.
3. Start the DAC channelx calibration, by setting the CENx bit in DAC_CR register to 1.
4. Apply a trimming algorithm:
a) Write a code into OTRIMx[4:0] bits, starting by 0b00000.
b) Wait for tTRIM delay.
c) Check if CAL_FLAGx bit in DAC_SR is set to 1.
d) If CAL_FLAGx is set to 1, the OTRIMx[4:0] trimming code is found and can be
used during device operation to compensate the output value, else increment
OTRIMx[4:0] and repeat sub-steps from (a) to (d) again.
The software algorithm may use either a successive approximation or dichotomy techniques
to compute and set the content of OTRIMx[4:0] bits in a faster way.
The commutation/toggle of CAL_FLAGx bit indicates that the offset is correctly
compensated and the corresponding trim code must be kept in the OTRIMx[4:0] bits in
DAC_CCR register.
Note: A tTRIM delay must be respected between the write to the OTRIMx[4:0] bits and the read of
the CAL_FLAGx bit in DAC_SR register in order to get a correct value.This parameter is
specified into datasheet electrical characteristics section.
If VDDA, VREF+ and temperature conditions do not change during device operation while it
enters more often in standby and VBAT mode, the software may store the OTRIMx[4:0] bits
found in the first user calibration in the flash or in back-up registers. then to load/write them
directly when the device power is back again thus avoiding to wait for a new calibration time.
When CENx bit is set, it is not allowed to set ENx bit.

26.4.13 Dual DAC channel conversion modes (if dual channels are
available)
To efficiently use the bus bandwidth in applications that require the two DAC channels at the
same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A
unique register access is then required to drive both DAC channels at the same time. For
the wave generation, no accesses to DHRxxxD registers are required. As a result, two
output channels can be used either independently or simultaneously.
11 conversion modes are possible using the two DAC channels and these dual registers. All
the conversion modes can nevertheless be obtained using separate DHRx registers if
needed.
All modes are described in the paragraphs below.

Independent trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).

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When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1
(three dac_pclk clock cycles later).
When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2
(three dac_pclk clock cycles later).

Independent trigger with single LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask value
in the MAMPx[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to
the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_pclk clock cycles
later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_pclk clock cycles
later). Then the LFSR2 counter is updated.

Independent trigger with different LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR masks
values in the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by
MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1
(three dac_pclk clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by
MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three dac_pclk clock cycles later). Then the LFSR2 counter is updated.

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Independent trigger with single triangle generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum
amplitude value in the MAMPx[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same
triangle amplitude, is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three dac_pclk clock cycles later). The DAC channel1 triangle counter is then
updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same
triangle amplitude, is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three dac_pclk clock cycles later). The DAC channel2 triangle counter is then
updated.

Independent trigger with different triangle generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bits.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle
amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is
transferred into DAC_DOR1 (three dac_pclk clock cycles later). The DAC channel1 triangle
counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle
amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is
transferred into DAC_DOR2 (three dac_pclk clock cycles later). The DAC channel2 triangle
counter is then updated.

Simultaneous software start

To configure the DAC in this conversion mode, the following sequence is required:
• Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
In this configuration, one dac_pclk clock cycle later, the DHR1 and DHR2 registers are
transferred into DAC_DOR1 and DAC_DOR2, respectively.

Simultaneous trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:

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1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and
DAC_DOR2, respectively (after three dac_pclk clock cycles).

Simultaneous trigger with single LFSR generation

1. To configure the DAC in this conversion mode, the following sequence is required:
2. Set the two DAC channel trigger enable bits TEN1 and TEN2.
3. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
4. Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask value
in the MAMPx[3:0] bits.
5. Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or
DHR8RD).
When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1
register and the sum is transferred into DAC_DOR1 (three dac_pclk clock cycles later). The
LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask,
is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_pclk
clock cycles later). The LFSR2 counter is then updated.

Simultaneous trigger with different LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR mask
values using the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is
added to the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_pclk
clock cycles later). The LFSR1 counter is then updated.
At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_pclk clock cycles
later). The LFSR2 counter is then updated.

Simultaneous trigger with single triangle generation

To configure the DAC in this conversion mode, the following sequence is required:

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1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum
amplitude value using the MAMPx[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the DAC channel1 triangle counter, with the same triangle
amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three
dac_pclk clock cycles later). The DAC channel1 triangle counter is then updated.
At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is
added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_pclk
clock cycles later). The DAC channel2 triangle counter is then updated.

Simultaneous trigger with different triangle generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude
configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB clock cycles later). Then the DAC channel1 triangle counter is
updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured
by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three dac_pclk clock cycles later). Then the DAC channel2 triangle counter is updated.

26.5 DAC in low-power modes

Table 230. Effect of low-power modes on DAC

Mode Description

Sleep No effect, DAC can be used with DMA

The DAC remains active with a static output value.
Stop
The Sample and hold mode is not available.
The DAC peripheral is powered down and must be reinitialized after exiting
Standby
Standby mode.

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26.6 DAC interrupts

Table 231. DAC interrupts
Interrupt Interrupt Enable Interrupt clear Exit Sleep Exit Stop Exit Standby
Event flag
acronym event control bit method mode mode mode

DMA DMAUDRI Write

DAC DMAUDRx Yes No No
underrun Ex DMAUDRx = 1

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26.7 DAC registers

Refer to Section 1 on page 101 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).

26.7.1 DAC control register (DAC_CR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAU DMAE
Res. CEN2 MAMP2[3:0] WAVE2[1:0] TSEL2[3] TSEL2[2] TSEL2[1] TSEL2[0] TEN2 EN2
DRIE2 N2
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAU DMAE
Res. CEN1 MAMP1[3:0] WAVE1[1:0] TSEL1[3] TSEL1[2] TSEL1[1] TSEL1[0] TEN1 EN1
DRIE1 N1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 CEN2: DAC channel2 calibration enable
This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be
written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only
when the DAC channel is disabled) Otherwise, the write operation is ignored.
0: DAC channel2 in Normal operating mode
1: DAC channel2 in calibration mode
Note: This bit is available only on dual-channel DACs. Refer to Section 26.3: DAC
implementation.
Bit 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
This bit is set and cleared by software.
0: DAC channel2 DMA underrun interrupt disabled
1: DAC channel2 DMA underrun interrupt enabled
Note: This bit is available only on dual-channel DACs. Refer to Section 26.3: DAC
implementation.
Bit 28 DMAEN2: DAC channel2 DMA enable
This bit is set and cleared by software.
0: DAC channel2 DMA mode disabled
1: DAC channel2 DMA mode enabled
Note: This bit is available only on dual-channel DACs. Refer to Section 26.3: DAC
implementation.

1064/3353 RM0433 Rev 8

RM0433 Digital-to-analog converter (DAC)

Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector

These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Note: These bits are available only on dual-channel DACs. Refer to Section 26.3: DAC
implementation.
Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable
These bits are set/reset by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
These bits are available only on dual-channel DACs. Refer to Section 26.3: DAC
implementation.
Bits 21:18 TSEL2[3:0]: DAC channel2 trigger selection
These bits select the external event used to trigger DAC channel2
0000: SWTRIG2
0001: dac_ch2_trg1
0010: dac_ch2_trg2
...
1111: dac_ch2_trg15
Refer to the trigger selection tables in Section 26.4.2: DAC pins and internal signals for
details on trigger configuration and mapping.
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
These bits are available only on dual-channel DACs. Refer to Section 26.3: DAC
implementation.
Bit 17 TEN2: DAC channel2 trigger enable
This bit is set and cleared by software to enable/disable DAC channel2 trigger
0: DAC channel2 trigger disabled and data written into the DAC_DHR2 register are
transferred one dac_pclk clock cycle later to the DAC_DOR2 register
1: DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred
three dac_pclk clock cycles later to the DAC_DOR2 register
Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the
DAC_DOR2 register takes only one dac_pclk clock cycle.
These bits are available only on dual-channel DACs. Refer to Section 26.3: DAC
implementation.

RM0433 Rev 8 1065/3353

1080
Digital-to-analog converter (DAC) RM0433

Bit 16 EN2: DAC channel2 enable

This bit is set and cleared by software to enable/disable DAC channel2.
0: DAC channel2 disabled
1: DAC channel2 enabled
Note: These bits are available only on dual-channel DACs. Refer to Section 26.3: DAC
implementation.
Bit 15 Reserved, must be kept at reset value.
Bit 14 CEN1: DAC channel1 calibration enable
This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be
written only if bit EN1 = 0 into DAC_CR (the calibration mode can be entered/exit only when
the DAC channel is disabled) Otherwise, the write operation is ignored.
0: DAC channel1 in Normal operating mode
1: DAC channel1 in calibration mode
Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable
This bit is set and cleared by software.
0: DAC channel1 DMA Underrun Interrupt disabled
1: DAC channel1 DMA Underrun Interrupt enabled
Bit 12 DMAEN1: DAC channel1 DMA enable
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude