Behavioral Code for 8x3 Encoder: Testbench for Behavioral Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity decoder_3_8_behav is entity tb_decoder_3_8_behav is

port(d: in std_logic_vector(2 downto 0); end tb_decoder_3_8_behav;
o: out std_logic_vector(7 downto 0));
end decoder_3_8_behav; architecture testbench of tb_decoder_3_8_behav is
component decoder_3_8_behav
architecture behavioural of decoder_3_8_behav is port(d: in std_logic_vector(2 downto 0);
begin o: out std_logic_vector(7 downto 0));
process (d) end component;
variable temp : std_logic_vector(7 downto 0); signal d : std_logic_vector(2 downto 0);
begin signal o : std_logic_vector(7 downto 0);
case d is begin
when "000" => temp := "00000001"; u1 : decoder_3_8_behav port map (d => d, o => o);
when "001" => temp := "00000010"; process begin
when "010" => temp := "00000100"; d<="000"; wait for 10 ns;
when "011" => temp := "00001000"; d<="001"; wait for 10 ns;
when "100" => temp := "00010000"; d<="010"; wait for 10 ns;
when "101" => temp := "00100000"; d<="011"; wait for 10 ns;
when "110" => temp := "01000000"; d<="100"; wait for 10 ns;
when "111" => temp := "10000000"; d<="101"; wait for 10 ns;
when others => temp := "XXXXXXXX"; d<="110"; wait for 10 ns;
end case; d<="111"; wait for 10 ns;
o <= temp; end process;
end process; end testbench;
end behavioural;

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Testbench for Structural Code: Structural Code for 8x3 Encoder:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity tb_decoder_3_8_struct is entity decoder_3_8_struct is

end tb_decoder_3_8_struct; port(d: in std_logic_vector(2 downto 0);
o: out std_logic_vector(7 downto 0));
architecture testbench of tb_decoder_3_8_struct is end decoder_3_8_struct;
component decoder_3_8_struct
port(d: in std_logic_vector(2 downto 0); architecture structural of decoder_3_8_struct is
o: out std_logic_vector(7 downto 0)); component and_3_gate is
end component; port(l, m, n: in std_logic;
signal d : std_logic_vector(2 downto 0); o: out std_logic);
signal o : std_logic_vector(7 downto 0); end component;
begin component not_gate is
u1 : decoder_3_8_struct port map (d => d, o => o); port(m: in std_logic;
process begin o: out std_logic);
d<="000"; wait for 10 ns; end component;
d<="001"; wait for 10 ns; signal dbar: std_logic_vector(2 downto 0);
d<="010"; wait for 10 ns; begin
d<="011"; wait for 10 ns;
d<="100"; wait for 10 ns; N1: not_gate port map(d(0), dbar(0));
d<="101"; wait for 10 ns; N2: not_gate port map(d(1), dbar(1));
d<="110"; wait for 10 ns; N3: not_gate port map(d(2), dbar(2));
d<="111"; wait for 10 ns; A1: and_3_gate port map(dbar(0), dbar(1), dbar(2),
end process; o(0));
end testbench; A2: and_3_gate port map(d(0), dbar(1), dbar(2),
o(1));
A3: and_3_gate port map(dbar(0), d(1), dbar(2),
o(2));
A4: and_3_gate port map(d(0), d(1), dbar(2), o(3));
A5: and_3_gate port map(dbar(0), dbar(1), d(2),
o(4));
A6: and_3_gate port map(d(0), dbar(1), d(2), o(5));
A7: and_3_gate port map(dbar(0), d(1), d(2), o(6));
A8: and_3_gate port map(d(0), d(1), d(2), o(7));

end structural;
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Dataflow Code for 8x3 Encoder: Testbench for Dataflow Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity decoder_3_8_dataf is entity tb_decoder_3_8_dataf is

port(d: in std_logic_vector(2 downto 0); end tb_decoder_3_8_dataf;
o: out std_logic_vector(7 downto 0));
end decoder_3_8_dataf; architecture testbench of tb_decoder_3_8_dataf is
component decoder_3_8_dataf
architecture dataflow of decoder_3_8_dataf is port(d: in std_logic_vector(2 downto 0);
begin o: out std_logic_vector(7 downto 0));
o(0)<=((not d(0)) and (not d(1)) and (not d(2))); end component;
o(1)<=((d(0)) and (not d(1)) and (not d(2))); signal d : std_logic_vector(2 downto 0);
o(2)<=((not d(0)) and (d(1)) and (not d(2))); signal o : std_logic_vector(7 downto 0);
o(3)<=((d(0)) and (d(1)) and (not d(2))); begin
o(4)<=((not d(0)) and (not d(1)) and (d(2))); u1 : decoder_3_8_dataf port map (d => d, o => o);
o(5)<=((d(0)) and (not d(1)) and (d(2))); process begin
o(6)<=((not d(0)) and (d(1)) and (d(2))); d<="000"; wait for 10 ns;
o(7)<=((d(0)) and (d(1)) and (d(2))); d<="001"; wait for 10 ns;
end dataflow; d<="010"; wait for 10 ns;
d<="011"; wait for 10 ns;
d<="100"; wait for 10 ns;
d<="101"; wait for 10 ns;
d<="110"; wait for 10 ns;
d<="111"; wait for 10 ns;
end process;
end testbench;

Waveform:

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