INTRODUCTION TO CMOS OIE _AND COMPARATORS ior. GREGORIANCONTENTS PREFACE 1 INTRODUCTION 1 1d 12 Classification of Signal Processing Techniques / 1 Examples of Applications of Op-Amps and Comparators in Analog MOS Circuits / 6 Problems / 16 References / 16 2 MOS DEVICES AS CIRCUIT ELEMENTS 17 21 22 23 24 25 26 27 28 Semiconductors / 17 MOS Transistors / 21 MOS Transistor Types: Body Effect / 27 ‘Small-Signal Operation and Equivalent Circuit of MOSFET Transistors / 30 Weak Inversion / 39 Impact Ionization / 40 Noise in MOSFETS / 41 CMOS Process / 44 Problems / 45 References / 47 viiviii. = CONTENTS 3 BASIC ANALOG CMOS SUBCIRCUITS 48 3.1 32 3.3 34 35 3.6 Bias Circuits in MOS Technology / 48 MOS Current Mirrors and Current Sources / 55 MOS Gain Stages / 63 MOS Source Followers / 74 MOS Differential Amplifiers / 77 Frequency Response of MOS Amplifier Stages / 84 Problems / 92 References / 94 4 CMOS OPERATIONAL AMPLIFIERS, 95 4.1 4.2 4.3 44 45 46 47 48 49 4.10 Operational Amplifiers / 95 Single-Stage Operational Amplifiers / 100 Two-Stage Operational Amplifiers / 106 Stability and Compensation of CMOS Amplifiers / 112 Dynamic Range of CMOS Op-Amps / 126 Frequency Response, Transient Response. and Slew Rate of ‘Compensated CMOS Op-Amps / 132 Noise Performance of CMOS Op-Amps / 137 Fully Differential Op-Amps / 140 CMOS Output Stages / 149 Op-Amps with Rail-to-Rail Input Common-Mode Range / 164 Problems / 170 References / 173 5 COMPARATORS 175 5.1 5.2 5.3 54 5.5 56 6.1 6.2 Circuit Modeling of a Comparator / 175 Single-Ended Auto-Zeroing Comparators / 177 Differential Comparators / 182 Regenerative Comparators (Schmitt Triggers) / 192 Fully Differential Comparators / 198 Latches / 205 Problems / 212 References / 213 DIGITAL-TO-ANALOG CONVERTERS. 214 Digital-to-Analog Conversion: Basic Principles / 214 Voltage-Mode D/A Converter Stages / 21863 6.4 65 6.6 CONTENTS = ix Charge-Mode D/A Converter Stages / 231 Hybrid D/A Converter Stages / 234 Current-Mode D/A Converter Stages / 238 Segmented Current-Mode D/A Converter Stages / 244 Problems / 252 References / 254 ANALOG-TO-DIGITAL CONVERTERS 255 TA 72 73 7 1S 76 TT Analog-to-Digital Conversion: Basic Principles / 255 Flash A/D Converters / 263 Interpolating Flash A/D Converters / 270 Two-Step A/D Converters / 273 Successive-Approximation A/D Converters / 282 Counting and Tracking A/D Converters / 294 Integrating A/D Converters / 295 Problems / 300 References / 301 PRACTICAL CONSIDERATIONS AND DESIGN EXAMPLES 303 81 8.2 8.3 Practical Considcrations in CMOS Op-Amp Design / 303 Op-Amp Design Techniques and Examples / 316 Comparator Design Techniques and Examples / 349 Problems / 355 References / 355 INDEX 357CHAPTER 1 INTRODUCTION Operational amplifiers (op-amps) and comparators are two of the. most important building blocks for analog signal processing. Op-amps and a few passivé components can be used to realize such important functions as summing and inverting amplifiers, integrators, and buffers. The combination of these functions and comparators can ‘result in many complex functions, such as high-order filters, signal amplifiers, ana- Jog-to-digital (A/D) and digital-to-analog (D/A) converters, input and output signal buffers, and many more. Making the op-amp and comparator faster has always been one of the goals of analog designers. In this chapter the basic concept of digital and analog signal processing is introduced. Then a third category of signal processing, the sampled-data analog technique, which is in between the two main classifications, is described. Finally, a few representative examples are given of circuits and systems utilizing CMOS op-amps and comparators, to illustrate the great potential of these components as part of an MOS-LSI chip. 1.1 CLASSIFICATION OF SIGNAL PROCESSING TECHNIQUES [1-4] Electrical signal processors are usually divided into two categories: analog and digital systems. An analog system carries signals in the form of voltages, currents, charges, and so on, which are continuous functions of the continuous-time variable. Some typical examples of analog signal processors are audio amplifiers, passive- or active- RC filters, and so on. By contrast, in a digital system each signal is represented by a sequence of numbers. Since these numbers can contain only a finite number of digits (typically, coded in the form of binary digits, or bits) they can only take on discrete values. Also, these numbers are the sampled values of the signal, taken at discrete time instances. Thus both the dependent and independent variables of a 12 INTRODUCTION signal are discrete. Since the processing of the digital bits is usually performed synchronously, a timing or clock circuit is an important part of the digital system. The timing provides one or more clock signals, each containing accurately timed pulses that operate or synchronize the operation of the components of the system. Typical examples of digital systems are a general-purpose digital computer or a special-purpose digital signal processor dedicated to (say) calculating the Fourier transform of a signal via the fast Fourier transform (FFT), or a digital filter used in speech analysis, and so on. By contrast, analog signal processing circuits utilize op-amps, comparators, resis- tors, capacitors, and switches to perform such functions as filters, amplifiers, recti- fiers, and many more. To understand the basic concepts of the most commonly used configurations of an analog circuit, consider the simple analog transfer function Vout (5) b Vi) 24 as +b" ap It is easy to verify that the RLC circuit shown in Fig. 1.1@ can realize this function (Problem 1.1). Although this circuit is easy to design, build, and test, the presence of the inductor in the circuit makes its fabrication in imegrated form impractical. In fact, for low-frequency applications, this circuit may well require a very large valued, and hence bulky, inductor and capacitor. To overcome this problem, the designer may decide to realize the desired transfer function using an active-RC circuit. It can readily be shown that the circuit in Fig. 1.1b, which utilizes three operational amplifiers, is capable of providing the transfer function specified in oo) Figure 1.1, Second-order filter realization: (a) passive circuit; (b) active-RC circuit.1.1 CLASSIFICATION OF SIGNAL PROCESSING TECHNIQUES [1-4] 3 qa 7h e (84g Figure 1.2. Switched-capacitor realization of a resistive branch. Eg. (1.1). This circuit needs no inductors and may be realized with small discrete components for a wide variety of specifications (Problem 1.2). It turns out, however, that while integration of this circuit on a bipolar chip is, in principle, feasible (since the amplifiers, resistors, and capacitors needed can all be integrated), there are some major practical obstacles to integration. These include the very large chip area needed by the RC components, as well as the stringent accuracy and stability requirements for these elements. These requirements cannot readily be satisfied by integrated components, since neither the fabricated values nor the temperature-induced varia- tions of the resistive and capacitive elements track each other. The resulting pole-zero variations are too large for most applications. Prior to mid-1970s, analog circuits such as the one shown in Fig. 1.1 were imple- mented using integrated bipolar op-amps and discrete passive components. In the 1970s two developments made it possible to fully integrate analog circuits in metal- oxide semiconductor (MOS) technology. The first development was the emergence of a technique called switched-capacitor (SC) circuits [6], which is an effective strategy for solving both the area and the matching problems by replacing each resistor in the circuit by the combination of a capacitor and a few switches. Consider the branches shown in Fig. 1.2. Here, the four switches S,, Sz, 53, and S, open and close periodically, at a rate which is much faster than that of the variations of the terminal voltage vy and vg. Switches 5; and 5, operate synchronously with each other but in opposite phase with 5, and 53. Thus when 5S; and S3 are closed, 5, and Sq are open, and vice versa. Now when S, and S; close, C is discharged. When S> and S3 open, $, and S, close, and C is recharged to the voltage tie = v4 — vp. This causes a charge y = C(u, — vg) to flow through the branch of Fig. 1.2. Next, C is again discharged by S2 and S3, and so on. If this cycle is repeated every T seconds (where T is the switching period or clock period), the average current through the branch is then le = 4 = Fon = wy). (2) Thus ig, is proportional to the branch voltage v4 — vp. Similarly, for a branch containing a resistor R, the branch current is i = (//R)(va — vg). Thus the average current flowing in these two branches are the same if the relation R = T/C holds.4 INTRODUCTION C4 Sa op ‘e9 Sols Ses | ty : | YY yy Figure 1.3. Second-order switched-capacitor filter section. Physically, the switches transform the capacitor C, a nondissipative memoried ele- ment, into a dissipative memoryless (i.c., resistive) onc. It is plausible therefore that the branch of Fig. 1.2 can be used to replace all resistors in the circuit of Fig. 1.16. The resulting stage [3] is shown in Fig. 1.3. In this circuit, switches that belong to different “resistors” but perform identical tasks have been combined. Furthermore, the second operational amplifier (op-amp) in Fig. 1.1b, which acted merely as a phase inverter, has been eliminated. This was possible since by simply changing the phasing of two of the switches associated with capacitor C3, the required phase inversion could be accomplished without an op-amp. As Fig. 1.3 illustrates, the transformed circuit contains only capacitors, switches, and op-amps. A major advantage of this new arrangement is that now all time constants, previously determined by the poorly controlled RC products, will be given by expressions of the form (T/C;)C2 = T(C2/C,). Here the clock period T is usually determined by a quartz-crystal-controlled clock circuit and hence is very accurate and stable. The other factor of the time constant is C2/C,, that is, the ratio of two on-chip MOS capacitances. Using some simple rules in the layout of these elements, it is possible to obtain an accuracy and stability on the order of 0.1% for this ratio. ‘The resulting overall accuracy is at least 100 times better than what can be achieved with an on-chip resistor and capacitor for the RC time constant. A dramatic improvement is also achievable for the area required by the passive elements. To achieve a time constant in the audio-frequency range (say 10 krad/s), even with a large (10-pF) capacitor, a resistance of 10-MQ is required. Such a resistor will occupy an area of about 10° j:m?, which is prohibitively large; it is nearly 10% of the area of an average chip. By contrast, for a typical clock period of 10 ys, the capacitance of the switched capacitor realizing a 10-MQ resistor is C= TR = 10-710" = 10-'?F = 1 pF. The area required realizing this capacitance is about 2500 um?, only 0.25% of that needed by the resistor that it replaces.1.1 CLASSIFICATION OF SIGNAL PROCESSING TECHNIQUES 1-4) 5 ‘The second development that made the realization of the fully integrated analog MOS circuits possible was the design of the MOS op-amp. Perhaps the most gener- ally useful analog circuit function is that of the operational amplifier. Prior to about 1977, there existed a clear separation of the bipolar and MOS technologies, according to the function required [1,5]. MOS technology, with its superior device density, was used mostly for digital logic and memory applications, while all required analog functions (such as amplification, filtering, and data conversion) were performed using bipolar integrated circuits, such as bipolar op-amps. Since that time, however, rapid progress made in MOS fabrication techniques made it possible to manufacture much more complex and flexible chips. In addition, new developments occurred in communication technology (such as digital telephony, data transmission via tele- phone lines, adaptive communication channels, etc.) which required analog and digital signal processing circuitry in the same functional blocks. The analog functions most often needed are filtering (for antialiasing, smoothing, band separation, etc.), amplification, sample-and-hold operations, voltage comparison, and the generation as well as precise scaling of voltages and currents for data conversion. The separation of these analog functions from the digital ones merely because of the different fabrication technologies used is undesirable, since it increases both the packaging costs and the space requirements and also, due to the additi interconnections required, degrades the performance. Hence there was strong motivation to develop novel MOS circuits, which can perform these analog functions and which can also share the area on the same chip with the digital circuitry. Compared with bipolar technology, MOS technology has both advantages and disadvantages. MOS device has extremely high impedance at its input (gate) termi- nal, which cnables it to sense the voltage across a capacitor without discharging it. Also, there is no inherent offset voltage across the MOS device when it is used as a charge switch. Furthermore, high-quality capacitors can be fabricated reliably on an MOS chip. These features make the realization of such circuits as precision sample-and-hold stages feasible on an MOS chip [1]. This is usually not possible in bipolar technology. On the negative side, the transconductance of MOS transistors is inherently lower than that of bipolar transistors. A typical transconductance value for a moderate- sized MOS device is around 2.5 mA/V; for a bipolar transistor, it may be about 50 times larger. This leads to a higher offset voltage for an MOS amplifier than for a bipolar amplifier. (At the same time, however, the input capacitance of the MOS transistor is typically much smaller than that of a bipolar transistor.) Also, the noise generated in an MOS device is much higher, especially at low frequencies, than in a bipolar transistor. The conclusion is that the behavior of an amplifier realized on an MOS chip tends to be inferior to an equivalent bipolar realization in terms of offset voltage, noise, and dynamic range. However, it can have much higher input impedance than that of its bipolar counterpart. ‘As a result of these properties, the largest use of the MOS op-amp is expected to be as part of an MOS-LSI (large-scale integration) chip. Here the design of the op-amp can take advantage of the important performance specifications that are needed. The loading of the op-amp is often very light and usually only a small-6 INTRODUCTION valued capacitor has to be driven by these op-amps. Switched-capacitor circuits fall especially into this category, where element-value accuracy is important but the signal frequency is not too high and the dynamic range required is not excessive. Voice- and audio-frequency filtering and data conversion are in this category and represent the bulk of the past applications. In addition to frequency-selective switched-capacitor filtering introduced in Fig. 1.3, which has been the most common application of MOS op-amps, there are many other functions for which op-amps and comparators can be used. These include analog-to-digital (A/D) and digital-to-analog (D/A) data conversion, programmable- gain amplification for AGC and other applications, peak-detection, rectification, zero-crossing detection, and so on. They have also been used extensively in large mixed-signal analog/digital systems such as voice codecs, high-speed data communi- cation modems, audio codecs, and speech processors. This range will expand contin- uously as the quality (bandwidth, dynamic range, power consumption, etc.) of the components, especially op-amps and comparators, improves. 1.2, EXAMPLES OF APPLICATIONS OF OP-AMPS AND COMPARATORS IN ANALOG MOS CIRCUITS In this section, a few selected examples of practical analog MOS circuits are given where CMOS op-amps and comparators are used extensively. Of course, the reader should not expect to understand the details of these systems at this stage. However, the diagrams may give an idea of the potentials of these components in analog signal processing. As mentioned earlier, one of the most important applications of CMOS op-amps is in switched-capacitor filters. Figure 1.4a shows the circuit diagram of a seventh- order switched-capacitor filter. Its measured frequency response is shown in Fig. 1.4b, The measured passband variation for the device is less than 0.06 dB. This represents a superior performance, which could not have been achieved without ‘extensive trimming using any other filter technology. An obvious application of a CMOS op-amp is the realization of charge-mode digital-to-analog converters (DAC). It can be obtained by combining a programmable capacitor array and an offset-free switched-capacitor gain stage. An example of an N-bit charge-mode DAC is shown in Fig. 1.5, where V,,; is a temperature-stabilized constant reference voltage. The output of the DAC is the product of the reference voltage and the binary-coded digital signal (by, bz, bs,..., by). In Chapter 6 the design of such circuits is discussed in some detail. Modulators, rectifiers, and peak detectors [6] belong to an important class of nonlinear circuits, which can be implemented with a combination of op-amps and comparators. In an amplitude modulator the amplitude of a signal x(t) (usually called the carrier) is varied (modulated) by m(,), the modulating signal. Hence the output signal y(t) is the product of x(r) and m(t), or y(t) = x(t\m(t). A periodic cartier signal, which is readily generated from a stable clock source, is a square wave alternating between two equal values + V. An easy way to perform modulation with-raujy ssed-mo] sonsedeo-poyortms Jopwo-tpvanas v Jo asuodses Aouanbaxy pamnsvau (q) ‘wex8eIp wna (P) “pT aanBiy ty8 INTRODUCTION o 4000 8000 12000 18000 frequency (Hz) o Figure 1.4. Continued top plate bottom plate Figure 1.5. Multiplying digital-to-analog converter.1.2. EXAMPLES OF APPLICATIONS OF OP-AMPS & COMPARATORS INANALOG MOSGIRGUITS = 9 Figure 1.6. Switched-capacitor modulator with two clock signals. a square-wave carrier is to switch the polarity of the input signal m(1) periodically. A stray-insensitive switched-capacitor modulator circuit which performs according to this principle is shown in Fig. 1.6. The clock phases , and ¢ are operated at the fast clock rate w,, while the phase ¢, changes at the slow carrier-frequency rate 4. Normally, w, is much larger (by a factor of 30 or more) than w,4. Another nonlinear circuit is a full-wave rectifier that converts an input signal viq(t) to its absolute value |via(t)]. A simple way of implementing a switched-capacitor full- wave rectifier is to add a comparator to an amplitude modulator. The circuit of a switched-capacitor full-wave rectifier based on the modulator of Fig. 1.6 is shown in Fig. 1.7a. Here A is set to “1” if uj, > 0 and to “0” if 4, < 0, while B is set to A by the comparator and the latch that follows it each time ,, goes high. The signals A and B then set the polarity of the transfer function so that it inverts the negative input signals, but not positive ones. Figure 1.7b shows an auto-zeroing comparator, which is discussed in detail in Chapter 5. A peak detector is a circuit whose output holds the largest positive (or, if so specified, negative) voltage earlier attained by the input signal. An MOS peak detec- tor is shown in Fig. 1.8. The op-amp acts as a comparator, with vou = Vmax and Up as its inputs. If y > Vmax, the op-amp output goes high and M, conducts, charging C until vow ~ vin is reached. If ti, < Vinax, the op-amp output is low, M; is cut off, and vx = Vmax is held by C. One of the most important applications of the comparators is in A/D converters. A successive-approximation A/D converter is one type of medium-speed Nyquist- rate converter that can be realized using a programmable capacitor array (PCA) and a voltage comparator. A 5-bit converter is shown in Fig. 1.9. For high-speed opera- tion, flash A/D converters can be used. In this configuration an array of 2” compara- tors are used for an N-bit A/D converter. A conceptual diagram of an N-bit flash10 INTRODUCTION (a) % ry - + og ‘n Yout %24| ) Figure 1.7. Switched-capacitor full-wave rectifier: (a) complete circuit; (b) offset-compen- sated comparator. AID convener is shown in Fig. 1.10. Analog-to-digital converters are discussed in detail in Chapter 7. With the recent rapid progress made in MOS fabrication techniques and the emergence of the submicron CMOS technology, many intricate systems containing analog and digital functions have been combined in a fully integrated form. One drawback of the submicron CMOS technology is the reduction in the power supply voltage, which results in a reduced signal swing and hence a lower dynamic range To improve the performance of the system and reduce the effects of noise injection from the power, ground, and clock lines, most modern high-performance mixed-1.2, EXAMPLES OF APPLICATIONS OF OP-AMPS & COMPARATORS IN ANALOG MOS CIRCUITS 11 Yop m1 Yout I Figure 1.8, Continuous-time peak detector. Q,- -2¢v,, e to the digital logic @ Figure 1.9. Five-bit successive-approximation A/D converter.12 INTRODUCTION Figure 1.10. Conceptual diagram of an N-bit A/D converter. signal integrated circuits make use of fully differential signal paths. With op-amps and comparators, the fully differential signal paths require fully differential outputs as well as inputs. and they are known as fully differential op-amps and comparators. Since this technique uses symmetrical layout, many of the noise voltages (power supply noise, clock-feedthrough noise, offset voltages) appear as common-mode signals. They are to a considerable extent canceled in the differential output voltage Zoe at all frequencies. A high-frequency high-Q switched-capacitor bandpass filter that uses a fully differential signal path is shown in Fig. 1.11. This filter is typically used in a radio-frequency (RF) receiver system, which requires high selectivity at high frequencies [7}. The two complementary switch blocks (X; and X2) are shown in Fig. 1.12. The filter uses fully differential single-pole transconductance folded- cascode op-amps with source-follower common-mode feedback as illustrated in Fig. 1.13 [8]. This op-amp achieves 100-MHz unity-gain bandwidth and 60 dB of gain with 1 mA of total current consumption. Fully differential op-amps are discussed in detail in Chapter 4.“ray ssedpueq ajod-|je 2oy2edes-payowas xopso-WIXIS & Jo wesBeIP OMEWOHDS “TTT aN14 INTRODUCTION X fs + = Figure 1.12. Two switch blocks for a double sampling. ‘Another application of the fully differential op-amps is in oversampling, or delta- sigma A/D converters. The oversampling converters operate at sampling rates of 16 to 512 times the Nyquist rate and increase the signal-to-noise ratio by subsequent filtering. The oversampling techniques lend themselves most favorably to applica- tions that require a relatively low frequency (<1 MHz) and high resolution (>12 bits). The most obvious application of delta-sigma converters is in digital telephony ss Figure 1.13. Wideband op-amp for the filter.1.2, EXAMPLES OF APPLICATIONS OF OP-AMPS & COMPARATORS IN ANALOG MOS CIRCUITS 15. Veet] [Vref Veet" [rot _ i j $4 ' s,| °F en Li x | ¥ “so i} fet 2 fem 2 war! toe wat by @ (o) Figure 1.14. (a) Fully differential CMOS implementation of a second-order delta-sigma modulator; (b) two-phase clock scheme. and digital audio. Figure 1.14 shows a fully differential, switched-capacitor CMOS implementation of a second-order delta-sigma modulator [9]. It consists of two para- sitic insensitive integrators, a comparator that serves as a 1 bit A/D converter, and a two-level (1-bit) D/A converter. Use of a fully differential configuration attenuates power supply noise, clock feedthrough, and even-order harmonic distortion. The modulator operates on (wo-phase nonoverlapping clocks consisting of a sampling phase and an integration phase. It achieves 16-bit dynamic range with an oversam- pling ratio of 256 and a signal bandwidth of 20 kHz.16 INTRODUCTION As the examples above illustrate, present-day CMOS op-amps and comparators and their use in analog MOS circuits have reached a certain level of maturity. Al- ready, almost any analog signal processing task in the voice- or audio-frequency range has a possible solution using such circuits. As fabrication technology and circuits design techniques continue to advance, the speed and dynamic range of these circuits will increase, allowing their use in such large-volume applications as video and radio systems, image processing, high-speed transmission circuits, and so on. PROBLEMS 1.1. Show that the circuit of Fig. 1.1a can realize the transfer function of Eq. (1.1). What should be the clement values R, L, and C? 1.2. Calculate the transfer function of the active-RC circuit of Fig. 1.1b. Assume that the circuit is to realize the transfer function of Eq, (1.1). Write the available equations for the element values. How many element values can be chosen arbitrarily? REFERENCES 1. R. W. Brodersen, P. R. Gray, and D. A. Hodges. Proc. IEEE. 67. 61-75 (1979) 2. Y. Tsividis, Proc. IEEE, 71, 926-940 (1983), 3. R. Gregorian, K. W. Martin, and G. C. Temes, Proc. IEEE. ~! 941-966 1983. 4. D. J. Allstot and W. C. Black, Jr., Proc. IEEE, 71, 967-986 11983 5. P.R. Gray and R. G. Meyer, Analysis and Design of Analog Ince eraed Circutts. 2ad ed. Wiley, New York, 1984. 6. R. Gregorian and G. C. Temes, Analog MOS Integrated Circutts for Signal Processing, Wiley, New York, 1986. . Bang-Sup Song and P. R. Gray, JEEE, J. Solid-State Circuits. SC-21(6), 924-933 (1986). 8. T.C. Choi, R. T. Kaneshira, R. W. Broderson, P. R. Gray. W. B, Jett, and M. Wilcox, IEEE J. Solid-State Cirewits, SC-18(6), 652-664 (1983), 9. B. P. Brandi. D. E. Wingard, and B. A. Wooley. IEEE J. Solid-State Circuits, SC-26(4), 618-627 (1991) _CHAPTER 2 a MOS DEVICES AS CIRCUIT ELEMENTS In this chapter the physics of MOS (metal-oxide semiconductor) devices is discussed briefly. The most important and simplest current-voltage relations are given, and simple models introduced for MOS transistors in linear operation. The discussion here is in the simplest possible terms, aimed at providing some physical understand- ing of the highly complex device operation for the circuit designer. Precision and depth have regretfully been sacrificed in the process. The ambitious reader is referred to the excellent specialized works listed as references at the end of the chapter. 2.1. SEMICONDUCTORS In metals (e.g., aluminum, copper, silver) that are good electrical conductors, the atoms are arranged in a regular crystal array. The electrons from the outer (valence) shell of the atoms are free to move within the material. Since the number of atoms, and thus the number of free electrons, is very large (on the order of 107° cm™*), even a small electric field results in a large electron current—hence the high conductivity observed for these metals. The picture is quite different for an insulator such as silicon dioxide (SiOz). Here the valence electrons form the bonds between adjacent atoms and hence are themselves tied to these atoms. Thus no frec clectrons are available for conduction and the conductivity is very low. Semiconductors (such as silicon or germanium) are in between conductors and insulators in their electrical properties. At very low temperatures, the valence elec- trons are bound to their atoms, which again form a regular lattice. However, as the temperature is raised, due to the thermal vibrations of the atoms, some bonds will be broken, and an electron escapes from each of these bonds. Such electrons are 718 MOS DEVICES AS CIRCUIT ELEMENTS capable of conducting electricity. Furthermore, each fugitive electron leaves a charge deficit (called a hole) behind in the bond. A valence electron in a bond close to a hole can easily move over, filling the hole and leaving a new hole in its own bond. The effect is the same as if the hole had moved from one bond to the next. Since the hole ‘‘moves’’ in a direction opposite that of the moving valence electron, in an electronic field it behaves like a positively charged particle. Electrical conduction is thus possible for a semiconductor at room temperature. The density of thermally gencrated electrons and holes is, however, much smaller than that of the free electrons in metal. Typical numbers are 10'° charge carriers per cubic centimeter for silicon and 10" in germanium. In what follows, the currently dominant material, silicon, is discussed exclusively. Adding foreign elements (dopants) to the pure silicon can raise the number of free charge carriers in a semiconductor. Silicon (and germanium) has four valence electrons. If an atom of an element with five valence electrons (such as arsenic, phosphorus, or antimony) is added to the semiconductor, it may take the place of a silicon atom in the crystal lattice. Thus four of its valence electrons will participate in the four bonds tying the atom to adjacent semiconductor atoms in the lattice. The fifth valence electron of the foreign atom, however, will not have a place in any bond and will thus be free to move away from its parent atom. Hence such a dopant element (called a donor, since it contributes free electrons to the semiconductor) enhances the conductivity of the material. Adding atoms of an clement with three valence electrons will also contribute to the conductivity. Now there will be a bond lacking a valence electron for each dopant atom. Thus each such atom creates one hole. These dopants (e.g., boron, aluminum, and gallium) are called acceptors, since the holes will propagate by accepting bound valence electrons from adjacent semiconductor atoms. In doped semiconductors there will be carriers due to thermal effects as well as to the donor (or acceptor) atoms. Materials containing donors will thus have both free electrons and holes, but there will be more electrons than holes, Such semicon- ductors will be called n-type, where n stands for negative. Materials containing acceptors will have a majority of holes; they are called p-type semiconductors, where p stands for positive. A semiconductor structure can also be fabricated that contains two adjacent re- gions of different types (Fig. 2.1). The surface joining the two regions is called a pn junction. When the junction is fabricated, the random thermal motion of the solder joint a type wire Z Figure 2.1. A pn junction diode. pn junction2.1. SEMICONDUCTORS 19 ++++ 4+ + 3 “| Figure 2.2. [on layers in a pn junction. majority carriers (elecurons in the n-type region, holes in the p-type region) will cause electrons to spill over from the n-type region to the p-type region. Vice versa, holes will move from the p-type region to the n-type semiconductor. Thus this random motion (called diffusion) results in the p-type semiconductor being charged negatively while the n-type region is charged positively. The effect will be strongest near the junction: There, in the p-type region, the negatively charged acceptor atoms will no longer be neutralized by holes, and (in the ri-type region) free electrons will no longer surround the positively charged donor ions. Hence in this area a dipole layer of fixed ions will be formed (Fig. 2.2). The electric field € created by the dipole opposes further majority-carrier diffusion, but it helps the thermally generated minority carriers (electrons in p-type regions, holes in n-type regions) to migrate from one region to another. Thus, after a short transient, equilibrium will be obtained. Four different carrier currents will flow: Majority carriers will move hy diffusion from region to region despite €, and minority carriers will flow aided by €. These currents cancel each other in equilibrium, since the effects of € compensate for the larger number of available majority carriers. The equilibrium will be upset if a voltage source is connected to the wires soldered to the semiconductor (Fig. 2.3). Assume first that the polarity of the source is such that it makes the p-region more positive with respect to the n-region; that is, v > 0 in Fig. 2.3. Then v will reduce € and thus increase the current of majority carriers held back by € from spilling over the boundary. Even a small reduction of € caused by, say, a battery of v = 0.8 V can result in a large majority-carrier current (say, depletion region Figure 2.3. Circuit for testing a pn diode,20 MOS DEVICES AS CIRCUIT ELEMENTS Nama) Figure 24, Current versus voltage 0.5 “ characteristics of a pn junction diode. 's i = 1 A) in the circuit. Hence v with the polarity indicated will be called forward voltage and i forward current. Let us now reverse the polarity of the voltage source so that v < 0 in Fig, 2.3. Now v will aid & in obstructing the flow of majority carriers from region to region. If vis large enough, the majority current is essentially eliminated, and only the flow of minority carriers (electrons moving from the p region to the n region, and holes moving in the opposite direction) remains. Since the number of minority carriers is, however, small and nearly independent of v, the resulting net current will be small and nearly constant. This is the case of reverse voltage and current. With the reference directions used in Fig. 2.3, now i < 0. Figure 2.4 illustrates the overall behavior of i as a function of v. A detailed theoretical analysis [1, Sec. 4.3; 2, Sec. 6.6] reveals that the describing equation is, to a good approximation, i = Ife — 1), (2.1) Here J is the saturation current, determined by the geometry and the material properties of the device, g ~ 1.6 X 10-9 C is the electron charge, and k = 1.38 X 107” J/K is Boltzmann’s constant. T is the temperature of the semiconductor, in Kelvin. At room temperature (T = 300 K), kT/q ~ 26 mV. Is is usually very small, on the order of 10~ A or less. Thus i increases exponentially with v for v > 0, while i= —Jg and is very small if v < 0 (Fig. 2.4). The behavior of the region directly adjacent to the boundary between the p and n regions is of prime importance. As mentioned earlier, the majority carriers are very sparse in this area; some have immigrated into the other region, and the others have been pushed back into the inside of their native region by the field €, Hence the border area contains only the fixed ions, charged negatively in the p-type region and positively in the n-type material (Fig. 2.3). This area is hence called the depletion region. Its width increases with increasing €; hence it will be greater (smaller) for reverse (forward) voltage v. Due to the field €, a voltage 4; (often called the built-in voltage) appears across the depletion region for v = 0. The total potential across the junction, for v¥ 0, is thus ¢;'— v. Typically, @; = 0.5 to 1 V. For v < 0, the pn junction can be regarded as a capacitor, since only a small22, MOS TRANSISTORS = 27 saturation current /s flows for a de voltage v, and since adjacent positive (+ Q) and negative (— Q) charges are stored in the depletion region (Fig. 2.3). Since the charge stored is a nonlinear function of v, the capacitance is nonlinear. We shall define the capacitance C by the incremental relation C = dQ/du It can then be shown [1, Sec. 3.3; 2, Sec. 6.5] that for the device illustrated in Fig. 2.3, rr c- (eta + uNath 22) o + lf holds. Here 1 KHz) signal rather than a constant voltage. Consider next the structure shown in Fig. 2.7. A new feature is the presence of two n* (ie. heavily doped n-type) regions in the p-type material. The one on the left will be called the source; a voltage us is connected to it. The n* region on the * Often, the oxide thickness / is measured in angstroms (1 A = 10~® em), Usual values of / are between 50 and 200 A.22. MOS TRANSISTORS 23. Figure 2.7, MOS transistor. right will be called the drain; its voltage is denoted by vp. The top metal electrode will be called the gate; its voltage is vg. The body of the semiconductor is usually called the substrate or bulk. The overall device is the MOS transistor. Its operation is discussed briefly next. Let the source be grounded, so that vs = 0. Also, let up have a sutall positive value, say 0.5 V. We will consider the behavior of the drain current ip as vg is raised from zero to higher positive values. Since the gate is insulated from the rest of the device by the oxide layer, it will not conduct any current. The n° drain region and the surrounding p-type substrate form a pn junction. Since the substrate is grounded, while vp > 0, this junction is reverse biased. Hence for ug = 0, in ~ 0. As ug is increased, the region R under the gate will first be depleted, then inverted, as discussed earlier in connection with Figs. 2.5 and 2.6. When R is depleted, ip remains Zero, since the area around the drain is still reverse biased. However, the situation changes when ug is so large that inversion occurs, so that R is filled with electrons. Now, a layer containing mobile electrons, called an inversion layer or channel, connects the drain to the source. Since the drain is positive with respect to the source, electrons will flow from the source to the drain and a positive current ip > 0 will be observed. The smallest voltage vg necessary to produce a channel is called the threshold voltage and is denoted by Vr. Usually, Vz is given as the ve value needed for ip = 1 wA; it may range from a fraction of a volt to several volts. It should be noted that for the structure of Fig. 2.7, most of the electrons in the channel do not originate from thermal effects in the bulk; instead, they are drawn by the electric field due to vg out of the source. Some electrons are also drawn from the drain; however, since vp > 0, the drain—substrate junction is more reverse biased, and hence it is harder for electrons to escape from the drain. Since a potential difference vp exists between the two ends of the channel, the electrons in the channel will be attracted to the drain. Therefore, in addition to the random thermal motion of the electrons, a steady motion (called drift) will occur, which causes the current flow. For small vp, the channel will therefore behave as a resistor, and hence ip ~ vp/R, where the channel resistance R is given by L R= Wald (2.4)24 MOS DEVICES AS CIRCUIT ELEMENTS. Figure 2.8. Pinch-off in an MOS transistor. Here L is the length and W the width of the channel, and y,, is the mobility of the electrons in the channel,* defined by the relation (electron drift velocity) = (mobil- ity) X (electric field). Finally. Q, is the charge density (in C/cm”) of the electrons in the channel. Since vg can be considered as the sum of two terms,V; (necessary to maintain the depletion region under the channel) and vg — Vz (necessary to maintain the channel), we have Q, = —Cox (We — Vr), (2.5) where Cox = €ox/l is the capacitance (per unit arca) of the oxide layer separating the gate from the channel. Hence, for small vp (i.¢., vp < ug — Vz), the relation Ww In = Wi€ox 7 (a — Vr 26) holds. Thus the transistor acts as a resistor, with resistance R = [p,Cox W/L(we — Vz)I7! controlled by ug. If up is increased so that it is no longer negligible compared to vg, Eq. (2.6) will become inaccurate. Since the potential of the channel at the grounded source is zero while at the drain it is vp, we can assume that its average potential is vp/2. Hence the average voltage between the gate and channel is (vg — vp/2). Replacing ug by (vq — vp/2) in Eq. (2.6) gives . w ip = PsCon T (x = Vy = hon 27 Equation (2.7) remains a good approximation for up < vg — Vz. This range is called the linear region (or triode region) of operation of the MOS transistor. When vp = uc — Vr, anew phenomenon occurs. Consider the situation illustrated in Fig. 2.8, where only the structure near the semiconductor surface is shown, magni- * The mobility in the bulk of the semiconductor is higher. since 1 decreases with the concentration of ionized impurities. Typical values are pty = 1000 cm?/V - s for Np = 10! cm7*, while tq = 100 cm*s Vs for Np = 10" cm™*.22. MOS TRANSISTORS = 25 fied. As the figure indicates, due to the variation of the potential along the channel, the charge density Q,, decreases near the drain. If vp = vg — Vz, at the drain the gate-to-channel voltage is no longer sufficient to maintain the channel. Thus the depletion region surrounding the source, the channel, and the drain extends all the way to the surface. This phenomenon is sometimes called pinch-off, and the region where it occurs is the pinch-off point (Fig. 2.8). If vp is increased further, the pinch- off point will move toward the source, since the area where ug — up = Vy will increase. Hence the channel will now extend only from the source to the pinch-off point, the latter being somewhere under the gate. The region between the pinch-off point and the drain is depleted. Electrons from the channel are injected into this depletion region at the pinch-off point and are swept to the drain by the field created by the potential difference between the drain and the pinch-off point. The voltage ups & up — ts is thus divided between the two series-connected regions: the channel between the source and the pinch-off point, and the depletion region between the pinch-off point and the drain. Clearly, the latter has a higher resistance, and hence most of ups in fact appears across it. Any increase of vp will, to a good approxima- tion, result in an equal voltage increase across the depletion region and will hardly change ip. Thus, for vp > ug — Vr, from Eq. (2.7), in(ep) = insa 2 ipW@nsst) (2.8) = be Fug — vn. This phenomenon is called saturation; ups. = ug — Vr is the drain saturation voltage and ipsa: as given by Eq. (2.8), is the drain saturation current. The drain current does, in reality, increase somewhat with increasing vp. This can be attributed to the move of the pinch-off point toward the source for increasing up and hence to the shortened channel; as Eq. (2.8) indicates, ip increases as L is reduced. As an approximation, this effect (often called channel-length modulation) can be included in the formula for ip (vp) in the form of an added factor (1 + dup). Here is a device constant that depends on L, on the doping concentration of the substrate, and on the substrate bias (discussed in the next section). For L ~ 10 ym, typically X ~ 0.03 V-); generally, & WL. It is usual to introduce the abbreviations k” the saturation current given by Eq. (2.8) becomes HnCon/2 and & 2 K (W/L). Then ip = kag — VrPC + dep), ug = Vn (2.9) which incorporates channel-length modulation. Figure 2.9 shows the variation of ip with vg for constant vp. Figure 2.10 illustrates its dependence on up for various ug values, Where ¥c1 < Ug2 < Vox ~ All derivations of this section were performed for the structure shown in Fig. 2.7, whose source, drain, and channel were all n type. This device is called an n- channel MOS, or NMOS transistor. A similar arrangement can be constructed by creating p* drain and source diffusions in an n-type substrate. Now a negative ug is needed to create a p-type channel under the gate, and a negative up is used to26 MOS DEVICES AS CIRCUIT ELEMENTS, ‘or Figure 2.9. Drain current versus gate voltage characteristics of an MOS tran- * ‘a sistor. T attract the holes in the channel to the drain. Also, ip will be negative if the reference direction of Fig. 2.7 is used. The resulting device is called a p-channel MOS or PMOS transistor. Formulas (2.3) to (2.9) remain valid if some small changes are made. The mobility 41, of electrons must be replaced by p1», the hole mobility in the channel. As would be expected from the more elaborate mechanism of hole conduction, jt, < }1,. Typical mobility values in the channel region for an impurity concentration of 10'° cm™? are y,, = 1000 cm7/V « s and pp, = 400 cm7/V - s. The electron charge density Q, in the channel is to be replaced by @,, the hole charge density; also, a negative sign must be included in Fags. (2.6) to (2.9) to account for the change in the charge of the carriers. Finally, vp must be replaced by |vp| in Eq. (2.9), since now vp < 0. In conclusion, Eq. (2.7) becomes ip = —2k (x —Vr- “| vp. (2.10) Here k A ,C,,WI2L and Vr <0, Equation (2.10) describes the drain current charac- teristics in the linear range. The behavior of ip in the saturation region can be obtained by modifying (2.9): ip = —k(0g — VrP(L + > fen)). (11) '0 Vp = Yq Vr linear -— | > saturation region Yee region Figure 2.10. Drain current versus drain-to-source voltage characteristics V@1 \p of an MOS transistor.23. MOS TRANSISTOR TYPES: BODY EFFECT 27 rain drain gate ----« bulk or gate bulk (a) NMOS drain or gate bulk. ‘source (8) PMOS drain gate —F--.+ bulk ‘source (e) Mos Figure 2.11. Transistor symbols. The circuit symbols used for NMOS and PMOS transistors are shown in Fig. 2.11a and 6, respectively. If the type is unimportant, the simplified symbol of Fig. 2.11c may be used for both NMOS and PMOS devices. Since the operation of the devices described in this section is dependent on the electric field induced by the gate voltage, they are called field-effect devices (FETs), or MOSFETs.* ince PMOS transistors are more easily fabricated than NMOS transistors, they ally predominant. However, later, when the techniques for the reliable production of NMOS devices were developed, the latter became standard. The main reason for this is the higher mobility of electrons, which makes the NMOS transistors faster than PMOS transistors. 2.3. MOS TRANSISTOR TYPES: BODY EFFECT The MOS transistors described in Section 2.2, both NMOS and PMOS types, share several features. In the structure, the gate is insulated electrically from the rest of * Since the charge carriers here are either electrons or holes (not both), FETs are also sometimes called unipolar devices, to contrast them with bipolar transistors, in which both electron and hole currents exist.28 MOS DEVICES AS CIRCUIT ELEMENTS: —{ Ho depletion MOSFET Figure 2.12, Symbols for depletion- mode transistors. the device by the SiO, layer under it, Hence it is often called an insulated-gate field-effect transistor (IGFET). Also, the voltage vg induces and enhances the drain current. Thus the devices described operate in the enhancement mode. Its also possible to fabricate an MOS transistor that conducts drain current when vg = 0. For example, an n-type layer can be introduced by doping, which connects the source and drain of an NMOS device. With such a doped channel, the field of the gate is not needed to produce an inversion layer: the region R (Fig. 2.7) now has a ‘‘built-in’’ conducting n-type channel. However, if a negative gate voltage is applied, the field thus created will repel electrons and create a depletion layer in the channel adjacent to the SiO, surface, thereby reducing the conductivity and thus the drain current. If the magnitude of the negative gate voltage is sufficiently large, the channel becomes completely de- pleted and ip ~ 0 results. The value ve at which this occurs is again called threshold voltage and is denoted by V7. Now, however, Vr < 0. Such a device is called a depletion-mode FET. It should be noted that even without a doped layer. an NMOS transistor can conduct for vg = 0 due to oxide charges [1, Sec. 7.4] if the bulk is very lightly doped. It is also possible to create a depletion-mode PMOS device, with V; > 0, by establishing a p-type doped channel. The relations (2.6) to (2.11) remain valid for depletion-mode devices if the value and sign of Vr is chosen appropriately, as described above. Two symbols often used to denote depletion-mode MOSFETS are shown in Fig. 2.12. A totally different structure can also be used to produce a depletion-mode field- effect transistor (Fig. 2.13). Here, a lightly doped n-type layer (channel) connects the n* source and drain regions and the gate is a p* region implanted in this layer. Hence, for vs = vg = 0 and v¢p > 0, a drain current will flow. If ug is made nega- tive, the p* implant acting as the gate will be surrounded by a depletion layer; the greater |uc|, the deeper the layer. The mobile electrons in the channel cannot Figure 2.13. Junction field-effect transistor.2.3. MOS TRANSISTOR TYPES: BODY EFFECT 29 enter this depletion layer, or the one along the pn junction between the channel and the substrate. Hence the effective cross section of the channel is reduced as |vg| is increased, At some value u = Vp (Vp < 0), ip becomes zero (in practice, < 1 pA). Thus Vp plays the same role as Vz for a depletion-mode MOSFET; it is called the pinch-off voltage. It can be visualized as the gate voltage, which causes the two depletion regions in the channel to merge, leaving no conductive path between source and The device described and shown in Fig. 2.13 is called an n-channel junction field- effect transistor FET), since its gate is separated from the rest of the device by a reverse-biased pn junction rather than by an SiO, layer as for the MOSFET (IGFET). Since the JFET is hardly ever used in analog MOS integrated circuits, it is not discussed in detail here. A clear description of its physics and current—voltage charac- teristics is given in Sec. 2.5 of Ref. 1. Next, a key limitation (called the body effect) of MOSFETs used as analog circuit elements is described. In the discussion in Section 2.2 it was always assumed that both the bulk and source are grounded, so that vp = ws = 0 held. Often, circuit considerations make this convenient arrangement impossible and us # vy must be used. Obviously, the voltage uy — vg must be such that the source—bulk junction is reverse biased, otherwise, a large junction current will flow inside the transistor. This current may damage the device, and in any case will impede its proper operation. Thus, say, in an NMOS transistor, the bulk must be biased to make it negative with respect to both source and drain. If the source potential is not zero, the voltages vg and vp must be replaced in all equations by rigs = tg — us and tp5 = Up — wy, respectively. In addition, the depletion region around the channel (Fig. 2.8) will become wider if the reverse voltage between the bulk and the source (and hence the channel) is increased. Since the voltage ue = Vy is the gate voltage necessary to maintain the depletion region (without creating a channel), Vr will increase in magnitude. The dependence of Vr on the voltage vsz 4 vs — vp can be shown [1, Sec. 8.2] to be in the form [vr] = [rol + YV2l6r1 + [esa] — V21bp))- (2.12) Here, V7 is the threshold voltage for usg = 0 and ¥ is a device constant given by V2€.qM imp (2.13) Ox In Eq. (2.13), és 18 the permittivity of silicon: ey = €oKs, Ks ~ 11.7. Also, Nimp is the density of the impurity ions in the bulk. For NMOS, Nimp = Na, the acceptor ion density; for PMOS, Ninp = Np, the donor ion density. For example, for Ninp = 10'S cm™* and 800 A oxide thickness (i.e., Cy, * 4.4 x 107 F/em?), y ~ 0.423V!”, Finally, $, is a material constant of the bulk; its value is around 03 V. * , 2 (E, — jg, where £, is the intrinsic Fermi energy and E, the Fermi energy of the semiconductor U1, p. 318}30 MOS DEVICES AS CIRCUIT ELEMENTS TABLE 2.1. Key Units and Constants for MOS Transistors 1pm = 107¢em = 10°A 1 mil = 25.4 pm = 0.0254 mm Electron charge (magnitude): ¢ = 1.6 x 107 C Permittivity of free space: € 86 x 10-' F/em Permittivity of silicon: ¢ = Ks = 1.04 x 107 !? Ffem; Ky = 11.7 Permittivity of silicon dioxide: €,, = 6K. = 3.5 X 10-" Flem; K,. = 3.9 Oxide capacitance: Cy. = éx/fox 5X 107 87et Flem* Intrinsic carrier concentration: n, = 1.5 X 10! em~?, T = 300 K Boltzmann’s constant: k = 1.38 x 10-* J/K; kTVq (at T = 300 K) = 0.026 V Electron mobility in Si (Nimp = 10'7 cm, T = 300 K): 670 cnv/V - s Hole mobility in Si (Nimp = 10'’em=, T = 300 K): 220 om2/V - s Body-cffect coefficient: y = \/7MaMen fox 1.67 x 10-3 sp VNB V" Bulk potential: y = — jy Mine = 0.026 In (0.67 x 10>" NE) This phenomenon, the body effect, is a major limitation of MOS devices operated with vs # vp; its evil influence will be lamented repeatedly later in the book. As Eqs. (2.12) and (2.13) show, to reduce the body effect, Nimp Should be made small. However, for very small Ny values (say, N4 < 10!3 cm~7), an NMOS may behave as a depletion-mode device, as explained earlier. Thus the body effect cannot be climinated completely. Some key constants and formulas on MOSFETs are summa- rized in Tables 2.1 and 2.2. 2.4. SMALL-SIGNAL OPERATION AND EQUIVALENT CIRCUIT OF MOSFET TRANSISTORS Earlier the physical principles and basic operation of MOS transistors were discussed briefly, and formulas derived that gave the drain current as a function of the voltages and/or currents at the various terminals of the device. In these earlier discussions it was assumed that all voltages and currents were constant or that they varied suffi- ciently slowly so that all capacitive currents (and hence all capacitances themselves) could be neglected in the discussions. On the other hand, the formulas derived were valid for large as well as small voltage and current variations. In many important linear applications (such as operational amplifiers, discussed in Chapter 4) the voltages and currents of the transistor vary so rapidly that capacitive effects cannot be ignored, and hence the capacitances of the device must be included in the analysis. At the same time, in such circuits the signals are sufficiently small, so that linear approximations may be used in all nonlinear relations. This simplifies the equations and permits the use of linear models (simple linear equivalent circuits) for these nonlinear devices.(ble A — 852 — | @lzAyh — e-"¢4A) = 4A “ctTNen-CA — 2%2—),_T © X ary “ Te. CN — 1) oth — $0) Fasoag = OF (*p pue & jo sonqea up 405 1°7 9198 998) (IZA — #8 + L2@1Z AA + 9 C4A) = 4A ‘TNen CA + 2%), 7 2» ¥ a1 saay + 1) ta — 8) —Te_ = (stay TCA ) aA " Fal - [2a] < [saa] ‘Hal < [| oar uonemieg Fal ~ [$a] > baal ‘Hal < [$a] sa, (& a =) Joye = 4 onl -!n a) Tega = a4 :uorax apouy. SOWd SOWN uogesdQ jo uoI3zay wopeiedg Kouambery-ao7y [eusg-a81e7] Uy SLAISOW 409y suopepy w9sINy-UPIG “TZ ATAVL a32 MOS DEVICES AS CIRCUIT ELEMENTS: In the following discussion, we concentrate on the linearized approximation and modeling process for MOSFETs operating in their saturation regions, which is the usual condition for linear (analog) operation. Afterward, we give a brief overview of the linearization and modeling for devices that operate in their triode (nonsatu- rated) or cutoff region. Assuming an NMOS transistor, and combining Eqs. (2.9) and (2.12), the relation ip = Kues — Vy ~ ¥WV20_ + vse + ¥V2b,)°CL + dvps) (2.14) results, Here we used ucs & ug — us and ups A up — ws to replace vg and up, since in general vs # 0. For small variations of ip, vcs, Ups, and vsg, the nonlinear expression (2.14) can be replaced by a first-order Taylor approximation. Specifically, near a constant bias point i9, = f (ves, v2s, vs) we can write 9 dip = 72 B+ Mip=B+ iD ip = Ip (22 (2.15) Here (dip/Augs)° and so on denote the partial derivatives evaluated at the bias point. Aip is the deviation (increment) of ip from its bias value; Aves, Aups. and Ausa are the increments of vgs, ups, and usp. All deviations must be small for Eq. (2.15) to hold. If only the incremental (small-signal ac) components are of interest, Eq. (2.15) can be written as Min = 8m Aves + 84 Avps + 8m» Ausp, (2.16) fe Figure 2.14. Low-frequency equivalent circuit of a MOSFET.2.4. SMALL-SIGNAL OPERATION AND EQUIVALENT CIRCUIT OF MOSFET TRANSISTORS 33. where (2.17) dip &mS (2) , Here g, is the (incremental) drain conductance: g,, and g,,. are transconductance, that can be represented by voltage-controlled current sources (VCCSs). Hence an equivalent-circuit model, shown in Fig. 2.14, can be constructed. The values of gm, Rmb. and gq can be found from Eq. (2.14): = 2k obs — Vo — ¥V26, + Bo + YV26)U + dvds) = 27k + AWB), (2.18) dip Bmp pe) = —Kuks — Vio — ¥W2bp + Ve + V2) x (L + Av) = (2.19) °s V2b, + vfs = 8m/2 © V2b, + Be” on wot (2) = ks — Vio — YV2b, + Be + YV20,)°A (2.20) Oups; = a 9, T+ pas? Hence, to a good approximation, gq and g,,» are proportional to ‘Vip, while gy is proportional to i}. The other important components of the complete small-signal model of the MOS- FET are the capacitors representing the incremental variations of stored charges with changing electrode voltages. These play an important role in the high-frequency operation of the device. The intrinsic components of the terminal capacitances of the MOSFET devices (associated with reverse-biased pn junctions and with channel and depletion regions) are strongly dependent on the region of operation, while the extrinsic components (due to layout parasitics, overlapping regions, etc.) are rela- tively constant. Assuming again that the transistor operates in the saturation region, it can be assumed that the channel begins at the source and extends over two-34 = MOS DEVICES AS CIRCUIT ELEMENTS thirds of the distance to the drain. In this region of operation. the most important capacitances are the following: Cys: Gate-to-Drain Capacitance. This is due to the overlap of the gate and the drain diffusion. It is a thin-oxide capacitance. and hence to a good approxi- mation can be regarded as being voltage independent. 2. Cys: Gate-to-Source Capacitance. This capacitance has two components: Cgsov. the gate-to-source thin-oxide overlap capacitance, and Cy,., the gate-to- channel capacitance. The latter (in the saturation region) is around 3C,., where C,. is the total thin-oxide capacitance between the gate and the surface of the substrate. In the triode region, C;, = Cox. Ces is nearly voltage independent in the saturation region. 3. Cyp: Source-to-Substrate Capacitance. This capacitance also has two compo- ents: Cyn, the pn junction capacitance between the source diffusion and the substrate, and C,,, which can be estimated as two-thirds of the capacitance of the depletion region under the channel. The overall capacitance Cy, has a voltage dependence which is similar to that of an abrupt pn junction. 4. Cy: Drain-to-Substrate Capacitance. This is a pn junction capacitance and is thus voltage dependent. 5. Cy»: Gate-to-Substrate Capacitance. This capacitance is usually small in the saturation region; its value is around 0.1C,,- Figure 2.15 illustrates the physical structure of an NMOS transistor and the locations of the capacitances in the cutoff (Fig. 2.15a). saturation (Fig. 2.155). and nonsatura- tion or triode (Fig, 2.15c) regions. Table 2.3 lists the terminal capacitors of the NMOS device and their estimated values in the three regions of operatian The notations used are those shown in Fig. 2.15u to c. Figure 2.16 depicts the complete high frequency (ac) small-signal mode! of the MOSFET. In analyzing the small- signal behavior of MOSFETs. the model of Fig. 2.14 can be used if only low- frequency signals are present: if the capacitive currents are also of interest. the circuit of Fig. 2.16 must be applied From the models of Figs. > 14 and 2.16 and accompanying discussions, a number of general statements can be made about the desirable construction of a MOSFET: 1, For high ac gain. g,, should be large. This will be the case, by Eq. (2.18). if £ 2B (WrCoxWV/2L 1s large. Thus the oxide should be thin to maximize C,, (which is the oxide capacitance per unit area); also, W/L should be as large as possible. These measures, however, tend to increase the size and thus the cost of the integrated circuit. Also, by Eq. (2.18), the quiescent (bias) current i, should be as large as the allowable de power dissipation permits. 2. As the negative sign in Eq. (2.19) indicates, the body effect reduces the gain. To minimize g,., by Eqs. (2.19) and (2.13), we need large Cyx. small Nimp (ie.. lightly doped substrate), and a large bias voltage v%g for the source.2.4. SMALL-SIGNAL OPERATION AND EQUIVALENT CIRCUIT OF MOSFET TRANSISTORS = 35, S t ception | EsL-2Lov region Cebpn p - substrate @ source side —,~ drain side t inversion layer —_p - substrate © Figure 2.15, Parasitic capacitances in MOSFET in the (a) cutoff region, (b) saturation region, and (c) triode region. (Of course, if usp is constant, no incremental body effect occurs and these requirements are irrelevant.) 3. Ideally, the MOSFET in saturation should behave as a pure current source. Hence, as Fig. 2.14 illustrates, g, should be small. By Eq. (2.20) this requires a small bias current i%, a large bias voltage «ps, and a small A. Since A is introduced by channel-length modulation, it can be reduced by increasing L and also [1, Sec. 8.4] by increasing Nimp. A summary of the formulas derived in this section is given in Table 2.4.“IZ — 1 SUP (Ty A" TMG Ay“ “O/TMt oar + PAMory + AM OW 0 (IE + “TOM. + TMH (@porn) paremesuony CAO TMS ayy +9 Ary + AO" (PAYOO TAR TM uorgex tonemreg wary aory “OK “OTM “TM wordar JJOI) wy "2 #9 ae “D uonesadg jo uolsay aouensede3, pMopEtedO Jo suoyBay UP) 224, 24) UN) LAASOW # JO saouNpedsy jeaULEL, “¢-7 ATAVL 362.4. SMALL-SIGNAL OPERATION AND EQUIVALENT CIRCUIT OF MOSFET TRANSISTORS 37. @ Figure 2.16. High-frequency equivalent circuit of a MOSFET. Next, we discuss briefly the linear model of a MOSFET that is biased in its nonsatu- rated (triode) region. Usually, such a device is used as a switch that is opened or closed (tumed on or off) by a large gate voltage or as a fairly linear large-valued variable resistor. Hence, here we derive its model only to analyze its behavior in such applications. We assume that ves is constant and that 2m» < ga and hence negligible. Under these conditions it can be seen from Eq, (2.7) that when the device conducts drain current, it behaves like a resistor connected between the drain and source terminals. The equivalent small-signal drain-to-source resistance for the case of ups near zero is given by 1 1 ra 94, ~ Walls = Veo) (2.21) and is thus controlled by the gate voltage overdrive v%s — Viv. In high-frequency application, the device capacitances must also be included in the model. A simple equivalent circuit is shown in Fig. 2.17. Since now a continuous channel extends from the source to the drain, the gate-to-channel capacitance Ci, is connected to both the drain and the source. An accurate high-frequency representa- tion of the channel should include a distributed resistive line extending from the source to the drain and capacitively coupled to both the gate and the substrate. However, as a first approximation, C4, can be treated as a lumped capacitance partitioned equally between C,, and C,¢, as indicated in the last row of Table 2.3. Finally, if the device is cut off, no channel exists and the model contains only Cyd Db Cap 6 tds B Ci a (Csb Figure 2.17. High-frequency model of a MOSFET in its s triode region.“Se[musoy [fe UI pouinsse st | > FAY “OTT “Biy eag,, “gery — 1A “eure - 1h “ouig + A “oye + IN (1?9)""2 aoueyoedes oD . OD Wi Wi ‘yinq-01-(ureup Jo) eamog depzoao P*D, dejsano 8 coumpoedes uresp-o1-21e5) “OME “TMS *%y sooysedva s0sn0s-0- 910) SON = 1 SHY +1 S00 = ny ea oR ae :goueionpuoo urea — “eA, a 4 a0 = ng BABA wg AA ne 5 mg tuk wk Ne rsouepnpuossuen 1995}2-Apog, song = = = 44 — 5) 2 1 = (4 — 8p) 7 ne Sue eA = 9) ao Taroe|\ > U8 — Goo aig © :eoueronpuoosues SOWd SOWN RULE, MONEINES UI SIAASOW JO SiaysmEseY [eusis-[ewS “PZ TTAVL2.5. WEAK INVERSION 39 Cad p Caw Cap a B Soe Cob Figure 2.18. High-frequency model of a MOSFET in its s cutoff region. the capacitances, with the values listed in the first row of Table 2.3. A simplified model of a MOSFET jin the cutoff region is shown in Fig. 2.18, where the drain—sourve resistance is infinity and C,, and Cy, capacitors are due w gate overlap and fringing capacitances. The gate-to-substrate capacitance C,a in the cutoff region is, however, highly nonlinear, and for the gate-to-source voltage around zero its value is approximately equal to WL'C,,, where L’ = L — 2, and Loy is the length of the overlap between the gate and the source-drain diffusion regions. 2.5. WEAK INVERSION ‘The triode and saturation regions of operation discussed earlier in this chapter assume that the device is operated in strong inversion and Ves — Vz = 100 mV (for an NMOS wansistor). If Ves — Vr < 100 mV, the device is in the weak inversion region (also called the subthreshold region) and operation of the n-channel MOS transistor with the source connected to substrate is more accurately described by the following exponential relationship between the gate-to-source control voltage and drain current: Ip= © igetteet, (2.22) where 1 nk: . — (gV/nkT + I) Ion = wobor mg ("q) orem 2.23) and the parameters m and n are defined in terms of the various capacitances in the device [3]. Equation (2.22) assumes that the device is operated with Vps > kT/q. The MOS transistors operating in the weak inversion region, similar to bipolar devices, have an exponential relationship. However, since Ino is very small (on the order of 10 to 20 nA), the available current to charge and discharge capacitances is also small, resulting in poor frequency performance. In practice, MOS transistors are operated in weak inversion only in low-frequency applications when low power consumption is desired.40 MOS DEVICES AS CIRCUIT ELEMENTS 2.6. IMPACT IONIZATION [4] One of the severe problems in submicron MOS technologies operating at supply voltages around 5 V is impact ionization. Figure 2.19 illustrates an n-channel MOS device cross section showing the impact ionization current flow and the J-V charac- teristic as a result of impact ionization. As depicted in the figure. when the drain- to-source voltage is increased, the strength of the electric field at the drain end of the channel eventually becomes high enough to induce significant impact ionization current which originates from the drain depletion region and flows into the substrate. Once this happens the current that flows into the drain terminal has two components. One component is the MOS transistor channel current that flows from the drain to the source, and the other is the impact ionization current that flows from the drain to the substrate. The impact ionization current is not a function of the wansistor channel length, and the magnitude of the current is not reduced dramatically simply by making the length longer. The current is largely determined by the peak electric field, which in tum is a function of the gate oxide thickness, drain junction depth, doping concentration in the substrate, the voltage between the drain terminal and the drain end of the channel region, and the gate-to-drain voltage. In technologies with feature sizes in the range of 2 jum, for an n-channel MOS device. the impact ionization current equals 1% of the drain current when the voltage between the drain and the drain end of the channel is in the range 4 to 9 V, and the device is biased los wo Figure 2.19, (a) An n-channel MOS device cross section showing umpax wmuzaon >rrent flow; (b) -V characteristic observed as a result of impact ionizazoe,2.7. NOISEINMOSFETS 41 in the saturation region. In p-channel MOS devices the effect occurs at substantially higher field strengths. ‘The impact ionization has several potentially damaging side effects. One serious negative consequence shown in Fig. 2.19b is degradation of the transistor output impedance, which results in reduced gain in amplifier stages that use transistors as active loads. One way w deul with this problem is dough circuit wechniques, where a shielding n-channel device is placed in series with the tansistor, preventing it from having a Vs greater than half the supply voltage [4]. The second damaging effect is the possibility of triggering latchup duc to the ohmic drop induced by the ionization current that flows into the substrate. Latchup is a phenomenon caused by the parasitic lateral pnp and npn bipolar transistors created on the chip. The collectors of each transistor feed the other’s base, and this creates an unstable device similar to a pnpn thyristor [5]. This causes a sustained de current that may cause the chip to stop functioning and may even destroy it. Latchup may be prevented by proper substrate strapping and using guard rings to surround some critical transistors on the chip. Another strategy is to reduce the substrate resistance. In this method the p- and n-channel transistors are formed in a lightly doped epitaxial layer that is grown on a low-resistivity substrate. Finally, the third serious side effect of impact ionization is the threshold shift of the MOS device due to the continuous operation in the impact ionization mode. This phenomenon is due to the high electric field which creates high energy carries that can be trapped in the gate oxide, resulting in long-term threshold shift. Several process modifications have been proposed that are effective at raising the voltage at which impact ionization becomes a problem. One technique is to lower the impurity gradient in the drain junction using lightly doped drain (LDD) structures. 2.7. NOISE IN MOSFETS There are three distinct sources of noise in solid-state devices: shot noise, thermal noise, and flicker noise. Shot Noise Since electric currents are carried by randomly propagating individual charge carriers (electrons or holes), superimposed on the nominal (average) current J, there is always a random variation i,s. This is due to fluctuation in the number of carriers crossing a given surface in the conductor in any time interval. It can be shown that the mean square of i,s is given by iE, = ql Af, (2.24) where q = 1.6 X 107! C is the magnitude of the electron charge and Af is the bandwidth. This formula only holds, Lowever, if the density of the charge cantiers is so low and the external electric field is so high that the interaction between the42 MOS DEVICES AS CIRCUIT ELEMENTS DI tar oe (b) fe) Figure 2.20. Thermal noise in a resistor: (a) noisy resistor; (b) and (c) equivalent circuits. camers 1s negligible. Otherwise, the randomness of their density and velocity is reduced due to the correlation introduced by the repulsion of their charges. The noise current is then much smaller than predicted by Eq. (2.24). In a conducting MOSFET channel, the charge density is usually high and the electric field is low. Therefore, Eq. (2.24) does not hold. The noise current due to random carrier motions is hence better described as thermal noise, which is discussed next. Thermal Noise In a real resistor R, the electrons are in random thermal motion. As a result, a fluctuating voltage v,r appears across the resistor even in the absence of a current from an external circuit (Fig. 2.20a). Thus the Thévenin model of the real (noisy) resistor is that shown in Fig. 2.20b. Clearly. the higher the absolute temperature T of the resistor, the larger v7 will be. In fact, it can be shown that the mean square of ur is given by ar = AKTR Af. (2.25) Here k is the ubiquitous Boltzmann’s constant, and Af is the bandwidth in which the noise is measured. in hertz. (The value of 4k7 at room temperature is about 1.66 x 107 V Cy If Eq. (2.25) was true for any bandwidth, the energy of the noise would be infinite. In fact, however, for very high frequencies (~10'? Hz) other physical phenomena enter, which cause ver to decrease with increasing frequency so that the overall noise energy is finite. The average value (dc component) of the thermal noise is zero. Since its spectral density v2p/Af is independent of frequency (at least for lower frequencies), it is a white noise. Clearly, Fig. 2.20b may be redrawn in the form of a Norton equivalent that is as a (noiseless) resistor R in parallel with a noise current source i,r (Fig. 2.20c). The value of the latter is given by By = 4kTG Af, (2.26) where G = UR.2.7. NOISE INMOSFETS 43 noiseless transistor (a) wo Figure 2.21. Equivalent models of the thermal noise in a MOSFET. Since the channel of a MOSFET in conduction contains free carriers, itis subject to thermal noise. Therefore, Fas. (2.25) and (2.26) will hold, with R given by the incremental channel resistance. The noise can then be modeled by a current source, as shown in Fig. 2.21a. If the device is in saturation, its channel tapers off (Fig. 2.8) and the approximation R ~ 3/2g,, can be used in Eq. (2.26). In most circuits it is convenient to model the effect of i,r caused by a voltage source connected to the gate of an (otherwise noiseless) MOSFET (Fig. 2.21). This “gate-referred”” noise voltage source is then given by (2.27) Both i,7 and v,r depend thus on the dimensions, bias conditions, and temperature of the device. As an example of their orders of magnitude, fora transistor with W = 200 pm, L = 10 wm, and Cop = 4.34 X 1078 F/em? (corresponding to an oxide thickness of 800 A) which is operated in saturation at a drain current i, ee 200 pA, the gate-referred noise voltage at room temperature is about 9 nV/\/H: If the device is switched off, R becomes very high, and the equivalent noise circuit will be a current source with a value given by Eq, (2.26). Clearly, 27 is very small; hence for usual (low or moderate) external impedance levels, the MOSFET can be regarded as a noiseless open circuit if it is turned off.44 — MOS DEVICES AS CIRCUIT ELEMENTS Flicker (1/f) Noise In an MOS wansistor, extra electron energy states exist at the boundary between the Si and SiO,. These can trap and release electrons from the channel, and hence introduce noise [6.7]. Since the process is relatively slow, most of the noise energy will be at low frequencies. As before. a possible model of this noise phenomenon is a current source in parallel with the channel resistance. The de value of noise current is again zero. [ts mean-square value increases with temperature and the density of the surface states: it decreases with the gate area W X L and the gate oxide capacitance per unit area C,.. For devices fabricated with a “‘clean”” process, the gate-referred noise voltage is nearly independent of the bias conditions and is given by the approximating formula K_ sf ty = a = GWE (2.28) Here K depends on the temperature and the fabrication process; a typical value [8, p. 31} is 3 x 10°74 V° - F. For the transistor described in the preceding example, the formula gives a noise voltage of 83 nV/\/Hz at f = 1 KHz. As before, the equivalent channel current noise is related to vr by the formula iy = gritty. The noise process described is usually called flicker noise or (in reference to the 1/f factor in v3,and i3,) Lf noise. As the example given illustrates, at low frequencies (say. below | kHz) it is usually the dominant noise mechanism in a MOSFET. In conclusion, the channel noise in a MOSFET can be modeled by an equivalent noise current generator, as in Fig. 2.214. In the small-signal model this generator will be in parallel with the current sources gnUes and gmotas (Fig. 2.16). Its value can be chosen as the root-mean-square (RMS) noise current, which from Eqs. (2.26)-(2.28) is Kaz = AKTG + WH) Af. Note that the mean squares of the noise currents are added, since the different noise mechanisms are statistically independent. Alternatively, the noise can be represented by its gate-referred voltage source (Fig. 2.216), in series with the gate terminal. The value of the source is i,,/g,,, with i, given by Eq. (2.29). (2.29) 2.8. CMOS PROCESS The CMOS process provides the most flexibility to the circuit designer, due to the availability of complementary MOS devices on the same chip. The original motivation for developing the CMOS technology was the need for low-power and high-speed logic gates for digital circuits. The required isolation between the two different device types is accomplished by the use of ‘‘wells,”” that is, large, low-doping-level deep diffusions, which serve as the substrates for one of the twa device types. Asan example, Fig. 2.22 shows part of an n-well CMOS chip, where high-resistivity p-type substrate is used for the n-channel devices, and diffused n wells for the p-channel devices.2.8. CMOS PROCESS 45 deposited oxide metal Pp \ fold * " well field implant polysilicon 2} polysilicon 4 > si Figure 2.22, Device structure fabricated in a high-performance n-well CMOS process. As will be shown in later chapters, a CMOS circuit can be operated with a single power supply, and it can be used to realize high-speed, high-gain, low-power analog amplifier stages. An additional advantage is that for the devices in the well (in Fig. 2.22, the PMOS transistor), the source can be connected to the well, thereby eliminat- ing the body effect, and if the device is used in an amplifier, increasing the gain of the circuit. This, however, results in a large stray capacitance between the source and the substrate, due to the large size of the well-to-body interface. Another important advantage of the CMOS process is the availability of transmission gates madc of a parallel connection of complementary transistors that can be used as switches. When such transmission gates are used, the signal is no longer limited to a level, which is a threshold voltage below that of the high clock signal, as is the case when single- channel switches are used. In addition, in CMOS chips a bipolar transistor can be fashioned from a source diffusion, the well, and the substrate. This can be used in an emitter-follower buffer stage (described later), in a bandgap voltage reference circuit, and so on. In addition to transistors, analog MOS circuits usually require on-chip capacitors, and sometimes also on-chip resistors. In a silicon-gate ‘‘double-poly”’ process, a second layer of low-resistivity polysilicon is available for usc as an interconnect or for the formation of a floating gate for memory applications. These two layers of polysilicon can also be used as the top and bottom electrodes of a monolithic capaci- tor. Figure 2.22 shows the construction of a capacitor with two polysilicon electrodes. Resistors can be created on an MOS chip using a diffused or implanted layer on the surface of the substrate. Since the sheet resistance of these resistive layers is relatively low (typically 25 to 70 for a square layer), the size of the resistors obtainable on a reasonably small area is limited to about 100 k®. The higher resistiv- ity well diffusion is also available as a resistor. This resistor, however, has much higher voltage and temperature coefficients compared to diffused or implanted ones. PROBLEMS 2.1. A pn junction diode is connected to an external voltage vin the forward direction (Fig. 2.3), Reversing the polarity of the voltage reduces the current by a factor46 Figure 2.23. Circuit for Problem 2.8. 2.2. 2.3. 24. 2.8. 2.6. 2.7. 2.8. 2.9. MOS DEVICES AS CIRCUIT ELEMENTS Yoo wo 1 10°. Assume that the diode satisfies Eq. (2.1) and is at room temperature. What is v? For a pn junction (Fig. 2.3), Ns = Np = 10'° ions/cm, | = 5V,A = 0.34 mm?, and the measured value of C is 27 pF. How much is x4, the width of the depletion layer? How much is 6,? Using the definition R = 1 /(ip/8Vps), calculate the channel resistance of an NMOS transistor from (a) Eq. (2.6), (b) Eq. (2.7), and (©) Eq. (2.9). For an NMOS wansistor, p,, = 10° cm?/V-s, the thickness of the gate oxide is 10° A(1A = 107% cm), W = 25 jum, and L = 5 ym. The threshold voltage is 4 V. Calculate ip for us = vp = 0 V and ug = 6 V, and (a) up = 0.1 V, (b) vp = 2 V, and (c) wp = 4V. Repeat the calculations of Problem 2.4 if uv; = 0, vs = —3 V, and $, = 03 V. What conclusions can you draw from your results regarding the body effect? For an NMOS transistor,” = 2 wA/V2, W = 30 um, L = 10 wm, bp = 03 V, y = 15 V'?, and X = 0.03 V~!. Find the incremental conductances Sm» Gus and By for usg = OV, vs = 5 V, and 7% = 10 WA. Repeat your calculations for vga = 2 V! ‘An NMOS switch transistor has a gate-to-source voltage ucs > Vr. Its drain is open-circuited. How much is vps? Why? In the circuit of Fig. 2.23, the switch 5 is opened at 1 = 0. (a) Is the transistor operating in its linear or saturation region? (b) Neglecting body effect and channel-length modulation, find u(t) by solving the appropriate differential equation for the circuit. In the circuit of Fig. 2.24 a noise voltage v, is generated due to thermal and ka. wv Figure 2.24, Circuit for Problem 2.9.2.8. CMOSPROCESS 47 @i ®@i @i ’ eg ® ®@ + + : Figure 2.25, Circuit for Problem 2.10. shot-noise effects. For what value of R will the two noise voltages v,r and v,s be equal? 2.10. Calculate the incremental impedance Ou/di seen at node A of the circuits shown in Fig. 2.25. 2.11. Show that the transconductance g,, in the saturation region is equal to the drain conductance in the triode region for a given device and a fixed Ve REFERENCES 1, R. S."Muller and T. I. Kamins, Device Electronics for Integrated Circuits, Wiley, New York, 1977. 2. A.S. Grove, Physics and Technology of Semiconductor Devices, Wiley, New York, 1967. 3. Y.P. Tsividis and R. W. Ulmer, A CMOS voltage reference, IEEE J. Solid-State Circuits, SC-13(6), 774-778 (1978). 4. C. A. Laber, C. F. Rahim, 8. F. Dryer, G. T. Uehara, P. T. Kwoh, and P. R. Gray, /EEE J. Solid-State Circuits, $C-22(2), 181-189 (1987). 5. S. M. Sze (Ed.), VESI Technology, McGraw Hill, New York, 1983. 6. M. B. Das and J, M. Moore, IEEE Trans. Electron, Devices, ED-21(2), 247-257 (1974). 7. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Wiley, New York, 197. 8. PR, Gray and D. A. Hodges, and R. W. Brodersen (Eds.), Analog MOS Integrated Circuits, IEEE Press, New York, 1980.CHAPTER 3 BASIC ANALOG CMOS SUBCIRCUITS In this chapter some of the basic subcircuits commonly utilized in analog MOS integrated circuits are examined. These blocks include a variety of bias circuits, current mirrors, single-stage amplifiers. source followers, and differential stages. ‘These subcircuits are typically combined to synthesize a more complex circuit func- tion. The operational amplifier and comparator, covered in later chapters, are exam- ples of how simple subcircuits are combined to form more complex functions. ‘The first part of this chapter covers the subject of the bias circuits in CMOS technology and the current mirrors. Next, the CMOS gain stage is introduced, with particular emphasis on the use of active devices as active loads. The current mirror subcircuit covered as a biasing clement is utilized as a dynamic load to obtain very high voltage gains from a single-stage amplifier. The differential amplifier, which represents a broad class of circuits, is discussed next. The differential amplifier is ‘one of the most widely used gain stages, whose basic function is to amplify the difference between two input signals. Finally, the last part of the chapter deals with the small-signal analysis and frequency response of CMOS amplifier stages. A good understanding of the topics presented in this chapter is essential for the analog CMOS designer, as most designs start at the subcircuit level and progress upward to realize a more complex function. 3.1. BIAS CIRCUITS IN MOS TECHNOLOGY Op-amp and amplifier stages, described in detail later, need various dc bias voltages and currents for their operation. An ideal voltage or current bias is independent of, the de power supply voltages (Vpp > 0 and Vsg = 0) and of temperature. To obtain the dc bias voltages Voi, Vers «... Von Where Vss < Voy < Vo2 <-> 483.1. BIAS CIRCUITS INMOS TECHNOLOGY = 49. drain 'b Figure 3.1. (a) Diode-connected NMOS transistor; (b) current-voltage characteristic of diode-connected transistor. Vin < Vow, voltage division can be used. Pure resistive dividers are seldom used in MOS technology because the resulting voltages cannot be used directly to establish bias currents in MOS transistors. Instead, combinations of MOSFETs and resistors are often used. A MOS transistor with its gate connected to the drain forms a two- terminal device, as shown in Fig. 3.1a. Its current-voltage characteristics are shown in Fig. 3.1b. Since Vps = Vos, the dynamic resistance rz, is characterized by B.D Therefore, a useful approximation valid for low frequencies, small signals, and negli- gible substrate effects is that the device behaves like a resistor of value I/g,,. Any number of n- and p-channel devices and resistors can be combined to form a voltage divider, as shown in Fig. 3.2, where both n- and p-channel transistors are used Figure 3.2, Voltage-divider-based bias circuit.5D BASIC ANALOG CuInS SUuRCIAC HTS, and Vss = 0 is chosen. Since Vas = Vos here for both devices, the condition for saturation, Vs > Vos — Vrs G2) is satisfied, Hence the common value of the drain currents is given approximately by | (Vor — Van” 1 mle Teas = x, w(t [ez — Voo) ~ VrnP 3) a = Here /eias is usually specified: then V1 and Vjo can be selected and Eq. (3.3) used to find the W/L ratios of the devices and the value R of the resistor. An undesirable feature of this configuration is that the bias voltages and current depend on the supply voltages Vin and Vcs. In fact, the bias current increases rapidly with increasing power supply voltage. Since such bias strings are used to provide bias for other devices in the circuit. the de power consumption of the overall circuit becomes heavily dependent on the supply’ voltages. ‘A CMOS circuit with (theoretically) perfect supply independence is shown in Fig. 3.3. If Q; and Q, are matched transistors so that (W/L); = (W/L).. they ideally carry equal currents. Choosing (W/L), = (W/L), will then result in Ves, = Vose, Figure 3.3. Vreferenced supply-independent CMOS bias source.3.1. BIAS CIRCUITS IN MOS TECHNOLOGY 51 and the voltage across the resistor, /iiasR, will be equal to Voso. This equilibrium condition leads to the equation 4 [Te Rls = Voso = \l epi + Vr- (3.4) Equation (3.4), which is independent of Von, can be solved to obtain Iyias. Note that in this analysis we neglected the effects of channel-length modulation (i.e., we as- sumed that Ip is independent of Vps). An alternative version of the bias circuit shown in Fig. 3.3 that uses the base-emit- ter voltage (Vpe) of a bipolar transistor as the reference voltage is shown in Fig. 3.4a. In a CMOS process, the substrate, well, and the source—drain junction inside the well can be used to form a vertical bipolar transistor. For example, Fig. 3.4b r-woil Prsubetrate: (b) Figure 3.4. (a) Vge-based supply-independent bias circuit; (b) vertical pnp bipolar transistor in an n-well CMOS process.52 BASIC ANALOG CMOS SUBCIRCUITS shows a vertical pnp device that is formed in an n-well process. The collector of this pnp device is the p~ substrate that is permanently connected to the most negative voltage on the chip. For the bipolar transistor, the collector current is given by I, = Le%ee\s, 3.5) where Vpe is the base-emitter voltage. Vr = &T/g, and J, is a constant current, which is proportional to the cross-sectional area of the emitter, which is used to describe the transfer characteristic of the transistor in the forward active region. In Fig, 3.4a, as in Fig. 3.3. if (W/L), = (WIL) and (W/L); = (W/L)s, equal currents are forced through the two branches of the bias circuit and the voltage drop across resistor R equals Ve. Thus the bias current is given by Tas = 36) Combining Eys. (3.5) and (3.6), we have Vrs Ioias Tics = ya. (3.7) This equation can be solved iteratively for Iyias Both supply-independent bias circuits have a second trivial steady -state condition, cutoff when /pias = 0. To prevent the bias circuit from settling to the wrong steady- state condition, a startup circuit is necessary in all practical applicanons. The circuit to the right of the dashed line in Fig. 3.5 functions as a startup circuit. If nas = 0, Qs is off and the voltage at node A is high, causing Qg to tun on and draw a current through Qs, forcing the circuit to move to its other equilibrium state. Once the circuit settles in the desired state, Qs tums on and node A goes low, turning off Qs. At this state the startup circuit is essentially out of the picture. Figure 3.5. Supply-independent bias circuit with startup.9.1, BIAS CIRCUITS INMOS TECHNOLOGY = 53 Another important performance aspect of the bias circuits is their temperature dependence. Unfortunately, supply-independent bias circuits are not necessarily tem- perature independent, because the base-emitter voltage (Vgr), and gate-to-source voltage (Vcs) are both temperature dependent. If the temperature coefficient Ter is defined as the relative change of the bias current per degree Celsius temperature variation, we have [1] — 1 Olbpias Ter = ar G.8) Using the definition above and Eq. (3.6), the relative temperature coefficient of the Vge-based bias generator can be calculated: Vee L _ Vag OR) 1 Ter ot) log 39 1 aR Ter = RF: (3.10) Since the temperature coefficient of the base-emitter junction voltage is negative (— 2 mV/°C) while resistors typically have a positive temperature coefficient, the two terms in Bq. (3.9) add, resulting in a net Te, that is quite high. The temperature behavior of the threshold-based bias gencrator of Fig. 3.3 is similar to the Vpz-based circuit. An alternative supply-independent bias generator is the A Vpg-based circuit shown in Fig. 3.6a, The operation of this circuit is based on the difference between the base-emitter voltages of two transistors operated at different current densitics. In Fig. 3.6a, as in Figs. 3.3 and 3.4, (W/L), = (W/L), and (W/L); = (WIL). Therefore, equal currents flow through the two branches of the circuit and Ves; = Ves. Also, the pnp transistor M,, has an emitter area that is m times the emitter area of, Mo. The voltage across the resistor R is AVpe = Varo — Veer. From Eq. (3.5), Trias = Le Vee s, Tring = mile Veer, .11) and hence AVee = Vee0 — Veer = Vrin(m). (3.12) AVog appears across R and produces a current of value = AYoe _ Vrinm Tis R R (3.13) Obviously, the resulting bias current is independent of the power supply Vpp. This circuit also has two operating states: one at the desired operating current given by Eq. (3.13) and the other at zero. To prevent the circuit from operating in the cutoff state, a startup circuit similar to the one shown in Fig. 3.5 is required.54 BASIC ANALOG CMOS SUBCIRCUITS Figure 3.6. (a) AVge-based supply independent bias generator; (b) high-performance AVae-based supply- independent bias generator. ‘The temperature coefficient of the bias current can be calculated from Eq. (3.13): = (Vekm _ Vrinm aR) 1 ter = (GH R 7 RE at) ia @.14) _ 1 av, _ 1 aR “vp ar Ra’ G.15) Ter3.2, MOS CURRENT MIRRORS AND CURRENT SOURCES 55, Since V;/8T and AR/QT are both positive, the two terms in the temperature coeffi- cients tend to cancel each other. Thus compared to Vge-or threshold-based bias circuits, the A Vpg-based bias circuit can produce a much smaller temperature coeffi- cient. ‘One drawback of the A Vpg-based bias generator is the strong dependence of Ibias ‘on the mismatches between Q, Q, and Q, Q, device pairs. The mismatch between Q;-Qz will result in different currents to flow in the two branches of the circuit. If 1 + € represents the ratio of the two currents, A Vge will become AVoe = Vr In (m(1 + €)], (3.16) which is equivalent to modifying m, the ratio of the emitter areas, by | + €. The mismatch between Q, and Q, and the current difference due to the mismatch of Qs and Q, will make the Ves values of Qy and Qs different. This is equivalent to a de offset voltage Vor = AVas. which modifies Eq. (3.13) to (3.17) Vr In [m(1_+ ©)] — AVas Jog = Assuming that m = 8, € = 0.01, and Vr = 26 mV at room temperature, A Vag = 26 X In[8(1 + 0.01)] = 54.3 mV results. For a AVcs = 5 mV offset voltage, from Eq. (3.17), Ibies Will change by 10%. To reduce this variation special care should be taken in the layout of Q:—Qs. For better geometrical matching, these devices should use a common-centroid layout strategy [2]. ‘The current-matching accuracy of the bias generator of Fig. 3.6a is further de- graded due to the mismatch between the drain-to-source voltages of Q;-Q, and Q1-Qz transistor pairs. The circuit can be made symmetrical, and the drain-to-source voltage drops equalized, by adding transistors Qs to Qg to the two branches of the circuit (Fig. 3.65). The improved configuration also uses the cascode current mirror principle, described in Section 3.2, wo improve the power supply i¢jection. On the other hand, the minimum power supply voltage is increased compared to the circuit of Fig. 3.6a, due to the extra voltage drops required by the two cascode devices. This becomes a major shortcoming in advanced submicron process technologies, ot in low-power/low-voltage applications where the power supply voltage is limited 103.3 V. 3.2. MOS CURRENT MIRRORS AND CURRENT SOURCES As will be seen in later sections, constant current sources and current mirrors are important components in MOS amplifiers. The MOS current sources are quite similar to the bipolar sources [1,3], where the current mirrors work on the principle that identical devices with equal gate-to-source and drain-to-source voltages carry equal