APPENDIX A

SAMPLE VERILOG TEMPLATES

A.l NUMBERS AND OPERATORS

A.l.l Sized and unsized numbers

number stored value comment

5'bllOlO 11010
5'blI-010 11010 - ignored
5'032 11010
5 'hla 11010
5'd26 11010
5'bO 00000 0 extended
5'bl 00001 0 extended
5'bz ZZZZZ z extended
5'bx XXXXX x extended
5'bxOl xxx0l x extended
-5 ' b0000 1 I1111 2's complement of 00001
' b11010 00000000000000000000OOOOOOOllOlO extended to 32 bits
' hee 00000000000000000000OOOOl1101110 extended to 32 bits
1 00000000000000000000000000000001 extended to 32 bits
-1 11111111111111111111111111111111 extended to 32 bits

FPGA Proto@ping by Verilog Examples. By Pong P. Chu

Copyright @ 2008 John Wiley & Sons, Inc.
A.1.2 Operators

n p e of Operator Description Number

operation symbol of operands
Arithmetic + addition 2
- subtraction 2
* multiplication 2
/ division 2
% modulus 2
+* exponentiation 2
Shift >> logical right shift 2
<< logical left shift 2
>>> arithmetic right shift 2
<<< logical left shift 2
Relational > greater than 2
< less than 2
>= greater than or equal to 2
<= less than or equal to 2
Equality -- equality
!= inequality
--- case equality
I == case inequality
Bitwise - bitwise negation 1
& bitwise and 2
I bitwise or 2
. bitwise xor 2
Reduction & reduction and 1
I reduction or 1
. reduction xor 1
Logical ! logical negation 1
&& logical and 2
II logical or 2
Concatenation { } concatenation any
{ { ) ) replication any
Conditional ? : conditional 3
A.2 GENERAL VERILOG CONSTRUCTS

A.2.1 Overall code structure

Listing A . l Overall code structure

module bin-counter
// o p t i o n a l parameter d e c l a r a t i o n
# ( p a r a m e t e r N=8) // d e f a u l t 8
// p o r t d e c l a r a t i o n
5 (
i n p u t w i r e clk, r e s e t , // c l o c k & r e s e t
i n p u t w i r e syn-clr, l o a d , en, // i n p u t c o n t r o l
i n p u t w i r e [N-1:Ol d, // i n p u t d a t a
o u t p u t w i r e max-tick, // o u t p u t s t a t u s
10 o u t p u t w i r e [N-1:Ol q // o u t p u t d a t a
);

// c o n s t a n t d e c l a r a t i o n
l o c a l p a r a m MAX = 2**N - 1;
I? // s i g n a l d e c l a r a t i o n
r e g IN-1:01 r-reg, r - n e x t ;

// body
.............................................
20 // component instantiation
.............................................
/ / no i n s t a n t i a t i o n i n t h i s code

zr / / memory e l e m e n t s

// r e g i s t e r
a l w a y s Q ( p o s e d g e clk, p o s e d g e reset)
i f (reset)
1u r-reg <= 0 ;
else
r-reg <= r-next;

35 // c o m b i n a t i o n a l circuits

// n e x t - . s t a t e logic
always Q*
i f (syn-clr)
r-next = 0 ;
e l s e i f (load)
r-next = d ;
e l s e i f (en)
r-next = r-reg + 1 ;
45 else
r-next = r - r e g ;
// o u t p u t l o g i c
 a s s i g n q = r-reg;
a s s i g n max-tick = (r-reg==2**N-1) ? l J b l : l J b O ;
50

endmodule

A.2.2 Component instantiation

Listing A.2 Component instantiation template

module counter-inst
(
i n p u t w i r e clk , reset,
i n p u t w i r e syn-clrl6, loadl6, en16,
5 i n p u t w i r e [15:01 d ,
o u t p u t w i r e max-tick8, max-tickl6,
o u t p u t w i r e [15:01 q
1;

lo //body
// i n s t a n t i a t i o n o f 1 6 - b i t c o u n t e r , a l l p o r t s u s e d
bin-counter #(.N(16)) counter-16-unit
( . clk(c1k) , .reset (reset),
. syn-clr (syn_clrl6), . load(loadl6), . en(enl61,
IS .d(d), .max-tick(max_tickl6), . q ( q ) ) ;
// i n s t a n t i a t i o n of f r e e - r u n n i n g 8 - b i t c o u n t e r
// with only the max-tick s i g n a l
bin-counter counter-8-unit
(.clk(clk), .reset(reset),
20 . syn-clr (1 'bO), . load(lJbO), . en(lJbl) ,
.d(8'h00), .max-tick(max_tick8), . q O ) ;

endmodule

A.3 ROUTING WITH CONDITIONAL OPERATOR AND IF AND CASE

STATEMENTS

A.3.1 Conditional operator and if statement

Listing A.3 Priority encoder using conditional operator and if statement

(
i n p u t w i r e [ 4 : 11 r ,
o u t p u t w i r e [2:0] yl,
o u t p u t r e g [2:0] y2
s 1;

// C o n d i t i o n a l o p e r a t o r
a s s i g n yl = (r [41) ? 3lb100 : // can a l s o use ( r [ 4 ] = = l ' b l )
(r[31) ? 3'b011 :
(r [ 2 ] ) ? 3'bOlO :
 // I f s t a t e m e n t
15 // - each branch can c o n t a i n m u l t i p l e s t a t e m e n t s
// with begin . . . end d e l i m i t e r s
a l w a y s Q*
i f (rC41)
y 2 = 3'blOO;
20 e l s e i f (r [31)
y 2 = 3'b011;
e l s e i f (r C21)
y 2 = 3'bOlO;
e l s e i f (r [I])
zj y 2 = 3'bOOl;
else
y 2 = 3'bOOO;

endmodule

A.3.2 Case statement

Listing A.4 Priority encoder using case statement

module prio-encoder-case
(
i n p u t w i r e [4:11 r ,
o u t p u t r e g [2:01 y 1 , y 2
5 1;

// case s t a t e m e n t
// - each branch can c o n t a i n m u l t i p l e statements
// with begin . . . end d e l i m i t e r s
10 a l w a y s Q*
c a s e (r)
4'b1000, 4'b1001, 4'b1010, 4'b1011,
4'b1100, 4'b1101, 4'b1110, 4'bllll:
yl = 3'blOO;
4'b0100, 4'b0101, 4'b0110, 4'b0111:
yl = 3'b011;
4'b0010, 4'bOOll:
yl = 3'bOlO;
4'b0001:
20 yl = 3'bOOl;
4'boo00 : / / d e f a u l t c a n a l s o be u s e d
yl = 3'bOOO;
endcase

2% // c a s e z s t a t e m e n t
always Q*
c a s e z (r)
4'bl???: y 2 = 3'blOO; // u s e ? f o r don ' t - c a r e
 4'b01??: y2 = 3'bOll;
30 4'b001?: y2 = 3'bOlO;
4'bOOOl: y2 = 3'bOOl;
4'bOOOO: y2 = 3'bOOO; // default can a l s o be used
endcase

35 endmodule

A.4 COMBINATIONAL CIRCUIT USING AN ALWAYS BLOCK

A.4.1 Always block without default output assignment

Listing A.5 Always block template (without default output assignment)

module compare-no-def ult
(
input wire a, b ,
o u t p u t r e g g t , eq
5 1;

/ / - u s e @* t o i n c l u d e a l l i n p u t s i n sensitivity list
/ / - e l s e b r a n c h c a n n o t be o m i t t e d
// - a l l o u t p u t s must be a s s i g n e d i n
a l l branches
10 always O*
i f ( a > b)
begin
gt = l'bl;
eq = l J b O ;
end
e l s e i f (a == b)
begin
gt = l J b O ;
eq = l'bl;
end
else // e l s e branch cannot be o m i t t e d
begin
gt = l J b O ;
eq = l J b O ;
25 end

endmodule

A.4.2 Always block with default output assignment

Listing A.6 Always block template (with default output assignment)

module c o m p a r e - w i t h - d e f a u l t
(
input wire a , b ,
o u t p u t r e g g t , eq
 MEMORY COMPONENTS 473

// - u s e @* t o i n c l u d e a l l i n p u t s i n s e n s i t i v i t y list
// - a s s i g n each o u t p u t with a d e f a u l t value
always Q*
lo begin
gt = l'bO; // d e f a u l t value f o r g t
e q = I'bO; / / d e f a u l t v a l u e f o r eq
i f ( a > b)
gt = l'bl;
e l s e i f (a == b)
eq = l'bl;
end

endmodule

A.5 MEMORY COMPONENTS

A.5.1 Register template

Listing A.7 Register template

module r e g - t e m p l a t e
(
input wire c l k , reset,
input wire en,
5 input wire [ 7 : 01 ql-next , q2-next , q 3 _ n e x t ,
output reg [7:01 q l - r e g , q 2 - r e g , q 3 - r e g
1;

10 // register without reset

.............................................

// use nonblock a s s i g n m e n t ( <= )

always Q(posedge c l k )
q l - r e g <= q l - n e x t ;
I i
.............................................
// register w i t h asynchronozrs reset

/ / u s e n o n b l o c k a s s i g n m e n t ( <= )
I always Q ( p o s e d g e c l k , posedge reset)
i f (reset)
q 2 - r e g <= 8'bO;
else
q 2 - r e g <= q 2 - n e x t ;
3
.............................................
// register w i t h e n a b l e and a s y n c h r o n o u s reset
.............................................
// use nonblock assignment ( <= )
474 SAMPLE VERILOG TEMPLATES

3 always @ ( p o s e d g e c l k , posedge r e s e t )
if (reset)
q 3 - r e g <= 8 ' b O ;
else i f (en)
q 3 - r e g <= q 3 - n e x t ;
35

endmodule

A.5.2 Register file

Listing A.8 Register file

module r e g - f i l e
#(
parameter B = 8, / / number of b i t s
W = 2 / / number of a d d r e s s bits
5 1
(
input wire c l k ,
input wire wr-en,
i n p u t w i r e [W-1:OI w - a d d r , r-addr,
i n p u t w i r e [B-1:Ol w - d a t a ,
o u t p u t w i r e [B-1:Ol r - d a t a
);

// s i g n a l d e c l a r a t i o n
15 r e g [B-1:Ol a r r a y - r e g [2**W-1:Ol ;

/ / body
// w r i t e
operation
always @ ( p o s e d g e c l k )
20 i f (wr-en)
a r r a y - r e g [w-addr] <= w - d a t a ;
// read o p e r a t i o n
assign r-data = array-reg [r-addrl ;

A.6 REGULAR SEQUENTIAL CIRCUITS

Listing A.9 Sequential circuit template

I I

// Universal counter function table

,,

// s y n - c l r load en q* operation
5 //
// I - - 0 synchronous c l e a r
// 0 1 - d parallel load
// 0 0 I q+l c o u n t up
 REGULAR SEQUENTIAL CIRCUITS 475

// 0 0 0 9 pause

module b i n - c o u n t e r
# ( p a r a m e t e r N=8) // default 8
(
input wire c l k , r e s e t , // c l o c k & r e s e t
IS input wire syn-clr, l o a d , e n , // i n p u t c o n t r o l
i n p u t w i r e [N-1:01 d , // i n p u t d a t a
output wire max-tick, // o u t p u t s t a t u s
o u t p u t w i r e [N-1:OI q // o u t p u t d a t a
1;
20

// c o n s t a n t d e c l a r a t i o n
l o c a l p a r a m MAX = 2**N - 1 ;
// s i g n a l d e c l a r a t i o n
r e g [N-1:Ol r - r e g , r - n e x t ;

// register
.............................................
30 // r e g i s t e r
always O(posedge c l k , posedge r e s e t )
if ( r e s e t )
r - r e g <= 0 ;
else
3s r - r e g <= r - n e x t ;
.............................................
// n e x t - s t a t e logic
.............................................
a l w a y s Q*
40 if (syn-clr)
r-next = 0;
else if (load)
r-next = d ;
else if (en)
r-next = r-reg + 1;
else
r-next = r-reg;
.............................................
// output logic
.............................................
assign q = r-reg;
a s s i g n max-tick = (r-reg==2**N-1) ? l'bl : 17bO;

endmodule
 (a) State diagram (b) A S M chart

Figure A.l State diagram and ASM chart of an FSM template.

A.7 FSM

Listing A.10 FSM template

/ / c o d e f o r [ h e FSM i n F i g u r e A . 1
module f sm-eg-2-seg
(
input wire clk, reset,
input wire a, b,
o u t p u t r e g y o , yl
);

// symbolic s t a t e d e c l a r a t i o n
10 l o c a l p a r a m [1:0] SO = 2 I b 0 0 ,
sl = 2'b01,
s2 = 2'biO;
// s i g n a l d e c l a r a t i o n
r e g [I: 01 s t a t e - r e g , s t a t e - n e x t ;
 FSM 477

// s t a t e
register
always Q ( p o s e d g e clk, posedge r e s e t )
if (reset)
state-reg <= s o ;
else
state-reg <= s t a t e - n e x t ;

// n e x t - s t a t e l o g i c and o u t p u t logic
always Q*
zs begin
state-next = state-reg; // d e f a u l t n e x t s t a t e : t h e same
y l = l'bO; // d e f a u l t o u t p u t : 0
yo = l ' b O ; // d e f a u l t o u t p u t : 0
case (state-reg)
SO : begin
yl = l'bl;
if (a)
if (b)
begin
state-next = s2;
yo = l ' b l ;
end
else
state-next = sl;
end
sl: begin
yl = l'bl;
if (a)
state-next = SO;
end
s 2 : s t a t e - n e x t = SO;
d e f a u l t : s t a t e - n e x t = SO;
endcase
end
sa endmodule
 Figure A.2 ASMD chart of an FSMD template.

A.8 FSMD

Listing A . l l FSMD template

// code f o r t h e FSMD shown i n F i g u r e A . 2
module f i b
(
input wire clk, r e s e t ,
input wire s t a r t ,
i n p u t w i r e C4:OI i ,
 FSMD 479

output reg r e a d y , done-tick ,

output wire [19:0] f
1;
10

// symbolic s t a t e declaration
l o c a l p a r a m 11 : 01
i d l e = 2 'b00,
op = 2'b01,
IS done = 2 ' b l O ;

// s i g n a l declaration
r e g [ I : 01 state-reg , state-next ;
reg [19:0] to-reg , to-next , t l - r e g , tl-next ;
20 reg [4:01 n-reg , n-next ;

// body
// s t a t e & d a t a registers
always O(posedge c l k , posedge r e s e t )
25 if (reset)
begin
s t a t e - r e g <= i d l e ;
t o - r e g <= 0 ;
t l - r e g <= 0 ;
n - r e g <= 0 ;
end
else
begin
s t a t e - r e g <= s t a t e - n e x t ;
t o - r e g <= t o - n e x t ;
t l - r e g <= t l - n e x t ;
n - r e g <= n - n e x t ;
end
// n e x t - s t a t e l o g i c and d a t a p a t h f u n c t i o n a l units
40 a l w a y s O*
begin
state-next = state-reg; // d e f a u l t r e t u r n t o same s t a t e
ready = l'bO; // default output 0
done-tick = l'bO; // default output 0
to-next = to-reg; // d e f a u l t keep p r e v i o u s value
tl-next = tl-reg; // d e f a u l t keep p r e v i o u s value
n-next = n-reg; // d e f a u l t keep p r e v i o u s value
case (state-reg)
idle :
begin
ready = l J b l ;
if (start)
begin
to-next = 0;
tl-next = 20'dl;
n-next = i ;
state-next = op;
end
end
 61) op :
if (n-reg==O)
begin
tl-next = 0;
state-next = done;
end
else if (n-reg==l)
s t a t e - n e x t = done;
else
begin
tl-next = tl-reg + to-reg;
to-next = t l - r e g ;
n-next = n-reg - 1 ;
end
done :
begin
done-tick = l ' b l ;
state-next = idle;
end
default: state-next = idle;
endcase
end
/ / OLltplrt
assign f = tl-reg;

A.9 S3 BOARD CONSTRAINT FILE (S3 .UCF)

# Pin assignment f o r Xilinx

# Spartan-3 S t a r t e r board
.........................................................

# c l o c k and r e s e t
.........................................................
NET " c l k " LOC = " T 9 " ;
NET " r e s e t " LOC = " L 1 4 " ;

# buttons & switches

.........................................................
# 4 pushbuttons
NET " b t n < O > " LOC = "M13";
NET " b t n < l > " LOC = "M14";
NET " b t n < 2 > " LOC = "L13";
#NET " b t n < 3 > " LOC = "L14"; #btn<3> also used as r e s e t

# 8 slide switches
NET " s w < O > " LOC = " F 1 2 " ,
NET "sw<l>" LOC = "G12";
NET "sw<2>" LOC = "H14";
NET "sw<3>" LOC = "H13";
NET "sw<4>" LOC = "514";
NET "sw<5>" LOC = "513";
NET "sw<6>" LOC = "K14";
NET "sw<7>" LOC = "K13";

.........................................................
# RS232
.........................................................
NET " r x " LOC = " T 1 3 " 1 DRIVE=8 I SLEW=SLOW;
NET " t x " LOC = " R 1 3 " I DRIVE=8 I SLEW=SLOW;

.........................................................
# 4 - d i g i t t i m e - m u l t i p l e x e d 7-segment LED d i s p l a y
.........................................................
# d i g i t enable
NET " a n < O > " LOC = "D14";
NET " a n < l > " LOC = "G14";
NET " a n < 2 > " LOC = "F14";
NET " a n < 3 > " LOC = "E13";

# 7-segment l e d segments
NET " s s e g < 7 > " LOC = " P 1 6 " ; # decimul point
NET "sseg<6>' LOC = " E 1 4 " ; # segment a
NET " s s e g < 5 > " LOC = "G13" , # segment b
NET " s s e g < 4 > " LOC = " N 1 5 " ; # segment c
NET " s s e g < 3 > " LOC = " P 1 5 " ; # segment d
NET " s s e g < 2 > " LOC = " R 1 6 " ; # segment e
NET " s s e g < l > " LOC = " F 1 3 " ; # segment f
NET " s s e g < O > " LOC = " N 1 6 " ; # segment g

.........................................................
# 8 d i s c r e t e LEDs
.........................................................
NET "led<O>" LOC = "K12";
NET "led<l>" LOC = "P14";
NET "led<2>" LOC = "L12";
NET "led<3>" LOC = "N14";
NET "led<4>" LOC = "P13";
NET "led<5>" LOC = "N12";
NET "led<6>" LOC = '1P12";
NET "led<7>" LOC = "P11":

.........................................................
# VGA o u t p u t s
.........................................................
NET "rgb<2>" LOC = "R12" I DRIVE=8 I SLEW=FAST;
NET "rgb<i>" LOC = "T12" I DRIVE=8 1 SLEW=FAST;
NET "rgb<O>" LOC = "R11" I DRIVE=8 I SLEW=FAST;
NET "vsync" LOC = " T 1 0 " I DRIVE=8 I SLEW=FAST;
NET "hsync" LOC = "R9" I DRIVE=8 I SLEW=FAST;
 .........................................................
# PS2 port
.........................................................
NET "ps2c" LOC="M1GW I IOSTANDARD=LVCMOS33 I DRIVE=8 ISLEW=SLOW:
NET "ps2d1'LOC="M15" I IOSTANDARD=LVCMOS33 I DRIVE=8 ISLEW=SLOW;
.........................................................
# two SRAM chips
.........................................................
# shared 18-bit memory a d d r e s s
NET "ad<17>" LOC="L3" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<16>" LOC="KS1' I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<15>" LOC="K3" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<14>" LOC="J3" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<13>I1 LOC="J4" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<12>" LOC="H4" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<ll>" LOC="H3" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<lO>" LOC="GS" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<9>" LOC="E4" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<8>" LOC="E3" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<7>" LOC="F4" I IOSTANDARD = LVCMOS33 I SLEW=FAST:
NET "ad<6>" LOC="F3" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<5>" LOC="G4" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
IOI NET "ad<4>" LOC="L4" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<3>" LOC="M3" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<2>I1 LOC="M4" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<l>" LOC="N3" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET "ad<O>" LOC="LSM I IOSTANDARD = LVCMOS33 I SLEW=FAST;

# shared oe, we
NET "oe-n" LOC="K4" I IOSTANDARD = LVCMOS33 I SLEW=FAST;
NET " we-n" LOC="G3" 1 IOSTANDARD = LVCMOS33 I SLEW=FAST;
# sram chip 1 data, ce, ub, lb
NET "dio-a<l5>" LOC="RIN I IOSTANDARD=LVCMOS33
NET "dio-a<l4>" LOC="PIM I IOSTANDARD=LVCMOS33
NET "dio-a<13>" LOC="L2" I IOSTANDARD=LVCMOS33
NET "dio-a <l2>It LOC="J2" I IOSTANDARD=LVCMOS33
NET "dio-a<ll>" LOC="Hll' I IOSTANDARD=LVCMOS33
NET "dio-a<lO>" LOC="F2" I IOSTANDARD=LVCMOS33
NET "dio-a <9>" LOC="P8" I IOSTANDARD=LVCMOS33
NET "dio-a<8>" LOC="D3" I IOSTANDARD=LVCMOS33
NET "dio-a<7>" LOC="B1" I IOSTANDARD=LVCMOS33
NET "dio-a<6>" LOC="C1" I IOSTANDARD=LVCMOS33
NET "dio-a<5>" LOC="C2" I IOSTANDARD=LVCMOS33
NET " dio-a <4>" LOC="RS1' I IOSTANDARD=LVCMOS33
NET "dio-a<3>" LOC="TSN I IOSTANDARD=LVCMOS33
NET "dio-a<2>" LOC="RGM I IOSTANDARD=LVCMOS33
NET "dio-a<l>" LOC="T8" I IOSTANDARD=LVCMOS33
NET " dio-a <O>" LOC="N7" I IOSTANDARD=LVCMOS33
NET "ce-a-nu LOC="P7" I IOSTANDARD=LVCMOS33
NET "ub-a-n" LOC="T4" I IOSTANDARD=LVCMOS33
 53 BOARD CONSTRAINT FILE (S3.UCF) 483

NET "lb-a-n" LOC="P6" I IOSTANDARD=LVCMOS33 I SLEW=FAST;

# sram chip 2 data, ce, ub, lb

NET "dio-b<l5>I1 LOC="N1" I IOSTANDARD=LVCMOS33
NET " dio-b <l4>" LOC="M1" I IOSTANDARD=LVCMOS33
NET "dio-b<l3>" LOC="K2" I IOSTANDARD=LVCMOS33
NET "dio-b <l2>" LOC="C3" I IOSTANDARD=LVCMOS33
NET "die-b <ll>" LOC="F5" I IOSTANDARD=LVCMOS33
NET " dio-b <lo>" LOC="GI " I IOSTANDARD=LVCMOS33
NET "dio-b<9>" LOC="E2" I IOSTANDARD=LVCMOS33
NET " dio-b <8>" LOC="D2" I IOSTANDARD=LVCMOS33
NET " dio-b < 7 > " LOC='Dll' I IOSTANDARD=LVCMOS33
NET "dio-b<6>" LOC="Ell' I IOSTANDARD=LVCMOS33
NET "dio-b<5>" LOC="G2" I IOSTANDARD=LVCMOS33
NET "dio-b<4>" LOC="Jl" I IOSTANDARD=LVCMOS33
NET "dio-b<3>" LOC="Kl" I IOSTANDARD=LVCMOS33
NET "dio-b<2>" LOC="M2" I IOSTANDARD=LVCMOS33
NET "dio-b <l>" LOC="N2" I IOSTANDARD=LVCMOS33
NET "die-b<O>" LOC="P2" I IOSTANDARD=LVCMOS33
NET "ce-b-n" LOC="N5" I IOSTANDARD=LVCMOS33
NET "ub-b-n" LOC="R4" I IOSTANDARD=LVCMOS33
NET " lb-b-n" LOC="P5" I IOSTANDARD=LVCMOS33

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# Timing constraint of S3 50-MHz onboard oscillator
# name of the clock signal is clk
.........................................................
NET "clk" TNM-NET = "clk";
TIMESPEC "TS-clk" = PERIOD "clk" 40 ns HIGH 50 %;