GP600 Portable Service Manual
GP600 Portable Service Manual
Portable Radio
Service Manual
68P02909X01B
CAUTION
iii
Cautions and Warnings
iv
Cautions and Warnings
SAFETY WARNINGS
v
Cautions and Warnings
vi
Contents
Service Manual
Contents
Section
1.0 Introduction
Gives a brief introduction into the manual and the service policy.
3.0 Maintenance
Describes how to disassemble/assemble the radio for maintenance purposes
and provides lists of test equipment.
4.0 Troubleshooting
Provides troubleshooting charts to aid in the service of the radio.
5.0 Accessories
Provides a list of accesories for the GP600 radio.
Appendix
A.0 PL (CTCSS) Codes
Chapter 1
Introduction
Table of Contents
Paragraph Page
1.0 Introduction ................................................................................................ 1
Introduction 1-i
Table of Contents
1-ii Introduction
Introduction
1.0 Introduction
This chapter outlines the scope and use of the manual and provides an overview of the warranty and
service support.
This manual is intended for use by experienced technicians familiar with similar types of equipment.
It contains service information required for the equipment described and is current as of the printing
date. Changes which occur after the printing date maybe incorporated by a complete Service
Manual revision to your Product Manual or alternatively, as additions to Band Specific information.
This Service Manual contains introductory chapters giving information on warranty, safety and
assembly/disassembly. Chapter 6 contains service information in band specific sub-chapters giving
information on models, test specifications, radio tuning, theory of operation and schematics/parts
lists. Refer to the Table of Contents for a general overview of the manual.
Introduction 1-1
Warranty and Service Support
Motorola offers long term support for its products. This support includes full exchange and/or repair
of the product. Any return-for-exchange or return-for-repair must be accompanied by a Warranty
Claim Form. Warranty Claim Forms are obtained by contacting Motorola Customer Services.
If within 30 days of the date-of-purchase, a malfunction with the product is encountered, a check of
the product should be performed. The check should insure the product is correctly programmed and
is free from mechanical malfunctions. If the check doesn't solve the problem, please contact
Motorola Customer Services who will make arrangements for a full exchange on a product-for-
product basis. Any exchange under this program will require a Warranty Claim Form which is
available from Motorola Customer Services. The product is to be returned to Motorola prior to
exchange of the product, at the end-user’s expense, together with the Warranty Claim Form.
The return process may change from time to time. In order to ensure the fastest possible return to
Motorola, please contact the Motorola office where the product was purchased, for full details.
Please return the product in the original shipping carton with the original packing materials. If this is
not possible, package the product to assure no damage during transit.
After 30 days from the date-of-purchase and for the remainder of the warranty period, the provisions
of the warranty are in effect. During this period, the product will be repaired or exchanged on a
product-for-product basis at the discretion of Motorola.
If a malfunction with the product is encountered, a check of the product should be performed. The
check should insure the product is correctly programmed and is free from mechanical malfunctions.
If the check doesn't solve the problem, please contact Motorola Customer Services who will make
arrangements for a return-for-repair. Any return- for-repair under this program will require a Warranty
Claim Form which is available from Customer Services. The product is to be returned, at the end-
user’s expense, together with the Warranty Claim Form to Motorola.
The return process may change from time to time. In order to ensure the fastest possible return to
Motorola, please contact the Motorola Customer Service office from where the product was
purchased, for full details. Please return the product in the original shipping carton with the original
packing materials. If this is not possible, package the product to assure no damage during transit.
After the warranty period, Motorola continues to support products through repair. Repair is handled
on a flat fee basis. The fees charged for this service depends on the product. The product is to be
returned at the end-user’s expense to Motorola.
The return process may change from time to time. In order to ensure the fastest possible return to
Motorola, please contact the nearest Motorola Service Depot for full details. Please return the
product in the original shipping carton with the original packing materials. If this is not possible,
package the product to assure no damage during transit.
1-2 Introduction
Warranty and Service Support
Some replacement parts, spare parts, and/or product information can be ordered directly. If a
complete Motorola part number is assigned to the part, it is available from Motorola. If a generic part
is listed or only a part description is listed, the part is not normally available from Motorola. If a parts
list is not included, this generally means that no user-serviceable parts are available for that kit or
assembly. All orders for parts/information should include the complete Motorola identification
number. All part orders should be directed to:
Motorola G.m.b.H.
European Parts Department
65232 Taunusstein
Germany
Motorola Product Services is available to assist the dealer/distributors in resolving any malfunctions
which may be encountered. Initial contact should be by telephone whenever possible. When
contacting Motorola Technical Support, be prepared with the product model number and the unit’s
serial number.
Introduction 1-3
Warranty and Service Support
1-4 Introduction
Table of Contents
Chapter 2
Safety Information
Table of Contents
Paragraph Page
1.0 Overview ..................................................................................................... 1
1.0 Overview
2.0 General
While designed for rugged use, the radios are not indestructible. Some general guidelines to assure
long life of the radio are:
The radios are not designed for use in Hazardous Environments! Other radios which are qualified for
use in hazardous environments are clearly labelled.
■ DO NOT operate the radio near unshielded explosive and/or explosives-detonation devices
such as blasting caps or electronic triggers.
■ DO NOT operate the radio in an explosive atmosphere or near explosive gases.
■ DO NOT attempt hazardous environment modification in the field or during repair.
4.0 RF Exposure
The radios perform well below the human RF exposure safety standards set for by Federal
Communications Commission General Docket action 79144, of March 13, 1985 when the safety
guidelines of this manual are followed. The guidelines are:
■ Hold the radio in a vertical upright position about 5-10 cm from the face so the antenna does
not touch, or come in close contact with any exposed parts of the body.
■ DO NOT press the transmit (PTT) unless transmitting.
■ DO NOT allow children to operate the radio.
The radios use Nickel-Cadmium batteries. Improper care and use of the batteries can lead to
damage of equipment, possible injury or affects on health. The proper care for these batteries
include:
WARNING: To prevent injury or burn, do not allow metal objects to contact or short
circuit the battery terminal.
■ DO NOT use new batteries before they are fully charged! New batteries are not charged.
■ DO NOT Quick-Rate charge new batteries. New batteries must be slow-charged the first time.
■ DO NOT transmit on a radio when the battery is being charged.
■ Use only Motorola Chargers. Use of other chargers void battery warranty and may damage
the battery and/or charger.
■ Use the charger only with the battery installed.
■ Charge batteries at about 77°F (25°C). Charging below 45°F (8°C) may cause damage and
leakage. Charging batteries over 95°F (34°C) reduces the battery charging capacity.
■ DO NOT get the batteries and/or charger wet during installation or charging.
■ DO NOT dispose of batteries by fire. High temperatures may result in explosion and/or
release of hazardous materials.
■ Dispose of batteries carefully. Batteries contain cadmium which is toxic. Batteries should be
recycled or disposed of with proper care.
Before using a battery charger, read all instructions and cautions on the radio, the battery pack, the
battery charger and the charging adapter.
Chapter 3
Maintenance
Table of Contents
Paragraph Page
1.0 Overview..................................................................................................... 1
Maintenance 3-i
Table of Contents
3-ii Maintenance
Overview
1.0 Overview
3
This chapter explains, step by step, how to disassemble and assemble the radio. The chapter also
contains a list of test equipment required to service the radio.
2. Press the battery housing against the radio, while sliding it down until it is free of the chassis
rails (Figure 3-2).
UHF
Battery
housing
3. To remove the battery, pull it straight out and away from the radio.
Maintenance 3-1
How to Disassemble the Radio
IMPORTANT: You must disconnect the ribbon cable before completely removing the
chassis.
5. Remove the ribbon cable connector from the main board using pliers or a flat blade screw-
driver (Figure 3-4).
Front Cover
Flexible Circuit
6. Pull the chassis out and away from the housing as shown by the arrow (Figure 3-4) and
beware of the front cover flexible circuit.
7. Remove the flexible circuit using a pair of tweezers or manually unlatching the ZIF connector
(Figure 3-5).
3-2 Maintenance
How to Disassemble the Radio
Chassis
Gasket
Main board
Locking clips
Maintenance 3-3
How to Disassemble the Radio
6. Separate the flexible circuit tail by undoing the ZIF connector latch (Figure 3-7).
.
3-4 Maintenance
How to Reassemble the Radio
3. Insert main board into chassis using alignment pins as a guide (Figure 3-9).
4. Place front shield on main board using tabs as a guide (Figure 3-9).
5. Press down on front shield until chassis, main board, and front shield are seated tightly
together.
6. Hook locking clips first to the chassis tab, then push clips over on shield with thumb until clips
lock into front shield holes (Figure 3-10).
Maintenance 3-5
How to Reassemble the Radio
9. Insert the flexible circuit tail from chassis to ZIF connector on front housing board. Lock the
tail in the ZIF connector by pressing down the latch.
Note: Flexible circuit tail must be fully inserted to prevent short circuit.
Note: The gasket helps keep the radio free from unwanted dirt, dust, and water. We recommend
using a new lubricated gasket when reassembling the radio. Using an old gasket could
impair the overall seal quality of the radio.
10. Insert assembled chassis, main board, and front shield into radio housing at approximately a
45-degree angle (Figure 3-12) using caution while inserting the volume and frequency con-
trols through the housing top.
IMPORTANT: The main board must be inserted into chassis (Step 2) before you can
secure chassis into radio housing.
11. Connect microphone/speaker ribbon cable (Figure 3-12).
12. While pressing chassis toward the housing top, press the bottom end down into the housing
until the bottom housing wall snaps over the chassis retaining studs.
3-6 Maintenance
How to Reassemble the Radio
5. Press down the shield at the four tabs until tabs lock into the front housing catches.
Maintenance 3-7
How to Reassemble the Radio
3-8 Maintenance
Mechanical Exploded View Diagram
21
23
10 12
20
19
11 29
31 27
8 28
18 7 30
13 43
14 15
16
39
17 9 33
42 35 34
41
32
2
36
38
37
4 3
1
26
5 25
24
Maintenance 3-9
Service Aids
Motorola
Description Application
Part No.
HLN9214 Radio Interface Box Enables communication between the radio and the compu-
ter’s serial communications adapter.
HSN9412 RIB Power supply Used to supply power to the RIB.
HKN9216 Computer Interface cable Connects the computer’s serial communications adapter to
the RIB.
HLN9390 AT to XT Computer adapter Allows HKN9216 to plug into a XT style communications
port.
HKN9857 Programming / test cable Connects radio to RIB. And can be used as a
Battery Eliminator.
HKN9755 Cloning Cable Allows the radio to be duplicated from a master radio by
transferring programmed data from one radio to another.
RTX4005 Portable Test Set Enables connection to the audio / accessory jack. Allows
switching for radio testing.
RKN4034 Test Set cable Connects radio to RTX4005 Test Box.
Figure 3-16 Service Cable (RKN4034) for the Test Set (RTX4005).
3-10 Maintenance
Test Equipment
Motorola
Description Characteristics Application
Model No.
R2200, R2400, Service Monitor This monitor will substi- Frequency/deviation meter and
or R2001D with tute for items with an signal generator for wide-range
trunking option asterisk * troubleshooting and alignment
*R1049A Digital Multimeter Two meters recommended for ac/
dc voltage and current
measurements
*S1100A Audio Oscillator 67 to 161.4Hz tones Used with service monitor for
injection of PL tones
*S1053D, AC Voltmeter, Power 1mV to 300V, 10Mohm Audio voltage measurements
*SKN6009A, Cable for meter, Test input impedance
*SKN6001A leads for meter
R1053 Dual-trace 20 Mhz bandwidth, Waveform measurements
Oscilloscope 5mV/cm - 20V/cm
*S1350C, Wattmeter, Plug-in 50-ohm, + 5% accuracy Transmitter power output
*ST1223B (UHF), Elements (UHF), RF 10 Watts, maximum measurements
*T1013A Dummy Load 0-1000 Mhz, 300W
S1339A RF Millivolt Meter 100uV to 3V rf, 10 khz RF level measurements
to 1.2 Ghz
*R1013A SINAD Meter Receiver sensitivity
S1347D or DC Power Supply 0-20 Vdc, 0-5 Amps Bench supply for 10Vdc
S1348D ( prog )
Maintenance 3-11
Test Equipment
3-12 Maintenance
Table of Contents
Chapter 4
Troubleshooting Charts
Table of Contents
Paragraph Page
1.0 Overview..................................................................................................... 1
Figure
4-1 Troubleshooting Flow Chart for Receiver............................................................................. 2
4-2 Troubleshooting Flow Chart for Transmitter......................................................................... 2
4-3 Troubleshooting Flow Chart for Synthesiser ........................................................................ 2
4-4 Troubleshooting Flow Chart for Microprocessor .................................................................. 2
4-5 Troubleshooting Flow Chart for Voltage Controlled Oscillator (VCO) .................................. 2
1.0 Overview
4
This section contains troubleshooting charts for the following radio components:
■ Receiver
■ Transmitter
■ Synthesiser
■ Microprocessor
■ Voltage Controlled Oscillator (VCO)
Start
1
Very low or no 12
Check IFIC
dB SINAD U51 (see Is 2nd LO on NO Are VDC of
freq? NO
below) pins 7,9, and
10 of IFIC
YES OK?
Noise at spkr NO YES
when radio is Noise at pin 23 NO
Check VDC of
unsqu’d? of IFIC U51? all IFIC pins
Check 2nd LO
XTAL and
YES YES components
Are YES
NO Check ASFIC voltages on
Is 1st LO at Check pins OK? Check IFIC
T2 3dBM? VCO/Synth (see below)
NO
YES Check external
Check external components
Inject on channel components connected to IFIC
signal at RF port connected to IFIC. If
of T1 OK, replace U51
YES NO
NO Is 12 dBS -117
dBm?
Inject Signal at
IF Port of T1 Check
at 45.1 MHz harmonic
filter and
antenna path NO
4.1VDC at
Pin 3 of U1
Is YES
12 dBS Check mixer
-120dBm? components YES
Start
No
Power
Is the Inspect:
NO 1)Controller flex
LED’s red light
on or not? 2)Voltage Regulator
YES
NO NO
Is Tx B+ Is Biasing of Replace
OK? Q154 OK? Q154
YES YES
NO Is
Replace PA Power Out of HIGH
Module Pin 6 at PA
OK
NO
Is PA Drive Troubleshoot
YES OK? VCO
Replace PA
Module
Inspect/Repair
TX Output
Network
Is YES
Power Done
OK?
NO
Replace PA
Module
Start
Visual
Correct NO
check of the
Problem Board OK?
Check 5V
YES Regulator
NO Is U201 Pin 32
AT = 13 VDC
+5V at U201 NO
Pin’s Is 16.8MHz NO Check
YES 12,22,23 Signal at Y201,C205,C206,R20
Check C202, &3 U201 Pin 14? 7 and CR203
C203, CR201 Fix YES
CR202 and C204 Connection YES
Are signals NO
Is U201 Pin 1 NO
at Pin’s 9 & Are Waveforms NO
<0.7 VDC in RX &
10 of U201? at Pins 9 & 10
>4.3 VDC in TX?
triangular?
YES
YES
Is Connection NO
between Pin 10 NO Do Pins 5,6 & 7
& of U201 toggle
Pin 1 OK? when channel is
NO
Is U201 Pin 18 changed?
NO Is there a short
AT4.65 VDC?
between Pin 32 and
YES Pins 9 & 10 of Check programming
U201? lines between U401
and U201 Pins 5,6 & 7 YES
Replace U201
YES YES
Remove
Shorts
NO
Is information
If line between
from µP U401
Pin 16 &3 of correct?
U257 OK then
Is RF level at NO
replace U201
Pin 20 Check µP U401
between -10 & Troubleshooting
Chart YES
+5 dBm?
Replace U201
If L203,C224,C226 & C227
YES and runners between
U201 Pin 20 & U251 Pin 23
are OK, then see VCO
troubleshooting chart
YES
Replace U201
START
YES
YES
Reprogram radio
Use RSS to Enable Tones with RSS. Apply
NO
Was good power-on beep power to radio and
present? turn on.
Are
YES Alert Tones
Enabled with YES
RSS?
DONE
NO
NO Was good
Check Radio power-on
Connection to Rib beep present
and Computer ?
YES
DONE
Main radio board must
be replaced
NO RIB/Radio
Connections
OK?
YES DONE
NO
With power connected to radio and the radio turned
on check the following: Are
tones present
on power up at
1) 5V at pin 4 of U704 and pin 71,12,31,41 of U709. U701 pin 66?
2) Check for 7.9488 MHz at pin 73 OF U709.
3) Check DC at pin 75 of U709. If < 4.5VDC check
U701 pin 38 for 2.1 MHz signal. YES
4) Check for typical voltages of U709 and U701.
Audio problem. Trouble-
shoot audio circuitry DONE
RX VCO TX VCO
Low or no Power Low or no power Power OK but no
at T2 of Mixer at U101 Pin 1 Modulation
YES YES
YES
0.7 VDC at NO Check runner NO 4.3 VDC at
U251 Pin 5? between U201 Pin 1 U251 Pin 5? If C284 and R254
and U251 Pin 5
are OK, then
replace CR255
YES
YES
YES Replace
YES L252
YES
YES
YES
If all parts from U251 Pin 2 to
If all parts from U251 Pin 4 to
T2 of mixer are OK, then
U101 Pin 1 OK, then replace
replace U251
U251
Figure 4-5 Troubleshooting Flow Chart for Voltage Controlled Oscillator (VCO).
Chapter 5
Accessories
Table of Contents
Paragraph Page
1.0 GP600 Accessories ....................................................................................1
1.1 Antennas.......................................................................................................1
1.2 Carrying Accessories....................................................................................1
1.3 Nickel-Cadmium Battery Chargers ...............................................................1
1.4 Batteries........................................................................................................1
1.5 Audio/RF Accessories ..................................................................................1
Accessories 5-i
Table of Contents
5-ii Accessories
GP600 Accessories
This chapter lists the accessories for the GP600 portable radio.
1.1 Antennas
1.4 Batteries
HNN9628_ 1200 mAH High Capacity Battery
HNN8308_ 600 mAH Slimline Battery
Accessories 5-1
5-2 Accessories
Table of Contents
Chapter 6
Band Specific Information
Chapter Page
6A UHF (403-433MHz) ............................................................................. 6A.1-i
Chapter 6A
403-433MHz Specific Information
Table of Contents
Chapter
6A.1 Model Chart and Test Specifications
Chapter 6A.1
Model Chart and Test Specifications
Table of Contents
Paragraph Page
1.0 Overview......................................................................................................1
1.0 Overview
6A.1
This chapter lists the UHF (403-433MHz) models and technical specifications for the GP600
portable radio.
2.0 UHF Model Chart GP600 403-433 MHz 12.5 kHz 4W MPT D
GP600 403-433 MHz 12.5 kHz 4W MPT
GP600
Description
UHF
403 - 433 MHz
X = Indicates one of each required
AZP94VJB05N1_E
AZP94VJA05N1_E
Model
Item Description
X X PMLE4022_ RF Board, 12.5 kHz, (403-433 MHz)
X PMLN4086_ GP600 Front Cover Display Kit
X PMLN4087_ GP600 Front Cover Non-Display Kit
X X HLN9667_ Chassis Hardware Assembly
X X NAE6483_ Whip Antenna (403-470 MHz)
X X HNN9628_ Battery
X X 6802908X01_ GP600 User Guide
12.5kHz 20/25kHz
Sensitivity*
12dB SINAD (emf) µV 0.35µV 0.35µV
20dB SINAD (emf) µV 0.5µV 0.5µV Note: Self Quieting Frequencies
Audio Output Power
Self-quieting frequencies are frequencies
<5% distortion @1kHz 500 mW 500 mW
that are also generated by the radio and
with rated audio output
cause internal interference. On these
Spurious / Image 70 dB 70 dB frequencies the interference caused by the
Rejection self-quieter spur is great enough that a
radio will not meet its receiver sensitivity
Selectivity 60 dB 60 dB
specification.
Intermodulation 65 dB 65 dB
The frequencies are:
Switching Bandwidth 30 MHz 403.2, 411.6, 420.0 and 431.55MHz
No degradation ....... ..... .
Chapter 6A.2
Radio Tuning Procedure
Table of Contents
Paragraph Page
1.0 GP600 Radio Tuning .................................................................................. 1
1.1 General ........................................................................................................ 1
1.2 Transmitter Power ....................................................................................... 2
1.3 Reference Oscillator .................................................................................... 3
1.4 Rated Volume .............................................................................................. 3
1.5 Squelch Attenuation..................................................................................... 4
1.6 Transmit Deviation Balance (Compensation) .............................................. 4
1.7 Transmit Deviation Limit .............................................................................. 5
1.8 RSSI ............................................................................................................ 5
1.9 MPT1327 Transmit Deviation / DTMF Transmit Deviation .......................... 6
1.1 General
The recommended hardware platform is a 386 or 486 DX 33 PC (personal computer) with 8 Mbytes
RAM, MsDOS 3.3, Windows 3.1 or later, and DPS (Dealer Programming Software). These are
required to align the radio. Refer to the DPS Installation Manual (section 2 of the Product Manual) for
installation and setup procedures for the required software; the user manual is accessed (and can
be printed if required) via the DPS.
To perform the alignment procedures, the radio must be connected to the PC, RIB (Radio Interface
Box), and Universal Test Set as shown in figure 2-1.
SERVICE MONITOR
30 dB PAD OR COUNTER
TRANSMIT
30 dB PAD WATTMETER
BNC
RF GENERATOR
SMA-BNC RECEIVE
58-80348B33
AUDIO IN TX
BATTERY TEST SET AUDIO GENERATOR
ELIMINATOR RTX-4005B
RLN-1014A RX
SINAD METER
RADIO TEST CABLE
RKN4034
AC VOLTMETER
PROGRAM/TEST CABLE
HKN9857
COMPUTER
RIB DATA
HLN9214 BUSY
GND
Before going into the Service menu, the radio must first be read using the File / Read Radio menu (if
the radio has just been programmed with data loaded from disk or from a newly created codeplug,
then it must still be read so that the DPS will have the radio’s actual tuning values).
All Service windows read and program the radio codeplug directly; you do NOT have to use the DPS
Read Radio / Write Radio functions to program new tuning values.
CAUTION: DO NOT switch radios in the middle of any Service procedure. Always use
the Program or Cancel key to close the tuning window before disconnect-
ing the radio. Improper exits from the Service window may leave the radio
in an improperly configured state and result in seriously degraded radio or
system performance.
The Service windows introduce the concept of the “Softpot”, an analog SOFTware controlled
POTentiometer used for adjusting all transceiver alignment controls. A softpot can be selected by
clicking with the mouse at the value or the slider or by hitting the TAB key until the value or the slider
is highlighted.
Each Service window provides the capability to increase or decrease the ‘softpot’ value with the
mouse, the arrow keys or by entering a value with the keyboard. The window displays the minimum,
maximum, and step value of the softpot. In addition transmitter tuning windows indicate the
transmitter frequency and whether the radio is keyed.
Adjusting the softpot value sends information to the radio to increase (or decrease) a DC voltage in
the corresponding circuit. For example, increasing the value in the Reference Oscillator tune window
instructs the radio microprocessor to increases the voltage across a varactor in the reference
oscillator to increase the frequency. Pressing the Program button stores all the softpot values of the
current window permanently in the radio.
In ALL cases, the softpot value is just a relative number corresponding to a D/A (Digital-to-Analog)
generated voltage in the radio. All standard measurement procedures and test equipment are
similar to previous radios.
Refer to the DPS on-line help for information on the tuning software. Perform the following
procedures in the sequence indicated.
Note: All tuning procedures must be performed at a supply voltage of 7.5V unless
otherwise stated.
The radio requires two power level settings, a high power level setting, and a low power level setting.
To set the transmitter power, either to high or low setting, follow the procedures below:
Adjustment of the reference oscillator is critical for proper radio operation. Improper adjustment will
not only result in poor operation, but also a misaligned radio that will interfere with other users
operating on the adjacent channels. For this reason, the reference oscillator should be checked
every time the radio is serviced. The frequency counter used for this procedure must have a stability
of 0.1 ppm (or better).
RF-Band Target
UHF ±150 Hz
The rated volume softpot sets the volume at normal test modulation.
1. Use test box (RTX4005) and set SW1 switch to speaker. Connect an AC voltmeter to the test
box meter port.
2. From the Service menu, select Receiver Alignment.
3. Select Rated Volume to open the rated volume tuning window. The screen will indicate the
receive test frequency to be used.
4. Set the RF test generator to the receive test frequency and apply -47 dBm RF carrier frequency
with a 1 kHz tone at 60 % rated deviation. The 1 kHz tone must be audible to make sure the
radio is receiving.
5. Adjust the value of the obtained rated audio volume ( as close as 2.7 Vrms)
6. Press Program to store the softpot value.
The squelch softpots set the signal to noise ratio at which the squelch opens. The squelch value
needs to be set at 7 frequencies across the frequency range.
1. Use test box (RTX4005), connect a SINAD meter to the “METER” port.
2. From the Service menu, select Receiver Alignment.
3. Select Squelch Attenuation to open the squelch attenuation tuning window. The window will
indicate the receive test frequencies to be used.
4. Select the first test frequency shown, and set the corresponding value to 0.
5. Set the RF test generator to the test frequency, offset it with +500 Hz, and modulate it at 60 %
deviation with 1 kHz tone. Adjust the generator for a 18 dB SINAD level (weighted with
psophometric filter).
6. Adjust the softpot value until the squelch just closes.
7. Monitor for squelch chatter; if chatter is present, repeat step 6.
8. When no chatter is detected, select the next softpot and repeat steps 5 -7 for all test
frequencies shown in the window.
9. Press Program to store the softpot values.
Compensation alignment balances the modulation sensitivity of the VCO and reference modulation
(synthesizer low frequency port) lines. Compensation algorithm is critical to the operation of
signalling schemes that have very low frequency components (e.g. DPL) and could result in
distorted waveforms if improperly adjusted. The compensation value needs to be set at 7
frequencies across the frequency range.
Note: The step size change for step 8 is approximately 2.5% softpot value.
The transmit deviation limit softpot sets the maximum deviation of the carrier. The deviation value
needs to be set at 7 frequencies across the frequency range.
1.8 RSSI
1. Use test box (RTX4005) and set the SW1 switch to SPEAKER.
2. From the Service menu, select Receiver Alignment.
3. Select RSSI to open the RSSI tuning window. The screen will indicate the receive test
frequency to be used.
4. Set the RF test generator to the receive test frequency, and set the RF level to the value
indicated for RSSI Level 0, modulated with 1 kHz tone at 60 % deviation. The 1 kHz tone must
be audible to make sure the radio is receiving.
5. Press Program to store the softpot value for RSSI Level 0.
6. Repeat steps 4 - 5 for the remaining RSSI levels.
7. Press Cancel to close the window.
The MPT1327 Deviation Softpot is used to tune the FFSK signalling deviation. Tuning is performed
at one frequency. The radio generates an alternating bit pattern for tuning. Values for others
frequencies are calculated by the radio software.
The DTMF Deviation Softpot is used to tune the DTMF signalling deviation. Tuning is performed at
one frequency. The radio generates a DTMF signal for tuning. Values for other frequencies are
calculated by the radio software.
Chapter 6A.3
Theory of Operation
Table of Contents
Paragraph Page
1.0 Overview..................................................................................................... 1
4.0 Controller.................................................................................................... 8
4.1 Functions ..................................................................................................... 9
4.2 Normal Operation ........................................................................................ 9
4.3 Clock Synthesizer ........................................................................................ 9
4.4 Bus Operation.............................................................................................. 9
4.5 RAM............................................................................................................. 9
4.6 EEPROM ................................................................................................... 10
4.7 SPI Interface .............................................................................................. 10
4.8 LED Control ............................................................................................... 10
4.9 Audio & Data Circuitry ............................................................................... 10
4.10 External PTT Sense Circuits...................................................................... 11
4.11 MIC Amplifier ............................................................................................. 11
4.12 TX Data Circuits......................................................................................... 11
4.13 Sub-Audible Data (PL/DPL)....................................................................... 11
4.14 High-Speed Data ....................................................................................... 12
4.15 DTMF Data ................................................................................................ 12
4.16 MDC Data .................................................................................................. 12
4.17 RX Audio Processing and Digital Volume Control ..................................... 12
Paragraph Page
4.18 Audio Power Amplifier ............................................................................... 13
4.19 Audio PA Muting and Output Protection .................................................... 13
4.20 Receive Data Circuits ................................................................................ 13
4.21 Alert Tone Circuits ..................................................................................... 13
Figure
3-1 RF Block Diagram.................................................................................................................1
3-2 Receiver Block Diagram .......................................................................................................2
3-3 Transmitter Block Diagram ...................................................................................................4
3-4 Synthesizer Block Diagram...................................................................................................5
3-5 VCO Block Diagram..............................................................................................................6
3-6 Controller Block Diagram......................................................................................................8
1.0 Overview
6A.3
This section provides a detailed theory of operation for the GP600 and its components:the receiver,
the transmitter, the frequency generation circuitry, the controller and audio & data circuitry.
2.0 RF Section
A block diagram of the RF section is shown in figure 3-1. The Rf section of the radio is divided into
Receiver and Transmitter functions.
Ref. Oscillator
Rx. Lo
Tx. Lo FRACT_N
VCO Mod. In
RF SYNTHESISER 28
PA Pin
Conn.
Mod.
ATTN Lock Det.
Current
Sense
Vctrl Prescalar
2.1MHz
Vref Reset Spi bus
Power
Control DAC
Circuit
Tx. MIC
Spi bus Audio Int./Ext
to AMP Mic
Rx./Tx, LED Rx. Audio
in from ASFIC
Int./Ext. Audio Pa ASFIC
Speaker
From
5V
REG. Reg. 5V
Batt.
PA Enable from
ASFIC
2.1 Receiver
The receiver of the GP600 radios consists of 4 major blocks each: the front-end module, the double
balanced mixer, the 45.1 MHz IF and the back-end IF IC.
The GP600 front-end modules consist of three blocks of circuitry each: a pre-selector, RF amplifier
and a post-selector filter. These three items are located on a receiver module pc-board that stands
perpendicular to the main radio PCB.
This module is enclosed in a shield to prevent radiation into and out of the module. It also improved
the grounding of the module by soldering the module shield to the main RF Board. All filters on the
UHF modules are fixed tuned designs to eliminate the need for factory tuning and to provide wide-
band operation.
“5R” (5V)
1st RF 2nd
Bandpass Bandpass
Filter Amp Filter
“5R” (5V)
Detected Audio
1st IF 2nd
Crystal Crystal IF IC
Filter Amp Filter
The shunt coupled resonator topology yields a more symmetrical frequency response to guard
against strong out of band signals that could produce IM products.
The pre-selector filter is a 4-pole, .01 dB Chebyshev bandpass design implemented in a shunt
coupled resonator topology. This topology maximizes the attenuation at the worst case image
frequency for UHF band which is 90.2 MHz below the filter passband. The 3 dB bandwidth is
approximately 52 MHz. The center of the band insertion loss is approximately 3.5 dB. The 4-pole
filter is designed to operate with a 50 ohm input termination, while the output termination is the input
impedance of the RF amplifier that follows it.
The RF amplifier, Q1, is a Motorola MMBR941 NPN device biased in a common emitter
configuration. The amp is stabilized by the shunt feedBack resistor R3, and has approximately 20 dB
of gain with a noise figure of about 2.5 dB. The amplifier draws 4.9 ma of current and is supplied by
the receiver 5 volt supply (indicated as “5R” on the schematics and block diagrams).
Terminating the RF amplifier is the post-selector filter. This filter is the same as the prefilter. The filter
is designed to be terminated with the amplifier output impedance on one side, and 50 ohm on the
other.
The net gain from the receiver module is about 12.5 dB in the center of the band and about 11.5 dB
at the band edges. The net center of the band noise figure is approximately 5.5 dB. This is sufficient
to achieve a typical center of the band sensitivity of 12 dBs.
The double balanced mixer is composed of the two baluns, T1 and T2, and the ring diode IC, CR2.
The mixer operates with an LO level of +6 dBm and the conversion loss is approximately 7.5 dB. The
double balanced type mixer provides excellent isolation between any two ports. And since a dBm
can operate over a large bandwidth, the same mixer can be used for UHF radios. The dBm also
provides excellent protection against receiver spurs due to non-linearizes, such as IM and Half-IF.
The received signal mixes down to the frequency of the first IF, 45.1 MHz, and enters the IF circuitry.
The Intermediate Frequency (IF) section of the portable radio consists of several sections including,
the high IF, the second LO, the second IF, and the IF IC chip. The first LO signal and the RF signal
mix to the IF frequency of 45.1 MHz, and then enters the IF portion of the radio.
The signal first enters the high IF, passes through a crystal filter, is then amplified by the IF amp, and
then passed through another crystal filter. The first crystal filter provides selectivity, second image
protection, and intermodulation protection. The amplifier provides approximately 16 dB of gain to the
signal. The signal then passes through the second crystal filter which provides further selectivity and
second image protection. The high IF has an approximate 3 dB bandwidth of 7 kHz for 20/25 kHz
models and 4 kHz for 12.5kHz models.
The filtered and amplified IF signal then mixes with the second local oscillator at 44.645 MHz. The
second LO uses an amplifier internal to the IF IC, an external crystal and some external chip parts.
The oscillator presents an approximate level of -15 dBm to the second IF mixer, internal to the IF IC.
The output of the mixing of the IF signal and the second LO produces a signal at 455kHz (second
IF). This signal is then filtered by external ceramic filters and amplified. It is then passed back to the
IF IC, sent to a phase-lock detector, and demodulated. The resulting detected audio output is then
sent to the ASFIC to recover the audio.
The IF IC also controls the squelch characteristics of the radio. With a few external parts the squelch
tail, hysteresis, attack and delay were optimized for the radio. The ASFIC allows the radio’s squelch
opening to be electronically adjusted.
2.2 Transmitter
The GP600 transmitters contain five basic circuits: a power amplifier, an antenna switch, a harmonic
filter, an antenna matching network, and a power control. Refer to the block diagram and the
schematic for more information.
The power amplifier used for transmitters is the LD-MOS module. The LD-MOS is capable of
supplying an output power at 6.8W with an input signal of 2mW and a supply voltage of 7.3V. The
power out can be varied by changing the biasing voltage at the first stage.
The antenna switch circuit consists of two PIN diodes (CR101and CR102), a pi network (C119,
L112, and part of C112), and at least one current limiting resistor R102 for UHF. In the transmit
mode, TX B+ is applied to the circuit to bias the diodes “on”. The shunt diode (CR102) shorts out the
receiver port, and the pi network, which operates as a quarter wave transmission line, transforms
the low impedance of the shunt diode to a high impedance at the input of the harmonic filter. In the
receive mode, the diodes are both off, and hence, there exists a low attenuation path between the
antenna and receiver ports.
The harmonic filter consists of part of C112, and L107, C113, L108, C114, L109, and C115. The
design of the harmonic filter for UHF is that of a Zolotarev design. This particular design is similar to
that of a Chebyshev filter except for a large amplitude first ripple (near dc). This type of filter has the
advantage that it can give greater attenuation in the stop-band for a given ripple level.
Another feature of this type of filter is that the coils tend to be smaller than with a Chebyshev design.
To optimize the performance of the transmitter and receiver into an antenna, a network is used to
match the antenna’s impedance to the harmonic filter. For UHF the network is made up of L111.
Note that, in order to measure the power out of the transmitter, one must remove the antenna and
screw in its place a special BNC-to-Phono adapter.
PTT
Power µP Serial
Ip R101 Control *Note: Connection to 50 ohms
Bus
can only be made by removing
antenna and screwing in its
Sw B+ place special BNC-to-Phono
adapter (5880166s01).
The power control circuit consists of the networks associated with U151, Q156, Q151, Q152, Q155,
and U152. The Op Amp U151A-1 and Q156, along with resistor R101, make up a current-to-voltage
amplifier whose gain is mainly dependent upon the ratio of R179 to R153. The current to the final
stage of the power module is supplied through R101 (0.1 Ohms), which provides a voltage
proportional to the current drain. This voltage is amplified and applied to the input of U151B. The
resistors at the input of U151A-1 (R151, R152, R154, and R155) keep the voltages at the inputs of
U151A-1 below its maximum allowable. These resistors are 1% tolerance parts to minimize the error
produced at the emitter of Q156 resulting from the voltage offset at the input of U151A-1.
The voltage at the other input of the summing amp, U151A-2, is supplied from two DACs contained
within U152. These DACs are controlled by the microprocessor, and provide the reference voltage
for the control loop. One of the DACs, that connected to Pin 9 of U152, provides a coarse tune
voltage, while the other provides a fine tune voltage.
Since the output of the DACs is not zero when they are set to their lowest level, resistor R169 is
provided to bias up the minus input of the summing amp to compensate for the bias resulting from
the DACs.
The error voltage at the input of U151A-2 produces a voltage at its output, which is in turn applied to
the series pass transistor, Q152, through its driver, Q151. The voltage at the collector of Q152 is
applied to the controlled stage of the power module, which for UHF is the module’s second stage.
The feedback from the collector of Q152 to the emitter of Q151 through R166 is provided to keep the
two stages stable. Likewise, the feedback from the collector of Q152 to the minus input of the
summing amp is to keep the whole control loop stable.
The purpose of Q155 and its associated circuitry is to keep the control voltage on the module below
7.0 Volts, which is the maximum allowed for the UHF module.
The purpose of R173 was originally that of providing compensation to the control loop for changes in
the supply voltage, TX B+. However, experimentation has shown that this compensation is not really
required. Also, thermistor, R170, was provided to enable the shut back of the PA in the event that it
would get too hot. This has also been shown to not be required
The supply for the synthesizer is from Regulated 5 Volts which also serves the rest of the radio. The
synthesizer in turn generates a superfiltered 5 Volts (*actually 4.65 Volts) which powers U251.
In addition to the VCO, the synthesizer must interface with the logic and ASFIC circuitry.
Programming for the synthesizer is accomplished through the data, clock, and chip enable lines
(pins 1, 2, and 35) from the microprocessor, U709. A serial stream of 98 bits is sent whenever the
synthesizer is programmed. A 5 volt dc signal from pin 2 indicates to the microprocessor that the
synthesizer is locked while unlock is indicated by a low voltage on this pin. Transmit modulation from
the ASFIC is applied to pin 8 of U201. Internally the audio is digitized by the Fractional-N and
applied to the loop divider to provide the low-port modulation. The audio is also run through an
internal attenuator for modulation balancing purposes before being outputted at pin 28 to the VCO. A
2.1 MHz clock for the AFIC is generated by the Fractional-N and is routed to pin 9 where it is filtered
and attenuated from 2.5 Volts to approximately 2 Volts.
3.1 Synthesizer
The Fractional-N synthesizer uses a 16.8 MHz crystal (Y201) to provide the reference frequency for
the system. The other reference oscillator components external to the IC are C205, C206, R207,
and CR203. The 16.8 MHz signal is divided down signal from the VCO. The loop filter, comprised of
R201, R202, R205, C201, C214, C215, and C216, provides the necessary d.c. steering voltage for
the VCO as well as filtering of spurious signals from the phase detector.
Data (5) 5
(U201) 2 Lock Det (to µP U709)
Clock (6) 6 FRACTIONAL_N
SYNTHESISER 11 Mod out (to ASFIC U701)
Cex (7) 7
28 Mod out (to VCO modulation)
Mod In (8) 8
Reg 5V 12,19,22,23,3
lout
GND (4,21,13,30) 4,21,13,30 29 2-Pole
Prescalar In ladapt Loop Filter
20 31
Crystal 1
14
Crystal 2 AUX3 Steering line
Reference
15 TRB 5
Oscillator Voltage
cp bias 1 1
27 Controlled
Filtered 5V Oscillator
26 18
cp bias 2 (U251)
32
VCP 10 9 16 23 4 2
Rx injection
Voltage V-mult 1 Warp
Multiplier V-mult 2 Tx injection
For achieving fast locking of the synthesizer, an internal adapt charge pump provides higher current
capability at pin 31 than when in the normal steady-state mode. Both the normal and adapt charge
pumps receive their supply from the voltage multiplier which is made up of C202, C203, C204,
C231, CR201, and CR202. By combining two 5 Volt square waves which are 180 out-of-phase along
with Regulated 5 Volts, a supply of approximately 12.6 Volts is available at pin 32 for the charge
pumps. The current for the normal mode charge pumps is set by R203. The pre-scaler for the loop is
internal to U201 with the value determined by the frequency band of operation.
3.2 VCO
The VCO (U251) in conjunction with the Fractional-N synthesizer (U201) generates rf in both the
receive and the transmit modes of operation. The TRB line (U251 pin 5) determines which oscillator
and buffer will be enabled. A sample of the rf signal from the enabled oscillator is routed from U251
pin 23, through a low pass filter, to the pre-scaler input (U201 pin 20). After frequency comparison in
the synthesizer, a resultant CONTROL VOLTAGE is received at the VCO. This voltage is a DC
voltage between 3 and 10 volts when the PLL is locked on frequency.
Lo Rf
Injection Low 10,11 Rx
Pass 2 Rx Rx Tank
Filter Buffer Osc Control
Voltage
Tx Rf
Injection Low 4 Tx
Tx Tx 15,16
Pass Tank
Attenuator Filter Buffer Osc
Filter
Audio
Tx/Rx/BS 5 Tx VCO In
Prescalar Switching TRB Mod
Buffer Network
Low
Prescalar RF out Pass Pre-In (U201 pin 20)
Filter
In the receive mode, U251 pin 5 is grounded. This activates the receive VCO by enabling the receive
oscillator and the receive buffer of U251. The rf signal at U251 pin 2 is run through a low pass filter.
The rf signal after the low pass filter is the LO RF INJECTION and it is applied to the first mixer at
T2.
During the transmit condition, PTT depressed, five volts is applied to U251 pin 5. This activates the
transmit VCO by enabling the transmit oscillator and the transmit buffer of U251. The rf signal at
U251 pin 4 is run through a low pass filter and an attenuator to give the correct drive level to the
input of the PA module (U101 pin 1). This rf signal is the TX RF INJECTION. Also in transmit mode,
the audio signal to be frequency modulated onto the carrier is received by the transmit VCO
modulation circuitry at AUDIO IN.
When a high impedance is applied to U251 pin 5, the VCO is operating in BATTERY SAVER mode.
In this case, both the receive and transmit oscillators as well as the receive, transmit, and pre-scaler
buffer are turned off. In the Fractional-N, the battery saver mode places the A/D and the modulation
attenuator in the off state. This mode is used to reduce current drain on the radio.
4.0 Controller
The GP600 controller is an open architecture which consists of:
■ U709, Motorola 68HC11K1 microprocessor
■ U701, Audio Signalling Filter Integrated Circuit, ASFIC
■ U703, 1Kbyte EEPROM
■ U705, 128/256Kbyte OTP/FLASH ROM
■ U706, 8/32Kbyte Static RAM
■ U707, LCD Display Driver and
■ U704, 5V Voltage Regulator
U709, U703, U705, U706 and U707 are powered by U704. U701 is powered from a 5V Regulator
(U708) on Radio Module. In addition to the external memory devices, U709 has 768 bytes of RAM
and 640 bytes of EEPROM.
Reset
Rx. Filter
Σ
2.1 Vol
Micro- MHz & De-emp
28 Attn Rx.
processor
Pin Sq. Audio
Conn. Out LCD
Attn
In
Data, Address
7.9488 and Control
MHz Clk
Keypad
Lock EE-
Detect PROM
Low Batt.
Monitor ROM/ RAM
SPI Bus FLASH
Vol
Sense
LED
5V From
5V Reg. Batt.
Push Channel
Button Switch
Reset
4.1 Functions
The microprocessor has two basic functions: interfacing with the outside world and controlling the
internal workings of the radio. The microprocessor interfaces directly with the keypad, side buttons,
PTT, rotary switch, battery low indicator, EXT PTT and volume sense. The microprocessor
constantly monitors these inputs and interprets any changes into commands that control the rest of
the radio. Some control functions it performs include loading the synthesizer with the desired RF
frequency, turning the RF PA on or off, enabling and disabling audio and data paths and generating
tones. Operations and operating conditions within the radio are interpreted by the microprocessor
and fed back to the operator as visible (the display) or audible (alert tone) indications of current
status.
The regulated 5V output from U704 powers the microprocessor (U709) and the rest of the digital IC
except ASFIC (U701). The microprocessor’s clock is generated by the ASFIC, which has a built-in
programmable clock synthesizer.
Upon power-up and assuming that the ASFIC receives a proper 2.1MHz input on U701-P38 (which
comes from the transceiver board), the ASFIC outputs a 7.9488MHz CMOS square wave (0-5Vpp
logic) on U701-P30, which connects to the EXTAL input of the microprocessor, U709-P73. The
microprocessor operates at 1/4 of this frequency, which in this case computes to 1.9872MHz. In
particular, the E clock output (U709-P72) will be a 50% duty cycle square wave at this frequency.
The microprocessor operates in expanded memory mode and executes firmware contained in OTP/
FLASH ROM, U705. The microprocessor uses a non-multiplexed address data bus, consisting data
lines D0 through D7 and address lines A0-A17. In addition, the microprocessor has integrated chip-
select logic so that external memories can be accessed without the need for external address
decoder gates. These chip-select signals are provided by U709-P28 and P29.
When the controller board is functioning normally, microprocessor’s address and data lines should
be toggling at CMOS logic levels. Specifically, the logic-high levels should be between 4.8 and 5.0V,
and the logic-low levels should be between 0 and 0.2V.
4.5 RAM
The on-chip 768 byte static RAM from U709 provides some scratch-pad memory, with the bulk of it
coming from the external 8 or 32Kbyte SRAM, U706. External SRAM accesses are indicated by the
U709-P28. Normally SRAM is accessed less often than the OTP/FLASH ROM, U705; i.e. the
number of transitions per second on U705 chip select (pin 30) should be 5-15 times higher than
those on U706 pin 20.
4.6 EEPROM
The radio codeplug storage is provided by U709 internal 640 byte EEPROM, with an additional 1K
byte of memory space provided by external EEPROM, U703. There are three basic types of
codeplug information: information on the trunked system on which the radio is authorized to operate;
information on the conventional system, which is either of the repeater or talk-around type on which
the radio is authorized to operate, and information on the configuration and tuning of the radio itself.
Tuning information is normally located in the internal EEPROM of U709.
The microprocessor communicates to several ICs and modules through a dedicated on-chip serial-
peripheral-interface (SPI) port which consists of transmit data line MOSI (U709-P1), receive data
line MISO (U709-P80), and clock line SCK (U709-P2). In addition, each IC that can be accessed by
the microprocessor using the SPI has a read/write select line associated with it. The ICs or circuits
and their associated select lines are:
■ EEPROM (U703) with select line U709-P3
■ ASFIC (U701) with select line U709-P34
■ LCD Driver (U707) with select line U709-P23
■ SRAM (U706) and OTP/FLASH ROM (U705) with select line U709-P33
■ Transceiver board Synthesizer (U201) with select line U709-P35
■ Transceiver board DAC IC (U152) with select line U709-P26
The LCD Driver uses the master out/slave in (MOSI) line to send data to the display driver IC, and
the master in/slave out (MISO) line to send data back to the microprocessor (U709). Note, however,
that the keypad (or any other SPI device) can never initiate display data; the microprocessor is at all
times the SPI master device. Thus the MOSI line and MISO line are always in the master
configuration.
The bi-colour LED on the top of the radio is indirectly activated by SPI of U709 via the DAC IC
(U152) on Transceiver Board. When either input to the dual NPN transistor (U410) is at logic high,
the corresponding output pin (pin 6 for the green LED, pin 3 for the red) should be at approximately
4.3 Vdc. Note that it is possible to have both LED outputs on simultaneously, in which case the LED
emits a yellow/orange light.
The transmit and receive audio paths are disabled in the standby mode and selectively enabled by
the microprocessor when the radio transmits or receives a signal. Also, there are minor differences
in the functioning of both paths depending on whether an internal or external (accessory)
microphone/speaker is being used. The radio constantly monitors the received data path for control-
channel data in trunking operation or sub-audible data in conventional operation.
On connecting an external MIC through connector J3, external PTT sense transistor Q408 switches
“ON” when the external PTT switch is closed. Q408 collector voltage is monitored by U709-P4.
When collector voltage is logic “HIGH”, the microprocessor configures the radio for transmit mode.
In PTT equipped accessories, the PTT switch is series connected with the external MIC element.
MIC audio from internal MIC MK401 is coupled through C429, L404, J3 and L403 to the MIC buffer
circuit U405-1. External MIC plug insertion mechanically disconnects the internal MIC. External MIC
audio is coupled through L403 to the MIC buffer input. The unity gain buffer will route the MIC audio
into MIC IN (U701-P7) through flex and connectors J200 and J700. Inside the ASFIC, the MIC audio
is amplified, filtered to eliminate components outside the 300-3000Hz voice band, pre-emphasized,
and then limited. The limited MIC audio is then routed through a summer, which is used to add in PL
or DPL sub-audio band modulation, and then to a splatter filter to eliminate high frequency spectral
components generated by the limiter. After the splatter filter, the audio is routed to the 8 bit
modulation attenuators, which are tuned in the factory of the field to set the proper amount of FM
deviation. The TX audio emerges from the ASFIC at U701-P55 is dc coupled and applied through
flex and connectors J700 and J200 to the synthesizer (U201) pin 8.
There are four major types of transmit data: sub-audible data (PL/DPL/Connect Tone) that gets
summed with voice, high speed data for trunking control channel communication, DTMF data for
telephone communication in trunked and conventional systems, and MDC data for use in Motorola
proprietary MDC systems. The deviation levels of the latter three types are tuned by a 5-bit digital
attenuation inside the ASFIC. For each data type and each band split, there is a distinct set of tuning
values that are programmed into the ASFIC before the data is generated and transmitted.
Sub-audible data is composed of low-frequency PL and DPL waveforms for conventional operation
and connect tones for trunked voice channel operation. (The trunking connect tone is simply a PL
sine wave at a higher deviation level than PL in a conventional system). Although it is referred to as
“sub-audible data”, the actual frequency spectrum of these waveforms may be as high as 250Hz,
which is audible to the human ear. However, the radio receiver filters out any audio below 300Hz, so
these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U701 at any one time. The process is as
follows: using the SPI, the microprocessor programs the ASFIC (U701) to set up the proper low-
speed data deviation and select the PL or DPL filters. The microprocessor then generates a square
wave from U705-P6 which strobes the ASFIC PL_CLK (U701-P20). For encode input at twelve
times the desired data rate. (For example, for a PL frequency of 103Hz, the frequency of the square
wave at U701-P20 would be a1236Hz). This derives a tone generator inside U701, which generates
a staircase approximation to a PL sine wave or DPL data pattern. This internal waveform is then low-
pass filtered and summed with voice or data. The resulting summed waveform then appears on
U701-P55 (VCO_ATN), where it is sent to the transceiver board as previously described for transmit
audio.
High-speed data refers to the 3600 baud data waveforms (ISWS AND OSWS) used in a trunking
system for high-speed communication between the radio and the central controller. To generate an
ISW, the microprocessor (U709) first programs the ASFIC (U701) to the proper filter and gain
settings. It then begins strobing U701-P54 (Trunking Clock In) with a square wave (from U709-P5) at
the same baud rate as the data. The output waveform from 5-3-2 State Encoder of U701 is then fed
to the post-limiter summer block and then the splatter filter. From that point it is routed through the
mode attenuator and then out of the ASFIC to the transceiver board via VCO_ATN (U701-P55).
DTMF data is a dual-tone waveform used during phone interconnect operation. They are divided into
low-group and high-group tones. The high-group tone is generated by U709-P5 strobing U701-P54
at six times the tone frequency for tones less than 1440Hz, or twice the frequency for tones greater
than 1440Hz. The low-group tone is generated by U709-P7 strobing U701-P53 (DTMF Clock) at six
times the tone frequency. Inside U701 the low-group and high-group tones are summed (with the
amplitude of the high-group tone being approximately 2dB greater than that of the low-group tone)
and then pre-emphasized before being routed to the summer and splatter filter. The DTMF
waveform then follows the same path as was described for high speed data.
The MDC signal follows exactly the same path as the DTMF high-group tone. MDC data utilizes
MSK modulation, in which a logic zero is represented by one cycle of a 1200Hz sine wave, and a
logic one is 1.5 cycles of an 1800Hz sine wave. To generate the data, the microprocessor (U709)
first programs the ASFIC (U701) to the proper filter and gain settings. It then begins strobing U701-
P54 with a square wave (from U709-P5) at the same baud rate as the data. The output waveform
from U701 is fed to the post-limiter summer block and then the splatter filter. From that point it is
routed through the mode attenuator and then out of ASFIC to the transceiver board via VCO_ATN
(U701-P55).
The radio’s RF circuit are constantly producing an output at the Detected Audio line. Whenever the
radio is in trunked standby mode, it is processing data from the control channel; while in
conventional standby mode, it is always monitoring the squelch line and/or sub-audible data. The
detected audio from the transceiver board enters the controller board at connector J700 pin 4. In
addition to the detected audio line, the transceiver board also provides a squelch noise from U51-
P30 into the ASFIC squelch-detect circuitry via U701-P56. When the microprocessor is satisfied that
it has received the proper data or signal type for unsquelching, it sets up the receive audio path and
sends data to U701 to do the same within.
The detected audio will enter U701 through RX IN (pin 57) and PL IN (pin 63) for further processing.
Inside the IC, the signal first passes through a low-pass filter to remove any frequency components
above 3000Hz and then a high-pass filter to strip off any sub-audible data below 300Hz. Next, the
recovered audio passes through a de-emphasis filter to reduce the effects of FM noise. Finally, the
IC amplifies the audio and passes it through the 8-bit programmable attenuator whose level is set
depending on the value of the volume control. The microprocessor (U709) programs the value of the
8-bit attenuator in accordance with the voltage sensed at the volume potentiometer, which is
connected to U709-P48. This pin is one of the eight channels of U709’s 8 bit A/D convertor. After
passing through the 8-bit digital attenuator, the audio goes to a buffer amplifier and then exits at
U701-P66, where it is routed to the Audio power amplifier circuit in the transceiver board.
Resistor R466 sets the input impedance to U409-P2 of the audio power amp. The audio PA circuit is
a bridged-tied-load (BTL) configuration with fixed gain of 40dB, developing 500mW (rated audio
power) output at less than 5% harmonic distortion into the 16 ohm internal speaker LS401 with
nominal 7.5Vdc battery supply. Maximum audio power output is greater than 1.2 watts.
PNP transistor Q410, the audio PA power switch, driven by NPN darlington transistor Q411, the PA
mute amp, controls Vcc supply to Audio PA U409-P1. U701-P5 is connected to Q411 base,
controlling audio PA Vcc supply. Resistors R489 and R490, PNP transistor Q412 and the current
sense circuit monitor current supplied to audio PA U409-P1. Worst case audio PA current (at 9Vdc
battery voltage, maximum volume and full system deviation) does not exceed 450mA at the nominal
16 ohm load. Resistor R488 and capacitor C461 provide an RC time delay for U405-2, a monostable
multivibrator circuit. A 2.5Vdc reference voltage is fed to U405-2-P6. On radio power-up, and in
normal operation U405-P7 monostable multivibrator output is logic “LO” pulling Q411 emitter to Vee
with the audio PA controlled by U701-P5. Should U409-P5 and/or U409-P8 become shorted to each
other or to the ground (Vee), current consumption exceeds 500 mA (approximately) and Q412
collector. When U405-2-P5 voltage rises higher than the U405-2-P6 reference voltage (rise time is
less than 50 usec), U405-2 is triggered and U405-2-P7 dc output voltage is switched to 4Vdc,
effectively biasing Q411 into cut-off and turning off the audio PA power switch Q410. U405-2-P7
remains in this state for 15 msec, then reset to logic “LO” state. Average power dissipation in the
audio PA circuit components is helped to a low level by the low duty cycle (less than 0.3%) of the
audio PA protection circuit. The cycle repeats until the audio PA output short is removed.
The ASFIC (U701) decodes all receive data, which includes PL, DPL, low-speed trunking, MDC,
and high-speed trunking data. The “decode” process for each data type typically involves low pass
or band pass filtering, signal amplification, and then routing the signal to a comparator, which
outputs a logic zero or one signal. The detected audio from the transceiver board is routed to U701-
P57 and P63 through coupling cap C435. Inside U701, the data is filtered according to the data type
(HS data or LS data, then hard-limited to a 0-5V digital level. The high-speed limited data output
(MDC and trunking high-speed) appears at U701-P51, where it connects to U709-P11. The low
speed limited data output (PL, DPL and trunking low-speed) appears at U701-P4, where it connects
to U709-P10.
When the microprocessor needs to give the operator feedback (for a good key press or for a bad key
press) or radio status (trunked system busy, low battery condition, phone call, circuit failures), it
sends an alert tone to the speaker. It does so by sending data to U701, which sets up the audio path
to the speaker for alert tones. The alert tone itself can be generated in one of two ways: internally by
the ASFIC, or externally using the microprocessor and the ASFIC. The allowable internal alert tones
are 300, 900 and 1800Hz. For external alert tones, the microprocessor can generate any tone within
the 100-3000Hz audio band. This is accomplished by the microprocessor toggling the output line
U709-P7, which is also the same line used to generate low-group DTMF data. Inside the ASFIC, this
signal is routed to the external input of the alert tone generator. The output of the generator is
summed into the audio chain just after the RX audio de-emphasis block. The tone is then amplified
and filtered before passing through the 8-bit digital volume attenuator. The tone exits at U701-P66,
then is routed to the audio PA circuitry in the transceiver board.
Chapter 6A.4
PCB/Schematic Diagrams and Parts Lists
Table of Contents
Description Page
UHF (403-433MHz) Diagrams and Parts Lists
Controller PCB Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Controller Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
RF PCB Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RF Overall Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RF (Receiver Module) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RF (Synthesizer) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RF (Transmitter Module) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RX-FE Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DS702 DS701
DS704 DS703
J701 1
34
32 17
15 14 33 16
R799
C721
R781 C745
S01 S02 S03 S04
U706 U707
R755 C787 C746
R700 C700
VR707
48 1
49 64 TP7
C754
R790
C781
R711
R713
C744
CR707 S13 S14 S15 S16
Q704 R710
28 1
C719
C758
R787
Q703 16 Q700
Q705 17 C720
4 R763 C777 C786
5 U705
C718
R712
R753
U703
C716
C717
8 1 TP4 32 1
C711
R726
1 60 6 4
J7 A7
U704
1 3 R786
U701
C763
C406 C765
R725
R764
U709
TP2 J2 A2 S05 S06 S11 S12
H1 B1
R754
TP1
R756
C738
C761
C707
R751
C737 C708
C731
C743
20 41 C769
21 C733 R705 C710
40
28
C741
C732
2
C435
C747
C742
R468
Q702
R752
J700
1 27
Controller Board
PCB No. 8404599J03
Controller Board-
8404599J03
Diode, Transistor:
Integrated Circuit:
SH104
3 4 3 4 5
L253 4 R256 R262 C33
L53
C226
C212
C227
L11
C233 Y51B
L204
Y201T 5 4 CF51 CF52
R252
C282
2 3 Q251 C283 6 3
T2
C56
C78
C30
C28 L55
CR203
R255 2 2
L203
R4602
C455
C258
C224 C272
L255
R253
Y51A
C268 2 3
L9
C58
R54
L268
C205 C232
5
L260
C59
C29
R254 5 30
C217 C279 C267 U51
C206
R207
8 5 R55
CR255 C55
C281 CR2
L262
C219
L201
C257 C278 R258 C266 4 L52
R205
C209
C73
C75
J6
C215
C259
L259
L258 4 3 2 R51 12 23
C79
L261
Y53
C265
SH105
C204
C74
R64
2 3 T1
L51
L58 C68
2
SH103
C269
C271
C51
C63
C270 C69 C67
4 5 C66 R57
SW401
C
C
R106
U252
R105
4
8
C117
R104
C418
R447 8 5 6 5 4 3 2
C419
CL5
C498
C116
U708
C425
L111
4
Q408
C421
J1
C424
R448
R452 C452 R169
R503 U101
R451 2
3
C464
4 4 L403 R170
C800 J2
C461
L710
U405 4
R173
U409
L404
C123
3
5 8
7
R702
C499
R488
C429
5 8 C124
L113
C409
C430 C102 C107
PB403 PB401 PB402 RF Board
CL4 CL3 CL2
Component Side
VR704
L54
R802
R803
R801
R804
C57
C454
CR405
C275 C789
C228
C208
C210 C273
R212
C207
C211
C456 R60
CR251
SH101
JU51
C70
L252 R251 C54
R263
R52
C62
R211
R411
R409
C457
C223 L717
R415
C77 R53
C82
R204
R408
C284
C472 L251
17
L254
R202 R203
21
22
17 24
16
R68
R497
R215 R206 16 25 C53 C71
C61
R414
C60
Q51
R67
C34
C235
R424 R261
L10
C13
R417 C202 U201 U251 C474
C83
C473 C256
C466 R260
4
2
CR201 C85 C87
10
C467 98 32 C216 L267 R66 DS401
C237
4
C468 R5
C263
C64
L256
R416
R58
C86
3
4
3
U410
C222 R201
C203
R413
C238 C261
Q405
R264
R412
C80
C262
6
C201 R257
C220
C221
CR253
L257
C260
C264
C436 C475
C276
SH100
VR401
CR202 C214 C285 C280
C459
C81
R162 C37
LOCKDET C231 C218 C229
C36
Q153
C156
C165 C157 C460
C410
R438
C158
R193
C443
SYNLE
C193
R167 SL R158
R216 C230
R6
C194
L406
5 8
J200
22 4
R160
U151A 2 C119 R102
C151
Q151
C154
21 5
C480
R450
R449
C426
4 R166 R161
C118
SRCLOCK C120 CR102 L405 3
C437
C105
C438 Q410 C121 2
R469
R154
C115
R155
Q152
L104
R101 L112
R507
J3
L106
R172
C481 R171
C428
C479 R466
C442 R153
C113
Q156
CR101
R156
Q411
L102
CL9
R467
C441
L108
6
C122
L107 C114
R152 C164
RF Board
SH102
J5
C110
C104
C108
C106
C109
C162
1 2 3 4 L103
Solder Side
RF Board
PCB No. 8404732J01
BATTERY
GRAPHICS ONLY
0180702489 BATT FILTER BOARD
* CONNECTION VIA CHASSIS
R497 SCI SCI
470 refer to R460 C3
SW402-1 CONN_BPLUS
39
L710 SW_ONOFF
5V SWB+ TXB+ EN_BIAS 5V SWB+ 5R THERMAL FUSE
F1
390nH P/O VOL
U708 C421 L1 L2 4A
.47uf CHG+
8 VIN VOUT
1 CR405 C1 C2 C4
6 5V_TAP SENSE 2 NU 39 39
7 FEEDBACK GND 4
C419 5 ERROR SHUTDOWN 3 SWB+
.018uf
(SOURCE) CHG-
5V SWB+ TXB+ 5V SWB+ 5R
C418 J200
10uf (SOURCE) CONN_89982-28
EN_BIAS SQATTNIN 5V 1 SWB+
2 GND
DETAUDIO 3 SQATTNIN
TRANSMITTER RX_IN RX_IN RECEIVER 4 DETAUDIO
RSSI 5 RSSI
CHAIN CHAIN 6 ADAPT
RX_INJ
ADAPT 7 LOCKDET
8 SYNLE
9 MODIN
CLK RESET DACLE TX_INJ 10 SB1
11 SB2
5V 12 ROT1
13 ROT2
(SOURCE FROM ASFIC) 14 2.5V
15 5V
16 MICIN
17 SRDATA
RX_INJ 5V 18 RXAUDIO
LOCKDET 19 GCB1
C497 20 VOL
CLK RESET DACLE SYNLE NU R447 21 PTT
22 EXTPTTSENSE
MODIN SB1 SB2 2.5V 5V 5V 23 SCI
NU C425 24 SRCLOCK
TX_INJ VOLUME
C424 NU 25 DACLE
DATA SRDATA PORT
SYNTHESIZER L717 26 RESET
VOL SENSE 27 GND
CLK SRCLK NU R460-2 XX .39uH 28 2.1MHZ
C480
NU XX
R448 R450 C789 VR704
2.1 MHZ 2.1 MHZ SW_ 100pf 6.8V
0 ONOFF XX
NU PTT DATA CLK DACLE RESET 2.1MHZ
U405-1
OPAMP_4PIN N2 C802
N1 C426 C427 NU
1 2
.22uf .22uf L403
R507 R489 R490 3 J3
SWB+
1000 2.7 2.7 N3 390nH EXT_MIC-SPKR
1/8W 1/8W N4 4 MMBT3906 R451 S22
C428 2200 C481
2 R449 150pf 3 Q408 150pf
SWB+ R494 S33
Q412 100K EXT MIC
2 100K
MMBT3906 1 MIC FILTER 1 S11
C438
C461 1
3 4.7uf 2.5V C410 VR401 J5 CONN_4PIN
3 2 R452 150pf C409 C436
.1uf C464 150pf 10V 150pf 1
3 R503 180K MK401
R488 5V
220K 8 N4
Q410 1 Q411 2 INT MIC
N3 5 .1uf MMBTA13 330 C452
M41L03 C498 L404
7 2 4.7uf
6 150pf 390nH
N1
SHIELDS AND BUTTERFLY CLIPS N2 R496
2.5V
U405-2 330
C429
LS401
4700pf 3
OPAMP_4PIN L405 R702
390nH 2000 4 INT SPKR
1 1 1 1 1 1 1 1 1 EN_BIAS 16 ohm
AUDIO AMPLIFIER C499 C430 C442
CL CL CL CL CL CL CL CL CL R467 J4
U409 150pf 150pf 1000pf EXT_MIC-SPKR
10 S22
CL11 CL9 CL8 CL7 CL6 CL5 CL4 CL3 CL2 TDA7052
R469 1 Vp 5 C441 S33
OUTPUT1
.1uf EXT SPKR
C437 1800 L406
2 8 S11
INPUT OUTPUT2
GND0
GND1
R466 390nH
NC0
NC1
.47uf C443
SH101 SH100 SH103 SH104 SH105 C469 4700 1000pf
47pf C479
SH1 SH1 SH1 SH1 SH1 470pf 3 6 4 7
NC NC
1 1 1 1 1
5V ROT1
C801 ROT2
SW401 NU R801 R802 R803 R804 R409 43K
SW_FREQ_16POS 10K 10K 10K 10K
SB1 SB2 PTT 8 R408 20K
PC3
PC2 4
C466 C467 C468 PC1 2 R411 43K
1
C0
C1
PC0
150pf 150pf 150pf R410 20K
C460 C475 C459 C474 C456 C454 C457 C455
150pf 150pf 150pf 150pf .01uf .01uf .01uf .01uf
R424 R416 R417
100 100 100 R414 R415
C476 C473 C472 510K 510K
150pf 150pf 150pf
SCHEMATIC DIAGRAM OF OVERALL CIRCUIT
SW_TACTILE
SW_TACTILE
RF Schematic Diagram
1
2
3
4
5
6
R6 T1 33nH 18nH .15uH C51 2
4 3
CR2-2 5R
RX_IN 22 VOLT
C36 XFMR 2 C33 C28 C29 82pf
6.2pf 7,8
C119 5 7 1.5pf 24pf 9.1pf
6.2pf 5 1
4
3,4
RX_INJ
4F(N) 6F(N)
4D(W) 4E(W)
C55 R55 CF51 CF52
5R 455kHz FILTER 455kHz FILTER_6POLE
.1uf 100 1 3 1 5
R54
2.5VDC
2.5VDC
2000
R52
33K C61
2
3.8VDC
C82 2 3 4
R67 JU51 1500pf
2.9VDC NU CR51 INSTPAR
4 3 36 35 33 32 INSTPAR
.1uf 6800
FIL_CAP_OUT
IF_AMP_OUT
2ND_IF_OUT
IF_AMP_IN
FIL_CAP_IN
LIM_IN
C56
3 JUMPER
20pf Y51B C78
C59
C54 INSTPAR 0.75VDC 6 PPC_AMP_IN
0.7VDC 1 Q51
1 3 0
NPN C57 L54 L55 C58 .1uf 1.5VDC 5
15pf NU NU 1.5uH NU DEMOD_OUT 31
R53 PPC_AMP_OUT
12K 2 45.1MHZ 2.0VDC
MMBR941 2
C60 .47uf
.1uf C62
8 IF_IN
3.0VDC AUDIO_IN 29 2.4VDC
1
GND
13 A+_B+ 28 2.5VDC
DETAUDIO
14 DRIVE AUDIO_OUT
SWB+
C75 4.4VDC 7 LO_IN U51 23 2.4VDC
C80
NU
3.9pf SQ_LIM_OUT
C73
2.6VDC 10 IFIC C63
OSC_OUT
20 2.4VDC
2 SQ_ATTEN_IN
Y53 13pf C74 R64 3.4VDC 9
R66 OSC_FB 51pf
820 45MHz 36pf 5600
27 22
5R T_R ADAPT ADAPT
44.645 1
2 5.0VDC(UNSQ)
VCC1 0VDC(SQ)
15 C87
C79 SQ_OUT 5.0VDC(UNSQ)
12 150pf
16pf VCC2 0VDC(SQ)
2.4VDC
17 18
5V VCC3 FAST_SQ
L58
INSTPAR 34
C71 C70 VCC4
PCC_2_SU
R68
RSSI_OUT
SQ_TAIL
30
10uf .1uf SQ_NOISE SQATTNIN
FILTER
SQ_IN
C81
3.7VDC 25 1000
ICO
RSSI_OUT_2
C83 C85 C86 R60
.1uf 16 19 11 26 24 150pf 150pf 150pf 130K
3-5VDC
3-5VDC RSSI
0.5-3.0VDC
0.65VDC
SCHEMATIC DIAGRAM OF RECEIVER CHAIN
PMLE4022A UHF1 (403 433MHZ) 12 5KHZ RF BOARD
RF (Receiver Module) Schematic Diagram
R256
RX_INJ
1500 C283
C282 3
470pf 150pf
1 Q251
NPN R262
MMBR941 390
2
R252
C260
4.3pf
R255 10K
11K
C272 C261
6.2pf R257 C280 3.9pf C231
C263 CR253 .01uf C237
C285 R264 C238 100pf 5V
R258 39K 3.3pf 100pf
C267 100 150pf R260 L256 150pf 100 C202
220 470nH C262 C264 L286
C204 5.0VDC (LOCKED)
150pf C268 C266 .01uf NU 0VDC (UNLOCKED)
FILT5V
1000pf 150pf L257 C278 9.1pf 9.1pf
470nH 4.7uf CR202 CR201
L259 .22uf L267 C203 C286
L255 L258 82nH C222
390nH 6 3 7 8 9 .01uf NU C228 C219 LOCKD
L262 390nH 34.4nH
L260 150pf 150pf
VCC
NC1
NC2
E1B
E1A
LA1
V_MULT_1
V_MULT_2
8.2nH
LOCK
VCP
CEX
150pf C265 5600pf 3-10VDC 29 I_OUT
22 NC4 .1uf
C271 C270
NU VCOBIC VC 13 C253 L254 SL 31 I_ADAPT 8 2.5VDC
NU 22pf C255 82nH R201 C201 MOD_IN MODIN
R261 82 NU T1 R206 R215
24 NC5 2.5VDC
BI2 14 1
4 GND FREQ_OUT
11
2.1MHZ
220 C284 11pf
CR251 C214 3-10VDC 13 GND 12 2200 1000 R216
1pf L253 DC_5V_REF_OSC 5V
1 GND2 B2 15 C279 1uf U201 24K C218
GND1
TRB
NC3
E2B
E2A
C254 XTAL_1
LA2
FRACTN-32 33pf
PS
DC_5V_REF_DIV
C275 WARP
DC_5V_PRESC
C252
L252 390nH C257 C258 20 PRE_IN 17 4.65VDC C206 R207 C232 2
SUP_F_OUT
6.8pf R253 R211
DC_5V_SRL
C235 Y201T
SUP_CAP
2200 NU
SRL_DATA
390nH CR255 47pf
CP_BIAS1
CP_BIAS2
SUP_F_IN
150pf NU
SRL_CLK
150pf R263 1800 .018uf 47K 16.8MHz
TEST_1
TEST_2
39K C207 1
C281 0.7VDC(R) 4.7uf C233
GND
1.5VDC
R251 C251
150pf 8.2pf 4.2VDC(T)
30K FILT5V
6 5 27 26 18 21 19 23 3 22 24 25 6.8pf
C209 NC NC CR203
FILT5V 150pf
C273 C224
150pf 150pf
L204
C211 .22uf
33nH
C227 C226 4.7uf C229
C276 NU R212 R203 R204
.01uf NU NU 220K 100K
L203
390nH 4.65VDC
(SOURCE)
FILT5V C210 C212 C236
4.7uf 1000pf 150pf
C208
C220 C221
4.7uf 150pf 150pf
SCHEMATIC DIAGRAM OF SYNTHESIZER
5V
DATA PMLE4022A UHF1 (403-433MHZ) 12.5KHZ RF BOARD
GEPD5555
C120 CR102
RX_IN
150pf C109 TXB+
C118 R102
150pf 330
NU
R101
10uf
3
SWB+ C158 150pf C168
Q154 .01uf 0.1 R174
TO U51-PIN 13,14 C101 1W C122 C124 C162 R151 NU
M41L03 R153 Q155
4.7uf NU 20pf 150pf 56.2K 1
Q405 2 22 100K NPN
2 3 1%
SWB+ MMBT3906
R175 MMBT3904
R438 SENSE HI 6200
R161 2
680 1 3300
1 R155 SENSE LO
5R 3 1
3 VDD 56.2K
SOURCE 1%
U152 R154 R152
SWB+ Q153 1 22
CLK DAC DAC2 11 100K 100K
4.52VDC(HI)
MMBT3904 24 9 1% 1%
RESET DAC1 2.00VDC(LO)
NPN C199 21 3
150pf EN BIAS_EN
2 C156 16 2
150pf TEMP ANT_SEL
14 8 R171 C153
U410 BATT 2_POLE_V 51K
15 12 C152 C163 C151 .1uf R166
AUX FREQ_SW_DA 180
1 4 NPN_DUAL R162 10
R_T
120 23 17
4
DATA_IN SCB1
18 150pf 150pf 150pf
Q152
5 2 R157
FREQ_SW0 SCB2 MJD2955
5 19 1800
FREQ_SW1 SCB3
6 20 N3 N2 R167 3 2
FREQ_SW2 SCB4 R172 U151A-1 SWB+
6 3 7 22K 3 2 16K
FREQ_SW3 OPAMP_4PIN
4 R160 TO U51-PIN 13,14
VSS N4 680
C193
13 1
R412 R413 3 1.65VDC(HI)
180 680 1 NU C165
N1 0.75VDC(LO)
Q156 U151A-2 .01uf
1 OPAMP_4PIN 3
NPN R193
DS401 DATA N2 Q151
3 1 MMBT3904 6 N1 1
NU NPN R158
2 N3 7
R179 R156 2.31VDC(HI) MMBT3904
5
8N4 180
3900 C800 R168 1.40VDC(LO)
360 R173 R170 2
C159 4.7uf 100K C154
150pf C166 R159
4 2 CLK RESET DACLE NU
LED_DUAL .47uf NU
2.91VDC(HI) 180
R169 C157 150pf
1.11VDC(LO)
10K
.01uf
5V
EN_BIAS
GEPD5557
RF (Transmitter Module) Schematic Diagram
C214 2311049A07 1.0 uF, 10%; 16V C265 2160521G37 0.1 uF, +80%/-20%; 25V
C279 2311049A03 0.33 uF, 10%; 25V C461 2160521G37 0.1 uF, +80%/-20%; 25V
C434 2160521G37 0.1 uF, +80%/-20%; 25V CF51 9180453B04 mini ceramic filter -6 pole
C452 2311049J11 4.7 uF, 10%; 16V CR051 4880154K03 dual Schottky mixer
CR405 4880107R01 silicon rectifier L111 2483035N13 coil air 24AWG 5TNS
DS401 4805729G49 diode red/yel L201 2462587N22 chip 390 nH, 10%
H101 300136783 screw 2-56" X 5/16" 2 off L204 2462587N47 chip 33 nH, 5%
H102 1405160A02 insulator, crystal L251 2461587N22 chip 390 nH, 10%
H103 0780511B01 bracket, freq switch, L252 2461587N22 chip 390 nH, 10%
plated
L253 2480145S07 RF coil 1-1/2T brass core
Connector, Receptacle:
L254 2462587N52 chip 82 nH, 5%
J1 3980515C02 antenna contact
L255 2462587N22 chip 390 nH, 10%
J2 0180117S05 RF jack assembly
L256 2462587N61 chip 470 nH, 5%
J3 0180417C01 assembly option jack
L257 2462587N61 chip 470 nH, 5%
J5 0180195R03 speaker microphone
header L258 2480145S08 2-1/2 violet toko
L011 2462587N47 chip 33 nH, 5% L268 2462587N22 chip 390 nH, 10%
L051 2483411T63 chip shielded L403 2462587N22 chip 390 nH, 10%
L052 2462587N61 chip 470 nH, 5% L404 2462587N22 chip 390 nH, 10%
L053 2462587N69 chip 1200 nH, 5% L405 2461587N22 chip 390 nH, 10%
Switch:
Integrated Circuit:
U051 5180207R01 IF
Zener Diode:
Crystal:
TP3
T1
1
150pf
C27 C28
3.9pf S5 150pf
GEPD5558
C12 2113740G36 20
C13 2113740G31 12
C20 2113740G36 20
C23 2113740G32 13
C25 2113740G30 11
C26 2113740G30 11
Chapter 6B
146-174MHz Specific Information
Table of Contents
Chapter
6B.1 Model Chart and Test Specifications
Chapter 6B.1
Model Chart and Test Specifications
Table of Contents
Paragraph Page
1.0 Overview......................................................................................................1
1.0 Overview
6B.1
This chapter lists the VHF models and technical specifications for the GP600 portable radio.
GP600
Description
VHF
146 - 174 MHz
X = Indicates one of each required
AZP93VJB05N2_E
AZP93VJA05N2_E
Model
Item Description
X X PMLD4049_ RF Board, 12.5 kHz, (146-174 MHz)
X PMLN4086_ GP600 Front Cover Display Kit
X PMLN4087_ GP600 Front Cover Non-Display Kit
X X HLN9667_ Chassis Hardware Assembly
X X NAD6502_ Antenna (146-174 MHz)
X X HNN9628_ Battery
X X 6802908X01_ GP600 User Guide
12.5kHz 20/25kHz
Sensitivity*
12dB SINAD (emf) µV 0.35µV 0.35µV
20dB SINAD (emf) µV 0.5µV 0.5µV Note: Self Quieting Frequencies
Audio Output Power
Self-quieting frequencies are frequencies
<5% distortion @1kHz 500 mW 500 mW
that are also generated by the radio and
with rated audio output
cause internal interference. On these
Spurious / Image 70 dB 70 dB frequencies the interference caused by the
Rejection self-quieter spur is great enough that a
radio will not meet its receiver sensitivity
Selectivity 60 dB 60 dB
specification.
Intermodulation 65 dB 65 dB
The frequencies are:
Switching Bandwidth 28 MHz 151.2, and 168.0MHz
No degradation ....... ..... .
Chapter 6B.2
Radio Tuning Procedure
Table of Contents
Paragraph Page
1.0 GP600 Radio Tuning .................................................................................. 1
1.1 General ........................................................................................................ 1
1.2 Transmitter Power ....................................................................................... 2
1.3 Reference Oscillator .................................................................................... 3
1.4 Rated Volume .............................................................................................. 3
1.5 Squelch Attenuation..................................................................................... 4
1.6 Transmit Deviation Balance (Compensation) .............................................. 4
1.7 Transmit Deviation Limit .............................................................................. 5
1.8 RSSI ............................................................................................................ 5
1.9 MPT1327 Transmit Deviation / DTMF Transmit Deviation .......................... 6
1.1 General
The recommended hardware platform is a 386 or 486 DX 33 PC (personal computer) with 8 Mbytes
RAM, MsDOS 3.3, Windows 3.1 or later, and DPS (Dealer Programming Software). These are
required to align the radio. Refer to the DPS Installation Manual (section 2 of the Product Manual) for
installation and setup procedures for the required software; the user manual is accessed (and can
be printed if required) via the DPS.
To perform the alignment procedures, the radio must be connected to the PC, RIB (Radio Interface
Box), and Universal Test Set as shown in figure 2-1.
SERVICE MONITOR
30 dB PAD OR COUNTER
TRANSMIT
30 dB PAD WATTMETER
BNC
RF GENERATOR
SMA-BNC RECEIVE
58-80348B33
AUDIO IN TX
BATTERY TEST SET AUDIO GENERATOR
ELIMINATOR RTX-4005B
RLN-1014A RX
SINAD METER
RADIO TEST CABLE
RKN4034
AC VOLTMETER
PROGRAM/TEST CABLE
HKN9857
COMPUTER
RIB DATA
HLN9214 BUSY
GND
Before going into the Service menu, the radio must first be read using the File / Read Radio menu (if
the radio has just been programmed with data loaded from disk or from a newly created codeplug,
then it must still be read so that the DPS will have the radio’s actual tuning values).
All Service windows read and program the radio codeplug directly; you do NOT have to use the DPS
Read Radio / Write Radio functions to program new tuning values.
CAUTION: DO NOT switch radios in the middle of any Service procedure. Always use
the Program or Cancel key to close the tuning window before disconnect-
ing the radio. Improper exits from the Service window may leave the radio
in an improperly configured state and result in seriously degraded radio or
system performance.
The Service windows introduce the concept of the “Softpot”, an analog SOFTware controlled
POTentiometer used for adjusting all transceiver alignment controls. A softpot can be selected by
clicking with the mouse at the value or the slider or by hitting the TAB key until the value or the slider
is highlighted.
Each Service window provides the capability to increase or decrease the ‘softpot’ value with the
mouse, the arrow keys or by entering a value with the keyboard. The window displays the minimum,
maximum, and step value of the softpot. In addition transmitter tuning windows indicate the
transmitter frequency and whether the radio is keyed.
Adjusting the softpot value sends information to the radio to increase (or decrease) a DC voltage in
the corresponding circuit. For example, increasing the value in the Reference Oscillator tune window
instructs the radio microprocessor to increases the voltage across a varactor in the reference
oscillator to increase the frequency. Pressing the Program button stores all the softpot values of the
current window permanently in the radio.
In ALL cases, the softpot value is just a relative number corresponding to a D/A (Digital-to-Analog)
generated voltage in the radio. All standard measurement procedures and test equipment are
similar to previous radios.
Refer to the DPS on-line help for information on the tuning software. Perform the following
procedures in the sequence indicated.
Note: All tuning procedures must be performed at a supply voltage of 7.5V unless
otherwise stated.
The radio requires two power level settings, a high power level setting, and a low power level setting.
To set the transmitter power, either to high or low setting, follow the procedures below:
Adjustment of the reference oscillator is critical for proper radio operation. Improper adjustment will
not only result in poor operation, but also a misaligned radio that will interfere with other users
operating on the adjacent channels. For this reason, the reference oscillator should be checked
every time the radio is serviced. The frequency counter used for this procedure must have a stability
of 0.1 ppm (or better).
RF-Band Target
VHF ±150 Hz
The rated volume softpot sets the volume at normal test modulation.
1. Use test box (RTX4005) and set SW1 switch to speaker. Connect an AC voltmeter to the test
box meter port.
2. From the Service menu, select Receiver Alignment.
3. Select Rated Volume to open the rated volume tuning window. The screen will indicate the
receive test frequency to be used.
4. Set the RF test generator to the receive test frequency and apply -47 dBm RF carrier frequency
with a 1 kHz tone at 60 % rated deviation. The 1 kHz tone must be audible to make sure the
radio is receiving.
5. Adjust the value of the obtained rated audio volume ( as close as 2.7 Vrms)
6. Press Program to store the softpot value.
The squelch softpots set the signal to noise ratio at which the squelch opens. The squelch value
needs to be set at 7 frequencies across the frequency range.
1. Use test box (RTX4005), connect a SINAD meter to the “METER” port.
2. From the Service menu, select Receiver Alignment.
3. Select Squelch Attenuation to open the squelch attenuation tuning window. The window will
indicate the receive test frequencies to be used.
4. Select the first test frequency shown, and set the corresponding value to 0.
5. Set the RF test generator to the test frequency, offset it with +500 Hz., and modulate it at 60 %
deviation with 1 kHz tone. Adjust the generator for a 18 dB SINAD level (weighted with
psophometric filter).
6. Adjust the softpot value until the squelch just closes.
7. Monitor for squelch chatter; if chatter is present, repeat step 6.
8. When no chatter is detected, select the next softpot and repeat steps 5 -7 for all test
frequencies shown in the window.
9. Press Program to store the softpot values.
Compensation alignment balances the modulation sensitivity of the VCO and reference modulation
(synthesizer low frequency port) lines. Compensation algorithm is critical to the operation of
signalling schemes that have very low frequency components (e.g. DPL) and could result in
distorted waveforms if improperly adjusted. The compensation value needs to be set at 7
frequencies across the frequency range.
Note: The step size change for step 8 is approximately 2.5% softpot value.
The transmit deviation limit softpot sets the maximum deviation of the carrier. The deviation value
needs to be set at 7 frequencies across the frequency range.
1.8 RSSI
1. Use test box (RTX4005) and set the SW1 switch to SPEAKER.
2. From the Service menu, select Receiver Alignment.
3. Select RSSI to open the RSSI tuning window. The screen will indicate the receive test
frequency to be used.
4. Set the RF test generator to the receive test frequency, and set the RF level to the value
indicated for RSSI Level 0, modulated with 1 kHz tone at 60 % deviation. The 1 kHz tone must
be audible to make sure the radio is receiving.
5. Press Program to store the softpot value for RSSI Level 0.
6. Repeat steps 4 - 5 for the remaining RSSI levels.
7. Press Cancel to close the window.
The MPT1327 Deviation Softpot is used to tune the FFSK signalling deviation. Tuning is performed
at one frequency. The radio generates an alternating bit pattern for tuning. Values for others
frequencies are calculated by the radio software.
The DTMF Deviation Softpot is used to tune the DTMF signalling deviation. Tuning is performed at
one frequency. The radio generates a DTMF signal for tuning. Values for other frequencies are
calculated by the radio software.
Chapter 6B.3
Theory of Operation
Table of Contents
Paragraph Page
1.0 Overview..................................................................................................... 1
4.0 Controller.................................................................................................... 8
4.1 Functions ..................................................................................................... 9
4.2 Normal Operation ........................................................................................ 9
4.3 Clock Synthesizer ........................................................................................ 9
4.4 Bus Operation.............................................................................................. 9
4.5 RAM............................................................................................................. 9
4.6 EEPROM ................................................................................................... 10
4.7 SPI Interface .............................................................................................. 10
4.8 LED Control ............................................................................................... 10
4.9 Audio & Data Circuitry ............................................................................... 10
4.10 External PTT Sense Circuits...................................................................... 11
4.11 MIC Amplifier ............................................................................................. 11
4.12 TX Data Circuits......................................................................................... 11
4.13 Sub-Audible Data (PL/DPL)....................................................................... 11
4.14 High-Speed Data ....................................................................................... 12
4.15 DTMF Data ................................................................................................ 12
4.16 MDC Data .................................................................................................. 12
4.17 RX Audio Processing and Digital Volume Control ..................................... 12
Paragraph Page
4.18 Audio Power Amplifier ............................................................................... 13
4.19 Audio PA Muting and Output Protection .................................................... 13
4.20 Receive Data Circuits ................................................................................ 13
4.21 Alert Tone Circuits ..................................................................................... 13
Figure
3-1 RF Block Diagram.................................................................................................................1
3-2 Receiver Block Diagram .......................................................................................................2
3-3 Transmitter Block Diagram ...................................................................................................4
3-4 Synthesizer Block Diagram...................................................................................................6
3-5 VCO Block Diagram..............................................................................................................7
3-6 Controller Block Diagram......................................................................................................9
1.0 Overview
6B.3
This section provides a detailed theory of operation for the VHF GP600 and its components:the
receiver, the transmitter, the frequency generation circuitry, the controller and audio & data circuitry.
2.0 RF Section
A block diagram of the RF section is shown in figure 3-1. The RF section of the radio is divided into
Receiver and Transmitter functions.
Ref. Oscillator
Rx. Lo
Tx. Lo FRACT_N
VCO Mod. In
RF SYNTHESISER 28
PA Pin
Conn.
Mod.
ATTN Lock Det.
Current
Sense
Vctrl Prescalar
2.1MHz
Vref Reset Spi bus
Power
Control DAC
Circuit
Tx. MIC
Spi bus Audio Int./Ext
to AMP Mic
Rx./Tx, LED Rx. Audio
in from ASFIC
Int./Ext. Audio Pa ASFIC
Speaker
From
5V
REG. Reg. 5V
Batt.
PA Enable from
ASFIC
2.1 Receiver
The receiver of the GP600 radios consists of 4 major blocks each: the front-end module, the double
balanced mixer, the 45.1 MHz IF and the back-end IF IC.
The GP600 front-end modules consist of three blocks of circuitry each: a pre-selector, RF amplifier
and a post-selector filter. These three items are located on a receiver module PCB that stands
perpendicular to the main radio PCB.
This module is enclosed in a shield to prevent radiation into and out of the module. It also improved
the grounding of the module by soldering the module shield to the main RF Board. All filters on the
VHF modules are fixed tuned designs to eliminate the need for factory tuning and to provide wide-
band operation.
“5R” (5V)
1st RF 2nd
Bandpass Bandpass
Filter Amp Filter
“5R” (5V)
Detected Audio
1st IF 2nd
Crystal Crystal IF IC
Filter Amp Filter
The shunt coupled resonator topology yields a more symmetrical frequency response to guard
against strong out of band signals that could produce IM products.
The worst case image frequency for this VHF band is 90.2 MHz above the filter passband. The 3 dB
bandwidth is approximately 35 MHz centred at 160 MHz. The centre of the band insertion loss is
approximately 1.9 dB. The 4-pole filter is designed to operate with 50 ohm input termination, while
the output termination is the input impedance of the RF amplifier that follows it.
The pre-selector filter is a 4-pole, 0.01 dB Chebyshev bandpass design implemented in a shunt
coupled resonator topology. This topology maximizes the attenuation at the worst case image
frequency for UHF band which is 90.2 MHz below the filter passband. The 3 dB bandwidth is
approximately 52 MHz. The centre of the band insertion loss is approximately 3.5 dB. The 4-pole
filter is designed to operate with a 50 ohm input termination, while the output termination is the input
impedance of the RF amplifier that follows it.
The RF amplifier, Q1, is a Motorola MMBR951, NPN device biased in a common emitter
configuration. The amp is stabilized by the shunt feedBack resistor R3, and has approximately 20 dB
of gain with a noise figure of about 3.0 dB (VHF). The amplifier draws 4.9mA of current and is
supplied by the receiver 5 volt supply (indicated as “5R” on the schematics and block diagrams).
Terminating the RF amplifier is the post-selector filter. This filter is the same as the prefilter. The filter
is designed to be terminated with the amplifier output impedance on one side, and 50 ohms on the
other.
The net gain from the receiver module is about 12.5 dB in the centre of the band and about 11.5 dB
at the band edges. The net centre of the band noise figure is approximately 5.5 dB. This is sufficient
to achieve a typical centre of the band sensitivity of 12 dBs.
The double balanced mixer is composed of the two baluns, T1 and T2, and the ring diode IC, CR2.
The mixer operates with an LO level of +6 dBm and the conversion loss is approximately 7.5 dB. The
double balanced type mixer provides excellent isolation between any two ports. And since a dBm
can operate over a large bandwidth, the same mixer can be used for VHF radios. The dBm also
provides excellent protection against receiver spurs due to non-linearizes, such as IM and Half-IF.
The received signal mixes down to the frequency of the first IF, 45.1 MHz, and enters the IF circuitry.
The Intermediate Frequency (IF) section of the portable radio consists of several sections including,
the high IF, the second LO, the second IF, and the IF IC chip. The first LO signal and the RF signal
mix to the IF frequency of 45.1 MHz, and then enters the IF portion of the radio.
The signal first enters the high IF, passes through a crystal filter, is then amplified by the IF amp, and
then passed through another crystal filter. The first crystal filter provides selectivity, second image
protection, and intermodulation protection. The amplifier provides approximately 16 dB of gain to the
signal. The signal then passes through the second crystal filter which provides further selectivity and
second image protection. The high IF has an approximate 3 dB bandwidth of 7 kHz for 20/25/30 kHz
models and 4 kHz for 12.5kHz models.
The filtered and amplified IF signal then mixes with the second local oscillator at 44.645 MHz. The
second LO uses an amplifier internal to the IF IC, an external crystal and some external chip parts.
The oscillator presents an approximate level of -15 dBm to the second IF mixer, internal to the IF IC.
The output of the mixing of the IF signal and the second LO produces a signal at 455kHz (second
IF). This signal is then filtered by external ceramic filters and amplified. It is then passed back to the
IF IC, sent to a phase-lock detector, and demodulated. The resulting detected audio output is then
sent to the ASFIC to recover the audio.
The IF IC also controls the squelch characteristics of the radio. With a few external parts the squelch
tail, hysteresis, attack and delay were optimized for the radio. The ASFIC allows the radio’s squelch
opening to be electronically adjusted.
2.2 Transmitter
The GP600 transmitters contain five basic circuits: a power amplifier, an antenna switch, a harmonic
filter, an antenna matching network, and a power control. Refer to the block diagram and the
schematic for more information.
The power amplifier used for transmitters is the LD-MOS module. The LD-MOS is capable of
supplying an output power at 6.8W with an input signal of 2mW and a supply voltage of 7.3V. The
power out can be varied by changing the biasing voltage at the first stage.
The antenna switch circuit consists of two PIN diodes (CR101and CR102), a pi network (C119,
L112, and part of C112), and at least one current limiting resistor (R102, R103 and R108 for VHF).
In the transmit mode, TX B+ is applied to the circuit to bias the diodes “on”. The shunt diode (CR102)
shorts out the receiver port, and the pi network, which operates as a quarter wave transmission line,
transforms the low impedance of the shunt diode to a high impedance at the input of the harmonic
filter. In the receive mode, the diodes are both off, and hence, there exists a low attenuation path
between the antenna and receiver ports.
PTT
Power µP Serial
Ip R101 Control *Note: Connection to 50 ohms
Bus
can only be made by removing
antenna and screwing in its
Sw B+ place special BNC-to-Phono
adapter (5880166s01).
The harmonic filter consists of part of C112, and L107, C113, L108, C114, L109, and C115. The
design of the harmonic filter for VHF is that of a Zolotarev design. This particular design is similar to
that of a Chebyshev filter except for a large amplitude first ripple (near dc). This type of filter has the
advantage that it can give greater attenuation in the stop-band for a given ripple level.
Another feature of this type of filter is that the coils tend to be smaller than with a Chebyshev design.
The design of the VHF filter was modified from the Zolotarev design by slightly changing its
capacitor values to yield a filter having an input impedance which optimized the efficiency of the
power module.
To optimize the performance of the transmitter and receiver into an antenna, a network is used to
match the antenna’s impedance to the harmonic filter. For VHF the network consists of C117, L111
and C122. Note that, in order to measure the power out of the transmitter, one must remove the
antenna and screw in its place a special BNC-to-Phono adapter.
The power control circuit consists of the networks associated with U151, Q156, Q151, Q152, Q155,
and U152. The Op Amp U151A-1 and Q156, along with resistor R101, make up a current-to-voltage
amplifier whose gain is mainly dependent upon the ratio of R179 to R153. The current to the final
stage of the power module is supplied through R101 (0.1 ohms), which provides a voltage
proportional to the current drain. This voltage is amplified and applied to the input of U151B. The
resistors at the input of U151A-1 (R151, R152, R154, and R155) keep the voltages at the inputs of
U151A-1 below its maximum allowable. These resistors are 1% tolerance parts to minimize the error
produced at the emitter of Q156 resulting from the voltage offset at the input of U151A-1.
The voltage at the other input of the summing amp, U151A-2, is supplied from two DACs contained
within U152. These DACs are controlled by the microprocessor, and provide the reference voltage
for the control loop. One of the DACs, that connected to Pin 9 of U152, provides a coarse tune
voltage, while the other provides a fine tune voltage.
Since the output of the DACs is not zero when they are set to their lowest level, resistor R169 is
provided to bias up the minus input of the summing amp to compensate for the bias resulting from
the DACs.
The error voltage at the input of U151A-2 produces a voltage at its output, which is in turn applied to
the series pass transistor, Q152, through its driver, Q151. The voltage at the collector of Q152 is
applied to the controlled stage of the power module, which for VHF is the module’s second stage.
The feedback from the collector of Q152 to the emitter of Q151 through R166 is provided to keep the
two stages stable. Likewise, the feedback from the collector of Q152 to the minus input of the
summing amp is to keep the whole control loop stable.
The purpose of Q155 and its associated circuitry is to keep the control voltage on the module below
7.0 Volts, which is the maximum allowed for the VHF module.
The purpose of R173 was originally that of providing compensation to the control loop for changes in
the supply voltage, TX B+. However, experimentation has shown that this compensation is not really
required. Also, thermistor, R170, was provided to enable the shut back of the PA in the event that it
would get too hot. This has also been shown to not be required
The supply for the synthesizer is from regulated 5 Volts which also serves the rest of the radio. The
synthesizer in turn generates a superfiltered 5 Volts (*actually 4.65 Volts) which powers U251.
In addition to the VCO, the synthesizer must interface with the logic and ASFIC circuitry.
Programming for the synthesizer is accomplished through the data, clock, and chip enable lines
(pins 1, 2, and 35) from the microprocessor, U709. A serial stream of 98 bits is sent whenever the
synthesizer is programmed. A 5 volt dc signal from pin 2 indicates to the microprocessor that the
synthesizer is locked while unlock is indicated by a low voltage on this pin. Transmit modulation from
the ASFIC is applied to pin 8 of U201. Internally the audio is digitized by the Fractional-N and
applied to the loop divider to provide the low-port modulation. The audio is also run through an
internal attenuator for modulation balancing purposes before being output at pin 28 to the VCO. A
2.1 MHz clock for the AFIC is generated by the Fractional-N and is routed to pin 9 where it is filtered
and attenuated from 2.5 Volts to approximately 2 Volts.
3.1 Synthesizer
The Fractional-N synthesizer uses a 16.8 MHz crystal (Y201) to provide the reference frequency for
the system. The other reference oscillator components external to the IC are C205, C206, R207,
and CR203. The 16.8 MHz signal is divided down signal from the VCO. The loop filter, comprised of
R201, R202, R205, C201, C214, C215, and C216, provides the necessary d.c. steering voltage for
the VCO as well as filtering of spurious signals from the phase detector.
Data (5) 5
(U201) 2 Lock Det (to µP U709)
Clock (6) 6 FRACTIONAL_N
SYNTHESIZER 11 Mod out (to ASFIC U701)
Cex (7) 7
28 Mod out (to VCO modulation)
Mod In (8) 8
Reg 5V 12,19,22,23,3
lout
GND (4,21,13,30) 4,21,13,30 29 2-Pole
Prescalar In ladapt Loop Filter
20 31
Crystal 1
14
Crystal 2 AUX3 Steering line
Reference
15 TRB 5
Oscillator Voltage
cp bias 1 1
27 Controlled
Filtered 5V Oscillator
26 18
cp bias 2 (U251)
32
VCP 10 9 16 23 4 2
Rx injection
Voltage V-mult 1 Warp
Multiplier V-mult 2 Tx injection
For achieving fast locking of the synthesizer, an internal adapt charge pump provides higher current
capability at pin 31 than when in the normal steady-state mode. Both the normal and adapt charge
pumps receive their supply from the voltage multiplier which is made up of C202, C203, C204,
C231, CR201, and CR202. By combining two 5 Volt square waves which are 180 out-of-phase along
with Regulated 5 Volts, a supply of approximately 12.6 Volts is available at pin 32 for the charge
pumps. The current for the normal mode charge pumps is set by R203. The pre-scaler for the loop is
internal to U201 with the value determined by the frequency band of operation.
3.2 VCO
The VCO (U251) in conjunction with the Fractional-N synthesizer (U201) generates rf in both the
receive and the transmit modes of operation. The TRB line (U251 pin 5) determines which oscillator
and buffer will be enabled. A sample of the rf signal from the enabled oscillator is routed from U251
pin 23, through a low pass filter, to the pre-scaler input (U201 pin 20). After frequency comparison in
the synthesizer, a resultant CONTROL VOLTAGE is received at the VCO. This voltage is a DC
voltage between 3 and 10 volts when the PLL is locked on frequency.
Lo Rf
Injection Low 10,11 Rx
Pass 2 Rx Rx Tank
Filter Buffer Osc Control
Voltage
Tx Rf
Injection Low 4 Tx
Tx Tx 15,16
Pass Tank
Attenuator Filter Buffer Osc
Filter
Audio
Tx/Rx/BS 5 Tx VCO In
Prescalar Switching TRB Mod
Buffer Network
Low
Prescalar RF out Pass Pre-In (U201 pin 20)
Filter
In the receive mode, U251 pin 5 is grounded. This activates the receive VCO by enabling the receive
oscillator and the receive buffer of U251. The rf signal at U251 pin 2 is run through a low pass filter.
The rf signal after the low pass filter is the LO RF INJECTION and it is applied to the first mixer at
T2.
During the transmit condition, PTT depressed, five volts is applied to U251 pin 5. This activates the
transmit VCO by enabling the transmit oscillator and the transmit buffer of U251. The rf signal at
U251 pin 4 is run through a low pass filter and an attenuator to give the correct drive level to the
input of the PA module (U101 pin 1). This rf signal is the TX RF INJECTION. Also in transmit mode,
the audio signal to be frequency modulated onto the carrier is received by the transmit VCO
modulation circuitry at AUDIO IN.
When a high impedance is applied to U251 pin 5, the VCO is operating in BATTERY SAVER mode.
In this case, both the receive and transmit oscillators as well as the receive, transmit, and pre-scaler
buffer are turned off. In the Fractional-N, the battery saver mode places the A/D and the modulation
attenuator in the off state. This mode is used to reduce current drain on the radio.
4.0 Controller
The GP600 controller is an open architecture which consists of:
■ U709, Motorola 68HC11K1 microprocessor
■ U701, Audio Signalling Filter Integrated Circuit, ASFIC
■ U703, 1KByte EEPROM
■ U705, 128/256KByte OTP/FLASH ROM
■ U706, 8/32KByte Static RAM
■ U707, LCD Display Driver and
■ U704, 5V Voltage Regulator
U709, U703, U705, U706 and U707 are powered by U704. U701 is powered from a 5V Regulator
(U708) on Radio Module. In addition to the external memory devices, U709 has 768 bytes of RAM
and 640 bytes of EEPROM.
Reset
Rx. Filter
Σ
2.1 Vol
Micro- MHz & De-emp
28 Attn Rx.
processor
Pin Sq. Audio
Conn. Out LCD
Attn
In
Data, Address
7.9488 and Control
MHz Clk
Keypad
Lock EE-
Detect PROM
Low Batt.
Monitor ROM/ RAM
SPI Bus FLASH
Vol
Sense
LED
5V From
5V Reg. Batt.
Push Channel
Button Switch
Reset
4.1 Functions
The microprocessor has two basic functions: interfacing with the outside world and controlling the
internal workings of the radio. The microprocessor interfaces directly with the keypad, side buttons,
PTT, rotary switch, battery low indicator, EXT PTT and volume sense. The microprocessor
constantly monitors these inputs and interprets any changes into commands that control the rest of
the radio. Some control functions it performs include loading the synthesizer with the desired RF
frequency, turning the RF PA on or off, enabling and disabling audio and data paths and generating
tones. Operations and operating conditions within the radio are interpreted by the microprocessor
and fed back to the operator as visible (the display) or audible (alert tone) indications of current
status.
The regulated 5V output from U704 powers the microprocessor (U709) and the rest of the digital IC
except ASFIC (U701). The microprocessor’s clock is generated by the ASFIC, which has a built-in
programmable clock synthesizer.
Upon power-up and assuming that the ASFIC receives a proper 2.1MHz input on U701-P38 (which
comes from the transceiver board), the ASFIC outputs a 7.9488MHz CMOS square wave (0-5Vpp
logic) on U701-P30, which connects to the EXTAL input of the microprocessor, U709-P73. The
microprocessor operates at 1/4 of this frequency, which in this case computes to 1.9872MHz. In
particular, the E clock output (U709-P72) will be a 50% duty cycle square wave at this frequency.
The microprocessor operates in expanded memory mode and executes firmware contained in OTP/
FLASH ROM, U705. The microprocessor uses a non-multiplexed address data bus, consisting data
lines D0 through D7 and address lines A0-A17. In addition, the microprocessor has integrated chip-
select logic so that external memories can be accessed without the need for external address
decoder gates. These chip-select signals are provided by U709-P28 and P29.
When the controller board is functioning normally, microprocessor’s address and data lines should
be toggling at CMOS logic levels. Specifically, the logic-high levels should be between 4.8 and 5.0V,
and the logic-low levels should be between 0 and 0.2V.
4.5 RAM
The on-chip 768 byte static RAM from U709 provides some scratch-pad memory, with the bulk of it
coming from the external 8 or 32Kbyte SRAM, U706. External SRAM accesses are indicated by the
U709-P28. Normally SRAM is accessed less often than the OTP/FLASH ROM, U705; i.e. the
number of transitions per second on U705 chip select (pin 30) should be 5-15 times higher than
those on U706 pin 20.
4.6 EEPROM
The radio codeplug storage is provided by U709 internal 640 byte EEPROM, with an additional
1Kbyte of memory space provided by external EEPROM, U703. There are three basic types of
codeplug information: information on the trunked system on which the radio is authorized to operate;
information on the conventional system, which is either of the repeater or talk-around type on which
the radio is authorized to operate, and information on the configuration and tuning of the radio itself.
Tuning information is normally located in the internal EEPROM of U709.
The microprocessor communicates to several ICs and modules through a dedicated on-chip serial-
peripheral-interface (SPI) port which consists of transmit data line MOSI (U709-P1), receive data
line MISO (U709-P80), and clock line SCK (U709-P2). In addition, each IC that can be accessed by
the microprocessor using the SPI has a read/write select line associated with it. The ICs or circuits
and their associated select lines are:
■ EEPROM (U703) with select line U709-P3
■ ASFIC (U701) with select line U709-P34
■ LCD Driver (U707) with select line U709-P23
■ SRAM (U706) and OTP/FLASH ROM (U705) with select line U709-P33
■ Transceiver board Synthesizer (U201) with select line U709-P35
■ Transceiver board DAC IC (U152) with select line U709-P26
The LCD Driver uses the master out/slave in (MOSI) line to send data to the display driver IC, and
the master in/slave out (MISO) line to send data back to the microprocessor (U709). Note, however,
that the keypad (or any other SPI device) can never initiate display data; the microprocessor is at all
times the SPI master device. Thus the MOSI line and MISO line are always in the master
configuration.
The bi-colour LED on the top of the radio is indirectly activated by SPI of U709 via the DAC IC
(U152) on Transceiver Board. When either input to the dual NPN transistor (U410) is at logic high,
the corresponding output pin (pin 6 for the green LED, pin 3 for the red) should be at approximately
4.3 Vdc. Note that it is possible to have both LED outputs on simultaneously, in which case the LED
emits a yellow/orange light.
The transmit and receive audio paths are disabled in the standby mode and selectively enabled by
the microprocessor when the radio transmits or receives a signal. Also, there are minor differences
in the functioning of both paths depending on whether an internal or external (accessory)
microphone/speaker is being used. The radio constantly monitors the received data path for control-
channel data in trunking operation or sub-audible data in conventional operation.
On connecting an external MIC through connector J3, external PTT sense transistor Q408 switches
“ON” when the external PTT switch is closed. Q408 collector voltage is monitored by U709-P4.
When collector voltage is logic “HIGH”, the microprocessor configures the radio for transmit mode.
In PTT equipped accessories, the PTT switch is series connected with the external MIC element.
MIC audio from internal MIC MK401 is coupled through C429, L404, J3 and L403 to the MIC buffer
circuit U405-1. External MIC plug insertion mechanically disconnects the internal MIC. External MIC
audio is coupled through L403 to the MIC buffer input. The unity gain buffer will route the MIC audio
into MIC IN (U701-P7) through flex and connectors J200 and J700. Inside the ASFIC, the MIC audio
is amplified, filtered to eliminate components outside the 300-3000Hz voice band, pre-emphasized,
and then limited. The limited MIC audio is then routed through a summer, which is used to add in PL
or DPL sub-audio band modulation, and then to a splatter filter to eliminate high frequency spectral
components generated by the limiter. After the splatter filter, the audio is routed to the 8 bit
modulation attenuators, which are tuned in the factory of the field to set the proper amount of FM
deviation. The TX audio emerges from the ASFIC at U701-P55 is dc coupled and applied through
flex and connectors J700 and J200 to the synthesizer (U201) pin 8.
There are four major types of transmit data: sub-audible data (PL/DPL/Connect Tone) that gets
summed with voice, high speed data for trunking control channel communication, DTMF data for
telephone communication in trunked and conventional systems, and MDC data for use in Motorola
proprietary MDC systems. The deviation levels of the latter three types are tuned by a 5-bit digital
attenuation inside the ASFIC. For each data type and each band split, there is a distinct set of tuning
values that are programmed into the ASFIC before the data is generated and transmitted.
Sub-audible data is composed of low-frequency PL and DPL waveforms for conventional operation
and connect tones for trunked voice channel operation. (The trunking connect tone is simply a PL
sine wave at a higher deviation level than PL in a conventional system). Although it is referred to as
“sub-audible data”, the actual frequency spectrum of these waveforms may be as high as 250Hz,
which is audible to the human ear. However, the radio receiver filters out any audio below 300Hz, so
these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U701 at any one time. The process is as
follows: using the SPI, the microprocessor programs the ASFIC (U701) to set up the proper low-
speed data deviation and select the PL or DPL filters. The microprocessor then generates a square
wave from U705-P6 which strobes the ASFIC PL_CLK (U701-P20). For encode input at twelve
times the desired data rate. (For example, for a PL frequency of 103Hz, the frequency of the square
wave at U701-P20 would be a1236Hz). This derives a tone generator inside U701, which generates
a staircase approximation to a PL sine wave or DPL data pattern. This internal waveform is then low-
pass filtered and summed with voice or data. The resulting summed waveform then appears on
U701-P55 (VCO_ATN), where it is sent to the transceiver board as previously described for transmit
audio.
High-speed data refers to the 3600 baud data waveforms (ISWS AND OSWS) used in a trunking
system for high-speed communication between the radio and the central controller. To generate an
ISW, the microprocessor (U709) first programs the ASFIC (U701) to the proper filter and gain
settings. It then begins strobing U701-P54 (Trunking Clock In) with a square wave (from U709-P5) at
the same baud rate as the data. The output waveform from 5-3-2 State Encoder of U701 is then fed
to the post-limiter summer block and then the splatter filter. From that point it is routed through the
mode attenuator and then out of the ASFIC to the transceiver board via VCO_ATN (U701-P55).
DTMF data is a dual-tone waveform used during phone interconnect operation. They are divided into
low-group and high-group tones. The high-group tone is generated by U709-P5 strobing U701-P54
at six times the tone frequency for tones less than 1440Hz, or twice the frequency for tones greater
than 1440Hz. The low-group tone is generated by U709-P7 strobing U701-P53 (DTMF Clock) at six
times the tone frequency. Inside U701 the low-group and high-group tones are summed (with the
amplitude of the high-group tone being approximately 2dB greater than that of the low-group tone)
and then pre-emphasized before being routed to the summer and splatter filter. The DTMF
waveform then follows the same path as was described for high speed data.
The MDC signal follows exactly the same path as the DTMF high-group tone. MDC data utilizes
MSK modulation, in which a logic zero is represented by one cycle of a 1200Hz sine wave, and a
logic one is 1.5 cycles of an 1800Hz sine wave. To generate the data, the microprocessor (U709)
first programs the ASFIC (U701) to the proper filter and gain settings. It then begins strobing U701-
P54 with a square wave (from U709-P5) at the same baud rate as the data. The output waveform
from U701 is fed to the post-limiter summer block and then the splatter filter. From that point it is
routed through the mode attenuator and then out of ASFIC to the transceiver board via VCO_ATN
(U701-P55).
The radio’s RF circuit are constantly producing an output at the Detected Audio line. Whenever the
radio is in trunked standby mode, it is processing data from the control channel; while in
conventional standby mode, it is always monitoring the squelch line and/or sub-audible data. The
detected audio from the transceiver board enters the controller board at connector J700 pin 4. In
addition to the detected audio line, the transceiver board also provides a squelch noise from U51-
P30 into the ASFIC squelch-detect circuitry via U701-P56. When the microprocessor is satisfied that
it has received the proper data or signal type for unsquelching, it sets up the receive audio path and
sends data to U701 to do the same within.
The detected audio will enter U701 through RX IN (pin 57) and PL IN (pin 63) for further processing.
Inside the IC, the signal first passes through a low-pass filter to remove any frequency components
above 3000Hz and then a high-pass filter to strip off any sub-audible data below 300Hz. Next, the
recovered audio passes through a de-emphasis filter to reduce the effects of FM noise. Finally, the
IC amplifies the audio and passes it through the 8-bit programmable attenuator whose level is set
depending on the value of the volume control. The microprocessor (U709) programs the value of the
8-bit attenuator in accordance with the voltage sensed at the volume potentiometer, which is
connected to U709-P48. This pin is one of the eight channels of U709’s 8 bit A/D convertor. After
passing through the 8-bit digital attenuator, the audio goes to a buffer amplifier and then exits at
U701-P66, where it is routed to the Audio power amplifier circuit in the transceiver board.
Resistor R466 sets the input impedance to U409-P2 of the audio power amp. The audio PA circuit is
a bridged-tied-load (BTL) configuration with fixed gain of 40dB, developing 500mW (rated audio
power) output at less than 5% harmonic distortion into the 16 ohm internal speaker LS401 with
nominal 7.5Vdc battery supply. Maximum audio power output is greater than 1.2 watts.
PNP transistor Q410, the audio PA power switch, driven by NPN darlington transistor Q411, the PA
mute amp, controls Vcc supply to Audio PA U409-P1. U701-P5 is connected to Q411 base,
controlling audio PA Vcc supply. Resistors R489 and R490, PNP transistor Q412 and the current
sense circuit monitor current supplied to audio PA U409-P1. Worst case audio PA current (at 9Vdc
battery voltage, maximum volume and full system deviation) does not exceed 450mA at the nominal
16 ohm load. Resistor R488 and capacitor C461 provide an RC time delay for U405-2, a monostable
multivibrator circuit. A 2.5Vdc reference voltage is fed to U405-2-P6. On radio power-up, and in
normal operation U405-P7 monostable multivibrator output is logic “LO” pulling Q411 emitter to Vee
with the audio PA controlled by U701-P5. Should U409-P5 and/or U409-P8 become shorted to each
other or to the ground (Vee), current consumption exceeds 500 mA (approximately) and Q412
collector. When U405-2-P5 voltage rises higher than the U405-2-P6 reference voltage (rise time is
less than 50 usec), U405-2 is triggered and U405-2-P7 dc output voltage is switched to 4Vdc,
effectively biasing Q411 into cut-off and turning off the audio PA power switch Q410. U405-2-P7
remains in this state for 15 msec, then reset to logic “LO” state. Average power dissipation in the
audio PA circuit components is helped to a low level by the low duty cycle (less than 0.3%) of the
audio PA protection circuit. The cycle repeats until the audio PA output short is removed.
The ASFIC (U701) decodes all receive data, which includes PL, DPL, low-speed trunking, MDC,
and high-speed trunking data. The “decode” process for each data type typically involves low pass
or band pass filtering, signal amplification, and then routing the signal to a comparator, which
outputs a logic zero or one signal. The detected audio from the transceiver board is routed to U701-
P57 and P63 through coupling cap C435. Inside U701, the data is filtered according to the data type
(HS data or LS data, then hard-limited to a 0-5V digital level. The high-speed limited data output
(MDC and trunking high-speed) appears at U701-P51, where it connects to U709-P11. The low
speed limited data output (PL, DPL and trunking low-speed) appears at U701-P4, where it connects
to U709-P10.
When the microprocessor needs to give the operator feedback (for a good key press or for a bad key
press) or radio status (trunked system busy, low battery condition, phone call, circuit failures), it
sends an alert tone to the speaker. It does so by sending data to U701, which sets up the audio path
to the speaker for alert tones. The alert tone itself can be generated in one of two ways: internally by
the ASFIC, or externally using the microprocessor and the ASFIC. The allowable internal alert tones
are 300, 900 and 1800Hz. For external alert tones, the microprocessor can generate any tone within
the 100-3000Hz audio band. This is accomplished by the microprocessor toggling the output line
U709-P7, which is also the same line used to generate low-group DTMF data. Inside the ASFIC, this
signal is routed to the external input of the alert tone generator. The output of the generator is
summed into the audio chain just after the RX audio de-emphasis block. The tone is then amplified
and filtered before passing through the 8-bit digital volume attenuator. The tone exits at U701-P66,
then is routed to the audio PA circuitry in the transceiver board.
Chapter 6B.4
PCB/Schematic Diagrams and Parts Lists
Table of Contents
Description Page
VHF (146-174MHz) Diagrams and Parts Lists
Controller PCB Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Controller Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
RF PCB Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RF Overall Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RF (Receiver Module) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RF (Synthesizer) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RF (Transmitter Module) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RX-FE Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DS702 DS701
DS704 DS703
J701 1
34
32 17
15 14 33 16
R799
C721
S01 S02 S03 S04
R781 C745
U706 U707
R755 C787 C746
R700 C700
VR707
48 1
49 64 TP7
C754
R790
C781
R711
R713
C744
CR707 S13 S14 S15 S16
Q704 R710
28 1
C719
C758
R787
Q703 16 Q700
Q705 17 C720
4 R763 C777 C786
5 U705
C718
R712
R753
U703
C716
C717
8 1 TP4 32 1
C711 S07 S08 S09 S10
R726
80 61 C407 H8 B8
R403
1 60 6 4 J7 A7
U704
1 3 R786
U701
C763
C406 C765
R725
R764
R751
C707
C737 C708
C731
C743
20 41 C769
21 C733 R705 C710
40
28
C741
C732
2
C747
C435
C742
R468
Q702
R752
J700
1 27
Controller Board
PCB No. 8404599J03
Controller Board-
8404599J03
Diode, Transistor:
Integrated Circuit:
C224 C226
C212
C227
C273
L204
L253 4 SH105 C33 L11 L53 Y51B
2
CR203
C272
Y201T 2 3 R253 5 4 6 3
C258
CF51 CF52
R54 C56
C59 C78
C29 C30
C286
C233 T2 C28
C455
L255 L260 L55 R460
L203 2
3
2 3
C217
C232 C205
C268
Y51A
R267 R254 L9 C58
L268 C279
R207
5
C206
C235 5 30
CR255 8 5 C55 R55
SH104
R205 C281 CR2
L262
C219
C790
C209
C215
L201 C257 C278 4 L52 U51
C75
R258 C266
C259 C73 J6
4 C265 L259 3 2 R51 C79
Y53
C204
12 23
C74
R64
C291 L258 L261
2 3
C269
L51
SH103 C68
C51
T1
C63
C271 L58
4
2
C270 C66 C69 R57 C67 SW401
4 5
C
8 C
C116 R105
R106 7
C117
C289 U252
C418
R104
C419
C288 C425 R447 6 5 4 3
C498
8 5
CL5
C424
R448
C485 C486
C287 U708
Q408 4 L111
C421
R169
L407 J1
R452 C452 R503 C122
R451
U709
2
L403 R170 3
4 4 C800
C461
R173
U405 L710 4
R702
C499
R488
U409 L404
5 8
6
5
4
2
5 8 C429 J2
C409
L101 C103
CL4
C430
PB403 PB401 PB402
RF Board
CL3 CL2
Component Side
VR704
R802 R410
R803 R411
R801R409
R804 R415
CR252
C57
CR405
L54
C254
C454 C789
C208
R212
C236
C207
R263
C251 C456
L251
CR51
R60
C62
JU51
R52
C54
C255
R203
C284 R261
R211 R251
C457
C82 R67
C252 C476
R408 C290 L256 C77 R53 L717
C472 17 24 R204 17 C71
C60
21 22
C61
R497
16
C70
R216 C230 25 L252 16 C53
R414
R202
C83 C64
R417 R215C223 C474
R264
C256
C31
C473 C466 U201 L267
C264 C263
32
R416
C237
8
R201
C201
3
4
R413
C86
CR201 R58
R412
U410
L254
3
C203 C222 C261
C220
C221
C80
R66
L257
R257
Q405
C262
C260
C238
6
CR202
C475 C436
1 CR253
VR401
C459 C443
C214 C276 C280
J200 C231 C218 C229 SH101 C81
SH100
C158
R193
C410
C34 R162 C460
C193 C151
R167 SL R158
C168 R168 5 8 C35
R160
R494
C199 R159
C154
C159 22 4
5 U151A Q151 2 C156 C120 3
C119
21
C480
R450
R449
C426
4 1 L112 L406
C437 R469
R166
CR102 R102
U152 Q153 R161
R489 R157 C153
C469 R466 C479
9 C152 C163 2
C105
17
Q154
C113
C438 Q410 16 10 C111 C118 L405
R155 Q156
R108
C428
CR101
C121
J3
R156
R153
R507
R103
L107
C464 C115
R175
R496
L102
C442 R174
L109
C114
Q411
R467 C441 C166 L106 5
CL9 R151 6
R152 C164 C167
C107
J5 L104 R107
C102 C106
1 2 3 4
RF Board
Solder Side
RF Board
PCB No. 8404880J01
BATTERY
GRAPHICS ONLY
0180702489 BATT FILTER BOARD
* CONNECTION VIA CHASSIS
R497 SCI SCI
470 refer to R460 C3
SW402-1 39
L710 SW_ONOFF CONN_BPLUS
5V SWB+ TXB+ EN_BIAS 5V SWB+ 5R THERMAL FUSE
390nH F1
U708 C421 P/O VOL
L1 L2 4A
8 1 .47uf
6
VIN VOUT
2 CHG+
7
5V_TAP SENSE
4 CR405 C1 C2 C4
C419 5 FEEDBACK GND NU 39 39
ERROR
.018uf SHUTDOWN 3
SWB+
(SOURCE) CHG-
L407 1.2uH
5V SWB+ TXB+ 5V SWB+ 5R
C418 C486 C485 J200
10uf 1000pf 1000pf CONN_89982-28
5V 1 SWB+
EN_BIAS SQATTNIN
(SOURCE) 2 GND
DETAUDIO 3 SQATTNIN
TRANSMITTER RX_IN RX_IN RECEIVER 4 DETAUDIO
RSSI 5 RSSI
RX_INJ 6 ADAPT
ADAPT 7 LOCKDET
8 SYNLE
9 MODIN
CLK RESET DACLE TX_INJ 10 SB1
11 SB2
5V 12 ROT1
13 ROT2
(SOURCE FROM ASFIC) 14 2.5V
15 5V
16 MICIN
17 SRDATA
RX_INJ 5V 18 RXAUDIO
LOCKDET 19 GCB1
C287 20 VOL
CLK RESET DACLE SYNLE 1000pf R447 21 PTT
22 EXTPTTSENSE
SB1 SB2 2.5V 5V 5V 23 SCI
MODIN NU C425
TX_INJ VOLUME 24 SRCLOCK
C424 NU 25 DACLE
DATA SRDATA PORT
SYNTHESIZER L717
VOL SENSE
26 RESET
27 GND
SRCLK NU C480 .39uH 28 2.1MHZ
CLK NU R460-2 XX
XX VR704
R448 R450 C789
SW_ 100pf 6.8V
2.1 MHZ 2.1 MHZ
0 ONOFF XX C288 C289
NU
U405-1 NU NU
DACLE
RESET
PTT
2.1MHZ
DATA
CLK
OPAMP_4PIN
2 N2 C426 C427
SWB+ 1 .22uf
.22uf L403
R507 R489 R490 N1 3 N3
1000 2.7 2.7 4 MMBT3906 390nH J3
1/8W 1/8W R451 C481 S2XX EXT_MIC-SPKR
SWB+ N4 Q408 2200 150pf
2 R449 C428
100K 470pf R494 3 S3XX
Q412 100K EXT MIC
MMBT3906 2 2 S1XX
1 C438 MIC FILTER
C461 4.7uf 1 C410
3 3 2.5V VR401 J5
R452 150pf C409 C436 CONN_4PIN
1 150pf 10V 470pf 1
.1uf C464 R503 180K MK401
3 INT MIC
R488 Q410 1
Q411 5V 2
220K 8 .1uf M41L03 MMBTA13 330 C452 L404
5 N4 2 C498 4.7uf
N3 R496 390nH
7 1000pf
SHIELDS AND BUTTERFLY CLIPS N1
6 330 C429
N2 U405-2 4700pf 3
2.5V L405 LS401
OPAMP_4PIN R702 INT SPKR
390nH EN_BIAS 4
1 1 1 1 1 1 1 1 1 16 ohm
AUDIO AMPLIFIER 2000 C430 C442
CL CL CL CL CL CL CL CL CL R467 C499 470pf J4
U409 10 1000pf 1000pf
CL11 CL9 CL8 CL7 CL6 CL5 CL4 CL3 CL2 TDA7052 S2XX EXT_MIC-SPKR
R469 1 5 C441 S3XX
Vp OUTPUT1 EXT SPKR
C437 .1uf L406
1800 2 INPUT 8 S1XX
OUTPUT2
GND0
GND1
390nH
NC1
NC0
.47uf C469 C443
SH101 SH100 SH103 SH104 SH105 R466 C479
47pf 4700 470pf 3 6 1000pf
SH1 SH1 SH1 SH1 SH1 4 7
NC NC
1 1 1 1 1
5V
ROT1
ROT2
R801 R802 R803 R804 R409 43K
SW_FREQ_16POS 10K 10K 10K 10K
SB1 SB2 PTT SW401 PC3 8 R408 20K
PC2 4
C466 C467 C468 PC1 2 R411 43K
PC0 1
1000pf 1000pf 1000pf C0 C1 C460 C475 C459 C474 C456 C454 C457 C455 R410 20K
.1uf .1uf .1uf .1uf
R416 1000pf 1000pf 1000pf 1000pf
R415 R417
100 100 100 R414 R415
C476 C472 510K 510K
C473 1000pf
1000pf 1000pf
SW_TACTILE
SW_TACTILE
SW_TACTILE
1 2 1 2 2 1
PB401 PB402 PB403
SCHEMATIC DIAGRAM OF OVERALL CIRCUITS
MON OPT2 PTT VHF (146-174MHz)
GEPD5564
RF Schematic Diagram
.01uf 1000pf
2
1,2 1 T2 Y51A
3 4
5V 5,6 45.1MHZ
FRONT END RECEIVER MODULE U252 6 8 2 INSTPAR
XFMR C30 R51 L51
MODRF_6PIN VOLT 1000pf 1 3
CR2-1 1 5 .15uH C53 L53 C77
51
1 2 3 4 5 6 C35 L9 22pf 1.2uH 3pf
T1 L11
4 3 C51 2
CR2-2
RX_IN VOLT 68nH 22nH
82pf C36 2
7,8 C33 C28 C29 82pf
NU 5 7
6.8pf 51pf 51pf
5 1
XFMR 4
3,4
RX_INJ
C790 1000pf
4F(N) 6F(N)
R55 4D(W) 4E(W)
C55 .1uf 455KHZ
5R 455KHZ
100 FILTER FILTER_6POLE
R54
2000 1 3 1 5
2.5VDC
2.5VDC
R52
C61
33K 2
3.8VDC
CF51 CF52
C82 INSTPAR 2 3 4 INSTPAR
R67 1500pf
2.9VDC JU51 CR51
4 3 36 35 33 32
.1uf 6800
FIL_CAP_OUT
2ND_IF_OUT
IF_AMP_OUT
LIM_IN
FIL_CAP_IN
IF_AMP_IN
C56 NU
3 Q51 JUMPER
20pf Y51B C59
NPN C78 0.75VDC
C54 INSTPAR 6 PPC_AMP_IN
0.7VDC MMBR941
1 1 3
C57 L54 0 C58 .1uf 1.5VDC 5
L55
15pf NU NU .15uH NU DEMOD_OUT 31 2.0VDC
R53 2 PPC_AMP_OUT
12K 45.1MHZ
2 C60 .47uf
.1uf C62
8 IF_IN
3.0VDC AUDIO_IN 29 2.4VDC
1
GND
13 28 2.5VDC
A+_B+ DETAUDIO
14 AUDIO_OUT
SWB+ DRIVE
C75
U51 2.4VDC
4.4VDC 7 LO_IN 23 C80
3.9pf SQ_LIM_OUT
IFIC NU
C73
2.6VDC 10 C63
OSC_OUT
20 2.4VDC
2 13pf SQ_ATTEN_IN
R66 Y53 C74 R64 3.4VDC 9
OSC_FB
820 45MHz 36pf 5600 51pf
1 27 22
44.645 5R T_R ADAPT ADAPT
2 5.0VDC(UNSQ)
VCC1 0VDC(SQ)
C79 15 C87
SQ_OUT 5.0VDC(UNSQ)
16pf 12 1000pf
VCC2 0VDC(SQ)
2.4VDC
17 18
5V VCC3 FAST_SQ
C69 L58
3.3uf 3-5VDC 1.2uH C71 C70 34
PCC_2_SU
VCC4 R68
RSSI_OUT
SQ_TAIL
10uf .1uf 30
SQ_NOISE SQATTNIN
FILTER
3.7VDC
SQ_IN
C68 R57 C81
.039uf 130K 25 0
ICO
RSSI_OUT_2
R60
.1uf 16 19 11 26 24 10K
C87 C85 C86
3-5VDC 1000pf 1000pf 1000pf
0.5-3.0VDC 0.65VDC
SCHEMATIC DIAGRAM OF RECEIVER MODULE
VHF (146-174MHz)
GEPD5563
RX_INJ
C260
8.2pf
C280
C272 R257 1000pf C231
3.6pf C261 C263
16pf 1.0pf C238 C237
82K CR253 .01uf 100pf 100pf C202
R258
R260 L256 C262 C264
100 C204 5.0VDC (LOCKED)
C266 FILT5V L257 .01uf 0VDC (UNLOCKED)
L259 1.2uH 220 1.2uH 9.1pf 13pf 5V
C268 1000pf
1.2uH C278 L267 4.7uf CR202 CR201
.22uf L258 C203
1000pf .18uH C222 .01uf LOCKDET
NC1 6
VCC 3
LA1 7
NC2 8
E1B 9
L262 L255 66.8nH C228 C219
L260 FILT5V 150pf 150pf
E1A
R264 12.6VDC
.12uH 2 RX 27nH 1.2uH R205 1000pf SYNLE
B1 11 C256 10 L201 2200 3-10VDC
C269 L261 C259 1.2uH
VCP 32
10
4 TX R202
BI1 12 1000pf C215 C216
7
TX_INJ C265 1000pf R265
.15uH 5600pf .1uf 2200
V_MULT_1
V_MULT_2
U251 .1uf
CEX
C270
LOCK
1000pf C271 L254 3-10VDC 29 I_OUT
3.9pf 22 NC4 4.7
4.7pf VCOBIC VC 13 C255 C201 SL 31 I_ADAPT 8 2.5VDC C218 MODIN
C253 R201 T1 MOD_IN
R261 .15uH 51 NU R206 R215
24 NC5 2.5VDC
BI2 14 6.8pf C284 22pf
1 4 GND FREQ_OUT
11 1000pf
2.1MHZ
220 3-10VDC 13 GND 12 2200 1000
L251 C254 1.5pf L253 CR252 C214 DC_5V_REF_OSC 5V R216
1 GND2 B2 15 C279 1.2uH 1.0pf 1uf U201 R286 R267 2.0VDC 24K C290
20 GND1
5 TRB
18 NC3
XTAL_1
17 E2B
16 E2A
1000pf
19 LA2
FRACTN-32 33pf
23 PS
23 DC_5V_REF_DIV
WARP
22 DC_5V_PRESC
1000pf C252 1.2uH 2
20 PRE_IN 17 4.65VDC C206 R207 Y201T
18 SUP_F_OUT
L252 11pf C257 R253 C258
3 DC_5V_SRL
C235 SUP_CAP
SRL_CLK
5 SRL_DATA
1.2uH CR255 47pf 2400 16.8MHz
27 CP_BIAS1
26 CP_BIAS2
19 SUP_F_IN
1000pf 3000 NU .018uf C232 1
24 TEST_1
25 TEST_2
C207 NU
R251 R263 C281 0.7VDC(R) 4.7uf
21 GND
C251 C233
1.5VDC
82K 7500 NU 15pf 4.2VDC(T)
FILT5V
FILT5V R211
6
C209 CR203 2.7pf
C276 NC NC 47K
C273 NU
1000pf C224
.220uf
L204 1000pf
C211 C229
.1uH 4.7uf .22uf
C227 C226 R212
7.5pf R203 R204
13pf L203 NU 47K 33K
1.2uH
4.65VDC
FILT5V
(SOURCE) C210 C212 C236
4.7uf 1000pf 470pf
C208 C291
.1uf C220
4.7uf 150pf C221 SCHEMATIC DIAGRAM OF SYNTHESIZER
150pf
VHF (146-174MHz)
5V CLK DATA GEPD5560
C120 CR102
RX_IN
470pf C119 C118 R102 TXB+
20pf 470pf 150
75 75
4
FREQ_SW3
N4 R160 TO U51-PIN 13,14
VSS
Q156 U151A-1 C193 680
13 MMBT3904 3 OPAMP_4PIN
R412 1
R413 NPN 1.65VDC(HI)
180 1 C165
680 N1 .1uf U151A-2 0.75VDC(LO)
.01uf 3
1 N2 OPAMP_4PIN
R193
DATA 6 Q151
3
DS401 1 7
N1
1
20K N3 NPN R158
R179 2 R156 R173 R170 2.31VDC(HI) MMBT3904
5
C800 8 N4 180
R168 1.40VDC(LO)
360 3900 NU NU .1uf 2
C159 100K C154
470pf R159
4 2 C166
CLK RESET DACLE R169
LED_DUAL 2.91VDC(HI) .47uf
180
1.11VDC(LO) C157 470pf
10K
5V .01uf
EN_BIAS
VHF (146-174MHz)
GEPD5562
H102 1405160A02 Insulator, crystal L253 2480145S05 Coil 51/2turn Ferrite core
J3 0180417C01 Assembly Option Jack L258 2480145S04 Coil, 4.5 turns, Ferrite
core
J5 0180195R03 Speaker Microphone
Header L259 2462587N69 Chip 1200nH, 5%
L101 2411087B24 TDK molded coil 68nH, L710 2462587N60 Chip 390nH, 5%
L102 2411087B24 TDK molded coil 68nH, L717 2462587N60 Chip 390nH, 5%
Circuit Motorola
Description
Ref Part no.
Crystal:
Non-referenced Items
7504620J01 Keypad
6104617J01 Lightpipe
3304623J01 Nameplate
C7 2113740G31 12
C8 2113740G16 3.6
C9 2113740G27 8.2
C10 2113740A37 22
C11 2113740A42 36
C13 2113740A33 15
C15 2113740A51 68
C16 2113740A37 22
C17 2113740A52 75
C18 2113740A39 27
C19 2113740A41 33
Diode:
Transistor:
R1 0660076A61 3300
R2 0660076A47 820
R3 0660076A69 6800
R4 0611077A18 4700
R5 0660076A43 560
Chapter 6C
438-470MHz Specific Information
Table of Contents
Chapter
6C.1 Model Chart and Test Specifications
Chapter 6C.1
Model Chart and Test Specifications
Table of Contents
Paragraph Page
1.0 Overview......................................................................................................1
1.0 Overview
6C.1
This chapter lists the UHF 438-470MHz models and technical specifications for the GP600 portable
radio.
GP600
Description
UHF
438 - 470 MHz
X = Indicates one of each required
AZP94VJB05N2_E
AZP94VJA05N2_E
Model
Item Description
X X PMLE4073_ RF Board, 12.5 kHz, (438-470 MHz)
X PMLN4086_ GP600 Front Cover Display Kit
X PMLN4087_ GP600 Front Cover Non-Display Kit
X X HLN9667_ Chassis Hardware Assembly
X X NAE6483_ Whip Antenna (438-470 MHz)
X X HNN9628_ Battery
X X 6802908X01_ GP600 User Guide
12.5kHz 20/25kHz
Sensitivity*
12dB SINAD (emf) µV 0.35µV 0.35µV
20dB SINAD (emf) µV 0.5µV 0.5µV Note: Self Quieting Frequencies
Audio Output Power
Self-quieting frequencies are frequencies
<5% distortion @1kHz 500 mW 500 mW
that are also generated by the radio and
with rated audio output
cause internal interference. On these
Spurious / Image 70 dB 70 dB frequencies the interference caused by the
Rejection self-quieter spur is great enough that a
radio will not meet its receiver sensitivity
Selectivity 60 dB 60 dB
specification.
Intermodulation 65 dB 65 dB
The frequency is: 453.6MHz
Switching Bandwidth 32 MHz
No degradation ....... ..... .
Chapter 6C.2
Radio Tuning Procedure
Table of Contents
Paragraph Page
1.0 GP600 Radio Tuning .................................................................................. 1
1.1 General ........................................................................................................ 1
1.2 Transmitter Power ....................................................................................... 2
1.3 Reference Oscillator .................................................................................... 3
1.4 Rated Volume .............................................................................................. 3
1.5 Squelch Attenuation..................................................................................... 4
1.6 Transmit Deviation Balance (Compensation) .............................................. 4
1.7 Transmit Deviation Limit .............................................................................. 5
1.8 RSSI ............................................................................................................ 5
1.9 MPT1327 Transmit Deviation / DTMF Transmit Deviation .......................... 6
1.1 General
The recommended hardware platform is a 386 or 486 DX 33 PC (personal computer) with 8 Mbytes
RAM, MsDOS 3.3, Windows 3.1 or later, and DPS (Dealer Programming Software). These are
required to align the radio. Refer to the DPS Installation Manual (section 2 of the Product Manual) for
installation and setup procedures for the required software; the user manual is accessed (and can
be printed if required) via the DPS.
To perform the alignment procedures, the radio must be connected to the PC, RIB (Radio Interface
Box), and Universal Test Set as shown in figure 2-1.
SERVICE MONITOR
30 dB PAD OR COUNTER
TRANSMIT
30 dB PAD WATTMETER
BNC
RF GENERATOR
SMA-BNC RECEIVE
58-80348B33
AUDIO IN TX
BATTERY TEST SET AUDIO GENERATOR
ELIMINATOR RTX-4005B
RLN-1014A RX
SINAD METER
RADIO TEST CABLE
RKN4034
AC VOLTMETER
PROGRAM/TEST CABLE
HKN9857
COMPUTER
RIB DATA
HLN9214 BUSY
GND
Before going into the Service menu, the radio must first be read using the File / Read Radio menu (if
the radio has just been programmed with data loaded from disk or from a newly created codeplug,
then it must still be read so that the DPS will have the radio’s actual tuning values).
All Service windows read and program the radio codeplug directly; you do NOT have to use the DPS
Read Radio / Write Radio functions to program new tuning values.
CAUTION: DO NOT switch radios in the middle of any Service procedure. Always use
the Program or Cancel key to close the tuning window before disconnect-
ing the radio. Improper exits from the Service window may leave the radio
in an improperly configured state and result in seriously degraded radio or
system performance.
The Service windows introduce the concept of the “Softpot”, an analog SOFTware controlled
POTentiometer used for adjusting all transceiver alignment controls. A softpot can be selected by
clicking with the mouse at the value or the slider or by hitting the TAB key until the value or the slider
is highlighted.
Each Service window provides the capability to increase or decrease the ‘softpot’ value with the
mouse, the arrow keys or by entering a value with the keyboard. The window displays the minimum,
maximum, and step value of the softpot. In addition transmitter tuning windows indicate the
transmitter frequency and whether the radio is keyed.
Adjusting the softpot value sends information to the radio to increase (or decrease) a DC voltage in
the corresponding circuit. For example, increasing the value in the Reference Oscillator tune window
instructs the radio microprocessor to increases the voltage across a varactor in the reference
oscillator to increase the frequency. Pressing the Program button stores all the softpot values of the
current window permanently in the radio.
In ALL cases, the softpot value is just a relative number corresponding to a D/A (Digital-to-Analog)
generated voltage in the radio. All standard measurement procedures and test equipment are
similar to previous radios.
Refer to the DPS on-line help for information on the tuning software. Perform the following
procedures in the sequence indicated.
Note: All tuning procedures must be performed at a supply voltage of 7.5V unless
otherwise stated.
The radio requires two power level settings, a high power level setting, and a low power level setting.
To set the transmitter power, either to high or low setting, follow the procedures below:
Adjustment of the reference oscillator is critical for proper radio operation. Improper adjustment will
not only result in poor operation, but also a misaligned radio that will interfere with other users
operating on the adjacent channels. For this reason, the reference oscillator should be checked
every time the radio is serviced. The frequency counter used for this procedure must have a stability
of 0.1 ppm (or better).
RF-Band Target
The rated volume softpot sets the volume at normal test modulation.
1. Use test box (RTX4005) and set SW1 switch to speaker. Connect an AC voltmeter to the test
box meter port.
2. From the Service menu, select Receiver Alignment.
3. Select Rated Volume to open the rated volume tuning window. The screen will indicate the
receive test frequency to be used.
4. Set the RF test generator to the receive test frequency and apply -47 dBm RF carrier frequency
with a 1 kHz tone at 60 % rated deviation. The 1 kHz tone must be audible to make sure the
radio is receiving.
5. Adjust the value of the obtained rated audio volume ( as close as 2.7 Vrms)
6. Press Program to store the softpot value.
The squelch softpots set the signal to noise ratio at which the squelch opens. The squelch value
needs to be set at 7 frequencies across the frequency range.
1. Use test box (RTX4005), connect a SINAD meter to the “METER” port.
2. From the Service menu, select Receiver Alignment.
3. Select Squelch Attenuation to open the squelch attenuation tuning window. The window will
indicate the receive test frequencies to be used.
4. Select the first test frequency shown, and set the corresponding value to 0.
5. Set the RF test generator to the test frequency, offset it with +500 Hz, and modulate it at 60 %
deviation with 1 kHz tone. Adjust the generator for a 18 dB SINAD level (weighted with
psophometric filter).
6. Adjust the softpot value until the squelch just closes.
7. Monitor for squelch chatter; if chatter is present, repeat step 6.
8. When no chatter is detected, select the next softpot and repeat steps 5 -7 for all test
frequencies shown in the window.
9. Press Program to store the softpot values.
Compensation alignment balances the modulation sensitivity of the VCO and reference modulation
(synthesizer low frequency port) lines. Compensation algorithm is critical to the operation of
signalling schemes that have very low frequency components (e.g. DPL) and could result in
distorted waveforms if improperly adjusted. The compensation value needs to be set at 7
frequencies across the frequency range.
Note: The step size change for step 8 is approximately 2.5% softpot value.
The transmit deviation limit softpot sets the maximum deviation of the carrier. The deviation value
needs to be set at 7 frequencies across the frequency range.
1.8 RSSI
1. Use test box (RTX4005) and set the SW1 switch to SPEAKER.
2. From the Service menu, select Receiver Alignment.
3. Select RSSI to open the RSSI tuning window. The screen will indicate the receive test
frequency to be used.
4. Set the RF test generator to the receive test frequency, and set the RF level to the value
indicated for RSSI Level 0, modulated with 1 kHz tone at 60 % deviation. The 1 kHz tone must
be audible to make sure the radio is receiving.
5. Press Program to store the softpot value for RSSI Level 0.
6. Repeat steps 4 - 5 for the remaining RSSI levels.
7. Press Cancel to close the window.
The MPT1327 Deviation Softpot is used to tune the FFSK signalling deviation. Tuning is performed
at one frequency. The radio generates an alternating bit pattern for tuning. Values for others
frequencies are calculated by the radio software.
The DTMF Deviation Softpot is used to tune the DTMF signalling deviation. Tuning is performed at
one frequency. The radio generates a DTMF signal for tuning. Values for other frequencies are
calculated by the radio software.
Chapter 6C.3
Theory of Operation
Table of Contents
Paragraph Page
1.0 Overview..................................................................................................... 1
4.0 Controller.................................................................................................... 8
4.1 Functions ..................................................................................................... 9
4.2 Normal Operation ........................................................................................ 9
4.3 Clock Synthesizer ........................................................................................ 9
4.4 Bus Operation.............................................................................................. 9
4.5 RAM............................................................................................................. 9
4.6 EEPROM ................................................................................................... 10
4.7 SPI Interface .............................................................................................. 10
4.8 LED Control ............................................................................................... 10
4.9 Audio & Data Circuitry ............................................................................... 10
4.10 External PTT Sense Circuits...................................................................... 11
4.11 MIC Amplifier ............................................................................................. 11
4.12 TX Data Circuits......................................................................................... 11
4.13 Sub-Audible Data (PL/DPL)....................................................................... 11
4.14 High-Speed Data ....................................................................................... 12
4.15 DTMF Data ................................................................................................ 12
4.16 MDC Data .................................................................................................. 12
4.17 RX Audio Processing and Digital Volume Control ..................................... 12
Paragraph Page
4.18 Audio Power Amplifier ............................................................................... 13
4.19 Audio PA Muting and Output Protection .................................................... 13
4.20 Receive Data Circuits ................................................................................ 13
4.21 Alert Tone Circuits ..................................................................................... 13
Figure
3.1 RF Block Diagram.................................................................................................................1
3.2 Receiver Block Diagram .......................................................................................................2
3.3 Transmitter Block Diagram ...................................................................................................4
3.4 Synthesizer Block Diagram...................................................................................................5
3.5 VCO Block Diagram..............................................................................................................6
3.6 Controller Block Diagram......................................................................................................8
1.0 Overview
6C.3
This section provides a detailed theory of operation for the GP600 and its components:the receiver,
the transmitter, the frequency generation circuitry, the controller and audio & data circuitry.
2.0 RF Section
A block diagram of the RF section is shown in figure 3-1. The RF section of the radio is divided into
Receiver and Transmitter functions.
Ref. Oscillator
Rx. Lo
Tx. Lo FRACT_N
VCO Mod. In
RF SYNTHESISER 28
PA Pin
Conn.
Mod.
ATTN Lock Det.
Current
Sense
Vctrl Prescalar
2.1MHz
Vref Reset Spi bus
Power
Control DAC
Circuit
Tx. MIC
Spi bus Audio Int./Ext
to AMP Mic
Rx./Tx, LED Rx. Audio
in from ASFIC
Int./Ext. Audio Pa ASFIC
Speaker
From
5V
REG. Reg. 5V
Batt.
PA Enable from
ASFIC
2.1 Receiver
The receiver of the GP600 radios consists of 4 major blocks each: the front-end module, the double
balanced mixer, the 45.1 MHz IF and the back-end IF IC.
The GP600 front-end modules consist of three blocks of circuitry each: a pre-selector, RF amplifier
and a post-selector filter. These three items are located on a receiver module PCB that stands
perpendicular to the main radio PCB.
This module is enclosed in a shield to prevent radiation into and out of the module. It also improved
the grounding of the module by soldering the module shield to the main RF Board. All filters on the
UHF modules are fixed tuned designs to eliminate the need for factory tuning and to provide wide-
band operation.
“5R” (5V)
1st RF 2nd
Bandpass Bandpass
Filter Amp Filter
“5R” (5V)
Detected Audio
1st IF 2nd
Crystal Crystal IF IC
Filter Amp Filter
The shunt coupled resonator topology yields a more symmetrical frequency response to guard
against strong out of band signals that could produce IM products.
The pre-selector filter is a 4-pole, 0.01 dB Chebyshev bandpass design implemented in a shunt
coupled resonator topology. This topology maximizes the attenuation at the worst case image
frequency for UHF band which is 90.2 MHz below the filter passband. The 3 dB bandwidth is
approximately 52 MHz. The centre of the band insertion loss is approximately 3.5 dB. The 4-pole
filter is designed to operate with a 50 ohm input termination, while the output termination is the input
impedance of the RF amplifier that follows it.
The RF amplifier, Q1, is a Motorola MMBR941 NPN device biased in a common emitter
configuration. The amp is stabilized by the shunt feedback resistor R3, and has approximately 20 dB
of gain with a noise figure of about 2.5 dB. The amplifier draws 4.9 mA of current and is supplied by
the receiver 5 volt supply (indicated as “5R” on the schematics and block diagrams).
Terminating the RF amplifier is the post-selector filter. This filter is the same as the prefilter. The filter
is designed to be terminated with the amplifier output impedance on one side, and 50 ohm on the
other.
The net gain from the receiver module is about 12.5 dB in the centre of the band and about 11.5 dB
at the band edges. The net centre of the band noise figure is approximately 5.5 dB. This is sufficient
to achieve a typical centre of the band sensitivity of 12 dBs.
The double balanced mixer is composed of the two baluns, T1 and T2, and the ring diode IC, CR2.
The mixer operates with an LO level of +6 dBm and the conversion loss is approximately 7.5 dB. The
double balanced type mixer provides excellent isolation between any two ports. And since a dBm
can operate over a large bandwidth, the same mixer can be used for UHF radios. The dBm also
provides excellent protection against receiver spurs due to non-linearizes, such as IM and Half-IF.
The received signal mixes down to the frequency of the first IF, 45.1 MHz, and enters the IF circuitry.
The Intermediate Frequency (IF) section of the portable radio consists of several sections including,
the high IF, the second LO, the second IF, and the IF IC chip. The first LO signal and the RF signal
mix to the IF frequency of 45.1 MHz, and then enters the IF portion of the radio.
The signal first enters the high IF, passes through a crystal filter, is then amplified by the IF amp, and
then passed through another crystal filter. The first crystal filter provides selectivity, second image
protection, and intermodulation protection. The amplifier provides approximately 16 dB of gain to the
signal. The signal then passes through the second crystal filter which provides further selectivity and
second image protection. The high IF has an approximate 3 dB bandwidth of 7 kHz for 20/25 kHz
models and 4 kHz for 12.5kHz models.
The filtered and amplified IF signal then mixes with the second local oscillator at 44.645 MHz. The
second LO uses an amplifier internal to the IF IC, an external crystal and some external chip parts.
The oscillator presents an approximate level of -15 dBm to the second IF mixer, internal to the IF IC.
The output of the mixing of the IF signal and the second LO produces a signal at 455kHz (second
IF). This signal is then filtered by external ceramic filters and amplified. It is then passed back to the
IF IC, sent to a phase-lock detector, and demodulated. The resulting detected audio output is then
sent to the ASFIC to recover the audio.
The IF IC also controls the squelch characteristics of the radio. With a few external parts the squelch
tail, hysteresis, attack and delay were optimized for the radio. The ASFIC allows the radio’s squelch
opening to be electronically adjusted.
2.2 Transmitter
The GP600 transmitters contain five basic circuits: a power amplifier, an antenna switch, a harmonic
filter, an antenna matching network, and a power control. Refer to the block diagram and the
schematic for more information.
The power amplifier used for transmitters is the LD-MOS module. The LD-MOS is capable of
supplying an output power at 6.8W with an input signal of 2mW and a supply voltage of 7.3V. The
power out can be varied by changing the biasing voltage at the first stage.
The antenna switch circuit consists of two PIN diodes (CR101and CR102), a pi network (C119,
L112, and part of C112), and at least one current limiting resistor R102 for UHF. In the transmit
mode, TX B+ is applied to the circuit to bias the diodes “on”. The shunt diode (CR102) shorts out the
receiver port, and the pi network, which operates as a quarter wave transmission line, transforms
the low impedance of the shunt diode to a high impedance at the input of the harmonic filter. In the
receive mode, the diodes are both off, and hence, there exists a low attenuation path between the
antenna and receiver ports.
The harmonic filter consists of part of C112, and L107, C113, L108, C114, L109, and C115. The
design of the harmonic filter for UHF is that of a Zolotarev design. This particular design is similar to
that of a Chebyshev filter except for a large amplitude first ripple (near dc). This type of filter has the
advantage that it can give greater attenuation in the stop-band for a given ripple level.
Another feature of this type of filter is that the coils tend to be smaller than with a Chebyshev design.
To optimize the performance of the transmitter and receiver into an antenna, a network is used to
match the antenna’s impedance to the harmonic filter. For UHF the network is made up of L111.
Note that, in order to measure the power out of the transmitter, one must remove the antenna and
screw in its place a special BNC-to-Phono adapter.
PTT
Power µP Serial
Ip R101 Control *Note: Connection to 50 ohms
Bus
can only be made by removing
antenna and screwing in its
Sw B+ place special BNC-to-Phono
adapter (5880166s01).
The power control circuit consists of the networks associated with U151, Q156, Q151, Q152, Q155,
and U152. The Op Amp U151A-1 and Q156, along with resistor R101, make up a current-to-voltage
amplifier whose gain is mainly dependent upon the ratio of R179 to R153. The current to the final
stage of the power module is supplied through R101 (0.1 Ohms), which provides a voltage
proportional to the current drain. This voltage is amplified and applied to the input of U151B. The
resistors at the input of U151A-1 (R151, R152, R154, and R155) keep the voltages at the inputs of
U151A-1 below its maximum allowable. These resistors are 1% tolerance parts to minimize the error
produced at the emitter of Q156 resulting from the voltage offset at the input of U151A-1.
The voltage at the other input of the summing amp, U151A-2, is supplied from two DACs contained
within U152. These DACs are controlled by the microprocessor, and provide the reference voltage
for the control loop. One of the DACs, that connected to Pin 9 of U152, provides a coarse tune
voltage, while the other provides a fine tune voltage.
Since the output of the DACs is not zero when they are set to their lowest level, resistor R169 is
provided to bias up the minus input of the summing amp to compensate for the bias resulting from
the DACs.
The error voltage at the input of U151A-2 produces a voltage at its output, which is in turn applied to
the series pass transistor, Q152, through its driver, Q151. The voltage at the collector of Q152 is
applied to the controlled stage of the power module, which for UHF is the module’s second stage.
The feedback from the collector of Q152 to the emitter of Q151 through R166 is provided to keep the
two stages stable. Likewise, the feedback from the collector of Q152 to the minus input of the
summing amp is to keep the whole control loop stable.
The purpose of Q155 and its associated circuitry is to keep the control voltage on the module below
7.0 Volts, which is the maximum allowed for the UHF module.
The purpose of R173 was originally that of providing compensation to the control loop for changes in
the supply voltage, TX B+. However, experimentation has shown that this compensation is not really
required. Also, thermistor, R170, was provided to enable the shut back of the PA in the event that it
would get too hot. This has also been shown to not be required
The supply for the synthesizer is from Regulated 5 Volts which also serves the rest of the radio. The
synthesizer in turn generates a superfiltered 5 Volts (*actually 4.65 Volts) which powers U251.
In addition to the VCO, the synthesizer must interface with the logic and ASFIC circuitry.
Programming for the synthesizer is accomplished through the data, clock, and chip enable lines
(pins 1, 2, and 35) from the microprocessor, U709. A serial stream of 98 bits is sent whenever the
synthesizer is programmed. A 5 volt dc signal from pin 2 indicates to the microprocessor that the
synthesizer is locked while unlock is indicated by a low voltage on this pin. Transmit modulation from
the ASFIC is applied to pin 8 of U201. Internally the audio is digitized by the Fractional-N and
applied to the loop divider to provide the low-port modulation. The audio is also run through an
internal attenuator for modulation balancing purposes before being outputted at pin 28 to the VCO. A
2.1 MHz clock for the AFIC is generated by the Fractional-N and is routed to pin 9 where it is filtered
and attenuated from 2.5 Volts to approximately 2 Volts.
3.1 Synthesizer
The Fractional-N synthesizer uses a 16.8 MHz crystal (Y201) to provide the reference frequency for
the system. The other reference oscillator components external to the IC are C205, C206, R207,
and CR203. The 16.8 MHz signal is divided down signal from the VCO. The loop filter, comprised of
R201, R202, R205, C201, C214, C215, and C216, provides the necessary d.c. steering voltage for
the VCO as well as filtering of spurious signals from the phase detector.
Data (5) 5
(U201) 2 Lock Det (to µP U709)
Clock (6) 6 FRACTIONAL_N
SYNTHESISER 11 Mod out (to ASFIC U701)
Cex (7) 7
28 Mod out (to VCO modulation)
Mod In (8) 8
Reg 5V 12,19,22,23,3
lout
GND (4,21,13,30) 4,21,13,30 29 2-Pole
Prescalar In ladapt Loop Filter
20 31
Crystal 1
14
Crystal 2 AUX3 Steering line
Reference
15 TRB 5
Oscillator Voltage
cp bias 1 1
27 Controlled
Filtered 5V Oscillator
26 18
cp bias 2 (U251)
32
VCP 10 9 16 23 4 2
Rx injection
Voltage V-mult 1 Warp
Multiplier V-mult 2 Tx injection
For achieving fast locking of the synthesizer, an internal adapt charge pump provides higher current
capability at pin 31 than when in the normal steady-state mode. Both the normal and adapt charge
pumps receive their supply from the voltage multiplier which is made up of C202, C203, C204,
C231, CR201, and CR202. By combining two 5 Volt square waves which are 180 out-of-phase along
with Regulated 5 Volts, a supply of approximately 12.6 Volts is available at pin 32 for the charge
pumps. The current for the normal mode charge pumps is set by R203. The pre-scaler for the loop is
internal to U201 with the value determined by the frequency band of operation.
3.2 VCO
The VCO (U251) in conjunction with the Fractional-N synthesizer (U201) generates rf in both the
receive and the transmit modes of operation. The TRB line (U251 pin 5) determines which oscillator
and buffer will be enabled. A sample of the rf signal from the enabled oscillator is routed from U251
pin 23, through a low pass filter, to the pre-scaler input (U201 pin 20). After frequency comparison in
the synthesizer, a resultant CONTROL VOLTAGE is received at the VCO. This voltage is a DC
voltage between 3 and 10 volts when the PLL is locked on frequency.
Lo Rf
Injection Low 10,11 Rx
Pass 2 Rx Rx Tank
Filter Buffer Osc Control
Voltage
Tx Rf
Injection Low 4 Tx
Tx Tx 15,16
Pass Tank
Attenuator Filter Buffer Osc
Filter
Audio
Tx/Rx/BS 5 Tx VCO In
Prescalar Switching TRB Mod
Buffer Network
Low
Prescalar RF out Pass Pre-In (U201 pin 20)
Filter
In the receive mode, U251 pin 5 is grounded. This activates the receive VCO by enabling the receive
oscillator and the receive buffer of U251. The rf signal at U251 pin 2 is run through a low pass filter.
The rf signal after the low pass filter is the LO RF INJECTION and it is applied to the first mixer at
T2.
During the transmit condition, PTT depressed, five volts is applied to U251 pin 5. This activates the
transmit VCO by enabling the transmit oscillator and the transmit buffer of U251. The rf signal at
U251 pin 4 is run through a low pass filter and an attenuator to give the correct drive level to the
input of the PA module (U101 pin 1). This rf signal is the TX RF INJECTION. Also in transmit mode,
the audio signal to be frequency modulated onto the carrier is received by the transmit VCO
modulation circuitry at AUDIO IN.
When a high impedance is applied to U251 pin 5, the VCO is operating in BATTERY SAVER mode.
In this case, both the receive and transmit oscillators as well as the receive, transmit, and pre-scaler
buffer are turned off. In the Fractional-N, the battery saver mode places the A/D and the modulation
attenuator in the off state. This mode is used to reduce current drain on the radio.
4.0 Controller
The GP600 controller is an open architecture which consists of:
■ U709, Motorola 68HC11K1 microprocessor
■ U701, Audio Signalling Filter Integrated Circuit, ASFIC
■ U703, 1Kbyte EEPROM
■ U705, 128/256Kbyte OTP/FLASH ROM
■ U706, 8/32Kbyte Static RAM
■ U707, LCD Display Driver and
■ U704, 5V Voltage Regulator
U709, U703, U705, U706 and U707 are powered by U704. U701 is powered from a 5V Regulator
(U708) on Radio Module. In addition to the external memory devices, U709 has 768 bytes of RAM
and 640 bytes of EEPROM.
Reset
Rx. Filter
Σ
2.1 Vol
Micro- MHz & De-emp
28 Attn Rx.
processor
Pin Sq. Audio
Conn. Out LCD
Attn
In
Data, Address
7.9488 and Control
MHz Clk
Keypad
Lock EE-
Detect PROM
Low Batt.
Monitor ROM/ RAM
SPI Bus FLASH
Vol
Sense
LED
5V From
5V Reg. Batt.
Push Channel
Button Switch
Reset
4.1 Functions
The microprocessor has two basic functions: interfacing with the outside world and controlling the
internal workings of the radio. The microprocessor interfaces directly with the keypad, side buttons,
PTT, rotary switch, battery low indicator, EXT PTT and volume sense. The microprocessor
constantly monitors these inputs and interprets any changes into commands that control the rest of
the radio. Some control functions it performs include loading the synthesizer with the desired RF
frequency, turning the RF PA on or off, enabling and disabling audio and data paths and generating
tones. Operations and operating conditions within the radio are interpreted by the microprocessor
and fed back to the operator as visible (the display) or audible (alert tone) indications of current
status.
The regulated 5V output from U704 powers the microprocessor (U709) and the rest of the digital IC
except ASFIC (U701). The microprocessor’s clock is generated by the ASFIC, which has a built-in
programmable clock synthesizer.
Upon power-up and assuming that the ASFIC receives a proper 2.1MHz input on U701-P38 (which
comes from the transceiver board), the ASFIC outputs a 7.9488MHz CMOS square wave (0-5Vpp
logic) on U701-P30, which connects to the EXTAL input of the microprocessor, U709-P73. The
microprocessor operates at 1/4 of this frequency, which in this case computes to 1.9872MHz. In
particular, the E clock output (U709-P72) will be a 50% duty cycle square wave at this frequency.
The microprocessor operates in expanded memory mode and executes firmware contained in OTP/
FLASH ROM, U705. The microprocessor uses a non-multiplexed address data bus, consisting data
lines D0 through D7 and address lines A0-A17. In addition, the microprocessor has integrated chip-
select logic so that external memories can be accessed without the need for external address
decoder gates. These chip-select signals are provided by U709-P28 and P29.
When the controller board is functioning normally, microprocessor’s address and data lines should
be toggling at CMOS logic levels. Specifically, the logic-high levels should be between 4.8 and 5.0V,
and the logic-low levels should be between 0 and 0.2V.
4.5 RAM
The on-chip 768 byte static RAM from U709 provides some scratch-pad memory, with the bulk of it
coming from the external 8 or 32Kbyte SRAM, U706. External SRAM accesses are indicated by the
U709-P28. Normally SRAM is accessed less often than the OTP/FLASH ROM, U705; i.e. the
number of transitions per second on U705 chip select (pin 30) should be 5-15 times higher than
those on U706 pin 20.
4.6 EEPROM
The radio codeplug storage is provided by U709 internal 640 byte EEPROM, with an additional 1K
byte of memory space provided by external EEPROM, U703. There are three basic types of
codeplug information: information on the trunked system on which the radio is authorized to operate;
information on the conventional system, which is either of the repeater or talk-around type on which
the radio is authorized to operate, and information on the configuration and tuning of the radio itself.
Tuning information is normally located in the internal EEPROM of U709.
The microprocessor communicates to several ICs and modules through a dedicated on-chip serial-
peripheral-interface (SPI) port which consists of transmit data line MOSI (U709-P1), receive data
line MISO (U709-P80), and clock line SCK (U709-P2). In addition, each IC that can be accessed by
the microprocessor using the SPI has a read/write select line associated with it. The ICs or circuits
and their associated select lines are:
■ EEPROM (U703) with select line U709-P3
■ ASFIC (U701) with select line U709-P34
■ LCD Driver (U707) with select line U709-P23
■ SRAM (U706) and OTP/FLASH ROM (U705) with select line U709-P33
■ Transceiver board Synthesizer (U201) with select line U709-P35
■ Transceiver board DAC IC (U152) with select line U709-P26
The LCD Driver uses the master out/slave in (MOSI) line to send data to the display driver IC, and
the master in/slave out (MISO) line to send data back to the microprocessor (U709). Note, however,
that the keypad (or any other SPI device) can never initiate display data; the microprocessor is at all
times the SPI master device. Thus the MOSI line and MISO line are always in the master
configuration.
The bi-colour LED on the top of the radio is indirectly activated by SPI of U709 via the DAC IC
(U152) on Transceiver Board. When either input to the dual NPN transistor (U410) is at logic high,
the corresponding output pin (pin 6 for the green LED, pin 3 for the red) should be at approximately
4.3 Vdc. Note that it is possible to have both LED outputs on simultaneously, in which case the LED
emits a yellow/orange light.
The transmit and receive audio paths are disabled in the standby mode and selectively enabled by
the microprocessor when the radio transmits or receives a signal. Also, there are minor differences
in the functioning of both paths depending on whether an internal or external (accessory)
microphone/speaker is being used. The radio constantly monitors the received data path for control-
channel data in trunking operation or sub-audible data in conventional operation.
On connecting an external MIC through connector J3, external PTT sense transistor Q408 switches
“ON” when the external PTT switch is closed. Q408 collector voltage is monitored by U709-P4.
When collector voltage is logic “HIGH”, the microprocessor configures the radio for transmit mode.
In PTT equipped accessories, the PTT switch is series connected with the external MIC element.
MIC audio from internal MIC MK401 is coupled through C429, L404, J3 and L403 to the MIC buffer
circuit U405-1. External MIC plug insertion mechanically disconnects the internal MIC. External MIC
audio is coupled through L403 to the MIC buffer input. The unity gain buffer will route the MIC audio
into MIC IN (U701-P7) through flex and connectors J200 and J700. Inside the ASFIC, the MIC audio
is amplified, filtered to eliminate components outside the 300-3000Hz voice band, pre-emphasized,
and then limited. The limited MIC audio is then routed through a summer, which is used to add in PL
or DPL sub-audio band modulation, and then to a splatter filter to eliminate high frequency spectral
components generated by the limiter. After the splatter filter, the audio is routed to the 8 bit
modulation attenuators, which are tuned in the factory of the field to set the proper amount of FM
deviation. The TX audio emerges from the ASFIC at U701-P55 is dc coupled and applied through
flex and connectors J700 and J200 to the synthesizer (U201) pin 8.
There are four major types of transmit data: sub-audible data (PL/DPL/Connect Tone) that gets
summed with voice, high speed data for trunking control channel communication, DTMF data for
telephone communication in trunked and conventional systems, and MDC data for use in Motorola
proprietary MDC systems. The deviation levels of the latter three types are tuned by a 5-bit digital
attenuation inside the ASFIC. For each data type and each band split, there is a distinct set of tuning
values that are programmed into the ASFIC before the data is generated and transmitted.
Sub-audible data is composed of low-frequency PL and DPL waveforms for conventional operation
and connect tones for trunked voice channel operation. (The trunking connect tone is simply a PL
sine wave at a higher deviation level than PL in a conventional system). Although it is referred to as
“sub-audible data”, the actual frequency spectrum of these waveforms may be as high as 250Hz,
which is audible to the human ear. However, the radio receiver filters out any audio below 300Hz, so
these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U701 at any one time. The process is as
follows: using the SPI, the microprocessor programs the ASFIC (U701) to set up the proper low-
speed data deviation and select the PL or DPL filters. The microprocessor then generates a square
wave from U705-P6 which strobes the ASFIC PL_CLK (U701-P20). For encode input at twelve
times the desired data rate. (For example, for a PL frequency of 103Hz, the frequency of the square
wave at U701-P20 would be a 1236Hz). This derives a tone generator inside U701, which generates
a staircase approximation to a PL sine wave or DPL data pattern. This internal waveform is then low-
pass filtered and summed with voice or data. The resulting summed waveform then appears on
U701-P55 (VCO_ATN), where it is sent to the transceiver board as previously described for transmit
audio.
High-speed data refers to the 3600 baud data waveforms (ISWS AND OSWS) used in a trunking
system for high-speed communication between the radio and the central controller. To generate an
ISW, the microprocessor (U709) first programs the ASFIC (U701) to the proper filter and gain
settings. It then begins strobing U701-P54 (Trunking Clock In) with a square wave (from U709-P5) at
the same baud rate as the data. The output waveform from 5-3-2 State Encoder of U701 is then fed
to the post-limiter summer block and then the splatter filter. From that point it is routed through the
mode attenuator and then out of the ASFIC to the transceiver board via VCO_ATN (U701-P55).
DTMF data is a dual-tone waveform used during phone interconnect operation. They are divided into
low-group and high-group tones. The high-group tone is generated by U709-P5 strobing U701-P54
at six times the tone frequency for tones less than 1440Hz, or twice the frequency for tones greater
than 1440Hz. The low-group tone is generated by U709-P7 strobing U701-P53 (DTMF Clock) at six
times the tone frequency. Inside U701 the low-group and high-group tones are summed (with the
amplitude of the high-group tone being approximately 2dB greater than that of the low-group tone)
and then pre-emphasized before being routed to the summer and splatter filter. The DTMF
waveform then follows the same path as was described for high speed data.
The MDC signal follows exactly the same path as the DTMF high-group tone. MDC data utilizes
MSK modulation, in which a logic zero is represented by one cycle of a 1200Hz sine wave, and a
logic one is 1.5 cycles of an 1800Hz sine wave. To generate the data, the microprocessor (U709)
first programs the ASFIC (U701) to the proper filter and gain settings. It then begins strobing U701-
P54 with a square wave (from U709-P5) at the same baud rate as the data. The output waveform
from U701 is fed to the post-limiter summer block and then the splatter filter. From that point it is
routed through the mode attenuator and then out of ASFIC to the transceiver board via VCO_ATN
(U701-P55).
The radio’s RF circuit are constantly producing an output at the Detected Audio line. Whenever the
radio is in trunked standby mode, it is processing data from the control channel; while in
conventional standby mode, it is always monitoring the squelch line and/or sub-audible data. The
detected audio from the transceiver board enters the controller board at connector J700 pin 4. In
addition to the detected audio line, the transceiver board also provides a squelch noise from U51-
P30 into the ASFIC squelch-detect circuitry via U701-P56. When the microprocessor is satisfied that
it has received the proper data or signal type for unsquelching, it sets up the receive audio path and
sends data to U701 to do the same within.
The detected audio will enter U701 through RX IN (pin 57) and PL IN (pin 63) for further processing.
Inside the IC, the signal first passes through a low-pass filter to remove any frequency components
above 3000Hz and then a high-pass filter to strip off any sub-audible data below 300Hz. Next, the
recovered audio passes through a de-emphasis filter to reduce the effects of FM noise. Finally, the
IC amplifies the audio and passes it through the 8-bit programmable attenuator whose level is set
depending on the value of the volume control. The microprocessor (U709) programs the value of the
8-bit attenuator in accordance with the voltage sensed at the volume potentiometer, which is
connected to U709-P48. This pin is one of the eight channels of U709’s 8 bit A/D convertor. After
passing through the 8-bit digital attenuator, the audio goes to a buffer amplifier and then exits at
U701-P66, where it is routed to the Audio power amplifier circuit in the transceiver board.
Resistor R466 sets the input impedance to U409-P2 of the audio power amp. The audio PA circuit is
a bridged-tied-load (BTL) configuration with fixed gain of 40dB, developing 500mW (rated audio
power) output at less than 5% harmonic distortion into the 16 ohm internal speaker LS401 with
nominal 7.5Vdc battery supply. Maximum audio power output is greater than 1.2 watts.
PNP transistor Q410, the audio PA power switch, driven by NPN darlington transistor Q411, the PA
mute amp, controls Vcc supply to Audio PA U409-P1. U701-P5 is connected to Q411 base,
controlling audio PA Vcc supply. Resistors R489 and R490, PNP transistor Q412 and the current
sense circuit monitor current supplied to audio PA U409-P1. Worst case audio PA current (at 9Vdc
battery voltage, maximum volume and full system deviation) does not exceed 450mA at the nominal
16 ohm load. Resistor R488 and capacitor C461 provide an RC time delay for U405-2, a monostable
multivibrator circuit. A 2.5Vdc reference voltage is fed to U405-2-P6. On radio power-up, and in
normal operation U405-P7 monostable multivibrator output is logic “LO” pulling Q411 emitter to Vee
with the audio PA controlled by U701-P5. Should U409-P5 and/or U409-P8 become shorted to each
other or to the ground (Vee), current consumption exceeds 500 mA (approximately) and Q412
collector. When U405-2-P5 voltage rises higher than the U405-2-P6 reference voltage (rise time is
less than 50 usec), U405-2 is triggered and U405-2-P7 dc output voltage is switched to 4Vdc,
effectively biasing Q411 into cut-off and turning off the audio PA power switch Q410. U405-2-P7
remains in this state for 15 msec, then reset to logic “LO” state. Average power dissipation in the
audio PA circuit components is helped to a low level by the low duty cycle (less than 0.3%) of the
audio PA protection circuit. The cycle repeats until the audio PA output short is removed.
The ASFIC (U701) decodes all receive data, which includes PL, DPL, low-speed trunking, MDC,
and high-speed trunking data. The “decode” process for each data type typically involves low pass
or band pass filtering, signal amplification, and then routing the signal to a comparator, which
outputs a logic zero or one signal. The detected audio from the transceiver board is routed to U701-
P57 and P63 through coupling cap C435. Inside U701, the data is filtered according to the data type
(HS data or LS data, then hard-limited to a 0-5V digital level. The high-speed limited data output
(MDC and trunking high-speed) appears at U701-P51, where it connects to U709-P11. The low
speed limited data output (PL, DPL and trunking low-speed) appears at U701-P4, where it connects
to U709-P10.
When the microprocessor needs to give the operator feedback (for a good key press or for a bad key
press) or radio status (trunked system busy, low battery condition, phone call, circuit failures), it
sends an alert tone to the speaker. It does so by sending data to U701, which sets up the audio path
to the speaker for alert tones. The alert tone itself can be generated in one of two ways: internally by
the ASFIC, or externally using the microprocessor and the ASFIC. The allowable internal alert tones
are 300, 900 and 1800Hz. For external alert tones, the microprocessor can generate any tone within
the 100-3000Hz audio band. This is accomplished by the microprocessor toggling the output line
U709-P7, which is also the same line used to generate low-group DTMF data. Inside the ASFIC, this
signal is routed to the external input of the alert tone generator. The output of the generator is
summed into the audio chain just after the RX audio de-emphasis block. The tone is then amplified
and filtered before passing through the 8-bit digital volume attenuator. The tone exits at U701-P66,
then is routed to the audio PA circuitry in the transceiver board.
Chapter 6C.4
PCB/Schematic Diagrams and Parts Lists
Table of Contents
Description Page
UHF (438-470MHz) Diagrams and Parts Lists
Controller PCB Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Controller Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
RF PCB Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RF Overall Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RF (Receiver Module) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RF (Synthesizer) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RF (Transmitter Module) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RX-FE Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DS702 DS701
DS704 DS703
J701 1
34
32 17
15 14 33 16
R799
C721
S01 S02 S03 S04
R781 C745
U706 U707
R755 C787 C746
R700 C700
VR707
48 1
49 64 TP7
C754
R790
C781
R711
R713
C744
CR707 S13 S14 S15 S16
Q704 R710
28 1
C719
C758
R787
Q703 16 Q700
Q705 17 C720
4 R763 C777 C786
5 U705
C718
R712
R753
U703
C716
C717
8 1 TP4 32 1
C711 S07 S08 S09 S10
R726
80 61 C407 H8 B8
R403
1 60 6 4 J7 A7
U704
1 3 R786
U701
C763
C406 C765
R725
R764
R751
C707
C737 C708
C731
C743
20 41 C769
21 C733 R705 C710
40
28
C741
C732
2
C747
C435
C742
R468
Q702
R752
J700
1 27
Controller Board
PCB No. 8404599J03
Controller Board-
8404599J03
Diode, Transistor:
Integrated Circuit:
3 4 3 4 5
C228
C212
C227
C233 Y201T L253 4 R256 R262 C33 L53
L11 Y51B
R252
C282
L204 2 Q251 5 4 CF51 CF52 6 R460 3
3 C283
C56
C78
C30
T2 C28 L55 1 2
C455
CR203 1 1 2
C258
R255 2
R253
C224 L203
L255 C272 1 2 3
Y51A
R54
C232 C205
C268 L9 C58
C59
C29
L258 8 30 5 1
R254 L260 5 5
C206
R207
C217 C279 C267
C801
R55
CR255 C55
C281 CR2 U51
C219
L262 J6
R205
C209
L52
C75
C278
C215
L201 C257 R258 C266
4 C73
1
C126 C259
C286 C125 L258 L259 3 2 1 R51 C79 12 23
C204
Y53
C265 L261 SW401
C74
R64
CR105 T1
C269
4
C51
L51 L58 C68 2
C63
CL5 C271
C270 4 5
CR106
C66 C69 R57
C67
CR103
CR104
R105
R106 U252 8 1
C127 8 5
C418
R105
1
C419
R447 6 5 4 3 2
C497
C498
C116
C425
U708
L111
Q408 1 4
C424
R448
C421 J1
C802 R452 R169
C452 R503
R451
U101 1 2
4 1
C464
L403 R170 J2 3
4 1 C800
C461
U405
R173
L710 U409 1 2 3 4 C123 5 6 7 4
L404
R702
C499
R488
5 5 8 C429
8
C409
C124
L113
C430 C102 C107
PB403 PB401 PB402 RF Board
CL4 CL3 CL2 Component Side
SH101 SH100
R804
R801
R803
R802
C57
CR405
VR704 L54
C228
C454
C208
C789
R212
C207
C275
C236
C273 C210
C211
CR251
CR51 C456 C251 C254
R60
R263
R409
R411
C70
JU51
R52
R410
C457
R415
C476
R204
C82
L717 17 21 C223
C284
R53 C77 24 17
R203 R202
R408
16 22 L251 L254 25 16 C472
R68
R497
C61
C235
C60
C34
R414
R67
Q51
24 R261
C13
R424
C474 L10 U251 1 U201 C202 R417
C83
C256 C473
R260 C466
C87 C85 CR201
C237
DS401
C263
U410 R66 10 4 L256 L267 C216 32 9 C467
C64
R5 C468
R416
3 4
C86
R413
C203
R58 9 1 8
5 R201 C222
R264
C238
R412
C261
CR253
C221
C220
C80
C260
R257
C264
L257
C475 C436
C276 1
C459
C36 LOCKDET
R193
C158
Q153
C410
C230 R216
R158 LS
C193 C151
8 5 R167
R6 22 24 1 4 C194 SYNLE
J200
R494
L406 R159 C199 R168
R160
C159
U151A
C154
C480
R450
R449
C426
C118
C437
1 CR102 C120 1 4
C153 R157
U152 R489
2 C101 SRCLOCK
C105
C469
J3 C163 C152 17 9
28
C111 Q154
R469
Q410
C115
R490
R155
L112 R101
R507
R172
R171
L106
C428
R466 C479
R153
C113
R156
CR101
C128
Q155
L109 Q156
C481
R174
R467
C441
C103 CL9
5 C166 R151
C122
R496
R175
6
C164
L108 L107
C442
C114
RF Board
C110
C108
C109
C106
C162
R152
L103 C104 4 3 2 1 J5
SB+ GND RESET
Solder Side
RF Board
PCB No. 8480473Z01
BATTER
GRAPHICS ONLY
0180702489 BATT FILTER BOARD
* CONNECTION VIA CHASSIS
R497 SCI
SCI
CONN_BPLUS
470 refer to R460 C3
SW402-1 39
L710 SW_ONOFF
J?
5V SWB+ TXB+ EN_BIAS 5V SWB+ 5R THERMAL FUSE
F1
390nH U708 P/O VOL
C421 L1 L2 4A
REG_8PIN .47uf
8 CHG+
VOUT 1 CR405 C1 C2 C4
6 VIN
5V_TAP SENSE 2 NU 39 39
7 4
C419 5 FEEDBACK GND 3
.018uF ERROR SHUT SWB+
DOWN (SOURCE) CHG-
5V SWB+ TXB+ 5V SWB+ 5R
C418 J200
(SOURCE)
10uf CONN_89982-28
EN_BIAS SQATTNIN 5V 1 SWB+
2
GND
DETAUDIO 3 SQATTNIN
TRANSMITTER RX_IN RX_IN RECEIVER 4 DETAUDIO
RSSI 5 RSSI
CHAIN CHAIN 6
RX_INJ ADAPT
ADAPT 7 LOCKDET
8 SYNLE
9 MODIN
CLK RESET DACLETX_INJ 10
SB1
11 SB2
5V 12 ROT1
13 ROT2
(SOURCE FROM ASFIC) 14
2.5V
15 5V
16 MICIN
17 SRDATA
RX_INJ 5V 18 RXAUDIO
LOCKDET 19 GCB1
C497 20 VOL
CLK RESET DACLE NU 21
SYNLE R447 PTT
22 EXTPTTSENSE
SB1 SB2 2.5V 5V 5V 23
MODIN NU SCI
TX_INJ C425 VOLUME 24 SRCLOCK
C424 NU 25
DATA SRDATA PORT DACLE
SYNTHESIZER 26
L717 VOL SENSE 27
RESET
GND
CLK SRCLK NU .39uH 28
C480 R460-2 XX 2.1MHZ
XX
NU C789 VR704
R448 R450
2.1 MHZ 2.1 MHZ 100pf 6.8V
SW_ONOFF XX
0 NU
U405-1 PTT DATA CLK DACLE RESET 2.1MHZ
OPAMP_4PIN N2 C802
SWB+ 1 2 NU
C426 C427 L403
R507 R489 R490 3 J3
1000 2.7 2.7 N1
4 N3 MMBT3906 390nH EXT_MIC-SPKR
1/8W 1/8W SWB+ .22uf .22uf C481 S2
2 N4 R449 C428 R451 150pf
100K 150pf R494 3 Q408 2200 S3
EXT MIC
1 100K
Q412 2 MIC FILTER 1 S1
MMBT3906 C438
3 C461 4.7uf 2.5V C410 J5
1 3 C409 VR401 C436
2 R452 150pf CONN_4PIN
C464 180K 150pf 10V 150pf 1 MK401
.1uf 3 Q410 R503
5V INT MIC
R488 .1uf M41L03 1 2
8 N4 330 C452
220K Q411 C498 L404
5N3 7N1 R496 2 4.7uf
MMBTA13 150pf 390nH
330
SHIELDS AND BUTTERFLY CLIPS 6N2 U405-2
OPAMP_4PIN
C429
2.5V 4700pf 3
R702 LS401
L405 EN_BIAS 2000 INT SPKR
4 16 ohm
1 1 1 1 1 1 1 1 1 390nH
AUDIO AMPLIFIER C499 C430 C442
CL CL CL CL CL CL CL CL CL R467 150pf NU J4
U409 150pf EXT_MIC-SPKR
10 S2
CL11 CL9 CL8 CL7 CL6 CL5 CL4 CL3 CL2 TDA7052
1 5
Vp OUTPUT1 C441 S3
.1uf EXT SPKR
C437 R469 2 8 L406
INPUT OUTPUT2 S1
GND0
GND1
1800 390nH
NC0
NC1
.47uf C469 C443
SH101 SH100 SH103 SH104 SH105 47pf R466 C479 1000pf
4700 470pf 3 6 4 7
SH1 SH1 SH1 SH1 SH1
NC NC
1 1 1 1 1
5V
ROT1
R801 R802 R803 ROT2
C801 10K 10K R409
NU 10K R804
SW_FREQ_16POS 10K 43K
SB1 SB2 PTT SW401 8 R408
PC3
PC2 4
C466 C467 2 20K
C468 PC1 R411
PC0 1
C0 C1
150pf 150pf 150pf 43K
C475 C459 C474 C456 C454 C457 C455 R410
C460
150pf 150pf 150pf 150pf .01uf .01uf .01uf .01uf
R424 R416 R417 20K
100 100 100 C476
150pf R414 R415
C473 C472 510K 510K
150pf 150pf
SCHEMATIC DIAGRAM OF OVERALL CIRCUITS
RF Schematic Diagram
.01uf NU
2
1,2 R51 L51 Y51A
FRONT END RECEIVER MODULE R5 1 T2
3 4 45.1MHZ
5V C53
U252 5,6 .15uH INSTPAR
160 2 22pf 1 3
6 8 XFMR C30
C13 C51
MODRF_6PIN 150pf VOLT 150pf
1 5 L53 C77
CR2-1 51
1 2 3 4 5 6 1.2uH 3pf
R6 T1 L11 L9 L10 82pf 2
4 3
CR2-2 5R
RX_IN VOLT 27nH 15nH .15uH
10 C36 2
XFMR C28 C29
4.3pf 5 7 7,8 C33
C119 10pf 12pf
5 1 1.5pf
NU
4
3,4
RX_INJ
2.5VDC
2.5VDC
2000
R52
33K C61
2
C82 CF51 2 3 4 CF52
R67
2.9VDC JU51 1500pf INSTPAR
3.8VDC
CR51 INSTPAR
4 3 36 35 33 32
6800
2ND_IF_OUT
.1uf
IF_AMP_IN
IF_AMP_OUT
FIL_CAP_OUT
LIM_IN
FIL_CAP_IN
C56 NU
3 JUMPER
Q51 20pf C59
C78 0.75VDC 6 PPC_AMP_IN
C54 MMBR941 1INSTPAR3
0.7VDC
1
C57 L54 0 L55 C58 .1uf 1.5VDC 5
15pf NPN NU NU Y51B INSTPAR NU PPC_AMP_OUT 31 2.0VDC
R53 2
12K 45.1MHZ DEMOD_OUT
2
C60
.1uf .47uf
8 IF_IN C62
AUDIO_IN 29
3.0VDC 1
GND 2.4VDC
13 28 2.5VDC
A+_B+ DETAUDIO
SWB+ 14 DRIVE AUDIO_OUT
C80
C75 4.4VDC 7 LO_IN 23 2.4VDC NU
SQ_LIM_OUT
C73 3.9pf
2 2.6VDC 10 C63
OSC_OUT
20 2.4VDC
R66 13pf C74 R64 3.4VDC 9
U51 SQ_ATTEN_IN
45MHz OSC_FB IFIC
820 Y53 36pf 5600 51pf
27 22
44.645 5R T_R ADAPT ADAPT
1
2 5.0VDC(UNSQ)
VCC1 0VDC(SQ)
C79 15 C87
SQ_OUT 5.0VDC(UNSQ)
16pf 12 150pf
VCC2 0VDC(SQ)
2.4VDC
17 18
5V VCC3 FAST_SQ
L58
INSTPAR C71 C70 34
PCC_2_SU
RSSI_OUT
VCC4 R68
SQ_TAIL
10uf .1uf SQ_NOISE 30 SQATTNIN
FILTER
C81
SQ_IN
3.7VDC 1000
25
ICO
RSSI_OUT_2
C83 C85 C86 R60
.1uf 16 19 11 26 24 150pf 150pf 150pf 130K
3-5VDC
RSSI
R58
3-5VDC C66 13K C64
C67 .1uf
4.7uf 150pf
C69 C68 R57
3.3uf .039uf 130K
SCHEMATIC DIAGRAM OF RECEIVER CHAIN
0.5-3.0VDC
0.65VDC
PMLE4073A UHF (438-470 MHz) 12.5 KHZ RF BOARD
GEPD5551
R256
RX_INJ
1500 C283
C282 3
470pf
Q251 150pf
1 NPN R262
MMBR941
2 120
R252
10K
R255
11K C260
C272 R257 C280 C231
5.6pf C261 5.6pf
5.1pf C263 C285 R264 C238 C237 5V
30K CR253 150pf 100
C267 R258 150pf 1.8pf .01uf 100pf 100pf C202
R260 L256 C262 C264
100 C204 L286 5.0VDC (LOCKED)
150pf C266 FILT5V 470nH .01uf 0VDC (UNLOCKED)
150pf L257 220 8.2pf 6.8pf
C268 C278 1000nH
470nH L267 4.7uf CR202 CR201
.22uf L258 56nH C222 C286
L259 C203 C228 LOCKD
1000pf 34.4nH NU C219
6
9
390nH L262 L255 .01uf 150pf
L260 150pf
VCC
NC1
NC2
E1B
E1A
LA1
FILT5V 1000pf 12.6VDC
27nH 15nH 390nH SYNLE
2 11 C256 L201
RX B1 R205 3-10VDC
C269 C259 390nH
L261
32
V_MULT_1 10
4 12 150pf 3300 C216 R202
V_MULT_2 9
7
TX BI1 C265 150pf C215
TX_INJ .1uf 2200
8.2nH 5600pf
LOCK
VCP
CEX
150pf .1uf 3-10VDC 29
C271 C270 22 U251 13 L254 SL
I_OUT
NU NU NC4 VC 31 I_ADAPT 8 2.5VDC
C253 C255 47nH R201 C201 MOD_IN MODIN
VCOBIC 82 NU T1
24 14 R261 4 11 2.5VDC R206 R215
NC5 BI2 30pf 9.1pf 1 GND FREQ_OUT 2.1MHZ
220 C284
L251 1pf L253 CR251 3-10VDC 13 12 2200 1000
1 15 C279 390nH C254 27.5nH C214 GND U201 DC_5V_REF_OSC 5V C223
R216
C218
GND2 B2 .22uf 1uf 24K
GND1
TRB
NC3
GND XTAL_1
E2B
E2A
LA2
PS
21
23
20
18
17
16
10K 1.2VDC
5
2.5VDC 1 16
AUX_3 WARP 2
DC_5V_REF_DIV
C275 C252 390nH
DC_5V_PRESC
20 PRE_IN 17 C232 Y201T
5.6pf C257 R253 C258 C235 10.0uf 4.65VDC R211 C206 R207
SUP_F_OUT
SUP_CAP 16.8MHz
DC_5V_SRL
CR255 47pf NU
SRL_CLK
150pf 1500 NU .018uf 2200
SRL_DATA
47K
27 CP_BIAS1
CP_BIAS2
19 SUP_F_IN
150pf R263 1
TEST_1
TEST_2
39K L252 C207 C233
R251 0.7VDC(R)
GND
390nH C251 4.7uf
1.5VDC
27K C281 4.2VDC(T)
5.6pf
150pf FILT5V 6.8pf
26
18
21
23
22
24
25
6
5
FILT5V
3
CR203
C209 NC NC
C273 150pf
150pf
C224
L204 150pf
C211 .22uf
12nH
C227 C226 4.7uf C229
C276 NU R212
11pf L203 NU R203 R204
.01uf 390nH 75K 75K
(SOURCE) 4.65VDC
FILT5V
C210 C212 C236
4.7uf 1000pf 150pf
C208
4.7uf C220 C221 SCHEMATIC DIAGRAM OF SYNTHESIZER
150pf 150pf
PMLE4073A UHF (438-470 MHz) 12.5 KHZ RF BOARD
5V CLK DATA
GEPD5550
C120 CR102
RX_IN
C109
150pf C118 33pf TXB+
R102
47pf 330
L102 C106
(SOURCE) C111 L104 C107 C108
C117 150pf BEAD .018uf .018uf
270nH
NU L105 150pf
BEAD
C105
10uf C164
5V
R101
150pf 3
0.1 R174
R153 1W C122 C124 C162 R151 Q155
SWB+ C158 C101 22 56.2K 1
NU 20pf 150pf MMBT3904
Q154 .01uf 4.7uf 1% 100K
TO U51-PIN 13,14 NPN
M41L03
C128 R175
2 3 2 6200
SWB+ SENSE HI 2
Q405 R438
1 .047uf
R161 MMBT3906 R155
3300 SENSE LO
680
56.2K
1 5R 3 1%
1
C125 R154 R152
SOURCE VDD
3 NU 100K 100K
U152 C126 4.52VDC(HI)
1% 1%
Q153 .47uf 2.00VDC(LO)
SWB+ MMBT3904 1 22 11
CLK DAC2
NPN 24 9
RESET DAC1
C199 21 3 R171 C153
150pf EN BIAS_EN .047uf
C156 16 TEMP 2 51K C152 C163 C151 R166
2 ANT_SEL 180
150pf CR106
14 8
BATT 2_POLE_V
U410 15 AUX FREQ_SW_DA 12
1 4 NPN_DUAL 150pf 150pf 150pf Q152
R162 10 R157
R_T MJD2955
120 23 DATA_IN 17 CR105 1800
SCB1 N3 N2
5 2 4 18 3 2 R167 3 2
FREQ_SW0 SCB2 SWB+
5 19 4 16K
FREQ_SW1 SCB3
6 20 U151A-1 R160 TO U51-PIN 13,14
FREQ_SW2 SCB4 N4 OPAMP_4PIN
6 3 7 R172 C193 680
FREQ_SW3 3
22K 1
VSS CR104 1 1.65VDC(HI)
Q156 N1
13 NU C165
1 NPN 3 0.75VDC(LO)
R412 R413 R193 N2 4700pf
180 MMBT3904 20K
680 6 OPAMP_4PIN
CR103 Q151
2 7 N1 1 MMBT3904
U151A-2 R158
DATA N3 5 NPN
R179 R156 R173 R170 2.31VDC(HI)
3 1
8 1.40VDC(LO) 180
C127 N4
360 3900 NU NU 2
C154 R159
2.91VDC(HI) C166 R169 NU
1.11VDC(LO) .22uf
C159 180
4 2 6800 C157 150pf
DS401 CLK RESET DACLE 150pf C800
LED_DUAL R168
.1uf 100K SCHEMATIC DIAGRAM OF TRANSMITTER CHAIN
5V .01uf
PMLE4073A UHF (438-470MHZ) 12.5KHZ RF BOARD
GEPD5552
EN_BIAS
C126 2311049A07 1.0 uF, 10%; 16V C216 2160521G37 0.1 nF, +80%/-20% , 16V
C203 2113741A45 10000 C251 2113740A21 5.6 pF, +-2.5 pF, 50V
C204 2311049J11 4.7 uF, 10%; 16V C252 2113740A21 5.6 pF, +-2.5 pF, 50V
C254 2113740A14 3.0 pF, +-2.5 pF C418 2311049J25 10 uF, 10%; 16V
C258 NU C425 NU
C260 2113740A21 5.6 pF, +-2.5 pF C427 2113743A23 0.22 uF, 10%, 16V
C265 2160521G37 0.1 uF, +80%/-20%; 16V C437 2311049A05 0.47 uF, 10%; 25V
CR405 4880107R01 silicon rectifier L111 2483035N13 coil air 24AWG 5TNS
H101 300136783 screw 2-56" X 5/16"; 2 L203 2462587N22 chip 390 nH, 10%
used
L204 2462587N42 chip 12 nH
Connector, Receptacle:
L251 2462587N22 chip 390 nH, 10%
J1 3904566J01 antenna contact
L252 2462587N22 chip 390 nH, 10%
L253 2480145S07 RF coil 1-1/2T brass core Q155 4880214G02 NPN MMBT3904
L255 2462587N22 chip 390 nH, 10% Q251 4813827A07 NPN SML SIG
MMBR941LT1
L256 2462587N61 chip 470 nH, 5%
Q405 4805128M67 NPN MMBT3906
L257 2462587N61 chip 470 nH, 5%
Q408 4805128M67 NPN MMBT3906
L258 2480145S08 RF coil 2-1/2 violet toko
Q410 4880141L03 PNP SOT23
L259 2462587N22 chip 390 nH, 10%
Q411 4805128M19 SOT-23 MMBTA13
L260 2462587N46 chip 27 nH, 5%
Q412 4805128M67 NPN MMBT3906
L261 0662057C01 0 ohm
Resistor, fixed: ohm +/-5%; 1/8W:
L262 2462587N43 chip 15 nH, 5%
R5 0662057C56 160
L267 2462587N50 chip 56 nH, 5%
R6 0662057C27 10
L268 2462587N22 chip 390 nH, 10%
R51 0662057C44 51
L286 2462587Q47 1uH
R52 0662057D12 33K
L403 2462587N22 chip 390 nH, 10%
R53 0662057D02 12K
L404 2462587N22 chip 390 nH, 10%
R54 0662057C82 2000
L405 2462587N22 chip 390 nH, 10%
R55 0662057C51 100
L406 2462587Q42 Ind chip 390 nH, 10%
R57 0662057D27 130K
L710 2462587N60 chip 390 nH, 5%
R58 0662057D03 13K
L717 2462587N60 chip 390 nH, 5%
R60 0662057D27 130K
Q152 4813822A10 PNP 60V 10A MJD R151 0660076F29 56.2K, +/-1%
2955T4
R152 0660076F01 100K
Q153 4880214G02 NPN MMBT3904
R153 0662057C35 22
Q154 4880141L03 PNP SOT23
R154 0660076F01 100K
TP3
T1
1
C03 2113740G21 Ceramic Chip 5.6 pF Q01 4813827A07 TSTR NPN SML SIG
MMBR941LT1 7Y
C04 2113740G28 Ceramic Chip 9.1 pF
Resistor, Fixed: Ohm ±5%; 1/8W
C05 2113740G23 Ceramic Chip 6.2 pF
R01 0662057C91 4700
C06 2113740G19 Ceramic Chip 4.7 pF
R02 0662057C89 3900
C07 2113740G29 Ceramic Chip 10pF ±2%
R03 0662057D03 13k
C08 2113740G16 Ceramic Chip 3.6 pF
Non-Referenced Items
C09 2113740G21 Ceramic Chip 5.6 pF
0780102S01 Leadframe
C10 2113740G32 Ceramic Chip 13 pF ±2%
0780102S01 Leadframe
C11 2113740G34 Ceramic Chip 16 pF ±2%
0780102S01 Leadframe
C12 2113740G33 Ceramic Chip 15pF ±2%
0780102S01 Leadframe
C13 2113740G30 Ceramic Chip 11 pF ±2%
2680625B02 Shield Receiver
C14 2113740A59 Ceramic Chip 150pF±30%
8480480D01 Rx Module PCB
C15 2113740G14 Ceramic Chip 3.0 pF
Appendix A
PL (CTCSS) Codes
Table of Contents
Paragraph Page
1.0 Allowable PL Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
The following PL Codes have been tested and are acceptable for programming into any transmit or
receive frequency.