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Apple Imac A1311 K74 051-8337 820-2784

This document appears to be a technical document that contains information about repairing or working on Apple notebooks. It includes sections like a system block diagram, power block diagram, list of components, and descriptions of connections and sensors related to power, temperature, fans, storage devices and other internal components of the notebook. The document contains technical specifications and is intended for an audience knowledgeable about the internal workings of Apple notebooks.

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0% found this document useful (0 votes)

667 views92 pages

Apple Imac A1311 K74 051-8337 820-2784

Uploaded by

Canchelo

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

TOC Overview

苹果笔记本维修交流群群号：325742634

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION

K74 MLB
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
A 0000891242 PRODUCTION RELEASED 2010-04-13

LAST_MODIFIED=Tue Apr 13 17:17:57 2010

(.csa) Date (.csa) Date

D Page Contents Sync Page Contents Sync D

TABLE_TABLEOFCONTENTS_HEAD

1 N/A TABLE_TABLEOFCONTENTS_HEAD

52 01/07/2010
1 Table of Contents K74_MASTER 49 SMBus Connections DAVE
2 N/A 53 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

2 System Block Diagram K74_MASTER 50 CPU/GPU POWER SENSE K74_MASTER

TABLE_TABLEOFCONTENTS_ITEM

3 N/A TABLE_TABLEOFCONTENTS_ITEM

54 N/A
3 Power Block Diagram K74_MASTER 51 HDD TEMP SENSE K74_MASTER
TABLE_TABLEOFCONTENTS_ITEM

4 N/A TABLE_TABLEOFCONTENTS_ITEM

55 11/06/2009
4 BOM Configuration K74_MASTER 52 REMOTE TEMP/POWER SENSORS NICK
6 N/A 56 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

5 Power Conn / Alias K74_MASTER 53 HD AND OD FAN K74_MASTER

7 N/A 57 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

6 Holes K74_MASTER 54 CPU FAN & AMBIENT SENSE K74_MASTER

TABLE_TABLEOFCONTENTS_ITEM

8 N/A TABLE_TABLEOFCONTENTS_ITEM

61 11/30/2009
7 UNUSED SIGNAL ALIAS K74_MASTER 55 SPI ROM K23F
TABLE_TABLEOFCONTENTS_ITEM

9 N/A TABLE_TABLEOFCONTENTS_ITEM

62 02/02/2010
8 Signal Aliases K74_MASTER 56 AUDIO: CODEC/REGULATOR BREECE
10 N/A 63 02/02/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

9 CPU DMI/PEG/FDI/RSVD K74_MASTER 57 AUDIO: FILTER/BUFFER BREECE

TABLE_TABLEOFCONTENTS_ITEM

11 N/A TABLE_TABLEOFCONTENTS_ITEM

64 02/02/2010
10 CPU CLOCK/MISC/JTAG K74_MASTER 58 AUDIO: SPEAKER AMP_1 BREECE
12 N/A 65 02/02/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

11 CPU DDR3 INTERFACES K74_MASTER 59 AUDIO: SPEAKER AMP BREECE

13 N/A 66 02/02/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

12 CPU POWER K74_MASTER 60 Audio: MLB to I/O Conn. BREECE

TABLE_TABLEOFCONTENTS_ITEM

14 N/A TABLE_TABLEOFCONTENTS_ITEM

67 02/02/2010
13 CPU GROUNDS K74_MASTER 61 AUDIO: Detects/Grounding BREECE
15 12/08/2009 68 02/02/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

14 STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU NICK 62 AUDIO: Mikey BREECE
TABLE_TABLEOFCONTENTS_ITEM

16 12/08/2009 TABLE_TABLEOFCONTENTS_ITEM

69 N/A
15 CPU NON-GFX DECOUPLING NICK 63 POWER SEQUENCING ENABLES K74_MASTER
17 N/A 70 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

16 CPU/PCH GFX DECOUPLING K74_MASTER 64 POWER SEQUENCING PGOOD K74_MASTER

18 12/08/2009 71 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

17 PCH SATA/PCIE/CLK/LPC/SPI 65 VREG: PPVCORE_S0_CPU

C TABLE_TABLEOFCONTENTS_ITEM

18
19
PCH DMI/FDI/GRAPHICS
NICK

K74_MASTER
N/A
TABLE_TABLEOFCONTENTS_ITEM

66
72
VREG: CPU CORE - PHASES 1-3
K74_MASTER

K74_MASTER
N/A C
TABLE_TABLEOFCONTENTS_ITEM

20 12/08/2009 TABLE_TABLEOFCONTENTS_ITEM

73 N/A
19 PCH PCI/FLASHCACHE/USB NICK 67 VREG: CPU CORE - CAPS K74_MASTER
21 11/30/2009 74 12/08/2009
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

20 PCH MISC K23F 68 CPU VTT REGULATOR NICK

22 11/30/2009 76 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

21 PCH POWER K23F 69 IBEX PEAK CORE K74_MASTER

TABLE_TABLEOFCONTENTS_ITEM

23 11/30/2009 TABLE_TABLEOFCONTENTS_ITEM

77 12/08/2009
22 PCH GROUNDS K23F 70 5V_S3 / 3V3_S5 VREGS NICK
24 N/A 78 11/30/2009
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

23 PCH DECOUPLING K74_MASTER 71 1.5V / 1.8V VREGS K23F

25 12/08/2009 79 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

24 EXTENDED DEBUG PORT(XDP) NICK 72 3.42 G3HOT SUPPLY K74_MASTER

26 11/30/2009 80 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

25 CLOCK (CK505) K23F 73 S3+S0 FETS K74_MASTER

27 01/06/2010 84 11/30/2009
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

26 DDR3 RESET MATT 74 MXM PCIe, DP & Power K23F

TABLE_TABLEOFCONTENTS_ITEM

28 N/A TABLE_TABLEOFCONTENTS_ITEM

85 N/A
27 CHIPSET SUPPORT K74_MASTER 75 MXM I/O K74_MASTER
29 01/06/2010 86 11/30/2009
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

28 DDR3 Vref Margining MATT 76 MXM PCIE CAPS K23F

30 N/A 87 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

29 MEMORY CAPS K74_MASTER 77 Display: Aliases K74_MASTER

31 N/A 90 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

30 DDR3 SO-DIMMs 0 & 2 K74_MASTER 78 Display: Int DP Connector K74_MASTER

32 N/A 91 01/07/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

31 DDR3 SO-DIMM CONNECTOR B K74_MASTER 79 DISPLAY: DP REDRIVER DAVE

33 N/A 92 01/07/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

32 DDR3 ALIAS AND BITSWAPS K74_MASTER 80 DISPLAYPORT CONNECTIONS DAVE

34 N/A 94 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

33 PCI-E MiniCard Connector K74_MASTER 81 Display: Ext DP Connector K74_MASTER

TABLE_TABLEOFCONTENTS_ITEM

35 N/A TABLE_TABLEOFCONTENTS_ITEM

100 N/A
34 USB HUB 1 K74_MASTER 82 K74/K75 RULE DEFINITIONS K74_MASTER

B
36 N/A 101 N/A
B
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

35 USB HUB 2 K74_MASTER 83 Memory Constraints K74_MASTER

38 N/A 102 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

36 Caesar II/IV Support MASTER 84 PCIE/DMI/FDI/SATA CONSTRAINTS K74_MASTER

TABLE_TABLEOFCONTENTS_ITEM

39 11/30/2009 TABLE_TABLEOFCONTENTS_ITEM

103 N/A
37 Ethernet PHY (Caesar II/IV) T27 85 IBEX PEAK CONSTRAINTS K74_MASTER
40 N/A 104 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

38 Ethernet Connector MASTER 86 ENET/SD/FW/AUD CONSTRAINTS K74_MASTER

41 N/A 105 01/07/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

39 FireWire LLC/PHY (XIO2213B) MASTER 87 GRAPHICS CONSTRAINTS DAVE

42 N/A 106 12/09/2009
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

40 FW: 1394B MISC MASTER 88 SMC Constraints TEMP

43 11/17/2009 107 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

41 FIREWIRE CONNECTOR MASTER 89 POWER CONSTRAINTS K74_MASTER

TABLE_TABLEOFCONTENTS_ITEM

45 N/A TABLE_TABLEOFCONTENTS_ITEM

109 N/A
42 SATA Connectors K74_MASTER 90 PM RESETS ENABLES PGOOD CONST K74_MASTER
46 11/30/2009 110 N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

43 EXTERNAL USB CONNECTORS MASTER 91 K74/K75 ICT/FCT K74_MASTER

TABLE_TABLEOFCONTENTS_ITEM

47 11/06/2009 TABLE_TABLEOFCONTENTS_ITEM

44 Internal USB Connections MASTER

48 N/A
TABLE_TABLEOFCONTENTS_ITEM

45 SD READER CONNECTOR K74_MASTER

TABLE_TABLEOFCONTENTS_ITEM

49 N/A
46 SMC K74_MASTER
TABLE_TABLEOFCONTENTS_ITEM

50 N/A
47 SMC Support K74_MASTER
51 11/30/2009
TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM
48 LPC+SPI Debug Connector K23F

A A
DRAWING TITLE

SCH,K74,MLB
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

8 7 6 5 4 3 2 1
2 SO-DIMMS
PG 10
POWER PGSENSE
53
U1000 J3100, J3100
DISPLAY PORT CONN X4 DP
J8400 DDR3 1333 CHA
SO-DIMMS
J9400 PG 94 MXM CONNECTOR PG 31
X16 PCI-E GEN2
INTEL CPU 2 SO-DIMMS

INTERNAL DISP X4 DP PG 84 J3200, J3200

J9000 PG 90
DDR3 1333 CHB
SO-DIMMS POWER SUPPLY
LGA1156 - CLARKDALE/LYNNFIELD PG 32
TEMP, CURRENT SENSE
J2500
XDP CONN
PG 25
X4 DMI

D TEMP SENSORS D
MXM - GPU DIE
PG 13 CPU HEATSINK
GPU HEATSINK
AMBIENT INTAKE
XDP
GPIOs FDI INTERFACE DMI INTERFACE CPU DIE-PECI
INTERFACE
HARD DRIVE
OPTICAL DRIVE
PG 19 PG 19 PG 19
LCD TEMP
SKIN TEMP
POWER SUPPLY
U2600 Misc
CK505 USB 96MHZ/PCIE 100MHZ/SATA 100MHZ/BCLK 133MHZ. CLK PG 55
PG 26
PG 19 U6100 J5600, J5601, J5700
SYNTH
FAN CONN AND CONTROL
SPI
Boot ROM PG 56,57
PG 61
PG 18 SPI J5100
J4510 LPC+SPI CONN

SATA-A0
SATA CONN SATA 2.0 3GHZ. Port80,serial
HD
PG 51
PG 45 PG 18
INTEL U4900
J4520 B,0 BSB ADC Fan

SATA-A1
SATA CONN
ODD
SATA 2.0 3GHZ.
SATA IBEX PEAK SMC Ser
6 SATA 2.O PORTS Prt
PG 45 LPC
C PG 49
C
U1800
PG 18
PG 18

ANALOG VIDEO OUTPUT

RGB OUT
PWR
(PORT A)

DIGITAL VIDEO OUTPUT

CTRL J4720 J4750 J4620 J4640 J4700 J4780 J4610 J4630
HDMI/DVI/DP
(PORT B) Bluetooth SD CARD EXT EXT CAMERA IR EXT EXT

0 1 2 3 4 5 6 7 8 9 10 11 12 13
PORT1 PORT3 PORT0 PORT2

PG 20
DIGITAL VIDEO OUTPUT
HDMI/DVI/DP
(PORT C) PG 47 PG 47 PG 46 PG 46 PG 47 PG 47 PG 46 PG 46

DIGITAL VIDEO OUTPUT

HDMI/DVI/DP
(PORT D)

(UP TO 14 DEVICES)
PG 19

USB 2.0

4
USB HUB 2 USB HUB 1
USX2061 USX2061
J3900 T3900
U3800
UP TO 8 LANES3
PCI-E GEN2

PG 36 PG 35
GB E-NET
E-NET E-NET X1 PCIE GEN1 LANE 2.5GBITPS
CONTROLLER
CONNECTOR MAGNETICS AND PHY
BCM5764M

B
PG 39 PG 39 PG 38
B X1 PCIE GEN1 LANE 2.5GBITPS SMB
DIMM’s
X1 PCIE GEN1 LANE 2.5GBITPS

PG 18 U6806
PG 18

PCI HDA MIKEY

(SUPPORTED UPTO 4 REQ/GNT)
PG 20 PG 18

U4100
U6201
TI 1394B Audio
XIO2211 Codec
PG 41

HEADPHONES
INTERNAL/EXTERNAL
苹果笔记本维修交流群群号：325742634
MICROPHONES SPEAKER AMPS

A LINE INPUT U6400, U6500

SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

System Block Diagram

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

J4300 J3400 Audio REVISION

FireWire Mini PCI-E Conns

R
A.0.0
J6600,J6601,J6602,J6603
NOTICE OF PROPRIETARY PROPERTY: BRANCH
Conn AirPort THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
PG 43 PG 34 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 92
8 7 6 3 2 1
8 7 6 5 4 3 2 1

AC/DC POWER SUPPLY

D SMBUS
D
TEMP SENSOR
CONTROL PM_SLP_S3_OD
DCM/FCM
12V_S5

PP12V_S0_HDD
PPLED_PWR

PP12V_S0

LCD PANEL
HARD DRIVE
MXM
FANS
PP12V_G3H: PM_SMC_G2_EN PP12V_S5: AUDIO

PP12V_G3H PP12V_S5
PP12V_S0:
USB
PP5V_S3_REG CAMERA
IR CPU_CORE
FET (10.3A) CARD READER PPVCORE_CPU
PAGE 74 WM .65-1.5V @ 90A
PAGE 71-72

P5VS0_EN CPU UNCORE

C PP3V42_G3H_REG
SMC
PP3V3_S5_AVREF_SMC SMC VREF
PPVTT_S0
1.1V @ 30A
PAGE 76
C
REG REG PP5V_S0 AUDIO PP1V8_S0_REG CPU PLL
PAGE 79 PAGE 50 IBEX PEAK SW (1A)
FET (6.9A) OPTICAL
PAGE 80 MXM PAGE 78 IBEX PEAK
HDD PP1V05_S0
1.05V @ 3A
PAGE 76

VCCME, PCH
PP3V3_S5_REG BOOT ROM PP1V05_S5
12V S5 FET ( 7A ) 3.3V @ 6.2A
IBEX PEAK
1.05V @ 0.4A
PAGE 76 PAGE 79
CRITICAL
Q8040
FDS4465_G
SOI-HF P3V3S3_EN
8
3 D4 ETHERNET FW
S3
D3
7 PP3V3_S3 BT PP1V95_S3
2 S2 3.3V @ 2.8A 1.0V @ 0.08A
6 AP
=PP12V_G3H_S5_FET 1 D2 PP12V_S5_FET PAGE 42
5 S1 D1 5 5 PAGE 80
MAKE_BASE=TRUE
VOLTAGE=12V
GATE MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
4 NET_SPACING_TYPE=POWER P3V3S0_EN
MAX_NECK_LENGTH=3 MM
R8040
1
LCD PANEL
10K
5% 1 C8040 PP3V3_S0
IBEX PEAK
AUDIO
1/16W
MF-LF 0.47UF
10% FET (2.8A)
MXM
BIDIVI
2 402 2 16V PAGE 80 FIREWIRE
P12V_S5_EN_G

B X7R
805 B
P12V_S5_EN_D

R8041 State Manageability SMC_PM_G2_ENABLE PM_S4_STATE_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_M_L

10K
1 2 Run (S0/M0) N/A 1 1 1 1 1
5%
1/16W
MF-LF MAIN MEMORY
Sleep (S3/M1) On 1 1 0 1 1
402 PPDDR_S3_REG
Soft-Off (S5/M1) On 1 0 0 1 1
R8045
1 13A (S3 & S0)
PAGE 75
10K Sleep (S3/M-Off) Off 1 1 0 1 0
5%
1/16W
MF-LF
PM_SLP_S3
Soft-Off (S5/M-Off) Off 1 0 0 0 0
2 402
0 0 0 0 0
P12V_S5_EN_R

Battery Off (G3Hot) N/A

CPU MEM
PP1V5_S0 AUDIO
1.5V @ 4.9A FIREWIRE
PAGE 78

3
MEM_VTT
D Q8041 PP0V75_S0
0.75V @ 0.6A
2N7002
1
SOT23-HF1 PAGE 75
46 IN SMC_PM_G2_EN G S

1
R8042 ENET
100K
A 5%
1/16W
MF-LF
PP1V2_S3
1.2V @ 0.2A
PAGE 38
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE
2 402
Power Block Diagram
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

COMMON
BOM Variants PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD

TABLE_5_ITEM

TABLE_BOMGROUP_HEAD

337S3828 1 IC,IBEX PEAK PRQ,DESKTOP,FCBGA,PCH,P425 U1800 CRITICAL

BOM NUMBER BOM NAME BOM OPTIONS TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

359S0157 1 IC,SLG2AP108,CLK GEN,CK505,QFN3 U2600 CRITICAL BUF_CLK

085-1107 PCBA,MLB,DEV,K74 DEVELOPMENT,DEV_GROUP TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

341T0230 1 IC,EFI BOOTROM,K74/K75 U6100 CRITICAL

639-0698 PCBA,MLB,K74,2.93GHZ,CKD K74,2P93GHZ_CKD_CPU,BASIC,CLARKDALE_73W TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

338S0765 1 IC,XIO2211ZAY,1394B_PCIE,PHY/LINK U4100 CRITICAL

639-0707 PCBA,MLB,K74,3.06GHZ,CKD K74,3P06GHZ_CKD_CPU,BASIC,CLARKDALE_73W
D
TABLE_5_ITEM

D 825-7122 1 MLB LABEL,48.0X4.8 X14 CRITICAL

TABLE_BOMGROUP_ITEM

639-0808 PCBA,MLB,K74,3.20GHZ,CKD K74,3P20GHZ_CKD_CPU,BASIC,CLARKDALE_73W TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

343S0493 1 IC,BCM5764M,ENET,8X8 U3900 CRITICAL BCM5764M

639-0695 PCBA,MLB,K74,3.46GHZ,CKD K74,3P46GHZ_CKD_CPU,BASIC,CLARKDALE_73W TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

343S0494 1 IC,BCM57765A,ENET&SD,8X8 U3900 CRITICAL BCM57765

639-0991 PCBA,MLB,K74,3.60GHZ,CKD K74,3P60GHZ_CKD_CPU,BASIC,CLARKDALE_73W TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

341T0269 1 ENET 1MBIT FLASH,CII,K74/K75 U3990 CRITICAL BCM5764M

639-0694 PCBA,MLB,K74,2.53GHZ,LFD K74,2P53GHZ_LFD_CPU,BASIC,LYNNFIELD_82W RAW: 335S0663 TABLE_5_ITEM

341T0246 1 ENET 1MBIT FLASH,CIV,K74/K75 U3990 CRITICAL BCM57765

BOM GROUPS TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM

BASIC COMMON,ALTERNATE,XDP,MXM,XDP_CPU_BPM,PCH_VRM,BUF_CLK,HUB_USX2061,FW_TI_INT_VREG,BCM5764M,SD_USB,METAL_IO,PRODUCTION

DEV_GROUP XDP_CONN,LPCPLUS,MOJOMUX,CPU_1V5_SENSE,VREFMRGN
TABLE_BOMGROUP_ITEM

CPUS TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

337S3837 1 CKD,Q3GR,QS,2.93,73W,1333,C2,4M,LGA CPU CRITICAL 2P93GHZ_CKD_CPU

TABLE_5_ITEM

337S3912 1 CKD,SLBTD,PRQ,3.06,73W,1333,K0,4M,LGA CPU CRITICAL 3P06GHZ_CKD_CPU

CPU SOCKET & ILM SUB-BOMS 337S3911 1 CKD,SLBUD,PRQ,3.20,73W,1333,K0,4M,LGA CPU CRITICAL 3P20GHZ_CKD_CPU
TABLE_5_ITEM

ALTERNATE SOCKET VENDORS MUST USE MATCHING ILM TABLE_5_ITEM

TABLE_5_HEAD

337S3900 1 CKD,SLBLT,PRQ,3.46,73W,1333,C2,4M,LGA CPU CRITICAL 3P46GHZ_CKD_CPU

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM

TABLE_5_ITEM

337S3910 1 CKD,SLBTM,PRQ,3.60,73W,1333,K0,4M,LGA CPU CRITICAL 3P60GHZ_CKD_CPU

511S0063 1 SOCKET,LGA1156,CPU-LF U1000 CRITICAL MOLEX_SOCKET TABLE_5_ITEM

TABLE_5_ITEM

337S3862 1 LFD,Q3C6,QS,2.53,82W,1333,B1,8M,LGA CPU CRITICAL 2P53GHZ_LFD_CPU

604-1161 1 ASSY,PURCHASED,ILM,MOLEX,K74 ILM CRITICAL MOLEX_SOCKET

C 511S0069 1 SOCKET,LGA1156,CPU-LF U1000 CRITICAL FOXCONN_SOCKET

TABLE_5_ITEM

TABLE_5_ITEM
C
604-1246 1 ASSY,PURCHASED,ILM,MOLEX,K74 ILM CRITICAL FOXCONN_SOCKET TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_BOMGROUP_HEAD TABLE_ALT_ITEM

BOM NUMBER BOM NAME BOM OPTIONS 337S3898 337S3912 3P06GHZ_CKD_CPUCPU C2,PRQ,3.06 GHZ CKD
TABLE_BOMGROUP_ITEM

607-6694 SUB ASSY,CPU SOCKET,K74,MOLEX MOLEX_SOCKET

TABLE_BOMGROUP_ITEM

607-6693 SUB ASSY,CPU SOCKET,K74,FOXCONN FOXCONN_SOCKET

TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

607-6694 1 MOLEX CPU SOCKET AND ILM SKT_ILM CRITICAL

TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM

607-6693 607-6694 SKT_ILM FOXCONN ALTERNATE

K74 PARTS TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

051-8337 1 SCH,MLB,K74 SCH1

TABLE_5_ITEM

820-2784 1 PCBF,MLB,K74 MLB1

TABLE_5_ITEM

341T0231 1 IC,SMC,K74 U4900 CRITICAL K74

BOARD STACK-UP
B TOP SIGNAL B
2 GROUND
3 SIGNAL ALTERNATES TABLE_ALT_HEAD

4 POWER PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS:

TABLE_ALT_ITEM

5 POWER 197S0339 197S0179 Y4190 FIREWIRE OSCILLATOR

TABLE_ALT_ITEM

128S0298 128S0293 C1670,C7260,C7444

6 SIGNAL
7 GROUND
BOTTOM SIGNAL

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

BOM Configuration
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

89 PPVTT_S0_DDR PPVTT_S0_DDR_FET 26 89 PP1V05_S0 PP1V05_S0_REG 69

MAKE_BASE=TRUE MAKE_BASE=TRUE 89 PP3V3_S5 PP3V3_S5_REG 5 70
VOLTAGE=0.75V =PP0V75_S0_MEM_VTT_B 31 VOLTAGE=1.05V =PP1V05_S0_PCH_VCCADPLL 16 MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mm MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.3V =PP3V3_S5_PCH 17 18 23
MIN_NECK_WIDTH=0.2 mm =PP0V75_S0_MEM_VTT_A 30 MIN_NECK_WIDTH=0.2 mm =PP1V05_S0_PCH_VCCIO_DMI 21 23 MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER NET_SPACING_TYPE=POWER MIN_NECK_WIDTH=0.2MM =PP3V3_S5_PCH_GPIO 19
MAX_NECK_LENGTH=3 MM MAX_NECK_LENGTH=3 MM =PP1V05_S0_PCH_VCCIO_SATA 17 21 23 NET_SPACING_TYPE=POWER
=PP3V3_S5_ROM

D 89 PPVCORE_S0_CPU
MAKE_BASE=TRUE
PPVCORE_S0_CPU_REG 65 66 67
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCC_CORE
17 18 21 23

21 23
MAX_NECK_LENGTH=3 MM
=PP3V3_S5_PCH_VCCSUS3_3_USB
48 55

21 23 D
VOLTAGE=1.1V =PPVCORE_S0_CPU =PP3V3_S5_PWRCTL
1 C690 518-0352
1 C691 MIN_LINE_WIDTH=0.6MM
12 15
=PP1V05_S0_PCH_VCCIO_USB 21 23
=PP3V3_S5_S3FET
10 63 64

47PF 47PF MIN_NECK_WIDTH=0.3MM

NET_SPACING_TYPE=POWER =PP1V05_S0_CK505 25
73
5% CRITICAL 5% MAX_NECK_LENGTH=3 MM =PP3V3_S5_S0FET 73
50V 50V
2 CERM 2 CERM
402 J600 402
=PP1V05_SM_PCH_VCC_ME 21 23 =PP3V3_S5_PCH_STRAPS 14
76833-0100 =PP3V3_S5_CPURESET 10
M-RT-TH 89 50 PPVTT_S0 PPVTT_S0_CPU_REG 68
MAKE_BASE=TRUE =PP3V3_S5_XDP
R690 1 8 R691 VOLTAGE=1.1V =PPVTT_S0_PCH_VCC_DMI 21 23 89 PP1V05_SM_PCH_LAN =PP1V05_SM_PCH_VCC_LAN 21 23
0 0 MIN_LINE_WIDTH=0.6 mm MAKE_BASE=TRUE =PP3V3_S5_LPCPLUS 48
49 =SMB_ACDC_SCL 1 2 SMB_ACDC_SCL_RC 2 9 SMB_ACDC_SDA_RC 1 2 =SMB_ACDC_SDA 49 MIN_NECK_WIDTH=0.2 mm =PPVTT_S0_XDP 24 VOLTAGE=1.05V UNUSED, GROUNDED ON CSA 24
3 10 NET_SPACING_TYPE=POWER
42 5 =PP5V_S0_SATA PP12V_S0 5 64 89 MAX_NECK_LENGTH=3 MM =PPVTT_S0_PCH_VCCP_CPU 21 23

89 72 5 PP12V_G3H 4 11 =PPVTT_S0_CPU 10 12 15 47 65
5 12
89 PP0V75_S0 PPVTT_S0_DDR_LDO 71
80 LCD_PWM 6 13 LCD_BKL_ON 78 MAKE_BASE=TRUE
VOLTAGE=0.75V =PP0V75_S0_MEM_VTT_S0FET 26 89 PP5V_S5 PP5V_S5_LDO 70
7 14 MIN_LINE_WIDTH=0.4 mm MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V =PP5V_S5_PCH 23
NET_SPACING_TYPE=POWER MIN_LINE_WIDTH=0.4 MM
89 50 PP1V5_CPU_MEM =PP1V5_CPU_MEM 10 12 15 29 MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE NET_SPACING_TYPE=POWER
VOLTAGE=1.5V MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
PP12V_S0 =PP12V_S0_FAN
1 C623 1 C631 1 C627 1 C626 1 C630 1 C624 NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
89 64 5
MAKE_BASE=TRUE
=PP12V_S0_AUDIO_SPKRAMP
53 54
89 PP12V_S5 PP12V_S5_FET 3
10UF 0.001UF 0.001UF 0.001UF 0.001UF 10UF VOLTAGE=12V
MIN_LINE_WIDTH=0.6MM
58 59 MAKE_BASE=TRUE
VOLTAGE=12V =PP12V_S5_DDR_VREG 71
20% 10% 10% 10% 10% 10% MIN_NECK_WIDTH=0.2MM =PP12V_S0_VRD 65 MIN_LINE_WIDTH=0.6 mm
10V 50V 50V 50V 50V 16V PP1V5_S0 PP1V5_S0_FET =PP12V_S5_P3V3S5_VREG
2 X5R 2 X7R 2 X7R 2 X7R 2 X7R 2 X5R-CERM 89 50 73 NET_SPACING_TYPE=POWER MIN_NECK_WIDTH=0.2 mm 70
805 402 402 402 402 1210 MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM =PPV_S0_MXM_PWR 50 NET_SPACING_TYPE=POWER
VOLTAGE=1.5V =PP1V5_S0_AUD_DIG 56 MAX_NECK_LENGTH=3 MM =PP12V_S5_P5VS3_VREG 70
MIN_LINE_WIDTH=0.4MM =PP12V_S0_LCD 78
MIN_NECK_WIDTH=0.2MM =PP1V5_FWRS0_FWXIO 39 =PP12V_S5_PWRCTL 64 73
NET_SPACING_TYPE=POWER =PP12V_S0_PCH_CORE_VREG 69
MAX_NECK_LENGTH=3 MM =PP1V5_S0_CK505 25
PM_ACDC_PS_ON =PP12V_S0_CPU_VTT_VREG 68
=PP1V5_S0_MINI 33
=PP12V_S0_PWRCTL 64

=PP12V_S0_SENSE 51
3
1 C600 =PP12V_S0_FW 41

C D
Q610
2N7002
SOT23-HF1 2
0.001UF
10%
50V
X7R
C
91 81 64 63 47 46 36 26 18 PM_SLP_S3_L 1 G S 402
IN

2 89 PP1V8_S0 PP1V8_S0_REG 71
MAKE_BASE=TRUE
VOLTAGE=1.5V =PP3V3R1V8_S0_PCH_VCCPNAND 21 23
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM =PP1V8R1V5_S0_PCH_VCCVRM 23
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM =PP1V8_S0_CPU_PLL 12 15 64 "S3" RAILS
ON IN RUN AND SLEEP

92 89 5 PP3V3_S3
DEVELOPMENT
89 PP1V5_S3 PP1V5_S3_REG 71
1
R600 MAKE_BASE=TRUE
VOLTAGE=1.5V =PP1V5_S3_MEMRESET 26
1K MIN_LINE_WIDTH=0.6 mm
=PPDDR_S3_S0FET
5% MIN_NECK_WIDTH=0.2 mm 73
PP3V3_S0 PP3V3_S0_FET
1/16W
MF-LF
89 5
MAKE_BASE=TRUE
=PP3V3_S0_PCH
73 NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM =PP1V5_S3_MEM_A 28 29 30 "G3H" RAILS
2 402 VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4MM
17 20 23 69
=PP1V5_S3_MEM_B 28 29 31
ITS_ALIVE MIN_NECK_WIDTH=0.2MM =PP3V3_S0_FAN 53 54 ALWAYS ON WHEN UNIT HAS AC POWER AND IN G3HOT PER SMC
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM =PP3V3_S0_PCH_VCCADAC 16
A DEVELOPMENT G3H: ALIASES
=PPSPD_S0_MEM_A 30 47
LED605 =PPSPD_S0_MEM_B 31
GREEN-3.6MCD PP3V42_G3H PP3V42_G3H_REG
89 72
K 2.0X1.25MM-SM =PP3V3_S0_VRD 65 92 89 5 PP3V3_S3 PP3V3_S3_FET 73 MAKE_BASE=TRUE
MAKE_BASE=TRUE VOLTAGE=3.42V =PP3V3_S5_RTC_D 27
=PP3V3_S0_AUDIO 56 58 59 60 61 62 VOLTAGE=3.3V =PP3V3_S3_BT 44 MIN_LINE_WIDTH=0.6MM
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2MM =PP3V3_G3H_SMC 46 47
=PP3V3R1V5_S0_PCH_VCCSUSHDA 21 23 MIN_NECK_WIDTH=0.2 mm =PP3V3_S3_SMBUS_SMC_A_S3 49 NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER MAX_NECK_LENGTH=3 MM =PP3V3_G3H_SMCUSBMUX 43
=PP3V3_S0_SMBUS 49 MAX_NECK_LENGTH=3 MM =PP3V3_S3_MINI 33
=PPVIN_S5_SMCVREF 47
=PP3V3_S0_SMC_LS 47 51 =PP3V3_S3_PWRCTL 64 73
92 89 5 PP3V3_S3 =PP3V3_G3H_LPCPLUS 48
70 5 PP3V3_S5_REG =PP3V3_S0_SMBUS_SMC_0_S0 49 =PP3V3_S3_MEMRESET 26

1
R601 R602
1 =PP3V3_S0_SMBUS_SMC_B_S0 49 =PP3V3_S3_USB_HUB 34 35

1K =PP3V3_S0_SMBUS_SMC_MGMT 49 =PP3V3_S3_USB_RESET 34
1K
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF
2 402
=PP3V3_S0_DPCONN
=PP3V3_S0_TSENS
81

52
=PP3V3_S3_SDCARD
=PP3V3_S3_VREFMRGN
44 45

28
B
2 402 89 72 5 PP12V_G3H =PP12V_G3H_S5_FET 3
CORE_VOLTAGES_ON_R =PP3V3_S0_MXM 64 74 75 =PP3V3_S3_ENETFET 36 MAKE_BASE=TRUE
ITS_PLUGGED_IN VOLTAGE=12V
=PP3V3_S0_ODD 42 MIN_LINE_WIDTH=0.6 mm
A MIN_NECK_WIDTH=0.2 MM
A =PP3V3_S0_SATALED 17 42 NET_SPACING_TYPE=POWER
LED602 MAX_NECK_LENGTH=3 MM
LED601 GREEN-3.6MCD
=PP3V3_S0_SMC 47 50
GREEN-3.6MCD 2.0X1.25MM-SM =PP3V3_S0_PWRCTL
2.0X1.25MM-SM
K 63 64 73
SILKSCREEN:2
K
SILKSCREEN:1
CORE_VOLTAGES_ON
=PP3V3_S0_PCH_VCC3_3_CORE 21 23
92 89 PP5V_S3 PP5V_S3_REG 70 92
GND RAILS
=PP3V3_FW_FWPHY 39 40 41 MAKE_BASE=TRUE
VOLTAGE=5V =PP5V_S3_USB 43
=PP3V3_FWRS0_FWXIO 39 MIN_LINE_WIDTH=0.6MM
3 MIN_NECK_WIDTH=0.2MM =PP5V_S3_S0FET 73
=PP3V3_S0_DP 78 79 80 NET_SPACING_TYPE=POWER
D MAX_NECK_LENGTH=3 MM =PP5V_S3_CAMERA 44 GND
Q602 =PP3V3_S0_PCH_VCC3_3_PCI 21 23 MIN_LINE_WIDTH=0.6MM
=PP5V_S3_IR 44 MIN_NECK_WIDTH=0.2MM
2N7002DW-X-G =PP3V3_S0_CK505 25 VOLTAGE=0V
91 64 IN ALL_SYS_PWRGD_R 5 G S SOT-363 =PP5V_S3_PWRCTL 63 NET_SPACING_TYPE=GND =PPVAXG_S0_CPU 12
=PP3V3_S0_PCH_GPIO 19 MAKE_BASE=TRUE
=PP5V_S3_MEMRESET 26 MAX_NECK_LENGTH=4.1 MM
4 =PP3V3_S0_PCH_STRAPS 14
=PP5V_S3_DDR_VREG 71
=PP3V3_S0_PCH_VCC3_3_SATA 21 23

=PP3V3_S0_RSTBUF 27
89 5 PP3V3_S0
MXM =PP3V3_S0_ENETPHY 37

R604
1 =PP3V3_S0_PCH_PM 27

1K
5%
=PP3V3_S0_SMBUS_SMC_BSA 49 ENET RAILS
1/16W =PP3V3_SM_PCH_VCC_ME 21 23
MF-LF
2 402 89 5 PP3V3_S0 =PP3V3_S0_SDCARD 45

GPU_PRESENT_R =PP3V3_S0_CPU_VTT_VREG 68
1
R603 PP3V3_ENET
MAKE_BASE=TRUE
PP3V3_ENET_FET 36
A MXM 1K VOLTAGE=3.3V =PP3V3_ENET_PHY 36 37 45
5% MIN_LINE_WIDTH=0.4MM
LED604 1/16W MIN_NECK_WIDTH=0.2MM
MF-LF NET_SPACING_TYPE=POWER

A
GREEN-3.6MCD
K 2.0X1.25MM-SM
SILKSCREEN:3
2 402
LCD_SHOULD_ON_R
92 89 PP5V_S0
MAKE_BASE=TRUE
PP5V_S0_FET 73
MAX_NECK_LENGTH=3 MM
SYNC_MASTER=K74_MASTER
PAGE TITLE
SYNC_DATE=N/A A
GPU_PRESENT_DRAIN VOLTAGE=5V =PP5V_S0_AUDIO 56

6
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=POWER
=PP5V_S0_SATA 5 42 Power Conn / Alias
MAX_NECK_LENGTH=3 MM =PP5V_S0_MXM 74 DRAWING NUMBER SIZE
D
A
=PP5V_S0_VRD 65
Apple Inc. 051-8337 D
Q602 =PP5V_S0_ISENSE 50 REVISION
2N7002DW-X-G LED603
20 IN MXM_GOOD 2 G S SOT-363 GREEN-3.6MCD
=PP5V_S0_P1V8_VREG 71
R
A.0.0
K 2.0X1.25MM-SM =PP5V_S0_PCH 23 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1 SILKSCREEN:4
=PP5V_S0_CPU_VTT_VREG 68 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
=PP5V_S0_LPCPLUS 48 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VIDEO_ON_L IN 78 =PP5V_S0_PCH_CORE_VREG 69
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 110
=PP5V_S0_DP_AUX_MUX SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 5 OF 92
8 7 6 3 2 1
8 7 6 5 4 3 2 1

CPU Heatsink DIMM CONNECTOR NUTS

4mm Plated Holes (998-0850) Nuts (805-9582)
OMIT OMIT OMIT OMIT
ZH0700 ZH0701 ZH0702 ZH0703 CRITICAL CRITICAL CRITICAL CRITICAL
4P75R4 4P75R4 4P75R4 4P75R4 NUT0750 NUT0751 NUT0752 NUT0753
1 1 1 1 NUT-4.25OD1.4H-1.40-3.25-TH NUT-4.25OD1.4H-1.40-3.25-TH NUT-4.25OD1.4H-1.40-3.25-TH NUT-4.25OD1.4H-1.40-3.25-TH

D 1 1 1 1 D

PCH HEATSINK
MOUNTING ANCHORS (511-0057)
CRITICAL CRITICAL
AN0700 AN0701
HB9703E-SLH HB9703E-SLH
HSK-TH HSK-TH
1 1
2 2

C C

Rear Cover
Standoffs (860-1255)
CRITICAL CRITICAL
CRITICAL SDF0714 CRITICAL CRITICAL SDF0718
SDF0713 STDOFF-6.8OD15.0H-1.56-TH SDF0715 SDF0717 STDOFF-6.8OD15.0H-1.56-TH
STDOFF-6.8OD15.0H-1.56-TH 1 STDOFF-6.8OD15.0H-1.56-TH STDOFF-6.8OD15.0H-1.56-TH 1
1 1 1

Backer Plate
B B
Nuts (835-0269)
CRITICAL CRITICAL CRITICAL
NUT0700 NUT0701 NUT0702
NUT-6.5OD1.4H-1.56-3.8-TH NUT-6.5OD1.4H-1.56-3.8-TH NUT-6.5OD1.4H-1.56-3.8-TH
1 1 1

For EMC
EMC Spring (870-1577); Near DIMMs
CRITICAL

A NOSTUFF
SC0702
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
1 EMI-SPRING PAGE TITLE
CLIP-SM-K2
Holes
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
7 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 6 OF 92
8 7 6 3 2 1
8 7 6 5 4 3 2 1
UNUSED CPU SIGNALS NC ON UNUSED PCIE ALIASES NC ON UNUSED DISPLAY ALIASES NC ON UNUSED FDI ALIASES
9 TP_CPU_RSVD<41..29> NC_CPU_RSVD<41..29>
MAKE_BASE=TRUE NO_TEST=TRUE 17 TP_PCIE_T28_D2R_N<3..0> NC_PCIE_T28_D2RN<3..0> 18 TP_CRT_IG_DDC_CLK NC_CRT_IG_DDC_CLK 9 TP_CPU_FDI_TX_N<7..0> NC_CPU_FDI_TXN<7..0>
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
9 TP_CPU_RSVD<26..1> NC_CPU_RSVD<26..1>
MAKE_BASE=TRUE NO_TEST=TRUE 17 TP_PCIE_T28_D2R_P<3..0> NC_PCIE_T28_D2RP<3..0> 9 TP_CPU_FDI_TX_P<7..0> NC_CPU_FDI_TXP<7..0>
12 TP_CPU_FC_AE38 NC_CPU_FC_AE38 MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_CRT_IG_DDC_DATA NC_CRT_IG_DDC_DATA MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCH_FDI_RX_N<7..0> NC_PCH_FDI_RXN<7..0>
17 TP_PCIE_T28_R2D_C_N<3..0> NC_PCIE_T28_R2D_CN<3..0> MAKE_BASE=TRUE NO_TEST=TRUE
12 TP_CPU_FC_AG40 NC_CPU_FC_AG40 MAKE_BASE=TRUE NO_TEST=TRUE TP_CRT_IG_RED NC_CRT_IG_RED
MAKE_BASE=TRUE NO_TEST=TRUE 18
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCH_FDI_RX_P<7..0> NC_PCH_FDI_RXP<7..0>
17 TP_PCIE_T28_R2D_C_P<3..0> NC_PCIE_T28_R2D_CP<3..0> MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
TP_CRT_IG_GREEN NC_CRT_IG_GREEN TP_CPU_FDI_FSYNC<1..0> NC_CPU_FDI_FSYNC<1..0>
NC ON UNUSED PCI ALIASES 17 TP_PCIE_CLK100M_T28_N NC_PCIE_CLK100M_T28N
MAKE_BASE=TRUE NO_TEST=TRUE
18
MAKE_BASE=TRUE NO_TEST=TRUE
9

TP_PCH_FDI_FSYNC<1..0>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_PCH_FDI_FSYNC<1..0>
D 19 TP_PCI_AD<31..0> NC_PCI_AD<31..0>
MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_PCIE_CLK100M_T28_P NC_PCIE_CLK100M_T28P
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_CRT_IG_BLUE NC_CRT_IG_BLUE
MAKE_BASE=TRUE NO_TEST=TRUE
18

9 TP_CPU_FDI_LSYNC<1..0>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_CPU_FDI_LSYNC<1..0>
D
TP_PCI_C_BE_L<3..0> NC_PCI_C_BE_L<3..0> MAKE_BASE=TRUE NO_TEST=TRUE
19
MAKE_BASE=TRUE NO_TEST=TRUE 17 PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_D2RP 18 TP_CRT_IG_HSYNC NC_CRT_IG_HSYNC
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCH_FDI_LSYNC<1..0> NC_PCH_FDI_LSYNC<1..0>
MAKE_BASE=TRUE NO_TEST=TRUE
TP_PCI_PAR NC_PCI_PAR 17 PCIE_EXCARD_D2R_N NC_PCIE_EXCARD_D2RN
19
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_CRT_IG_VSYNC NC_CRT_IG_VSYNC 9 TP_CPU_FDI_INT NC_CPU_FDI_INT
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_PCI_RESET_L NC_PCI_RESET_L 17 PCIE_EXCARD_R2D_C_P NC_PCIE_EXCARD_R2D_CP 18 TP_PCH_FDI_INT NC_PCH_FDI_INT
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
17 PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_CN 18 TP_DP_IG_B_MLN<3..0> NC_DP_IG_B_MLN<3..0>
20 TP_PCIE_CLK100M_XDPP NC_PCIE_CLK100M_XDPP MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_DP_IG_B_MLP<3..0> NC_DP_IG_B_MLP<3..0>
17 PCIE_CLK100M_EXCARD_P NC_PCIE_CLK100M_EXCARDP MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_PCIE_CLK100M_XDPN NC_PCIE_CLK100M_XDPN MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_DP_IG_B_AUX_N NC_DP_IG_B_AUXN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_DMI_CLK100M_LAP NC_DMI_CLK100M_LAP
MAKE_BASE=TRUE NO_TEST=TRUE
17 PCIE_CLK100M_EXCARD_N NC_PCIE_CLK100M_EXCARDN
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_DP_IG_B_AUX_P NC_DP_IG_B_AUXP
MAKE_BASE=TRUE NO_TEST=TRUE
NC ON UNUSED SATA ALIASES
20 TP_DMI_CLK100M_LAN NC_DMI_CLK100M_LAN 17 TP_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE5P 18 TP_DP_IG_B_HPD NC_DP_IG_B_HPD 17 TP_SATA_D_D2RN NC_SATA_D_D2RN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5N 18 TP_DP_IG_B_DDC_CLK NC_DP_IG_B_CTRL_CLK 17 TP_SATA_D_D2RP NC_SATA_D_D2RP
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_LPC_DREQ1_L NC_LPC_DREQ1_L 18 TP_DP_IG_B_DDC_DATA NC_DP_IG_B_CTRL_DATA
MAKE_BASE=TRUE NO_TEST=TRUE
17 DMI_MIDBUS_CLK100M_P NC_DMI_MIDBUS_CLK100MP MAKE_BASE=TRUE NO_TEST=TRUE 17 TP_SATA_D_R2D_CN NC_SATA_D_R2D_CN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_LPC_DREQ0_L NC_LPC_DREQ0_L TP_SATA_D_R2D_CP NC_SATA_D_R2D_CP
MAKE_BASE=TRUE NO_TEST=TRUE 17 DMI_MIDBUS_CLK100M_N NC_DMI_MIDBUS_CLK100MN 17
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_DP_IG_C_MLN<3..0> NC_DP_IG_C_MLN<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE NC_SATA_E_D2RN
NC ON UNUSED NAND ALIASES 18 TP_DP_IG_C_MLP<3..0> NC_DP_IG_C_MLP<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_SATA_E_D2RN
MAKE_BASE=TRUE NO_TEST=TRUE
NC_SATA_E_D2RP
19 TP_NV_CE_L<3..0> NC_NV_CE_L<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE NC ON UNUSED USB ALIASES 18 TP_DP_IG_C_AUX_N NC_DP_IG_C_AUXN
MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_SATA_E_D2RP
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_NV_DQS<1..0> NC_NV_DQS<1..0> TP_SATA_E_R2D_CN NC_SATA_E_R2D_CN
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_DP_IG_C_AUX_P NC_DP_IG_C_AUXP 17
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_USB_1N NC_USB_1N MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_NV_DQ<15..0> NC_NV_DQ<15..0> MAKE_BASE=TRUE NO_TEST=TRUE 17 TP_SATA_E_R2D_CP NC_SATA_E_R2D_CP
MAKE_BASE=TRUE NO_TEST=TRUE
C 19 TP_NV_RCOMP NC_NV_RCOMP
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_USB_1P NC_USB_1P
MAKE_BASE=TRUE NO_TEST=TRUE
18

18
TP_DP_IG_C_HPD
TP_DP_IG_C_CTRL_CLK
NC_DP_IG_C_HPD
MAKE_BASE=TRUE NO_TEST=TRUE
NC_DP_IG_C_CTRL_CLK 17 TP_SATA_F_D2RN
MAKE_BASE=TRUE
NC_SATA_F_D2RN
NO_TEST=TRUE
C
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_USB_2N NC_USB_2N TP_SATA_F_D2RP NC_SATA_F_D2RP
19 TP_NV_RB_L NC_NV_RB_L MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_DP_IG_C_CTRL_DATA NC_DP_IG_C_CTRL_DATA 17
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_USB_2P NC_USB_2P
19 TP_NV_WR_RE_L<1..0> NC_NV_WR_RE_L<1..0> MAKE_BASE=TRUE NO_TEST=TRUE 17 TP_SATA_F_R2D_CN NC_SATA_F_R2D_CN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_USB_3N NC_USB_3N 18 TP_DP_IG_D_MLN<3..0> NC_DP_IG_D_MLN<3..0> 17 TP_SATA_F_R2D_CP NC_SATA_F_R2D_CP
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_NV_WE_CK_L<1..0> NC_NV_WE_CK_L<1..0>
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_USB_3P NC_USB_3P 18 TP_DP_IG_D_MLP<3..0> NC_DP_IG_D_MLP<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE TP_SATA_SSD_D2R_N NC_SATA_SSD_D2RN
19 TP_NV_ALE NC_NV_ALE 17
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_DP_IG_D_AUXN NC_DP_IG_D_AUXN
MAKE_BASE=TRUE NO_TEST=TRUE TP_SATA_SSD_D2R_P NC_SATA_SSD_D2RP
19 TP_NV_CLE NC_NV_CLE TP_USB_4N NC_USB_4N 17
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 19
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_DP_IG_D_AUXP NC_DP_IG_D_AUXP
MAKE_BASE=TRUE NO_TEST=TRUE
NC ON UNUSED MEM ALIASES 19 TP_USB_4P NC_USB_4P
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_DP_IG_D_HPD NC_DP_IG_D_HPD
MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_SATA_SSD_R2D_C_N NC_SATA_SSD_R2D_CN
MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_SATA_SSD_R2D_C_P NC_SATA_SSD_R2D_CP
TP_MEM_A_CS_L<7..4> NC_MEM_A_CS_L<7..4> TP_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_CLK MAKE_BASE=TRUE NO_TEST=TRUE
11
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_USB_5N NC_USB_5N 18
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_MEM_A_DQ_CB<7..0> NC_MEM_A_DQ_CB<7..0> 19 TP_USB_5P NC_USB_5P 18 TP_DP_IG_D_CTRL_DATA NC_DP_IG_D_CTRL_DATA
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE

19 TP_USB_6N NC_USB_6N
11 TP_MEM_A_DQS_N<8> NC_MEM_A_DQSN<8> MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE TP_GFX_VID<0..6> NC_GFX_VID<0..6>
19 TP_USB_6P NC_USB_6P 12
MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_MEM_A_DQS_P<8> NC_MEM_A_DQSP<8> MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
12 TP_GFX_VSENSE_N NC_GFX_VSENSEN
11 TP_MEM_B_CS_L<7..4> NC_MEM_B_CS_L<7..4> 19 TP_USB_7N NC_USB_7N MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_MEM_B_DQ_CB<7..0> NC_MEM_B_DQ_CB<7..0> 19 TP_USB_7P NC_USB_7P 12 TP_GFX_VSENSE_P NC_GFX_VSENSEP
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE

19 TP_USB_9N NC_USB_9N
B 11 TP_MEM_B_DQS_N<8> NC_MEM_B_DQSN<8>
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_USB_9P
MAKE_BASE=TRUE
NC_USB_9P
MAKE_BASE=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
18 TP_SDVO_TVCLKINN NC_SDVO_TVCLKINN
MAKE_BASE=TRUE NO_TEST=TRUE
B
11 TP_MEM_B_DQS_P<8> NC_MEM_B_DQSP<8>
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_SDVO_TVCLKINP NC_SDVO_TVCLKINP
19 TP_USB_10N NC_USB_10N MAKE_BASE=TRUE NO_TEST=TRUE
NC ON UNUSED MISC ALIASES 19 TP_USB_10P
MAKE_BASE=TRUE
NC_USB_10P
NO_TEST=TRUE
18 TP_SDVO_STALLN NC_SDVO_STALLN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_HDA_SDIN1 NC_HDA_SDIN1
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_SDVO_STALLP NC_SDVO_STALLP
19 TP_USB_11N NC_USB_11N MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_HDA_SDIN2 NC_HDA_SDIN2 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_USB_11P NC_USB_11P 18 TP_SDVO_INTN NC_SDVO_INTN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_HDA_SDIN3 NC_HDA_SDIN3
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_SDVO_INTP NC_SDVO_INTP
TP_JTAG_XDP_TRST_L NC_JTAG_XDP_TRST_L 19 TP_USB_12N NC_USB_12N MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_USB_12P NC_USB_12P
20 TP_PCH_PWM0 NC_PCH_PWM0 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE

20 TP_PCH_PWM1 NC_PCH_PWM1 19 TP_USB_13N NC_USB_13N

MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_USB_13P NC_USB_13P
20 TP_PCH_PWM2 NC_PCH_PWM2 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE

20 TP_PCH_PWM3 NC_PCH_PWM3
MAKE_BASE=TRUE NO_TEST=TRUE

20 TP_PCH_SST NC_PCH_SST
MAKE_BASE=TRUE NO_TEST=TRUE

9 SNS_CPU_THERMD_N NC_SNS_CPU_THERMDN
MAKE_BASE=TRUE NO_TEST=TRUE
SNS_CPU_THERMD_P NC_SNS_CPU_THERMDP
A 9
MAKE_BASE=TRUE NO_TEST=TRUE
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

UNUSED SIGNAL ALIAS

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

D D

PEG Slot Support

THIS SIGNAL NAME IS CONNECTED TO MXM
17 IN PEG_CLK100M_P 84 GPU_CLK100M_PCIE_P CLK_100M_MXM_P OUT 74
MAKE_BASE=TRUE
17 IN PEG_CLK100M_N 84 GPU_CLK100M_PCIE_N CLK_100M_MXM_N OUT 74
MAKE_BASE=TRUE
9 IN =PEG_R2D_C_P<0..15> PEG_R2D_C_P<0..15> OUT 76 84
MAKE_BASE=TRUE
9 IN =PEG_R2D_C_N<0..15> PEG_R2D_C_N<0..15> OUT 76 84
MAKE_BASE=TRUE

C 9

9
OUT =PEG_D2R_P<0..15>
=PEG_D2R_N<0..15>
PEG_D2R_P<0..15>
MAKE_BASE=TRUE
PEG_D2R_N<0..15>
IN 76 84

76 84
C
OUT IN
MAKE_BASE=TRUE

17 IN PEG_CLKREQ_L MXM_CLKREQ_L OUT 74

MAKE_BASE=TRUE

74 MXM_RESET_L PEG_RESET_L 27 91
MAKE_BASE=TRUE

B B

R929
22
91 85 18 IN PM_CLK32K_SUSCLK_R 1 2 PM_CLK32K_SUSCLK OUT 46 85 91

PLACEMENT_NOTE=PLACE CLOSE TO U1800 5%

1/16W
MF-LF
402

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

Signal Aliases
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

84 18 IN DMI_S2N_N<0> DMI_RX_0* U1000 PEG_ICOMPI 84 CPU_PEG_COMP

84 18 IN DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_RX_1* LYNNFIELD PEG_ICOMPO 7 TP_CPU_RSVD<1>
TP_CPU_RSVD<2>
A12
AD2
RSVD_A12 U1000 RSVD_AL15 AL15
AL17
TP_CPU_RSVD<19>
TP_CPU_RSVD<20>
7

84 18 IN DMI_RX_2* LGA1156-SKT PEG_RCOMPO 7 RSVD_AD2 RSVD_AL17 7

84 18 IN DMI_S2N_N<3> DMI_RX_3* (1 OF 10) PEG_RBIAS 84 CPU_PEG_RBIAS 7 TP_CPU_RSVD<3> AE2 RSVD_AE2 LYNNFIELDRSVD_AL18 AL18 TP_CPU_RSVD<21> 7

7 TP_CPU_RSVD<4> AH40 RSVD_AH40 LGA1156-SKTRSVD_AL26 AL26 TP_CPU_RSVD<22> 7

84 18 IN DMI_S2N_P<0> DMI_RX_0 OMIT PEG_RX_0* =PEG_D2R_N<0> IN 8
AJ39 AL27
R1012 1 1
R1010 7 TP_CPU_RSVD<5> RSVD_AJ39 (5 OF 10) RSVD_AL27 TP_CPU_RSVD<23> 7
84 18 IN DMI_S2N_P<1> DMI_RX_1 PEG_RX_1* =PEG_D2R_N<1> IN 8
AK12 AL29
750 49.9 7 TP_CPU_RSVD<6> RSVD_AK12 RSVD_AL29 TP_CPU_RSVD<24> 7
84 18 IN DMI_S2N_P<2> DMI_RX_2 PEG_RX_2* =PEG_D2R_N<2> IN 8 1% 1% OMIT
TP_CPU_RSVD<7> AK13 RSVD_AK13 RSVD_AM13 AM13 TP_CPU_RSVD<25>

D 84 18 IN DMI_S2N_P<3> DMI_RX_3 PEG_RX_3*

PEG_RX_4*
=PEG_D2R_N<3>
=PEG_D2R_N<4>
IN
IN
8

8
1/16W
MF-LF
402
2 2
1/16W
MF-LF
402
7

7 TP_CPU_RSVD<8> AK14
AK15
RSVD_AK14 RSVD_AM14 AM14
AM15
TP_CPU_RSVD<26>
7

7 D
84 18 OUT DMI_N2S_N<0> DMI_TX_0* 7 TP_CPU_RSVD<9> RSVD_AK15 RSVD_AM15 SNS_CPU_THERMD_P 7
PEG_RX_5* =PEG_D2R_N<5> IN 8
AK16 AM16

DMI
84 18 OUT DMI_N2S_N<1> DMI_TX_1* PLACE R1010 AND R1012 CLOSE TO CPU BALLS 7 TP_CPU_RSVD<10> RSVD_AK16 RSVD_AM16 SNS_CPU_THERMD_N 7
PEG_RX_6* =PEG_D2R_N<6> 8
84 18 DMI_N2S_N<2> DMI_TX_2*
IN
7 TP_CPU_RSVD<11> AK18 RSVD_AK18 RSVD_AM17 AM17 TP_CPU_RSVD<29> 7
OUT =PEG_D2R_N<7>
PEG_RX_7* IN 8
AK25 AM18
84 18 OUT DMI_N2S_N<3> DMI_TX_3* 7 TP_CPU_RSVD<12> RSVD_AK25 RSVD_AM18 TP_CPU_RSVD<30> 7
PEG_RX_8* =PEG_D2R_N<8> IN 8
7 TP_CPU_RSVD<13> AK26 RSVD_AK26 RSVD_AM19 AM19 TP_CPU_RSVD<31> 7
84 18 OUT DMI_N2S_P<0> DMI_TX_0 PEG_RX_9* =PEG_D2R_N<9> IN 8
7 TP_CPU_RSVD<14> AK27 RSVD_AK27 RSVD_AM20 AM20 TP_CPU_RSVD<32> 7

RESERVED
84 18 OUT DMI_N2S_P<1> DMI_TX_1 PEG_RX_10* =PEG_D2R_N<10> IN 8
AK28 AM21
7 TP_CPU_RSVD<15> RSVD_AK28 RSVD_AM21 TP_CPU_RSVD<33> 7
84 18 OUT DMI_N2S_P<2> DMI_TX_2 PEG_RX_11* =PEG_D2R_N<11> IN 8
AK29 AM25
7 TP_CPU_RSVD<16> RSVD_AK29 RSVD_AM25 TP_CPU_RSVD<34> 7
84 18 OUT DMI_N2S_P<3> DMI_TX_3 PEG_RX_12* =PEG_D2R_N<12> IN 8
7 TP_CPU_RSVD<17> AL12 RSVD_AL12 RSVD_AM26 AM26 TP_CPU_RSVD<35> 7

PCI EXPRESS -- GRAPHICS

PEG_RX_13* =PEG_D2R_N<13> IN 8
7 TP_CPU_RSVD<18> AL14 RSVD_AL14 RSVD_AM27 AM27 TP_CPU_RSVD<36> 7
7 TP_CPU_FDI_TX_N<0> FDI_TX_0* PEG_RX_14* =PEG_D2R_N<14> IN 8
RSVD_AM28 AM28 TP_CPU_RSVD<37> 7
E8

FLEXIBLE DISPLAY INTERFACE

7 TP_CPU_FDI_TX_N<1> FDI_TX_1* PEG_RX_15* =PEG_D2R_N<15> IN 8 84 24 IN CPU_CFG<0> CFG_0 AM29
G8 RSVD_AM29 TP_CPU_RSVD<38> 7
7 TP_CPU_FDI_TX_N<2> FDI_TX_2* 84 24 IN CPU_CFG<1> CFG_1 AM30
PEG_RX_0 =PEG_D2R_P<0> IN 8
E10 RSVD_AM30 TP_CPU_RSVD<39> 7
7 TP_CPU_FDI_TX_N<3> FDI_TX_3* 84 24 CPU_CFG<2> CFG_2
PEG_RX_1 =PEG_D2R_P<1> 8
IN
RSVD_L12 L12 TP_CPU_RSVD<40> 7
TP_CPU_FDI_TX_N<4> IN CPU_CFG<3> F10
7 FDI_TX_4* 84 24 14 IN CFG_3 M12
PEG_RX_2 =PEG_D2R_P<2> IN 8
H10 RSVD_M12 TP_CPU_RSVD<41> 7
7 TP_CPU_FDI_TX_N<5> FDI_TX_5* 84 24 IN CPU_CFG<4> CFG_4
PEG_RX_3 =PEG_D2R_P<3> IN 8
H9 A4
7 TP_CPU_FDI_TX_N<6> FDI_TX_6* 84 24 IN CPU_CFG<5> CFG_5 RSVD_NCTF_A4 TP_CPU_RSVD_NCTF<1>
PEG_RX_4 =PEG_D2R_P<4> IN 8
E9 AU40
7 TP_CPU_FDI_TX_N<7> FDI_TX_7* 84 24 IN CPU_CFG<6> CFG_6 RSVD_NCTF_AU40 TP_CPU_RSVD_NCTF<2>
PEG_RX_5 =PEG_D2R_P<5> IN 8
F9
84 24 CPU_CFG<7> CFG_7 RSVD_NCTF_AV1 AV1 TP_CPU_RSVD_NCTF<3>
TP_CPU_FDI_TX_P<0> =PEG_D2R_P<6> IN
7 FDI_TX_0 PEG_RX_6 IN 8
G12 AV39
84 24 IN CPU_CFG<8> CFG_8 RSVD_NCTF_AV39 TP_CPU_RSVD_NCTF<4>
7 TP_CPU_FDI_TX_P<1> FDI_TX_1 PEG_RX_7 =PEG_D2R_P<7> IN 8
H12
84 24 CPU_CFG<9> CFG_9 RSVD_NCTF_AW2 AW2 TP_CPU_RSVD_NCTF<5>
TP_CPU_FDI_TX_P<2> =PEG_D2R_P<8> IN
7 FDI_TX_2 PEG_RX_8 IN 8
K10 AW38
84 24 IN CPU_CFG<10> CFG_10 RSVD_NCTF_AW38 TP_CPU_RSVD_NCTF<6>
7 TP_CPU_FDI_TX_P<3> FDI_TX_3 PEG_RX_9 =PEG_D2R_P<9> IN 8
K8
84 24 CPU_CFG<11> CFG_11 RSVD_NCTF_AY3 AY3 TP_CPU_RSVD_NCTF<7>
TP_CPU_FDI_TX_P<4> =PEG_D2R_P<10> IN
7 FDI_TX_4 PEG_RX_10 IN 8
J12 AY37
84 24 IN CPU_CFG<12> CFG_12 RSVD_NCTF_AY37 TP_CPU_RSVD_NCTF<8>
7 TP_CPU_FDI_TX_P<5> FDI_TX_5 PEG_RX_11 =PEG_D2R_P<11> IN 8
L8 B3
84 24 IN CPU_CFG<13> CFG_13 RSVD_NCTF_B3 TP_CPU_RSVD_NCTF<9>
7 TP_CPU_FDI_TX_P<6> FDI_TX_6 PEG_RX_12 =PEG_D2R_P<12> IN 8
K9 C2
84 24 CPU_CFG<14> CFG_14 RSVD_NCTF_C2 TP_CPU_RSVD_NCTF<10>
C
IN
C 7

7
TP_CPU_FDI_TX_P<7>

TP_CPU_FDI_FSYNC<0>
FDI_TX_7

FDI_FSYNC_0
PEG_RX_13
PEG_RX_14
=PEG_D2R_P<13>
=PEG_D2R_P<14>
IN
IN
8

8
84 24

84 24
IN CPU_CFG<15>
CPU_CFG<16>
K12
H7
CFG_15
CFG_16
RSVD_NCTF_D1 D1 TP_CPU_RSVD_NCTF<11>

=PEG_D2R_P<15> IN AN11 TP_CPU_RSVD_TP<1>

PEG_RX_15 IN 8
L11 RSVD_TP_AN11
7 TP_CPU_FDI_FSYNC<1> FDI_FSYNC_1 84 24 IN CPU_CFG<17> CFG_17
INTEL SUGGESTS TO KEEP THESE TPS
PEG_TX_0* =PEG_R2D_C_N<0> OUT 8
7 TP_CPU_FDI_INT FDI_INT
PEG_TX_1* =PEG_R2D_C_N<1> OUT 8

7 TP_CPU_FDI_LSYNC<0> FDI_LSYNC_0 PEG_TX_2* =PEG_R2D_C_N<2> OUT 8

7 TP_CPU_FDI_LSYNC<1> FDI_LSYNC_1 PEG_TX_3* =PEG_R2D_C_N<3> OUT 8 FOR LYNNFIELD PROCESSOR

PEG_TX_4* =PEG_R2D_C_N<4> OUT 8 CFG [1:0] :PCIE CONFIGURATION SELECT 11 = 1 X16 PCI EXPRESS 10 = 2 X8 PCI EXPRESS
PEG_TX_5* =PEG_R2D_C_N<5> OUT 8 FOR CLARKDALE PROCESSOR
PEG_TX_6* =PEG_R2D_C_N<6> OUT 8 CFG3 :PCIE LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
PEG_TX_7* =PEG_R2D_C_N<7> OUT 8 CFG4 :NOT USED ON DESKTOP
PEG_TX_8* =PEG_R2D_C_N<8> OUT 8

PEG_TX_9* =PEG_R2D_C_N<9> OUT 8

PEG_TX_10* =PEG_R2D_C_N<10> OUT 8

PEG_TX_11* =PEG_R2D_C_N<11> OUT 8

PEG_TX_12* =PEG_R2D_C_N<12> OUT 8

PEG_TX_13* =PEG_R2D_C_N<13> OUT 8

PEG_TX_14* =PEG_R2D_C_N<14> OUT 8

PEG_TX_15* =PEG_R2D_C_N<15> OUT 8

PEG_TX_0 =PEG_R2D_C_P<0> OUT 8

PEG_TX_1 =PEG_R2D_C_P<1> OUT 8

PEG_TX_2 =PEG_R2D_C_P<2> OUT 8

PEG_TX_3 =PEG_R2D_C_P<3> OUT 8

PEG_TX_4 =PEG_R2D_C_P<4> OUT 8

PEG_TX_5 =PEG_R2D_C_P<5> OUT 8

PEG_TX_6 =PEG_R2D_C_P<6>
B PEG_TX_7 =PEG_R2D_C_P<7>
OUT
OUT
8

8 B
PEG_TX_8 =PEG_R2D_C_P<8> OUT 8

PEG_TX_9 =PEG_R2D_C_P<9> OUT 8

PEG_TX_10 =PEG_R2D_C_P<10> OUT 8

PEG_TX_11 =PEG_R2D_C_P<11> OUT 8

PEG_TX_12 =PEG_R2D_C_P<12> OUT 8

PEG_TX_13 =PEG_R2D_C_P<13> OUT 8

PEG_TX_14 =PEG_R2D_C_P<14> OUT 8

PEG_TX_15 =PEG_R2D_C_P<15> OUT 8

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

65 47 15 12 10 5 =PPVTT_S0_CPU

1 R1101 1 1 1
R1100 51 R1104 R1103
51 5% 51 1K
5% 1/16W 5% 5%
1/16W MF-LF 1/16W 1/16W
MF-LF 402 MF-LF MF-LF
2

D
2
402

84 CPU_COMP3
2 402
2
402

C11 COMP3 U1000 BCLK_0 AA7 FSB_CLK133M_CPU_P IN 20 84

D
CPU_COMP2 B11 AA6 FSB_CLK133M_CPU_N
84

AF2
COMP2 LYNNFIELD BCLK_0* IN 20 84

84 CPU_COMP1 COMP1 LGA1156-SKT AA8

AF36 BCLK_1 GFX_CLK120M_DPLLSS_P IN 17 84
84 CPU_COMP0 COMP0 (2 OF 10) Y8
BCLK_1* GFX_CLK120M_DPLLSS_N IN 17 84
OMIT

MISC
AK39 FSB_CLK133M_ITP_P

CLOCKS
R1110 1 R1112 1 63 CPU_SKTOCC_L AK38 SKTOCC* BCLK_ITP OUT 24 84

20 49.9 BCLK_ITP* AK40 FSB_CLK133M_ITP_N 24 84

OUT
1% 1% (GND)
1/16W 1/16W
MF-LF MF-LF PEG_CLK AA3 PCIE_CLK100M_CPU_P 17 84
IN
402 402
2 2 CPU_CATERR_L AG39 CATERR* PEG_CLK* AA4 PCIE_CLK100M_CPU_N 17 84
IN

1 1
SM_DRAMRST* AV8 CPU_MEM_RESET_L
R1111 R1113 CPU_PECI AG35 PECI OUT 26 91

THERMAL
20 BI
20 49.9

DDR3
MISC
1% 1% SM_RCOMP_0 AG1 83 CPU_SM_RCOMP0
1/16W 1/16W
MF-LF MF-LF SM_RCOMP_1 AD1 83 CPU_SM_RCOMP1
402 402 47 CPU_PROCHOT_L AH34 PROCHOT*
2 2 BI AE1 CPU_SM_RCOMP2
SM_RCOMP_2 83

PM_EXT_TS_0* AB5 =PPVTT_S0_CPU 5 10 12 15 47 65

PM_THRMTRIP_L AF35 THERMTRIP*
PLACE
PLACE
R1110
R1111
CLOSE
CLOSE
TO
TO
C11
B11
91 47 20 OUT
PM_EXT_TS_1* AB4 R1160 1 R1162 1
PLACE R1112 CLOSE TO AF2 130 100
PLACE R1113 CLOSE TO AF36 1% 1%
1/16W 1/16W
PRDY* AJ38 XDP_PRDY_L 24 MF-LF MF-LF
FSB_CPURSTOUT_L AL39 RESET_OBS* OUT
91 24 OUT 402 402
PREQ* AK37 XDP_PREQ_L 24
2 2
IN

TCK AN37 XDP_TCK 24

PM_SYNC AH39 PM_SYNC IN 1
91 18 IN
TMS AN40 XDP_TMS R1161

PWR MANAGEMENT
IN 24
65 47 15 12 10 5 =PPVTT_S0_CPU 24.9
TRST* AM39 XDP_TRST_L 24 1%
IN

JTAG & MBP

1/16W
AH36 VCCPWRGOOD_1 MF-LF
AM37 XDP_TDI
R1122 1 TDI IN 24
2
402

C 1.1K
1%
1/16W
MF-LF
91 24 20 IN CPU_PWRGD AH35 VCCPWRGOOD_0
TDO

TDI_M
AM38

AF37
XDP_TDO

CPU_TDO_M_TDI_M
OUT 24

PLACE R1160 CLOSE TO AE1

C
402
2 AF38 PLACE R1161 CLOSE TO AD1
TDO_M PLACE R1162 CLOSE TO AG1
91 18 10 PM_MEM_PWRGD AH37 SM_DRAMPWROK
IN AL40 XDP_DBRESET_L
DBR* OUT 24 27 91

BPM_0* AL33 XDP_BPM_L<0> 24 84

CPUVTT_REG_PGOOD AG37 VTTPWRGOOD OUT
91 68 64 63 IN
COMES FROM VTT VR BPM_1* AL32 XDP_BPM_L<1> 24 84
OUT
BPM_2* AK33 XDP_BPM_L<2> 24 84
OUT
91 24 XDP_CPUPWRGD AK34 TAPPWRGOOD BPM_3* AK32 XDP_BPM_L<3> 24 84
OUT OUT
BPM_4* AM31 XDP_BPM_L<4> 24 84
OUT
BPM_5* AL30 XDP_BPM_L<5> 24 84
PLT_RESET_LS1V1_L AF34 RSTIN* OUT
91 10
BPM_6* AK30 XDP_BPM_L<6> 24 84
OUT
NOSTUFF AK31
BPM_7* XDP_BPM_L<7> OUT 24 84
C1100 1
0.1UF
10% 1
16V
2
R1170
X7R-CERM
402
51
5%
1/16W
MF-LF
402
2

PM_MEM_PWRGD MUST ASSERT MIN. 100 NS AFTER =PP1V5_CPU_MEM IS STABLE

PRIMARY SOLUTION: PULL PM_MEM_PWRGD TO CPU VTT, WHICH RISES SEVERAL MS AFTER 1.5V. STUFF R1122
CPU RESET LEVEL SHIFTER
B BACKUP SOLUTION (FOR CLEANER EDGE): PULL TO 1.5V (DIVIDED) AND DELAY PGOOD. NO-STUFF R1122, STUFF CIRCUIT BELOW
5 =PP3V3_S5_CPURESET =PPVTT_S0_CPU 5 10 12 15 47 65
B
R1180-R1182 PROVIDE OPTIONS TO TRIGGER FROM RISE OF 1.5V, OR FROM PGOOD
C1180 CAN BE TUNED FOR SPECIFIC DELAY
R11271
150
29 15 12 10 5 =PP1V5_CPU_MEM 1%
1/16W

NOSTUFF R11261 MF-LF

402
2
R1120 1 10K
1%
1.1K 1/16W
1% MF-LF PLT_RESET_LS1V1_L 10 91
1/16W 402
MF-LF
2
402
2
3
64 63 5 =PP3V3_S5_PWRCTL PM_MEM_PWRGD 10 18 91
5 Q1177
PLT_RESET_LS3V3 MMDT3904-X-G
SOT-363-LF

4
1 NOSTUFF
R1183 1
NOSTUFF
R1121
R1125 6
29 15 12 10 5 =PP1V5_CPU_MEM 10K 10K 2
Q1177
5% 6 3.01K 91 27 IN CPU_RESET_L 2 1 CPU_RESET_L_R MMDT3904-X-G
1/16W NOSTUFF 1%
SOT-363-LF
1%
1NOSTUFF 2
MF-LF
402
D Q1180 1/16W
MF-LF 1/16W
MF-LF 1
R1181 DMB53D0UV 2
402
402
27.4K SOT-563
1%
1/16W PM_MEM_PWRGD_L 2 G
MF-LF
402
2
NOSTUFF
R1180 3 NOSTUFF S
0
91 73 IN PGOOD_P1V5_S0 2 1 PGOOD_P1V5_S0_DLY
5 Q1180 1
5%
1/16W
DMB53D0UV
SOT-563
A MF-LF
402
NOSTUFF 1
R1182
33.2K
NOSTUFF
C1180 1 4
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
1%
100PF PAGE TITLE
1/16W
MF-LF
402
2
5%
50V
CERM 2
402
CPU CLOCK/MISC/JTAG
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

83 32 BI MEM_A_DQ<0>
MEM_A_DQ<1>
AH1 SA_DQ_0
AJ4 SA_DQ_1 U1000 SA_CK_0 AR22
AR21
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
OUT 32 83 83 32 BI MEM_B_DQ<0>
MEM_B_DQ<1>
AD7
AD6
SB_DQ_0 U1000 SB_CK_0 AR17
AR16
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT 32 83

SA_CK_0* SB_DQ_1
83 32

83 32
BI
MEM_A_DQ<2> AL2 SA_DQ_2 LYNNFIELD
OUT 32 83 83 32

83 32
BI
MEM_B_DQ<2> AH8 SB_DQ_2
LYNNFIELD SB_CK_0* OUT 32 83

BI AU10 BI AW8
MEM_A_DQ<3> AL1 SA_DQ_3 LGA1156-SKT SA_CKE_0 MEM_A_CKE<0> OUT 30 83
MEM_B_DQ<3> AJ8 LGA1156-SKT SB_CKE_0 MEM_B_CKE<0> OUT 31 83
83 32 BI 83 32 BI SB_DQ_3
83 32 MEM_A_DQ<4> AG2 SA_DQ_4 (3 OF 10) SA_CK_1 AP18 MEM_A_CLK_P<1> 32 83 83 32 MEM_B_DQ<4> AC7 SB_DQ_4 (4 OF 10) SB_CK_1 AT15 MEM_B_CLK_P<1> 32 83
BI OUT BI OUT
83 32 MEM_A_DQ<5> AH2 SA_DQ_5 OMIT SA_CK_1* AN18 MEM_A_CLK_N<1> 32 83 83 32 MEM_B_DQ<5> AC6 SB_DQ_5 OMIT SB_CK_1* AR15 MEM_B_CLK_N<1> 32 83
BI OUT BI OUT
83 32 MEM_A_DQ<6> AK1 SA_DQ_6 83 32 MEM_B_DQ<6> AF5 SB_DQ_6
BI AW10 MEM_A_CKE<1> BI AY9 MEM_B_CKE<1>
AK2 SA_DQ_7 SA_CKE_1 OUT 30 83
AE6 SB_CKE_1 OUT 31 83
83 32 BI MEM_A_DQ<7> 83 32 BI MEM_B_DQ<7> SB_DQ_7
83 32 MEM_A_DQ<8> AN3 SA_DQ_8 SA_CK_2 AN21 MEM_A_CLK_P<2> 32 83 83 32 MEM_B_DQ<8> AG5 SB_DQ_8 SB_CK_2 AN17 MEM_B_CLK_P<2> 32 83
BI OUT BI OUT
MEM_A_DQ<9> AN2 SA_DQ_9 SA_CK_2* AP21 MEM_A_CLK_N<2> MEM_B_DQ<9> AH7 SB_DQ_9 SB_CK_2* AN16 MEM_B_CLK_N<2>

D
83 32

83 32
BI
BI MEM_A_DQ<10> AR3 SA_DQ_10
AR2 SA_DQ_11 SA_CKE_2 AV10 MEM_A_CKE<2>
OUT

OUT
32 83

30 83
83 32

83 32
BI
BI MEM_B_DQ<10> AK6
AL4
SB_DQ_10
SB_CKE_2 AU9 MEM_B_CKE<2>
OUT

OUT
32 83

31 83
D
83 32 BI MEM_A_DQ<11> 83 32 BI MEM_B_DQ<11> SB_DQ_11
83 32 MEM_A_DQ<12> AM3 SA_DQ_12 SA_CK_3 AP19 MEM_A_CLK_P<3> 32 83 83 32 MEM_B_DQ<12> AG6 SB_DQ_12 SB_CK_3 AR19 MEM_B_CLK_P<3> 32 83
BI OUT BI OUT
83 32 MEM_A_DQ<13> AM2 SA_DQ_13 SA_CK_3* AN19 MEM_A_CLK_N<3> 32 83 83 32 MEM_B_DQ<13> AG4 SB_DQ_13 SB_CK_3* AR18 MEM_B_CLK_N<3> 32 83
BI OUT BI OUT
83 32 MEM_A_DQ<14> AP1 SA_DQ_14 83 32 MEM_B_DQ<14> AJ7 SB_DQ_14
BI
SA_CKE_3 AY10 MEM_A_CKE<3> 30 83
BI
SB_CKE_3 AV9 MEM_B_CKE<3> 31 83
MEM_A_DQ<15> AR4 SA_DQ_15 OUT MEM_B_DQ<15> AK7 OUT
83 32 BI 83 32 BI SB_DQ_15
83 32 MEM_A_DQ<16> AT4 SA_DQ_16 SA_CS_0* AV21 MEM_A_CS_L<0> 30 83 83 32 MEM_B_DQ<16> AL6 SB_DQ_16 SB_CS_0* AY27 MEM_B_CS_L<0> 31 83
BI OUT BI OUT

DDR SYSTEM MEMORY A

83 32 MEM_A_DQ<17> AU2 SA_DQ_17 SA_CS_1* AW24 MEM_A_CS_L<1> 30 83 83 32 MEM_B_DQ<17> AN5 SB_DQ_17 SB_CS_1* AW29 MEM_B_CS_L<1> 31 83
BI OUT BI OUT
83 32 MEM_A_DQ<18> AW3 SA_DQ_18 SA_CS_2* AU21 MEM_A_CS_L<2> 30 83 83 32 MEM_B_DQ<18> AP6 SB_DQ_18 SB_CS_2* AV26 MEM_B_CS_L<2> 31 83
BI OUT BI OUT
83 32 MEM_A_DQ<19> AW4 SA_DQ_19 SA_CS_3* AU23 MEM_A_CS_L<3> 30 83 83 32 MEM_B_DQ<19> AR5 SB_DQ_19 SB_CS_3* AV29 MEM_B_CS_L<3> 31 83
BI OUT BI OUT
83 32 MEM_A_DQ<20> AT3 SA_DQ_20 SA_CS_4* AK22 TP_MEM_A_CS_L<4> 7 83 32 MEM_B_DQ<20> AL5 SB_DQ_20 SB_CS_4* AM23 TP_MEM_B_CS_L<4> 7
BI BI
83 32 MEM_A_DQ<21> AT1 SA_DQ_21 SA_CS_5* AM22 TP_MEM_A_CS_L<5> 7 83 32 MEM_B_DQ<21> AM4 SB_DQ_21 SB_CS_5* AM24 TP_MEM_B_CS_L<5> 7
BI BI
83 32 MEM_A_DQ<22> AV2 SA_DQ_22 SA_CS_6* AL23 TP_MEM_A_CS_L<6> 7 83 32 MEM_B_DQ<22> AN7 SB_DQ_22 SB_CS_6* AL24 TP_MEM_B_CS_L<6> 7
BI BI
83 32 MEM_A_DQ<23> AV4 SA_DQ_23 SA_CS_7* AK23 TP_MEM_A_CS_L<7> 7 83 32 MEM_B_DQ<23> AP5 SB_DQ_23 SB_CS_7* AK24 TP_MEM_B_CS_L<7> 7
BI BI
83 32 MEM_A_DQ<24> AW5 SA_DQ_24 83 32 MEM_B_DQ<24> AT6 SB_DQ_24
BI AV23 MEM_A_ODT<0> BI AU27 MEM_B_ODT<0>
AY5 SA_DQ_25 SA_ODT_0 OUT 30 83
AR7 SB_ODT_0 OUT 31 83
83 32 BI MEM_A_DQ<25> 83 32 BI MEM_B_DQ<25> SB_DQ_25 AU29
SA_ODT_1 AV24 MEM_A_ODT<1> 30 83 SB_ODT_1 MEM_B_ODT<1> 31 83
MEM_A_DQ<26> AU8 SA_DQ_26 OUT MEM_B_DQ<26> AR9 OUT
83 32 BI AW23 83 32 BI SB_DQ_26 AV27
SA_ODT_2 MEM_A_ODT<2> OUT 30 83
AM8 SB_ODT_2 MEM_B_ODT<2> OUT 31 83
83 32 MEM_A_DQ<27> AY8 SA_DQ_27 83 32 MEM_B_DQ<27> SB_DQ_27
BI AY24 MEM_A_ODT<3> BI AU28 MEM_B_ODT<3>
AU5 SA_DQ_28 SA_ODT_3 OUT 30 83
AN8 SB_ODT_3 OUT 31 83
83 32 BI MEM_A_DQ<28> 83 32 BI MEM_B_DQ<28> SB_DQ_28
83 32 MEM_A_DQ<29> AV5 SA_DQ_29 SA_DM_0 AJ2 MEM_A_DM<0> 32 83 83 32 MEM_B_DQ<29> AR6 SB_DQ_29 SB_DM_0 AE4 MEM_B_DM<0> 32 83
BI OUT BI OUT
83 32 MEM_A_DQ<30> AV7 SA_DQ_30 SA_DM_1 AN1 MEM_A_DM<1> 32 83 83 32 MEM_B_DQ<30> AL8 SB_DQ_30 SB_DM_1 AH4 MEM_B_DM<1> 32 83
BI OUT BI OUT
83 32 MEM_A_DQ<31> AW7 SA_DQ_31 SA_DM_2 AU1 MEM_A_DM<2> 32 83 83 32 MEM_B_DQ<31> AT9 SB_DQ_31 SB_DM_2 AM7 MEM_B_DM<2> 32 83
BI OUT BI OUT
83 32 MEM_A_DQ<32> AN27 SA_DQ_32 SA_DM_3 AV6 MEM_A_DM<3> 32 83 83 32 MEM_B_DQ<32> AN23 SB_DQ_32 SB_DM_3 AT7 MEM_B_DM<3> 32 83
BI OUT BI OUT
83 32 MEM_A_DQ<33> AT28 SA_DQ_33 SA_DM_4 AN29 MEM_A_DM<4> 32 83 83 32 MEM_B_DQ<33> AP23 SB_DQ_33 SB_DM_4 AN24 MEM_B_DM<4> 32 83
BI OUT BI OUT

DDR SYSTEM MEMORY B

83 32 MEM_A_DQ<34> AP28 SA_DQ_34 SA_DM_5 AW31 MEM_A_DM<5> 32 83 83 32 MEM_B_DQ<34> AR25 SB_DQ_34 SB_DM_5 AN32 MEM_B_DM<5> 32 83
BI OUT BI OUT
83 32 MEM_A_DQ<35> AP30 SA_DQ_35 SA_DM_6 AU35 MEM_A_DM<6> 32 83 83 32 MEM_B_DQ<35> AR26 SB_DQ_35 SB_DM_6 AM33 MEM_B_DM<6> 32 83
BI OUT BI OUT

C 83 32

83 32
BI
BI
MEM_A_DQ<36>
MEM_A_DQ<37>
AN26 SA_DQ_36
AR27 SA_DQ_37
SA_DM_7

SA_DQS_0*
AT38

AJ3
MEM_A_DM<7>

MEM_A_DQS_N<0>
OUT 32 83

32 83
83 32

83 32
BI
BI
MEM_B_DQ<36>
MEM_B_DQ<37>
AT23
AP22
SB_DQ_36
SB_DQ_37
SB_DM_7

SB_DQS_0*
AK35

AE5
MEM_B_DM<7>

MEM_B_DQS_N<0>
OUT 32 83

32 83
C
MEM_A_DQ<38> AR29 SA_DQ_38 BI MEM_B_DQ<38> AP25 BI
83 32 BI AP3 83 32 BI SB_DQ_38 AJ5
SA_DQS_1* MEM_A_DQS_N<1> BI 32 83 SB_DQS_1* MEM_B_DQS_N<1> BI 32 83
83 32 MEM_A_DQ<39> AN30 SA_DQ_39 83 32 MEM_B_DQ<39> AT26 SB_DQ_39
BI AU3 MEM_A_DQS_N<2> BI AM6 MEM_B_DQS_N<2>
AU30 SA_DQ_40 SA_DQS_2* BI 32 83
AT32 SB_DQS_2* BI 32 83
83 32 BI MEM_A_DQ<40> AW6 83 32 BI MEM_B_DQ<40> SB_DQ_40 AP8
SA_DQS_3* MEM_A_DQS_N<3> BI 32 83 SB_DQS_3* MEM_B_DQS_N<3> BI 32 83
83 32 MEM_A_DQ<41> AU31 SA_DQ_41 83 32 MEM_B_DQ<41> AP31 SB_DQ_41
BI AT29 MEM_A_DQS_N<4> BI AR24 MEM_B_DQS_N<4>
AV33 SA_DQ_42 SA_DQS_4* BI 32 83
AR33 SB_DQS_4* BI 32 83
83 32 BI MEM_A_DQ<42> 83 32 BI MEM_B_DQ<42> SB_DQ_42
SA_DQS_5* AW32 MEM_A_DQS_N<5> 32 83 SB_DQS_5* AR32 MEM_B_DQS_N<5> 32 83
MEM_A_DQ<43> AU34 SA_DQ_43 BI MEM_B_DQ<43> AM32 BI
83 32 BI AV35 83 32 BI SB_DQ_43 AR37
SA_DQS_6* MEM_A_DQS_N<6> BI 32 83 SB_DQS_6* MEM_B_DQS_N<6> BI 32 83
83 32 MEM_A_DQ<44> AV30 SA_DQ_44 83 32 MEM_B_DQ<44> AT31 SB_DQ_44
BI AR38 MEM_A_DQS_N<7> BI AM36 MEM_B_DQS_N<7>
AW30 SA_DQ_45 SA_DQS_7* BI 32 83
AR31 SB_DQS_7* BI 32 83
83 32 BI MEM_A_DQ<45> AM10 83 32 BI MEM_B_DQ<45> SB_DQ_45 AR13
SA_DQS_8* TP_MEM_A_DQS_N<8> 7
AR34 SB_DQS_8* TP_MEM_B_DQS_N<8> 7
83 32 MEM_A_DQ<46> AU33 SA_DQ_46 83 32 MEM_B_DQ<46> SB_DQ_46
BI BI
83 32 MEM_A_DQ<47> AW33 SA_DQ_47 SA_DQS_0 AK3 MEM_A_DQS_P<0> 32 83 83 32 MEM_B_DQ<47> AT33 SB_DQ_47 SB_DQS_0 AF4 MEM_B_DQS_P<0> 32 83
BI BI BI BI
83 32 MEM_A_DQ<48> AW35 SA_DQ_48 SA_DQS_1 AP2 MEM_A_DQS_P<1> 32 83 83 32 MEM_B_DQ<48> AR35 SB_DQ_48 SB_DQS_1 AH6 MEM_B_DQS_P<1> 32 83
BI BI BI BI
83 32 MEM_A_DQ<49> AY35 SA_DQ_49 SA_DQS_2 AU4 MEM_A_DQS_P<2> 32 83 83 32 MEM_B_DQ<49> AT36 SB_DQ_49 SB_DQS_2 AN6 MEM_B_DQS_P<2> 32 83
BI BI BI BI
83 32 MEM_A_DQ<50> AV37 SA_DQ_50 SA_DQS_3 AY6 MEM_A_DQS_P<3> 32 83 83 32 MEM_B_DQ<50> AN33 SB_DQ_50 SB_DQS_3 AR8 MEM_B_DQS_P<3> 32 83
BI BI BI BI
83 32 MEM_A_DQ<51> AU37 SA_DQ_51 SA_DQS_4 AR28 MEM_A_DQS_P<4> 32 83 83 32 MEM_B_DQ<51> AP36 SB_DQ_51 SB_DQS_4 AT25 MEM_B_DQS_P<4> 32 83
BI BI BI BI
83 32 MEM_A_DQ<52> AY34 SA_DQ_52 SA_DQS_5 AV32 MEM_A_DQS_P<5> 32 83 83 32 MEM_B_DQ<52> AP34 SB_DQ_52 SB_DQS_5 AP32 MEM_B_DQS_P<5> 32 83
BI BI BI BI
83 32 MEM_A_DQ<53> AW34 SA_DQ_53 SA_DQS_6 AW36 MEM_A_DQS_P<6> 32 83 83 32 MEM_B_DQ<53> AT35 SB_DQ_53 SB_DQS_6 AR36 MEM_B_DQS_P<6> 32 83
BI BI BI BI
83 32 MEM_A_DQ<54> AV36 SA_DQ_54 SA_DQS_7 AR39 MEM_A_DQS_P<7> 32 83 83 32 MEM_B_DQ<54> AN34 SB_DQ_54 SB_DQS_7 AL37 MEM_B_DQS_P<7> 32 83
BI BI BI BI
83 32 MEM_A_DQ<55> AW37 SA_DQ_55 SA_DQS_8 AL10 TP_MEM_A_DQS_P<8> 7 83 32 MEM_B_DQ<55> AP37 SB_DQ_55 SB_DQS_8 AR14 TP_MEM_B_DQS_P<8> 7
BI BI
83 32 MEM_A_DQ<56> AT39 SA_DQ_56 83 32 MEM_B_DQ<56> AL35 SB_DQ_56
BI AW18 MEM_A_A<0> BI AU20 MEM_B_A<0>
AT40 SA_DQ_57 SA_MA_0 OUT 30 83
AM35 SB_MA_0 OUT 31 83
83 32 BI MEM_A_DQ<57> 83 32 BI MEM_B_DQ<57> SB_DQ_57 AU18
SA_MA_1 AY15 MEM_A_A<1> 30 83 SB_MA_1 MEM_B_A<1> 31 83
MEM_A_DQ<58> AN38 SA_DQ_58 OUT MEM_B_DQ<58> AJ36 OUT
83 32 BI AV15 83 32 BI SB_DQ_58 AV18
AN39 SA_DQ_59 SA_MA_2 MEM_A_A<2> OUT 30 83
AJ37 SB_MA_2 MEM_B_A<2> OUT 31 83
83 32 BI MEM_A_DQ<59> 83 32 BI MEM_B_DQ<59> SB_DQ_59 AU17
SA_MA_3 AU15 MEM_A_A<3> 30 83 SB_MA_3 MEM_B_A<3> 31 83
MEM_A_DQ<60> AU38 SA_DQ_60 OUT MEM_B_DQ<60> AN35 OUT
83 32 BI AW14 83 32 BI SB_DQ_60 AY18
AU39 SA_DQ_61 SA_MA_4 MEM_A_A<4> OUT 30 83
AM34 SB_MA_4 MEM_B_A<4> OUT 31 83
83 32 BI MEM_A_DQ<61> 83 32 BI MEM_B_DQ<61> SB_DQ_61 AV17
SA_MA_5 AY13 MEM_A_A<5> 30 83 SB_MA_5 MEM_B_A<5> 31 83
MEM_A_DQ<62> AP39 SA_DQ_62 OUT MEM_B_DQ<62> AJ35 OUT
SB_DQ_62
B
83 32

83 32
BI
BI MEM_A_DQ<63> AP40 SA_DQ_63 SA_MA_6
SA_MA_7
AV14
AW13
MEM_A_A<6>
MEM_A_A<7>
OUT
OUT
30 83

30 83
83 32

83 32
BI
BI MEM_B_DQ<63> AL36 SB_DQ_63
SB_MA_6
SB_MA_7
AW17
AU16
MEM_B_A<6>
MEM_B_A<7>
OUT
OUT
31 83

31 83
B
83 30 MEM_A_BA<0> AV20 SA_BS_0 SA_MA_8 AU14 MEM_A_A<8> 30 83 83 31 MEM_B_BA<0> AU25 SB_BS_0 SB_MA_8 AT17 MEM_B_A<8> 31 83
OUT OUT OUT OUT
83 30 MEM_A_BA<1> AU19 SA_BS_1 SA_MA_9 AW12 MEM_A_A<9> 30 83 83 31 MEM_B_BA<1> AW25 SB_BS_1 SB_MA_9 AY16 MEM_B_A<9> 31 83
OUT OUT OUT OUT
83 30 MEM_A_BA<2> AU12 SA_BS_2 SA_MA_10 AT19 MEM_A_A<10> 30 83 83 31 MEM_B_BA<2> AV12 SB_BS_2 SB_MA_10 AY25 MEM_B_A<10> 31 83
OUT OUT OUT OUT
SA_MA_11 AU13 MEM_A_A<11> 30 83 SB_MA_11 AW16 MEM_B_A<11> 31 83
MEM_A_CAS_L AU22 SA_CAS* OUT MEM_B_CAS_L AW27 SB_CAS* OUT
83 30 OUT 83 31 OUT
SA_MA_12 AW11 MEM_A_A<12> 30 83 SB_MA_12 AW15 MEM_B_A<12> 31 83
MEM_A_RAS_L AT20 SA_RAS* OUT MEM_B_RAS_L AW26 SB_RAS* OUT
83 30 83 31
OUT
SA_MA_13 AU24 MEM_A_A<13> 30 83
OUT
SB_MA_13 AW28 MEM_B_A<13> 31 83
MEM_A_WE_L AT22 SA_WE* OUT MEM_B_WE_L AU26 SB_WE* OUT
83 30 OUT 83 31 OUT
SA_MA_14 AT11 MEM_A_A<14> 30 83 SB_MA_14 AY12 MEM_B_A<14> 31 83
OUT OUT
83 28 CPU_DIMM_VREF_A AF3 SA_DIMM_VREFDQ SA_MA_15 AR10 MEM_A_A<15> 30 83 83 28 CPU_DIMM_VREF_B AG3 SB_DIMM_VREFDQ SB_MA_15 AV11 MEM_B_A<15> 31 83
OUT OUT OUT OUT

SA_ECC_CB_0 AP10 TP_MEM_A_DQ_CB<0> 7 SB_ECC_CB_0 AR12 TP_MEM_B_DQ_CB<0> 7

SA_ECC_CB_1 AN10 TP_MEM_A_DQ_CB<1> 7 SB_ECC_CB_1 AT13 TP_MEM_B_DQ_CB<1> 7

SA_ECC_CB_2 AR11 TP_MEM_A_DQ_CB<2> 7 SB_ECC_CB_2 AN15 TP_MEM_B_DQ_CB<2> 7

SA_ECC_CB_3 AP11 TP_MEM_A_DQ_CB<3> 7 SB_ECC_CB_3 AP14 TP_MEM_B_DQ_CB<3> 7

SA_ECC_CB_4 AK9 TP_MEM_A_DQ_CB<4> 7 SB_ECC_CB_4 AM12 TP_MEM_B_DQ_CB<4> 7

SA_ECC_CB_5 AL9 TP_MEM_A_DQ_CB<5> 7 SB_ECC_CB_5 AN12 TP_MEM_B_DQ_CB<5> 7

SA_ECC_CB_6 AK11 TP_MEM_A_DQ_CB<6> 7 SB_ECC_CB_6 AN14 TP_MEM_B_DQ_CB<6> 7

SA_ECC_CB_7 AM11 TP_MEM_A_DQ_CB<7> 7 SB_ECC_CB_7 AP13 TP_MEM_B_DQ_CB<7> 7

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

CPU DDR3 INTERFACES

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

D J25
J27
VCC_103
LGA1156-SKT
(10 OF 10)
B28
B29
VCC_10
VCC_11
VTT_10
VTT_11
AC36
AC37 D
VCC_104 OMIT B31 AC38
J28 VCC_12 VTT_12
VCC_105 B32 AC39
J30 VCC_13 VTT_13 5 =PPVAXG_S0_CPU
J31
VCC_106
VCC_107
B34 VCC_14 VTT_14 AC40 THIS SUPPLY IS NEEDED ONLY FOR SYSTEM WITH DALE IG
A14 VAXG_0 U1000
B35 AC5 A15
J33 VCC_108 B37
VCC_15 VTT_15
AC8 A17
VAXG_1 LYNNFIELD
J34 VCC_16 VTT_16 VAXG_2 LGA1156-SKT
VCC_109 B38 AD33 A18
J36 VCC_17 VTT_17 VAXG_3 ( 7 OF 10 )
VCC_110 C23 AD34 B14
VCC_18 VTT_18 VAXG_4 OMIT

SENSE
LINES
J37 VCC_111 VSSAXG_SENSE B13 TP_GFX_VSENSE_N 7
C24 VCC_19 VTT_19 AD35 B15 VAXG_5
J39 VCC_112 VAXG_SENSE A13 TP_GFX_VSENSE_P 7
C25 VCC_20 VTT_20 AD36 B17 VAXG_6
J40 VCC_113 C27 VCC_21 VTT_21 AD37 B18 VAXG_7
K17 VCC_114 C28 VCC_22 VTT_22 AD38 C14 VAXG_8 GFX_VID_0 G10 TP_GFX_VID<0> 7
K18 VCC_115 C30 VCC_23 VTT_23 AD39 C15 VAXG_9 GFX_VID_1 B12 TP_GFX_VID<1> 7
K20 VCC_116 C31 VCC_24 VTT_24 AD40 C17 VAXG_10 GFX_VID_2 E12 TP_GFX_VID<2> 7
K21

GRAPHICS VIDS
VCC_117 C33 AE33 C18 E11
VCC_25 VTT_25 VAXG_11 GFX_VID_3 TP_GFX_VID<3> 7
K23 VCC_118 C34 VCC_26 VTT_26 AE34 C20 VAXG_12 GFX_VID_4 C12 TP_GFX_VID<4> 7
K24 VCC_119 C36 VCC_27 VTT_27 AE39 C21 VAXG_13 GFX_VID_5 G11 TP_GFX_VID<5> 7
K26 VCC_120 C37 VCC_28 VTT_28 AE40 D14 VAXG_14 GFX_VID_6 J11 TP_GFX_VID<6> 7
K27 VCC_121 C39 VCC_29 VTT_29 AE8 D15 VAXG_15
K29 VCC_122 GFX_VR_EN F12 TP_GFX_VR_EN
D23 VCC_30 VTT_30 AF33 D17 VAXG_16
K30 VCC_123 GFX_DPRSLPVR J10 TP_GFX_DPRSLPVR
D24 VCC_31 VTT_31 AG33 D18 VAXG_17
K32 VCC_124 GFX_IMON F6
D26 VCC_32 VTT_32 AJ17 D20 VAXG_18
K33 VCC_125 D27 VCC_33 VTT_33 AJ19 D21 VAXG_19 =PP1V5_CPU_MEM 5 10 15 29
K35 VCC_126 D29 VCC_34 VTT_34 AJ21 E14 VAXG_20 VDDQ_0 AJ11
K36 VCC_127 D30 VCC_35 VTT_35 AJ23 E15 VAXG_21 VDDQ_1 AJ13
K38

GRAPHICS
VCC_128 D32 AJ25 E17 AJ15
VCC_36 VTT_36 VAXG_22 VDDQ_2
C
K39
L17
VCC_129
VCC_130
D33
D35
VCC_37
VCC_38
VTT_37
VTT_38
AJ27
AJ29
E18
E20
VAXG_23
VAXG_24
VDDQ_3
VDDQ_4
AT10
AT18
C
L19 VCC_131 D36 VCC_39 VTT_39 AJ31 F14 VAXG_25 VDDQ_5 AT21
L20 VCC_132 D38 VCC_40 VTT_40 AJ32 F15 VAXG_26 VDDQ_6 AU11

POWER
L22 VCC_133 D39 VCC_41 VTT_41 AK19 F17 VAXG_27 VDDQ_7 AV13

DDR3-1.5V RAILS
L23 VCC_134 E22 VCC_42 VTT_42 AK20 F18 VAXG_28 VDDQ_8 AV16
L25 VCC_135 E23 VCC_43 VTT_43 AK21 F19 VAXG_29 VDDQ_9 AV19
L26 VCC_136 E25 VCC_44 VTT_44 AL20 G14 VAXG_30 VDDQ_10 AV22
L28 VCC_137 E26 VCC_45 VTT_45 AL21 G15 VAXG_31 VDDQ_11 AV25
L29 VCC_138 E28 VCC_46 VTT_46 L10 G17 VAXG_32 VDDQ_12 AV28
L31 VCC_139 E29 M10 G18 AW9

1.1V RAIL POWER

L32 VCC_47 VTT_47 VAXG_33 VDDQ_13
VCC_140 E31 M11 H14 AY11
L34 VCC_48 VTT_48 VAXG_34 VDDQ_14
VCC

VCC_141 E32 M9 H15 AY14

L35 VCC_49 VTT_49 VAXG_35 VDDQ_15
VCC_142 E34 N7 H17 AY17
L37 VCC_50 VTT_50 VAXG_36 VDDQ_16
VCC_143 E35 P6 J14 AY23
L38 VCC_51 VTT_51 VAXG_37 VDDQ_17
VCC_144 E37 P7 J15 AY26
L40 VCC_52 VTT_52 VAXG_38 VDDQ_18
VCC_145 E38 P8 J16
M17 VCC_53 VTT_53 VAXG_39
VCC_146 =PP1V8_S0_CPU_PLL 5 15 64
E40 VCC_54 VTT_54 T2 K14 VAXG_40
M19 VCC_147 VCCPLL_0 AF7

1.8V
CGC_TP_NCTF B39 TP_CPU_CGC_NCTF F21 VCC_55 VTT_55 T6 K15 VAXG_41
M21 AF8
NCTF

VCC_148 F22 T7 K16 VCCPLL_1

M22 A38 VCC_56 VTT_56 VAXG_42 AG8
VCC_149 VCC_NCTF_0 =PPVCORE_S0_CPU 5 12 15 VCCPLL_2
F24 VCC_57 VTT_57 T8 L14 VAXG_43
M24 VCC_150 VCC_NCTF_1 C40
F25 VCC_58 VTT_58 V2 L15 VAXG_44
M25 VCC_151
FC_AE38 AE38 TP_CPU_FC_AE38 7
F27 VCC_59 VTT_59 V33 L16 VAXG_45
M27 VCC_152 F28 VCC_60 VTT_60 V34 M14 VAXG_46
M28 VCC_153 FC_AG40 AG40 TP_CPU_FC_AG40 7
F30 VCC_61 VTT_61 V35 M15 VAXG_47

CPU CORE SUPPLY

M30 VCC_154 F31 VCC_62 VTT_62 V36 M16 VAXG_48
M33 VCC_155
B M34
M36
VCC_156
F33
F34
VCC_63
VCC_64
VTT_63
VTT_64
V37
V38 B
VCC_157 F36 V39
M37 VCC_65 VTT_65
VCC_158 F37 V40
M39 VCC_66 VTT_66
VCC_159 F39 V6
M40 VCC_67 VTT_67
VCC_160 F40 V7

POWER
N33 VCC_68 VTT_68
VCC_161 G20 V8
N35 VCC_69 VTT_69
VCC_162 G21 W1
N36 VCC_70 VTT_70
VCC_163 G23 W6
N38 VCC_71 VTT_71
VCC_164 G24 Y33
N39 VCC_72 VTT_72
VCC_165 G26 Y34
P33 VCC_73 VTT_73
VCC_166 G27 Y35
P34 VCC_74 VTT_74
VCC_167 G29 Y36
P35 VCC_75 VTT_75
VCC_168 G30 Y37
P36 VCC_76 VTT_76
VCC_169 G32 Y38
P37 VCC_77 VTT_77
VCC_170 G33
P38 VCC_78
VCC_171 G35
P39 VCC_79
VCC_172 G36 AG38
VCC_80 PSI* CPU_PSI_L OUT 65 89
P40 VCC_173 G38 VCC_81
R33 VCC_174 VID_0/MSID_0 U40 CPU_VID<0> 15 65 89
G39 OUT
R34 VCC_82 U39
VCC_175 VID_1/MSID_1 CPU_VID<1> OUT 15 65 89
H19
CPU VIDS

R35 VCC_83 U38

VCC_176 VID_2/MSID_2 CPU_VID<2> OUT 15 65 89
H20 VCC_84
R36 VCC_177 VID_3/CSC_0 U37 CPU_VID<3> 15 65 89
H22 OUT
R37 VCC_85 U36
VCC_178 H23 VID_4/CSC_1 CPU_VID<4> OUT 15 65 89
R38 VCC_86 U35
VCC_179 H25 VID_5/CSC_2 CPU_VID<5> OUT 15 65 89
R39 VCC_87 U34
VCC_180 H26 VID_6 CPU_VID<6> OUT 15 65 89
R40 VCC_88 U33
A VCC_181 H28
H29
VCC_89
VCC_90
VID_7

VTT_SELECT AF39
CPU_VID<7>

TP_CPU_VTTSELECT
OUT 15 65 89

SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE
H31
H32
VCC_91
VCC_92
CPU POWER
SENSE LINES

H34 T40 CONNECTED TO THE IMON OUT FROM CPU REG DRAWING NUMBER SIZE
VCC_93 ISENSE VR_CPU_IOUT
H35 VCC_94
IN 65 88
Apple Inc. 051-8337 D
VCC_SENSE T35 CPU_VCC_PKG_SENSE_P 50 65 89 REVISION
H37 OUT
VCC_95
H38 VCC_96
VSS_SENSE T34 CPU_VCC_PKG_SENSE_N OUT 65 89
R
A.0.0
H40 AE35 CPU_VTTSENSE_P
NOTICE OF PROPRIETARY PROPERTY: BRANCH
VCC_97 VTT_SENSE OUT 68 89
J18 AE36 THE INFORMATION CONTAINED HEREIN IS THE
VCC_98 VSS_SENSE_VTT CPU_VTTSENSE_N OUT 68 89 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
J19 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VCC_99 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
13 OF 110

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 12 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

A16
A25
VSS_0 U1000 VSS_80 AP15
AP16
VSS_1 VSS_81
A28 VSS_2
LYNNFIELD VSS_82 AP17
A34 LGA1156-SKT AP20
VSS_3 VSS_83
A37 ( 8 OF 10 ) AP24
VSS_4 VSS_84
AA5 VSS_5 VSS_85 AP26
AB3 OMIT AP27
VSS_6 VSS_86

D
AB33
AB34
VSS_7
VSS_8
VSS_87
VSS_88
AP29
AP33 D
AB35 VSS_9 VSS_89 AP35
AB36 VSS_10 VSS_90 AP38
E24
E27
VSS_160 U1000 VSS_219 K13
K19
VSS_161 VSS_220
AB37 VSS_11 VSS_91 AP4
E3 VSS_162
LYNNFIELD VSS_221 K2
AB38 VSS_12 VSS_92 AP7 LGA1156-SKT
E30 VSS_163 VSS_222 K22
AB39 VSS_13 VSS_93 AP9 (9 OF 10)
E33 VSS_164 VSS_223 K25
AB40 VSS_14 VSS_94 AR1
E36 VSS_165 VSS_224 K28
AB6 VSS_15 VSS_95 AR20 OMIT
E39 VSS_166 VSS_225 K31
AB8 VSS_16 VSS_96 AR23
E4 VSS_167 VSS_226 K34
AC1 VSS_17 VSS_97 AR30
F11 VSS_168 VSS_227 K37
AD5 VSS_18 VSS_98 AR40
F13 VSS_169 VSS_228 K40
AD8 AT12

VSS
VSS_19 VSS_99 F16 K5
AE3 AT14 VSS_170 VSS_229
VSS_20 VSS_100 F2 K6
AE37 AT16 VSS_171 VSS_230
VSS_21 VSS_101 F20 L13
AE7 AT2 VSS_172 VSS_231
VSS_22 VSS_102 F23 L18
AF1 AT24 VSS_173 VSS_232
VSS_23 VSS_103 F26 L21
AF40 AT27 VSS_174 VSS_233
VSS_24 VSS_104 F29 L24
AG34 AT30 VSS_175 VSS_234
VSS_25 VSS_105 F32 L27
AG36 AT34 VSS_176 VSS_235
VSS_26 VSS_106 F35 L30
AG7 AT37 VSS_177 VSS_236
VSS_27 VSS_107 F38 L33
AH3 AT5 VSS_178 VSS_237
VSS_28 VSS_108 F8 L36
AH33 AT8 VSS_179 VSS_238
VSS_29 VSS_109 G13 L39
AH38 AU32 VSS_180 VSS_239
VSS_30 VSS_110 G16 L4
AH5 AU36 VSS_181 VSS_240
VSS_31 VSS_111 G19 L9
AJ1 AU6 VSS_182 VSS_241
VSS_32 VSS_112 G22 M13

VSS
AJ12 AU7 VSS_183 VSS_242
VSS_33 VSS_113
C AJ14
AJ16
VSS_34
VSS_35
VSS_114
VSS_115
AV3
AV31
G25
G28
VSS_184
VSS_185
VSS_243
VSS_244
M18
M2 C
G31 VSS_186 VSS_245 M20
AJ18 VSS_36 VSS_116 AV34
G34 VSS_187 VSS_246 M23
AJ20 VSS_37 VSS_117 AV38
G37 VSS_188 VSS_247 M26
AJ22 VSS_38 VSS_118 AY33
G4 VSS_189 VSS_248 M29
AJ24 VSS_39 VSS_119 AY36
G40 VSS_190 VSS_249 M32
AJ26 VSS_40 VSS_120 AY4
G9 VSS_191 VSS_250 M35
AJ28 VSS_41 VSS_121 AY7
H11 VSS_192 VSS_251 M38
AJ30 VSS_42 VSS_122 B16
H13 VSS_193 VSS_252 M5
AJ33 VSS_43 VSS_123 B24
H16 VSS_194 VSS_253 M6
AJ34 VSS_44 VSS_124 B27
H18 VSS_195 VSS_254 M7
AJ40 VSS_45 VSS_125 B30
H2 VSS_196 VSS_255 N34
AJ6 VSS_46 VSS_126 B33
H21 VSS_197 VSS_256 N37
AJ9 VSS_47 VSS_127 B36
H24 VSS_198 VSS_257 N4
AK10 VSS_48 VSS_128 B7
H27 VSS_199 VSS_258 N40
AK17 VSS_49 VSS_129 B9
H30 VSS_200 VSS_259 P2
AK36 VSS_50 VSS_130 C13
H33 VSS_201 VSS_260 P5
AK4 VSS_51 VSS_131 C16
H36 VSS_202 VSS_261 R4
AK5 VSS_52 VSS_132 C19
H39 VSS_203 VSS_262 T33
AK8 VSS_53 VSS_133 C22
H5 VSS_204 VSS_263 T36
AL11 VSS_54 VSS_134 C26
H6 VSS_205 VSS_264 T37
AL13 VSS_55 VSS_135 C29
J13 VSS_206 VSS_265 T38
AL16 VSS_56 VSS_136 C32
J17 VSS_207 VSS_266 T39
AL19 VSS_57 VSS_137 C35
J20 VSS_208 VSS_267 T5
AL22 VSS_58 VSS_138 C38
J23 VSS_209 VSS_268 U4
AL25 VSS_59 VSS_139 C5
J26 VSS_210 VSS_269 V5
B AL28
AL3
VSS_60
VSS_61
VSS_140
VSS_141
D10
D12
J29
J32
VSS_211 VSS_270 W33
W34
B
AL31 D13 VSS_212 VSS_271
VSS_62 VSS_142 J35 W35
AL34 D16 VSS_213 VSS_272
VSS_63 VSS_143 J38 W36
AL38 D19 VSS_214 VSS_273
VSS_64 VSS_144 J4 W37
AL7 D22 VSS_215 VSS_274
VSS_65 VSS_145 J7 W38
AM1 D25 VSS_216 VSS_275
VSS_66 VSS_146 J9 Y7
AM40 D28 VSS_217 VSS_276
VSS_67 VSS_147 K11 AF6
AM5 D31 VSS_218 VSS_277
VSS_68 VSS_148
AM9 VSS_69 VSS_149 D34 1157
AN13 VSS_70 VSS_150 D37 1158
SKT MNT HOLE
AN20 VSS_71 VSS_151 D4 1159
AN22 VSS_72 VSS_152 D40
AN25 VSS_73 VSS_153 D5
AN28 VSS_74 VSS_154 D6
AN31 VSS_75 VSS_155 D8
AN36 VSS_76 VSS_156 E13
AN4 VSS_77 VSS_157 E16
AN9 VSS_78 VSS_158 E19
AP12 VSS_79 VSS_159 E21

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

CPU GROUNDS
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 13 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

UNUSED GPIO SIGNALS

14 5 =PP3V3_S0_PCH_STRAPS
14 5 =PP3V3_S5_PCH_STRAPS
84 24 9 CPU_CFG<3>

BUF_CLK
R1500 1 R15911 R15291 R15231 R15241 R15281 R15081 R15261 R15041 R15061 R15031 R15091 R15381 R15351 R15901 R15171
1.5K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K

D CPU_CFG<3> IS USED FOR

PCIE LANE REVERSAL
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
D
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CPU_CFG<3> PCIE LANES

PCH_GPIO8_FCIM_EN_L 20
0 REVERSAL
PCH_GPIO0_BMBUSY_L 20 PCH_GPIO24 20
1 NO REVERSAL
PCH_GPIO21_SATA0GP 17 BRCRYPT_PWR_EN 17

PCH_GPIO19_SATA1GP 17 PCH_GPIO15 20

PCH_GPIO37_SATA3GP 20

PCH_GPIO49_SATA5GP 20

PCH_GPIO6_TACH2 20

PCH_GPIO34_STP_PCI_L 20

PCH_GPIO38_SLOAD 20

PCH_GPIO39_SDATAOUT0 20

AP_PWR_EN 20

FW_PWR_EN 20

37 17 ENET_ENERGY_DET 14 5 =PP3V3_S0_PCH_STRAPS
14 5 =PP3V3_S5_PCH_STRAPS
37 20 ENET_LOW_PWR
91 18 PM_LAN_PWRGD
PCH_VRM
R15251 R15221 R15391 R15301 R15151
C R1501
10K
1
R1510
10K
1
R1511
10K
1 10K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
C
5% 5% 5% 402 402 402 402 402
1/16W 1/16W 1/16W
2 2 2 2 2
MF-LF MF-LF MF-LF
402 402 402
2 2 2
PM_BATLOW_L 18 46 91
ENET_CLKREQ_L 17 37
PCH_GPIO27_VRMEN 20
FW_CLKREQ_L 17 40

MINI_CLKREQ_L 17 33

UNUSED CLKREQS
14 5 =PP3V3_S0_PCH_STRAPS
14 5 =PP3V3_S0_PCH_STRAPS
14 5 =PP3V3_S0_PCH_STRAPS

R15751 R15741 R15731 R15711 R15701 R15431

10K 10K 10K 10K 10K 10K R15361 R15321 R15331 1 1
5% 5% 5% 5% 5% 5% 10K 10K 10K R1527 R1507
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 5% 5% 5% 10K 10K
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF 1/16W 1/16W 1/16W 5% 5%
402 402 402 402 402 402 MF-LF MF-LF MF-LF 1/16W 1/16W
2 2 2 2 2 2 402 402 402 MF-LF MF-LF
2 2 2 402 402
2 2

FW_PME_L 20 40

EXCARD_CLKREQ_L 17 SMC_RUNTIME_SCI_L 20 46

B PCH_SPKR
PM_CLKRUN_L
17

18 46 48 91
T28_CLKREQ_L
PEB_CLKREQ_L
17

17
B
SPI_DESCRIPTOR_OVERRIDE_L 17 46

BRCRYPT_RESET 17

PCH_CLKOUTFLEX1 17
NOSTUFF
PCH_CLKOUTFLEX2 17 R15371
PCH_CLKOUTFLEX3 17 10K
5%
1/16W
MF-LF
R15721 402
2 IF LIKE TO HAVE THE PEB CLOCKS ENABLED. STUFF R1535 AND UNSTUFF R1534

10K
5%
1/16W
MF-LF
402
2

BOOT STRAP OPTIONS

20 ODD_PWR_EN_L 19 PCH_PCI_GNT3_L
36 20 WOL_EN 19 PCH_PCI_GNT2_L
20 PCH_INIT3V3_L 19 PCH_PCI_GNT1_L
19 PCH_PCI_GNT0_L

NOSTUFF1 1 1
R1550 R1555 R1512
1K 10K 10K NOSTUFF1 NOSTUFF
1 NOSTUFF
1 NOSTUFF
1
5%
1/16W
5%
1/16W
5%
1/16W
R1551 R1552 R1553 R1554
MF-LF MF-LF MF-LF 10K 10K 10K 10K
A 402
2
402
2 402
2 5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SYNC_MASTER=NICK SYNC_DATE=12/08/2009 A
2 2 2 2 PAGE TITLE

STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

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IV ALL RIGHTS RESERVED 14 OF 92
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8 7 6 5 4 3 2 1
CPU VCORE DECOUPLING
INTEL RECOMMENDATION 17X 22UF 0805
CPU Power On Configuration (POC) Straps
Intel recommends all option straps should be provided in layout

12 5 =PPVCORE_S0_CPU 65 47 15 12 10 5 =PPVTT_S0_CPU

CPUPOC4U
CPUMSI0U1 CPUMSI2U1
1
C1600 1
C1601 1
C1602 1
C1603 1
C1604 1
C1605 1
C1606 1
C1607 1
C1608 1
C1609 R1600 R1602 R1604 1
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 1K 1K 1K
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 5% 5% 5%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 1/16W 1/16W 1/16W
805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3 MF-LF MF-LF MF-LF

D
402
2
402
2

CPUPOC3U
402
2

CPUPOC5U
D
1
CPUMSI1U 1 1
R1601 R1603 R1605
1K 1K 1K
5% 5% 5%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
402 402 402
2 2 2
NOSTUFF NOSTUFF NOSTUFF
1
C1610 1
C1611 1
C1612 1
C1613 1
C1614 1
C1615 1
C1616 1
C1617 1
C1618 1
C1619 89 65 12 OUT CPU_VID<0>
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 89 65 12 CPU_VID<1>
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% OUT
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V CPU_VID<2>
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 89 65 12 OUT
805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3 CPU_VID<3>
89 65 12 OUT
89 65 12 OUT CPU_VID<4>
89 65 12 OUT CPU_VID<5>
89 65 12 OUT CPU_VID<6>
BULK CAPS ON CPU VREG PAGE 74 89 65 12 OUT CPU_VID<7>

CPUPOC4D
CPUMSI0D CPUMSI2D1
R1610 1 R1612 R1614 1 R1616 1
1K 1K 1K 1K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 402 402 402
2 2 2 2

CPUPOC3D CPUPOC5D
CPUMSI1D
1 1 1 1
R1611 R1613 R1615 R1617
1K 1K 1K 1K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 402 402
2 2 2 2 402

C VID[2:0] = FUNCTION MSI[2:0]

C
VID[5:3] = IMON CONFIG DEFAULT
VID[6] = Reserved (0)

VTT (CPU Uncore) DECOUPLING MSI - MARKET SEGMENT IDENTIFICATION

VID[7] = VRD SELECT (0)

PREVENTS THE PLATFORM BOOTING USING A HIGHER POWERED CPU

8X 22UF 0805, 7X 10UF 0805 INTEL RECOMMENDATION 9X22UF 0805 TABLE_BOMGROUP_HEAD

BOM GROUP IMAX @ 900mV CPU Gain Setting BOM OPTIONS Equivalent Gain
PLACEMENT_NOTE (C1650-C1657): TABLE_BOMGROUP_ITEM

CPUPOC_IMAX_DIS 000 CPUPOC5D,CPUPOC4D,CPUPOC3D

65 47 15 12 10 5 =PPVTT_S0_CPU
Place under socket cavity on secondary side. TABLE_BOMGROUP_ITEM

CPUPOC_IMAX_0_40 40A 001 CPUPOC5D,CPUPOC4D,CPUPOC3U 45

TABLE_BOMGROUP_ITEM

CPUPOC_IMAX_40_60 60A 010 CPUPOC5D,CPUPOC4U,CPUPOC3D 30

1
C1650 1
C1651 1
C1652 1
C1653 1
C1654 1
C1655 1
C1656 1
C1657 TABLE_BOMGROUP_ITEM

22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF CPUPOC_IMAX_60_80 80A 011 CPUPOC5D,CPUPOC4U,CPUPOC3U 22.5
20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 2 2 2 2 2 2 2
TABLE_BOMGROUP_ITEM

CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R

805 805 805 805 805 805 805 805 CPUPOC_IMAX_80_100 100A 100 CPUPOC5U,CPUPOC4D,CPUPOC3D 18
TABLE_BOMGROUP_ITEM

CPUPOC_IMAX_100_120 120A 101 CPUPOC5U,CPUPOC4D,CPUPOC3U 15

PLACEMENT_NOTE (C1660-C1666): TABLE_BOMGROUP_ITEM

CPUPOC_IMAX_120_140 140A 110 CPUPOC5U,CPUPOC4U,CPUPOC3D 12.857

Place at edge of socket. BULK CAPS ON CPU VREG PAGE 72 TABLE_BOMGROUP_ITEM

CPUPOC_IMAX_140_180 180A 111 CPUPOC5U,CPUPOC4U,CPUPOC3U 10

1
C1660 1
C1661 1
C1662 1
C1663 1
C1664 1
C1665 1
C1666
10uF 10uF 10uF 10uF 10uF 10uF 10uF
20% 20% 20% 20% 20% 20% 20% TABLE_BOMGROUP_HEAD

2
6.3V
X5R 2
6.3V
X5R 2
6.3V
X5R 2
6.3V
X5R 2
6.3V
X5R 2
6.3V
X5R 2
6.3V
X5R BOM GROUP BOM OPTIONS
603 603 603 603 603 603 603 TABLE_BOMGROUP_ITEM

CLARKDALE_73W CKD,CPUPOC_IMAX_60_80,CPUMSI2U,CPUMSI1D,CPUMSI0U

B B
TABLE_BOMGROUP_ITEM

LYNNFIELD_82W LFD,CPUPOC_IMAX_60_80,CPUMSI2U,CPUMSI1D,CPUMSI0U
BULK CAPS ON CPU VTT REG PAGE 74 TABLE_BOMGROUP_ITEM

LYNNFIELD_95W LFD,CPUPOC_IMAX_100_120,CPUMSI2U,CPUMSI1U,CPUMSI0D

1
C1670 1
C1671 NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.
330UF-0.0045OHM 330UF-0.0045OHM
20%
2V
20%
2V
Instead call out appropriate BOM GROUP defined in tables above.
2 2
POLY POLY
CASE-D2-SM CASE-D2-SM

Memory (CPU VCCDDR) DECOUPLING

2x 22uF 0805, 5x 1uF 0402
29 12 10 5 =PP1V5_CPU_MEM

1
C1680 1
C1681 1
C1682 1
C1683 1
C1684 1
C1685 1
C1686
22uF 22uF 1UF 1UF 1UF 1UF 1UF
20% 20% 10% 10% 10% 10% 10%
6.3V 6.3V 10V 10V 10V 10V 10V
2 CERM-X5R 2 CERM-X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 402 402 402 402 402

A PLL (CPU VCCSFR) DECOUPLING SYNC_MASTER=NICK SYNC_DATE=12/08/2009 A

PAGE TITLE
1x 22uF 0805, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402
CPU NON-GFX DECOUPLING
64 12 5 =PP1V8_S0_CPU_PLL DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

REVISION
1
C1690 1
C1691 1
C1692 1
C1693 1
C1694
R
A.0.0
22uF 4.7UF 2.2UF 1UF 1UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
20% 10% 10% 10% 10%
6.3V 6.3V 6.3V 10V 10V
2 CERM-X5R 2 X5R-CERM 2 X5R 2 X5R 2 X5R THE INFORMATION CONTAINED HEREIN IS THE
805 603 402 402 402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
16 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 15 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C

R1750
0
5 =PP3V3_S0_PCH_VCCADAC 1 2 PP3V3_S0_PCH_VCCA_DAC 21 89
MIN_LINE_WIDTH=0.4 MM
69 mA 5% MIN_NECK_WIDTH=0.2 MM 69 mA
1/16W VOLTAGE=3.3V
MF-LF
402

R1760
0
5 =PP1V05_S0_PCH_VCCADPLL 1 2 PP1V05_S0_PCH_VCCADPLLA 21 89
MIN_LINE_WIDTH=0.4 MM
150 MA 5% MIN_NECK_WIDTH=0.2 MM 75 MA

B B
1/16W VOLTAGE=1.05V
MF-LF
402

R1765
0
1 2 PP1V05_S0_PCH_VCCADPLLB 21 89
MIN_LINE_WIDTH=0.4 MM 75 MA
5% MIN_NECK_WIDTH=0.2 MM
1/16W VOLTAGE=1.05V
MF-LF
402

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

CPU/PCH GFX DECOUPLING

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 16 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
23 21 5 =PP1V05_S0_PCH_VCCIO_SATA
69 23 20 5 =PP3V3_S0_PCH 23 21 18 5 =PP1V05_S0_PCH_VCCIO_PCIE

1
PLACE THIS RESISTOR NEAR THE PCH PIN
R1890
R1830 1 90.9
37.4 1%
1% 1/16W
1/16W MF-LF
IBEX-PEAK-DESKTOP LPC_R_AD<0> R1860 1 2 33 LPC_AD<0> BI 46 48 85
MF-LF
402
402
2
5% 1/16W MF-LF 402 2
85 27 IN PCH_CLK32K_RTCX1 AW30 RTCX1 OMIT FWH0/LAD0 AT12 LPC_R_AD<1> R1861 1 2 33 LPC_AD<1> 46 48 85
86 37 IN PCIE_ENET_D2R_N D15 PERN1 OMIT SMBALERT*/GPIO11 AL31 SMC_WAKE_SCI_L 17 46
BI
85 27 OUT PCH_CLK32K_RTCX2 BA30 RTCX2 U1800 FWH1/LAD1 AK16 5% 1/16W MF-LF 402
86 37 IN PCIE_ENET_D2R_P C16 PERP1 U1800

(IPU)
AL16 LPC_R_AD<2> R1862 1 2 33 LPC_AD<2> SMBCLK AV32 SMBUS_PCH_CLK OUT 49 88
46 48 85 1 PCIE_ENET_R2D_C_N D18
FCBGA FWH2/LAD2 5% 1/16W MF-LF 402
BI R1820 86 37 OUT PETN1 IBEX-PEAK-DESKTOP SMBDATA AM31 SMBUS_PCH_DATA BI 49 88
FWH3/LAD3 AM16 10K PCIE_ENET_R2D_C_P D17 PETP1 FCBGA
D 91 17 RTC_RESET_L AK24 RTCRST* (1 OF 10)
FWH4/LFRAME* AR14
LPC_R_AD<3>

LPC_FRAME_R_L
R1863
R1864 1
1
5% 1/16W
2 33 LPC_AD<3>
MF-LF 402

2 33 LPC_FRAME_L
BI 46 48 85

46 48 85
5%
1/16W
MF-LF
86 37

84 33
OUT

IN PCIE_MINI_D2R_N B17 PERN2

(2 OF 10)
SML0ALERT*/GPIO60 BA33 SML_PCH_0_ALERT_L 17
D
5% 1/16W MF-LF 402
OUT 402
17 PCH_SRTCRST_L AP28 SRTCRST* 2
84 33 IN PCIE_MINI_D2R_P A16 PERP2
AL12 TP_LPC_DREQ0_L AW33 SML_PCH_0_CLK

RTC
LPC
(IPU) LDRQ0* 7 SML0CLK OUT 49 88
PCIE_MINI_R2D_C_N H16 PETN2

SMBUS
84 33 OUT
17 PCH_INTRUDER_L AN24 INTRUDER* LDRQ1*/GPIO23 AP14 TP_LPC_DREQ1_L 7 SML0DATA AT34 SML_PCH_0_DATA BI 49 88
84 33 OUT PCIE_MINI_R2D_C_P G16 PETP2
17 PCH_INTVRMEN_L AW31 INTVRMEN SERIRQ AL40 LPC_SERIRQ BI 46 48
84 39 IN PCIE_FW_D2R_N B15 PERN3 SML1ALERT*/GPIO74 AY32 SML_PCH_1_ALERT_L 17

84 39 IN PCIE_FW_D2R_P C14 PERP3

SML1CLK/GPIO58 AV31 SML_PCH_1_CLK OUT 49 88
85 17 HDA_BIT_CLK_R AW14 HDA_BCLK (IPD) SATA0RXN W41 SATA_HDD_D2R_N IN 42 84 84 39 OUT PCIE_FW_R2D_C_N H14 PETN3
SML1DATA/GPIO75 AR31 SML_PCH_1_DATA BI 49 88
SATA0RXP V40 SATA_HDD_D2R_P IN 42 84 84 39 OUT PCIE_FW_R2D_C_P G14 PETP3
85 17 HDA_SYNC_R AU15 HDA_SYNC (IPD) SATA0TXN U38 SATA_HDD_R2D_C_N OUT 42 84
7 IN PCIE_EXCARD_D2R_N D14 PERN4
SATA0TXP V38 SATA_HDD_R2D_C_P OUT 42 84
7 IN PCIE_EXCARD_D2R_P D13 PERP4
14 PCH_SPKR AJ38 SPKR (IPD)
SATA1RXN Y38 SATA_ODD_D2R_N IN 42 84 7 OUT PCIE_EXCARD_R2D_C_N K14 PETN4
SATA1RXP Y37 SATA_ODD_D2R_P PCIE_EXCARD_R2D_C_P L14 PETP4

IHDA
IN 42 84 7 OUT
85 17 HDA_RST_R_L AV14 HDA_RST* (IPD)
SATA1TXN AB36 SATA_ODD_R2D_C_N OUT 42 84
7 TP_PCIE_T28_D2R_N<0> C12 PERN5
SATA1TXP AB35 SATA_ODD_R2D_C_P OUT 42 84
85 56 IN HDA_SDIN0 AV13 HDA_SDIN0 (IPD) 7 TP_PCIE_T28_D2R_P<0> B13 PERP5
PEG_A_CLKRQ*/GPIO47 AV39 PEG_CLKREQ_L IN 8
7 TP_HDA_SDIN1 AP18 HDA_SDIN1 (IPD) SATA2RXN AD36 TP_SATA_SSD_D2R_N IN 7 7 TP_PCIE_T28_R2D_C_N<0> H12 PETN5
7 TP_HDA_SDIN2 AU13 HDA_SDIN2 (IPD) SATA2RXP AD35 TP_SATA_SSD_D2R_P IN 7 7 TP_PCIE_T28_R2D_C_P<0> G12 PETP5
CLKOUT_PEG_A_N Y6 PEG_CLK100M_N OUT 8

PEG
7 TP_HDA_SDIN3 AN16 HDA_SDIN3 (IPD) SATA2TXN AB31 TP_SATA_SSD_R2D_C_N OUT 7
7 TP_PCIE_T28_D2R_N<1> D8 PERN6 CLKOUT_PEG_A_P Y7 PEG_CLK100M_P OUT 8
SATA2TXP AB32 TP_SATA_SSD_R2D_C_P OUT 7
7 TP_PCIE_T28_D2R_P<1> C9 PERP6
85 17 HDA_SDOUT_R AP16 HDA_SDO (IPD)
SATA3RXN AC41 TP_SATA_D_D2RN 7 7 TP_PCIE_T28_R2D_C_N<1> G11 PETN6
CLKOUT_DMI_N H40 PCIE_CLK100M_CPU_N OUT 10 84
SATA3RXP AC39 TP_SATA_D_D2RP 7 7 TP_PCIE_T28_R2D_C_P<1> H11 PETP6
46 14 IN SPI_DESCRIPTOR_OVERRIDE_L AT16 GPIO33 (IPU) CLKOUT_DMI_P J41 PCIE_CLK100M_CPU_P OUT 10 84
SATA3TXN AB37 TP_SATA_D_R2D_CN 7

SATA
37 14 ENET_ENERGY_DET AR16 GPIO13 7 TP_PCIE_T28_D2R_N<2> A12 PERN7
SATA3TXP AB38 TP_SATA_D_R2D_CP 7
7 TP_PCIE_T28_D2R_P<2> B11 PERP7
CLKOUT_DP_N/CLKOUT_BCLK1_N H37 GFX_CLK120M_DPLLSS_N 10 84

PCI-E*
AF41 TP_SATA_E_D2RN TP_PCIE_T28_R2D_C_N<2> D11 OUT
SATA4RXN 7 7 PETN7
17 JTAG_PCH_TCK AK33 JTAG_TCK (IPU) CLKOUT_DP_P/CLKOUT_BCLK1_P H38 GFX_CLK120M_DPLLSS_P 10 84

C
OUT
C 17 JTAG_PCH_TMS AL34 JTAG_TMS (IPU) JTAG
SATA4RXP
SATA4TXN
AE40
AD38
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
7

7
7

7
TP_PCIE_T28_R2D_C_P<2>

TP_PCIE_T28_D2R_N<3>
D10

C7
PETP7

PERN8
SATA4TXP AE38 TP_SATA_E_R2D_CP 7 CLKIN_DMI_N H20 PCIE_CLK100M_PCH_N IN 25 84
17 JTAG_PCH_TDI AL36 JTAG_TDI (IPU) 7 TP_PCIE_T28_D2R_P<3> B8 PERP8
CLKIN_DMI_P G20 PCIE_CLK100M_PCH_P IN 25 84
SATA5RXN AF35 TP_SATA_F_D2RN 7 7 TP_PCIE_T28_R2D_C_N<3> K12 PETN8
17 JTAG_PCH_TDO AN34 JTAG_TDO
SATA5RXP AF34 TP_SATA_F_D2RP 7 7 TP_PCIE_T28_R2D_C_P<3> J12 PETP8
TP_JTAG_PCH_TRST_L AL35 TRST* (IPU) SATA5TXN AD33 TP_SATA_F_R2D_CN 7 CLKIN_BCLK_N Y32 FSB_CLK133M_PCH_N IN 25 84

SATA5TXP AD32 TP_SATA_F_R2D_CP PCIE_CLK100M_ENET_N V2 CLKOUT_PCIE0N CLKIN_BCLK_P Y31 FSB_CLK133M_PCH_P

FROM CLK BUFFER

7 84 37 OUT IN 25 84

R1822 1 22 84 37 OUT PCIE_CLK100M_ENET_P W1 CLKOUT_PCIE0P

85 55 48 OUT SPI_CLK_R 2 SPI_CLK_1_R V31 SPI_CLK
5% 1/16W MF-LF 402 SATAICOMPO T41 85 PCH_SATAICOMP
TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS 37 14 IN ENET_CLKREQ_L AN35 PCIECLKRQ0*/GPIO73 CLKIN_DOT_96N AM22 PCH_CLK96M_DOT_N IN 25 84
85 48 OUT SPI_CS0_R_L V32 SPI_CS0* SATAICOMPI T39
AL22 PCH_CLK96M_DOT_P
SPI

CLKIN_DOT_96P IN 25 84
84 33 OUT PCIE_CLK100M_MINI_N T10 CLKOUT_PCIE1N
TP_SPI_CS1_L T32 SPI_CS1*
(IPU) SATALED* AN39 PCH_SATALED_L 17 42 84 33 OUT PCIE_CLK100M_MINI_P T9 CLKOUT_PCIE1P
85 55 48 OUT SPI_MOSI_R R1823 1 2 22 SPI_MOSI_1_R T34 SPI_MOSI (IPD) CLKIN_SATA_N/CKSSCD_N Y34 PCH_CLK100M_SATA_N IN 25 84
5% 1/16W MF-LF 402 SATA0GP/GPIO21 AJ37 PCH_GPIO21_SATA0GP 14 33 14 IN MINI_CLKREQ_L AM39 PCIECLKRQ1*/GPIO18
CLKIN_SATA_P/CKSSCD_P Y35 PCH_CLK100M_SATA_P IN 25 84
85 55 48 IN SPI_MISO V30 SPI_MISO (IPU) SATA1GP/GPIO19 AH38 PCH_GPIO19_SATA1GP 14
84 39 OUT PCIE_CLK100M_FW_N M6 CLKOUT_PCIE2N
84 39 OUT PCIE_CLK100M_FW_P M7 CLKOUT_PCIE2P
REFCLK14IN AF7 PCH_CLK14P3M_REFCLK IN 25 85

40 14 IN FW_CLKREQ_L AP38 PCIECLKRQ2*/GPIO20

7 OUT PCIE_CLK100M_EXCARD_N M9 CLKOUT_PCIE3N CLKIN_PCILOOPBACK AL11 PCH_CLK33M_PCIIN IN 27 85

DOES THIS NEED LENGTH MATCH???
7 OUT PCIE_CLK100M_EXCARD_P M10 CLKOUT_PCIE3P

14 IN EXCARD_CLKREQ_L AP33 PCIECLKRQ3*/GPIO25 XTAL25_IN Y4 PCH_CLK25M_XTALIN IN 27 85

89 27 23 21 PP3V3_G3_RTC XTAL25_OUT Y2 PCH_CLK25M_XTALOUT OUT 27 85

42 5 =PP3V3_S0_SATALED 7 TP_PCIE_CLK100M_T28_N P7 CLKOUT_PCIE4N
7 TP_PCIE_CLK100M_T28_P P6 CLKOUT_PCIE4P
XCLK_RCOMP AA3 85 PCH_XCLK_RCOMP
R1802 1
1
R1803 14 IN T28_CLKREQ_L AW37 PCIECLKRQ4*/GPIO26
20K 20K
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF
R18501
7

7
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
Y8
Y9
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKOUTFLEX0/GPIO64
(IPD)
AD10 BRCRYPT_RESET 14 B
10K

CLOCK
402 402
2 2

FLEX
5%
1/16W 14 BRCRYPT_PWR_EN AW38 PCIECLKRQ5*/GPIO44 CLKOUTFLEX1/GPIO65 AK1 PCH_CLKOUTFLEX1 14
MF-LF (IPD)
402
1 1 2 DMI_MIDBUS_CLK100M_N V7 CLKOUT_PEG_B_N
R1800 R1801 7 OUT
CLKOUTFLEX2/GPIO66 AB6 PCH_CLKOUTFLEX2 14
330K 1M 7 OUT DMI_MIDBUS_CLK100M_P V8 CLKOUT_PEG_B_P (IPD)
5% 5%
1/16W 1/16W
MF-LF MF-LF RTC_RESET_L 17 91 14 PEB_CLKREQ_L AW35 PEG_B_CLKRQ*/GPIO56 CLKOUTFLEX3/GPIO67 AL3 PCH_CLKOUTFLEX3 14
402 402 (IPD)
2 2 PCH_SRTCRST_L 17

PCH_INTRUDER_L 17

PCH_INTVRMEN_L 17
23 18 17 5 =PP3V3_S5_PCH
PCH_SATALED_L 17 42

C1802 1 1
C1803
1UF 1UF
10% 10%
10V 10V
X5R 2 2 X5R
402 402
1 1 1
R1853 R1854 R1855
10K 10K 10K
5% 5% 5%
23 18 17 5 =PP3V3_S5_PCH 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
402 402
XDP 2 2 2 402
XDP XDP
R1881
1
R1883
1 1
R1885 PLACE THESE 33 OHM RESISTORS CLOSE TO PCH (MIN 500MIL)
200 200 200 R1810 46 17 SMC_WAKE_SCI_L
5% 5% 5%
1/16W 1/16W 1/16W 33
MF-LF MF-LF MF-LF 85 17 HDA_BIT_CLK_R 1 2 HDA_BIT_CLK OUT 56 85
2 402 2 402 2 402 17 SML_PCH_0_ALERT_L
5%
1/16W
MF-LF SML_PCH_1_ALERT_L
17 JTAG_PCH_TMS 402 R1811 17

17 JTAG_PCH_TCK 33
A 17 JTAG_PCH_TDI
85 17 HDA_SYNC_R 1

5%
2 HDA_SYNC OUT 56 85

SYNC_MASTER=NICK SYNC_DATE=12/08/2009 A
1
R1856 17 JTAG_PCH_TDO
R1812
1/16W
MF-LF PAGE TITLE

5%
51
1/16W XDP 85 17 HDA_RST_R_L 1
33
2
402

HDA_RST_L OUT 56 85
PCH SATA/PCIE/CLK/LPC/SPI
MF-LF XDP XDP DRAWING NUMBER SIZE
2 402 R1882
1
R1884
1 1
R1886 5%
1/16W 051-8337 D
100
5%
100
5%
100
5%
MF-LF
402 R1813 Apple Inc. REVISION
1/16W 1/16W 1/16W 33
MF-LF MF-LF MF-LF 85 17 HDA_SDOUT_R 1 2 HDA_SDOUT OUT 56 85
R
A.0.0
2 402 2 402 2 402 5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/16W
MF-LF THE INFORMATION CONTAINED HEREIN IS THE
402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
18 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 17 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

=PP3V3_S5_PCH 5 17 18 23

=PP1V05_S0_PCH_VCCIO_PCIE 5 17 21 23

1 1
R1905 R1915 1
10K 100K R1900
1% 1% 49.9
1/16W 1/16W 1%
MF-LF MF-LF 1/16W
402 402 2 MF-LF
2
2
402 IBEX-PEAK-DESKTOP =PP3V3_S5_PCH 5 17 18 23
IBEX-PEAK-DESKTOP
84 9 IN DMI_N2S_N<0> A19 DMI0RXN OMIT FDI_RXN0 K30 TP_PCH_FDI_RX_N<0> 7 OMIT SDVO_TVCLKINN L7 TP_SDVO_TVCLKINN 7

84 9 IN DMI_N2S_N<1> B20 DMI1RXN U1800 FDI_RXN1 H30 TP_PCH_FDI_RX_N<1> 7

1
R1925 U1800 SDVO_TVCLKINP L6 TP_SDVO_TVCLKINP 7

D 84 9

84 9
IN
IN
DMI_N2S_N<2>
DMI_N2S_N<3>
E20
G18
DMI2RXN
DMI3RXN
FCBGA FDI_RXN2
FDI_RXN3
D31
F31
TP_PCH_FDI_RX_N<2>
TP_PCH_FDI_RX_N<3>
7

7
1K
1%
FCBGA
SDVO_STALLN P3 TP_SDVO_STALLN 7 D
1/16W SDVO_STALLP N2 TP_SDVO_STALLP 7
(3 OF 10) FDI_RXN4 K31 TP_PCH_FDI_RX_N<4> 7 MF-LF (4 OF 10)
84 9 IN DMI_N2S_P<0> B18 DMI0RXP 402 2
FDI_RXN5 C30 TP_PCH_FDI_RX_N<5> 7 SDVO_INTN N4 TP_SDVO_INTN 7
84 9 IN DMI_N2S_P<1> C19 DMI1RXP
FDI_RXN6 A33 TP_PCH_FDI_RX_N<6> 7 SDVO_INTP M3 TP_SDVO_INTP 7
84 9 IN DMI_N2S_P<2> D20 DMI2RXP
FDI_RXN7 C33 TP_PCH_FDI_RX_N<7> 7
84 9 IN DMI_N2S_P<3> H18 DMI3RXP
(IPD) SDVO_CTRLCLK AB13 TP_DP_IG_B_DDC_CLK 7
FDI_RXP0 J30 TP_PCH_FDI_RX_P<0> 7
(IPD) SDVO_CTRLDATA AB12 TP_DP_IG_B_DDC_DATA 7
84 9 OUT DMI_S2N_N<0> J22 DMI0TXN FDI_RXP1 G30 TP_PCH_FDI_RX_P<1> 7
PCIE_WAKE_L 18 33 36
84 9 OUT DMI_S2N_N<1> G22 DMI1TXN FDI_RXP2 D32 TP_PCH_FDI_RX_P<2> 7 DDPB_AUXN L2 TP_DP_IG_B_AUX_N 7

84 9 OUT DMI_S2N_N<2> H24 DMI2TXN FDI_RXP3 G31 TP_PCH_FDI_RX_P<3> 7 DDPB_AUXP M1 TP_DP_IG_B_AUX_P 7

84 9 OUT DMI_S2N_N<3> L24 DMI3TXN FDI_RXP4 J31 TP_PCH_FDI_RX_P<4> 7 DDPB_HPD J1 TP_DP_IG_B_HPD 7

DMI
FDI
FDI_RXP5 B31 TP_PCH_FDI_RX_P<5> 7
84 9 OUT DMI_S2N_P<0> H22 DMI0TXP DDPB_0N J8 TP_DP_IG_B_MLN<0> 7
FDI_RXP6 B32 TP_PCH_FDI_RX_P<6> 7 EXTERNAL DP
84 9 OUT DMI_S2N_P<1> F22 DMI1TXP DDPB_0P K10 TP_DP_IG_B_MLP<0> 7
FDI_RXP7 B34 TP_PCH_FDI_RX_P<7> 7
84 9 OUT DMI_S2N_P<2> G24 DMI2TXP DDPB_1N J11 TP_DP_IG_B_MLN<1> 7

84 9 OUT DMI_S2N_P<3> K24 DMI3TXP DDPB_1P K11 TP_DP_IG_B_MLP<1> 7

FDI_INT B36 TP_PCH_FDI_INT 7

DIGITAL DISPLAY INTERFACE

DDPB_2N F6 TP_DP_IG_B_MLN<2> 7

FDI_FSYNC0 E34 TP_PCH_FDI_FSYNC<0> 7 DDPB_2P H6 TP_DP_IG_B_MLP<2> 7

FDI_FSYNC1 E36 TP_PCH_FDI_FSYNC<1> 7 DDPB_3N H4 TP_DP_IG_B_MLN<3> 7

DDPB_3P G4 TP_DP_IG_B_MLP<3> 7
85 PCH_DMI_COMP C21 DMI_ZCOMP FDI_LSYNC0 C35 TP_PCH_FDI_LSYNC<0> 7
SHORT THESE TWO PINS VERY NEAR THE PINS
PLACE THE RESISTOR VERY CLOSE TO COMMON POINT D21 DMI_IRCOMP FDI_LSYNC1 D35 TP_PCH_FDI_LSYNC<1> 7 (IPU)
DDPC_CTRLCLK AB10 TP_DP_IG_C_CTRL_CLK 7

DDPC_CTRLDATA AB11 TP_DP_IG_C_CTRL_DATA 7

SYSTEM POWER
(IPD)
91 46 27 IN PM_SYSRST_L AL38 SYS_RESET* WAKE* AR33 PCIE_WAKE_L IN 18 33 36
DDPC_AUXN L10 TP_DP_IG_C_AUX_N

MANAGEMENT
7

91 64 IN PM_SYS_PWRGD AT38 SYS_PWROK GPIO32 AJ40 PM_CLKRUN_L BI 14 46 48 91 DDPC_AUXP L9 TP_DP_IG_C_AUX_P 7

DDPC_HPD J3 TP_DP_IG_C_HPD 7
91 64 PM_PCH_PWRGD AM24 PWROK
C
IN
C 91 64 IN PM_ME_PWRGD AL33 MEPWROK SUS_STAT*/GPIO61 AK31 LPC_PWRDWN_L OUT 46 48
DDPC_0N
DDPC_0P
F4
E3
TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
7

7
INTERNAL DP
91 14 IN PM_LAN_PWRGD AY31 LAN_RST* SUSCLK/GPIO62 AH31 PM_CLK32K_SUSCLK_R OUT 8 85 91 DDPC_1N G3 TP_DP_IG_C_MLN<1> 7

DDPC_1P F2 TP_DP_IG_C_MLP<1> 7
91 10 OUT PM_MEM_PWRGD AW32 DRAMPWROK SLP_S5*/GPIO63 AU36 PM_SLP_S5_L OUT 47 91
DDPC_2N C4 TP_DP_IG_C_MLN<2> 7

91 63 IN PM_RSMRST_PCH_L AL24 RSMRST* SLP_S4* AP35 PM_SLP_S4_L OUT 18 47 91 DDPC_2P B4 TP_DP_IG_C_MLP<2> 7

DDPC_3N D2 TP_DP_IG_C_MLN<3> 7
91 PM_SUS_PWR_ACK AT37 SUS_PWR_DN_ACK/GPIO30 SLP_S3* AV35 PM_SLP_S3_L OUT 5 26 36 46 47 63 64 81 91
DDPC_3P D3 TP_DP_IG_C_MLP<3> 7

91 46 24 IN PM_PWRBTN_L AK36 PWRBTN* (IPU) SLP_M* AT36 PM_SLP_M_L OUT 63 91

(IPU)
DDPD_CTRLCLK AB7 TP_DP_IG_D_CTRL_CLK 7
18 IN PCH_ACPRESENT_GPIO31 AP40 ACPRESENT/GPIO31 TP23 AH35 TP_PM_SLP_DSW_L
DDPD_CTRLDATA AB9 TP_DP_IG_D_CTRL_DATA 7
(IPD)
91 46 14 IN PM_BATLOW_L AY34 GPIO72 PMSYNCH C37 PM_SYNC OUT 10 91 7 TP_CRT_IG_BLUE AB2 CRT_BLUE
DDPD_AUXN L4 TP_DP_IG_D_AUXN 7
7 TP_CRT_IG_GREEN AC3 CRT_GREEN
PCH_RI_L AT33 RI* SLP_LAN*/GPIO29 BA35 TP_SLP_LAN_L DDPD_AUXP K4 TP_DP_IG_D_AUXP 7
KEEPING TP, IF NEED TO USE IT LATER 7 TP_CRT_IG_RED AC1 CRT_RED
DDPD_HPD H2 TP_DP_IG_D_HPD 7

1
R1909 TP_CRT_IG_DDC_CLK AG2 CRT_DDC_CLK DDPD_0N B6 TP_DP_IG_D_MLN<0>

CRT
7 7
10K 7 TP_CRT_IG_DDC_DATA AG4 CRT_DDC_DATA DDPD_0P C5 TP_DP_IG_D_MLP<0> 7
1%
1/16W
DDPD_1N D7 TP_DP_IG_D_MLN<1> 7
MF-LF
402
2 7 TP_CRT_IG_HSYNC AD4 CRT_HSYNC DDPD_1P D6 TP_DP_IG_D_MLP<1> 7

7 TP_CRT_IG_VSYNC AD3 CRT_VSYNC DDPD_2N G8 TP_DP_IG_D_MLN<2> 7

DDPD_2P F8 TP_DP_IG_D_MLP<2> 7
=PP3V3_S5_PCH 5 17 18 23
PCH_DAC_IREF AE2 DAC_IREF DDPD_3N G9 TP_DP_IG_D_MLN<3> 7

AB4 CRT_IRTN DDPD_3P F9 TP_DP_IG_D_MLP<3> 7

1
1 R1951
R1961 1K
10K 5%
1% 1/16W

B
1/16W
MF-LF
402
2
MF-LF
2 402
PLACE CLOSE TO U1800 PIN
B
NOSTUFF
R1960
0
47 46 SMC_ADAPTER_EN 2 1 PCH_ACPRESENT_GPIO31 18

5%
1/16W
MF-LF
402

R1966
PM_SLP_S4_L 2
33 1 PM_SLP_S4_1_L
91 47 18 63 91
TO SMC To U6900
5%
1/16W
MF-LF
402

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

PCH DMI/FDI/GRAPHICS
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 18 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

IBEX-PEAK-DESKTOP
7 TP_PCI_AD<0> AT9 AD0 OMIT NV_CE0* H36 TP_NV_CE_L<0> 7

7 TP_PCI_AD<1>
TP_PCI_AD<2>
AP11 AD1 U1800 NV_CE1* H35 TP_NV_CE_L<1>
TP_NV_CE_L<2>
7

7 AU6 AD2 FCBGA NV_CE2* P32 7

7 TP_PCI_AD<3> AY10 AD3 NV_CE3* E41 TP_NV_CE_L<3> 7

7 TP_PCI_AD<4> AP9 AD4 (5 OF 10)

NV_DQS0 P36 TP_NV_DQS<0> 7
7 TP_PCI_AD<5> AV8 AD5
NV_DQS1 F40 TP_NV_DQS<1> 7
7 TP_PCI_AD<6> AR9 AD6
7 TP_PCI_AD<7> AV7 AD7 NV_DQ0/NV_IO0 T33 TP_NV_DQ<0> 7

D 7

7
TP_PCI_AD<8>
TP_PCI_AD<9>
AW9
AR3
AD8
AD9
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
P35
T31
TP_NV_DQ<1>
TP_NV_DQ<2>
7

7
D
7 TP_PCI_AD<10> AW7 AD10 NV_DQ3/NV_IO3 P33 TP_NV_DQ<3> 7

7 TP_PCI_AD<11> AR8 AD11 NV_DQ4/NV_IO4 M35 TP_NV_DQ<4> 7

NVRAM
7 TP_PCI_AD<12> AU3 AD12 NV_DQ5/NV_IO5 L33 TP_NV_DQ<5> 7

7 TP_PCI_AD<13> AP2 AD13 NV_DQ6/NV_IO6 M36 TP_NV_DQ<6> 7

7 TP_PCI_AD<14> AU1 AD14 NV_DQ7/NV_IO7 M34 TP_NV_DQ<7> 7

7 TP_PCI_AD<15> AN3 AD15 NV_DQ8/NV_IO8 M30 TP_NV_DQ<8> 7

7 TP_PCI_AD<16> AM2 AD16 NV_DQ9/NV_IO9 F36 TP_NV_DQ<9> 7

7 TP_PCI_AD<17> AM11 AD17 NV_DQ10/NV_IO10 H33 TP_NV_DQ<10> 7

7 TP_PCI_AD<18> AM4 AD18 NV_DQ11/NV_IO11 F37 TP_NV_DQ<11> 7

7 TP_PCI_AD<19> AY8 AD19 NV_DQ12/NV_IO12 E39 TP_NV_DQ<12> 7

7 TP_PCI_AD<20> AL10 AD20 NV_DQ13/NV_IO13 G33 TP_NV_DQ<13> 7

7 TP_PCI_AD<21> AT5 AD21 NV_DQ14/NV_IO14 D40 TP_NV_DQ<14> 7

7 TP_PCI_AD<22> AL2 AD22 NV_DQ15/NV_IO15 F33 TP_NV_DQ<15> 7

7 TP_PCI_AD<23> AT2 AD23

(IPD) NV_ALE J34 TP_NV_ALE 7
7 TP_PCI_AD<24> AL4 AD24
(IPD) NV_CLE L35 TP_NV_CLE 7
7 TP_PCI_AD<25> AV10 AD25
7 TP_PCI_AD<26> AL9 AD26 NV_RCOMP L36 TP_NV_RCOMP 7

7 TP_PCI_AD<27> AN7 AD27

(IPU) NV_RB* M32 TP_NV_RB_L 7
7 TP_PCI_AD<28> AK7 AD28
7 TP_PCI_AD<29> AN6 AD29 NV_WR0_RE* J36 TP_NV_WR_RE_L<0> 7

7 TP_PCI_AD<30> AH12 AD30 NV_WR1_RE* J35 TP_NV_WR_RE_L<1> 7

7 TP_PCI_AD<31> AN11 AD31

NV_WE_CK0* M31 TP_NV_WE_CK_L<0> 7

7 TP_PCI_C_BE_L<0> AV3 C/BE0* NV_WE_CK1* F38 TP_NV_WE_CK_L<1> 7

7 TP_PCI_C_BE_L<1> AY6 C/BE1*

C 5 =PP3V3_S0_PCH_GPIO
7

7
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>
AP5
AW10
C/BE2*
C/BE3*
USBP0N
USBP0P
AW25
AY25
USB_HUB1_UP_N
USB_HUB1_UP_P
BI 34 85

34 85
USB HUB 1
C
BI
R2010 10K 1 2 PCI_INTA_L AT8 PIRQA* USBP1N BA23 TP_USB_1N BI 7

(DPD)
5% 1/16W MF-LF 402
R2011 10K 1 2 PCI_INTB_L AR4 PIRQB* USBP1P AY24 TP_USB_1P BI 7
Unused
5% 1/16W MF-LF 402
R2012 10K 1 2 PCI_INTC_L AT11 PIRQC* USBP2N AW23 TP_USB_2N

PCI
BI 7
5% 1/16W MF-LF 402
R2013 10K 1 2 PCI_INTD_L BA5 PIRQD* USBP2P AY22 TP_USB_2P BI 7
Unused
5% 1/16W MF-LF 402
USBP3N AR22 TP_USB_3N
R2015 10K 1 2 85 PCI_REQ0_L AP4 REQ0* BI 7
Unused

EHCI1
5% 1/16W MF-LF 402 USBP3P AP22 TP_USB_3P
R2016 10K PCI_REQ1_L AW5 BI 7

NOTE: Internal pull-downs on all USB pins

1 2 85 REQ1*/GPIO50
5% 1/16W MF-LF 402 USBP4N AV21 TP_USB_4N
R2017 10K 1 2 PCI_REQ2_L AY4 REQ2*/GPIO52 BI 7
Unused
5% 1/16W MF-LF 402 USBP4P AV22 TP_USB_4P
R2018 10K 1 2 PCI_REQ3_L AH8 REQ3*/GPIO54
BI 7

5% 1/16W MF-LF 402 USBP5N AY20 TP_USB_5N BI 7

Unused
14 PCH_PCI_GNT0_L AK11 GNT0* (IPU) USBP5P AW21 TP_USB_5P BI 7

14 PCH_PCI_GNT1_L AK6 GNT1*/GPIO51 USBP6N AK20 TP_USB_6N BI 7

Unused
14 PCH_PCI_GNT2_L BA9 GNT2*/GPIO53 USBP6P AL20 TP_USB_6P BI 7

14 PCH_PCI_GNT3_L AM3 GNT3*/GPIO55 USBP7N AV20 TP_USB_7N BI 7

Unused
USBP7P AW19 TP_USB_7P
R2030 10K 1 2 PCI_INTE_L AU8 PIRQE*/GPIO2 BI 7

5% 1/16W MF-LF 402 USBP8N BA19 USB_HUB2_UP_N BI 35 85

61 AUD_IP_PERIPHERAL_DET AH7 PIRQF*/GPIO3 USB HUB 2
USBP8P AY18 USB_HUB2_UP_P
R2031 10K 1 2 PCI_INTG_L AP12 PIRQG*/GPIO4
BI 35 85

5% 1/16W MF-LF 402 USBP9N AM20 TP_USB_9N BI 7

(DPD)
62 AUD_I2C_INT_L AW4 PIRQH*/GPIO5 Unused

USB
USBP9P AN20 TP_USB_9P BI 7

7 TP_PCI_RESET_L AH10 PCIRST* USBP10N AV17 TP_USB_10N BI 7

Unused =PP3V3_S5_PCH_GPIO 5

EHCI2
USBP10P AV18 TP_USB_10P
R2020 10K 1 2 PCI_SERR_L AV6 SERR* BI 7

5% 1/16W MF-LF 402 USBP11N AR20 TP_USB_11N NO STUFF 1

R2067
1
R2064
1
R2066
R2021 10K 1 2 PCI_PERR_L AT4 PERR* BI 7
Unused 1
R2061
5% 1/16W MF-LF 402 USBP11P AT20 TP_USB_11P BI 7 10K 10K 10K
10K 5% 5% 5%
R2022 10K 1 2 PCI_IRDY_L AP7 IRDY* USBP12N AK18 TP_USB_12N BI 7 5% 1/16W 1/16W 1/16W
5% 1/16W MF-LF 402 Unused 1/16W MF-LF MF-LF MF-LF
7 TP_PCI_PAR AP6 PAR USBP12P AL18 TP_USB_12P BI 7 MF-LF
2
402
2
402
2
402

B R2023
R2024
10K
10K
1
1
2
2
5% 1/16W MF-LF 402
PCI_DEVSEL_L
PCI_FRAME_L
AT6
AL7
DEVSEL*
FRAME*
USBP13N
USBP13P
AY17
BA16
TP_USB_13N
TP_USB_13P
BI
BI
7

7
Unused
2
402

R2062 1
B
5% 1/16W MF-LF 402
R2027 10K 1 2 PCI_PLOCK_L AK12 PLOCK* R2060
1 10K
5%
R2065 1
1
R2068
5% 1/16W MF-LF 402 USBRBIAS* AY15 85 PCH_USB_RBIAS 10K 1/16W 10K 10K
5% MF-LF 5% 5%
R2025 10K 1 2 PCI_STOP_L AN8 STOP* USBRBIAS AV15
TIE TRACES TOGETHER CLOSE TO PINS
1/16W 402
2
1/16W 1/16W
5% 1/16W MF-LF 402 MF-LF MF-LF MF-LF
R2026 10K 1 2 PCI_TRDY_L AL6 TRDY* 402
2
402
2 2 402
5% 1/16W MF-LF 402
TP_PCI_PME_L AH11 PME* (IPU) OC0*/GPIO59 AT31 PCH_GPIO59_OC0_L
OC1*/GPIO40 AT30 USB_HUB_SOFT_RESET_L 34
91 27 OUT PLT_RESET_L AV34 PLTRST*
OC2*/GPIO41 AK28 PCH_GPIO41_OC2_L
85 27 OUT LPC_CLK33M_SMC_R AF6 CLKOUT_PCI0 OC3*/GPIO42 AP30 PCH_GPIO42_OC3_L
85 27 OUT LPC_CLK33M_LPCPLUS_R AD7 CLKOUT_PCI1 OC4*/GPIO43 AP31 PCH_GPIO43_OC4_L
TP_PCI_CLK33M_OUT2 AF9 CLKOUT_PCI2 OC5*/GPIO9 AL28 PCH_GPIO9_OC5_L
TP_PCI_CLK33M_OUT3 AD9 CLKOUT_PCI3 OC6*/GPIO10 AL30 PCH_GPIO10_OC6_L
85 27 OUT PCH_CLK33M_PCIOUT AD12 CLKOUT_PCI4 OC7*/GPIO14 AM30 PCH_GPIO14_OC7_L

R2070 1
22.6
1%
1/16W
MF-LF
402
2
PLACE THE RESISTOR CLOSE TO COMMON POINT

A SYNC_MASTER=NICK SYNC_DATE=12/08/2009 A
PAGE TITLE

PCH PCI/FLASHCACHE/USB
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 19 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

IPU* = Only on TACH function. =PP3V3_S0_PCH 5 17 20 23 69

69 23 20 17 5 =PP3V3_S0_PCH 14 PCH_GPIO0_BMBUSY_L AK41 BMBUSY*/GPIO0 OMIT CLKOUT_PCIE6N U4 TP_PCIE_CLK100M_XDPN 7

D 40 14 FW_PME_L AL14 TACH1/GPIO1 (IPU*)

U1800
IBEX-PEAK-DESKTOP
CLKOUT_PCIE6P V4 TP_PCIE_CLK100M_XDPP 7
R2150 1 1
R2155 D
R21901 14 PCH_GPIO6_TACH2 AV11 TACH2/GPIO6 (IPU*) FCBGA CLKOUT_PCIE7N T7 TP_DMI_CLK100M_LAN 7
10K
5%
10K
5%
OUT
47K 1/16W 1/16W
5% (6 OF 10) CLKOUT_PCIE7P T6 TP_DMI_CLK100M_LAP 7 MF-LF MF-LF
1/16W 46 14 IN SMC_RUNTIME_SCI_L AY11 TACH3/GPIO7 (IPU*) 402
2 2
402
MF-LF
402
2 14 PCH_GPIO8_FCIM_EN_L AK30 GPIO8 (IPU) MISC A20GATE AG37 PCH_A20GATE

37 14 ENET_LOW_PWR AU34 LAN_PHY_PWR_CTRL/GPIO12

CLKOUT_BCLK0_N/CLKOUT_PCIE8N L38 FSB_CLK133M_CPU_N OUT 10 84
14 PCH_GPIO15 AY36 GPIO15 (IPD)
CLKOUT_BCLK0_P/CLKOUT_PCIE8P K38 FSB_CLK133M_CPU_P OUT 10 84

62 AUD_IPHS_SWITCH_EN AH39 SATA4GP/GPIO16

PECI D36 CPU_PECI BI 10
48 IN LPCPLUS_GPIO AW11 TACH0/GPIO17 (IPU*)

CPU
14 ODD_PWR_EN_L AN41 SCLOCK/GPIO22 RCIN* AM40 PCH_RCIN_L

14 IN PCH_GPIO24 AR34 GPIO24

PROCPWRGD B38 CPU_PWRGD OUT 10 24 91

14 PCH_GPIO27_VRMEN AP37 GPIO27

THRMTRIP* C38 PM_THRMTRIP_L IN 10 47 91
26 OUT ISOLATE_CPU_MEM_L AV40 GPIO28

GPIO
14 PCH_GPIO34_STP_PCI_L AT40 STP_PCI*/GPIO34
TP1 L18 TP_PCH_TP1
5 MXM_GOOD AR41 GPIO35
TP2 K18 TP_PCH_TP2
92 91 44 SDCARD_RESET AK39 SATA2GP/GPIO36

14 PCH_GPIO37_SATA3GP AR38 SATA3GP/GPIO37 TP3 J20 TP_PCH_TP3

14 PCH_GPIO38_SLOAD AM38 SLOAD/GPIO38

TP4 P12 TP_PCH_TP4
14 PCH_GPIO39_SDATAOUT0 AL39 SDATAOUT0/GPIO39
C 36 14 WOL_EN AV36 PCIECLKRQ6*/GPIO45
TP5 P13 TP_PCH_TP5 C
14 AP_PWR_EN AP36 PCIECLKRQ7*/GPIO46 TP6 T13 TP_PCH_TP6

14 FW_PWR_EN AG38 SDATAOUT1/GPIO48

TP7 T12 TP_PCH_TP7
14 PCH_GPIO49_SATA5GP AG40 SATA5GP/GPIO49
TP8 V34 TP_PCH_TP8
85 48 SPIROM_USE_MLB AL32 GPIO57

TP9 AT24 TP_PCH_TP9

TP10 AR24 TP_PCH_TP10

TP11 V20 TP_PCH_TP11

7 TP_PCH_PWM0 BA12 PWM0

RSVD
7 TP_PCH_PWM1 AR12 PWM1 TP12 P10 TP_PCH_TP12
7 TP_PCH_PWM2 AW12 PWM2
7 TP_PCH_PWM3 AY13 PWM3 TP13 P9 TP_PCH_TP13

7 TP_PCH_SST AN31 SST TP20 AU39 TP_PCH_TP20

TP21 AH30 TP_PCH_TP21

TP22_NCTF0 A3
TP22_NCTF1 A41
TP22_NCTF2 AY1
TP22_NCTF3 BA41
A40 VSS_NCTF0

B A5
AW41
VSS_NCTF1
VSS_NCTF2
TP18 AK35 TP_PCH_TP18
B
AY2 VSS_NCTF3 TP19 AN36 TP_PCH_TP19
AY41 VSS_NCTF4

NCTF
B2 VSS_NCTF5
NC0 AF15
B40 VSS_NCTF6
NC1 V10
B41 VSS_NCTF7
NC2 V11
BA1 VSS_NCTF8
NC3 Y11
BA2 VSS_NCTF9
NC4 Y12
C1 VSS_NCTF10
C41 VSS_NCTF11
E1 VSS_NCTF12 (IPD) INIT3_3V* AR39 PCH_INIT3V3_L 14

THIS SIGNAL IS INTEDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

A SYNC_MASTER=K23F SYNC_DATE=11/30/2009 A
PAGE TITLE

PCH MISC
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 20 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT
IBEX-PEAK-DESKTOP
U1800
IBEX-PEAK-DESKTOP OMIT

PP1V05_S0_PCH_VCCA_CLK
FCBGA
=PP1V05_S0_PCH_VCCIO_USB
U1800
89 23 (10 OF 10) 5 23 FCBGA
3.251 A
AA1 VCCACLK VCCIO4 AH23
(VCCIO[1-56] total) (7 OF 10)

USB
VCCIO5 AJ22 89 16 PP3V3_S0_PCH_VCCA_DAC =PP1V05_S0_PCH_VCC_CORE 5 23

NAND / SPI DMI CRT

VCCIO6 AT28 69 MA AF1 VCCADAC VCCCORE0 A26 1.629 A
23 5 =PP1V05_SM_PCH_VCC_LAN
VCCIO7 B24 =PP1V05_S0_PCH_VCCIO_DMI VCCCORE1 A28

D 372 MA S0, 78 MA M-ON Y20

Y22
VCCLAN0
VCCLAN1 =PP3V3_S5_PCH_VCCSUS3_3_USB
5 21 23

5 23
89 23 21 PP1V8R1V5_S0_PCH_VCCVRM VCCCORE2 AA23 D
196 MA ( TOTAL 4 PINS) C3 VCCVRM1 VCCCORE3 AA24
VCCSUS3_3_0 AK26 163 mA S0, 65 mA S3-S5
PCH output, for decoupling only VCCCORE4 AB24
VCCSUS3_3_1 AL26 (VCCSUS3_3 - 17 TOTAL) 23 5 =PPVTT_S0_PCH_VCC_DMI
89 PPVOUT_S5_PCH_DCPSUSBYP AF27 DCPSUSBYP VCCCORE5 AB26

CLOCK AND MISCELLANEOUS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V VCCSUS3_3_2 AM26 65 MA A23 VCCDMI
VCCCORE6 AD18
NOSTUFF 1 23 21 5 =PP1V05_SM_PCH_VCC_ME VCCSUS3_3_3 AN26
C2260 =PP3V3R1V8_S0_PCH_VCCPNAND
VCCCORE7 AD20
0.1UF 2.222A S0, 800 MA M-ON AA15 VCCME0 VCCSUS3_3_4 AP26 23 5
20%
VCCCORE8 AD23
10V (VCCME[1-16] total) AA16 VCCME1 VCCSUS3_3_5 AR26 156 MA (1.8V) M39 VCCPNAND0
CERM 2 VCCCORE9 AD26
AA18 VCCME2 VCCSUS3_3_6 AT26 M41 VCCPNAND1
402 1 C2200 VCCCORE10 AE18
0.1UF AB15 VCCME3 VCCSUS3_3_7 AU26 P30 VCCPNAND2
20%
VCCCORE11 AE19
10V
AB16 VCCME4 VCCSUS3_3_8 AU27
2 CERM 23 5 =PP3V3_SM_PCH_VCC_ME VCCCORE12 AE20
402
AD13 VCCME5 VCCSUS3_3_9 AV25
85 mA S0, 22 mA M-on N38 VCCME3_3_0 VCCCORE13 AE22
AD15 VCCME6 VCCSUS3_3_10 AV27
N40 VCCME3_3_1 VCCCORE14 AE23
AD16 VCCME7 VCCSUS3_3_11 AV29
PLACE C2260 ON THE BACK SIDE NEAR AF27 VCCCORE15 AE24
AE15 VCCME8 VCCSUS3_3_12 AW26
VCCCORE16 AE26
AE16 VCCME9 VCCSUS3_3_13 AW39 M24 VCCIO23
VCCCORE17 AF19
AF10 VCCME10 VCCSUS3_3_14 AW40
89 23 PP1V05_S0_PCH_VCCAPLL_EXP VCCCORE18 AF20
AF13 VCCME11 VCCSUS3_3_15 AY27
40 mA (if GPIO27 is low) A21 VCCAPLLEXP VCCCORE19 AF22
VCCSUS3_3_16 BA26
PCH output, for decoupling only VCCCORE20 AF23
23 18 17 5 =PP1V05_S0_PCH_VCCIO_PCIE
89 PPVOUT_G3_PCH_DCPRTC AY38 DCPRTC VCCCORE21 AF24
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 3.251 A M26 VCCIO24
VCCCORE22 B27
89 23 21 PP1V8R1V5_S0_PCH_VCCVRM (VCCIO[1-56] total) N16 VCCIO25
1
C2210 VCCCORE23 B29
0.1UF 196 MA (VCCVRM[0-3] TOTAL) L39 VCCVRM2 N18 VCCIO26
20%
VCCCORE24 C26
N20 VCCIO27

VCC CORE
10V PP1V05_S0_PCH_VCCADPLLA
2 CERM 89 16 VCCCORE25 C28
402
N22 VCCIO28
75 MA R2 VCCADPLLA VCCCORE26 D27
N24 VCCIO29
VCCSUS3_3_NCTF0 AY40 VCCCORE27 D28
N26 VCCIO30
C 89 16 PP1V05_S0_PCH_VCCADPLLB
75 MA T1 VCCADPLLB
VCCSUS3_3_NCTF1 BA40
P15
P16
VCCIO31
VCCIO32
VCCCORE28
VCCCORE29
D29
E26 C
VCCCORE30 E27
P18 VCCIO33
VCCCORE31 E29
P19 VCCIO34
23 21 5 =PP1V05_S0_PCH_VCCIO_DMI VCCCORE32 F28
P24 VCCIO35
3.251 A M18 VCCIO20 VCCCORE33 G28
=PP1V05_S0_PCH_VCCIO_SATA P38 VCCIO36

VCCIO
23 21 17 5
(VCCIO[1-56] total) M20 VCCIO21 VCCCORE34 H28
PP5V_S5_PCH_V5REFSUS 23 89 3.251 A P39 VCCIO37
M22 VCCIO22 VCCCORE35 J28
V5REF_SUS AW16 < 1 mA S0-S5 (VCCIO[1-56] total) R37 VCCIO38
VCCCORE36 K28
R38 VCCIO39
AA27 VCCIO1 PP5V_S0_PCH_V5REF 23 89 VCCCORE37 L28
R40 VCCIO40
AH20 VCCIO2 V5REF AN1 < 1 mA VCCCORE38 M28
PCI/GPIO/LPC

T15 VCCIO41
AH22 VCCIO3 VCCCORE39 N28
=PP3V3_S0_PCH_VCC3_3_PCI 5 21 23 T19 VCCIO42
VCCCORE40 P26
PCH output, for decoupling only VCC3_3_7 AK14 357 mA T29 VCCIO43
VCCCORE41 P27
89 PPVOUT_S0_PCH_DCPSST AH33 DCPSST VCC3_3_8 AV2 (VCC3_3[1-14] total) T30 VCCIO44
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V VCCCORE42 P29
VCC3_3_9 AY3 T36 VCCIO45
PCH output, for decoupling only VCCCORE43 T20
1
C2220 89 PPVOUT_S5_PCH_DCPSUS AF30
VCC3_3_10 U40 =PP3V3_S0_PCH_VCC3_3_SATA 5 21 23 T37 VCCIO46
T22
0.1UF DCPSUS VCCCORE44
20% MIN_LINE_WIDTH=0.2 mm U15 VCCIO47
10V MIN_NECK_WIDTH=0.2 mm VCC3_3_NCTF0 AW1 VCCCORE45 T23
2 CERM VOLTAGE=3.3V U19 VCCIO48
AH13 VCCME16 VCC3_3_NCTF1 BA3 VCCCORE46 T24
402 1
C2230 V15 VCCIO49
0.1UF AH3 VCCME17 VCCCORE47 T26
20%
V29 VCCIO50
10V
AH4 VCCME18 VCCCORE48 T27
2 CERM
V36 VCCIO51
402 AH6 VCCME19 VCCCORE49 U20
PP1V05_S0_PCH_VCCAPLL_SATA 23 89 Y26 VCCIO52
AJ2 VCCME20 VCCCORE50 U22
VCCSATAPLL P41 31 mA (if GPIO27 is low)
AJ4 VCCME21 Y29 VCCIO53 VCCCORE51 U23
AJ5 VCCME22 Y36 VCCIO54 VCCCORE52 U26
Y15 VCCME23 =PP1V05_S0_PCH_VCCIO_DMI 5 21 23 VCCCORE53 V23
3.251 A 23 21 5 =PP3V3_S0_PCH_VCC3_3_PCI
Y16 VCCME24 VCCIO8 B25 VCCCORE54 V24
B Y18 VCCME25
(VCCIO[1-56] total)
PP1V8R1V5_S0_PCH_VCCVRM 21 23 89
357 mA (VCC3_3[1-14] total) A9 VCC3_3_0
VCCCORE55 V26 B
Y19 VCCME26 89 23 21 PP1V8R1V5_S0_PCH_VCCVRM VCCCORE56 Y23
VCCVRM3 L40 196 MA (VCCVRM[0-3] TOTAL)
196 MA (VCCVRM[0-3] TOTAL) C2 VCCVRM0 VCCCORE57 Y24
=PP3V3_S0_PCH_VCC3_3_CORE
PCI/GPIO/LPC

23 5

HVCMOS
FDI
89 23 PP1V05_S0_PCH_VCCAPLL_FDI
357 mA AH18 VCC3_3_4 VCCIO9 C24 GPIO27 HDA_SYNC VCCVRM PLL POWERS A37
=PP3V3_S0_PCH_VCC3_3_SATA 5 21 23
5 mA (if GPIO27 is low) VCCFDIPLL 357 mA (VCC3_3[1-14] total)
SATA

(VCC3_3 - 9 TOTAL PINS) AJ14 VCC3_3_5 VCCIO10 C25 VCC3_3_1 AD27

AJ16 VCC3_3_6 VCCIO11 D24 1 (IPU) 0 (IPD) 1.8V Float 23 21 17 5 =PP1V05_S0_PCH_VCCIO_SATA VCC3_3_2 AE27
VCCIO12 D25 3.251 A AA26 VCCIO0 VCC3_3_3 AH16
F26
1 (IPU) 1 1.5V Float
VCCIO13 (VCCIO[1-56] total)
VCCIO14 G26 0 1 1.5V 1.05V
VCCIO15 H26
J26
0 0 1.8V 1.05V
VCCIO16
VCCIO17 K26
Note: 1.5V option consumes more current than 1.8V
L26
CPU

VCCIO18
PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL
VCCIO19 M16
23 5 =PPVTT_S0_PCH_VCCP_CPU
< 1 mA B39 V_CPU_IO =PP1V05_SM_PCH_VCC_ME 5 21 23

A39 V_CPU_IO_NCTF VCCME12 AF16 2.222 A S0, 800 MA M-ON

VCCME13 AF8 (VCCME[1-16] total)
VCCME14 AG5
VCCME15 AH1

PPVOUT_S0_PCH_VCCRTC_NCTF BA39 VCCRTC_NCTF =PP3V3R1V5_S0_PCH_VCCSUSHDA

RTC
HDA

5 23
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
89 27 23 17 PP3V3_G3_RTC AY29 VCCRTC VCCSUSHDA AJ18 6 MA S0
2 mA S0-S5, ~6 uA G3
1 C2250
0.1UF

A
20%
10V
2 CERM
402
PAGE TITLE
A
PCH POWER
DRAWING NUMBER SIZE

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 21 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

IBEX-PEAK-DESKTOP IBEX-PEAK-DESKTOP
A14 OMIT AJ24
C11 OMIT L22
A30 U1800 AJ26
C17 U1800 L3
A35 FCBGA AJ28
C18 FCBGA L30
A7 AK10
(8 OF 10) C23 (9 OF 10) L31
AA19 AK22

D AA20 AK3
C31
C32
L32
L34
D
AA22 AK32
C39 L8
AA38 AK34
D22 M11
AA39 AK37
D34 M12
AA4 AK5
D37 M14
AA41 AK8
D39 M33
AB18 AK9
E12 M37
AB19 AL8
E13 M5
AB20 AM10
E15 M8
AB22 AM12
E16 N14
AB23 AM14
E19 N37
AB27 AM18
E22 N5
AB29 AM28
E23 P1
AB30 AM32
E30 P11
AB33 AN12
E33 P20
AB34 AN14
E37 P22
AB40 AN18
E4 P23
AB5 AN22
E5 P31
AB8 AN28
E6 P34
AC37 AN30
E8 P4
AC5 AN37
E9 P8
AD11 AN5
F11 R4
AD19 AP20
F12 R5
AD2 AP24
F14 T11
AD22 AR1
F16 T16
AD24 AR11
F18 T18
C AD29
AD30
VSS VSS
AR18
AR28
F20
F24
VSS VSS
T3
T35
C
AD31 AR30
F30 T5
AD34 AT14
F34 T8
AD39 AT18
F5 U16
AD40 AT22
G1 U18
AD6 AU12
G34 U2
AD8 AU16
G38 U24
AE3 AU19
G39 U27
AE39 AU20
G41 U3
AE4 AU22
H31 U39
AF11 AU23
H5 V12
AF12 AU29
H7 V13
AF18 AU30
H9 V16
AF26 AU33
J14 V18
AF29 AU37
J16 V19
AF3 AU38
J18 V22
AF31 AU41
J24 V27
AF32 AU5
J37 V3
AF33 AU9
J39 V33
AF36 AV24
J5 V35
AF37 AV28
J6 V39
AF39 AV5
J7 V6
AF5 AW17
K16 V9
AH15 AW18
K2 W3
AH19 AW24
K20 W37
AH24 AW28
B AH26 AW3
K22
K3
W39
W5
B
AH27 B10
K32 Y10
AH29 B22
K39 Y13
AH32 BA14
K40 Y27
AH34 BA21
L11 Y30
AH36 BA28
L12 Y33
AH41 BA37
L16 Y40
AH9 BA7
L20 Y5
AJ20 C10

A SYNC_MASTER=K23F SYNC_DATE=11/30/2009 A
PAGE TITLE

PCH GROUNDS
DRAWING NUMBER SIZE

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 22 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH VCCRTC BYPASS PCH VCCPNAND BYPASS
18 17 5 =PP3V3_S5_PCH (PCH RTC 3.3V PWR) (PCH NAND 1.8V/3.3V PWR)
5 =PP5V_S5_PCH PCH V5REF_SUS Filter & Follower
89 27 21 17 PP3V3_G3_RTC 21 5 =PP3V3R1V8_S0_PCH_VCCPNAND
1 mA S0-S5 (PCH Reference for 5V Tolerance on USB)
2 4 2 mA S0-S5 / NOSTUFF
R2400 2 D2400 6 uA G3 1
C2440 1 C2441
10 NC 0.1UF 0.1UF
5% BAT54DW-X-G C2420 1 1
C2421 1
C2422

NC
1/16W 10% 10%
MF-LF 3
SOT-363 1UF 0.1UF 0.1UF PLACEMENT_NOTE: 2
16V
2 16V
10% 10% 10% X5R X5R
402 6.3V 16V 16V 402 402
1
CERM 2 2 X5R 2 X5R
402 402 402 PLACE C2440 NEAR BALL P30
PP5V_S5_PCH_V5REFSUS 21 89 PLACE C2441 NEAR BALL P30
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM <1 MA S0-S5
VOLTAGE=5V PLACEMENT_NOTEs (all 3):
C2400 1 PCH VCCSUSHDA BYPASS
PLACE C2421 NEAR BALL AY29
D
0.1UF
20%
10V
CERM 2 PLACEMENT_NOTE:
PLACE C2420 NEAR BALL AY29 (PCH HD Audio 3.3V/1.5V PWR)
PCH VCCIO BYPASS
D
402 PCH VCCSUS3_3 BYPASS 21 5 =PP3V3R1V5_S0_PCH_VCCSUSHDA
(PCH CLK 1.05V PWR)
PLACE C2400 NEAR BALL AW16 6 MA
(PCH SUSPEND USB 3.3V PWR)
=PP3V3_S5_PCH_VCCSUS3_3_USB
1
C2445 21 5 =PP1V05_S0_PCH_VCCIO_DMI
23 21 5
1UF
10%
6.3V
PLACEMENT_NOTE: 2
1 C2425 CERM
20 17 5 =PP3V3_S0_PCH
0.1UF
402 1
C2475 1
C2476 1
C2477
69 PLACE C2445 NEAR BALL AJ18 1UF 1UF 1UF
5 =PP5V_S0_PCH PCH V5REF Filter & Follower 10%
16V 10% 10% 10%
PLACEMENT_NOTE: 2 X5R 6.3V 6.3V 6.3V
1 mA (PCH Reference for 5V Tolerance on PCI)

(VCCSUS3_3 Total)
402 2 CERM 2 CERM 2 CERM
2 1 402 402 402
R2401 PLACE C2425 NEAR BALL AV25 PCH V_CPU_IO BYPASS
100
5 D2400 (PCH 1.1V/1.05V CPU I/O PWR)
5%
NC BAT54DW-X-G PLACEMENT_NOTEs:
NC

1/16W SOT-363
MF-LF 6 357 MA S0 / PCH USB/VCCSUS3_3 BYPASS 21 5 =PPVTT_S0_PCH_VCCP_CPU
PLACE C2475 NEAR BALL D25

(VCCIO TOTAL)
402
1
88 MA S3-S5 (PCH SUSPEND USB 3.3V PWR) <1 MA
PLACE C2476 NEAR BALL H26
PP5V_S0_PCH_V5REF 21 89
MIN_LINE_WIDTH=0.3MM 23 21 5 =PP3V3_S5_PCH_VCCSUS3_3_USB PLACE C2477 NEAR BALL AH22
MIN_NECK_WIDTH=0.25MM <1 MA C2450 1 1 C2451 1 C2452 3.251 A S0 /
VOLTAGE=5V 4.7UF 0.1UF 0.1UF
C2401 1
20% 10% 10%
369 MA IDLE PCH VCCIO BYPASS
1UF 6.3V
2 2
16V
2
16V
(PCH USB 1.05V PWR)
10%
10V
1 C2426 1 C2427 X5R
603
X5R
402
X5R
402
X5R 2 PLACEMENT_NOTE: 0.1UF 0.1UF
402 10% 10%
21 5 =PP1V05_S0_PCH_VCCIO_USB
16V 16V
PLACE C2401 NEAR BALL AN1 2 X5R 2 X5R PLACEMENT_NOTEs (all 3):
PLACEMENT_NOTEs: 402 402
PLACE C2450 NEAR BALL B39 C2488 1 1
C2480
4.7UF 1UF
PLACE C2426 NEAR BALL AW39 20% 10%
6.3V 6.3V
PCH VCCIO BYPASS PLACEMENT_NOTE: X5R 2 2 CERM
PLACE C2427 NEAR BALL AJ18 603 402
(PCH DMI 1.05V PWR)
PLACE C2480 NEAR BALL AJ22
PCH VCCME3_3 BYPASS PLACE C2488 NEAR BALL AH23
21 5 =PPVTT_S0_PCH_VCC_DMI
(PCH ME 3.3V PWR)
65 MA
C PCH_VRM
GPIO27: 1 = enabled, 0 = disabled 21 5 =PP3V3_SM_PCH_VCC_ME 1
C2455
1UF
PCH VCCIO BYPASS
(PCH SATA 1.05V PWR)
C
PP1V8R1V5_S0_PCH_VCCVRM 21 89
10%

=PP1V8R1V5_S0_PCH_VCCVRM R2410 MIN_LINE_WIDTH=0.5MM

1
C2430 PLACEMENT_NOTE: 2
6.3V
CERM 21 17 5 =PP1V05_S0_PCH_VCCIO_SATA
5 MIN_NECK_WIDTH=0.25MM 196 MA 0.1UF 402
0 VOLTAGE=1.5V
10%
196 MA 1 2 MAKE_BASE=TRUE (OR 1.5V) PLACE C2455 NEAR BALL A23
PLACEMENT_NOTE: 2
16V
C2486 1 1
C2485
5% X5R
1/16W 402 22UF 1UF
20% 10%
MF-LF PLACE C2430 NEAR BALL N38 6.3V 6.3V
402 NOTE: VccVRM input also supports PCH VCCLAN BYPASS PLACEMENT_NOTE: CERM 2 2 CERM
805 402
1.5V, but draws more current. (PCH 1.05V LAN Core PWR)
PLACE C2485 NEAR BALL Y26
HDA_SYNC: 0 = 1.8V, 1 = 1.5V PCH CORE/VCC3_3 BYPASS PLACE C2465 NEAR BALL Y29
21 5 =PP1V05_SM_PCH_VCC_LAN
(PCH MISC 3.3V PWR)
372 MA
PCH VCCAPLLEXP Filter
21 5 =PP3V3_S0_PCH_VCC3_3_CORE
1
R2460 PCH VCCIO BYPASS
(PCH PCIe PLL PWR) 1K (PCH PCIE 1.05V PWR)
5%
PP1V05_S0_PCH_VCCAPLL_EXP 21 89
1 1/16W
MIN_LINE_WIDTH=0.5MM
1
C2435 C2439 PLACEMENT_NOTE: MF-LF 21 18 17 5 =PP1V05_S0_PCH_VCCIO_PCIE
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V 0.1UF 0.1UF 2 402
10% 10%
16V 16V
PLACEMENT_NOTE: 2 X5R 2 X5R
402 402
C2490 1 1
C2491 1
C2492 1
C2493 1
C2494
1
C2413 PLACE C2435 NEAR BALL AE27 22UF 1UF 1UF 1UF 1UF
1UF PLACE C2439 NEAR BALL A9 PCH VCCME BYPASS 20% 10% 10% 10% 10%
10% 6.3V 6.3V 6.3V 6.3V 6.3V
6.3V (PCH 1.05V ME Core PWR) CERM 2 2 CERM 2 CERM 2 CERM 2 CERM
2 CERM PLACEMENT_NOTEs: 805 402 402 402 402
402 PCH VCC3_3 BYPASS
21 5 =PP1V05_SM_PCH_VCC_ME
(PCH PCI 3.3V PWR) 2.22 A
PLACEMENT_NOTEs (all 5):
21 5 =PP3V3_S0_PCH_VCC3_3_PCI
PLACE C2413 AT BALL A21 1 PLACE C2465 NEAR BALL P18
NOSTUFF C2465 1
C2466 1
C2467 1
C2468 1
C2469
1 1 22UF 22UF 10UF 1UF 1UF PLACE C2491 NEAR BALL P18
PCH VCCFDIPLL Filter 1
C2436 C2437 C2438 20% 20% 20% 10% 10%
0.1UF 0.1UF 0.1UF 6.3V 6.3V 6.3V 6.3V 6.3V PLACE C2492 NEAR BALL P15
(PCH FDI PLL PWR) 10% 10% 10% CERM 2 CERM 2 X5R 2 2 CERM 2 CERM
16V PLACE C2493 NEAR BALL U15
PLACEMENT_NOTE: 2 X5R 2 16V
X5R 2 16V
X5R
805 805 603 402 402
PP1V05_S0_PCH_VCCAPLL_FDI PLACE C2465 NEAR BALL P24
B MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
21 89

PLACE C2436 NEAR BALL AV2

PLACE C2437 NEAR BALL AH16
402 402 402
PLACEMENT_NOTEs: B
PLACE C2438 NEAR BALL AH16
PLACE C2465 NEAR BALL AB15
PLACE C2466 NEAR BALL AH4
1 C2415
1UF PCH VCC3_3 BYPASS PLACE C2467 NEAR BALL AH1
10%
6.3V (PCH SATA 3.3V PWR) PLACE C2468 NEAR BALL AJ4
2 CERM PLACEMENT_NOTEs:
402 PLACE C2469 NEAR BALL AF10
21 5 =PP3V3_S0_PCH_VCC3_3_SATA

1
C2446
PLACE C2415 AT BALL A37 0.1UF
10%
16V
PCH VCCSATAPLL Filter PLACEMENT_NOTE: 2 X5R
402
(PCH SATA PLL PWR)
PLACE C2446 NEAR BALL U40
PP1V05_S0_PCH_VCCAPLL_SATA 21 89
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V

1
C2417
1UF
10%
6.3V
2 CERM PLACEMENT_NOTEs:
402

PCH VCCCORE BYPASS

(PCH 1.05V CORE PWR)
PLACE C2417 AT BALL P41
21 5 =PP1V05_S0_PCH_VCC_CORE
PCH VCCACLK Filter
1.629 A
(PCH Misc PLL PWR)
A PP1V05_S0_PCH_VCCA_CLK
MIN_LINE_WIDTH=0.5MM
21 89 C2470 1 1 C2471 1 C2472 1 C2473 SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
MIN_NECK_WIDTH=0.25MM
10UF 1UF 4.7UF 22UF PAGE TITLE
VOLTAGE=1.05V 20%
6.3V
X5R
603
2 2
10%
6.3V
CERM
402
2
20%
6.3V
X5R
603
20%
2 6.3V
CERM
805
PCH DECOUPLING
PLACEMENT_NOTEs: DRAWING NUMBER SIZE
1 C2419
PLACE C2470 NEAR BALL AE18 Apple Inc. 051-8337 D
1UF PLACE C2471 NEAR BALL AE18 REVISION
10%
PLACE C2472 NEAR BALL AE18
2
6.3V
CERM PLACEMENT_NOTEs: PLACE C2473 NEAR BALL AE18
R
A.0.0
402
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PLACE C2419 AT BALL AA1 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
24 OF 110

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.
IV ALL RIGHTS RESERVED 23 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROCESSOR MINI XDP
5 =PPVTT_S0_XDP

XDP_CPU_BPM CRITICAL XDP

RP2500 XDP_CONN 1
R2515
84 10 IN XDP_BPM_L<0> 1 8
J2500 51
5%
PLACE IT NEAR THE XDP
84 10 IN XDP_BPM_L<1> 2
0
7
DF40C-60DS-0.4V 1/16W
5% F-ST-SM-HF MF-LF
84 10 IN XDP_BPM_L<2> 3
1/16W
6
402
2
SM-LF
XDP_BPM_L<3> 4 5 1 2

D
84 10 IN
10 BI XDP_PREQ_L OBSFN_A0 3
5
4
6
OBSFN_C0 CPU_CFG<8> IN 9 84 D
XDP_CPU_CFG 10 IN XDP_PRDY_L OBSFN_A1 OBSFN_C1 CPU_CFG<9> IN 9 84

RP2501 7 8

84 9 CPU_CFG<12> 1 8 84 XDP_OBSDATA_A<0> OBSDATA_A0 9 10 OBSDATA_C0 CPU_CFG<0> 9 84

IN IN
84 9 CPU_CFG<13> 2
0
7 84 XDP_OBSDATA_A<1> OBSDATA_A1 11 12 OBSDATA_C1 CPU_CFG<1> 9 84
IN IN
5%
84 9 CPU_CFG<14> 3
1/16W
6 13 14
IN
SM-LF
84 9 CPU_CFG<15> 4 5 84 XDP_OBSDATA_A<2> OBSDATA_A2 15 16 OBSDATA_C2 CPU_CFG<2> 9 84
IN IN
84 XDP_OBSDATA_A<3> OBSDATA_A3 17 18 OBSDATA_C3 CPU_CFG<3> 9 14 84
IN
PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs.
19 20

84 9 CPU_CFG<17> OBSFN_B0 21 22 OBSFN_D0 CPU_CFG<10> 9 84

IN IN
84 9 CPU_CFG<16> OBSFN_B1 23 24 OBSFN_D1 CPU_CFG<11> 9 84
IN IN
25 26

84 10 XDP_BPM_L<4> OBSDATA_B0 27 28 OBSDATA_D0 CPU_CFG<4> 9 84

IN IN
84 10 XDP_BPM_L<5> OBSDATA_B1 29 30 OBSDATA_D1 CPU_CFG<5> 9 84
IN IN
31 32

84 10 XDP_BPM_L<6> OBSDATA_B2 33 34 OBSDATA_D2 CPU_CFG<6> 9 84

IN IN
XDP 35 36
84 10 IN XDP_BPM_L<7> OBSDATA_B3 OBSDATA_D3 CPU_CFG<7> IN 9 84
R2510 37 38
1K 39 40
91 20 10 IN CPU_PWRGD 1 2 91 XDP_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 FSB_CLK133M_ITP_P IN 10 84
41 42 XDP
5% 91 46 18 IN PM_PWRBTN_L HOOK1 ITPCLK#/HOOK5 FSB_CLK133M_ITP_N IN 10 84
1/16W
MF-LF VCC_OBS_AB 43 44 VCC_OBS_CD R2511
402
45 46
1K
91 10 IN XDP_CPUPWRGD HOOK2 RESET#/HOOK6 XDP_CPURST_L 1 2 FSB_CPURSTOUT_L IN 10 91

TP_XDP_HOOK3 HOOK3 47 48 DBR#/HOOK7 XDP_DBRESET_L 10 27 91 5% PLACEMENT_NOTE=Place close to CPU to minimize stub.

OUT 1/16W
49 50 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. MF-LF
402
49 =SMBUS_XDP_SDA SDA 51 52 TDO XDP_TDO 10
BI IN
49 =SMBUS_XDP_SCL SCL 53 54 TRSTn XDP_TRST_L 10
BI OUT

C 10 OUT XDP_TCK
TCK1
TCK0
NC
55
57
56
58
TDI
TMS
XDP_TDI
XDP_TMS
OUT
OUT
10

10
C
59 60 XDP_PRESENT#
XDP XDP
C2500 1 1
C2501
0.1uF 517S0774 0.1uF
10% 10%
16V 16V
X5R 2 2 X5R
402 402

B B

A SYNC_MASTER=NICK SYNC_DATE=12/08/2009 A
PAGE TITLE

EXTENDED DEBUG PORT(XDP)

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 24 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
BUF_CLK BUF_CLK
BUF_CLK
L2600 L2650
FERR-120-OHM-1.5A FERR-120-OHM-1.5A R2650
=PP1V05_S0_CK505 1 2 89 PP1V05_S0_CK505_F =PP1V5_S0_CK505 1 2 89 PP1V5_S0_CK505_F 1
2.2 2 89 PP1V5_S0_CK505_R
5 5
0402
MIN_LINE_WIDTH=0.5mm
0402
MIN_LINE_WIDTH=0.5mm BUF_CLK BUF_CLK BUF_CLK
MIN_NECK_WIDTH=0.2mm BUF_CLK BUF_CLK BUF_CLK BUF_CLK BUF_CLK MIN_NECK_WIDTH=0.2mm 5% PLACE IT CLOSE TO POWER PINS
VOLTAGE=1.05V VOLTAGE=1.5V 1/16W C2650 1 1 C2652
C2600 1 1 C2602 1 C2603 1 C2604 1 C2605 MF-LF
402 10UF
1 C2651 0.1UF
10UF 0.1UF 0.1UF 0.1UF 0.1UF 20% 0.1UF 10%
20% 10% 10% 10% 10% 6.3V 10% 16V
6.3V 16V 16V 16V 16V X5R 2 16V 2 X5R
X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 603 2 X5R 402
603 402 402 402 402 PLACE IT CLOSE TO L2650 402
PLACE IT CLOSE TO L2600
BUF_CLK PLACE IT CLOSE TO POWER PINS

L2610
FERR-120-OHM-1.5A
5 =PP3V3_S0_CK505 1 2 89 PP3V3_S0_CK505_F
MIN_LINE_WIDTH=0.5mm
0402 MIN_NECK_WIDTH=0.2mm BUF_CLK BUF_CLK BUF_CLK
VOLTAGE=3.3V
C2610 1 1 C2615 1 C2616
10UF 0.1UF 0.1UF
20% 10% 10%
6.3V 16V 16V
X5R 2 2 X5R 2 X5R
603 402 402
PLACE IT CLOSE TO L2610

PLACE IT CLOSE TO POWER PINS

C C

CRITICAL
Y2620

22
14.31818

4
CK505_XTAL_OUT_R 1 2
BUF_CLK

VDD_CPU_IO

VDD_SRC_IO

VDD_SATA_IO

VDD_27

VDD_96_IO

VDD_REF
BUF_CLK

VDD_CORE
C2620 1 5X3.2-SM
NO STUFF
18pF BUF_CLK 1
C2621 1
5% 18pF R2616
50V 5%
CERM 2 50V 10M
402 2 CERM 5% PLACE R2699 NEAR PIN 26
402 1/16W
MF-LF CRITICAL BUF_CLK
2 402
BUF_CLK U2600 R2699
R2615 CK505_XTAL_IN 24 X1
SLG2AP108
QFN REF 26 PCH_CLK14P3M_REFCLK_R 5% 1
33 2 402 PCH_CLK14P3M_REFCLK
B B
85 17 85
OUT
0 1/16W MF-LF
1
5% 2
1/16W 85 CK505_XTAL_OUT 23 X2 OMIT
CPU* 18 FSB_CLK133M_PCH_N OUT 17 84
MF-LF 402
49 IN =SMBUS_CK505_SCL 3 SCL CPU 19 FSB_CLK133M_PCH_P OUT 17 84 PCH BCLK 133MHZ
49 BI =SMBUS_CK505_SDA 2 SDA SRC_2* 11 PCIE_CLK100M_PCH_N OUT 17 84

SRC_2 10 PCIE_CLK100M_PCH_P OUT 17 84

91 65 64 IN PM_PGOOD_PVCORE_CPU 1 CKPWRGD/PD* PCH DMI/PCIe 100MHz
SATA* 15 PCH_CLK100M_SATA_N OUT 17 84
91 CK505_27MHZ_EN 32 27MHZ_EN
SATA 14 PCH_CLK100M_SATA_P OUT 17 84
PCH SATA 100MHZ
27MHZ 29 CK505_CLK27M

BUF_CLK 27MHZ_SS 30 TP_CK505_CLK27M_SS

1
R2600 DOT_96* 7 PCH_CLK96M_DOT_N OUT 17 84
10K

VSS_SATA

VSS_CORE
VSS_REF
VSS_CPU

VSS_SRC
5% DOT_96 6 PCH_CLK96M_DOT_P 17 84

VSS_27

VSS_96
OUT
1/16W PCH USB Clock 96MHz
MF-LF
2 402 THRM
PAD BUF_CLK
1
R2690
20

33
10K
5%
1/16W
MF-LF
2 402

A SYNC_MASTER=K23F SYNC_DATE=11/30/2009 A
PAGE TITLE

CLOCK (CK505)
DRAWING NUMBER SIZE

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IV ALL RIGHTS RESERVED 25 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR3 RESET Support S5
CPU_RESET_L
0
ISOLATE_L
3.3V
MEM_RESET_L
0
LFD CANNOT CONTROL THIS SIGNAL DIRECTLY SINCE IT MUST BE HIGH IN SLEEP AND CPU MEM RAILS ARE NOT POWERED IN SLEEP.
S0 0 3.3V 0

S0 1.5V 3.3V 1.5V

BUFFER ISOLATE_CPU_MEM_L TO 5V S3 0 0 1.5V

S0 1.5V 3.3V 1.5V

5 =PP3V3_S3_MEMRESET 26 5 =PP5V_S3_MEMRESET
S5 0 3.3V 0

D 1
R2750
1
R2751
20K
1
R2752
26 5 =PP5V_S3_MEMRESET D
20K 5% 20K 1
5% 1/16W 5% R2787
1/16W MF-LF 1/16W 20K 1
MF-LF
2 402 MF-LF
5%
R2784
402 402 20K
2 2 1/16W
MF-LF 5%
ISOLATE_CPU_MEM_5V_L 26 28
2 402 1/16W
MF-LF
ISOLATE_CPU_MEM PM_SLP_S3_5V 2 402
3 26
PM_SLP_S3_5V_L 26
6 D 6
D Q2706 D
3
Q2706 5
2N7002DW-X-G Q2770 D
G S SOT-363
ISOLATE_CPU_MEM_L 2 G S
2N7002DW-X-G
PM_SLP_S3_L 2 G S
2N7002DW-X-G Q2770
20 SOT-363 SOT-363 2N7002DW-X-G
91 81 64 63 47 46 36 18 5
4 5 G S SOT-363
1 1
4

CRITICAL

MEM RESET ISOLATION Q2775

FDMC8298
MLP3.3X3.3
5 =PP1V5_S3_MEMRESET

1 2 3
1 5
PPVTT_S0_DDR_FET =PP0V75_S0_MEM_VTT_S0FET

D
R2753 5 5

C 0.0022UF
C2753
10%
1
20K
5%
C

G
50V 1/16W
1 1
CERM 2 MF-LF
402
R2741 R2740
402 2 10 100K
5% 4 5%
91 10 CPU_MEM_RESET_L 2 3 MEM_RESET_L 30 31 91
1/16W 1/16W
MF-LF MF-LF
S D PM_SLP_S3_5V_L
Q2704 2 402 26
2 402
2N7002 G VTT_R
SOT23-HF1
1
3
ISOLATE_CPU_MEM_5V_L D
28 26
Q2780
2N7002
26 PM_SLP_S3_5V 1 G S SOT23-HF1

B B

A SYNC_MASTER=MATT SYNC_DATE=01/06/2010 A
PAGE TITLE

DDR3 RESET
DRAWING NUMBER SIZE

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8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RTC Power Sources Platform Reset Connections
Unbuffered
D2800
BAT54DW-X-G
SOT-363
5 =PP3V3_S5_RTC_D PP3V3_G3_RTC 17 21 23 89
1 6 MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
R2881
Coin-Cell Holder R2800 VOLTAGE=3.3V
PLT_RESET_L 1
33
2 DEBUG_RESET_L
91 19 IN OUT 48 91
1K MAKE_BASE=TRUE
89 PPVBATT_G3_RTC 2 1 89 PPVBATT_G3_RTC_R 4 3 5%
MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm 1/16W
5% MF-LF
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V 1/16W
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V 402 R2883
5 NC NC 2 33
D
MF-LF
NC NC SMC_LRESET_L
D
402 1 2 46 91
OUT
1
J2800 5%
BB10201-C1403-7H 1/16W
MF-LF
2 SM R2882 402
33
511-0054 1 2 ENET_RESET_L OUT 37 91
NOTE: R2800 and D2800 form the double-
5%
fault protection for RTC battery. 1/16W
MF-LF
402

R2892
33
1 2 FW_RESET_L OUT 39 91

5%
1/16W
MF-LF
R2888
PCH RTC Crystal 402

1
33
2 MINI_RESET_L OUT 33 91

5%
1/16W
MF-LF
C2810 402
R2810 12pF R2887
0 1 2
33
85 17 IN PCH_CLK32K_RTCX2 1 2 PCH_CLK32K_RTCX2_R 1 2 PCA9557D_RESET_L OUT 28

5% 5%
1/16W 5% 1/16W
1 CRITICAL 50V
R2811 MF-LF
CERM
MF-LF

3
402 402
10M 402

4
5% Y2810 NC
32.768K

2
1/16W NC
MF-LF SM-2
C2811

1
402 2
12pF
PCH_CLK32K_RTCX1 1 2
R2895
85 17 OUT 33 SDCARD_PLT_RST_L
1 2 OUT 44 91
5% =PP3V3_S0_RSTBUF
27 5 5%
50V
CERM
402
Buffered 1/16W
MF-LF
402

C UNUSED PCH 25MHZ CRYSTAL 1

5 MC74VHC1G08
SOT23-5-HF R2890
C
4
33
PLT_RST_BUF1_L 1 2 PEG_RESET_L
2
U2880 OUT 8 91

5%
85 17 IN PCH_CLK25M_XTALOUT TP_PCH_CLK25M_XTALOUT 1
1/16W
MAKE_BASE=TRUE 3 R2880 MF-LF
402
R2820 C2880 1 100K
0 0.1UF 5%
85 17 OUT PCH_CLK25M_XTALIN 1 2 1/16W MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED
20% MF-LF
5% 10V
2
1/16W CERM 2 402
MF-LF 402
402

27 5 =PP3V3_S0_RSTBUF

5 MC74VHC1G08
1 SOT23-5-HF R2891
4
33
PLT_RST_BUF2_L 1 2 CPU_RESET_L
2
U2890 OUT 10 91

5%
1/16WVTT voltage divider on CPU page
MF-LF
3 402
1
C2890 1 R2893
0.1UF 100K
5%
20%
10V 1/16W
CERM 2 MF-LF

B 402 2 402
B

5 =PP3V3_S0_PCH_PM
Reset Button
1
R2897
4.7K
5%
1/16W
MF-LF
402
2

R2825
PLACEMENT_NOTE=Place close to U1800 33
85 19 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 46 85

5%
XDP 1/16W
MF-LF
402 R2826
R2896 PLACEMENT_NOTE=Place close to U1800 33
0 85 19 IN LPC_CLK33M_LPCPLUS_R 1 2 LPC_CLK33M_LPCPLUS OUT 48 85
91 24 10 IN XDP_DBRESET_L 1 2 PM_SYSRST_L OUT 18 46 91
5%
5% 1/16W
1/16W MF-LF
MF-LF R2827 402
402 PLACEMENT_NOTE=Place close to U1800 33
85 19 IN PCH_CLK33M_PCIOUT 1 2 PCH_CLK33M_PCIIN OUT 17 85

1NOSTUFF
5%
R2898 1/16W
MF-LF
0 402
5%
1/8W
MF-LF
2 805

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE
SILK_PART=SYS RESET
CHIPSET SUPPORT
DRAWING NUMBER SIZE

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IV ALL RIGHTS RESERVED 27 OF 92
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8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
- =PP3V3_S3_VREFMRGN
5 =PP3V3_S3_VREFMRGN
Signal aliases required by this page:
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
VREFMRGN VREFMRGN
BOM options provided by this page:
C2900 1 1
C2901 VREFMRGN
D VREFMRGN - Stuffs VREF Margining Circuitry. 2.2UF
20%
6.3V
0.1UF
20%
10V
CRITICAL C2903
0.1UF
1

A2
B1
VREFMRGN
U2902 CKD D
CERM 2 2 CERM VREFMRGN 20% MAX4253 R2904
402-LF 402 10V V+ UCSP
8 U2900 CERM 2 A1 VREFMRGN_DQ_SODIMMA_BUF 1
332
2 PP0V75_S3_MEM_VREFDQ_A 28 30 89
402
VDD 1%
A4
49 IN =I2C_VREFDACS_SCL 6 SCL
MSOP VOUTA 1 VREFMRGN_SODIMMA_DQ A3
V- 1/16W
MF-LF
B4 402

DAC5574
49 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2 VREFMRGN_SODIMMB_DQ
9 A0 VOUTC 4

Addr=0x98(WR)/0x99(RD) 10 A1 5
VOUTD

GND
3 VREFMRGN
1
R2901
100K
5% CKD
1/16W VREFMRGN
MF-LF
2
402
C2
B1 U2902
MAX4253 R2906
V+ UCSP
C1
332
VREFMRGN_DQ_SODIMMB_BUF 1 2 PP0V75_S3_MEM_VREFDQ_B 28 31 89

C4 1%
C3 1/16W
V- MF-LF
B4 402

CRITICAL
VREFMRGN
VREFMRGN

16
C2902 1
0.1UF VCC VREFMRGN
20% 1
10V
2 U2901 R2902
CERM 100K
402 PCA9557 5%
QFN 1/16W

C 3
A0
(OD) P0
P1
6
7
NC
VREFMRGN_DQ_SODIMMA_EN 2
MF-LF
402 C
Addr=0x30(WR)/0x31(RD) 4
A1 P2 9 VREFMRGN_DQ_SODIMMB_EN
5
A2 P3 10

P4 11

P5 12

49 IN =I2C_PCA9557D_SCL 1
SCL P6 13

49 BI =I2C_PCA9557D_SDA 2
SDA P7 14
NC
RESET* 15 =PP1V5_S3_MEM_A
THRM 30 29 28 5
30 29 28 5 =PP1V5_S3_MEM_A
PAD GND
R2988

8
1
1K
1
R2978
1% 1K
1/16W 1%
MF-LF 1/16W
2 402 MF-LF
2 402

27 IN PCA9557D_RESET_L PP0V75_S3_MEM_VREFCA_A 30 89 PP0V75_S3_MEM_VREFCA_B 31 89

RST* on ’platform reset’ so that system

NOSTUFF NOSTUFF
watchdog will disable margining. 1
R2989 1 C2921
1
R2979 1 C2991
NOTE: Margining will be disabled across all 1K 0.1UF 1K 0.1UF
1% 10% 1% 10%
soft-resets and sleep/wake cycles. 1/16W 16V 1/16W 16V
MF-LF 2 X5R MF-LF 2 X5R
2 402 402 2 402 402

PLACE IT CLOSE TO DIMM CONNECTOR PIN PLACE IT CLOSE TO DIMM CONNECTOR PIN

B Memory Reset Isolation

=PP1V5_S3_MEM_A =PP1V5_S3_MEM_B
B
30 29 28 5 31 29 5

R2970
1
R2975
1

1K 1K
1% 1%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402

PP0V75_S3_MEM_VREFDQ_A 28 30 89 PP0V75_S3_MEM_VREFDQ_B 28 31 89

NOSTUFF
NOSTUFF R2976
1
1 C2951
1
R2971 1K 0.1UF
1K
1 C2950 1%
1/16W 10%
1% 0.1UF MF-LF
16V
2 X5R
LFD 1/16W 10% LFD
MF-LF 2 16V 2 402 402
X5R
83 11 CPU_DIMM_VREF_A 2 3 2 402 402
83 11 CPU_DIMM_VREF_B 2 3 PLACE IT CLOSE TO DIMM CONNECTOR PIN

S D PLACE IT CLOSE TO DIMM CONNECTOR PIN S D

Q2993 Q2991
G 2N7002 G 2N7002
SOT23-HF1 SOT23-HF1
1 1
28 26 ISOLATE_CPU_MEM_5V_L 28 26 ISOLATE_CPU_MEM_5V_L

A MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG GPU Frame Buffer (1.8V, 70% VRef)
SYNC_MASTER=MATT SYNC_DATE=01/06/2010 A
PAGE TITLE

DAC Channel: A B C C D D
DDR3 Vref Margining
DRAWING NUMBER SIZE
PCA9557D Pin: 1 2 3 4 5 6
Apple Inc. 051-8337 D
REVISION
Nominal value 0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A) 1.267V (DAC: 0x8B) R
A.0.0
Margined target: 0.300V - 1.200V (+/- 450mV) 1.998V - 1.002V (+/- 498mV) 1.056V - 1.442V (+/- 180mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
DAC range: 0.000V - 1.501V (0x00 - 0x74) 0.000V - 1.501V (0x00 - 0x74) 0.000V - 3.300V (0x00 - 0xFF) PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VRef current: +3.4mA - -3.4mA (- = sourced) +33uA - -33uA (- = sourced) +6.0mA - -5.0mA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
29 OF 110

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SHEET
DAC step size: 7.69mV / step @ output 8.59mV / step @ output 1.51mV / step @ output III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 28 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DIMM A (FURTHER FROM CPU) CAPS TO COUPLE CPU 1V5_MEM DIMM B (CLOSER TO CPU)

29 15 12 10 5 =PP1V5_CPU_MEM

1 C3016 1 C3017 1 C3018 1 C3019 1 C3010 1 C3025 1 C3026 1 C3027 1 C3028 1 C3029 1 C3020 1 C3021 1 C3022 1 C3023 1 C3014 1 C3030 1 C3031 1 C3032 1 C3033
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
6.3V
2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

D D

EXTRA DECOUPLING CAPS FOR CPU MEM RAIL

29 15 12 10 5 =PP1V5_CPU_MEM

1 C3040 1 C3043 1 C3045 1 C3047 1 C3048 1 C3049 1 C3090 1 C3091 1 C3092 1 C3093 1 C3094
1 C3041 1 C3042 1 C3044 1 C3046 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
1UF 1UF 1UF 1UF 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10% 10% 10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 402 402 402 402 402 402 402 402 402 402 402
402 402 402 402

29 15 12 10 5 =PP1V5_CPU_MEM

1 C30A0 1 C30A1 1 C30A2 1 C30A3 1 C30A4 1 C30A5 1 C30A6 1 C30A7 1 C30A8 1 C30A9 1 C30AA 1 C30AB 1 C30AC 1 C30AD 1 C30AE
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM

C 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
C

DECOUPLING CAPS FOR DIMM ON CHANNEL A - AT CONNECTOR

30 28 5 =PP1V5_S3_MEM_A

B B
1
C3050 1
C3051 1 C3052 1 C3053 1 C3054 1 C3055 1 C3056 1 C3057 1 C3058 1 C3059 1 C3060 1 C3061 1 C3062 1 C3063 1 C3064 1 C3065 1 C3066 1 C3067 1 C3068 1 C3069
10UF 10UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
603 603 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

DECOUPLING CAPS FOR DIMM ON CHANNEL B - AT CONNECTOR

31 28 5 =PP1V5_S3_MEM_B

1
C3070 1
C3071 1 C3072 1 C3073 1 C3074 1 C3075 1 C3076 1 C3077 1 C3078 1 C3079 1 C3080 1 C3081 1 C3082 1 C3083 1 C3084 1 C3085 1 C3086 1 C3087 1 C3088 1 C3089
10UF 10UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2
6.3V
X5R 2
6.3V
X5R 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
603 603 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

MEMORY CAPS
DRAWING NUMBER SIZE

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 29 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP0V75_S3_MEM_VREFDQ_A 1A 2A PP0V75_S3_MEM_VREFDQ_A 1B 2B
89 30 28 VREFDQ VSS_0 89 30 28 VREFDQ VSS_0
3A 4A 3B 4B
VSS_1CRITICAL DQ4 =MEM_A_DQ<4> =MEM_A_DQ<4>
32 30 =MEM_A_DQ<0> 5A
DQ0 J3100 DQ5
6A =MEM_A_DQ<5>
30 32

30 32 32 30 =MEM_A_DQ<0> 5B
VSS_1
DQ0
J3100 DQ4
DQ5
6B =MEM_A_DQ<5>
30 32

30 32
DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD) DIMM2 SPD ADDR=0XA2(WR)/0XA3(RD)
7A F-RT-TH 8A 7B F-RT-TH 8B
32 30 =MEM_A_DQ<1> DQ1 VSS_2 32 30 =MEM_A_DQ<1> DQ1 VSS_2 30 MEM_DIMM0_SA<1> 47 30 5 =PPSPD_S0_MEM_A
9A (1 OF 2) 10A =MEM_A_DQS_N<0> 9B (2 OF 2) 10B =MEM_A_DQS_N<0>
VSS_3 DQS0* VSS_3 DQS0*

DDR3-SODIMM-DUAL
30 32 30 32
CRITICAL MEM_DIMM0_SA<0>

DDR3-SODIMM-DUAL
=MEM_A_DM<0> 11A 12A =MEM_A_DQS_P<0> =MEM_A_DM<0> 11B 12B =MEM_A_DQS_P<0>
30
32 30 DM0 DQS0 30 32 32 30 DM0 DQS0 30 32
1
13A 14A 13B 14B R3142
VSS_4 VSS_5 VSS_4 VSS_5 1 1 10K
32 30 =MEM_A_DQ<2> 15A
DQ2 DQ6
16A =MEM_A_DQ<6> 30 32 32 30 =MEM_A_DQ<2> 15B
DQ2 DQ6
16B =MEM_A_DQ<6> 30 32
R3140 R3141 5%
17A 18A 17B 18B 10K 10K 1/16W
32 30 =MEM_A_DQ<3> DQ3 DQ7 =MEM_A_DQ<7> 30 32 32 30 =MEM_A_DQ<3> DQ3 DQ7 =MEM_A_DQ<7> 30 32 5% 5% MF-LF
19A 20A 19B 20B 1/16W 1/16W 402
2
VSS_6 VSS_7 VSS_6 VSS_7 MF-LF MF-LF
21A 22A 21B 22B 402 402
32 30 =MEM_A_DQ<8> DQ8 DQ12 =MEM_A_DQ<12> 30 32 32 30 =MEM_A_DQ<8> DQ8 DQ12 =MEM_A_DQ<12> 30 32
2 2

23A 24A 23B 24B 30 MEM_DIMM2_SA<0>

=MEM_A_DQ<9> =MEM_A_DQ<13> =MEM_A_DQ<9> =MEM_A_DQ<13>

D
32 30
25A
27A
DQ9
VSS_8
DQ13
VSS_9
26A
28A
30 32 32 30
25B
27B
DQ9
VSS_8
DQ13
VSS_9
26B
28B
30 32

30 MEM_DIMM2_SA<1> D
32 30 =MEM_A_DQS_N<1> DQS1* DM1 =MEM_A_DM<1> 30 32 32 30 =MEM_A_DQS_N<1> DQS1* DM1 =MEM_A_DM<1> 30 32

=MEM_A_DQS_P<1> 29A 30A MEM_RESET_L =MEM_A_DQS_P<1> 29B 30B MEM_RESET_L

32 30 DQS1 RESET* 26 30 31 91 32 30 DQS1 RESET* 26 30 31 91
31A 32A 31B 32B 1
VSS_10 VSS_11 VSS_10 VSS_11 R3143
=MEM_A_DQ<10> 33A 34A =MEM_A_DQ<14> =MEM_A_DQ<10> 33B 34B =MEM_A_DQ<14> 10K
32 30 DQ10 DQ14 30 32 32 30 DQ10 DQ14 30 32

=MEM_A_DQ<11> 35A 36A =MEM_A_DQ<15> =MEM_A_DQ<11> 35B 36B =MEM_A_DQ<15>

5%
32 30 DQ11 DQ15 30 32 32 30 DQ11 DQ15 30 32 1/16W
MF-LF
37A 38A 37B 38B
VSS_12 VSS_13 VSS_12 VSS_13 2
402

=MEM_A_DQ<16> 39A 40A =MEM_A_DQ<20> =MEM_A_DQ<16> 39B 40B =MEM_A_DQ<20>

32 30 DQ16 DQ20 30 32 32 30 DQ16 DQ20 30 32

=MEM_A_DQ<17> 41A 42A =MEM_A_DQ<21> =MEM_A_DQ<17> 41B 42B =MEM_A_DQ<21>

32 30 DQ17 DQ21 30 32 32 30 DQ17 DQ21 30 32
=PPSPD_S0_MEM_A
43A 44A 43B 44B 47 30 5
VSS_14 VSS_15 VSS_14 VSS_15
=MEM_A_DQS_N<2> 45A 46A =MEM_A_DM<2> =MEM_A_DQS_N<2> 45B 46B =MEM_A_DM<2>
32 30 DQS2* DM2 30 32 32 30 DQS2* DM2 30 32

=MEM_A_DQS_P<2> 47A 48A =MEM_A_DQS_P<2> 47B 48B 1

C3140
32 30 DQS2 VSS_16 32 30 DQS2 VSS_16
49A 50A =MEM_A_DQ<22> 49B 50B =MEM_A_DQ<22> 2.2UF
VSS_17 DQ22 30 32 VSS_17 DQ22 30 32
20%
=MEM_A_DQ<18> 51A 52A =MEM_A_DQ<23> =MEM_A_DQ<18> 51B 52B =MEM_A_DQ<23> 6.3V
32 30 DQ18 DQ23 30 32 32 30 DQ18 DQ23 30 32 2 CERM
=MEM_A_DQ<19> 53A 54A =MEM_A_DQ<19> 53B 54B 402-LF
32 30 DQ19 VSS_18 32 30 DQ19 VSS_18
55A 56A =MEM_A_DQ<28> 55B 56B =MEM_A_DQ<28>
VSS_19 DQ28 30 32 VSS_19 DQ28 30 32

=MEM_A_DQ<24> 57A 58A =MEM_A_DQ<29> =MEM_A_DQ<24> 57B 58B =MEM_A_DQ<29>

32 30 DQ24 DQ29 30 32 32 30 DQ24 DQ29 30 32

=MEM_A_DQ<25> 59A 60A =MEM_A_DQ<25> 59B 60B

32 30 DQ25 VSS_20 32 30 DQ25 VSS_20
61A 62A =MEM_A_DQS_N<3> 61B 62B =MEM_A_DQS_N<3>
VSS_21 DQS3* 30 32 VSS_21 DQS3* 30 32

=MEM_A_DM<3> 63A 64A =MEM_A_DQS_P<3> =MEM_A_DM<3> 63B 64B =MEM_A_DQS_P<3>

32 30 DM3 DQS3 30 32 32 30 DM3 DQS3 30 32
PP0V75_S3_MEM_VREFCA_A
65A 66A 65B 66B 89 30 28
VSS_22 VSS_23 VSS_22 VSS_23
=MEM_A_DQ<26> 67A 68A =MEM_A_DQ<30> =MEM_A_DQ<26> 67B 68B =MEM_A_DQ<30>
32 30 DQ26 DQ30 30 32 32 30 DQ26 DQ30 30 32

=MEM_A_DQ<27> 69A 70A =MEM_A_DQ<31> =MEM_A_DQ<27> 69B 70B =MEM_A_DQ<31>

32 30 DQ27 DQ31 30 32 32 30 DQ27 DQ31 30 32
71A 72A 71B 72B
VSS_24 VSS_25 VSS_24 VSS_25
KEY KEY
1
C3135 1
C3136
MEM_A_CKE<0> 73A 74A MEM_A_CKE<1> MEM_A_CKE<2> 73B 74B MEM_A_CKE<3> 2.2UF 0.1UF
83 11 CKE0 CKE1 11 83 83 11 CKE0 CKE1 11 83
20% 20%
=PP1V5_S3_MEM_A 75A 76A =PP1V5_S3_MEM_A =PP1V5_S3_MEM_A 75B 76B =PP1V5_S3_MEM_A 6.3V 10V
30 29 28 5 VDD_0 VDD_1 5 28 29 30 30 29 28 5 VDD_0 VDD_1 5 28 29 30 2 2

C MEM_A_BA<2>
77A
79A
NC_0 A15
78A
80A
MEM_A_A<15>
MEM_A_A<14>
11 30 83

MEM_A_BA<2>
77B
79B
NC_0 A15
78B
80B
MEM_A_A<15>
MEM_A_A<14>
11 30 83
CERM
402-LF
CERM
402
C
83 30 11 BA2 A14 11 30 83 83 30 11 BA2 A14 11 30 83
81A 82A 81B 82B
VDD_2 VDD_3 VDD_2 VDD_3
MEM_A_A<12> 83A 84A MEM_A_A<11> MEM_A_A<12> 83B 84B MEM_A_A<11>
83 30 11 A12/BC* A11 11 30 83 83 30 11 A12/BC* A11 11 30 83

MEM_A_A<9> 85A 86A MEM_A_A<7> MEM_A_A<9> 85B 86B MEM_A_A<7> PP0V75_S3_MEM_VREFDQ_A

83 30 11 A9 A7 11 30 83 83 30 11 A9 A7 11 30 83 89 30 28
87A 88A 87B 88B
VDD_4 VDD_5 VDD_4 VDD_5

DIMM 2
MEM_A_A<8> 89A 90A MEM_A_A<6> MEM_A_A<8> 89B 90B MEM_A_A<6>
DIMM 0

83 30 11 A8 A6 11 30 83 83 30 11 A8 A6 11 30 83

MEM_A_A<5> 91A 92A MEM_A_A<4> MEM_A_A<5> 91B 92B MEM_A_A<4>

83 30 11 A5 A4 11 30 83 83 30 11 A5 A4 11 30 83
1
C3130 1
C3131
93A 94A 93B 94B
VDD_6 VDD_7 VDD_6 VDD_7 2.2UF 0.1UF
MEM_A_A<3> 95A 96A MEM_A_A<2> MEM_A_A<3> 95B 96B MEM_A_A<2> 20% 20%
83 30 11 A3 A2 11 30 83 83 30 11 A3 A2 11 30 83
6.3V 10V
MEM_A_A<1> 97A 98A MEM_A_A<0> MEM_A_A<1> 97B 98B MEM_A_A<0>
2 CERM 2 CERM
83 30 11 A1 A0 11 30 83 83 30 11 A1 A0 11 30 83 402-LF 402
99A 100A 99B 100B
VDD_8 VDD_9 VDD_8 VDD_9
=MEM_A_CLK_P<0> 101A 102A =MEM_A_CLK_P<1> =MEM_A_CLK_P<2> 101B 102B =MEM_A_CLK_P<3>
32 CK0 CK1 32 32 CK0 CK1 32

=MEM_A_CLK_N<0> 103A 104A =MEM_A_CLK_N<1> =MEM_A_CLK_N<2> 103B 104B =MEM_A_CLK_N<3>

32 CK0* CK1* 32 32 CK0* CK1* 32
105A 106A 105B 106B
VDD_10 VDD_11 VDD_10 VDD_11 =PP0V75_S0_MEM_VTT_A
MEM_A_A<10> 107A 108A MEM_A_BA<1> MEM_A_A<10> 107B 108B MEM_A_BA<1>
30 5
83 30 11 A10_AP BA1 11 30 83 83 30 11 A10_AP BA1 11 30 83

MEM_A_BA<0> 109A 110A MEM_A_RAS_L MEM_A_BA<0> 109B 110B MEM_A_RAS_L

83 30 11 BA0 RAS* 11 30 83 83 30 11 BA0 RAS* 11 30 83
111A 112A 111B 112B
VDD_12 VDD_13 VDD_12 VDD_13
MEM_A_WE_L 113A 114A MEM_A_CS_L<0> MEM_A_WE_L 113B 114B MEM_A_CS_L<2> 1
C3150 1
C3151
83 30 11 WE* S0* 11 83 83 30 11 WE* S0* 11 83

MEM_A_CAS_L 115A 116A MEM_A_ODT<0> MEM_A_CAS_L 115B 116B MEM_A_ODT<2> 2.2UF 2.2UF
83 30 11 CAS* ODT0 11 83 83 30 11 CAS* ODT0 11 83
20% 20%
117A 118A 117B 118B 6.3V 6.3V
VDD_14 VDD_15 VDD_14 VDD_15 2 CERM 2 CERM
MEM_A_A<13> 119A 120A MEM_A_ODT<1> MEM_A_A<13> 119B 120B MEM_A_ODT<3> 402-LF 402-LF
83 30 11 A13 ODT1 11 83 83 30 11 A13 ODT1 11 83

MEM_A_CS_L<1> 121A 122A MEM_A_CS_L<3> 121B 122B

83 11 S1* NC_1 83 11 S1* NC_1
123A 124A 123B 124B
VDD_16 VDD_17 VDD_16 VDD_17
125A 126A PP0V75_S3_MEM_VREFCA_A 125B 126B PP0V75_S3_MEM_VREFCA_A
TEST VREFCA 28 30 89 TEST VREFCA 28 30 89
127A 128A 127B 128B
VSS_26 VSS_27 VSS_26 VSS_27
B 32 30

32 30
=MEM_A_DQ<32>
=MEM_A_DQ<33>
129A
131A
DQ32
DQ33
DQ36
DQ37
130A
132A
=MEM_A_DQ<36>
=MEM_A_DQ<37>
30 32

30 32
32 30

32 30
=MEM_A_DQ<32>
=MEM_A_DQ<33>
129B
131B
DQ32
DQ33
DQ36
DQ37
130B
132B
=MEM_A_DQ<36>
=MEM_A_DQ<37>
30 32

30 32
B
133A 134A 133B 134B
VSS_28 VSS_29 VSS_28 VSS_29
=MEM_A_DQS_N<4> 135A 136A =MEM_A_DM<4> =MEM_A_DQS_N<4> 135B 136B =MEM_A_DM<4>
32 30 DQS4* DM4 30 32 32 30 DQS4* DM4 30 32

=MEM_A_DQS_P<4> 137A 138A =MEM_A_DQS_P<4> 137B 138B

32 30 DQS4 VSS_30 32 30 DQS4 VSS_30
139A 140A =MEM_A_DQ<38> 139B 140B =MEM_A_DQ<38>
VSS_31 DQ38 30 32 VSS_31 DQ38 30 32

=MEM_A_DQ<34> 141A 142A =MEM_A_DQ<39> =MEM_A_DQ<34> 141B 142B =MEM_A_DQ<39>

32 30 DQ34 DQ39 30 32 32 30 DQ34 DQ39 30 32

32 30 =MEM_A_DQ<35> 143A
145A
DQ35 VSS_32
144A
146A
32 30 =MEM_A_DQ<35> 143B
145B
DQ35 VSS_32
144B
146B
Page Notes
VSS_33 DQ44 =MEM_A_DQ<44> 30 32 VSS_33 DQ44 =MEM_A_DQ<44> 30 32

=MEM_A_DQ<40> 147A 148A =MEM_A_DQ<45> =MEM_A_DQ<40> 147B 148B =MEM_A_DQ<45>

32 30 DQ40 DQ45 30 32 32 30 DQ40 DQ45 30 32 Power aliases required by this page:
=MEM_A_DQ<41> 149A 150A =MEM_A_DQ<41> 149B 150B
32 30 DQ41 VSS_34 32 30 DQ41 VSS_34 - =PP1V5_S0_MEM_A
151A 152A =MEM_A_DQS_N<5> 151B 152B =MEM_A_DQS_N<5>
VSS_35 DQS5* 30 32 VSS_35 DQS5* 30 32 - =PP1V5_S3_MEM_A
=MEM_A_DM<5> 153A 154A =MEM_A_DQS_P<5> =MEM_A_DM<5> 153B 154B =MEM_A_DQS_P<5>
32 30 DM5 DQS5 30 32 32 30 DM5 DQS5 30 32 - =PP0V75_S0_MEM_VTT_A
155A 156A 155B 156B
VSS_36 VSS_37 VSS_36 VSS_37 - =PPSPD_S0_MEM_A (2.5 - 3.3V)
=MEM_A_DQ<42> 157A 158A =MEM_A_DQ<46> =MEM_A_DQ<42> 157B 158B =MEM_A_DQ<46>
32 30 DQ42 DQ46 30 32 32 30 DQ42 DQ46 30 32
159A 160A 159B 160B Signal aliases required by this page:
32 30 =MEM_A_DQ<43> DQ43 DQ47 =MEM_A_DQ<47> 30 32 32 30 =MEM_A_DQ<43> DQ43 DQ47 =MEM_A_DQ<47> 30 32
161A 162A 161B 162B - =I2C_SODIMMA_SCL - ALL DQ, DQS, DM SIGNALS;
VSS_38 VSS_39 VSS_38 VSS_39 TO FACILITATE BITSWAPS WITH ALIASES
163A 164A 163B 164B - =I2C_SODIMMA_SDA
32 30 =MEM_A_DQ<48> DQ48 DQ52 =MEM_A_DQ<52> 30 32 32 30 =MEM_A_DQ<48> DQ48 DQ52 =MEM_A_DQ<52> 30 32

=MEM_A_DQ<49> 165A 166A =MEM_A_DQ<53> =MEM_A_DQ<49> 165B 166B =MEM_A_DQ<53>

32 30 DQ49 DQ53 30 32 32 30 DQ49 DQ53 30 32 BOM options provided by this page:
167A 168A 167B 168B
VSS_40 VSS_41 VSS_40 VSS_41 (NONE)
=MEM_A_DQS_N<6> 169A 170A =MEM_A_DM<6> =MEM_A_DQS_N<6> 169B 170B =MEM_A_DM<6>
32 30 DQS6* DM6 30 32 32 30 DQS6* DM6 30 32

=MEM_A_DQS_P<6> 171A 172A =MEM_A_DQS_P<6> 171B 172B

32 30 DQS6 VSS_42 32 30 DQS6 VSS_42
173A 174A =MEM_A_DQ<54> 173B 174B =MEM_A_DQ<54>
VSS_43 DQ54 30 32 VSS_43 DQ54 30 32

=MEM_A_DQ<50> 175A 176A =MEM_A_DQ<55> =MEM_A_DQ<50> 175B 176B =MEM_A_DQ<55>

32 30 DQ50 DQ55 30 32 32 30 DQ50 DQ55 30 32

=MEM_A_DQ<51> 177A 178A =MEM_A_DQ<51> 177B 178B

32 30 DQ51 VSS_44 32 30 DQ51 VSS_44
179A 180A =MEM_A_DQ<60> 179B 180B =MEM_A_DQ<60>
VSS_45 DQ60 30 32 VSS_45 DQ60 30 32

A 32 30 =MEM_A_DQ<56>
=MEM_A_DQ<57>
181A
183A
DQ56 DQ61
182A
184A
=MEM_A_DQ<61> 30 32 32 30 =MEM_A_DQ<56>
=MEM_A_DQ<57>
181B
183B
DQ56 DQ61
182B
184B
=MEM_A_DQ<61> 30 32
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
32 30 DQ57 VSS_46 32 30 DQ57 VSS_46 PAGE TITLE
185A 186A 185B 186B
32 30 =MEM_A_DM<7> 187A
VSS_47
DM7
DQS7*
DQS7
188A
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
30 32

30 32 32 30 =MEM_A_DM<7> 187B
VSS_47
DM7
DQS7*
DQS7
188B
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
30 32

30 32
DDR3 SO-DIMMs 0 & 2
189A 190A 189B 190B DRAWING NUMBER SIZE

=MEM_A_DQ<58> 191A
VSS_48 VSS_49
192A =MEM_A_DQ<62> =MEM_A_DQ<58> 191B
VSS_48 VSS_49
192B =MEM_A_DQ<62> Apple Inc. 051-8337 D
32 30 DQ58 DQ62 30 32 32 30 DQ58 DQ62 30 32
REVISION
=MEM_A_DQ<59> 193A 194A =MEM_A_DQ<63> =MEM_A_DQ<59> 193B 194B =MEM_A_DQ<63>
32 30
195A
DQ59 DQ63
196A
30 32 32 30
195B
DQ59 DQ63
196B
30 32 R
A.0.0
VSS_50 VSS_51 VSS_50 VSS_51 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MEM_DIMM0_SA<0> 197A 198A MEM_EVENT_L MEM_DIMM2_SA<0> 197B 198B MEM_EVENT_L
30 SA0 EVENT* 30 31 47 30 SA0 EVENT* 30 31 47
199A 200A 199B 200B THE INFORMATION CONTAINED HEREIN IS THE
47 30 5 =PPSPD_S0_MEM_A VDDSPD SDA =I2C_SODIMMA_SDA 30 49 47 30 5 =PPSPD_S0_MEM_A VDDSPD SDA =I2C_SODIMMA_SDA 30 49 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
201A 202A 201B 202B THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MEM_DIMM0_SA<1> =I2C_SODIMMA_SCL MEM_DIMM2_SA<1> =I2C_SODIMMA_SCL
30

=PP0V75_S0_MEM_VTT_A 203A
SA1 SCL
204A =PP0V75_S0_MEM_VTT_A
30 49 30

=PP0V75_S0_MEM_VTT_A 203B
SA1 SCL
204B =PP0V75_S0_MEM_VTT_A
30 49
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
31 OF 110
30 5 VTT_0 VTT_1 5 30 30 5 VTT_0 VTT_1 5 30

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
409
MTG PIN MTG PIN
410 IV ALL RIGHTS RESERVED 30 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP0V75_S3_MEM_VREFDQ_B 1A 2A PP0V75_S3_MEM_VREFDQ_B 1B 2B
89 31 28 VREFDQ VSS_0 89 31 28 VREFDQ VSS_0
3A 4A 3B 4B
VSS_1CRITICAL DQ4 =MEM_B_DQ<4> VSS_1CRITICAL DQ4 =MEM_B_DQ<4>
32 31 =MEM_B_DQ<0> 5A
DQ0 J3200 DQ5
6A =MEM_B_DQ<5>
31 32

31 32 32 31 =MEM_B_DQ<0> 5B
DQ0
J3200 DQ5
6B =MEM_B_DQ<5>
31 32

31 32
7A F-RT-TH 8A 7B F-RT-TH 8B
32 31 =MEM_B_DQ<1> DQ1 VSS_2 32 31 =MEM_B_DQ<1> DQ1 VSS_2
9A (1 OF 2) 10A =MEM_B_DQS_N<0> 9B (2 OF 2) 10B =MEM_B_DQS_N<0>
VSS_3 DQS0* VSS_3 DQS0* DIMM1 SPD ADDR=0XA4(WR)/0XA5(RD) DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)

DDR3-SODIMM-DUAL
31 32 31 32

DDR3-SODIMM-DUAL
=MEM_B_DM<0> 11A 12A =MEM_B_DQS_P<0> =MEM_B_DM<0> 11B 12B =MEM_B_DQS_P<0>
32 31 DM0 DQS0 31 32 32 31 DM0 DQS0 31 32
=PPSPD_S0_MEM_B =PPSPD_S0_MEM_B
13A 14A 13B 14B 31 5 31 5
VSS_4 VSS_5 VSS_4 VSS_5
=MEM_B_DQ<2> 15A 16A =MEM_B_DQ<6> =MEM_B_DQ<2> 15B 16B =MEM_B_DQ<6>
32 31 DQ2 DQ6 31 32 32 31 DQ2 DQ6 31 32

=MEM_B_DQ<3> 17A 18A =MEM_B_DQ<7> =MEM_B_DQ<3> 17B 18B =MEM_B_DQ<7> 1 1 1

32 31 DQ3 DQ7 31 32 32 31 DQ3 DQ7 31 32 R3240 R3242 R3243
19A 20A 19B 20B 10K 10K 10K
VSS_6 VSS_7 VSS_6 VSS_7
21A 22A 21B 22B 5% 5% 5%
32 31 =MEM_B_DQ<8> DQ8 DQ12 =MEM_B_DQ<12> 31 32 32 31 =MEM_B_DQ<8> DQ8 DQ12 =MEM_B_DQ<12> 31 32 1/16W 1/16W 1/16W

=MEM_B_DQ<9> 23A 24A =MEM_B_DQ<13> =MEM_B_DQ<9> 23B 24B =MEM_B_DQ<13>

MF-LF MF-LF MF-LF

D
32 31
25A
27A
DQ9
VSS_8
DQ13
VSS_9
26A
28A
31 32 32 31
25B
27B
DQ9
VSS_8
DQ13
VSS_9
26B
28B
31 32
2
402
2
402
2
402

D
32 31 =MEM_B_DQS_N<1> DQS1* DM1 =MEM_B_DM<1> 31 32 32 31 =MEM_B_DQS_N<1> DQS1* DM1 =MEM_B_DM<1> 31 32 31 MEM_DIMM3_SA<1>
29A 30A 29B 30B 31 MEM_DIMM1_SA<1>
32 31 =MEM_B_DQS_P<1> DQS1 RESET* MEM_RESET_L 26 30 31 91 32 31 =MEM_B_DQS_P<1> DQS1 RESET* MEM_RESET_L 26 30 31 91
31A 32A 31B 32B 31 MEM_DIMM1_SA<0> 31 MEM_DIMM3_SA<0>
VSS_10 VSS_11 VSS_10 VSS_11
=MEM_B_DQ<10> 33A 34A =MEM_B_DQ<14> =MEM_B_DQ<10> 33B 34B =MEM_B_DQ<14>
32 31 DQ10 DQ14 31 32 32 31 DQ10 DQ14 31 32

=MEM_B_DQ<11> 35A 36A =MEM_B_DQ<15> =MEM_B_DQ<11> 35B 36B =MEM_B_DQ<15> 1

32 31 DQ11 DQ15 31 32 32 31 DQ11 DQ15 31 32 R3241
37A 38A 37B 38B 10K
VSS_12 VSS_13 VSS_12 VSS_13
39A 40A 39B 40B 5%
32 31 =MEM_B_DQ<16> DQ16 DQ20 =MEM_B_DQ<20> 31 32 32 31 =MEM_B_DQ<16> DQ16 DQ20 =MEM_B_DQ<20> 31 32 1/16W
41A 42A 41B 42B MF-LF
32 31 =MEM_B_DQ<17> DQ17 DQ21 =MEM_B_DQ<21> 31 32 32 31 =MEM_B_DQ<17> DQ17 DQ21 =MEM_B_DQ<21> 31 32
2
402
43A 44A 43B 44B
VSS_14 VSS_15 VSS_14 VSS_15
=MEM_B_DQS_N<2> 45A 46A =MEM_B_DM<2> =MEM_B_DQS_N<2> 45B 46B =MEM_B_DM<2>
32 31 DQS2* DM2 31 32 32 31 DQS2* DM2 31 32

=MEM_B_DQS_P<2> 47A 48A =MEM_B_DQS_P<2> 47B 48B

32 31 DQS2 VSS_16 32 31 DQS2 VSS_16
49A 50A =MEM_B_DQ<22> 49B 50B =MEM_B_DQ<22> =PPSPD_S0_MEM_B
VSS_17 DQ22 31 32 VSS_17 DQ22 31 32 31 5

=MEM_B_DQ<18> 51A 52A =MEM_B_DQ<23> =MEM_B_DQ<18> 51B 52B =MEM_B_DQ<23>

32 31 DQ18 DQ23 31 32 32 31 DQ18 DQ23 31 32

=MEM_B_DQ<19> 53A 54A =MEM_B_DQ<19> 53B 54B

32 31 DQ19 VSS_18 32 31 DQ19 VSS_18
55A 56A =MEM_B_DQ<28> 55B 56B =MEM_B_DQ<28> 1
C3240
VSS_19 DQ28 31 32 VSS_19 DQ28 31 32

=MEM_B_DQ<24> 57A 58A =MEM_B_DQ<29> =MEM_B_DQ<24> 57B 58B =MEM_B_DQ<29> 2.2UF

32 31 DQ24 DQ29 31 32 32 31 DQ24 DQ29 31 32
20%
=MEM_B_DQ<25> 59A 60A =MEM_B_DQ<25> 59B 60B 6.3V
32 31 DQ25 VSS_20 32 31 DQ25 VSS_20 2 CERM
61A 62A =MEM_B_DQS_N<3> 61B 62B =MEM_B_DQS_N<3> 402-LF
VSS_21 DQS3* 31 32 VSS_21 DQS3* 31 32

=MEM_B_DM<3> 63A 64A =MEM_B_DQS_P<3> =MEM_B_DM<3> 63B 64B =MEM_B_DQS_P<3>

32 31 DM3 DQS3 31 32 32 31 DM3 DQS3 31 32
65A 66A 65B 66B
VSS_22 VSS_23 VSS_22 VSS_23
=MEM_B_DQ<26> 67A 68A =MEM_B_DQ<30> =MEM_B_DQ<26> 67B 68B =MEM_B_DQ<30>
32 31 DQ26 DQ30 31 32 32 31 DQ26 DQ30 31 32

=MEM_B_DQ<27> 69A 70A =MEM_B_DQ<31> =MEM_B_DQ<27> 69B 70B =MEM_B_DQ<31>

32 31 DQ27 DQ31 31 32 32 31 DQ27 DQ31 31 32
71A 72A 71B 72B
VSS_24 VSS_25 VSS_24 VSS_25
73A KEY 74A 73B KEY 74B
83 11 MEM_B_CKE<0> CKE0 CKE1 MEM_B_CKE<1> 11 83 83 11 MEM_B_CKE<2> CKE0 CKE1 MEM_B_CKE<3> 11 83 89 31 28 PP0V75_S3_MEM_VREFCA_B
=PP1V5_S3_MEM_B 75A 76A =PP1V5_S3_MEM_B =PP1V5_S3_MEM_B 75B 76B =PP1V5_S3_MEM_B
31 29 28 5 VDD_0 VDD_1 5 28 29 31 31 29 28 5 VDD_0 VDD_1 5 28 29 31

C MEM_B_BA<2>
77A
79A
NC_0 A15
78A
80A
MEM_B_A<15>
MEM_B_A<14>
11 31 83

MEM_B_BA<2>
77B
79B
NC_0 A15
78B
80B
MEM_B_A<15>
MEM_B_A<14>
11 31 83 C
83 31 11 BA2 A14 11 31 83 83 31 11 BA2 A14 11 31 83
81A 82A 81B 82B 1
C3235 1
C3236
VDD_2 VDD_3 VDD_2 VDD_3
MEM_B_A<12> 83A 84A MEM_B_A<11> MEM_B_A<12> 83B 84B MEM_B_A<11> 2.2UF 0.1UF
DIMM 1

83 31 11 A12/BC* A11 11 31 83 83 31 11 A12/BC* A11 11 31 83

DIMM 3
20% 20%
MEM_B_A<9> 85A 86A MEM_B_A<7> MEM_B_A<9> 85B 86B MEM_B_A<7> 6.3V 10V
83 31 11 A9 A7 11 31 83 83 31 11 A9 A7 11 31 83 2 CERM 2 CERM
87A 88A 87B 88B 402-LF 402
VDD_4 VDD_5 VDD_4 VDD_5
MEM_B_A<8> 89A 90A MEM_B_A<6> MEM_B_A<8> 89B 90B MEM_B_A<6>
83 31 11 A8 A6 11 31 83 83 31 11 A8 A6 11 31 83

MEM_B_A<5> 91A 92A MEM_B_A<4> MEM_B_A<5> 91B 92B MEM_B_A<4>

83 31 11 A5 A4 11 31 83 83 31 11 A5 A4 11 31 83
93A 94A 93B 94B
VDD_6 VDD_7 VDD_6 VDD_7
MEM_B_A<3> 95A 96A MEM_B_A<2> MEM_B_A<3> 95B 96B MEM_B_A<2> PP0V75_S3_MEM_VREFDQ_B
83 31 11 A3 A2 11 31 83 83 31 11 A3 A2 11 31 83 89 31 28

MEM_B_A<1> 97A 98A MEM_B_A<0> MEM_B_A<1> 97B 98B MEM_B_A<0>

83 31 11 A1 A0 11 31 83 83 31 11 A1 A0 11 31 83
99A 100A 99B 100B
VDD_8 VDD_9 VDD_8 VDD_9
=MEM_B_CLK_P<0> 101A 102A =MEM_B_CLK_P<1> =MEM_B_CLK_P<2> 101B 102B =MEM_B_CLK_P<3>
32 CK0 CK1 32 32 CK0 CK1 32
1
C3230 1
C3231
=MEM_B_CLK_N<0> 103A 104A =MEM_B_CLK_N<1> =MEM_B_CLK_N<2> 103B 104B =MEM_B_CLK_N<3>
32 CK0* CK1* 32 32 CK0* CK1* 32
2.2UF 0.1UF
105A 106A 105B 106B 20% 20%
VDD_10 VDD_11 VDD_10 VDD_11 6.3V 10V
MEM_B_A<10> 107A 108A MEM_B_BA<1> MEM_B_A<10> 107B 108B MEM_B_BA<1>
2 CERM 2 CERM
83 31 11 A10_AP BA1 11 31 83 83 31 11 A10_AP BA1 11 31 83 402-LF 402
MEM_B_BA<0> 109A 110A MEM_B_RAS_L MEM_B_BA<0> 109B 110B MEM_B_RAS_L
83 31 11 BA0 RAS* 11 31 83 83 31 11 BA0 RAS* 11 31 83
111A 112A 111B 112B
VDD_12 VDD_13 VDD_12 VDD_13
MEM_B_WE_L 113A 114A MEM_B_CS_L<0> MEM_B_WE_L 113B 114B MEM_B_CS_L<2>
83 31 11 WE* S0* 11 83 83 31 11 WE* S0* 11 83

MEM_B_CAS_L 115A 116A MEM_B_ODT<0> MEM_B_CAS_L 115B 116B MEM_B_ODT<2>

83 31 11 CAS* ODT0 11 83 83 31 11 CAS* ODT0 11 83
=PP0V75_S0_MEM_VTT_B
117A 118A 117B 118B 31 5
VDD_14 VDD_15 VDD_14 VDD_15
MEM_B_A<13> 119A 120A MEM_B_ODT<1> MEM_B_A<13> 119B 120B MEM_B_ODT<3>
83 31 11 A13 ODT1 11 83 83 31 11 A13 ODT1 11 83

MEM_B_CS_L<1> 121A 122A MEM_B_CS_L<3> 121B 122B

83 11 S1* NC_1 83 11 S1* NC_1
123A 124A 123B 124B 1
C3250 1
C3251
VDD_16 VDD_17 VDD_16 VDD_17
125A 126A PP0V75_S3_MEM_VREFCA_B 125B 126B PP0V75_S3_MEM_VREFCA_B 2.2UF 2.2UF
TEST VREFCA 28 31 89 TEST VREFCA 28 31 89
20% 20%
127A 128A 127B 128B 6.3V 6.3V
VSS_26 VSS_27 VSS_26 VSS_27 2 CERM 2 CERM

B 32 31

32 31
=MEM_B_DQ<32>
=MEM_B_DQ<33>
129A
131A
DQ32
DQ33
DQ36
DQ37
130A
132A
=MEM_B_DQ<36>
=MEM_B_DQ<37>
31 32

31 32
32 31

32 31
=MEM_B_DQ<32>
=MEM_B_DQ<33>
129B
131B
DQ32
DQ33
DQ36
DQ37
130B
132B
=MEM_B_DQ<36>
=MEM_B_DQ<37>
31 32

31 32
402-LF 402-LF
B
133A 134A 133B 134B
VSS_28 VSS_29 VSS_28 VSS_29
=MEM_B_DQS_N<4> 135A 136A =MEM_B_DM<4> =MEM_B_DQS_N<4> 135B 136B =MEM_B_DM<4>
32 31 DQS4* DM4 31 32 32 31 DQS4* DM4 31 32

=MEM_B_DQS_P<4> 137A 138A =MEM_B_DQS_P<4> 137B 138B

32 31 DQS4 VSS_30 32 31 DQS4 VSS_30
139A 140A =MEM_B_DQ<38> 139B 140B =MEM_B_DQ<38>
VSS_31 DQ38 31 32 VSS_31 DQ38 31 32

=MEM_B_DQ<34> 141A 142A =MEM_B_DQ<39> =MEM_B_DQ<34> 141B 142B =MEM_B_DQ<39>

32 31 DQ34 DQ39 31 32 32 31 DQ34 DQ39 31 32

32 31 =MEM_B_DQ<35> 143A
145A
DQ35 VSS_32
144A
146A
32 31 =MEM_B_DQ<35> 143B
145B
DQ35 VSS_32
144B
146B
Page Notes
VSS_33 DQ44 =MEM_B_DQ<44> 31 32 VSS_33 DQ44 =MEM_B_DQ<44> 31 32

=MEM_B_DQ<40> 147A 148A =MEM_B_DQ<45> =MEM_B_DQ<40> 147B 148B =MEM_B_DQ<45>

32 31 DQ40 DQ45 31 32 32 31 DQ40 DQ45 31 32 Power aliases required by this page:
=MEM_B_DQ<41> 149A 150A =MEM_B_DQ<41> 149B 150B
32 31 DQ41 VSS_34 32 31 DQ41 VSS_34 - =PP1V5_S0_MEM_B
151A 152A =MEM_B_DQS_N<5> 151B 152B =MEM_B_DQS_N<5>
VSS_35 DQS5* 31 32 VSS_35 DQS5* 31 32 - =PP1V5_S3_MEM_B
=MEM_B_DM<5> 153A 154A =MEM_B_DQS_P<5> =MEM_B_DM<5> 153B 154B =MEM_B_DQS_P<5>
32 31 DM5 DQS5 31 32 32 31 DM5 DQS5 31 32 - =PP0V75_S0_MEM_VTT_B
155A 156A 155B 156B
VSS_36 VSS_37 VSS_36 VSS_37 - =PPSPD_S0_MEM_B (2.5 - 3.3V)
=MEM_B_DQ<42> 157A 158A =MEM_B_DQ<46> =MEM_B_DQ<42> 157B 158B =MEM_B_DQ<46>
32 31 DQ42 DQ46 31 32 32 31 DQ42 DQ46 31 32
159A 160A 159B 160B Signal aliases required by this page:
32 31 =MEM_B_DQ<43> DQ43 DQ47 =MEM_B_DQ<47> 31 32 32 31 =MEM_B_DQ<43> DQ43 DQ47 =MEM_B_DQ<47> 31 32
161A 162A 161B 162B - =I2C_SODIMMB_SCL - ALL DQ, DQS, DM SIGNALS;
VSS_38 VSS_39 VSS_38 VSS_39 TO FACILITATE BITSWAPS WITH ALIASES
163A 164A 163B 164B - =I2C_SODIMMB_SDA
32 31 =MEM_B_DQ<48> DQ48 DQ52 =MEM_B_DQ<52> 31 32 32 31 =MEM_B_DQ<48> DQ48 DQ52 =MEM_B_DQ<52> 31 32

=MEM_B_DQ<49> 165A 166A =MEM_B_DQ<53> =MEM_B_DQ<49> 165B 166B =MEM_B_DQ<53>

32 31 DQ49 DQ53 31 32 32 31 DQ49 DQ53 31 32 BOM options provided by this page:
167A 168A 167B 168B
VSS_40 VSS_41 VSS_40 VSS_41 (NONE)
=MEM_B_DQS_N<6> 169A 170A =MEM_B_DM<6> =MEM_B_DQS_N<6> 169B 170B =MEM_B_DM<6>
32 31 DQS6* DM6 31 32 32 31 DQS6* DM6 31 32

=MEM_B_DQS_P<6> 171A 172A =MEM_B_DQS_P<6> 171B 172B

32 31 DQS6 VSS_42 32 31 DQS6 VSS_42
173A 174A =MEM_B_DQ<54> 173B 174B =MEM_B_DQ<54>
VSS_43 DQ54 31 32 VSS_43 DQ54 31 32

=MEM_B_DQ<50> 175A 176A =MEM_B_DQ<55> =MEM_B_DQ<50> 175B 176B =MEM_B_DQ<55>

32 31 DQ50 DQ55 31 32 32 31 DQ50 DQ55 31 32

=MEM_B_DQ<51> 177A 178A =MEM_B_DQ<51> 177B 178B

32 31 DQ51 VSS_44 32 31 DQ51 VSS_44
179A 180A =MEM_B_DQ<60> 179B 180B =MEM_B_DQ<60>
VSS_45 DQ60 31 32 VSS_45 DQ60 31 32

A 32 31 =MEM_B_DQ<56>
=MEM_B_DQ<57>
181A
183A
DQ56 DQ61
182A
184A
=MEM_B_DQ<61> 31 32 32 31 =MEM_B_DQ<56>
=MEM_B_DQ<57>
181B
183B
DQ56 DQ61
182B
184B
=MEM_B_DQ<61> 31 32
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
32 31 DQ57 VSS_46 32 31 DQ57 VSS_46 PAGE TITLE
185A 186A 185B 186B
32 31 =MEM_B_DM<7> 187A
VSS_47
DM7
DQS7*
DQS7
188A
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
31 32

31 32 32 31 =MEM_B_DM<7> 187B
VSS_47
DM7
DQS7*
DQS7
188B
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
31 32

31 32
DDR3 SO-DIMM CONNECTOR B
189A 190A 189B 190B DRAWING NUMBER SIZE

=MEM_B_DQ<58> 191A
VSS_48 VSS_49
192A =MEM_B_DQ<62> =MEM_B_DQ<58> 191B
VSS_48 VSS_49
192B =MEM_B_DQ<62> Apple Inc. 051-8337 D
32 31 DQ58 DQ62 31 32 32 31 DQ58 DQ62 31 32
REVISION
=MEM_B_DQ<59> 193A 194A =MEM_B_DQ<63> =MEM_B_DQ<59> 193B 194B =MEM_B_DQ<63>
32 31
195A
DQ59 DQ63
196A
31 32 32 31
195B
DQ59 DQ63
196B
31 32 R
A.0.0
VSS_50 VSS_51 VSS_50 VSS_51 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MEM_DIMM1_SA<0> 197A 198A MEM_EVENT_L MEM_DIMM3_SA<0> 197B 198B MEM_EVENT_L
31 SA0 EVENT* 30 31 47 31 SA0 EVENT* 30 31 47
199A 200A 199B 200B THE INFORMATION CONTAINED HEREIN IS THE
31 5 =PPSPD_S0_MEM_B VDDSPD SDA =I2C_SODIMMB_SDA 31 49 31 5 =PPSPD_S0_MEM_B VDDSPD SDA =I2C_SODIMMB_SDA 31 49 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
201A 202A 201B 202B THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MEM_DIMM1_SA<1> =I2C_SODIMMB_SCL MEM_DIMM3_SA<1> =I2C_SODIMMB_SCL
31

=PP0V75_S0_MEM_VTT_B 203A
SA1 SCL
204A =PP0V75_S0_MEM_VTT_B
31 49 31

=PP0V75_S0_MEM_VTT_B 203B
SA1 SCL
204B =PP0V75_S0_MEM_VTT_B
31 49
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
32 OF 110
31 5 VTT_0 VTT_1 5 31 31 5 VTT_0 VTT_1 5 31

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
409
MTG PIN MTG PIN
410 IV ALL RIGHTS RESERVED 31 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU CHANNEL A DQS 0 -> DIMM A DQS 7 CPU CHANNEL B DQS 0 -> DIMM B DQS 7
83 11 MEM_A_DQS_N<0> =MEM_A_DQS_N<7> 30 83 11 MEM_B_DQS_N<0> =MEM_B_DQS_N<7> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQS_P<0> =MEM_A_DQS_P<7> 30 83 11 MEM_B_DQS_P<0> =MEM_B_DQS_P<7> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DM<0> =MEM_A_DM<7> 30 83 11 MEM_B_DM<0> =MEM_B_DM<7> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<7> =MEM_A_DQ<60> 30 83 11 MEM_B_DQ<7> =MEM_B_DQ<61> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<6> =MEM_A_DQ<56> 30 83 11 MEM_B_DQ<6> =MEM_B_DQ<60> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<5> =MEM_A_DQ<58> 30 83 11 MEM_B_DQ<5> =MEM_B_DQ<62> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<4> =MEM_A_DQ<59> 30 83 11 MEM_B_DQ<4> =MEM_B_DQ<63> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<3> =MEM_A_DQ<57> 30 83 11 MEM_B_DQ<3> =MEM_B_DQ<56> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<2> =MEM_A_DQ<61> 30 83 11 MEM_B_DQ<2> =MEM_B_DQ<57> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
D 83 11

83 11
MEM_A_DQ<1>
MEM_A_DQ<0>
MAKE_BASE=TRUE
=MEM_A_DQ<62>
=MEM_A_DQ<63>
30

30
83 11

83 11
MEM_B_DQ<1>
MEM_B_DQ<0>
MAKE_BASE=TRUE
=MEM_B_DQ<58>
=MEM_B_DQ<59>
31

31
D
MAKE_BASE=TRUE MAKE_BASE=TRUE
CPU CHANNEL A DQS 1 -> DIMM A DQS 6 CPU CHANNEL B DQS 1 -> DIMM B DQS 6
83 11 MEM_A_DQS_N<1> =MEM_A_DQS_N<6> 30 83 11 MEM_B_DQS_N<1> =MEM_B_DQS_N<6> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQS_P<1> =MEM_A_DQS_P<6> 30 83 11 MEM_B_DQS_P<1> =MEM_B_DQS_P<6> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DM<1> =MEM_A_DM<6> 30 83 11 MEM_B_DM<1> =MEM_B_DM<6> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<15> =MEM_A_DQ<49> 30 83 11 MEM_B_DQ<15> =MEM_B_DQ<51> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<14> =MEM_A_DQ<52> 30 83 11 MEM_B_DQ<14> =MEM_B_DQ<54> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<13> =MEM_A_DQ<51> 30 83 11 MEM_B_DQ<13> =MEM_B_DQ<53> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<12> =MEM_A_DQ<50> 30 83 11 MEM_B_DQ<12> =MEM_B_DQ<52> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<11> =MEM_A_DQ<48> 30 83 11 MEM_B_DQ<11> =MEM_B_DQ<48> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<10> =MEM_A_DQ<53> 30 83 11 MEM_B_DQ<10> =MEM_B_DQ<49> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<9> =MEM_A_DQ<55> 30 83 11 MEM_B_DQ<9> =MEM_B_DQ<50> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<8> =MEM_A_DQ<54> 30 83 11 MEM_B_DQ<8> =MEM_B_DQ<55> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
CPU CHANNEL A DQS 2 -> DIMM A DQS 5 CPU CHANNEL B DQS 2 -> DIMM B DQS 5
83 11 MEM_A_DQS_N<2> =MEM_A_DQS_N<5> 30 83 11 MEM_B_DQS_N<2> =MEM_B_DQS_N<5> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQS_P<2> =MEM_A_DQS_P<5> 30 83 11 MEM_B_DQS_P<2> =MEM_B_DQS_P<5> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DM<2> =MEM_A_DM<5> 30 83 11 MEM_B_DM<2> =MEM_B_DM<5> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<23> =MEM_A_DQ<40> 30 83 11 MEM_B_DQ<23> =MEM_B_DQ<45> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<22> =MEM_A_DQ<45> 30 83 11 MEM_B_DQ<22> =MEM_B_DQ<40> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<21> =MEM_A_DQ<43> 30 83 11 MEM_B_DQ<21> =MEM_B_DQ<42> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<20> =MEM_A_DQ<42> 30 83 11 MEM_B_DQ<20> =MEM_B_DQ<47> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<19> =MEM_A_DQ<41> 30 83 11 MEM_B_DQ<19> =MEM_B_DQ<44> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<18> =MEM_A_DQ<44> 30 83 11 MEM_B_DQ<18> =MEM_B_DQ<41> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<17> =MEM_A_DQ<46> 30 83 11 MEM_B_DQ<17> =MEM_B_DQ<46> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<16> =MEM_A_DQ<47> 30 83 11 MEM_B_DQ<16> =MEM_B_DQ<43> 31

C MAKE_BASE=TRUE
CPU CHANNEL A DQS 3 -> DIMM A DQS 4
MAKE_BASE=TRUE
CPU CHANNEL B DQS 3 -> DIMM B DQS 4 C
83 11 MEM_A_DQS_N<3> =MEM_A_DQS_N<4> 30 83 11 MEM_B_DQS_N<3> =MEM_B_DQS_N<4> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQS_P<3> =MEM_A_DQS_P<4> 30 83 11 MEM_B_DQS_P<3> =MEM_B_DQS_P<4> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DM<3> =MEM_A_DM<4> 30 83 11 MEM_B_DM<3> =MEM_B_DM<4> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<31> =MEM_A_DQ<37> 30 83 11 MEM_B_DQ<31> =MEM_B_DQ<32> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<30> =MEM_A_DQ<33> 30 83 11 MEM_B_DQ<30> =MEM_B_DQ<39> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<29> =MEM_A_DQ<35> 30 83 11 MEM_B_DQ<29> =MEM_B_DQ<37> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<28> =MEM_A_DQ<34> 30 83 11 MEM_B_DQ<28> =MEM_B_DQ<38> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<27> =MEM_A_DQ<36> 30 83 11 MEM_B_DQ<27> =MEM_B_DQ<35> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<26> =MEM_A_DQ<32> 30 83 11 MEM_B_DQ<26> =MEM_B_DQ<34> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<25> =MEM_A_DQ<38> 30 83 11 MEM_B_DQ<25> =MEM_B_DQ<36> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<24> =MEM_A_DQ<39> 30 83 11 MEM_B_DQ<24> =MEM_B_DQ<33> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
CPU CHANNEL A DQS 4 -> DIMM A DQS 3 CPU CHANNEL B DQS 4 -> DIMM B DQS 3
83 11 MEM_A_DQS_N<4> =MEM_A_DQS_N<3> 30 83 11 MEM_B_DQS_N<4> =MEM_B_DQS_N<3> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQS_P<4> =MEM_A_DQS_P<3> 30 83 11 MEM_B_DQS_P<4> =MEM_B_DQS_P<3> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DM<4> =MEM_A_DM<3> 30 83 11 MEM_B_DM<4> =MEM_B_DM<3> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<39> =MEM_A_DQ<25> 30 83 11 MEM_B_DQ<39> =MEM_B_DQ<28> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<38> =MEM_A_DQ<29> 30 83 11 MEM_B_DQ<38> =MEM_B_DQ<24> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<37> =MEM_A_DQ<27> 30 83 11 MEM_B_DQ<37> =MEM_B_DQ<31> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<36> =MEM_A_DQ<31> 30 83 11 MEM_B_DQ<36> =MEM_B_DQ<30> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<35> =MEM_A_DQ<28> 30 83 11 MEM_B_DQ<35> =MEM_B_DQ<29> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<34> =MEM_A_DQ<24> 30 83 11 MEM_B_DQ<34> =MEM_B_DQ<25> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<33> =MEM_A_DQ<26> 30 83 11 MEM_B_DQ<33> =MEM_B_DQ<27> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<32> =MEM_A_DQ<30> 30 83 11 MEM_B_DQ<32> =MEM_B_DQ<26> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
CPU CHANNEL A DQS 5 -> DIMM A DQS 2 CPU CHANNEL B DQS 5 -> DIMM B DQS 2
B 83 11 MEM_A_DQS_N<5>
MAKE_BASE=TRUE
=MEM_A_DQS_N<2> 30 83 11 MEM_B_DQS_N<5>
MAKE_BASE=TRUE
=MEM_B_DQS_N<2> 31 B
83 11 MEM_A_DQS_P<5> =MEM_A_DQS_P<2> 30 83 11 MEM_B_DQS_P<5> =MEM_B_DQS_P<2> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DM<5> =MEM_A_DM<2> 30 83 11 MEM_B_DM<5> =MEM_B_DM<2> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<47> =MEM_A_DQ<17> 30 83 11 MEM_B_DQ<47> =MEM_B_DQ<18> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<46> =MEM_A_DQ<16> 30 83 11 MEM_B_DQ<46> =MEM_B_DQ<20> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<45> =MEM_A_DQ<22> 30 83 11 MEM_B_DQ<45> =MEM_B_DQ<23> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<44> =MEM_A_DQ<23> 30 83 11 MEM_B_DQ<44> =MEM_B_DQ<22> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<43> =MEM_A_DQ<21> 30 83 11 MEM_B_DQ<43> =MEM_B_DQ<19> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<42> =MEM_A_DQ<20> 30 83 11 MEM_B_DQ<42> =MEM_B_DQ<21> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<41> =MEM_A_DQ<18> 30 83 11 MEM_B_DQ<41> =MEM_B_DQ<17> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<40> =MEM_A_DQ<19> 30 83 11 MEM_B_DQ<40> =MEM_B_DQ<16> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
CPU CHANNEL A DQS 6 -> DIMM A DQS 1 CPU CHANNEL B DQS 6 -> DIMM B DQS 1
83 11 MEM_A_DQS_N<6> =MEM_A_DQS_N<1> 30 83 11 MEM_B_DQS_N<6> =MEM_B_DQS_N<1> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQS_P<6> =MEM_A_DQS_P<1> 30 83 11 MEM_B_DQS_P<6> =MEM_B_DQS_P<1> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DM<6> =MEM_A_DM<1> 30 83 11 MEM_B_DM<6> =MEM_B_DM<1> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<55> =MEM_A_DQ<12> 30 83 11 MEM_B_DQ<55> =MEM_B_DQ<8> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<54> =MEM_A_DQ<13> 30 83 11 MEM_B_DQ<54> =MEM_B_DQ<14> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
MEM_A_DQ<53> =MEM_A_DQ<10> MEM_B_DQ<53> =MEM_B_DQ<10>
83 11

83 11 MEM_A_DQ<52>
MAKE_BASE=TRUE
=MEM_A_DQ<15>
30

30
83 11

83 11 MEM_B_DQ<52>
MAKE_BASE=TRUE
=MEM_B_DQ<11>
31

31
MEMORY CLOCK ALIASING
MAKE_BASE=TRUE MAKE_BASE=TRUE 83 11 MEM_A_CLK_P<0> =MEM_A_CLK_P<0> 30
83 11 MEM_A_DQ<51> =MEM_A_DQ<8> 30 83 11 MEM_B_DQ<51> =MEM_B_DQ<9> 31 MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE 83 11 MEM_A_CLK_N<0> =MEM_A_CLK_N<0> 30
83 11 MEM_A_DQ<50> =MEM_A_DQ<9> 30 83 11 MEM_B_DQ<50> =MEM_B_DQ<15> 31 MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE 83 11 MEM_A_CLK_P<1> =MEM_A_CLK_P<1> 30
83 11 MEM_A_DQ<49> =MEM_A_DQ<11> 30 83 11 MEM_B_DQ<49> =MEM_B_DQ<12> 31 MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE 83 11 MEM_A_CLK_N<1> =MEM_A_CLK_N<1> 30
83 11 MEM_A_DQ<48> =MEM_A_DQ<14> 30 83 11 MEM_B_DQ<48> =MEM_B_DQ<13> 31 MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE 83 11 MEM_A_CLK_P<2> =MEM_A_CLK_P<2> 30
MAKE_BASE=TRUE
CPU CHANNEL A DQS 7 -> DIMM A DQS 0 CPU CHANNEL B DQS 7 -> DIMM B DQS 0 83 11 MEM_A_CLK_N<2> =MEM_A_CLK_N<2> 30
MAKE_BASE=TRUE
A 83 11

83 11
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
30

30
83 11

83 11
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
31

31
83 11

83 11
MEM_A_CLK_P<3>
MEM_A_CLK_N<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_CLK_P<3>
=MEM_A_CLK_N<3>
30

30 SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
83 11 MEM_A_DM<7> =MEM_A_DM<0> 30 83 11 MEM_B_DM<7> =MEM_B_DM<0> 31
PAGE TITLE

83 11 MEM_A_DQ<63>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<5> 30 83 11 MEM_B_DQ<63>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<2> 31 83 11 MEM_B_CLK_P<0>
MAKE_BASE=TRUE
=MEM_B_CLK_P<0> 31 DDR3 ALIAS AND BITSWAPS
83 11 MEM_A_DQ<62> =MEM_A_DQ<4> 30 83 11 MEM_B_DQ<62> =MEM_B_DQ<1> 31 83 11 MEM_B_CLK_N<0> =MEM_B_CLK_N<0> 31 DRAWING NUMBER SIZE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<61>
MAKE_BASE=TRUE
=MEM_A_DQ<3> 30 83 11 MEM_B_DQ<61>
MAKE_BASE=TRUE
=MEM_B_DQ<3> 31 83 11 MEM_B_CLK_P<1>
MAKE_BASE=TRUE
=MEM_B_CLK_P<1> 31
Apple Inc. 051-8337 D
83 11 MEM_A_DQ<60> =MEM_A_DQ<2> 30 83 11 MEM_B_DQ<60> =MEM_B_DQ<7> 31 83 11 MEM_B_CLK_N<1> =MEM_B_CLK_N<1> 31 REVISION
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<59>
MAKE_BASE=TRUE
=MEM_A_DQ<1> 30 83 11 MEM_B_DQ<59>
MAKE_BASE=TRUE
=MEM_B_DQ<4> 31 83 11 MEM_B_CLK_P<2>
MAKE_BASE=TRUE
=MEM_B_CLK_P<2> 31
R
A.0.0
83 11 MEM_A_DQ<58> =MEM_A_DQ<0> 30 83 11 MEM_B_DQ<58> =MEM_B_DQ<5> 31 83 11 MEM_B_CLK_N<2> =MEM_B_CLK_N<2> 31 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
83 11 MEM_A_DQ<57> =MEM_A_DQ<7> 30 83 11 MEM_B_DQ<57> =MEM_B_DQ<6> 31 83 11 MEM_B_CLK_P<3> =MEM_B_CLK_P<3> 31 THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
83 11 MEM_A_DQ<56> =MEM_A_DQ<6> 30 83 11 MEM_B_DQ<56> =MEM_B_DQ<0> 31 83 11 MEM_B_CLK_N<3> =MEM_B_CLK_N<3> 31 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
33 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 32 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

NO STUFF CRITICAL
R3400
1
0 2
J3400
AS0B226-S40N-7F
F-RT-SM
5%
1/16W 54

C MF-LF
402
NO STUFF
C
36 18 OUT PCIE_WAKE_L 1 2
R3401 RSVD_MINI_WLAN_ACTIVE 3 4 =PP1V5_S0_MINI 5
0
1 2 RSVD_MINI_BT_ACTIVE 5 6
5% 17 14 OUT MINI_CLKREQ_L 7 8 NC
1/16W
MF-LF
402
9 10 NC C3400 1 C3401 1
84 17 IN PCIE_CLK100M_MINI_N 11 12 NC 0.1uF 10uF
20% 20%
PCIE_CLK100M_MINI_P 13 14 NC 10V 6.3V 2
84 17 IN CERM 2 X5R
15 16 NC 402 603
RESERVED NC 17 KEY 18
84 17 OUT PCIE_MINI_D2R_N 19 20
RESERVED NC NC
84 17 OUT PCIE_MINI_D2R_P 21 22 MINI_RESET_L IN 27 91
23 24

PLACEMENT_NOTE=PLACE CLOSE TO U1800. 25 26

R3490 0
C3431 27 28 1 2 =SMB_MINI_SCL 49

0.1uF 29 30 SMB_MINI_SCL R3491 0

84 17 IN PCIE_MINI_R2D_C_N 1 2 84 PCIE_MINI_R2D_N 31 32 SMB_MINI_SDA 1 2 =SMB_MINI_SDA 49

10%
84 PCIE_MINI_R2D_P 33 34
16V
X5R
35 36 TP_USB_MININ
402 37 38 TP_USB_MINIP
PLACEMENT_NOTE=PLACE CLOSE TO U1800. 39 40 NO AVAILALBLE USB ON THIS PLATFORM
C3430 41 42 NC TARGET CARDS DO NOT USE IT
0.1uF 43 44
PCIE_MINI_R2D_C_P 1 2 NC
84 17 IN
NC 45 46 NC
10% NC 47 48
16V
X5R NC 49 50

B 402
NC 51 52 B
53

516S0457

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

PCI-E MiniCard Connector

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 33 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
USB HUB-1
L3558
FERR-120-OHM-1.5A 5 =PP3V3_S3_USB_RESET
35 34 5 =PP3V3_S3_USB_HUB 1 2 USB_HUB1_VDDPLL3V3
1 1
0402
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM R3540 R3541
20K 10K
1 C3536 1 C3537 1 C3538 1 C3539 5%
1/16W
5%
1/16W
0.01UF 100PF 10UF 0.1UF MF-LF
402
MF-LF
10% 5% 20% 10% 2 2 402
16V
2 CERM
50V
2 CERM
6.3V
2 X5R
16V
2 X7R-CERM NOSTUFF
1 C3518 402 402 603 402 C3541 1
10UF 100PF
20% 5%
2 6.3V
X5R 50V
603 CERM 2 USB_HUB_RESET
402 USB_HUB_RESET_L 34 35

L3559 Q3540
FERR-120-OHM-1.5A 2N7002DW-X-G
6 3

1 2
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM USB_HUB1_VDDA3V3 =PP3V3_S3_USB_HUB 5 34 35 SOT-363 D D
0402
Q3540
2N7002DW-X-G
1 C3523 1 C3525 1 C3526 1 C3529 91 73 PGOOD_P3V3_S3 2 G S 5 G S SOT-363
1 C3542 1 C3543 1 C3544 1 C3545 1 C3546 1 C3547 0.1UF
10%
0.1UF
10%
0.01UF
10% 10%
0.01UF
NOSTUFF
0.01UF 100PF 10UF 0.1UF 0.1UF 0.1UF 16V 16V 16V 16V 1 4
10%
16V
2 CERM
5%
50V
2 CERM
20%
6.3V
2 X5R
10%
16V
2 X7R-CERM
10%
16V
2 X7R-CERM
10%
16V
2 X7R-CERM
2 X7R-CERM
402
2 X7R-CERM
402
2 CERM
402
2 CERM
402
1 C3540
0.47UF
402 402 603 402 402 402 10%
6.3V
2 CERM-X5R
402

C C
35 34 5
=PP3V3_S3_USB_HUB R3545
USB_HUB_SOFT_RESET_L 1
0 2
19

10
15
23
29
36
5
5%
NOSTUFF NOSTUFF 1/16W
1 1
CRITICAL R3597 R3599 VDD33
MF-LF
402
Y3500 10K 100K
5% 5%
24.000M-60PPM-16PF 1/16W 1/16W
1 2 MF-LF MF-LF

USB_HUB1_TEST
402 2 402 2 OMIT

1 C3519
5X3.2X1.4-SM
R3591
1 C3520 U3500
5%
18PF 1M 5%
18PF USB2514-AEZG
1 2
50V 50V
2 CERM
402
5%
2 CERM
402
11 TEST QFN USBDM_DN1/PRT_DIS_M1 1 USB_CAMERA_N 44 85
1/16W
MF-LF USBDP_DN1/PRT_DIS_P1 2 USB_CAMERA_P
402 USB_HUB_RESET_L 26 RESET*
44 85
35 34 IN
USBDM_DN2/PRT_DIS_M2 3 USB_IR_N 44 85
85 USB_HUB1_XTAL1 33 XTALIN/CLKIN
USBDP_DN2/PRT_DIS_P2 4 USB_IR_P 44 85
85 USB_HUB1_XTAL2 32 XTALOUT
USBDM_DN3/PRT_DIS_M3 6 USB_EXTA_N
USB_HUB1_LOCAL_PWR 28 43 85
SUSP_IND/LOCAL_PWR/NON_REM0 7
USBDP_DN3/PRT_DIS_P3 USB_EXTA_P 43 85
22 SDA/SMBDATA/NON_REM1
USB_HUB1_SMBDATA 8 USB_EXTC_N
USBDM_DN4/PRT_DIS_M4 43 85
USB_HUB1_SMBCLK 24 SCL/SMBCLK/CFG_SEL0 USBDP_DN4/PRT_DIS_P4 9 USB_EXTC_P 43 85
=PP3V3_S3_USB_HUB
=PP3V3_S3_USB_HUB USB_HUB1_CFG_SEL1 25 12
5 34 35
35 34 5
HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* TP_USB_HUB1_PRTPWR1
PRTPWR2/BC_EN2* 16 TP_USB_HUB1_PRTPWR2
14 CRFILT 1
1 1 NOSTUFF
1
R3598 PRTPWR3/BC_EN3* 18 TP_USB_HUB1_PRTPWR3 1
R3580 R3581 1
R3550
R3504 R35921 R3594 34 PLLFILT 20 10K
10K 10K PRTPWR4/BC_EN4* TP_USB_HUB1_PRTPWR4 10K 10K
8

NOSTUFF 10K 10K 5%

B 5%
1/16W
MF-LF
VCC
5%
1/16W
5%
1/16W
5%
1/16W
MF-LF OCS1* 13 TP_USB_HUB1_OCS1_L
5%
1/16W
MF-LF
1/16W
MF-LF
2 402
5%
1/16W
MF-LF B
2 402 U3514 MF-LF
402 2
MF-LF
2 402
2 402 OCS2* 17 TP_USB_HUB1_OCS2_L 2 402
2 402
M24C02 OSC3* 19 USB_EXTA_OC_L 43
WP_HUB1 7 WC* MLP8 SDA 5 21
OSC4* USB_EXTC_OC_L 43
1 C3534
0.1UF 6 SCL CRITICAL 1 35 USB_HUB1_RBIAS
10%
R3501 RBIAS 85

16V
2 X5R
10K 27 USB_HUB1_VBUS_DET
5% VBUS_DET
402 1 E0 NOSTUFF 1/16W MIN_NECK_WIDTH=0.25MM
1 MF-LF MIN_LINE_WIDTH=0.5MM
2 E1 R3566 1
R3565 1
R3567 402 2 USBDM_UP 30 USB_HUB1_UP_N IN 19 85

3 E2 10K 10K 10K USBDP_UP 31 USB_HUB1_UP_P 19 85

5% IN
1/16W 5% 5%
VSS THRM_PAD 1/16W 1/16W THRM_PAD
MF-LF MF-LF MF-LF
2 402
4

2 402 2 402

37
R3500
1
12K 2
1%
1/16W
BOM TABLE
MF
TABLE_5_HEAD

402 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

SEL1 SEL0 DESCRIPTION 338S0721 2 SMSC USX2061-AEZG U3500,U3600 CRITICAL HUB_USX2061

TABLE_5_ITEM

DEFAULT K23F ==> 0 0 Internal Default with Self powered Operation 338S0824 2 SMSC USB2514B U3500,U3600 CRITICAL HUB_USB2514B

0 1 SMBUS Slave Config USB_HUB1_VDD1V8

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1 0 Internal Default with Bus powered Operation
USB_HUB1_VDD1V8PLL
1 1 EEPROM Supported MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM 1 C3524 1 C3527 1 C3528 1 C3530
0.1UF 1UF 0.1UF 1UF
A 10%
16V
2 X7R-CERM
10%
16V
2 X5R
10%
16V
2 X7R-CERM
10%
16V
2 X5R SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
402 402 402 402 PAGE TITLE
NON_REM1 NON_REM0 DESCRIPTION
0 0 All ports are Non removable USB HUB 1
0 1 Port1 is non removable DRAWING NUMBER SIZE

DEFAULT K23F ==> 1 0 Port 1 and 2 are non removable Apple Inc. 051-8337 D
1 1 Port1,2 and 3 are non Removable REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
35 OF 110

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 34 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D
USB HUB-2 D
L3658
FERR-120-OHM-1.5A
35 34 5 =PP3V3_S3_USB_HUB 1 2 USB_HUB2_VDDPLL3V3
0402 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1 C3636 1 C3637 1 C3638 1 C3639
0.01UF 100PF 10UF 0.1UF
10% 5% 20% 10%
2 16V
CERM 2 50V
CERM
6.3V
2 X5R 16V
2 X7R-CERM
402 402 603 402
1 C3618
10UF
20%
6.3V
2 X5R
603
L3629
FERR-120-OHM-1.5A
1 2
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM USB_HUB2_VDDA3V3 =PP3V3_S3_USB_HUB 5 34 35

0402
1 C3623 1 C3625 1 C3626 1 C3629
1 C3642 1 C3643 1 C3644 1 C3645 1 C3646 1 C3647 0.1UF
10%
0.1UF
10%
0.01UF
10% 10%
0.01UF
0.01UF 100PF 10UF 0.1UF 0.1UF 0.1UF
10% 5% 20% 10% 10% 10% 2 16V
X7R-CERM
16V
2 X7R-CERM 2 16V
CERM
16V
2 CERM
16V 50V 6.3V 16V 16V 16V 402 402 402 402
2 CERM 2 CERM 2 X5R 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM
402 402 603 402 402 402

35 34 5
=PP3V3_S3_USB_HUB

C C

10
15
23
29
36
1

5
CRITICAL NOSTUFF NOSTUFF
R36971 R36991 VDD33
Y3600 10K 100K
5% 5%
24.000M-60PPM-16PF 1/16W 1/16W
1 2 MF-LF MF-LF
402 2 402 2 OMIT

1 C3619
5X3.2X1.4-SM
R3691 1 C3620 U3600
5%
18PF 1M 5%
18PF USB2514-AEZG
1 2
50V 50V
2 CERM
402
5%
2 CERM
402
USB_HUB2_TEST 11 TEST QFN USBDM_DN1/PRT_DIS_M1 1 USB_BT_N 44 85
1/16W
MF-LF USBDP_DN1/PRT_DIS_P1 2 USB_BT_P 44 85
402 34 IN USB_HUB_RESET_L 26 RESET*
USBDM_DN2/PRT_DIS_M2 3 USB_SDCARD_N 44 85
85 USB_HUB2_XTAL1 33 XTALIN/CLKIN
USBDP_DN2/PRT_DIS_P2 4 USB_SDCARD_P 44 85
85 USB_HUB2_XTAL2 32 XTALOUT
USBDM_DN3/PRT_DIS_M3 6 USB_EXTB_N 43 85
USB_HUB2_LOCAL_PWR 28 SUSP_IND/LOCAL_PWR/NON_REM0
USBDP_DN3/PRT_DIS_P3 7 USB_EXTB_P 43 85
USB_HUB2_SMBDATA 22 SDA/SMBDATA/NON_REM1
USBDM_DN4/PRT_DIS_M4 8 USB_EXTD_N 43 85
USB_HUB2_SMBCLK 24 SCL/SMBCLK/CFG_SEL0 USBDP_DN4/PRT_DIS_P4 9 USB_EXTD_P 43 85

35 34 5
=PP3V3_S3_USB_HUB USB_HUB2_CFG_SEL1 25 HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* 12 TP_USB_HUB2_PRTPWR1
PRTPWR2/BC_EN2* 16 TP_USB_HUB2_PRTPWR2 =PP3V3_S3_USB_HUB 5 34 35
14 CRFILT
NOSTUFF PRTPWR3/BC_EN3* 18 TP_USB_HUB2_PRTPWR3
1
R3604 R3692 1 1
R3694
1
R3698 34 PLLFILT PRTPWR4/BC_EN4* 20 TP_USB_HUB2_PRTPWR4 R3680 1 R3681 1
R36821
10K 10K 10K 10K 10K 10K 10K
8

5%
NOSTUFF 5% 5%
5% 5%
5%
5%
1/16W VCC 1/16W 1/16W
1/16W OCS1* 13 TP_USB_HUB2_OCS1 1/16W
1/16W
1/16W
MF-LF MF-LF MF-LF
MF-LF MF-LF
MF-LF
MF-LF
2 402 U3614 402 2
2 402 2 402 OCS2* 17
19
TP_USB_HUB2_OCS2 402 2 402 2 402 2

M24C02 OSC3* USB_EXTB_OC_L 43

B 1
WP_HUB2
C3634
7 WC* MLP8 SDA 5 OSC4* 21

35
USB_EXTD_OC_L 43
B
RBIAS USB_HUB2_RBIAS
0.1UF
10%
6 SCL CRITICAL R3601 1 85

16V
2 X5R
10K VBUS_DET 27 USB_HUB2_VBUS_DET
5%
402 1 E0 1/16W
NOSTUFF MF-LF USBDM_UP 30 USB_HUB2_UP_N
2 E1 402 2 IN 19 85

3 E2
1
R3665 1R3666 1R3667 USBDP_UP 31 USB_HUB2_UP_P IN 19 85
10K 10K 10K THRM_PAD
VSS THRM_PAD 5% 5% 5%
1/16W 1/16W 1/16W
4

MF-LF MF-LF MF-LF

37
2 402 2 402 2 402

R3600
1
12K 2
1%
1/16W
MF
402

USB_HUB2_VDD1V8
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM

USB_HUB2_VDD1V8PLL
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1 C3624 1 C3627 1 C3628 1 C3630
0.1UF 1UF 0.1UF 1UF
10% 10% 10% 10%
16V 16V 16V 16V
2 X7R-CERM 2 X5R 2 X7R-CERM 2 X5R
402 402 402 402

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

USB HUB 2
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 35 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CAESAR II/IV 1V2 RAIL SUPPLY

BCM57765
R3810

D
1
0
5%
1/16W
2 BCM57765_SR_VDD 37
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
CAESAR II/IV 25MHZ XTAL D
MF-LF VOLTAGE=3.3V
402

BCM5764_CLK25M_XTALI 37 86

BCM57765 PLACE AS CLOSE TO ENET CONTROLLER AS POSSIBLE

L3800
4.7UH-0.8A
R3850
BCM5764M 1 2 BCM57765_SR_LX 37 200
R3802 MAKE_BASE=TRUE 1 2 BCM5764_CLK25M_XTALO 37 86
PCAA031B-SM MIN_LINE_WIDTH=0.4MM
1.5 MAX CURRENT = 396MA MIN_NECK_WIDTH=0.2MM 5%
45 37 36 5 =PP3V3_ENET_PHY 1 2 VOLTAGE=1.2V Y3850 1/16W
MF-LF
5% 25.0000M 402
1/4W 89 PP_ENET_CTRL12 1 2
MF-LF MIN_LINE_WIDTH=0.6MM
1 C3817 1 C3818 1206 MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
BCM57765 8X4.5MM-SM-HF
86 BCM5764_CLK25M_XTAL
4.7UF 0.1UF R3813 197S0286 XTAL CHANGED FROM 197S0167 DUE TO HEIGHT RESTRICTIONS
20% 10% 0
6.3V 16V 1 2 BCM57765_SR_VFB 37
2 CERM 2 X5R CRITICAL
BCM5764M MAKE_BASE=TRUE
603 402
3
5% MIN_LINE_WIDTH=0.25MM 1 C3850 1 C3851
Q3810 1/16W
MF-LF
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V 5%
27PF
5%
27PF
402
1 PBSS5540ZDG 2 50V
CERM 2 50V
CERM
WE WANT THESE FOR EITHER CAESAR CHIP 402 402
SOT223

4 2
=PP1V2_ENET_PHY 37

BCM57765
R3811 PP1V2_ENET_PHY
MAKE_BASE=TRUE
0 MIN_LINE_WIDTH=0.6MM
37 TP_BCM57765_SR_VDDP 1 2 MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE VOLTAGE=1.2V
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
5%
1/16W
1 C3825 1 C3826
VOLTAGE=3.3V MF-LF 10UF 0.1UF
402 20% 10%
6.3V 16V
2 X5R 2 X5R

C BCM5764M
603-2 402
C
R3812 WE WANT THESE FOR EITHER CAESAR CHIP
0 PLACE THESE CLOSE TO L3800 AND AS CLOSE TO ENET CONTROLLER AS POSSIBLE
1 2 ENET_CTRL12
5%
1/16W
MF-LF
402

CAESAR II/IV ACTIVITY LED

45 37 36 5 =PP3V3_ENET_PHY

37 BCM57765_SR_DISABLE DEVELOPMENT

BCM57765
1
R3805
330
NO INTERNAL PULL UP/DOWN. MUST PULL DOWN TO USE INTERNAL SWITCHER R3830
1 5%
1/16W
10K MF-LF
5% 2 402
1/16W
MF-LF ENET_ACT
2 402
A
DEVELOPMENT
LED3801
GREEN-3.6MCD
2.0X1.25MM-SM
K
SILKSCREEN:ENET ACT

B B
3.3V ENET FET
ENET_PWR_ON = "S0" || (S3 power && WOL_EN)
37 TP_BCM5764_TRAFFICLED_L ENET_LED_ACT_L
MAKE_BASE=TRUE

CRITICAL
Q3880
NTR4101P
SOT-23-HF

5 =PP3V3_S3_ENETFET
PP3V3_ENET_FET 5
CAESAR II/IV WAKE# ISOLATION
S

2 3

R3880
1 =PP3V3_ENET_PHY 5
G

36 37 45

10K
1 C3880
5% 0.1UF 1
1/16W 10%
MF-LF
2 402
16V
2 X5R C3881
1
R3870
R3881 402 Q3870 10K
0.01UF 5%

G 1
100K SSM3K15FV 1/16W
1 2 ENET_PWR_L 1 2 MF-LF
WOL_EN_L 5%
SOD-VESM-HF 2 402
1/16W 10%
CERM
Q3881 MF-LF

S
3 402 16V 33 18 PCIE_WAKE_L ENET_WAKE_L =ENET_WAKE_L 37
BCM5764M 402 MAKE_BASE=TRUE

3
2N7002DW-X-G

2
D

SOT-363 6
20 14 WOL_EN 5 G S
BCM5764M
A D
Q3881
4 2N7002DW-X-G
SOT-363
SYNC_MASTER=MASTER SYNC_DATE=N/A A
91 81 64 63 47 46 26 18 5 PM_SLP_S3_L 2 G S PAGE TITLE

1
Caesar II/IV Support
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 36 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BCM57765 SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor. BCM57765

36 TP_BCM57765_SR_VDDP BCM57765_SR_LX 36 37
R3920 =PP1V2_ENET_PHY 36 37
BCM57765 0
37 36 BCM57765_SR_VDD 37 36 BCM57765_SR_VFB 1 2 396mA (1000base-T, Caesar II)
45 37 36 5 =PP3V3_ENET_PHY 37 PP3V3R1V8_SW_LR_OUT R3915 5% CRITICAL
0 1/16W
86mA (1000base-T, Caesar II) 1 2 37 BCM57765_VDDOCR_PIN20 MF-LF L3920
402
CRITICAL 5%
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
FERR-600-OHM-0.5A
1/16W BCM57765 VOLTAGE=3.3V
L3900 MF-LF PP1V2_ENET_PHY_AVDDL 1 2
402
FERR-600-OHM-0.5A R3900 MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm SM
1 2 37 PP3V3_ENET_PHY_XTALVDDH
0 VOLTAGE=1.2V
1 2 37 BCM57765_XTALVDDH
SM
MIN_LINE_WIDTH=0.4 mm MIN_LINE_WIDTH=0.4 mm C3921 1 1 C3920
D
MIN_NECK_WIDTH=0.2 mm 5% MIN_NECK_WIDTH=0.2 mm 0.1UF 4.7UF
D VOLTAGE=3.3V 1/16W VOLTAGE=3.3V
C3900 1 MF-LF
402
10%
16V
10%
6.3V
2 2
0.1UF X7R-CERM X5R-CERM
10% 402 603
16V
X7R-CERM 2 CRITICAL
CRITICAL 402 L3925
L3905 FERR-600-OHM-0.5A
FERR-600-OHM-0.5A
PP1V2_ENET_PHY_PCIEPLL 1 2
1 2 PP3V3_ENET_PHY_BIASVDDH MIN_LINE_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SM
SM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
VOLTAGE=3.3V 1 C3905 C3926 1 1 C3925
0.1UF 0.1UF 4.7UF
10% 10% 10%
16V 16V 6.3V
2 X7R-CERM X7R-CERM 2 2 X5R-CERM
CRITICAL 402 402 603
L3910 CRITICAL
FERR-600-OHM-0.5A L3930
1 2 PP3V3_ENET_PHY_AVDDH FERR-600-OHM-0.5A
MIN_LINE_WIDTH=0.4 mm
SM PP1V2_ENET_PHY_GPHYPLL 1 2
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V MIN_LINE_WIDTH=0.4 mm
R3910 1
1 C3910 1 C3911 MIN_NECK_WIDTH=0.2 mm SM
VOLTAGE=1.2V
4.7K 0.1UF 0.1UF
5%
10%
16V
10%
16V C3931 1 1
C3930
1/16W 2 2
MF-LF
X7R-CERM X7R-CERM 0.1UF 4.7UF
402 402 10% 10%
402 16V 6.3V
2
X7R-CERM 2 2 X5R-CERM
402 603

BCM57765 BCM57765
R3940 1
1
R3941 C3915 1 1
C3916
4.7K 4.7K 4.7UF 0.1UF
C3936 C3935

61
10% 10% 1 1
5% 5%

7
6.3V 16V
1/16W 1/16W 2 2

C
X5R-CERM X7R-CERM 0.1UF 10UF
C

BIASVDDH

VDDC

VDDIO
XTALVDDH
VDDIO
VDDIO

VDDC

REGCTL12

VDDIO

WAKE*

GPHY_PLLVDDL

VDDC
VDDC
MF-LF MF-LF 603 402
=PP3V3_S0_ENETPHY 10% 10%
AVDDH AVDDL

PCIE_PLLVDDL
37 5 402 402 16V 6.3V
2 2
X7R-CERM 2 2 X5R
BCM57765 402 805
1
R3942
C3950 1K
0.1uF 5% GPIO1_LR_OUT is not for SD Card power,
1/16W CRITICAL
86 17 OUT PCIE_ENET_D2R_N 1 2
MF-LF just decoupling for BCM57765 CR I/Os.
2
402 OMIT
Connect only to U3900 pins 9 and 20.
10%
16V C3951 BCM57765_VMAIN_PRSNT 58
U3900 40 ENET_MDI_P<0>
37 SMB_DATA (IPD-BCM57765) TRD0_P BI 38 86
X5R
0.1uF BCM5764M PP3V3R1V8_SW_LR_OUT 37
402
QFN-8X8 TRD0_N 41 ENET_MDI_N<0> BI 38 86 MIN_LINE_WIDTH=0.3 mm
86 17 OUT PCIE_ENET_D2R_P 1 2
MIN_NECK_WIDTH=0.2 mm
86 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N VERSION 2 TRD1_P 44 ENET_MDI_P<1> BI 38 86 VOLTAGE=3.3V
10% 86 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P TRD1_N 43 ENET_MDI_N<1> BI 38 86 BCM57765 BCM57765 BCM57765
16V

C3955
X5R
402 PCIE_ENET_R2D_P 33
TRD2_P 46 ENET_MDI_P<2> BI 38 86 C3970 1 1
C3971 1
C3972
86 PCIE_RXD_P 4.7UF 0.1UF 0.1UF
0.1uF TRD2_N 47 ENET_MDI_N<2> BI 38 86
86 PCIE_ENET_R2D_N 34 PCIE_RXD_N 10%
6.3V
10%
16V
10%
16V
86 17 IN PCIE_ENET_R2D_C_P 1 2
TRD3_P 50 ENET_MDI_P<3> BI 38 86
X5R-CERM 2 2 X7R-CERM 2 X7R-CERM
PCIE_CLK100M_ENET_P 31 49 ENET_MDI_N<3> 603 402 402
10%
84 17 IN PCIE_REFCLK_P TRD3_N BI 38 86
16V C3956 84 17 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N
X5R
402
0.1uF 5
GPIO_0/SERIAL_DO NC
86 17 IN PCIE_ENET_R2D_C_N 1 2
91 27 IN ENET_RESET_L 11 PERST* (IPD)

(IPD)
GPIO_1/SERIAL_DI 8 BCM57765
BCM57765 R3972 0
10% ENET_CLKREQ_L 12 CLKREQ* GPIO_2 9 BCM57765_MEDIA_SENSE 1 2 ENET_ENERGY_DET
R3943 16V
17 14 OUT (OD)
5% 1/16W MF-LF 402
OUT 14 17 37

0 X5R
NOTE: "IPx" == Programmable pull-up/down BCM57765
=ENET_WAKE_L 1 2 402 BCM57765_WAKE_L 3 LINKLED* (OD)
37 36 OUT
(IPx-BCM57765) NC 1 BCM57765_SD_DETECT_L R3973 0 1 2 SDCONN_CD_L IN 45
(See note) 5% 5% 1/16W MF-LF 402
1/16W
MF-LF 20 14 IN ENET_LOW_PWR 4 LOW_PWR (IPD) (IPU-BCM57765) PCIE_VDDL 26 37 BCM57765_CR_CMD R3974 0 1 2 SDCONN_CMD IN 45 86
WAKE# 402 PLACE_NEAR=L3999.1:1 mm 5% 1/16W MF-LF 402

DC0 21 SDCONN_CLK OUT 45 86

Must isolate from PCIe WAKE# if PHY 37 BCM57765_SMB_CLK 6 VDDC
is powered-down in S3/S5. Standard BCM57765_SMB_DATA 10 UART_MODE (IPD-BCM5764M) DC4 25 SDCONN_DATA<0> BI 45 86

N-channel FET isolation suggested. DC3 24 SDCONN_DATA<1> BI 45 86

BCM5764_SCLK 66 SCLK
B If PHY is always powered then alias
37
DC2 23 SDCONN_DATA<2> 45 86
B

(IPU-BCM57765)
BCM5764_MISO 64 BI
37 SI

(IPU)
=ENET_WAKE_L to PCIE_WAKE_L. DC1 22 SDCONN_DATA<3> BI 45 86
BCM5764_MOSI 65 SO
37
NC 52 86 BCM57765_CR_DATA<4> R3975 0 1 2 SDCONN_DATA<4> BI 45 86
BCM5764_CS_L 63 CS* 5% 1/16W MF-LF 402
37
VMAIN_PRSNT 53
86
37 BCM57765_CR_DATA<5> R3976 0 1 2 SDCONN_DATA<5> BI 45 86
5% 1/16W MF-LF 402
TP_BCM5764_SPD100LED_L 2 SPD100LED* VAUX_PRSNT 54
86
37 BCM57765_CR_DATA<6> R3977 0 1 2 SDCONN_DATA<6> BI 45 86
5% 1/16W MF-LF 402
36 TP_BCM5764_TRAFFICLED_L 67 TRAFFICLED* VDDC 55
86
37 BCM57765_CR_DATA<7> R3978 0 1 2 SDCONN_DATA<7> BI 45 86
5% 1/16W MF-LF 402

(IPx-BCM57765) SMB_CLK 59 BCM57765_CE_L_MS_INS_L 37 BCM57765

86 36 IN BCM5764_CLK25M_XTALI 18 XTALI All resistors above BOMOPTIONed BCM57765
(IPU-BCM57765) ENERGY_DET 60 BCM57765_CR_PWREN 37
86 36 OUT BCM5764_CLK25M_XTALO 19 XTALO
(IPU-BCM57765) DC5 57 SDCONN_WP IN 45

86 BCM5764_RDAC 38 RDAC (IPD?-BCM57765) SPD1000LED* 68 BCM57765_SR_DISABLE 36 BCM57765 supports both active-levels for WP.
THRM_PAD (See note)
PHY Non-Volatile Memory BCM5764M Support

69
1
R3965 All parts below BOMOPTIONed BCM5764M
1.24K BCM57765_SR_DISABLE
ROM contains MAC address, PCIe config 1% BCM5764M pin-function BCM5764M
1/16W
info as well as code for Bonjour proxy. MF-LF If BCM57765 switching regulator is 60-ENERGY_DET 37 BCM57765_CR_PWREN R3980 0 1 2 ENET_ENERGY_DET 14 17 37
2 402 5% 1/16W MF-LF 402
Required for proper PHY operation. used, this pin can float (alias to (See note)
13-WAKE* 37 36 BCM57765_SR_VFB R3981 0 1 2 =ENET_WAKE_L 36 37
(Required ROM size TBD) TP_). If not used, must be pulled 5% 1/16W MF-LF 402

45 37 36 5 =PP3V3_ENET_PHY to 3.3V ENET via 1K resistor (not 53-VMAIN_PRSNT 86 37 BCM57765_CR_DATA<5> R3982 1K 1 2 =PP3V3_S0_ENETPHY 5 37
5% 1/16W MF-LF 402
provided on this page). R3983 4.7K
59-SMB_CLK 37 BCM57765_CE_L_MS_INS_L 1 2 =PP3V3_ENET_PHY 5 36 37 45
5% 1/16W MF-LF 402
58-SMB_DATA 37 BCM57765_VMAIN_PRSNT R3984 4.7K 1 2
5% 1/16W MF-LF 402
C3990 R3985 1K
6

1
54-VAUX_PRSNT 86 37 BCM57765_CR_DATA<6> 1 2
5% 1/16W MF-LF 402
VCC 0.1UF
10% 16-VDDIO 37 36 BCM57765_SR_LX R3986 0 1 2
16V 5% 1/16W MF-LF 402
U3990 2 X7R-CERM
20-XTALVDDH 37 BCM57765_VDDOCR_PIN20 R3987 0 1 2 PP3V3_ENET_PHY_XTALVDDH 37
AT45DB011D 402
5% 1/16W MF-LF 402
SOIC-8S1
55-VDDC 86 37 BCM57765_CR_DATA<7> R3988 0 1 2 =PP1V2_ENET_PHY 36 37
BCM5764_SCLK 2
SCK SI 1 BCM5764_MOSI 5% 1/16W MF-LF 402
37 37
R3989 0
A BCM5764_CS_L 4 CS*
OMIT 17-VDDC
14-VDDC 37 36
37 BCM57765_XTALVDDH
BCM57765_SR_VDD R3998 0
1

1
2

2
5%
5%
1/16W
1/16W
MF-LF
MF-LF
402
402
SYNC_MASTER=T27 SYNC_DATE=11/30/2009 A
37
06-VDDC 37 BCM57765_SMB_CLK R3999 0 1 2 PAGE TITLE
SO 8 BCM5764_MISO
5
WP*
NOSTUFF
37

L3999
5% 1/16W MF-LF 402
Ethernet PHY (Caesar II/IV)
1 1 FERR-600-OHM-0.5A DRAWING NUMBER SIZE
3 RESET* R3990 R3997 051-8337 D
GND
5%
4.7K
5%
4.7K 26-PCIE_VDDL 37 BCM57765_CR_CMD
PLACE_NEAR=U3900.26:2 mm
1 2 Apple Inc. REVISION
7

1/16W 1/16W Keep net short, BCM5764M BCM5764M SM CRITICAL R

MF-LF MF-LF A.0.0
2 402 2 402 with no stubs. C3999 1 1
C3998
0.1UF 4.7UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: Pull-down on SO plus internal pull-ups on 10% 10%
16V 6.3V THE INFORMATION CONTAINED HEREIN IS THE
other 3 SPI pins configures BCM57765 for the X7R-CERM 2 2 X5R-CERM PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
402 603 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
Atmel AT45DB011D (1Mbit) ROM. If a different I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
PLACE_NEAR=U3900.26:1 mm PLACE_NEAR=L3999.1:1 mm 39 OF 110
ROM is used then the straps must change. II NOT TO REPRODUCE OR COPY IT

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
NOTE: BCM5764M requires SI pull-down instead of SO.
IV ALL RIGHTS RESERVED 37 OF 92

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

CRITICAL

T4000
LFE9249APF
SOI
1 TCT1 MCT1 24 ENET_MCT0

C 86 37 ENET_MDI_P<3> 2 TD1+ 1CT:1CT MX1+ 23 ENET_MDI_T_P<3> 38 86 OMIT_TABLE

CRITICAL
C
86 37 ENET_MDI_N<3> 3 TD1- MX1- 22 ENET_MDI_T_N<3> 38 86
J4000
4 TCT2 MCT2 21 ENET_MCT1
RJ45-K74-K75
F-ANG-TH
ENET_MDI
86 37 ENET_MDI_N<2> 5 TD2+ 1CT:1CT MX2+ 20 ENET_MDI_T_N<2> 38 86 86 38 ENET_MDI_T_P<0> 1
TRAN_P0
86 38 ENET_MDI_T_N<0> 2
TRAN_N0
86 37 ENET_MDI_P<2> 6 TD2- MX2- 19 ENET_MDI_T_P<2> 38 86 86 38 ENET_MDI_T_P<1> 3
TRAN_P1
86 38 ENET_MDI_T_P<2> 4
TRAN_P2
7 TCT3 MCT3 18 ENET_MCT2 86 38 ENET_MDI_T_N<2> 5
TRAN_N2
86 38 ENET_MDI_T_N<1> 6
TRAN_N1
86 37 ENET_MDI_P<0> 8 TD3+ 1CT:1CT MX3+ 17 ENET_MDI_T_P<0> 38 86
86 38 ENET_MDI_T_P<3> 7
TRAN_P3
86 38 ENET_MDI_T_N<3> 8
TRAN_N3
86 37 ENET_MDI_N<0> 9 TD3- MX3- 16 ENET_MDI_T_N<0> 38 86

9
10 TCT4 MCT4 15 ENET_MCT3 SHIELD
10 PINS
86 37 ENET_MDI_N<1> 11 TD4+ 1CT:1CT MX4+ 14 ENET_MDI_T_N<1> 38 86
514-0733

86 37 ENET_MDI_P<1> 12 TD4- MX4- 13 ENET_MDI_T_P<1> 38 86

TABLE_5_HEAD

157S0071 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

514-0654 1 K22/K23 PROD. RJ45 J4000 CRITICAL METAL_IO

TABLE_5_ITEM

514-0733 1 K74/K75 RJ45, PLASTIC, PD/NI J4000 CRITICAL PLASTIC_IO

B B

ENET_TCT R4000
1
R4001
1
R4002
1
R4003
1

75 75 75 75
5% 5% 5% 5%
1 C4001 1 C4002 1 C4003 1 C4004 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 2 402 2 402 2 402 2 402
10V
2 CERM 2 10V 10V
2 CERM 2 10V
CERM CERM
402 402 402 402
ENET_MCT_BS
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
NOSTUFF
PLACE ONE CAP PER TCT PIN 1 C4000
NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps. 1000PF
10%
2 2KV
CERM
1206

NOTE: BOB SMITH TERMINATION FOR EMC.

A SYNC_MASTER=MASTER SYNC_DATE=N/A A
PAGE TITLE

Ethernet Connector
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 38 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V5_FWRS0_FWXIO 5
5 =PP3V3_FWRS0_FWXIO
41 40 39 5 =PP3V3_FW_FWPHY

C4124 1
C4123 1
C4122 1
C4121 1
C4120 1
R4125 1
C4100 1
C4101 1
C4102 1
C4103 1
C4104 1
C4105 1
1UF 1UF 1UF 1UF 1UF 1
1UF 1UF 1UF 1UF 1UF 1UF 10% 10% 10% 10% 10%
5%
10% 10% 10% 10% 10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 1/16W
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 402 402 402 402 402 MF-LF
402 402 402 402 402 402 402
2

89 PP1V5_FW_VDDA
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
C4128 1
C4127 1
C4126 1
C4125 1

1
C4106 1
C4107 1
C4108 1
1UF 1UF 1UF 1UF

D
R4110
1
5%
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2 D
1/16W 402 402 402
MF-LF
402
2

89 PP3V3_FW_AVDD
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V PP1V95_FW_FWPHY 40 89
1
C4110 1
C4111 1
C4112 1
C4113 1
C4114 1
C4115 1

R4117 1UF 1UF 1UF 1UF 1UF 1UF

1 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V Layout Pads Overlayed
5% 2 2 2 2 2 2
1/16W
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402 C4132 1
C4131 1
C4130 1
R4135 1
R4119 1 MF-LF
402
1UF 1UF 1UF 1
FW_TI_EXT_VREG FW_TI_INT_VREG
1 2 10% 10% 10% 1 1
5%
6.3V
2
6.3V
2
6.3V
2
5%
1/16W
R4190 R4192
1/16W 89 PP3V3_FW_VDDA CERM
402
CERM
402
CERM
402 MF-LF 4.7 1
MF-LF MIN_LINE_WIDTH=0.3 mm 402 5% 5%
2
402
2
MIN_NECK_WIDTH=0.2 mm 1/16W 1/16W
VOLTAGE=3.3V MF-LF MF-LF
89 PP3V3_FW_PLLVDD 89 PP1V96_FW_PLLVDD 2 402 2 402
MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V FWXIO_VDD15COMB VOLTAGE=1.96V
C4117 1
C4118 1
C4119 1
FWXIO_VDD33COMB
C4135 1
Power Aliases: 1UF 1UF 1UF 1UF
10%
6.3V
10%
6.3V
10%
6.3V
FWXIO_VDD33COMIO 10%
6.3V
PP1V96_FW_XTAL
FW_FWPHY nets are PHY power, and for CERM 2 CERM 2 CERM 2 CERM 2 MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

G10

H10

J10

B12

A10

E10

F10

M10

K10

B10

C12

B11

C11
402 402 402 402
multi-port systems must come from bus power.

C8
J3

G3
H3

M9
VOLTAGE=1.96V
4
C4190 1
FWRS0_FWXIO nets are OHCI/PCIe power, and C4137 1 1
C4138 1
C4139 VCC 0.22UF

PLLVDD_3_3

PLLVDD_CORE

VDD_15_COMB

VDD_33_COMB

VDD_33_COM_IO
FWXIO_REF_PCIE VDD_33 DVDD_3_3 VDDA_33 AVDD_3_3 VDD_15 VDDA_15 DVDD_CORE 1UF 1UF 1UF 10%
can be S0.

(VDD_33_AUX)
10%
6.3V
10%
6.3V
10%
6.3V
Y4190 6.3V
CERM-X5R 2
OMIT CERM 2 2 CERM 2 CERM
98P3040MHZ 402
1
For single-port systems, all FW power should R4141 R4140 1 CRITICAL 402 402 402 R4191 SM

be tied together and powered by S0 or by the 232 14.3K 22 3 CRITICAL 1

1% 1% U4100 1 2 CLK98M_FW_XI_R OUT TRI-ST/NC NC
5K pull-down device detect circuit. 1/16W 1/16W
MF-LF MF-LF 5%
402 402
XIO2213B 1/16W
2 2 MF-LF GND

C PLACEMENT_NOTE=Place C4140 close to U1400

PLACEMENT_NOTE=Place C4141 next to C4140
FWXIO_REF0_PCIE
FWXIO_REF1_PCIE
A13

A12
REF0_PCIE
REF1_PCIE
BGA

Single-port:
XI
RSVD_19
P4

P3
CLK98M_FW_XI
TP_FWOHCI_XO
402
2 C
PC[0:2] = ’000’
84 17 IN PCIE_FW_R2D_C_P C4140 1 2 91 27 IN FW_RESET_L B13 PERST* PC0 E9 =FWPHY_PC0 IN 40
10% 16V X5R 402
0.1uF Multiple-ports: PC1 E8
84 PCIE_FW_R2D_P A4 RXP
84 17 IN PCIE_FW_R2D_C_N C4141 1 2
PC[0:2] = ’100’ PC2 A11
10% 16V X5R 402 84 PCIE_FW_R2D_N A3 RXN =PP3V3_FW_FWPHY 5 39 40 41
0.1uF
Alias =FWPHY_PC0 DS0 N9 =FWPHY_DS0 IN 40

84 17 OUT PCIE_FW_D2R_P C4145 1 2

84 PCIE_FW_D2R_C_P A9 TXP PCI EXPRESS as appropriate DS1 P9 =FWPHY_DS1 IN 40
R4170 1
R4171
10% 16V X5R 402 84 PCIE_FW_D2R_C_N A8 TXN 1K
0.1uF LINKON_L E1 FWOHCI_LINKON_L 1 2 470
5%
84 17 OUT PCIE_FW_D2R_N C4146 1 2
LKON_DS2_P D1 FWPHY_LKON_DS2 5% 1/16W
10% 16V X5R 402 1/16W MF-LF DS2 hard-strapped to 1,
0.1uF 40 OUT =FW_CLKREQ_L J12 CLKREQ* MF-LF 402
PLACEMENT_NOTE=Place C4145 close to UA200 LCLK_L G2 FWOHCI_CLK98M_LCLK 402 2
page assumes no more than
PLACEMENT_NOTE=Place C4146 next to C4145
84 17 IN PCIE_CLK100M_FW_P A1 REFCLK_P LCLK_P H2 2 FW800 connectors
84 17 IN PCIE_CLK100M_FW_N B1 REFCLK_M
PCLK_L G1 FWPHY_CLK98M_PCLK Strap DSx high on unused ports.
FWXIO_REFCLK_SEL H13 REFCLK_SEL PCLK_P F1

PINT_L D2 FWPHY_PINT
FWXIO_SCL J13 SCL PINT_P D3

FWXIO_SDA H12 SDA

LPS_L C1 FWOHCI_LPS
P1 GPIO0 LPS_P C2
NC
R4151 1
1
R4150 1 R4152 N2 GPIO1 1
1K 220 220 NC LREQ_L F2 FWOHCI_LREQ R4175
P2 GPIO2 10K
5%
1/16W
5%
1/16W
5%
1/16W
NC LREQ_P E2 5%
N3 GPIO3
MF-LF MF-LF
402 2
MF-LF NC (IPU)
1/16W
2 402
402 MF-LF
2 N4 H1
NC GPIO4 CTL0 NC 2
402
P5 GPIO5 CTL1 J1
NC NC
P6 GPIO6
NC D0 J2

B NC
N6 GPIO7
D1 K2
NC
NC B
40 OUT =FW_PME_L P8 OHCI_PME* D2 K1
NC
D3 L1
FWXIO_CYCLEOUT N8 CYCLEOUT NC
D4 L2
NO STUFF NC
1
TP_FWXIO_GRST_L C13 GRST* (IPU) D5 L3
NC
1
R4185
R4153 D6 M2 6.34K
=PP3V3_FW_FWPHY
47K 1394B OHCI & PHY D7 M3
NC 1%
=PPVP_FW_PHY_CPS
41 40 39 5 5%
1/16W TP_FWXIO_JTAG_TMS E12 RSVD_0 (JTAG_TMS)
NC 1/16W
MF-LF
40

MF-LF 402
2
402 TP_FWXIO_JTAG_TDO F12 RSVD_1 (JTAG_TDO) R0 N1 FWPHY_R0 2
1
TP_FWXIO_JTAG_TDI F13 RSVD_2 (JTAG_TDI) R1 M1 FWPHY_R1 R4186
1 390K
R4160 G12 RSVD_3 (JTAG_TCK) 5%
1K K12
PD B3 1/16W
5% NC RSVD_4 MF-LF
1/16W 402
MF-LF NC
L12 RSVD_5 CNA A2 TP_FWPHY_CNA 2
402
2 L13 RSVD_6 CPS P12 FWPHY_CPS
NC
91 FWXIO_SNOOP_EN M8 RSVD_7
(IPU) PHY_RESET* B4 91 FWPHY_RESET_L
(Snoop Enable, for FireBug) M11 RSVD_8
NC
M12 RSVD_9
NC 1
C4189
M13 RSVD_10 TPBIAS0 K13 FW_P0_TPBIAS
NC BI 40
0.22UF
N10 G13 FW_P1_TPBIAS 10%
NC RSVD_11 Unused Ports: TPBIAS1 BI 40 6.3V
2 CERM-X5R
R4180
1
NC
N11 RSVD_12 TPBIAS2 E13 FW_P2_TPBIAS BI 40 402
N12
TP/NC TPBIASx
1K NC RSVD_13
5% TP/NC TPAx_P/TPAx_N TPA0_P K14 FW_P0_TPA_P BI 40
N13 RSVD_14
1/16W
MF-LF
NC Ground TPBx_P/TPBx_N TPA0_N L14 FW_P0_TPA_N BI 40
P10 RSVD_15
402
2 NC TPA1_P F14 FW_P1_TPA_P BI 40 86
P11 RSVD_16
NC TPA1_N G14 FW_P1_TPA_N BI 40 86
FW_TI_EXT_VREG D12 RSVD_17 (JTAG_TRST)
R41811 1
R4182 TPA2_P B14 FW_P2_TPA_P BI 40 86
D13 RSVD_18
A 1K
5%
1/16W
MF-LF
1K
5%
1/16W
MF-LF
TPA2_N

TPB0_P
C14

M14
FW_P2_TPA_N

FW_P0_TPB_P
BI 40 86

40
SYNC_MASTER=MASTER SYNC_DATE=N/A A
FWPHY_BMODE A5 BI PAGE TITLE
402 402 BMODE
2 2

FWPHY_TESTM B2 TESTM
TPB0_N
TPB1_P
N14

H14
FW_P0_TPB_N BI
FireWire LLC/PHY (XIO2213B)
DRAWING NUMBER SIZE
FWPHY_TESTW A6 TESTW_VREG_PD TPB1_N J14

P13 SE TPB2_P D14 Apple Inc. 051-8337 D

FW_TI_INT_VREG
1 P14 E14
REVISION
R4189 SM TPB2_N
1K
R
A.0.0
GND VSS VSSA VSSA_PCIE NOTICE OF PROPRIETARY PROPERTY: BRANCH
5%
1/16W
PLLGND
MF-LF THE INFORMATION CONTAINED HEREIN IS THE
N5

G5
G6

G8
G9

H5
H6

H8
H9

A14

C10

C7
402
2
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
41 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 39 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Termination
Place close to FireWire PHY

39 FW_P0_TPBIAS
VOLTAGE=1.86V
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.08MM

1394 PHY 1.95V SUPPLY 1 C4250

D TI PHY requires 1UF, not 0.33uF spec value. 1UF
10%
D
2 6.3V
CERM
402

FW_TI_EXT_VREG
CRITICAL
L4250 L4251
U4200 PP1V95_FW_FWPHY 39
MAKE_BASE=TRUE
89
18NH-250MA
1 2
18NH-250MA
1 2
41 40 39 5 =PP3V3_FW_FWPHY TPS799195 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm TI PHY "Peaking Inductors" To improve Data Eye.
SON NET_SPACING_TYPE=POWER 0402 0402
6 IN OUT 1 MAX_NECK_LENGTH=3 MM
4 EN VOLTAGE=1.96V
NR 2 P1V95_FW_NR Peak Current: 100mA
FW_TI_EXT_VREG 86 FW_P0_TPA_L_P 86 FW_P0_TPA_L_N
FW_TI_EXT_VREG FW_TI_EXT_VREG VOLTAGE=1.86V VOLTAGE=1.86V
C4200 1 5 NC
THRML
C4201 1 1 C4202 NO_TEST=TRUE NO_TEST=TRUE
1UF GND PAD
10%
6.3V 3 7
0.01UF 2.2UF
CERM 2
402
10%
16V
CERM 2
20%
4V
2 X5R R42501 R4251
1

402 402 56.2 56.2

1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402

39 FW_P0_TPA_P FW_PORT0_TPA_P 41 86
MAKE_BASE=TRUE
39 FW_P0_TPA_N FW_PORT0_TPA_N 41 86
MAKE_BASE=TRUE
39 FW_P0_TPB_P FW_PORT0_TPB_P 41 86
MAKE_BASE=TRUE
39 FW_P0_TPB_N FW_PORT0_TPB_N 41 86
MAKE_BASE=TRUE

R42521 R4253
1

C FireWire Aliases For Connectivity 56.2

1%
1/16W
1%
56.2
1/16W
C
MF-LF MF-LF
402 2 2 402
39 =FW_CLKREQ_L FW_CLKREQ_L 14 17
MAKE_BASE=TRUE
86 FW_P0_TPB_L_N 86 FW_P0_TPB_L_P
39 =FW_PME_L FW_PME_L 14 20 VOLTAGE=0V VOLTAGE=0V
MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE

L4252 L4253
39 =PPVP_FW_PHY_CPS PPVP_FW_PHY_CPS 41 89
18NH-250MA 18NH-250MA
MAKE_BASE=TRUE
1 2 1 2
0402 0402

FW_P0_TPA_C

R4254
1

C4254 1 1%
4.99K
220PF 1/16W
5% MF-LF
25V
CERM 2 2 402
1394 PHY STRAPPING OPTIONS 402

B 41 40 39 5 =PP3V3_FW_FWPHY
B
NOSTUFF
2ND & 3RD TPA/TPB PAIR UNUSED
R4255 1R4256
1

10K 10K
5% 5% 39 FW_P1_TPBIAS NC_FW_PORT1_TPBIAS
1/16W 1/16W MAKE_BASE=TRUE
MF-LF MF-LF NO_TEST=TRUE
2 402 2 402
86 39 FW_P1_TPA_P NC_FW_PORT1_TPA_P
MAKE_BASE=TRUE
39 =FWPHY_DS0 FW_PHY_DS0 NO_TEST=TRUE
MAKE_BASE=TRUE
86 39 FW_P1_TPA_N NC_FW_PORT1_TPA_N
39 =FWPHY_DS1 FW_PHY_DS1 MAKE_BASE=TRUE
MAKE_BASE=TRUE THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT NO_TEST=TRUE
IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE.

R4258
1

10K
5%
1/16W
MF-LF 39 FW_P2_TPBIAS NC_FW_PORT2_TPBIAS
2 402 MAKE_BASE=TRUE
NO_TEST=TRUE

86 39 FW_P2_TPA_P NC_FW_PORT2_TPA_P
MAKE_BASE=TRUE
NO_TEST=TRUE
86 39 FW_P2_TPA_N NC_FW_PORT2_TPA_N
MAKE_BASE=TRUE
NO_TEST=TRUE

A 39 =FWPHY_PC0 FW_PHY_PC0
MAKE_BASE=TRUE
SYNC_MASTER=MASTER SYNC_DATE=N/A A
iMacs are now one port only and have Power Code "000" PAGE TITLE

R4257
1 FW: 1394B MISC
10K DRAWING NUMBER SIZE
5%
1/16W
MF-LF Apple Inc. 051-8337 D
2 402 REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
42 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 40 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CRITICAL
INRUSH RESETABLE PTC
F4301
0.3AMP-60V
1 2
PLACEMENT_NOTE=PLACE CLOSE TO F4300
SMD030F-SM XW4300 PPVP_FW_PHY_CPS FAST NON-RESETABLE FUSE
1 2 40 89 THIS FUSE WILL NOT BLOW
CRITICAL VOLTAGE=12V IT IS HERE FOR SAFETY ONLY
R4300 SM MIN_LINE_WIDTH=0.5MM CRITICAL CRITICAL
POUR COPPER TO SINK HEAT CRITICAL
0.33 2 Q4300
MIN_NECK_WIDTH=0.25MM
F4300 L4300
D 41 5 =PP12V_S0_FW 1
5%
P12V_FW_R
MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM FDC610PZ
D4300
SM 3AMP-32V
FW_PORT0_VP_F
FERR-250-OHM
FW_PORT0_VP
D
1W VOLTAGE=12V P12V_FW_CL 1 2 P12V_FW_D 1 2 89 1 2 89

12 VOLTS MF
2512
SSOT6
MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM
MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM
MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM SM MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM
7 WATTS MAX PER PORT

6
VOLTAGE=12V CRS08-1.5A-30V VOLTAGE=12V 603 VOLTAGE=12V VOLTAGE=12V

2 5
4
1 C4300
0.01UF

1
10% SHOULD BE DONE AS A POWER STRIP(SUBPLANE)
50V
2 X7R
Q4301 5.1V 3 603-1

3
1
MMBT2907AXG D4301
60V-600MA MMBZ5231BXG
SOT23 1
SOT23

3
R4352
51.1K2
1 41 FW_CURRENT_LIMIT
1%
1/16W
MF-LF
1
R4301
402 10K FW_TURN_ON_V
5%
1/16W 1
R4302 1R4303
PP3V3_FW_ESD"Snapback" & "Late VG" Protection
MF-LF
2 402 15K 20K 89 41
5% 5% CRITICAL
FW_CURRENT_LIMIT_Q 1/10W 1/16W
MF-LF MF-LF CRITICAL DP4310
2 603 2 402
3 DP4310 BAV99DW-X-G
SOT-363
Q4302 1 FW_FET_LINEAR_LIMIT_OUT 41
BAV99DW-X-G
SOT-363 5
MMBT2222A7F C4310 1 C4311 1
SOT23 FW_FET_LINEAR_LIMIT_IN 41 2
2 PLACE CLOSE TO COMPARITOR
0.01UF
10%
0.01UF
10%
3
R4310 PORT 0
50V 2 50V 2 0
1
1
C4302 R4307 X7R
402
6
X7R
402
4 1 2 1394B
0.01UF 20K
C 2
20%
16V
CERM
5%
1/16W
MF-LF
1

FL4310
5%
1/16W
OMIT_TABLE
CRITICAL
C
402 2 402 12-OHM-100MA J4300
TCM1210-4SM FWB-PL-K74-K75
SYM_VER-1
F-ANG-TH
86 40 FW_PORT0_TPB_N R4312 1 4
TPB(R)
0 86 FW_PORT0_TPB_F_N 1 TPB-
1 2
NOSTUFF 9
5%
86 40 FW_PORT0_TPB_P 1/16W 2 3 86 FW_PORT0_TPB_F_P 2 TPB+ VP
R4311 8
FL4311
12-OHM-100MA 1
0 2 7 SC/NC

R4304 D4302 TCM1210-4SM

SYM_VER-1 5% 6
100K 2 BAS40XG FW_PORT0_TPA_N 1 4
1/16W
FW_PORT0_TPA_F_N
86 3 TPA- VG
86 40
1 FW_FET_LINEAR_LIMIT_FB 1 3
FW_PORT0_TPA_R 5
5% NOSTUFF
1/16W SOT23 4 TPA+ TPA(R)
MF-LF 86 40 FW_PORT0_TPA_P 2 3 86 FW_PORT0_TPA_F_P
402
41 5 =PP12V_S0_FW 1 C4304 R4313 10
0.1UF 89 41 PP3V3_FW_ESD 1
0 2 11
SHIELD
PINS
10% NOSTUFF
16V CRITICAL
8 2 CRITICAL 5%
X7R-CERM
402
DP4311 DP4311
1/16W C4332 1 514-0724
V+ 0.001UF
U4300 BAV99DW-X-G BAV99DW-X-G 10%
50V
SOT-363 SOT-363 CERM 2
LM393 2 5 402
6 SOI-HF
5.1V 7 NC
R4305
D4303
SOT23
5
C4312 1
6
C4313 1
3

100K 2 0.01UF 1 0.01UF 4

41 FW_CURRENT_LIMIT 1 FW_CURRENT_LIMIT_R 3 1 FW_CURRENT_LIMIT_RD 2
1 FW_FET_LINEAR_LIMIT_OUT 41
10%
50V 2
X7R
10%
50V 2
X7R
R43351 1 C4335
5%
1/16W
41 FW_FET_LINEAR_LIMIT_IN 3
402 402 1M 0.1UF
1%
MF-LF MMBZ5231BXG 1/16W 10%
50V
402 GND
B 4
MF-LF
402 2
2 X7R
603-1 B
PLACE CLOSE TO COMPARATOR 1
R4306
C4305 1 200K
5%
2.2UF 1/16W
10% MF-LF
16V
X5R 2 2 402
603 TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

514-0656 1 K22/K23 PROD. FW J4300 CRITICAL METAL_IO

TABLE_5_ITEM

CRITICAL
514-0724 1 K74/K75 FW, PLASTIC, PD/NI J4300 PLASTIC_IO

ESD Rail
R4390
332
40 39 5 =PP3V3_FW_FWPHY 1 2 PP3V3_FW_ESD 41 89
VOLTAGE=3.3V
1% MIN_LINE_WIDTH=0.38 mm
1/16W MIN_NECK_WIDTH=0.25 mm
MF-LF
[ LATE VG NOTES ] 402
3

CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V CRITICAL
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP D4390
SOT23
MMBZ5227BLT1H
1

A SYNC_MASTER=MASTER SYNC_DATE=11/17/2009 A
PAGE TITLE

FIREWIRE CONNECTOR
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 41 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

SATA Activity LED

SILKSCREEN:HDD SATA PORT A0 FOR HDD
CRITICAL 17 5 =PP3V3_S0_SATALED
J4510
EP00-081-91 DEVELOPMENT
M-ST-SM C4510 1 2 SATA_HDD_R2D_C_P IN 17 84 R4599 1
1 0.01UF 10% 16V CERM 402 330
2 84 SATA_HDD_R2D_P C4511 1 2 SATA_HDD_R2D_C_N IN 17 84
5%
1/10W
MF-LF
3 84 SATA_HDD_R2D_N 0.01UF 10% 16V CERM 402
603
2
4 SATALED_R_L
5 84 SATA_HDD_D2R_C_N
C4515 DEVELOPMENT
6 84 SATA_HDD_D2R_C_P 1 2 SATA_HDD_D2R_N OUT 17 84
A

7 10% 16V CERM 402

DS4599
0.01UF GREEN-3.6MCD
C4516 1 2 SATA_HDD_D2R_P OUT 17 84
2.0X1.25MM-SM
K
0.01UF 10% 16V CERM 402
SILK_PART=SATA ACTIVE
17 PCH_SATALED_L SATALED_L
C 518S0251 MAKE_BASE=TRUE
C

SILKSCREEN:ODD SATA PORT A1 FOR SLIMLINE ODD

CRITICAL
J4520
EP00-081-91
M-ST-SM C4520 1 2 SATA_ODD_R2D_C_P IN 17 84
1 0.01UF 10% 16V CERM 402

2 84 SATA_ODD_R2D_P C4521 1 2 SATA_ODD_R2D_C_N IN 17 84

3 84 SATA_ODD_R2D_N 0.01UF 10% 16V CERM 402

4
5 84 SATA_ODD_D2R_C_N C4522 1 2 SATA_ODD_D2R_N OUT 17 84
6 84 SATA_ODD_D2R_C_P 0.01UF 10% 16V CERM 402

7 C4523 1 2 SATA_ODD_D2R_P OUT 17 84

10% 16V CERM 402
0.01UF

SILKSCREEN:ODD PWR

CRITICAL

B J4530
50293-0057N-001
B
M-ST-SM

1 =PP5V_S0_SATA 5
2
3
=PP3V3_S0_ODD 5

4
1 C4524 1 C4525
5
1UF
10%
1UF
10% R45201
6.3V
2 CERM
6.3V
2 CERM
33K
5%
402 402 1/10W
MF-LF
603
2
518S0792 SMC_ODD_DETECT 46 92

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

SATA Connectors
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

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IV ALL RIGHTS RESERVED 42 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL

U4601
=PP5V_S3_USB TPS2060 CRITICAL
2 7
43 5 IN
MSOP
OUT1
L4630
USB_EXTC_OC_L 8 FERR-250-OHM
34 OC1*
3 EN1* OUT2 6 89 PP5V_USB2_PORT3 1 2 89 PP5V_USB2_PORT3_F
5 VOLTAGE=5V SM
VOLTAGE=5V
35 USB_EXTD_OC_L OC2* MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
1
R4600
10K
4
EN2*

GND TPAD
USB/SMC DEBUG MUX MIN_NECK_WIDTH=0.2MM
1 C4630
MIN_NECK_WIDTH=0.2MM

(PUT CAP ON CONNECTOR SIDE) 0.01uF

5%
1/16W 1 9 5 =PP3V3_G3H_SMCUSBMUX 20%
16V

PORT 3
D
MF-LF
2 402
1 C4621
0.1UF
20%
1 C4631
0.1UF
20%
1 C4650
2 CERM
402 D
USB_PWR_ENA_L 10V 10V 0.1UF
2 CERM 2 CERM 20% OMIT_TABLE
CRITICAL 402 402 10V
2 CERM CRITICAL
1 C4605 1
C4606 402 J4630
0.1UF CRITICAL USB-MG4-K74-K75
20%
330UF CRITICAL F-ANG-TH
20%

9
10V 5
2 CERM
402
2 6.3V
POLY-TANT
CASE-D3L-SM VCC L4631
120-OHM-90MA
5 M+ DLP0NS
48 47 46 SMC_RX_L MOJOMUX Y+ 1 SYM_VER-1
VDD 1
VBUS
4 M- Y- 2 4 3 2
48 47 46 SMC_TX_L
U4650 85 USB_D_MUXED_N 85 USB_PORT3_N D-
3
DATA-
PI3USB102ZLE D+ DATA+
85 35 USB_EXTD_P 7 D+ TQFN GND 4
85 USB_D_MUXED_P 1 2 85 USB_PORT3_P GND
85 35 USB_EXTD_N 6 D-
USB_DEBUGPRT_EN_L 46 47
6
SEL=0: CHOOSE SMC
8 OE* SEL 10 SEL=1: CHOOSE USB
2 5 3 4
GND
Q4600 514-0732

NC
IO
NC
IO
3 2N7002 6 VBUS

3
SOT23-HF1
D
PRODUCTION 1 GND
R4651
63 PM_EN_USB_PWR 1 G S
1
0 2
2 PRODUCTION 5% D4630
R4652 1/16W
MF-LF
RCLAMP0502N
SLP1210N6
1
0 2
402
CRITICAL
5%
1/16W CRITICAL
MF-LF
402 L4620
FERR-250-OHM
C CRITICAL 89 PP5V_USB2_PORT2
VOLTAGE=5V
1 2 89 PP5V_USB2_PORT2_F
VOLTAGE=5V
C
MIN_LINE_WIDTH=0.6MM SM MIN_LINE_WIDTH=0.6MM
U4600 MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
TPS2060 CRITICAL
43 5 =PP5V_S3_USB 2 IN OUT1 7
L4610
1 C4620
MSOP
FERR-250-OHM (PUT CAP ON CONNECTOR SIDE) 0.01uF
USB_EXTA_OC_L 8 20%
34 OC1* 16V

PORT 2
89 PP5V_USB2_PORT1_F 2 CERM
3 OUT2 6 89 PP5V_USB2_PORT1 1 2
EN1* 402
5 VOLTAGE=5V SM VOLTAGE=5V
35 USB_EXTB_OC_L OC2* MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM OMIT_TABLE
4 MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
EN2* CRITICAL
1 C4610 J4620
GND TPAD
0.01uF USB-MG4-K74-K75

PORT 1
1 9 20% (PUT CAP ON CONNECTOR SIDE) CRITICAL F-ANG-TH
16V 5
1 C4603 1 C4611 2 CERM
402
L4621
120-OHM-90MA
0.1UF 0.1UF DLP0NS
CRITICAL 20% 20% SYM_VER-1
VDD 1
2 10V 10V
2 CERM VBUS
1 C4601 1
C4602 CERM
402 402 OMIT_TABLE 85 34 USB_EXTC_N 4 3 85 USB_PORT2_N D- 2
DATA-
0.1UF 330UF CRITICAL D+ 3
20% 20% DATA+
10V
2 CERM 2 6.3V
POLY-TANT J4610 85 34 USB_EXTC_P 1 2 85 USB_PORT2_P
GND 4
GND
402 CASE-D3L-SM USB-MG6-K74-K75
CRITICAL F-ANG-TH 6
5
L4611
120-OHM-90MA
DLP0NS 1
SYM_VER-1
VDD VBUS 514-0732
85 35 USB_EXTB_N 4 3 85 USB_PORT1_N D- 2 2 5 3 4
DATA-

NC
IO
NC
IO
D+ 3
DATA+ 6 VBUS
USB PORT POWER: 85 35 USB_EXTB_P 1 2 85 USB_PORT1_P
GND 4
GND
1 GND
EACH PORT IS HARDWARE CAPABLE OF 1.5A 2 5 3 4 6

B SOFTWARE WILL ALLOW 500 MA PER PORT, PLUS

NC
IO
NC
IO
1200 MA ’EXTRA’ POWER TO BE DISTRIBUTED TO APPROVED 6 VBUS
D4620
DEVICES ON A FIRST-COME, FIRST-SERVED BASIS 1 GND 514-0731 RCLAMP0502N
SLP1210N6
EXAMPLE: WIRED KEYBOARD WITH 2 500 MA PORTS = 1100 MA TOTAL ON ONE PORT CRITICAL
500 MA STANDARD + 600 MA ’EXTRA’ POWER D4610
IPHONE ’FAST’ CHARGING AT 1000 MA ON ANOTHER PORT RCLAMP0502N
500 MA STANDARD + 500 MA ’EXTRA’ POWER SLP1210N6
TABLE_5_HEAD

2 STANDARD PORTS AT 500 MA EACH CRITICAL PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
CRITICAL
TOTAL: 3100 MA (STILL 100 MA SPARE EXTRA POWER)
L4600 514-0672 2 K22/K23 PROD. USB J4600,J4610 CRITICAL METAL_IO
TABLE_5_ITEM

FERR-250-OHM TABLE_5_ITEM

1 2 514-0731 2 K74/K75 USB, PLASTIC, PD/NI J4600,J4610 CRITICAL PLASTIC_IO

IN S3, SOFTWARE MAY ALLOCATE UP TO 2000 MA TOTAL FOR CHARGING DEVICES 89 PP5V_USB2_PORT0 89 PP5V_USB2_PORT0_F
VOLTAGE=5V SM VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
TABLE_5_HEAD

1 C4600 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

0.01uF CRITICAL
TABLE_5_ITEM

PORT 0
20% (PUT CAP ON CONNECTOR SIDE) 514-0659 2 K22/K23 PROD. USB J4620,J4630 METAL_IO
16V
2 CERM TABLE_5_ITEM

402 514-0732 2 K74/K75 USB, PLASTIC, PD/NI J4620,J4630 CRITICAL PLASTIC_IO

OMIT_TABLE
CRITICAL
J4600
USB-MG6-K74-K75
CRITICAL F-ANG-TH
5
L4601
120-OHM-90MA
DLP0NS

A VDD 1
A
SYM_VER-1
VBUS
85 34 USB_EXTA_N 4 3 85 USB_PORT0_N D- 2 SYNC_MASTER=MASTER SYNC_DATE=11/30/2009
DATA-
D+ 3 PAGE TITLE
DATA+
85 34 USB_EXTA_P 1 2 85 USB_PORT0_P
GND 4
GND EXTERNAL USB CONNECTORS
DRAWING NUMBER SIZE
2 5 3 4
6
Apple Inc. 051-8337 D
NC
IO
NC
IO

6 VBUS REVISION

1 GND 514-0731
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
D4600 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
RCLAMP0502N I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
46 OF 110
SLP1210N6

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
CRITICAL IV ALL RIGHTS RESERVED 43 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

IR RECEIVER CONNECTOR CAMERA/ALS & BLUETOOTH (K37A) CONNECTOR

D CRITICAL
CRITICAL
D
J4780 CRITICAL
L4702
120-OHM-90MA
53261-8604 L4700
M-RT-SM
DLP0NS
SYM_VER-1 5 5 =PP5V_S3_CAMERA 220-OHM-1.4A
4 3 NET_PHYSICAL_TYPE=POWER 1 2 89 PP5V_S3_CAMERA_FLT
85 34 USB_IR_N USB_IR_L_N 0603 VOLTAGE=5V
92 85

85 USB_IR_L_P
1 1 C4700 C4701 1 MIN_LINE_WIDTH=0.6MM
85 34 USB_IR_P 1 2
92 2 10UF 0.1UF MIN_NECK_WIDTH=0.2MM
20% 20%
3
92 89 PP5V_S3_IR_FLT 2 6.3V
CERM
10V
CERM 2 J4700
VOLTAGE=5V 4 805-1 402 CRITICAL
=PP5V_S3_IR L4703 MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM L4701 50224-01311-001
5 220-OHM-1.4A 1
6 120-OHM-90MA
M-RT-SM
DLP0NS 14
NET_PHYSICAL_TYPE=POWER 1 2 C4781 SYM_VER-1

0603 2
1UF 518S0667 4 3
10% 6.3V
CRITICAL 402 CERM 1
85 34 USB_CAMERA_N
92 85 USB_CAMERA_L_N 2
85 34 USB_CAMERA_P 1 2 92 85 USB_CAMERA_L_P 3
CRITICAL 4
L4720
120-OHM-90MA
92 49 =SMB_ALS_SCL 5
DLP0NS
SYM_VER-1
92 49 =SMB_ALS_SDA 6
7
85 35 USB_BT_N 4 3
92 85 USB_BT_L_N 8
85 35 USB_BT_P 92 85 USB_BT_L_P 9
1 2 10
88 52 SNS_T1_DN2_DP3 11
88 52 SNS_T1_DP2_DN3 12
L4721 13
220-OHM-1.4A
C 5 =PP3V3_S3_BT
NET_PHYSICAL_TYPE=POWER
1
0603
2 PP3V3_S3_BT_FLT
VOLTAGE=3.3V
89
15
C
CRITICAL MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM1
C4720 1 C4721
10UF 0.1UF
20% 20%
2 6.3V
CERM 2 10V
CERM
805-1 402

LAZAURS SD CARD READER BOARD CONNECTOR

BACKUP TO CAESAR IV
SD_USB SD_USB
CRITICAL CRITICAL
L4750 J4750
120-OHM-90MA SM06B-SRKS-G-TB-HF
DLP0NS F-RT-SM
SYM_VER-1 7

B 85 35 USB_SDCARD_N
4 3
92 85 USB_SDCARD_L_N 1
B
85 35 USB_SDCARD_P 1 2
92 85 USB_SDCARD_L_P 2
3

CRITICAL 4

L4751 5
220-OHM-1.4A 6

45 5
=PP3V3_S3_SDCARD 1 2 PP3V3_S3_SDCARD_FLT 89

NET_PHYSICAL_TYPE=POWER 0603 VOLTAGE=3.3V 8

MIN_NECK_WIDTH=0.2MM
SD_USB MIN_LINE_WIDTH=0.6MM
518S0751
SDCARD_RESET_L
SD_USB
SD_USB
R4750 C4750 1

10K 1UF
1 2 10%
6.3V
CERM 2
1%
1/16W 402
MF-LF
402 6 SD_USB
D Q4710
2N7002DW-X-G
SOT-363
92 91 20 SDCARD_RESET 2 G S

1
R4751
1

10K
1%
1/16W
MF-LF SDCARD_PLT_RST_R_L
2 402
3 SD_USB
A D Q4710
2N7002DW-X-G SYNC_MASTER=MASTER SYNC_DATE=11/06/2009 A
SOT-363 PAGE TITLE
SDCARD_PLT_RST_L
91 27
5 G S
Internal USB Connections
4 DRAWING NUMBER SIZE

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IV ALL RIGHTS RESERVED 44 OF 92
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8 7 6 5 4 3 2 1

D D

37 36 5 =PP3V3_ENET_PHY

NOSTUFF
R48501
10K
5%
1/16W 44 5 =PP3V3_S3_SDCARD
MF-LF
402 2 BCM57765
BCM57765 CRITICAL
37 OUT SDCONN_CD_L R48001 J4800
10K 51281-2695
5% F-RT-SM
3 1/16W 28
MF-LF
BCM57765 402 2
D
Q4850 1
2N7002
SOT23-HF1 S G 1 SDCONN_DETECT 2 IMAC CARD DETECT SWITCH IS NORMALLY-CLOSED TO GND
3 (CARD INSERTED = OPEN)
2

C 37

86 37
OUT
BI
SDCONN_WP
SDCONN_DATA<7>
4
5
CAESAR-IV CARD DETECT IS PROGRAMMABLE, BUT A SILICON BUG
MAKES THE ACTIVE-HIGH CASE UNUSABLE.
C
86 37 SDCONN_DATA<6> 6
BI
7

86 37 SDCONN_DATA<1> 8
BI
9

86 37 SDCONN_DATA<0> 10
BI
11

86 37 SDCONN_CLK 86
47 SDCONN_CLK_R 12
IN
R4810 1 2 13
BCM57765 14
BCM57765
CRITICAL CRITICAL 15
=PP3V3_S0_SDCARD F4800 L4800 SDCONN_CMD 16
5
1.0AMP-32V FERR-120-OHM-3A 86 37 OUT
17
1 2 PP3V3_S0_SDCARD_F 1 2 PP3V3_S0_SDCARD_CONN
VOLTAGE=3.3V VOLTAGE=3.3V 86 37 SDCONN_DATA<3> 18
0603 BI
MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
0603 MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM 19
NET_SPACING_TYPE=POWER NET_SPACING_TYPE=POWER 20
MAX_NECK_LENGTH=3 MM MAX_NECK_LENGTH=3 MM 86 37 BI SDCONN_DATA<5>
21

86 37 SDCONN_DATA<2> 22
BI
23

86 37 SDCONN_DATA<4> 24
BI
25
BCM57765 BCM57765 26
C4800 1 1 C4801
1UF 10UF
10% 20% 27
6.3V 6.3V
CERM 2 2 X5R
402 603

B B

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

SD READER CONNECTOR
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

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IV ALL RIGHTS RESERVED 45 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
89 47 PP3V3_G3H_AVREF_SMC Peak/Ave/Standby = 2mA/1mA/5uA

47 5 =PP3V3_G3H_SMC Peak/Ave/Sleep/Standby = 40mA/25mA/20mA/50uA

SMC_EXCARD_PWR_EN
U4900 SMC_PM_G2_EN
B12 P10 H8S2117 P60 L13
D
47

47
OUT
OUT SMC_RSTGATE_L A13 P11 LGA-HF P61 K12 NC
OUT 3
C4902
22UF
1 1 C4903
0.1UF
1
C4904
0.1UF
20%
1
C4905
0.1UF
20%
1
C4906
0.1UF
20%
D
91 64 IN ALL_SYS_PWRGD_SMC A12 P12 (1 OF 3) P62 K11 NC
20%
6.3V
20%
10V 2
10V
2
10V
2
10V
2 2 CERM CERM CERM
RSMRST_PWRGD CERM CERM
91 64 IN B13 P13 P63 J12 NC 805 402 402 402 402

NC D11 P14 OMIT P64 K13 SMC_ADAPTER_EN OUT 18 47 PLACEMENT_NOTE=Place C4907 close to U4900 pin 13
PM_RSMRST_L C13 P15 P65 J10
91 63 OUT NC
CPUIMVP_VR_ON C12 P16 P66 J11 SMC_PROCHOT_3_3_L SMC_VCL
47 OUT IN 47
R4999 Peak/Ave/Standby= 2mA/1mA/5uA
91 24 18 OUT PM_PWRBTN_L D10 P17 P67 H12 SMC_BIL_BUTTON_L IN 47 4.7
1 2 89 PP3V3_G3H_SMC_AVCC
BDV_SRC_AUX_TERM_EN SMC_CPU_ISENSE
MIN_LINE_WIDTH=0.25 MM C4907 1

M12

H10

L11
47 OUT D13 P20 P70 N10 IN 50 88 5% MIN_NECK_WIDTH=0.20 MM
0.47UF

B1
M1

E1
1/16W VOLTAGE=3.4V
E11 P21 P71 M11 SMC_CPU_VSENSE MF-LF 10%
NC IN 50 88
402 6.3V
D12 P22 P72 L10 SMC_ANALOG_P72 C4920 1 CERM-X5R 2
NC IN 47
0.1UF AVCC VCC VCL AVREF
402
F11 P23 P73 N11 SMC_GPU_VSENSE 20%
NC IN 50
10V
R4909 1 1
R4901
NC E13 P24 P74 N12 SMC_DCIN_ISENSE IN 47 CERM
402
2
U4900 NC E5 10K 10K
NC E12 P25 P75 M13 SMC_PBUS_VSENSE IN 47
PLACEMENT_NOTE=Place R4999 close to U4900 pin 76
H8S2117 5%
1/16W
5%
1/16W
47 BDV_AV_MUX_SEL_SMC F13 P26 P76 N13 SMC_CPU_VTT_ISENSE 50 PLACEMENT_NOTE=Place C4920 close to U4900 pin 76 LGA-HF MF-LF MF-LF
OUT IN
402 402
NC E10 P27 P77 L12 SMC_CPU_VTT_VSENSE IN 50 (3 OF 3) 2 2

MD1 D1 SMC_MD1 IN 48
85 48 17 BI LPC_AD<0> A9 P30 P80 A7 SMC_WAKE_SCI_L OUT 17
MD2 H1 SMC_KBC_MDE
LPC_AD<1> D9 P31 P81 B6 SMC_RESET_L D3 RES* OMIT
85 48 17 BI NC 91 48 47 IN
85 48 17 BI LPC_AD<2> C8 P32 P82 C7 PM_CLKRUN_L OUT 14 18 48 91
88 47 SMC_XTAL A3 XTAL
85 48 17 BI LPC_AD<3> B7 P33 P83 D5 LPC_PWRDWN_L IN 18 48 SMC_NMI
88 47 SMC_EXTAL A2 EXTAL NMI E3 IN 48
85 48 17 IN LPC_FRAME_L A8 P34 P84 A6 SMC_TX_L OUT 43 46 47 48

91 27 IN SMC_LRESET_L D8 P35 P85 B5 SMC_RX_L IN 43 46 47 48

85 27 IN LPC_CLK33M_SMC D7 P36 P86 C6 (OC) SMB_MGMT_CLK BI 49

LPC_SERIRQ D6 H3 SMC_TRST_L
48 17 BI P37 ETRST IN 48
P90 J4 SMC_ONOFF_L IN 47

D4 P40 P91 G3 SMC_BC_ACOK AVSS L9 NOSTUFF

NC IN 47
1
SMC_P41 A5 P41 P92 H2 VSS R4902 1
R4998 1
R4903
47
NC
C 49 BI SMB_MGMT_DATA (OC) B4 P42 P93 G1 PM_SLP_S3_L IN 5 18 26 36 47 63 64 81 91
10K
5%
1/16W
5%
10K
5%
0
C

D2
L3
F10
B11
C5
47 OUT SMS_ONOFF_L A1 P43 P94 H4 BDV_AUXP_STATE IN 47 XW4900 MF-LF
1/16W
MF-LF
1/16W
MF-LF
SM 402
NC C2 P44 P95 G4 PM_SLP_S45_L IN 47
2
2 402 2 402
2 1

NC B2 P45 P96 F4 PM_CLK32K_SUSCLK IN 8 85 91

47 OUT SMC_GFX_THROTTLE_L C1 P46 P97 F1 (OC) SMB_0_S0_DATA BI 49

NC C3 P47

48 47 46 43 OUT SMC_TX_L G2 P50

GND_SMC_AVSS 47 50 88
48 47 46 43 IN SMC_RX_L F3 P51
49 BI SMB_0_S0_CLK (OC) E4 P52

BDV_AUXN_STATE
U4900 BDV_DP_VIDEO_ON
47 IN N3 PA0 H8S2117 PE0 K1 IN 47

17 14 OUT SPI_DESCRIPTOR_OVERRIDE_L (OC) N1 PA1 LGA-HF PE1 J3 SMC_TCK IN 47 48

91 27 18 OUT PM_SYSRST_L (OC) M3 PA2 (2 OF 3) PE2 K2 SMC_TDI IN 47 48

47 43 OUT USB_DEBUGPRT_EN_L (OC) M2 PA3 PE3 J1 SMC_TDO OUT 47 48

47 IN MEM_EVENT_A_L (OC) N2 PA4 OMIT PE4 K4 SMC_TMS IN 47 48

47 IN MEM_EVENT_B_L (OC) L1 PA5 PF0 K5 G3_POWERON_L IN 47

47 BI SYS_ONEWIRE (OC) K3 PA6

PF1 N5 SMC_SYS_LED OUT 47
91 18 14 OUT PM_BATLOW_L (OC) L2 PA7
PF2 M6 SMC_LID OUT 47

NC B8 PB0 PF3 L5 NC
B 20 14

92 42
OUT
IN
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
C9
B9
PB1
PB2
PF4
PF5
M5
N4
NC
BDV_PWM_OR_SINK_TERM OUT 47
B
SMC_PB3 (See below) A10 PB3 PF6 L4
47
NC
SMC_HDD_OOB_TEMP C10 PB4 PF7 M4
88 51 IN NC
NC B10 PB5
PG0 M8 NC
47 IN BDV_HPD_STATE C11 PB6
PG1 N7 =SMC_SMS_INT IN 47 NOTE: SMS Interrupt can be active high or low, rename net accordingly.
47 IN SMC_GFX_OVERTEMP_L A11 PB7
PG2 K8 (OC) SMB_BSA_DATA BI 49 If SMS interrupt is not used, pull up to SMC rail.
53 OUT SMC_FAN_0_CTL G11 PC0 PG3 K7 (OC) SMB_BSA_CLK BI 49

53 OUT SMC_FAN_1_CTL G13 PC1 PG4 K6 (OC) SMB_A_S3_DATA BI 49

NC F12 PC2 PG5 N6 (OC) SMB_A_S3_CLK BI 49

54 OUT SMC_FAN_3_CTL H13 PC3 PG6 M7 (OC) SMB_B_S0_DATA BI 49

53 IN SMC_FAN_0_TACH G10 PC4 PG7 L6 (OC) SMB_B_S0_CLK BI 49

53 IN SMC_FAN_1_TACH G12 PC5

PH0 E2 SMC_PROCHOT OUT 47
NC H11 PC6
PH1 F2 SMC_THRMTRIP OUT 47
54 IN SMC_FAN_3_TACH J13 PC7
PH2 J2 NC
SMC_CPU_1V5_VSENSE M10 PD0 PH3 A4
88 50 IN NC
SMC_GPU_ISENSE N9 PD1 PH4 B3
50 IN NC
47 IN SMC_ANALOG_PD2 K10 PD2 PH5 C4 NC
47 IN SMC_ANALOG_PD3 L8 PD3
88 50 IN SMC_CPU_1V5_ISENSE M9 PD4
47 IN SMC_ANALOG_PD5 N8 PD5
47 IN SMC_ANALOG_PD6 K9 PD6
47 IN SMC_ANALOG_PD7 L7 PD7

A SMC_PB3: SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A

PAGE TITLE
SMC_IG_THROTTLE_L for MG systems.
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
SMC
DRAWING NUMBER SIZE

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SMC Reset "Button", Supervisor & AVREF Supply MISC. SIGNAL ALIASES
47 46 SMC_GFX_OVERTEMP_L MXM_ALERT_L 75 47 46 5
=PP3V3_G3H_SMC
=PP3V3_G3H_SMC MAKE_BASE=TRUE
47 46 5

5 =PPVIN_S5_SMCVREF 46 SMC_GFX_THROTTLE_L MXM_PWR_LEVEL SMC_ONOFF_L R5032 10K 1 2

75 47 46
MAKE_BASE=TRUE
48 46 43 SMC_TX_L R5035 10K 1 2
5% 1/16W MF-LF 402
CPUIMVP_VR_ON SMC_DELAYED_PWRGD 5% 1/16W MF-LF 402
46
MAKE_BASE=TRUE
64 91
48 46 43 SMC_RX_L R5036 100K 1 2
1 5% 1/16W MF-LF 402
R5037 2.0K
R5000 SYS_ONEWIRE
D

3
1 2
C5000 1 46

D 0.47UF
10%
6.3V
V+
U5010
VIN
5%
1K
1/16W
48 46

48 46
SMC_TMS
SMC_TDO
R5039
R5040
10K
10K
1

1
2

2
5%

5%
1/16W

1/16W
MF-LF

MF-LF
402

402

SILK_PART=SMC RESET CERM-X5R 2

VREF-3.3V-VDET-3.0V
MF-LF
SMC_TDI R5041 10K 5% 1/16W MF-LF 402
402 2 402 48 46 1 2
5% 1/16W MF-LF 402
DEVELOPMENT
NC 6 MR1*
DFN
RESET* 5 SMC_RESET_L 48 46 SMC_TCK R5042 10K 1 2

S5000 NC 7
MR2*
SN0903048
(IPU)

(IPU)
OUT 46 48 91
46 SMC_BIL_BUTTON_L R5092 10K 1 2
5% 1/16W MF-LF 402

NTC020-CC1J-B260T PP3V3_G3H_AVREF_SMC 46 89
46 SMC_BC_ACOK R5047 10K 1 2
5% 1/16W MF-LF 402

1 SM 2 SMC_MANUAL_RST_L 4 8 MIN_LINE_WIDTH=0.4 mm 5% 1/16W MF-LF 402

DELAY REFOUT MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V 46 18 SMC_ADAPTER_EN R5049 10K 1 2
THRM R5098 10K 5% 1/16W MF-LF 402
GND PAD 46 43 USB_DEBUGPRT_EN_L 1 2

C5001 1 46 =SMC_SMS_INT SMC_SMS_INT R5091 10K 1 2

5% 1/16W MF-LF 402

9
0.01UF C5025 1 1 C5026 46 SMC_LID
MAKE_BASE=TRUE
R5087 10K 1 2
5% 1/16W MF-LF 402

3 4
10%
16V
CERM 2
10uF
20%
6.3V
0.01UF
10%
16V
UNUSED PORT 7 ANALOG SENSORS 46 G3_POWERON_L R5086 10K 1 2
5%

5%
1/16W

1/16W
MF-LF

MF-LF
402

402
402 X5R 2 2 CERM BDV_AUXP_STATE R5060 100K 1 2
46
603 402
BDV_AUXN_STATE 5% 1/16W MF-LF 402
46 R5061 100K 1 2

GND_SMC_AVSS BDV_HPD_STATE R5062 100K 1 2

5% 1/16W MF-LF 402
46 50 88 46
MIN_LINE_WIDTH=0.4 mm 5% 1/16W MF-LF 402
MIN_NECK_WIDTH=0.1 mm
MR1* and MR2* must both be low to cause manual reset. VOLTAGE=0V

Used on mobiles to support SMC reset via keyboard.

NOTE: Internal pull-ups are to VIN, not V+. 46 SMC_ANALOG_P72

50 47 5
=PP3V3_S0_SMC
46 SMC_DCIN_ISENSE R5002
10K
46 SMC_PBUS_VSENSE SMC_UNUSED_ADC_PORT7 2 1
MAKE_BASE=TRUE
5% 47 46 SMC_GFX_OVERTEMP_L R5099 10K 1 2
1/16W 5% 1/16W MF-LF 402
MF-LF
402
SMC Crystal Circuit
BDV_DP_VIDEO_ON R5063
C C5020
22PF 91 81 64 63 46 36 26 18 5
46

PM_SLP_S3_L R5094
100K
100K
1

1
2

2
5%

5%
1/16W

1/16W
MF-LF

MF-LF
402

402
C
88 46 SMC_XTAL 1 2
UNUSED PORT D ANALOG (INTERNAL PULLUPS) PM_SLP_S5_L R5090 100K 1 2
5% 1/16W MF-LF 402
5%
91 18 PM_SLP_S4_L R5089 100K 1 2
CRITICAL 5% 1/16W MF-LF 402
1
50V
46 PM_SLP_S45_L
Y5020 CERM
20.000M
SM-4
402
POWER BUTTON 46 SMC_ANALOG_PD2 NC_SMC_ANALOG_PD2
2
C5021 SILK_PART=PWR BTN MAKE_BASE=TRUE NO_TEST=TRUE
22PF SMC_ANALOG_PD3 NC_SMC_ANALOG_PD3
88 46 SMC_EXTAL 1 2 J5010 46
MAKE_BASE=TRUE NO_TEST=TRUE
53261-8602 SMC_ANALOG_PD5 NC_SMC_ANALOG_PD5
5%
50V
CERM
L5010
M-RT-SM
3 518S0665
46

46 SMC_ANALOG_PD6
MAKE_BASE=TRUE
NC_SMC_ANALOG_PD6
NO_TEST=TRUE
SMC PROCHOT 3.3V LEVEL SHIFTING
402 FERR-220-OHM MAKE_BASE=TRUE NO_TEST=TRUE

1 2 POWER_BUTTON_L 1 46 SMC_ANALOG_PD7 NC_SMC_ANALOG_PD7 =PP3V3_S0_SMC_LS

51 47 5
MAKE_BASE=TRUE NO_TEST=TRUE
0402 2
R5078 1
65 15 12 10 5 =PPVTT_S0_CPU 470
4 5%
SMC_ONOFF_R_L 1/16W

DEVELOPMENT CRITICAL UNUSED TP/NC ALIASES TO CPU R5070 1

3.3K
MF-LF
402 2 SMC_PROCHOT_3_3_L
TO SMC

S5010 5%
1/16W
OUT 46

NTC020-CC1J-B260T R5010 SMC_ONOFF_L MF-LF 3

1K OUT 46 47 402 2
1 SM 2 1 2 46 SMC_EXCARD_PWR_EN TP_SMC_EXCARD_PWR_EN 10 BI CPU_PROCHOT_L R5071 CPU_PROCHOT_BUF 5
Q5077
MAKE_BASE=TRUE
3.3K MMDT3904-X-G
5%
1/16W 46 SMS_ONOFF_L TP_SMS_ONOFF_L 1 2 CPU_PROCHOT_L_R SOT-363-LF
MF-LF MAKE_BASE=TRUE
402
1
C5010 SMC_RSTGATE_L TP_SMC_RSTGATE_L SMC_PROCHOT
5% 6 4

0.1UF 46
MAKE_BASE=TRUE
46 IN 3
1/16W
MF-LF 2
Q5077
20%
10V
402 MMDT3904-X-G
3 4 2 CERM 46 SMC_P41 TP_SMC_P41 FROM SMC D
Q5095 SOT-363-LF
402 MAKE_BASE=TRUE
2N7002DW-X-G 1
46 SMC_SYS_LED TP_SMC_SYS_LED 5
SOT-363
MAKE_BASE=TRUE G S

B SILK_PART=SYS POWER
46 SMC_PB3 TP_SMC_PB3
MAKE_BASE=TRUE 4
B

SMC & MXM THERMTRIP LEVEL SHIFTING

MXM
51 47 5 =PP3V3_S0_SMC_LS
R5018
MXM MXM 0
BDV_PWM_OR_SINK_TERM TP_BDV_PWM_OR_SINK_TERM 1 1
MXM_THRMTRIP_L 1 2 PM_THRMTRIP_L
46 10 20 91
MAKE_BASE=TRUE R5068 R5069 5%
OUT
10K 3.3K 6 PULL-UP ON PAGE 14
MEM_EVENT 46 BDV_SRC_AUX_TERM_EN TP_BDV_SRC_AUX_TERM_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
5%
1/16W D
3 MXM
Q5096
1/16W
MF-LF
402 D Q5095
46 BDV_AV_MUX_SEL_SMC TP_BDV_AV_MUX_SEL_SMC MF-LF
2N7002DW-X-G
MAKE_BASE=TRUE 2 402 2
402 2N7002DW-X-G SOT-363
SOT-363 2 G S
MXM_THRMTRIP 5 G S
6
MXM 1
30 5 =PPSPD_S0_MEM_A 50 47 5 =PP3V3_S0_SMC 4
TIES OFF AUDIO DETECT CIRCUIT WHEN BIDIVI IS NOT USED D Q5096
BDV_AV_MUX_SEL 2N7002DW-X-G
R50801 R50851 61 GND_AUDIO_CODEC 56 57 61 62 SOT-363
75 IN MXM_OVERT_L 2 G S
10K 10K MAKE_BASE=TRUE
46 IN SMC_THRMTRIP
5% 5% FROM MXM
1/16W 1/16W 1 FROM SMC
MF-LF MF-LF
402 2 402 2

FROM DIMMS
31 30 IN MEM_EVENT_L
MEM_EVENT_B_L 46
TO SMC

A 46 MEM_EVENT_A_L
MAKE_BASE=TRUE SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
TO/FROM SMC PAGE TITLE

SMC Support
DRAWING NUMBER SIZE

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IV ALL RIGHTS RESERVED 47 OF 92
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8 7 6 5 4 3 2 1

LPC+SPI Connector
FRANK CONNECTOR
CRITICAL
LPCPLUS
J5100
55909-0374
D 5 =PP3V3_G3H_LPCPLUS 31
M-ST-SM
32 D
5 =PP5V_S0_LPCPLUS
1 2 LPC_CLK33M_LPCPLUS IN 27 85

85 46 17 BI LPC_AD<0> 3 4 LPC_AD<2> BI 17 46 85

85 46 17 BI LPC_AD<1> 5 6 LPC_AD<3> BI 17 46 85
7 8

85 48 IN SPI_ALT_MOSI 9 10 SPIROM_USE_MLB OUT 20 48 85

85 48 OUT SPI_ALT_MISO 11 12 SPI_ALT_CLK IN 48 85

85 46 17 IN LPC_FRAME_L 13 14 SPI_ALT_CS_L IN 48 85

91 46 18 14 OUT PM_CLKRUN_L 15 16 LPC_SERIRQ BI 17 46

47 46 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 18 46

91 27 IN DEBUG_RESET_L 19 20 SMC_TDI OUT 46 47

47 46 OUT SMC_TDO 21 22 SMC_TCK OUT 46 47

46 IN SMC_TRST_L 23 24 SMC_RESET_L OUT 46 47 91

46 OUT SMC_MD1 25 26 SMC_NMI OUT 46

47 46 43 IN SMC_TX_L 27 28 SMC_RX_L OUT 43 46 47

29 30 LPCPLUS_GPIO OUT 20

33 34

516S0573

C C
Alternate SPI ROM Support
48 5 =PP3V3_S5_LPCPLUS
55 5 =PP3V3_S5_ROM
=PP3V3_S5_LPCPLUS
1 C5144 48 5

R51441 0.1UF
20%
20K LPCPLUS 2 10V R5140 1
5% CERM 100K
1/16W 402 5%
MF-LF 1/16W
402 2 U5100 MF-LF
402 2
NC7SB3157P6XG
PATH=I96
SC70
85 55 OUT SPI_MLB_CS_L 1 B1 SEL 6 SPIROM_USE_MLB 20 48 85
MAKE_BASE=TRUE
1
2 GND VCC 5 LPCPLUS
0 R5145
SPI_ALT_CS_L 3 4 85 SPI_CS0_L 1
0 2 SPI_CS0_R_L IN 17 85
85 48 OUT
B0 A
5% PLACEMENT_NOTE=Place near U1400
Pull-up on debug card VER 1 1/16W
MF-LF
CRITICAL 402

PRODUCTION
R5146
B 1
0 2
B
5% PLACEMENT_NOTE=PLACE NEXT TO U5100
1/16W
MF-LF
402

SPI Bus Series Resistance Option

LPCPLUS
R5156
0
85 48 OUT SPI_ALT_CLK 1 2 SPI_CLK_R IN 17 55 85

PLACEMENT_NOTE=Place next to R6150 5%

1/16W
LPCPLUS
MF-LF
402 R5157
0
85 48 OUT SPI_ALT_MOSI 1 2 SPI_MOSI_R IN 17 55 85

LPCPLUS 5%
1/16W
PLACEMENT_NOTE=Place next to R6152
MF-LF
R5158 402
0
85 48 IN SPI_ALT_MISO 1 2 SPI_MISO OUT 17 55 85

PLACEMENT_NOTE=Place next to R6105 5%

A 1/16W
MF-LF
402 SYNC_MASTER=K23F SYNC_DATE=11/30/2009 A
PAGE TITLE

LPC+SPI Debug Connector

DRAWING NUMBER SIZE

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IV ALL RIGHTS RESERVED 48 OF 92
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8 7 6 5 4 3 2 1
PCH "SMBUS" CONNECTIONS PCH "SML 0" CONNECTIONS SMC "A" SMBus Connections
NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE
BUS A CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K74 CHOOSES 1
=PP3V3_S0_SMBUS =PP3V3_S0_SMBUS
49 5 49 5
5 =PP3V3_S3_SMBUS_SMC_A_S3

PCH R5208
1 1
R5209 MEMORY A DIMMS PCH R5202
1 1
R5203 SMC R52701 1
R5271 ALS
2.2K 2.2K 8.2K 8.2K 4.7K 4.7K
U1800 5% 5% J3100-A/B U1800 5% 5% U4900 5% 5% (WRITE: 0X52 READ: 0X53)
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
(MASTER) MF-LF MF-LF (Write: 0xA0 Read: 0xA1) (MASTER) MF-LF MF-LF (MASTER) MF-LF MF-LF
402
2 2
402 402
2 2
402 402 2 2 402
(WRITE: 0XA2 READ: 0XA5)

D 88 17 SMBUS_PCH_CLK
MAKE_BASE=TRUE
=I2C_SODIMMA_SCL 30 88 17 SML_PCH_0_CLK
MAKE_BASE=TRUE
46 SMB_A_S3_CLK 88 SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
=SMB_ALS_SCL 44 92
D
88 17 SMBUS_PCH_DATA =I2C_SODIMMA_SDA 30 88 17 SML_PCH_0_DATA 46 SMB_A_S3_DATA 88 SMBUS_SMC_A_S3_SDA =SMB_ALS_SDA 44 92
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MEMORY B DIMMS
J3200-A/B
(WRITE: 0XA4 READ: 0XA3)
(WRITE: 0XA6 READ: 0XA7) SMC SLAVE SMBUS "2" CONNECTIONS
=I2C_SODIMMB_SCL 31 USES INTERNAL SMC CONTROLLER CHANNEL 2 ONLY

=I2C_SODIMMB_SDA 31 5 =PP3V3_S0_SMBUS_SMC_BSA

MIKEY SMC R5280 1

1
R5281 DISPLAY TCON
4.7K 4.7K DP RX MASTER FOR MCCS
U6806 U4900 5% 5%
SMC SLAVE ADDRESS TBD
SMC "B" SMBus Connections
1/16W 1/16W
(WRITE: 0X72 READ: 0X73) (SLAVE) MF-LF MF-LF
402 2 2 402
BUS B CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K74 CHOOSES 0
=I2C_AUDIO_SCL 62 46 SMB_BSA_CLK 88 SMBUS_SMC_BSA_SCL =SMB_DP_TCON_SCL 78
MAKE_BASE=TRUE
5 =PP3V3_S0_SMBUS_SMC_B_S0
=I2C_AUDIO_SDA 62 46 SMB_BSA_DATA 88 SMBUS_SMC_BSA_SDA =SMB_DP_TCON_SDA 78
MAKE_BASE=TRUE

AC/DC PS TEMPS
R5260 1
1 EMC1403-[1,2]: ACDC THRU J600
SMC R5261
XDP CK505 U4900
2.2K
5%
2.2K
5%
(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)
J2500 U2600 1/16W 1/16W 3 SENSE POINTS - PRIMARY, SECONDARY, AMB
(MASTER) MF-LF MF-LF
(MASTER) (WRITE: 0XD2 READ: 0XD3) 402
2 2
402

C 24 =SMBUS_XDP_SCL =SMBUS_CK505_SCL 25
46

46
SMB_B_S0_CLK

SMB_B_S0_DATA
88 SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
88 SMBUS_SMC_B_S0_SDA
=SMB_ACDC_SCL

=SMB_ACDC_SDA
5

5
SMC "MANAGEMENT" SMBUS (BUS 1)
USES INTERNAL SMC CONTROLLER CHANNEL 1 ONLY
C
24 =SMBUS_XDP_SDA =SMBUS_CK505_SDA 25 MAKE_BASE=TRUE

5 =PP3V3_S0_SMBUS_SMC_MGMT

AC/DC PS POWER
MEMORY VREF DAC INA219: ACDC THRU J600
R5290 1
1
U2900 (WRITE: 0X80, READ: 0X81)) SMC R5291 DP TX REDRIVER
4.7K 4.7K
(WRITE: 0X98 READ: 0X99) OUTPUT VOLTAGE, CURRENT, POWER U4900 5% 5% U9180
1/16W 1/16W
(MASTER) MF-LF MF-LF (WRITE: 0X9C, READ: 0X9D)
402 2
=I2C_VREFDACS_SCL 2 402
28

46 SMB_MGMT_CLK 88 SMBUS_SMC_MGMT_SCL =I2C_DP_DRV_SCL 79

=I2C_VREFDACS_SDA 28 MAKE_BASE=TRUE

46 SMB_MGMT_DATA 88 SMBUS_SMC_MGMT_SDA =I2C_DP_DRV_SDA 79

MAKE_BASE=TRUE

MEMORY VREF MARGIN

U2910
(WRITE: 0X30 READ: 0X31)

=I2C_PCA9557D_SCL
SMC "0" SMBus Connections
28 USES INTERNAL SMC CONTROLLER CHANNEL 0 ONLY

=I2C_PCA9557D_SDA 28 5 =PP3V3_S0_SMBUS_SMC_0_S0

Also reserve 0x56 and 0x32 per spec

SMC R5250 1
1
R5251 MXM TEMP
4.7K 4.7K GPU ON CARD - J8400
U4900
PCH "SML 1" CONNECTIONS
5% 5%
1/16W 1/16W NV INSIDE (WRITE: 0X9E READ: 0X9F)
(MASTER) MF-LF MF-LF MXM CARD (WRITE: 0X98 READ: 0X99)

B 46 SMB_0_S0_CLK 88 SMBUS_SMC_0_S0_SCL
402 2 2 402

=SMB_MXM_THRM_SCL 75
B
49 5 =PP3V3_S0_SMBUS MAKE_BASE=TRUE

46 SMB_0_S0_DATA 88 SMBUS_SMC_0_S0_SDA =SMB_MXM_THRM_SDA 75

MAKE_BASE=TRUE
NOSTUFF NOSTUFF
R5204 1
1
PCH R5205
8.2K 8.2K
U1800 5%
1/16W
5%
1/16W
HEATSINK TEMPS
(SLAVE) MF-LF MF-LF

(WRITE: 0X88 READ: 0X89)

402 2 2 402 R5206
0
88 17 SML_PCH_1_CLK 1 2
MAKE_BASE=TRUE
5%
EMC1414: U5500
88 17 SML_PCH_1_DATA
MAKE_BASE=TRUE
1/16W
MF-LF R5207 (WRITE: 0XD8 READ: 0XD9)
402 0
1 2 =SMB_SNS1_SCL 52

5%
1/16W =SMB_SNS1_SDA 52
MF-LF
402

AMB,ODD,SKIN TEMPS
TMP423: U5550
(WRITE: 0X9A READ: 0X9B)
=SMB_SNS2_SCL 52

=SMB_SNS2_SDA 52

A SYNC_MASTER=DAVE SYNC_DATE=01/07/2010 A
PAGE TITLE

PCIE MINI-CARD SMBus Connections

X18 WI-FI MODULE DRAWING NUMBER
051-8337
SIZE
D
TMP106: J3400
Apple Inc. REVISION
(WRITE: 0X90 READ: 0X91)
R
A.0.0
=SMB_MINI_SCL
NOTICE OF PROPRIETARY PROPERTY: BRANCH
33
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
=SMB_MINI_SDA 33 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
52 OF 110

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IV ALL RIGHTS RESERVED 49 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
CPU 1.5V CURRENT SENSE CPU 1.5V VOLTAGE SENSE CPU Voltage Sense / Filter
PP1V5_CPU_MEM
OMIT
5 89
R5359
IMAX = 6A 4.53K
R5300 89 65 12 CPU_VCC_PKG_SENSE_P 1 2 SMC_CPU_VSENSE OUT 46 88
0.002 CPU_1V5_SENSE 1%
1% 1/16W 1
C5359
1/4W
MF-LF R5302 MF-LF
402 0.22UF
PP1V5_S0_FET 1206 4.53K2 SMC_CPU_1V5_VSENSE
20%
73 5 1 2 1 46 88 PLACE R CLOSE TO CPU 2
6.3V
X5R
3 4 1% OMIT 402
1/16W
MF-LF
402
1 C5302 GND_SMC_AVSS 46 47 50 88
=PP3V3_S0_SMC 5 47 0.22UF PLACE C CLOSE TO SMC
20%
6.3V
2 X5R
CPU_1V5_SENSE 402
1 C5300 GND_SMC_AVSS
0.22UF 46 47 50 88
20% CPU CURRENT SENSE AMP & FILTER

3
6.3V
2 X5R
V+ 402 CPU_1V5_SENSE
U5300 R5301 R5363
INA210 4.53K2 1
21K 2
SENSE_CPU_1V5_N 5 IN- SC70 6 SMC_CPU_1V5_ISENSE_R 1 SMC_CPU_1V5_ISENSE 88 SNS_PS_CPU_ISNS
88 OUT 88 46 88

1% 1%
CPU_1V5_SENSE 1/16W 1/16W
MF-LF
C5360
88 SENSE_CPU_1V5_P 4 IN+ REF 1 MF-LF
402 402 0.01UF
OMIT 5 =PP5V_S0_ISENSE 1 2
GND 1 C5301 20%
353S2073 0.22UF 16V

2
20% CERM PCB: PLACE R5364, C5362 WITHIN 1" OF SMC (U4900)
GAIN = 200V/V 6.3V 402
2 X5R

C 402
GND_SMC_AVSS 46 47 50 88 VR_CPU_IMON 1
R5360
10K 2 VR_ISNS_CPU_P 1 5
U5360
OPA348 AMPLIFIED AND FILTERED ISNS TO SMC
C
89 65 IN 88
SC70-5 R5364
1%
1/16W 4 1
5.1K 2 SMC_CPU_ISENSE
OUT 46 88
IMAX = 0.9V MF-LF
402 3
5%
88 VR_ISNS_CPU_N CRITICAL 1/16W 1 C5362
TABLE_5_HEAD

2 MF-LF
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION IMAX = 2.79V 402 0.22UF
10%
2 6.3V
TABLE_5_ITEM

CERM-X5R
104S0018 1 RES,2 MILLIOHM,1206 R5300 CPU_1V5_SENSE 1
R5361 402
10K
TABLE_5_ITEM

101S0414 1 RES,0 OHM,1206,20 MILLIOHM MAX R5300 PRODUCTION 1% GND_SMC_AVSS 46 47 50 88

TABLE_5_ITEM 1/16W
132S0080 2 CAP,0.22UF,402 C5301,C5302 CPU_1V5_SENSE MF-LF
TABLE_5_ITEM
2 402
116S0004 2 RES,0 OHM,402 C5301,C5302 PRODUCTION

MXM PWRSRC CURRENT & VOLTAGE SENSE

CPU VTT CURRENT SENSE CRITICAL PPV_S0_MXM_PWRSRC
MAKE_BASE=TRUE
89

R5330
B 0.015
1%
=PPV_S0_MXM_PWRSRC 74 B
IMAX = 30A
1W
MF R5331
1
2512
2
IMAX = 4A 18.2K2 SMC_GPU_VSENSE
5 =PPV_S0_MXM_PWR 1 46
3 4 1%
1/16W
SENSE_MXM_N_R
MF-LF
402
R5332
1 1 C5331
6.04K 0.22UF
R5320 1% 20%
6.3V
4.53K2 SMC_CPU_VTT_ISENSE
1/16W
MF-LF 2 X5R
CPUVTT_IMON 1
68

1%
46
R5333
1
2 402 402
1/16W 100 GND_SMC_AVSS 46 47 50 88
MF-LF 5%
402 1/16W
MF-LF
2 402
1 C5320 C5332
0.22UF 0.33UF
20%
6.3V 1 2
2 X5R CRITICAL
402
GND_SMC_AVSS 10%
46 47 50 88 6.3V
CERM-X5R
402
U5330
MAX9938
UCSP-2
88 SENSE_MXM_P A1 RS+
OUT B2 SMC_GPU_ISENSE
46

88 SENSE_MXM_N A2 RS-

GND 1 C5330
R5321 0.1UF

B1
20%
4.53K2 SMC_CPU_VTT_VSENSE 10V
2 CERM
89 5 PPVTT_S0 1 46
402
1% GND_SMC_AVSS
1/16W 46 47 50 88

A MF-LF
402
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
1 C5321 PAGE TITLE
0.22UF
20%
6.3V
CPU/GPU POWER SENSE
2 X5R DRAWING NUMBER SIZE
402
GND_SMC_AVSS Apple Inc. 051-8337 D
46 47 50 88
REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
53 OF 110

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 50 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

HDD OUT OF BAND TEMPERATURE SENSING LEVEL SHIFTING

5 =PP12V_S0_SENSE

R54001
64.9K
1%
1/16W
MF-LF
402
2

C 51 47 5 =PP3V3_S0_SMC_LS
R54011
10K
1%
C5400
0.1UF
1

=PP3V3_S0_SMC_LS 5 47 51
C
20%
1/16W 16V
MF-LF CERM 2
402
2 603
1
1 R5405
R5402 1K
FROM DRIVE: 62K 5%
SILK_PART=HDD TEMP 5% CRITICAL 1/16W
LOW: -0.3V TO 0.5V 1/16W MF-LF
J5400 HIGH: 2.0V TO 3.6V
MF-LF
2 402
8 U5400 2 402
53780-8602 HDD_OOB_1V60_REF 2 LM393
M-RT-SM
SOI-HF
3 L5400 V+
1 SMC_HDD_OOB_TEMP
FERR-220-OHM R5403 46 88

1 1 2 3.3K 3 GND
92 88 HDD_OOB_TEMP_FILT 88 HDD_OOB_TEMP 1 2 88 HDD_OOB_TEMP_R
2 0402 5% 4
1/16W
R5404 1 MF-LF
402
4 200K
5%
1/16W
CRITICAL MF-LF
402 2
518S0698

Drive active = valid signal protocol

Drive asleep = HDD drives HDD_OOB_TEMP low
Drive disconnected = pulled high

Cannot pull low because some drives use this bit to

determine 1.5 Gbps vs. 3.0 Gbps SATA

Must pull high to 2.5V for compatibility with all drives

B B

CRITICAL

8 U5400
SPARE 6 LM393
V+ SOI-HF
7

5 GND
51 47 5 =PP3V3_S0_SMC_LS
4

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

HDD TEMP SENSE

DRAWING NUMBER SIZE

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8 7 6 5 4 3 2 1

REMOTE HEATSINK SENSORS

D D
REMOTE SKIN & ODD THERMAL SENSORS

=PP3V3_S0_TSENS 5 52

88 52 SNS_T2_DP1
52 5 =PP3V3_S0_TSENS
C5551 1

C5500 1 0.001UF
20%
1UF 50V
2 XW5551 C5550 1
10% CERM
10V 1 1 402 SM 1UF
88 52 SNS_T1_DP1 X5R 2 R5504 R5508 10%
DIFFERENTIAL_PAIR=SNS_T1 402-1
88 52 SNS_T2_DN1 1 2
10V
1
15K 10K 2
C5501 5% 5%
SNS_T2_DP2
X5R
402-1
1/16W 1/16W 88 52
0.0022UF MF-LF MF-LF
10%
402 402
50V
2 1 2 2 C5552 1
CERM
402 VDD 0.001UF
88 52 SNS_T1_DN1
DIFFERENTIAL_PAIR=SNS_T1 U5500 20%
50V
2 XW5552
EMC1414-A CERM
402 SM
88 52 44 SNS_T1_DP2_DN3 MSOP
DIFFERENTIAL_PAIR=SNS_T2 2 DP1 7 88 52 SNS_T2_DN2 1 2
1 THERM*/ADDR SNS1_ADDR
C5502 SNS_T2_DP3
0.0022UF 3 DN1 CRITICALALERT* 8 SNS1_ALERT_L
88 52 8
10%
50V
2
V+
4 DP2/DN3 9
88 52 44 SNS_T1_DN2_DP3
CERM
402 SMDATA =SMB_SNS1_SDA 49
C5553 1 U5550
DIFFERENTIAL_PAIR=SNS_T2 5 DN2/DP3 SMCLK 10 =SMB_SNS1_SCL 49
0.001UF TMP423
C GND
6
20%
50V
CERM
402
2
XW5553
1 DXP1
2 DXP2
SOT23-8 SCL
CRITICAL
7
SDA 6
=SMB_SNS2_SCL
=SMB_SNS2_SDA
49

49
C
SM 3 DXP3
88 52 SNS_T2_DN3 1 2 SNS_T2_DN 4 DXN

GND
PLACE SHORTS CLOSE TO U5550 5

SILK_PART=ODD TEMP SILK_PART=SKIN TEMP

PLACE HSK SENSOR CONN. TOP SIDE NEAR MXM OR CPU J5551 J5560
L5553 53780-8603 L5563 53261-8602
FERR-220-OHM M-RT-SM FERR-220-OHM M-RT-SM
4 3
SNS_T2_DP2 1 2 1 2
SILK_PART=CPU HSK SILK_PART=MXM HSK
88 52
88 52 SNS_T2_DP3
0402 0402
J5510 MXM J5511 92 88 SNS_ODD_P 1
92 88 SNS_SKIN_P 1
L5510 53398-8602 L5512 53398-8602 L5554 92 88 SNS_ODD_N 2
L5564 92 88 SNS_SKIN_N 2
FERR-220-OHM M-ST-SM FERR-220-OHM M-ST-SM FERR-220-OHM 3 FERR-220-OHM
3 3
SNS_T1_DP1 1 2 SNS_T1_DP2_DN3 1 2 SNS_T2_DN2 1 2

B
88 52
0402
88 SNS_CPU_H_P 1
88 52 44
0402
MXM 88 SNS_MXM_P 1
88 52
0402 5
88 52 SNS_T2_DN3 1
0402
2 4

CRITICAL
B
L5511 88 SNS_CPU_H_N 2 L5513 88 SNS_MXM_N 2 CRITICAL 518S0665
FERR-220-OHM FERR-220-OHM
1 2 4 1 2 4
518S0677
88 52 SNS_T1_DN1 88 52 44 SNS_T1_DN2_DP3
0402 CRITICAL 0402 CRITICAL
518S0678 MXM AMBIENT SENSE CONNECTOR COMBINED WITH CPU FAN
518S0678

L5522
FERR-220-OHM
88 52 SNS_T2_DP1 1 2
0402
SNS_AMB_P 54 88 92

L5523 SNS_AMB_N 54 88 92
FERR-220-OHM
88 52 SNS_T2_DN1 1 2
0402

A SYNC_MASTER=NICK SYNC_DATE=11/06/2009 A
PAGE TITLE

REMOTE TEMP/POWER SENSORS

DRAWING NUMBER SIZE

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IV ALL RIGHTS RESERVED 52 OF 92
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FAN 0 CRITICAL

=PP12V_S0_FAN
L5610
54 53 5 220-OHM-1.4A
1 2 92
89 PP12V_S0_FAN0_L
0603 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
54 53 5 =PP3V3_S0_FAN VOLTAGE=12V
1
R5602 R5603 1

R5606
1 1.5K 1.5K
10K 5%
1/4W
5%
1/8W 1 C5606 1 C5607
5%
1/16W
MF-LF
2 1206
MF-LF
805 2
CRITICAL
5 4.7UF 0.01UF
D MF-LF
2 402 R5605
20%
16V
2 CERM
20%
2 16V
CERM D
3.9K2 1206-1 402
F0_VOLTAGE8R5 1 F0_GATESLOWDN
4 Q5600
5% NTHS5443T1H
1/8W
MF-LF
805 1206A-03-HF ODD FAN
1 C5601 CRITICAL

1
2
3

6
7
8
0.47UF
J5600
46 SMC_FAN_0_CTL
10% CRITICAL 53780-8604
2 16V
3 M-RT-SM
MIN_NECK_WIDTH=0.25MM
X7R
805 L5620 MIN_LINE_WIDTH=0.5MM 5
D Q5602 MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
220-OHM-1.4A
2N7002 1 2 1
1
SOT23-HF1 FAN_0_PWR 92 FAN_0_PWR_L MOTOR CONTROL
G S
0603 92 FAN_TACH0_L 2 TACH
2 CRITICAL 3 GND
3
D5600
1
C5602 4 12V DC
54 53 5 =PP3V3_S0_FAN 100UF
1 MMBD914XG 20%
2 16V 6
SOT23 ELEC
6.3X5.5-SM1-HF 518S0730
1
R5600
10K CRITICAL
92 FAN_0_GND
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
5%
R5699
1/16W
MF-LF
L5600
FERR-220-OHM
1
R5620
0
47K 2 402 5%
46 SMC_FAN_0_TACH 1 2 FAN_TACH0 1 2 1/10W
0402 MF-LF
5%
1/16W 2 603
MF-LF
402 PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3

C NOTE: ADDED TO PROTECT SMC

FAN 1 CRITICAL

=PP12V_S0_FAN
L5630
54 53 5 220-OHM-1.4A
1 2 92
54 53 5 =PP3V3_S0_FAN 89 PP12V_S0_FAN1_L
MIN_LINE_WIDTH=0.5MM
0603 MIN_NECK_WIDTH=0.25MM
VOLTAGE=12V
R5611
1
10K
5%
1
R5610
1/16W
MF-LF 5%
1.5K R56071 1 C5608 1 C5628 1 C5609
2 402 1/4W 1.5K 2.2UF 2.2UF 0.01UF
MF-LF 5% 10% 10% 20%
2 1206 1/8W
MF-LF CRITICAL 2 16V 2 16V 2 16V
805 2 5 X5R X5R CERM
603 603 402
R5609
3.9K
F1_VOLTAGE8R5 1 2 F1_GATESLOWDN 4 Q5603 HD FAN
5% NTHS5443T1H
1/8W
46 SMC_FAN_1_CTL MF-LF 1206A-03-HF
805 CRITICAL
B 1 C5603
0.47UF CRITICAL
J5601
53780-8604
B
10% M-RT-SM

1
2
3

6
7
8
MIN_NECK_WIDTH=0.25MM
3 2 16V
X7R L5640 MIN_LINE_WIDTH=0.5MM 5
805 MIN_LINE_WIDTH=0.5MM 220-OHM-1.4A
D
Q5605 MIN_NECK_WIDTH=0.25MM
2N7002 FAN_1_PWR 1 2 92 FAN_1_PWR_L 1 MOTOR CONTROL
1 SOT23-HF1
G S 0603 92 FAN_TACH1_L 2 TACH
3 GND
54 53 5 =PP3V3_S0_FAN
2
3 D5601 1
CRITICAL
C5605
4 12V DC
MMBD914XG 100UF
R5601
1
10K
1 SOT23
20%
2 16V
TANT
6

518S0730
5% D-HF 92 FAN_1_GND
1/16W MIN_LINE_WIDTH=0.5MM
MF-LF MIN_NECK_WIDTH=0.25MM
2 402
C5605 IS POLY-TANT BECAUSE IT MUST BE PLACED ON THE BOTTOM
L5601
CRITICAL R5630
1
0
R5698 FERR-220-OHM 5%
1/10W
47K 1 2 MF-LF
46 SMC_FAN_1_TACH 1 2 FAN_TACH1 2 603
5% 0402
1/16W PLACEMENT_NOTE=PLACE R5630 CLOSE TO J5601 Pin3
MF-LF
402

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

HD AND OD FAN
DRAWING NUMBER SIZE

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8 7 6 5 4 3 2 1

FAN 2 UNUSED

D D

C C
FAN 3 CRITICAL

=PP12V_S0_FAN
L5710
53 5 220-OHM-1.4A
1 2 PP12V_S0_FAN2_L 89 92
0603
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
54 53 5 =PP3V3_S0_FAN VOLTAGE=12V

R5705
1
R5704
1
R57011
10K
1.5K 1.5K
1 C5708 1 C5709
5%
1/16W 5% 5% 4.7UF 0.01UF
MF-LF 1/4W 1/8W CRITICAL 20% 20%
16V
2 CERM 2 16V
2 402 MF-LF MF-LF CERM
2 1206 805 2 5 1206-1 402
46 SMC_FAN_3_CTL
R5703
F2_VOLTAGE8R5 1
3.9K 2 F2_GATESLOWDN
CPU FAN
4 1206A-03-HF
5% NTHS5443T1H
1/8W
MF-LF
Q5700
805 CRITICAL
J5700
1 C5701 CRITICAL 53780-8606
0.47UF M-RT-SM

1
2
3

6
7
8
3
10%
16V L5720 MIN_LINE_WIDTH=0.5MM 7
D
Q5702 2 X7R MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
220-OHM-1.4A MIN_NECK_WIDTH=0.25MM
2N7002 805
1 2
SOT23-HF1 FAN_2_PWR 92 FAN_2_PWR_L 1 MOTOR CONTROL
1 G S
0603 92 FAN_TACH2_L 2 TACH
B 2 3
1
CRITICAL
C5702
3 GND B
D5700
MMBD914XG 100UF
4 12V DC
SOT23 20% 92 88 52 IN SNS_AMB_P 5
54 53 5 =PP3V3_S0_FAN 1 2 16V
ELEC 92 88 52 IN SNS_AMB_N 6
6.3X5.5-SM1-HF

R5700
1
8
10K CRITICAL
5%
1/16W L5701
MF-LF FERR-220-OHM
2 402
FAN_TACH2 1 2
92 FAN_2_GND
0402 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

R5720
1
0
5%
1/10W
MF-LF
2 603
R5797
47K
46 SMC_FAN_3_TACH 1 2
PLACEMENT_NOTE=PLACE R5720 CLOSE TO J5700 Pin3
5%
1/16W
MF-LF
402

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

CPU FAN & AMBIENT SENSE

DRAWING NUMBER SIZE

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D D

C C
48 5 =PP3V3_S5_ROM

R6100 1 1
R6101 CRITICAL

8
C6100 1
3.3K 3.3K
5% 5% 0.1UF
20%
VDD
1/16W 1/16W 10V
MF-LF MF-LF 2
402 2 2 402
CERM
402 U6100
R6150 32MBIT R6152
0 SOIC 0
85 48 17 IN SPI_CLK_R 1 2 85 SPI_CLK 6 SCK SI 5 85 SPI_MOSI 1 2 SPI_MOSI_R IN 17 48 85

PLACEMENT_NOTE=PLACE CLOSE TO U6100 5%

1/16W
SST25VF032B 5%
1/16W
PLACEMENT_NOTE=PLACE CLOSE TO U6100
MF-LF R6105 MF-LF
85 48 IN SPI_MLB_CS_L 402 1 CE* OMIT
SO 2 85 SPI_MISO_R 1
0
2
402
SPI_MISO OUT 17 48 85
SPI_WP_L 3 WP* 5%
SPI_HOLD_L 7 HOLD* 1/16W
MF-LF
VSS 402

4
B B

A SYNC_MASTER=K23F SYNC_DATE=11/30/2009 A
PAGE TITLE

SPI ROM
DRAWING NUMBER SIZE

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8 7 6 5 4 3 2 1
AUDIO CODEC
APPLE P/N 353S2592

VD MUST BE LESS THAN OR EQUAL TO VL_HD =PP5V_S0_AUDIO IN 5 56

5 =PP1V5_S0_AUD_DIG
=PP3V3_S0_AUDIO IN
C6203 1 1 C6258 5 56 58 59 60 61 62

4.7UF 0.47UF
20%
4V
10%
10V PP4V5_AUDIO_ANALOG IN 56 89
X5R 2 2 X5R VOLTAGE=4.5V
MIN_LINE_WIDTH=0.20MM
402 402
C6259 1 C6264 1
C6265 1 1 C6213 MIN_NECK_WIDTH=0.10MM

D C6260 1
10UF C6261 1 1
C6262 10V
X5R
1UF
10%
2
0.47UF
10%
10V
X5R 2
0.47UF
10%
10V 2
10UF
20%
6.3V
D
20% 2 X5R
16V 2 0.47UF 10UF 402-1 402 X5R
61 60 56 GND_AUDIO_HP_AMP_L POLY-TANT 10%
10V 2
20% 402 603

25
CASE-B2-SM 2 16V
PP4V5_AUDIO_ANALOG X5R GND_AUDIO_HP_AMP_L 56 60 61

9
POLY-TANT
89 56 IN
C6204 1 1 C6205 402 CASE-B2-SM
GND_AUDIO_CODEC 47 56 57
1
R6255 10UF 10UF VD VA_REF VA_HP VA 61 62
20%
6.3V 2
20% VBIAS_DAC 29 VBIAS_DAC
2.67K 2 6.3V
1% X5R X5R CRITICAL HPOUT_L 38 MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_HP_L OUT 56 60
1/16W
603 603 CS4206_FP 44 VHP_FILT+
40 AUD_HP_R
MF-LF
2 402
CS4206_FN 41 VHP_FILT- U6201 HPOUT_R MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM OUT 56 60

CS4206ACNZC HPREF 39 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM AUD_HP_PORT_REF IN 60

QFN
NC TP_AUD_GPIO0 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 AUD_LO1_P_L OUT 59 86

NC TP_AUD_GPIO_1 12 GPIO1/DMIC_SDA2 LINEOUT_L1-

/SPDIF_OUT2
34 AUD_LO1_N_L OUT 59 86

TP_AUD_GPIO_2 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_P_R 58 86

58
NC AUD_GPIO_3 15 GPIO3 LINEOUT_R1- 37 AUD_LO1_N_R
OUT
58 86
OUT OUT

61 IN AUD_SENSE_A 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_P_L OUT 59 86

CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_N_L OUT 59 86

CS4206_FLYC LINEOUT_R2+ 32 AUD_LO2_P_R OUT 58 86

45 FLYP
LINEOUT_R2- 33 AUD_LO2_N_R
C6206 1 1 C6208 43 FLYC OUT 58 86

2.2UF 2.2UF 42 FLYN

20% 20%
6.3V
CERM 2 2 6.3V
CERM MICBIAS 16 AUD_CODEC_MICBIAS OUT 61
402-LF 402-LF
3 VL_HD
CS4206_FLYN
VCOM 28 CS4206_VCOM
1 VL_IF
PLACE TP FOR ALL HDA SIGNALS NEAR CODEC
AUD_LI_P_L
C 85 17 IN HDA_BIT_CLK 6 BITCLK
LINEIN_L+
LINEIN_C-
21
22 AUD_LI_COM
IN
IN
57

57
C
85 17 IN HDA_SYNC LINEIN_R+ 23 AUD_LI_P_R IN 57

R6254 10 SYNC
22
85 17 OUT HDA_SDIN0 1 2 85 AUD_SDI_R 8 SDI MICIN_L+ 18 AUD_MIC_INP_L IN 62

5% 5 SDO MICIN_L- 17 AUD_MIC_INN_L IN 62

1/16W
MF-LF MICIN_R+ 19 AUD_MIC_INP_R IN 61
402 11 RESET*
85 17 IN HDA_SDOUT MICIN_R- 20 AUD_MIC_INN_R IN 61

85 17 IN HDA_RST_L
77 AUD_SPDIF_IN_CODEC 47 SPDIF_IN
IN
85 AUD_SPDIF_CHIP 48 SPDIF_OUT
VREF+_ADC 27 CS4206_VREF_ADC NC
R6257
22
85 60 OUT AUD_SPDIF_OUT 1 2 DMIC_SCL 4 TP_AUD_DMIC_CLK NC
5% R62951
1/16W
MF-LF
100K
1%
402 1/16W DGND THRM_PAD AGND
MF-LF
402 2

26
CRITICAL CRITICAL
C6211 1 1
C6263 NOSTUFF DIFF FSINPUT= 2.45VRMS
1UF 10UF
NOSTUFF 10%
20V 2
20%
2 16V
R6267
1 SE FSINPUT= 1.22VRMS
R6263
1 TANT
CASE-P3-HF
POLY-TANT
CASE-B2-SM 5%
100K DAC1 FSOUTPUT= 1.34VRMS
5%
0 1/16W
MF-LF
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
1/16W
MF-LF 2 402 DAC2/3 FSOUTPUTSE= 1.34VRMS
2 402

62 61 57 56 47 GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
B VOLTAGE=0V
HP OUT ZOBEL NETWORK B
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM AUD_HP_L
OUT 56 60

APPLE P/N 353S2456 MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM AUD_HP_R
4.5V POWER SUPPLY FOR CODEC OUT 56 60

MIN_LINE_WIDTH=0.20MM
C6298 1 C6297 1

MIN_NECK_WIDTH=0.10MM 0.1UF 0.1UF MIN_LINE_WIDTH=0.30MM

VOLTAGE=4.5V 10% 10% MIN_NECK_WIDTH=0.20MM
16V 16V
MIN_LINE_WIDTH=0.20MM X7R-CERM 2 X7R-CERM 2
MIN_NECK_WIDTH=0.10MM
L6201 402 402
FERR-220-OHM VR6201
TPS71745
VOLTAGE=4.5V
AUD_Z_R NC
56 5 =PP5V_S0_AUDIO 1 89 2 4V5_REG_IN 6 IN SON 1 PP4V5_AUDIO_ANALOG 56 89
AUD_Z_L NC
IN OUT OUT
R6201 0402 CRITICAL R62961 R62971 MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
4V5_REG_EN 4V5_NR
=PP3V3_S0_AUDIO 12.21K2 39 39
91 4 EN NR/FB 3
62 61 60 59 58 56 5 IN 5% 5%
1/16W 1/16W
1%
GND NC 5 MF-LF MF-LF
1/16W 402 2 402 2
MF-LF
402 2
C6266 1
1 C6207 GND_AUDIO_HP_AMP_L
1 C6201 1 C6202 1UF 56 60 61
0.1UF 10%
1UF 1UF 10% 2 10V
10% 10% 16V X5R
10V 10V X7R-CERM 2 402-1
2 X5R 2 X5R 402
402-1 402-1
GND_AUDIO_CODEC 47 56 57 61 62

A XW6201
SM SYNC_MASTER=BREECE SYNC_DATE=02/02/2010 A
1 2 GND_AUDIO_HP_AMP_L 56 60 61
PAGE TITLE
VOLTAGE=0V
AUDIO: CODEC/REGULATOR
DRAWING NUMBER SIZE

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8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C CODEC Nom SE RIN = 20K OHMS

C
FC = 3.62 HZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
NET RIN = 18K OHMS
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM CRITICAL MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM R6300 C6300
AUD_LI_LF 2.2UF
7.87K2
60 IN AUD_LI_L 1 1 2 AUD_LI_P_L OUT 56

1%
1/16W 10%
MF-LF 25V
402 X5R-CERM
805

NOSTUFF
R63011 1 C6301
21.5K 820PF
1% 10%
1/16W 50V
MF-LF 2 CERM
402 2 402

CRITICAL
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=0.3MM C6302 MIN_LINE_WIDTH=.3MM
2.2UF
60 IN AUD_LI_GND 1 2 AUD_LI_COM OUT 56

10%
25V
X5R-CERM
1
R6303 805

10
B 1%
1/16W
MF-LF R63051
NOSTUFF B
2 402 21.5K
1 C6304
1% 820PF
1/16W 10%
62 61 56 47 IN GND_AUDIO_CODEC MF-LF 2 50V
CERM
402 2 402
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
CRITICAL
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM R6306
MIN_LINE_WIDTH=.3MM C6303
AUD_LI_RF 2.2UF
7.87K2
60 IN AUD_LI_R 1 1 2 AUD_LI_P_R OUT 56

1%
1/16W 10%
MF-LF 25V
402 X5R-CERM
805

A SYNC_MASTER=BREECE SYNC_DATE=02/02/2010 A
PAGE TITLE

AUDIO: FILTER/BUFFER
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 57 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

RIGHT CH. SPEAKER AMP

APPLE P/N 353S2768
D D

59 5 IN =PP12V_S0_AUDIO_SPKRAMP

CRITICAL CRITICAL
1 C6400 1 C6401 1 C6402 1 C6403 1 C6404 1 C6405 1
C6406 1
C6408
10UF 0.1UF 0.1UF 1UF 0.1UF 1UF 100UF 100UF
10% 10% 10% 10% 10% 10% 20% 20%
25V 25V 25V 25V 25V 25V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 16V 2 16V
TANT TANT
805 402 402 603-1 402 603-1 D-HF D-HF

L6400 C6407
FERR-1000-OHM 0.068UF
86 56 IN AUD_LO1_P_R 1 2 86 AUDAMPINBRP 1 2 86 AUDAMPINRP
0402
10%
25V
X5R
0402 C6410
L6401 C6409 0.22UF
CRITICAL
FERR-1000-OHM 0.068UF AUDBAMPBSRP 1 2
MIN_LINE_WIDTH=0.5MM
AUD_LO1_N_R AUDAMPINBRN AUDAMPINRN L6404

26
PVCCL 27

34
PVCCR 35
86 56
1 2 86 1 2 86 MIN_NECK_WIDTH=0.2MM
IN 20%
0402 AVCC 25V MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
FERR-220-OHM-2.5A
10% X5R
25V
X5R
603 AUDAMPOUTBRP 1 2 AUD_SPKR_OUTLO1R_POUT OUT 60 85
92
0402 0603
3 43 CRITICAL
L6402 C6411 2
RINP BSRP
41
C AUD_LO2_N_R
FERR-1000-OHM
1 2 86 AUDAMPINBLN
0.068UF
1 2 86 AUDAMPINLN 6
RINN
U6400
ROUTP1
ROUTP2
42 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
L6405
FERR-220-OHM-2.5A
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM C
LINN
86 56 IN
0402 86 AUDAMPINLP 5 TPA3103D2 39 AUDAMPOUTBRN 1 2 AUD_SPKR_OUTLO1R_NOUT
10% LINP QFN ROUTN1 OUT 60 85
25V
ROUTN2
40 C6415 0603
92

X5R
0402
AUDAMPMUTE 45 MUTE*
38 0.22UF
BSRN AUDBAMPBSRN 1 2
CRITICAL
AUDAMPFAULT 46 FAULT
L6403 C6413 BSLP
18
20% C6416
FERR-1000-OHM 0.068UF =PP3V3_S0_AUDIO 44 19 25V 0.22UF
AUD_LO2_P_R 62 61 60 59 58 56 5 SD* LOUTP1 X5R
20 CRITICAL
86 56 IN
1 2 86 AUDAMPINBLP 1 2
10 MSTR/SLV* LOUTP2 AUDBAMPBSLP 603 1 2
AUDAMPMSTR
0402 NOSTUFF 10% 21 20% L6406 MIN_LINE_WIDTH=0.5MM
R6410 25V AUDAMPG1 8 GAIN0 LOUTN1
22
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM 25V FERR-220-OHM-2.5A MIN_NECK_WIDTH=0.2MM
270K 2 X5R X5R AUD_SPKR_OUTLO2R_POUT
62 61 60 59 58 56 5 =PP3V3_S0_AUDIO 1 0402 AUDAMPG2 9 GAIN1 LOUTN2
23 AUDAMPOUTBLP 603 1 2
OUT 60 85

5%
BSLN 0603
92
NOSTUFF MIN_LINE_WIDTH=0.5MM
1/16W AUDAMPVREG 15 VREG 31 MIN_NECK_WIDTH=0.2MM CRITICAL
MF-LF
402 R6412 AUDAMPVBYP 16 VBYP
VCLAMPR
30 AUDAMPOUTBLN L6407 MIN_LINE_WIDTH=0.5MM
1
R6411 0 14 ROSC VCLAMPL FERR-220-OHM-2.5A MIN_NECK_WIDTH=0.2MM
R6401 0
1 2
11
AUD_SPKR_OUTLO2R_NOUT
AUD_GPIO_3 1
0 2
5% 5%
1/16W
SYNC C6417 1 2
OUT 60 85
92
56 IN 1/16W
5%
MF-LF MF-LF
402 1 0.22UF 0603
2 402 NC0
1/16W AUDBAMPBSLN 1 2
R64001 MF-LF
402
3 NC1 7
12
100K AUD_SPKRAMP_MUTE_L D NOSTUFF NC2 20%
25V
5% NOSTUFF
1/16W
MF-LF C6414 1 Q6400 NC3 13 X5R
603 C6420 1
C6421 1
402 2 NC4 24 0.001UF
100PF 5 G NTZD3154NT1H 10% 0.001UF
5%
50V SOT-563-HF NC5 25 AUDSPKRAMPSYNC OUT 59
50V
CERM 2
10%
50V
CERM 2 36 402 CERM 2
402 NC6 402
S 37
NC7

PGNDL

PGNDR
6 4 NC8 47
THM
NOSTUFF AUDAMPCLAMPR
B Q6400
D AGND PAD
AUDAMPCLAMPL 1 C6422 1 C6423 B

4
17

28
29

32
33

49
NTZD3154NT1H G 2 0.001UF 0.001UF
59 58 59 58 OUT AUD_SPKRAMP_MUTE_L SOT-563-HF
10%
50V
10%
50V
2 CERM 2 CERM

AUDAMPROSC
402 402
S

62 61 60 59 58 56 5 =PP3V3_S0_AUDIO
C6424 1 1 C6425
1UF 1UF
NOSTUFF NOSTUFF 10% 10%
25V 2 2 25V
X5R X5R
R6402
1
R6404 1
R6406
1
603-1 603-1
100K 100K 100K
5% 5% 5%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
2 402 402 2 2 402
R6408
1
100K
5%
1/16W
MF-LF
2 402

R64051
1
R6407 C6418
0.01UF
1 1 C6419
1UF
100K
100K 5% 10%
25V
10%
10V
5% 1/16W X7R 2 2 X5R
1/16W MF-LF 402 402
A MF-LF
402 2 2 402 U6400 IS CLOCK MASTER
R6402=HIGH=MASTER SYNC_MASTER=BREECE SYNC_DATE=02/02/2010 A
PAGE TITLE
SPEAKER AMP GAIN = 9DB AUDIO: SPEAKER AMP_1
SPEAKER AMP RIN = 89.6K TO 134K W/ 9DB DRAWING NUMBER SIZE
FC_HPF = 2.5HZ TO 3.8HZ 051-8337 D
Apple Inc. REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
64 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 58 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

LEFT CH. SPEAKER AMP

APPLE P/N 353S2768

D 58 5 IN =PP12V_S0_AUDIO_SPKRAMP
D
CRITICAL CRITICAL
1 C6500 1 C6501 1 C6502 1 C6503 1 C6504 1 C6505 1
C6506 1
C6508
10UF 0.1UF 0.1UF 1UF 0.1UF 1UF 100UF 100UF
10% 10% 10% 10% 10% 10% 20% 20%
25V 25V 25V 25V 25V 25V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 16V 2 16V
TANT TANT
805 402 402 603-1 402 603-1 D-HF D-HF

L6500 C6507
FERR-1000-OHM 0.068UF
AUD_LO1_P_L
86 56 IN
1 2 86 AUDAMPINCRP 1 2 86 AUD_AMPINRP
0402
10%
25V
X5R
0402 C6510
L6501 C6509 0.22UF
FERR-1000-OHM 0.068UF AUDCAMPBSRP 1 2 CRITICAL
AUD_LO1_N_L MIN_LINE_WIDTH=0.5MM
AUDAMPINCRN AUD_AMPINRN L6504

26
PVCCL 27

34
PVCCR 35
86 56
1 2 86 1 2 86 MIN_NECK_WIDTH=0.2MM
IN 20%
0402 25V MIN_LINE_WIDTH=0.5MM FERR-220-OHM-2.5A
10% AVCC X5R MIN_NECK_WIDTH=0.2MM
25V
X5R
603 AUDAMPOUTCRP 1 2 AUD_SPKR_OUTLO1L_POUT OUT 60 85 92
0402 0603
3 43 CRITICAL
L6502 C6511 2
RINP BSRP
41
FERR-1000-OHM 0.068UF RINN ROUTP1 L6505 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
AUD_LO2_N_L 1 2 86 AUDAMPINCLN 1 2 86 AUD_AMPINLN 6
LINN
U6500 ROUTP2
42 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
FERR-220-OHM-2.5A
86 56 IN
0402 AUD_AMPINLP 5 TPA3103D2 39 AUDAMPOUTCRN 1 2
AUD_SPKR_OUTLO1L_NOUT
10%
86 LINP QFN ROUTN1 OUT 60 85 92
40 C6515
C
25V
X5R
0402
AUD_AMPMUTE 45 MUTE*
CRITICAL
ROUTN2
BSRN
38
AUDCAMPBSRN
0.22UF
1 2
0603
C
AUD_AMPFAULT 46 FAULT
L6503 C6513 BSLP
18
20% C6516
FERR-1000-OHM 0.068UF =PP3V3_S0_AUDIO 44 19 25V 0.22UF
AUD_LO2_P_L 59 58 56 5 SD* LOUTP1 X5R
62 61 60
20 CRITICAL
86 56 IN
1 2 86 AUDAMPINCLP 1 2
10 MSTR/SLV* LOUTP2 AUDCAMPBSLP 603 1 2
AUD_AMPSLAVE
0402
10% 21 20%
L6506 MIN_LINE_WIDTH=0.5MM
NOSTUFF 25V AUD_AMPG1 8 GAIN0 LOUTN1 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM 25V FERR-220-OHM-2.5A MIN_NECK_WIDTH=0.2MM
X5R 22 X5R
0402 AUD_AMPG2 9 GAIN1 LOUTN2 AUDAMPOUTCLP 603 1 2 AUD_SPKR_OUTLO2L_POUT
R6510 BSLN
23 OUT 60 85 92

=PP3V3_S0_AUDIO 1 270K 2 MIN_LINE_WIDTH=0.5MM 0603

62 61 60 59 58 56 5 NOSTUFF AUD_AMPVREG 15 VREG 31 MIN_NECK_WIDTH=0.2MM
5% R6511 R6512 AUD_AMPVBYP 16 VBYP
VCLAMPR
30 AUDAMPOUTCLN CRITICAL
1/16W 0
MF-LF
402
1 2
1
0 2
14 ROSC VCLAMPL
L6507 MIN_LINE_WIDTH=0.5MM
11 FERR-220-OHM-2.5A MIN_NECK_WIDTH=0.2MM
5%
1/16W 6 5%
SYNC C6517 1 2
AUD_SPKR_OUTLO2L_NOUT
MF-LF
402
1/16W
MF-LF 1 0.22UF OUT 60 85 92
D NOSTUFF NC0
58 IN AUD_SPKRAMP_MUTE_L 402
7
AUDCAMPBSLN 1 2 0603
NC1
Q6500 NC2 12 20%
2 G NTZD3154NT1H 25V
SOT-563-HF NC3 13 X5R
603 C6520 1 C6521 1
NC4 24 0.001UF 0.001UF
S 10% 10%
3 NC5 25 AUDSPKRAMPSYNC IN 58
50V
CERM 2
50V
CERM 2
NOSTUFF 1 NC6 36 402 402
D
NC7 37
Q6500

PGNDL

PGNDR
NC8 47
NTZD3154NT1H G 5 THM
SOT-563-HF AGND PAD AUDAMPVCLAMPR
AUDAMPVCLAMPL
S 1 C6522 1 C6523

4
17

28
29

32
33

49
0.001UF 0.001UF
4 10% 10%
50V 50V

B
2 CERM
402
2 CERM
402 B
62 61 60 59 58 56 5 =PP3V3_S0_AUDIO

AUD_AMPROSC

NOSTUFF NOSTUFF
R65041 R6506
1

100K 100K
5%
1/16W
5%
1/16W
C6524 1 1 C6525
MF-LF MF-LF 1UF 1UF
402 2 10% 10%
2 402 25V 25V
X5R 2 2 X5R
603-1 603-1

R6508
1

100K
5%
1/16W
1
R6503 MF-LF
2 402
100K R6507
1
5%
1/16W 100K
MF-LF 5%
2 402 1/16W
U6500 IS SLAVE
A R6505
100K
1 MF-LF
2 402
C6518 1 1 C6519 R6503 = LOW = SLAVE SYNC_MASTER=BREECE SYNC_DATE=02/02/2010 A
5% PAGE TITLE
0.01UF 1UF
1/16W
MF-LF
402 2
10%
25V
X7R 2
10%
10V
2 X5R
AUDIO: SPEAKER AMP
402 402 SPEAKER AMP GAIN = 9DB DRAWING NUMBER SIZE
SPEAKER AMP RIN = 89.6K TO 134K W/ 9DB Apple Inc. 051-8337 D
FC_HPF = 2.5HZ TO 3.8HZ REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
65 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 59 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SPEAKER CABLE CONNECTORS
INTERNAL MIC CON APPLE P/N 518S0748
APPLE P/N 518S0677 APPLE P/N 518S0656

PROPERTIES FOR ALL SPKR NETS

CRITICAL
CRITICAL
L6600 L6601 J6601 PROPERTIES FOR ALL SPKR NETS CRITICAL
MIN_LINE_WIDTH=0.5MM J6603
53780-8603 MIN_NECK_WIDTH=0.2MM
FERR-1000-OHM FERR-1000-OHM M-RT-SM MIN_LINE_WIDTH=0.5MM J6602 78048-0573
MIN_NECK_WIDTH=0.2MM M-RT-SM
61 AUD_MIC1_IN_N 1 2 AUD_MIC_IN1_N_EMI 1 2 92 AUD_MIC_IN1_N_CONN
4 78048-0473
OUT M-RT-SM
0402 0402 92 85 59 IN AUD_SPKR_OUTLO2L_POUT 1
1 AUD_SPKR_OUTLO2R_POUT 1 WOOFER (BL) AUD_SPKR_OUTLO2L_NOUT 2

D GND_AUDIO_MIC1_CONN 2
WOOFER (BR)
92 85 58

92 85 58
IN
IN AUD_SPKR_OUTLO2R_NOUT 2
92 85 59

NO_TEST
IN
NC NC_J6702_3 3 D
L6602 L6603 3 92 85 58 IN AUD_SPKR_OUTLO1R_POUT 3 92 85 59 IN AUD_SPKR_OUTLO1L_POUT 4
TWEETER (FR) AUD_SPKR_OUTLO1R_NOUT TWEETER (FL) AUD_SPKR_OUTLO1L_NOUT
FERR-1000-OHM FERR-1000-OHM 92 85 58 IN
4 92 85 59 IN
5
5
61 OUT AUD_MIC1_IN_P 1 2 AUD_MIC_IN1_P_EMI 1 2 92 AUD_MIC_IN1_P_CONN
0402 0402

CRITICAL CRITICAL
2 2
DZ6600 DZ6601 R6600
1
6.8V-100PF 6.8V-100PF 0
402 402 5%
1/16W
MF-LF
1 1 2 402

R6601
22
85 77 OUT AUD_SPDIF_IN 1 2
L6604 5%
1/16W
FERR-1000-OHM MF-LF
402
59 58 56 5 IN =PP3V3_S0_AUDIO 1 2
62 61
0402
L6605 REMOTE I/O CONNECTOR
FERR-1000-OHM APPLE P/N 518S0791
C 61 OUT AUD_LI_TIP_DET
CRITICAL L6610
1
0402
2
C
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM 600OHM-0.2A
57 OUT AUD_LI_GND 1 2

MIN_LINE_WIDTH=0.3MM 0402 L6607

MIN_NECK_WIDTH=0.2MM FERR-1000-OHM
57 OUT AUD_LI_R 1 2
0402
MIN_LINE_WIDTH=0.3MM L6608 CRITICAL
MIN_NECK_WIDTH=0.2MM FERR-1000-OHM
AUD_SPDIFIN_JACK IN 60 92
J6600
57 OUT AUD_LI_L 1 2 50238-02071
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V PP3V3_AUDIO_SPDIF_JACK F-ST-SM
MIN_LINE_WIDTH=0.15MM 0402 L6609 AUD_LI_DET_JACK 21
MIN_NECK_WIDTH=0.1MM FERR-1000-OHM MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM IN 60 92
VOLTAGE=0V
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 92 AUD_LI_GND_JACK
62 OUT HS_MIC_LO 1 2
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_LI_R_JACK 60 92 1 2 AUD_SPDIFIN_JACK 60 92
MIN_LINE_WIDTH=0.15MM L6606 0402
AUD_LI_GND_JACK
IN
3 4 AUD_LI_DET_JACK
OUT
MIN_NECK_WIDTH=0.1MM FERR-1000-OHM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM OUT 60 92

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_LI_L_JACK IN 60 92 5 6 AUD_LI_R_JACK OUT 60 92

62 OUT HS_MIC_HI 1 2
MIN_LINE_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 92 HS_MIC_LO_JACK 7 8 AUD_LI_L_JACK 60 92
0402 OUT
MIN_NECK_WIDTH=0.1MM XW6617 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM HS_MIC_HI_JACK IN 60
9 10 HS_MIC_HI_JACK OUT 60 92
56 OUT AUD_HP_PORT_REF 92
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 92 AUD_HP_GND_JACK 11 12 AUD_HP_L_JACK 60 92
1 2 IN
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
SM
R6617 MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_HP_L_JACK OUT 60 13 14 AUD_HP_R_JACK IN 60 92
0 92
61 56 OUT GND_AUDIO_HP_AMP_L 1 2 AUD_HP_GND_JACK 15 16 AUD_IP_PERPH_JACK OUT 60 92

5% MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_HP_R_JACK OUT 60 92 17 18 PP3V3_AUDIO_SPDIF_JACK 60 89 92

MIN_LINE_WIDTH=0.3MM 1/10W
MIN_NECK_WIDTH=0.2MM L6616
MF-LF MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM 92 AUD_HP_TYPEDET_JACK 19 20
220-OHM-0.7A-0.28-OHM 603 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM AUD_IP_PERPH_JACK 60 92
IN
56 IN AUD_HP_L 1 2 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM 92 AUD_HP_TIPDET_JACK 22

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
0402 L6618 PP3V3_AUDIO_SPDIF_JACK 60 89 92

VOLTAGE=0V
220-OHM-0.7A-0.28-OHM 92 AUD_SPDIF_OUT_JACK

B 56 IN AUD_HP_R 1 2 B
MIN_LINE_WIDTH=0.2MM L6614 0402
MIN_NECK_WIDTH=0.1MM FERR-1000-OHM
61 OUT AUD_HP_TYPE 1 2
0402 L6615
MIN_LINE_WIDTH=0.2MM FERR-1000-OHM
MIN_NECK_WIDTH=0.1MM
61 OUT AUD_IP_PERPH_DET 1 2

MIN_LINE_WIDTH=0.2MM L6612 0402

MIN_NECK_WIDTH=0.1MM FERR-1000-OHM
61 OUT AUD_HP_TIP_DET 1 2
0402 L6613
FERR-1000-OHM
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
AUD_SPDIF_OUT 1 2 CRITICAL CRITICAL 2 2 2 2 2
85 56 IN
0402
2
DZ6603
2
DZ6605 DZ6607 DZ6609 DZ6611 DZ6613 DZ6615
6.8V-100PF 6.8V-100PF 6.8V-100PF 6.8V-100PF 6.8V-100PF
6.8V-100PF 6.8V-100PF 402 402 402 402 402
402 402
CRITICAL 2
CRITICAL 2 1
CRITICAL 2 1
CRITICAL 2 1
CRITICAL CRITICAL 1 1
1
DZ6604
2 1
DZ6606
2 DZ6608 DZ6610 DZ6612 DZ6614
6.8V-100PF 6.8V-100PF 6.8V-100PF 6.8V-100PF
6.8V-100PF ESDALC5-1BM2 402 402 402 402
402 SOD882
1 1 1 1
1 1
C6600 1 1 C6601
1UF 0.47UF
10% 10%
10V 2 2 10V
X5R X5R
402-1 402

A SYNC_MASTER=BREECE SYNC_DATE=02/02/2010 A
PAGE TITLE

Audio: MLB to I/O Conn.

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 60 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

AUDIO STAR GND AND STUFFING OPTIONS

Internal Microphone Impedance Matching XW6705
SM
1 2 GND_AUDIO_CODEC OUT 47 56 57 61 62
R6743
2.2K 2 NOSTUFF
AUD_INTMICBIAS 1 AUD_CODEC_MICBIAS IN 56

5% R6747
1/16W
1
0 2
CRITICAL MF-LF
402

D
1
R6793 C6751 1
3.40K 4.7UF
5%
1/16W
MF-LF
D
1% 20% 402
1/16W 6.3V 2
MF-LF TANT NOSTUFF
603-HF
2 402 GND_AUDIO_CODEC
C6795
47 56 57 61 62
R6748
0
0.1UF 1 2
60 IN AUD_MIC1_IN_P 1 2 AUD_MIC_INP_R OUT 56 5%
1/16W
MF-LF
C6750 1
1
R6791 10%
16V
402

0.0082UF 100K X5R

402
10% 5% NOSTUFF
25V
X7R 2
1/16W
MF-LF C6796 R6749
402 2 402 0.1UF
0
60 IN AUD_MIC1_IN_N 1 2 AUD_MIC_INN_R OUT 56 60 56 GND_AUDIO_HP_AMP_L 1 2 GND_AUDIO_CODEC 47 56 57 61 62

5%
10% 1/16W
16V MF-LF
1
R6792 X5R
402
402
3.40K
1%
1/16W
MF-LF
2 402 XW6702
AUD_MIC1_IN_G 1
SM
2 GND_AUDIO_CODEC 47 56 57 61 62 IPHS HS Detect Debounce CKT
62 61 60 59 58 56 5 =PP3V3_S0_AUDIO

R6797
1
R67981 R67681
100K
100K 100K 5%
5% 5% 1/16W
1/16W 1/16W MF-LF
MF-LF MF-LF 402 2 R6799
C 2 402 402 2
AUD_IP_PERPH_DET_DB 1
0 2 AUD_IP_PERIPHERAL_DET
OUT 19
C
5%
1/16W
6 MF-LF
402
D
R6796 Q6701
AUD_IP_PERPH_DET_INV 0 AUD_IP_PERPH_DET_R G
1 2 2 NTZD3154NT1H
5% SOT-563-HF
1/16W
3 MF-LF S
402
D 1
R6700 Q6701 NOSTUFF
17.4K2
60 IN AUD_IP_PERPH_DET 1 AUD_IP_PER_DEB 5 G NTZD3154NT1H 1 C6797
1%
SOT-563-HF 0.1UF
1/16W 10%
MF-LF
402
1 C6740 S 2 16V
X5R
0.1UF 402
10% 4
2 16V
X5R
402

62 61 57 56 47 GND_AUDIO_CODEC

Digital Out Headphone Out LI Insert Detect

B 61 56 IN AUD_SENSE_A
61 56 IN AUD_SENSE_A 61 56 IN AUD_SENSE_A
B
62 61 60 59 58 56 5 IN =PP3V3_S0_AUDIO CRITICAL 62 61 60 59 58 56 5 IN =PP3V3_S0_AUDIO
61 60 59 58 56 5 IN =PP3V3_S0_AUDIO
R6794
1 62
R6744
1

R6790
1 20K 39.2K
100K
0.1%
1/16W R67951 1%
1/16W R67301 1
R6701
5% MF 100K MF-LF 100K 10K
1/16W 2 402 5% 2 402 5% 1%
MF-LF 1/16W 1/16W 1/16W
2 402 AUD_Q6702_D3 NC MF-LF
402 2 AUD_Q6701_D6 NC MF-LF
402 2
MF-LF
2 402

6 3

D D
Q6700 Q6702 60 IN AUD_LI_TIP_DET
60 AUD_HP_TYPE 2 G NTZD3154NT1H AUD_HP_TYPE_INV 5 G NTZD3154NT1H
IN
SOT-563-HF SOT-563-HF

S S
AUD_LI_TIP_DET_INV
1 4

62 61 60 59 58 56 5 IN =PP3V3_S0_AUDIO
6

AUD_HP_TIP_DET_INV D
1
R6762 Q6703
100K 2 G NTZD3154NT1H
A 5%
1/16W
MF-LF 3 6
S
SOT-563-HF
SYNC_MASTER=BREECE SYNC_DATE=02/02/2010 A
2 402 3 PAGE TITLE
D
Q6700
D
Q6702 DP Audio Enable 1 D AUDIO: Detects/Grounding
AUD_HP_TIP_DET 5 G NTZD3154NT1H 2 G NTZD3154NT1H BDV_AV_MUX_SEL Q6703 DRAWING NUMBER SIZE
60 IN
SOT-563-HF SOT-563-HF 47 IN
5 G NTZD3154NT1H
Apple Inc. 051-8337 D
SOT-563-HF
REVISION
S S
S
R
A.0.0
4 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
4
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
62 61 57 56 47 GND_AUDIO_CODEC THE POSESSOR AGREES TO THE FOLLOWING: PAGE
GND_AUDIO_CODEC
62 61 57 56 47
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
67 OF 110

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 61 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ENABLE/
FUNCTION PIN CONVERTER VOLUME CNTRL TYPE DETECT/INTERRUPT
0X0B 0X04 0X04 GPIO 3 N/A
PRIMARY 0X03 0X03 GPIO 3
SECONDARY 0X0A N/A
0X09 0X02 0X02 N/A 0X09 (A)
HEADPHONES 0X05 0X05 N/A
LINE INPUT 0X0C LINE IN
BUILT-IN MICROPHONE 0X0D(13,B,RIGHT) 0X06 0X06 MICBIAS 80% N/A
D HEADSET MICROPHONE 0X0D (13,V22,B,LEFT) 0X06 0X06 MIKEY MIKEY D
SPDIF OUT 0X10 0X08 N/A N/A 0X0D (B)
SPDIF IN 0X0F 0X07 N/A N/A N/A
MIKEY N/A N/A N/A MCP GPIO_38 MCP GPIO_5

C C

MIKEY RECEIVER CKT

WRITE: 0X72 READ: 0X73 APN 353S2256
MIN_LINE_WIDTH=0.15MM
L6840 MIN_NECK_WIDTH=0.1MM
FERR-1000-OHM VOLTAGE=3.3V
89 PP3V3_S0_HS_F
61 60 59 58 56 5 IN =PP3V3_S0_AUDIO 1 2
0402

R6802 1 C6852
=I2C_AUDIO_SCL 1
0 2
1
R6806 1UF
49 IN
5%
10K
5%
10%
2 10V
1 C6853
1/16W X5R 0.1UF CRITICAL

3
1/16W 402 10%
MF-LF MF-LF
402
2 402 2 16V
X5R AVDD
402 MIN_LINE_WIDTH=0.15MM
R6803 U6806 MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM MIN_LINE_WIDTH=0.15MM
0 CD3275 MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM
49 BI =I2C_AUDIO_SDA 1 2 DRC
1
HS_MIC_BIAS
5% HS_SCL 6 SCL MICBIAS
1/16W
MF-LF
402 HS_SDA 5 SDA DETECT 2 HS_SW_DET
CRITICAL
R6804 HS_INT_L 7 INT* BYPASS 10 HS_RX_BP 1
C6854
AUD_I2C_INT_L 1
0 2 4.7UF
19 OUT HS_RST 8 ENABLE 20%
5% 2 6.3V
B 1/16W
MF-LF 1
R6807
GND THM 1 C6899
0.01UF
TANT
603-HF B
4
9

402
100K 10%
R6805 5% 2 25V
X7R
1/16W 402 GND_AUDIO_CODEC 47 56 57 61 62

AUD_IPHS_SWITCH_EN1 0 2
MF-LF R6852
1 1
R6809
20 IN 2 402 1K 2.2K
5% 5% 5%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
402
2 402 2 402

62 61 57 56 47 GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.15MM R6810
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM C6801 MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM 0.1UF
2.2K 2
60 IN HS_MIC_HI 1 AUD_MIC_INF 1 2 AUD_MIC_INP_L OUT 56

5%
1/16W 10%
1
R6808 MF-LF
402 1 C6855
16V
X5R
100K 0.0082UF
402
5% 10%
1/16W 25V
MF-LF
2 402 MIN_LINE_WIDTH=0.15MM
2 X7R
402
C6802 MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM 0.1UF
60 IN HS_MIC_LO 1 2 AUD_MIC_INN_L OUT 56

10%
16V
X5R
402

FLP = 8.82 KHZ

FHP = 80 HZ
A SYNC_MASTER=BREECE SYNC_DATE=02/02/2010 A
PAGE TITLE

AUDIO: Mikey
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 62 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
State Manageability SMC_PM_G2_ENABLE PM_S4_STATE_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_M_L

R6901 Run (S0/M0) N/A 1 1 1 1 1

91 46 IN
PM_RSMRST_L 1 0
5%
1/16W
2 PM_RSMRST_PCH_L OUT 18 91
SLP_S4 ENABLES Sleep (S3/M1)

Soft-Off (S5/M1)
On

On
1
1
1
0
0
0
1
1
1
1
MF-LF
402
=PP3V3_S5_PWRCTL
Sleep (S3/M-Off) Off 1 1 0 1 0
64 63 10 5

C6910 Soft-Off (S5/M-Off) Off 1 0 0 0 0

0.1UF
2 1 Battery Off (G3Hot) N/A 0 0 0 0 0
20%

D
10V
CERM
402 D
14 74LVC08
91 18 PM_SLP_S4_1_L 1 TSSOP-HF R6911
3
33 P3V3S3_EN
U6900 S4_ENABLES 1 2 73 91
2 08 5% Enable FET
1/16W
MF-LF
7 402

MEMVTT_EN SEQUENCE R6912

1
33 2 P5VS3_EN 70 91

=PP3V3_S0_PWRCTL 5% ENABLE REGULATOR

73 64 63 5 1/16W
MF-LF
64 63 10 5 =PP3V3_S5_PWRCTL 402

1
R6951 1
R6952
10K 10K R6915
1
5% 5% 10K
1/16W
MF-LF
1/16W
MF-LF
1
R6916 5%
1/16W
NOSTUFF NOSTUFF
2 402 2 402 100K MF-LF 1
C6920 1
C6921
5% 2 402 0.47UF 0.47UF
DDRVTT_EN 63 71 91
1/16W 10% 10%
MF-LF
NOSTUFF 2 402
CPU_SKTOCC 2
6.3V
CERM-X5R
2
6.3V
CERM-X5R

1 C6951 1
NOSTUFF
C6953 3
402 402

100PF
5% 3
0.1UF D
50V Q6911 10%
2 CERM
402
VTT_REG_PGOOD_L 5
MMDT3904-X-G
16V
2 X5R Q6910
SOT-363-LF 402 2N7002
10 CPU_SKTOCC_L 1 G S SOT23-HF1
4

2
R6950 C
C
6
NOSTUFF
100K 2 Q6911
91 68 64 63 10 CPUVTT_REG_PGOOD 1 CPUVTT_REG_PGOOD_R 2
MMDT3904-X-G
1
R6917 PLACE TOP SIDE
5 =PP5V_S3_PWRCTL
5% SOT-363-LF 0
1/16W NOSTUFF 5% REWORK TO POWER UP WITH NO CPU
MF-LF 1 1/16W
402 1 C6952 MF-LF
2 402
1
R6910
0.47UF 100K
10% 5%
6.3V 1/16W
2 CERM-X5R MF-LF
402
2 402

70 P5VS3_REG_PGOOD PM_EN_USB_PWR 43
MAKE_BASE=TRUE
NOSTUFF
1
C6924
0.47UF =DDRREG_EN 71
10%
6.3V
2 CERM-X5R
402

64 63 10 5 =PP3V3_S5_PWRCTL
SLP_S3 ENABLES
OTHER RAILS ENABLED BY P3V3_S0 AND P5V_S0:

UNUSED R6946 PP1V8_S0 VREG (CPU PLL)

1
33 2 P3V3S0_EN OUT 73 91
64 63 10 5 =PP3V3_S5_PWRCTL 5% Enable FET
1/16W
MF-LF
14 74LVC08 402
4 TSSOP-HF 14 74LVC08
PM_SLP_S3_L 10 TSSOP-HF R6947
B 5
U6900
08
6 91 81 64 47 46 36 26 18 5

9
U6900
8 (PM_SLP_S3_L_BUF) PM_SLP_S3_BUF_L
MAKE_BASE=TRUE
1
33 2 P5VS0_EN OUT 73 91 B
08 5% Enable FET
1/16W
7 NOSTUFF MF-LF
7 402
2 R6944 2 R6941
1% 5%

10K

10K
64 PGOOD_P12V_S0 1/16W 1/16W
MAKE_BASE=TRUE MF-LF
402
MF-LF
402
1 1

PM_SLP_S3_BUF_L 6363

Enable FET
P1V5_S0_EN 73 91
91 71 PM_PGOOD_DDRREG_S3

DDRVTT_EN 63 71 91

Enable regulator

NOSTUFF
NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1
C6947 1
C6941 1
C6945 1
C6946
0.47UF
1
C6944 0.47UF 0.47UF 0.47UF
10% 0.47UF 10% 10% 10%
6.3V 6.3V 6.3V 6.3V
ME RAILS TIED TO S0 ONLY 2 CERM-X5R
10%
6.3V
2 CERM-X5R
2 CERM-X5R
2 CERM-X5R
402
2 CERM-X5R 402 402 402

91 18 PM_SLP_M_L TP_PM_SLP_M_L 402

MAKE_BASE=TRUE

73 64 63 5 =PP3V3_S0_PWRCTL

A 2 R6942
5% SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
10K

1/16W
MF-LF Enable regulator PCHCORE VREG ENABLE FET PAGE TITLE
1
402
PCHCORE_REG_EN 69 91 91 69 64 PCHCORE_REG_PGOOD
MAKE_BASE=TRUE
P1V05_ME_S0_EN POWER SEQUENCING ENABLES
DRAWING NUMBER SIZE
91 73 PGOOD_P5V_S0
MAKE_BASE=TRUE Apple Inc. 051-8337 D
REVISION
1
C6942
1UF
R
A.0.0
10%
6.3V
NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 CERM
Enable regulator
CPUVTT VREG Enable regulator THE INFORMATION CONTAINED HEREIN IS THE
402
CPUVTT_REG_EN 68 91 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
91 68 64 63 10 CPUVTT_REG_PGOOD PM_EN_PVCORE_CPU 65 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MAKE_BASE=TRUE
TO ENABLE OF CPU VREG I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
69 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 63 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PGOOD COMPARATORS FOR PP1V8_S0 AND PP12V_S0
=PP3V3_S0_PWRCTL =PP3V3_S5_PWRCTL
73 64 63 5 64 63 10 5
5 =PP12V_S0_PWRCTL

1
R7020
64.9K 1
R7017
1
R7061
1% 10K
1/16W 10K 5%
MF-LF 5% 1/16W CPUVTT_REG_PGOOD 10 63 68 91
2 402 1/16W MF-LF
MF-LF 2 402
R7007 1
1
R7018 2 402
10K PGOOD_P1V8_S0 64 91
1
49.9K 5% 3
R7021 1% 1/16W
Q7060
D 10K
1%
1/16W
CRITICAL
1/16W
MF-LF
402
2
MF-LF
2 402 3

Q7011
VTTS3PG_2 5
MMDT3904-X-G
SOT-363-LF
D
2
MF-LF
402 8 U7080 PGOOD_1V8_S0_G2 5
MMDT3904-X-G
SOT-363-LF
4

1V60_COMP_REF 6 LM393 6
V+ SOI-HF Q7011
4
R7060 6

R7002 7 PGOOD_1V8_S0_G1 2
MMDT3904-X-G 10K Q7060
91 81 63 47 46 36 26 18 5 PM_SLP_S3_L 1 2 VTTS3PG_1 2
2.0K 2 5 GND SOT-363-LF MMDT3904-X-G
15 12 5 =PP1V8_S0_CPU_PLL 1 1V80_COMP_REF 1
5% SOT-363-LF
1/16W
1% MF-LF 1
4
1/16W 402
MF-LF
402 (1.67V/1.22V; 132mV Hysteresis)

DISABLE CPUVTT_REG_PGOOD WHEN SLP_S3_L = 0 (PER PIKETON PDG)

=PP3V3_S3_PWRCTL
73 5
73 64 5 =PP12V_S5_PWRCTL

1
R7080
33.2K
1
R7086
1% 10K
1/16W
MF-LF 73 64 5 =PP12V_S5_PWRCTL
1
R7084 5%
1/16W
2 402 10K MF-LF
5% 2 402
1/16W
1
C7080 R70831 MF-LF PGOOD_P12V_S0 63

49.9K 2 402
1 0.1UF 3
R7081 20%
1%
1/16W
16V PGOOD_12V_S0_G2 D
100K 2 CERM MF-LF Q7080
1% 603 CRITICAL 402
2
1/16W 2N7002DW-X-G
MF-LF
U7080 6 SOT-363

C 2 402
9V_91_COMP_REF 2
8
LM393
SOI-HF
D Q7080
2N7002DW-X-G
5 G S

4 64 63 10 5 =PP3V3_S5_PWRCTL
=PP3V3_S5_PWRCTL
5 10 63 64 C
V+ SOT-363
1
R7082 PGOOD_12V_S0_G1 2 G S NOSTUFF
1
2.0K 2 GND R7050
89 5 PP12V_S0 1 12V_COMP_REF 3 1 R6902
1
1K
1% 4 100K 5%
1/16W 5% 1/16W
MF-LF 1/16W MF-LF
402 MF-LF 402
2
(9.91V/9.58V; 330mV Hysteresis) 2 402
R6903
0 RSMRST_PWRGD
70
P3V3S5_REG_PGOOD 1 2 OUT 46 91
IN
5% To SMC (2)
1/16W NOSTUFF
MF-LF
402
1 C7050
0.1UF
FROM THIS SMC GENERATES PM_RSMRST_L
10% WHICH GOES INTO RSMRST_L OF PCH
16V
2 X5R DELAY IS ABOUT 200MS
402

S0 RAILS PGOOD

73 64 63 5 =PP3V3_S0_PWRCTL

=PP3V3_S0_PWRCTL 5 63 64 73
73 64 63 5 =PP3V3_S0_PWRCTL
1
R7025 R7032
10K
5% 1
C7022 33
1/16W 0.1UF
1 2 PM_MXM_EN 75
MF-LF
2 402 14 74LVC08 20%
10V
5%
1/16W
91 65 25 PM_PGOOD_PVCORE_CPU 4 TSSOP-HF 2
CERM
MF-LF
402
402
B PM_SPARE_PGOOD 5
U7000
08
6

R7022 SMC
B
7 1
33 2 ALL_SYS_PWRGD_SMC
OUT 46 91

14 74LVC08 5%
1/16W
91 PGOOD_CPU_GFX_DDR 1 TSSOP-HF MF-LF
402 OPTION FOR SMC TO OUPUT
3 91 PGOOD_SYSPWROK
U7000 DELAYED PWRGD (BY 99MS)
91 PGOOD_PCH_AND_P1V8 2 08
R7030
7 0
1 2 SMC_DELAYED_PWRGD IN 47 91

NOSTUFF 5%
1/16W
73 64 63 5 =PP3V3_S0_PWRCTL R7029 MF-LF
402
0
1 2
R7071
5% 33
1/16W 1 2 PM_ME_PWRGD 18 91
MF-LF
402 5%
=PP3V3_S0_PWRCTL 14 74LVC08 1/16W
MF-LF
73 64 63 5
91 64 PGOOD_P1V8_S0 10 TSSOP-HF 402
8 64 63 10 5 =PP3V3_S5_PWRCTL
U7000 R7023
9 08
1
33 2 ALL_SYS_PWRGD_R
OUT 5 91
7 14 74LVC08
14 74LVC08 75 74 5 =PP3V3_S0_MXM =PM_MXM_PGOOD_PULLUP 75 91 PGOOD_SYSPWROK_R 13 TSSOP-HF 5%
1/16W
91 73 PGOOD_P3V3_S0 13 TSSOP-HF MF-LF
11 ALL_SYS_PWRGD 402
11 PGOOD_PCH_S0 U6900
U7000 91
12
91 69 63 PCHCORE_REG_PGOOD 12 08 PULL-UP ON MXM PAGE
08 R7028
7 1
33 2 PM_SYS_PWRGD 18 91
7
5%
APPROXIMATE DELAY OF 10-15MS 91 75 PM_MXM_PGOOD 1/16W

A NOSTUFF
R7024
IBEX PEAK EDS
MF-LF
402
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
10K R7027 PAGE TITLE

NOSTUFF
1
5%
2
1
33 2 PM_PCH_PWRGD 18
POWER SEQUENCING PGOOD
1/16W NOSTUFF 91 DRAWING NUMBER SIZE
R7031
1 MF-LF
402 1 C7023 OPTION FOR PCH PWROK AND SYSPWROK 5%
1/16W 051-8337 D
5%
100K 0.47UF TO BE DRIVEN BY SAME SIGNAL MF-LF
402
Apple Inc. REVISION
1/16W 10%

ALL_SYS_PWRGD CIRCUIT MF-LF

6.3V
2 CERM-X5R
R
A.0.0
2 402 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
ASK INTEL: NEED 100K PULL-DOWN? I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
70 OF 110

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IV ALL RIGHTS RESERVED 64 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CPU CORE REG 1.1V/???A O/P= PPVCORE_S0_CPU_REG

R7118 CPU VCORE
5
=PP5V_S0_VRD 2
2.2 1 89 65 PP5V_S0_CPU_VCORE_VCC
C7104 5% VOUT = VCORE
47PF 1/8W
67 66 5 PPVCORE_S0_CPU_REG 89 VR_CPU_FB_R
1 2
89 VR_CPU_COMP_R MF-LF
805
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.3MM PEAK = ???A
SM R7127 MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V AVG = ???A
1K 5%

D
1 89

OMIT
2 VR_CPU_VSNS_XW_P
VOLTAGE=1.1V
NET_PHYSICAL_TYPE=SNS_DIFF
1
5%
2
R7139
10 89 VR_CPU_VSEN
R7101
50V
CERM
402 0.0022UF
C7105 D
1/16W 1 2 16.5K2
XW7120 R7128 MF-LF
402 5% SIGNAL_MODEL=EMPTY
1 89 VR_CPU_COMP_RC 1 2
VR_CPU_PWM1 OUT 66 89
1
0 2 VR_CPU_VSNS_R_P 1/16W 1%
MF-LF 1/16W 10%
402 NOSTUFF MF-LF 50V
CPU_VCC_PKG_SENSE_P 5%
1/16W 1 C7101 402 R7179 CERM
402 LOCAL 5V R7131 R7132
89 50 12 IN MF-LF 0 0
402 1.25 mOhm loadline 0.0022UF 1 2
NOSTUFF NOSTUFF 165 VR_CPU_ISNS1_RR_2 2 1
89 12 CPU_VCC_PKG_SENSE_N 10%
5% R7148 R7144
1 2
IN 50V
2 CERM 1/16W R7147 1% 5%
R7129 R7137 402 MF-LF
402 NOSTUFF 1 C7107 1 1 1
1/16W
MF-LF
1/16W
MF-LF
0 10 VR_CPU_RGND 402
1 2 VR_CPU_VSNS_R_N 1 2
89

R7103 R7146 1R7104

1 1UF
10% 5%
0
5%
0 0 NOSTUFF
402
DIFFERENTIAL_PAIR=VR_CPU_ISNS1
R7102 1M 0 10V 5% 1 C7132
5%
1/16W
5%
1/16W 1 C7102 1 C7103 1K VR_VDF_R1 1
287 2
5% 5%
2 X5R 1/16W
MF-LF
1/16W
MF-LF 1/16W C7130 1 1 C7131 0.1UF
1 C7133 VR_CPU_ISNS1_P IN 66 89
XW7130 MF-LF
R7138 MF-LF
0.0022UF 1 2 1/16W
MF-LF 1/16W 402 402 2 402 2 MF-LF
402 2 15PF 10% 220PF
SM 402
1K
402 0.0022UF 10% 1% MF-LF 1% 150PF 16V 5%
VR_CPU_ISNS1_N
2 402

19
10% 1% AGND_CPU 65 50V 25V
1 2 89 VR_CPU_VSNS_XW_N 1 2 2 50V 1/16W 1/16W 2 402 C0G 2
5% 2 X5R 2 CERM IN 66 89
VOLTAGE=0V 2 50V
CERM CERM MF-LF MF-LF
402 2 50V
CERM 402 402 DIFFERENTIAL_PAIR=VR_CPU_ISNS1
402 402 VCC
NET_PHYSICAL_TYPE=SNS_DIFF 5% 402 402 402
OMIT 1/16W VR_CPU_COMP 13 COMP CRITICAL 26
MF-LF AGND_CPU
89
SYM_VER_2 PWM1
402 65

PP5V_S0_CPU_VCORE_VCC
C7106
470PF
R7149 89 VR_CPU_FB 14 FB U7100ISEN1+ 28 89 VR_CPU_ISNS1_R_P R7133
89 65
1 2 VR_VDF_R2 1 47.5 2 QFN
ISEN1- 27 VR_CPU_ISNS1_R_N 1
1.02K2

ISL6334
89

NOSTUFF NOSTUFF NOSTUFF 10% 1% 1%

1/16W 1/16W
R71001 R71051 R71781 R71771 50V
CERM MF-LF VR_CPU_VDIFF 15 VDIFF MF-LF
VR_HOT goes HIGH when VTM/VCC < 28% 1.02K 20.0K 0 0 402 402 17 VSEN R7140 402
and LOW when VTM/VCC > 33%. 1% 1% 5% 5%
16 RGND 0 VR_CPU_PWM2
1/16W
MF-LF 1/16W 1/16W
MF-LF
1/16W
MF-LF PWM2 20 89 VR_CPU_PWM2_R 2 1
OUT 66 89
402 2 MF-LF 402 2 402 2
402 2 5%
1/16W
18 TCOMP ISEN2+ 22 89 VR_CPU_ISNS2_R_P MF-LF
89 VR_CPU_TCOMP 402
R7141
LAYOUT: PLACE RT7101 NEAR HOT SPOT. ISEN2- 21 89 VR_CPU_ISNS2_R_N
165
R7142
1 2 VR_CPU_ISNS2_RR_2 2
0 1
VR_CPU_OFS 9 OFS
1%

C
5%
C
1 1/16W 1/16W
1 R7106 1 R7107 MF-LF
1 C7180 R7108
1 1
R7109 89 VR_CPU_FS 34 FS
PWM3 31 VR_CPU_PWM3_R
402 MF-LF
402
RT7101 0.1UF 0 21K 75K 100K
89
NOSTUFF
DIFFERENTIAL_PAIR=VR_CPU_ISNS2

6.8K 20% 5%
1/16W
1%
1/16W
1%
1/16W 1%
1/16W VR_CPU_SS 35 SS C7140 1 1 C7141 1 C7142 1 C7143 VR_CPU_ISNS2_P IN 66 89
2 10V 150PF 0.1UF 220PF
89
CERM MF-LF MF-LF MF-LF MF-LF R7110 ISEN3+ 29 89 VR_CPU_ISNS3_R_P 15PF
0603 402 2 402 2 402 2 402 2 402 C7110 1% 5% 10% 5% VR_CPU_ISNS2_N
ISEN3- 30 50V 16V 25V IN 66 89
1K 11 DAC 89 VR_CPU_ISNS3_R_N 50V 2 2 CERM 2 X5R 2 CERM
2 1500PF 1 2 89 VR_CPU_DAC C0G 402 402 402 DIFFERENTIAL_PAIR=VR_CPU_ISNS2
402
AGND_CPU 1 2 1%
65
1/16W
MF-LF VR_CPU_REF 12 REF R7143
10% 402
89
1
1.02K2
25V
X7R
39 TM PWM4 25 VR_CPU_PWM4_R 89 1%
402 89 VR_CPU_TM 1/16W

63
PM_EN_PVCORE_CPU R7111
1
0 2 VR_CPU_EN_VTT 33 EN_VTT ISEN4+ 23 R7150
MF-LF
402
IN
5% ISEN4- 24 0
1/16W 36 VR_RDY 2 1 VR_CPU_PWM3 OUT 66 89
MF-LF
89 65
PP5V_S0_CPU_VCORE_VCC 402 7 VID0
5%
1/16W
MF-LF
R7151 R7152
165 0
5
=PP3V3_S0_VRD NOSTUFF
6
5
VID1 402 1 2 VR_CPU_ISNS3_RR_2 2 1
VID2 1%
=PPVTT_S0_CPU R7112 1 1 C7109 4 1/16W
MF-LF
5%
1/16W
0.01UF VID3 MF-LF
47 15 12 10 5 2.0K 10% 3 402 402 DIFFERENTIAL_PAIR=VR_CPU_ISNS3
5% VID4 VR_CPU_ISNS3_P
NOSTUFF 1/16W
MF-LF
2 16V
CERM R7114 R7115 2 VID5
NOSTUFF 1 C7153 IN 66 89

R71721 402 2 402

1 1 1 VID6 C7150 1 1 C7151 1 C7152 5%
220PF
1.02K 15PF 150PF 0.1UF 25V
2 CERM VR_CPU_ISNS3_N
1% 40 VID7 5% IN 66 89
1/16W 49.9K 49.9K 1%
50V 50V
2 CERM
10%
16V 402
DIFFERENTIAL_PAIR=VR_CPU_ISNS3
MF-LF 1% 1% C0G 2 2 X5R
402 2 1/16W 1/16W 402 402 402
PM_PGOOD_PVCORE_CPU MF-LF MF-LF 8 PSI*
91 64 25 OUT 402 2 2 402 R7153
1.02K2
1
VR_CPU_PSI_L
1%
0 1/16W
VR_CPU_IOUT R7145
B 88 12 OUT
NOSTUFF
1
5%
2
VR_CPU_IMON 10 IMON MF-LF
402 B
1/16W
VR_CPU_FAN 37 VR_FAN
D7171 MF-LF
402
89
AGND_CPU 65
CPU_PSI_L
NSR0140P2T5G R7117
1
38 VR_HOT
89 12 IN
2 1 10K VR_CPU_VRDHOT EN_PWR 32
VR_CPU_IOUT_PD

1%
SOD-923-HF
1/16W
MF-LF
1 C7112 THRM_PAD
NOSTUFF 0.022UF
2 402

41
10% 89 50 OMIT
16V OUT
R7171 1 C7171 2 CERM-X5R
402 SM
XW7101
0 0.020UF
1 2 10%
50V R7116
1
65 AGND_CPU 1 2
5%
2 CERM 1.54K MAX_NECK_LENGTH=3MM
1/16W 402 1% MIN_NECK_WIDTH=0.3MM
MF-LF 89 1/16W MIN_LINE_WIDTH=0.6MM
402 MF-LF VOLTAGE=0V
2 402

89 15 12 IN
CPU_VID<7..0> 7

6 R7136
1
10K 2 VR_CPU_EN_PWR
5

4 5%
1/16W
3 MF-LF
402
R71351 1
2
1K 0.001UF
5% 10%
1 1/16W 50V
MF-LF 2 CERM
0 402 2 402
C7135
CRITICAL

L7100
A 1UH-20A-4.5MOHM SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
=PP12V_S0_VRD PP12V_S0_CPU_FLTRD PAGE TITLE
5

IMAX = 10.5A
1
TH-VERT-HF
2
NET_PHYSICAL_TYPE=POWER
VOLTAGE=12V
66 89
VREG: PPVCORE_S0_CPU
DIDT=TRUE DRAWING NUMBER SIZE
152-0110
Apple Inc. 051-8337 D
CPU CORE INPUT Filtering REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
71 OF 110

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 65 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
89 65
PP12V_S0_CPU_FLTRD
CRITICAL CRITICAL CRITICAL THESE TWO CAPS ARE FOR EMC
1
C7270 1
C7271 Q7201
CRITICAL
CRITICAL CRITICAL
270UF 270UF NOSTUFF
376S0772 IRF6710
1
C7205 1 1 C7215 1
20%
R7201 C7206 C7207 1 C7210 1 C7211
PHASE 1
2 16V
20%
2 16V R7202 1 R7205 1 S1
1
270UF 10UF 10UF 1UF 0.001UF 0.001UF
ELEC ELEC 20% 10%
8X9-TH1 10 1 10 10% 10% 10% 10%
8X9-TH1
5% 0 5%
D
2 2 16V
ELEC 2 16V 2 16V
X5R-CERM 2 16V 2 50V 2 50V
1/10W 5% 1/10W 8X9-TH1 X5R-CERM 0805 X5R X7R X7R
MF-LF 1/10W MF-LF 5 0805 603 402 402
603 2 MF-LF
603 2 2 603 4 G 6
VR_CPU_DRV1_VCC VR_CPU_DRV1_PVCC CRITICAL R7208
NET_PHYSICAL_TYPE=VR_CTL_PHY 3 S CRITICAL 0.0005
NET_PHYSICAL_TYPE=VR_CTL_PHY
1 C7201 L7201 1%

D VR_CPU_DRV1_UVCC
NET_PHYSICAL_TYPE=VR_CTL_PHY
1UF
10%
2 16V
89 VR_CPU_BOOT1_RC
NET_PHYSICAL_TYPE=VR_CTL_PHY
0.36UH-35A
1 2 89 PPVCORE_S0_CPU_REG1
1W
MF
0612
PPVCORE_S0_CPU_REG 5 65 66 67 D
X5R 1 C7203 1 2
603
R72041 DIDT=TRUE 0.22UF MSQ1208-TH 3 4

7
10%
VCC UVCC LVCC
5%
0
2 16V
X7R
R72061 152-0114
U7201 1/10W
MF-LF 603 5%
1
ISL6622 603 2 1/8W
MF-LF
DFN 805 2
VR_CPU_DRV1_GDSEL 3 GDSEL
89
BOOT 2 89 VR_CPU_DRV1_BOOT
NOSTUFF NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE VR_CPU_PH1_SNUB 89
C7202 1 1 C7200 1
R7207 UGATE
CRITICAL 1 89 VR_CPU_DRV1_UGATE 1 2 6 7
NET_PHYSICAL_TYPE=VR_CTL_PHY
1UF 1UF NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE CRITICAL DIDT=TRUE
0 D
10% 10% PHASE 10 VR_CPU_PHASE1 1 C7208
16V 2
X5R 2 16V
X5R
5%
1/10W
MF-LF
89

NET_PHYSICAL_TYPE=POWER DIDT=TRUE Q7202 1000PF

603 603 603 4 PWM LGATE 6 89 VR_CPU_DRV1_LGATE 5 G IRF6795 5%
2 DIDT=TRUE DIRECTFET-MX 25V
2 NP0-C0G
NET_PHYSICAL_TYPE=VR_CTL_PHY S
THRML 402
GND PAD
376S0771 3 4 VR_CPU_ISNS1_P

11
OUT 65 89

VR_CPU_PWM1
89 65 IN VR_CPU_ISNS1_N OUT 65 89

CRITICAL THESE TWO CAPS ARE FOR EMC

CRITICAL CRITICAL CRITICAL
376S0772 Q7221 1
C7225 1 C7226 1 C7229 1 C7227 1 C7230 1 C7231
PHASE 2
IRF6710
NOSTUFF 1
R7221 S1 270UF 10UF 10UF 1UF 0.001UF 0.001UF
R72221 R72251 10
1 20% 10%
16V
10%
16V
10% 10% 10%
2 16V 2 16V 2 50V 2 50V
D
10 5% 2 ELEC 2 X5R-CERM 2 X5R-CERM X5R X7R X7R
5% 0 1/10W 8X9-TH1 0805 0805 603 402 402
1/10W 5% MF-LF 5

C VR_CPU_DRV2_VCC
MF-LF
603 2
1/10W
MF-LF
603 2
2 603 4 G 6
CRITICAL C
NET_PHYSICAL_TYPE=VR_CTL_PHY VR_CPU_DRV2_PVCC 3 S
CRITICAL
R7228
0.0005
VR_CPU_DRV2_UVCC NET_PHYSICAL_TYPE=VR_CTL_PHY
89 VR_CPU_BOOT2_RC L7221 1%
1W PPVCORE_S0_CPU_REG
NET_PHYSICAL_TYPE=VR_CTL_PHY 0.36UH-35A MF 5 65 66 67
NET_PHYSICAL_TYPE=VR_CTL_PHY PPVCORE_S0_CPU_REG2 0612
NOSTUFF
1 C7221 1 2 89
1 2
C7222 1 1 C7220 1UF R72241 DIDT=TRUE MSQ1208-TH 3 4
7

10%
9

1UF 1UF 16V 1 C7223 152-0114

10% 10% VCC PVCC 2 X5R 0
16V 2 16V 603 5% 0.22UF R72261
X5R
603
2 X5R
603
U7221 1/10W
MF-LF
10%
2 16V 1
ISL6612 603 2 X7R 5%
603 1/8W
QFN1 MF-LF
805 2
4 PWM BOOT 2 89 VR_CPU_DRV2_BOOT
89 65 IN
VR_CPU_PWM2 CRITICAL NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE VR_CPU_PH2_SNUB 89
UGATE 1 89 VR_CPU_DRV2_UGATE 1 2 6 7
NET_PHYSICAL_TYPE=VR_CTL_PHY
NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE D CRITICAL DIDT=TRUE
PHASE 10 VR_CPU_PHASE2 1 C7228
89 VR_CPU_DRV2_GDSEL 3 NC
89

NET_PHYSICAL_TYPE=POWER DIDT=TRUE Q7222 1000PF

NOSTUFF 8 NC LGATE 6 89 VR_CPU_DRV2_LGATE 5 G IRF6795 5%
DIRECTFET-MX 25V
2 NP0-C0G
R7227
1
THRML
NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE S 402
0 GND PAD
5%
376S0771 3 4 VR_CPU_ISNS2_P
5

1/10W OUT 65 89
MF-LF
2 603
VR_CPU_ISNS2_N OUT 65 89

CRITICAL CRITICAL THESE TWO CAPS ARE FOR EMC

CRITICAL CRITICAL
B Q7241 1
C7245
270UF
1 C7246 1 C7249 1 C7247 1 C7250 1 C7251 B
PHASE 3
1 IRF6710 10UF 10UF 1UF 0.001UF 0.001UF
NOSTUFF R7241
R72421 R7245 1
10 376S0772 S1
1
20% 10% 10% 10% 10% 10%
10 5% D
2 16V
ELEC 2 16V
X5R-CERM
16V
2 X5R-CERM2 16V
X5R
50V
2 X7R
50V
2 X7R
5% 0 1/10W 2 8X9-TH1 0805 0805 603 402 402
1/10W 5% MF-LF
MF-LF 1/10W 5
603 2 MF-LF 2 603
603 2 4 G 6
VR_CPU_DRV3_VCC CRITICAL R7248
NET_PHYSICAL_TYPE=VR_CTL_PHY VR_CPU_DRV3_PVCC 3 S CRITICAL 0.0005
VR_CPU_DRV3_UVCC NET_PHYSICAL_TYPE=VR_CTL_PHY 89 VR_CPU_BOOT3_RC L7241 1%
1W PPVCORE_S0_CPU_REG
NET_PHYSICAL_TYPE=VR_CTL_PHY NET_PHYSICAL_TYPE=VR_CTL_PHY 0.36UH-35A MF 5 65 66 67
PPVCORE_S0_CPU_REG3 1 0612
NOSTUFF
1 C7241 DIDT=TRUE
1 2 89
2
1UF R72441
C7242 1 1 C7240 MSQ1208-TH 3 4
7

10% 1
9

1UF 1UF 16V

2 X5R 0 C7243 152-0114
VCC PVCC 0.22UF
10% 10% 603 5% 10% R72461
16V 2
X5R 2 X5R
16V U7241 1/10W
MF-LF 2 16V
X7R 1
603 603 ISL6612 603 2 603
376S0771
5%
1/8W
QFN1 MF-LF
805 2
4 PWM BOOT 2 89 VR_CPU_DRV3_BOOT 1 2 6 7
VR_CPU_PWM3 CRITICAL NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE VR_CPU_PH3_SNUB 89
89 65 IN UGATE 1 D CRITICAL
VR_CPU_DRV3_UGATE NET_PHYSICAL_TYPE=VR_CTL_PHY
PHASE 10
89

89 VR_CPU_PHASE3
DIDT=TRUE Q7242 1 C7248
DIDT=TRUE
89 VR_CPU_DRV3_GDSEL 3 NC DIDT=TRUE 5 G IRF6795
NOSTUFF 89 VR_CPU_DRV3_LGATE
DIRECTFET-MX 1000PF
8 NC LGATE 6 S 5%
1
R7247 NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE 2 25V
NP0-C0G VR_CPU_ISNS3_P
0 THRML NET_PHYSICAL_TYPE=POWER 3 4 402 OUT 65 89
5% GND PAD NET_PHYSICAL_TYPE=VR_CTL_PHY
1/10W
VR_CPU_ISNS3_N
5

MF-LF 65 89
OUT
2 603

A A
OUTPUT BULK DECOUPLING: 128S0209
PPVCORE_S0_CPU_REG
SYNC_MASTER=K74_MASTER
PAGE TITLE
SYNC_DATE=N/A

5 65 66 67 VREG: CPU CORE - PHASES 1-3

DRAWING NUMBER SIZE
???A MAX 051-8337 D
Apple Inc.
1
C7260 1
C7261 1
C7262 1
C7263 1
C7264 REVISION
330UF-0.0045OHM
20% 20%
330UF-0.0045OHM 330UF-0.0045OHM
20%
330UF-0.0045OHM
20%
330UF-0.0045OHM
20%
R
A.0.0
2 2V
POLY
2 2V
POLY
2 2V
POLY
2 2V
POLY
2 2V
POLY
NOTICE OF PROPRIETARY PROPERTY: BRANCH
CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
72 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 66 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C

66 65 5
PPVCORE_S0_CPU_REG

1 C7330 1 C7331 1 C7332 1 C7333 1 C7334 1 C7335 1 C7336 1 C7337 1 C7338 1 C7339
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402

1 C7340 1 C7341 1 C7342 1 C7343 1 C7344 1 C7345 1 C7346 1 C7347 1 C7348 1 C7349
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603

B B

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

VREG: CPU CORE - CAPS

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 67 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CPU VTT REG 1.1V O/P= PPVTT_S0_CPU_REG

50 OUT CPUVTT_IMON R7467 5 =PP12V_S0_CPU_VTT_VREG

DIDT=TRUE
2.2
OUT CPUVTT_REG_PGOOD
91 64 63 10 1 2
5% THESE TWO CAPS ARE FOR EMC
D
1/10W
MF-LF
603
R7460
R7480 CRITICAL CRITICAL
D
2.2 1CRITICAL 1CRITICAL 1
=PP5V_S0_CPU_VTT_VREG 1
2.2
2 5V_S0_VTTREG_VIN
PP12V_S0_CPU_VTT_VREG_VIN 1 2 1
C7434 C7426 C7420 C7421 1 C7422 1 C7423 1 C7424 1 C7425
5 VOLTAGE=12V 10UF 10UF 1UF 0.01UF 0.01UF
VOLTAGE=5V 0.6 mm 5% 100UF 270UF 270UF
5% 0.6 mm 0.2 MM 1/10W 20% 20% 20% 10% 10% 10% 20% 20%
1/10W MF-LF 16V 16V 16V 16V 16V
0.2 MM 1 2 16V 2 16V 2 16V 2 X5R-CERM 2 X5R-CERM 2 X5R 2 CERM 2 CERM
MF-LF C7430 603 376S0772 POLY ELEC ELEC
603 6.3X6-TH 8X9-TH1 8X9-TH1 0805 0805 603 402 402
1UF
5 =PP3V3_S0_CPU_VTT_VREG
NOSTUFF 5V_S0_VTTREG_VDD 10% Q7420
C7465 1 C7461 1 VOLTAGE=5V
1 C7462 2 16V IRF6710
X5R S1
1UF 1UF 0.6 mm 1UF 402 1
1 1NOSTUFF 1NOSTUFF NOSTUFF
1 10% 10% 0.2 MM 10% D
R7490 R7491 R7492 R7484 16V 16V 16V GND_CPUVTTS0_AGND 68 2
X5R 2 X5R 2 2 X5R

22
20.0K 20.0K 20.0K 20.0K 1
1% 1% 1% 1% R7461 402 402 402 5
1/16W 1/16W 1/16W 1/16W 1K VDD PVCC 4 G 6
MF-LF MF-LF MF-LF MF-LF 5% (CPUVTTS0_UGATE)
2 402 2 402 2 402 402 2 1/16W MIN_LINE_WIDTH=0.5 MM

VTT_REG_VID0
MF-LF
2 402
U7401 MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE 3 S

1 RBIAS QFN DIDT=TRUE

CPUVTTS0_RBIAS VIN 14

ISL9563A
R7474 C7464
CPUVTTS0_SOFT 2 SOFT 0 0.22UF
VTT_REG_VID1 UGATE 18 CPUVTTS0_UGATE 1 2 MCPCORES0_BOOT_R
0.25 MM
1 2
CRITICAL
R7420
0.0005
28 IMON BOOT 17 CPUVTTS0_BOOT
5%
1/10W
0.2 MM
DIDT=TRUE
16V
X7R
L7420 1%
1W
0.2 MM
0.25 MM
MF-LF
603
603 0.36UH-45A-0.76MOHM MF
31 10%
VTT_REG_VID2 PGOOD PHASE 19 DIDT=TRUE
1 2 2
0612
1
CPUVTTS0_PHASE (CPUVTTS0_PHASE) CPUVTTS0_PHASE_L PPVTT_S0_CPU_REG 5 68
24 VID0 MIN_LINE_WIDTH=0.5 MM SWITCHNODE MIN_LINE_WIDTH=0.5 MM
NOSTUFF MIN_NECK_WIDTH=0.2 MM MSQ1211R36LF-TH MIN_NECK_WIDTH=0.2 MM 4 3
25 VID1 SWITCH_NODE=TRUE DIDT=TRUE
1 1 1 DIDT=TRUE
R7493 R7494 R7495 26 VID2 CRITICAL 1 C7463
20.0K 20.0K 20.0K 1000PF
1% 1% 1% VTT_REG_VID3 27 VID3
1/16W 1/16W 1/16W 1 2 6 7 5%
23 25V
MF-LF MF-LF MF-LF 1 NC NC 2 NP0-C0G
2 402 2 402 2 402 R7483 29 D 376S0771 402
91 63 IN CPUVTT_REG_EN VR_ON DIDT=TRUE
20.0K
1% CPUVTTS0_FDE 30 AF_EN LGATE 21 CPUVTTS0_LGATE Q7421 MCPCORES0_SNUBBER
MIN_LINE_WIDTH=0.4MM
1/16W
32 (CPUVTTS0_LGATE) 5 G IRF6795 MIN_NECK_WIDTH=0.4MM
MF-LF FDE DIRECTFET-MX
C 402 2
CPUVTTS0_VSEN
CPUVTTS0_RTN
8
9
VSEN
RTN
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
DIDT=TRUE
S 1
R7462
1
CPUVTTS0_ISP_R
C
3 4
5%
1/10W
CPUVTTS0_VW 4 VW MF-LF
2 603 (CPUVTTS0_V0)
1
VO 12 CPUVTTS0_VO R7464
1K
1%
CPUVTTS0_COMP 5 COMP OCSET 3 CPUVTTS0_OCSET 1/16W
MF-LF
2 402
CPUVTTS0_FB 6 FB ISP 13 CPUVTTS0_ISP
ISN 11 CPUVTTS0_ISN
CPUVTTS0_VDIFF 7 VDIFF
1 1NOSTUFF
ICOMP 10 CPUVTTS0_ICOMP R7469 1 C7473 R7470
12.4K 0.01UF 10K
68 5 PPVTT_S0_CPU_REG PGND VSS THRM_PAD 1% 10% 1%
1/16W 50V 1/16W
MF-LF 2 X7R MF-LF

33
1
R7463 (CPUVTTS0_VO) 2 402 402 2 402
100 1
1% C7476 1 R7472
1/16W 0.1UF 150K 1
MF-LF 10% 1% R7473 1 1
R7466 2 402 16V 1/16W C7477 C7478
X7R-CERM 2 MF-LF 10K 0.1UF 0.1UF
20 (CPUVTTS0_VSEN) 402 2 402 1% 10% 10%
89 12 CPU_VTTSENSE_P 1 2 1/16W
MF-LF 2 25V
X5R 2 25V
X5R
1%
1/16W 1 C7470 (CPUVTTS0_ISP) 2 402 402 402
MF-LF
402 0.001UF (CPUVTTS0_ISN)
10%
R7468 2 50V
20 X7R
CPU_VTTSENSE_N 1 2 402 1
89 12
(CPUVTTS0_RTN) XW7461 R7475
1% SM 45.3K
1/16W
MF-LF 1 2
1%
1/16W
OUTPUT BULK DECOUPLING
402
1
68 GND_CPUVTTS0_AGND MF-LF
OMIT PPVTT_S0_CPU_REG
B R7471
100
1%
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM (CPUVTTS0_ICOMP)
2 402 68 5

B
1/16W
MF-LF 1
C7444 1
C7445 1
C7446 1
C7447 1 C7428 1 C7429
2 402 330UF-0.0045OHM 330UF-0.0045OHM 330UF-0.0045OHM 330UF-0.0045OHM 22UF 22UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V
2 2V 2 2V 2 2V 2 2V 2 CERM-X5R 2 CERM-X5R
POLY POLY POLY POLY
CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM 805 805

(CPUVTTS0_VW)

C7479 1
0.001UF
C7480 10%
50V
33PF X7R 2 1
1 2 402 R7476
6.65K
5% 1%
1/16W
50V 1.1V DEFAULT, OTHER VALUES TBD
CERM C7481 MF-LF
R7477 402 0.0022UF 2 402
56.2K 1 2
1 2 CPUVTTS0_COMP_C
(CPUVTTS0_COMP)
1%
1/16W 10% VID<2:0> Voltage
MF-LF 50V
402 CERM
402 (CPUVTTS0_FB) 000 +1.100V
C7482
R7478 560PF
100 1 2
1 2 CPUVTTS0_VDIF_C
1%
1/16W 10%
MF-LF R7479 50V
402
1
2.21K2 CERM
402
(CPUVTTS0_VDIFF)
A 1%
1/16W
MF-LF
402
SYNC_MASTER=NICK SYNC_DATE=12/08/2009 A
PAGE TITLE

CPU VTT REGULATOR

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 68 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

IBEX PEAK CORE REG 1.05V OUTPUT = PP1V05_S0_REG

PP1V05_S0_REG
VOUT = 1.05V
PEAK = 7.5A
AVG = 3A
C 5
=PP12V_S0_PCH_CORE_VREG C
OP_1V05_S0_FB

5
=PP5V_S0_PCH_CORE_VREG NET_PHYSICAL_TYPE=POWER R7651
200K 2
89 PCHCORE_REG_TON 1
C7601 1

23 20 17 5
=PP3V3_S0_PCH 1
R7670
300
10UF
20%
1%
1/16W
MF-LF
402
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
6.3V
5% X5R 2
1/16W 603
MF-LF CRITICAL CRITICAL CRITICAL
R76801 2 402 PCHCORE_REG_5V_FLT
R7650 1 C7611
10K 89 PCHCORE_REG_BOOT 2 0 1 89 PCHCORE_REG_BOOT_R
1 C7610 0.1UF
1 C7612 1 C7613 1 C7620 1 C7621
1% 10UF 10% 10UF 10UF 0.001UF 0.001UF

10
2 16V

4
1/16W 10% 10% 10% 10% 10%
MF-LF
402 2
5%
1/10W C7650 16V
2 X5R-CERM
X5R
402
16V
2 X5R-CERM
16V
2 X5R-CERM
50V
2 X7R
50V
2 X7R
V5FILT V5DRV
MF-LF
603
0.1UF 0805 0805 0805 402 402
2 1
PCHCORE_REG_PGOOD U7600 DIDT=TRUE
91 64 63 OUT TPS51117RGY_QFN14 MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM 10%

2
QFN 25V
MIN_LINE_WIDTH=0.6MM X5R CRITICAL
SYM 2 402
91 63 IN
PCHCORE_REG_EN 1 EN_PSV TON 2
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE D1 Q7601
CRITICAL RJK0384DPA CRITICAL
L7614
(PP1V05_S0_FB)
6 PGOOD

3 VOUT
VBST 14
DIDT=TRUE MIN_NECK_WIDTH=0.2MM
1 G1 WPAK
376S0801 1.0UH-13A-5.6M-OHM PP1V05_S0_REG
DRVH 13 89 PCHCORE_REG_UGATE MIN_LINE_WIDTH=0.6MM S1/D2 7 1 2
5
NET_PHYSICAL_TYPE=POWER
89 PCHCORE_REG_VFB 5 VFB LL 12 89 PCHCORE_REG_PHASE SWITCHNODE SM-IHLP-1
DIDT=TRUE MIN_LINE_WIDTH=0.6MM
NOSTUFF
89 PCHCORE_REG_TRIP 11 TRIP DRVL 9 89 PCHCORE_REG_LGATE
MIN_NECK_WIDTH=0.2MM
6 G2 1 C7614 XW7614
B GND THRM_PAD PGND
DIDT=TRUE MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
5%
1000PF
SM
1 2 B
15

S2 25V
OUTPUT BULK DECOUPLING
7

2 CERM OMIT
R7660
1
603

5
6.98K
1% NOSTUFF
PCHCORE_REG_PHASE_C
1/16W
MF-LF
PCHCORE_PGND_XW 1
R7615 CRITICAL CRITICAL CRITICAL
2 402 1
NOSTUFF
R7614
8.45K
1%
1
C7607 1 C7608 1 C7609
330UF 10UF 10UF
XW7600 XW7601
SM
0.499
1%
1/16W
MF-LF 20%
2 6.3V
10%
16V
10%
16V
SM 1/10W 2 402 POLY-TANT 2 X5R-CERM 2 X5R-CERM
1 2 MF CASE-D3L-SM 0805 0805
1 2
OMIT 2 603
OMIT
(PPCHCORE_REG_FB)
1
R7616
21K
1%
1/16W
MF-LF
1 C7670 2 402
1UF
10%
16V
2 X5R
402 AGND_PCHCORE_REG

Vout= 0.75*( 1+R7615/R7616)

Vout= 0.75*( 1 + 8.45/21) = 1.05

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

IBEX PEAK CORE

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 69 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
3V3 S5 REGULATOR C7766 1 C7783
5V S3 REGULATOR
1 1 1 1 1 1
C7751 C7752 C7753 C7758 C7765
270UF 22UF 10UF 10UF 10UF 10UF 10UF
20% 20%

5
=PP12V_S5_P5VS3_VREG 16V
ELEC
2
16V
X7R 2
10%
16V
2
10%
16V
2
10%
16V
2
10%
16V
2
10%
16V
2
X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM
8X9-TH1 1210
NET_PHYSICAL_TYPE=POWER 0805 0805 0805 0805 0805

5
=PP12V_S5_P3V3S5_VREG EMC CAPS
PLACE CLOSE TO FET
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
Power Rating ?
C7718 1 C7719 1 C7712 1 C7710 1 1 C7711 1 C7722
100UF 100UF 10UF 10UF 0.1UF 0.1UF
20% 20% 10% 10% 10% 10%
16V 16V
16V 2 16V 2 X5R-CERM 2 X5R-CERM 2 2 16V
X5R 2 16V
X5R
POLY POLY
6.3X6-TH 6.3X6-TH 0805 0805 402 402

PP5V_S5_LDO 5

EMC: C7754,C7755
3V3 OUTPUT PLACE AT Q7330

2
CRITICAL
RJK0384DPA
Q7710 D1
C7754 1 C7755 1 5V OUTPUT
PP3V3_S5_REG L7710 WPAK G1 1 (P3V3S5_UGATE)
0.1UF
10%
0.1UF
10%
5 2.2UH-14A 376S0801 MIN_NECK_WIDTH=0.2MM
NET_PHYSICAL_TYPE=POWER 25V
2 25V
2
1 2 SWITCHNODE NET_PHYSICAL_TYPE=POWER 7 S1/D2 MIN_LINE_WIDTH=0.6MM 1 C7742 1
R7740 X5R
402
X5R
402

C MMD06CZ-SM
1
DIDT=TRUE
C7730
GATE_NODE=TRUE 4.7UF
20%
6.3V
2 CERM
5%
2.2
1/8W
DIDT=TRUE
EMC: C7763,C7764
PLACE AT L7750.2
C
C7790 1000PF G2 6 (P3V3S5_LGATE) 603 MF-LF
8200PF R7790 5% MIN_NECK_WIDTH=0.2MM 2 805 5
16.5K 2 25V
NP0-C0G MIN_LINE_WIDTH=0.6MM P5V_S5_LDO_R P5VS3_REG_PGOOD
50V 1 2 CERM 1 2
402 GATE_NODE=TRUE OUT 63
C7763 1 C7764 1
10% 603 1% NOSTUFF
S2
D CRITICAL 0.001UF 0.001UF
10% 10%
1/16W P5V_S5_VCC1
Q7750 50V 2

3
1
MF-LF 1 C7741 4 G
50V
X7R 2 X7R
R7791 402
NOSTUFF C7740 1 1UF MIN_LINE_WIDTH=0.6MM
CSD58851Q5A 402 402
16.5K 1 10% MIN_NECK_WIDTH=0.2 MM MLP5X6-LFPAK-Q5A
1%
R7730 1UF 16V
2 X5R
0.499 10% 376S0631

P5VS3_REG_BOOT_R
1/16W 16V 603

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2 MM
MF-LF 1% X5R 2 S
2 402 1/10W 603
MF CRITICAL
2 603 1 2 3 L7750
C7756

VCC1 5

4
R7750 2.2UH-10A-12.5MOHM
0.1UF

VCC2
2
0 1 2 1 1 2 PP5V_S3_REG 5 92
P3V3S5_REG_SNUB 18 LDO5 VIN 17 SWITCHNODE PAB0705AR-SM
89
C7714 R7710 5% DIDT=TRUE
DIDT=TRUE 10%
1
X7R
2 89 P3V3S5_REG_BOOT_R 1
0
2
U7700 FCCM 3 TP_P5VS3_REG_FCCM
1/10W
MF-LF
10%
25V
X5R NOSTUFF
DIDT=TRUE NET_PHYSICAL_TYPE=POWER NET_PHYSICAL_TYPE=POWER
50V 603-1 MIN_NECK_WIDTH=0.2MM
5%
ISL62383 603
402 C7757 1
MIN_LINE_WIDTH=0.6MM 64 OUT P3V3S5_REG_PGOOD 7 PGOOD1 PGOOD2 1
0.1UF DIDT=TRUE 1/10W QFN MIN_NECK_WIDTH=0.2 MM 0.001UF C7770
MF-LF CRITICAL MIN_LINE_WIDTH=0.6MM 10%
50V
R7770 0.01UF
(P3V3S5_PHASE)
603
89 P3V3S5_REG_UGATE 14 UGATE1 UGATE2 22 89 P5VS3_REG_UGATE CERM 2 CRITICAL 14.3K 1 2 OUTPUT BULK DECOUPLING:
DIDT=TRUE 2 1
15 BOOT1
DIDT=TRUE 402 D7750
89 P3V3S5_REG_BOOT BOOT2 21 89 P5VS3_REG_BOOT CTLSH3-30M833 1% 1/16W 10%
16V
402
CERM
MIN_NECK_WIDTH=0.2MM DIDT=TRUE DIDT=TRUE 402 MF-LF
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2 MM 5V_SNUBBER CRITICAL CRITICAL
89 P3V3S5_REG_PHASE 13 PHASE1 PHASE2 23 89 P5VS3_REG_PHASE MIN_LINE_WIDTH=0.6MM TLM833
MIN_NECK_WIDTH=0.2MM DIDT=TRUE DIDT=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.4MM
1 C7760 C7761 1 1
C7762
MIN_LINE_WIDTH=0.6MM
89 P3V3S5_REG_LGATE 16 LGATE1 LGATE2 20 89 P5VS3_REG_LGATE MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 1 10UF 330UF 330UF
DIDT=TRUE MIN_LINE_WIDTH=0.6MM 5 20% 20%
DIDT=TRUE 1 2 20% 6.3V 6.3V 2 2 6.3V
P3V3S5_REG_ISEN 10 ISEN2 26 P5VS3_REG_ISEN R7752 CERM 805-1 POLY-TANT POLY-TANT
OUTPUT BULK DECOUPLING: PLACEMENT_NOTE=PLACE NEXT TO C7716 89 ISEN1 89
D 0.499 2
R7771 1 CASE-D3L-SM CASE-D3L-SM
2 1
P3V3S5_REG_OCSET 11 OCSET1 OCSET2 25 89 P5VS3_REG_OCSET 5 14.3K
128S0237 89 1% 1/10W

B C7715 1 C7717 1
CRITICAL
1 XW7716
SM
P3V3S5_REG_VOUT1 9 VOUT1 VOUT2 27 P5VS3_REG_VOUT2
4 G MF 603
2 NOSTUFF
3
1%
1/16W
MF-LF
B
C7721 CRITICAL
402 2
P3V3S5_REG_FB_R

10UF 10UF OMIT P3V3S5_REG_FB

330UF 1
89
8 FB1 FB2 28 89 P5VS3_REG_FB 4
10% 10%
16V
2
20% R7724 Q7751 S
16V
X5R-CERM 2 X5R-CERM 6.3V 2
POLY-TANT R77201 976 6 FSET1 FSET2 2 P5VS3_REG_FSET2 CSD58851Q5A
0805
0805
CASE-D3L-SM 45.3K 1%
1/16W
1
R7722 MLP5X6-LFPAK-Q5A 1 2 3 2
1% MF-LF 68K 12 EN1 24
<Ra> 1/16W
MF-LF 402 2 5% EN2 376S0631
402 2 1/16W
MF-LF THRM SM XW7751
2 402 PAD PGND OMIT
1
C7720 P3V3S5_12VE_EN1

19
1
R7721 1 1000PF
1 C7723 1
C7716 <Rb> 10.0K 5%
25V 1
R7723
0.1UF 0.1UF 0.5% NP0-C0G 2
20% 20%
1/16W
MF
402 33K
2
16V
2
16V
402
5% P3V3S5_REG_FSET1
CERM CERM 2 1/16W
603 603 MF-LF
2 402 1 C7701 1
R7701
0.01UF 16.5K
EMC CAPS Vout = 0.6V * (1 + Ra / Rb) 10%
16V 1%

P5VS5_REG_FB_R
PLACE CLOSE
TO L
2 CERM
402
1/16W
MF-LF R77591 R77551
2 402 976 75K RA
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2

91 63
P5VS3_EN RB

1 NOSTUFF
C7759 1 1
R7756
1 C7747 R7747 1000PF 10K
0.01UF 16.5K 1 C7777 5%
25V 1%
10% 1% 0.001UF NP0-C0G 2 1/16W
2 16V
CERM
1/16W
MF-LF 10% 402 MF-LF
402 50V 2 402
2 402 2 CERM

A 402
SYNC_MASTER=NICK SYNC_DATE=12/08/2009 A
PAGE TITLE

5V_S3 / 3V3_S5 VREGS

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 70 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

1.5 V DDR SUPPLY PPDDR_S3_REG

NET_PHYSICAL_TYPE=POWER VOUT = 1.5V
PEAK = 11A
5
=PP12V_S5_DDR_VREG
EMC CAPS
AVG = 6.7A
NET_PHYSICAL_TYPE=POWER DIDT=TRUE PLACE CLOSE TO FET

=PP5V_S3_DDR_VREG R7801 CRITICAL CRITICAL 1 1

5 C7833 C7834 EMC CAPS
NET_PHYSICAL_TYPE=POWER 1
4.7
2 89 PP5V_S3_DDR_REG_V5FILT C7830 1 C7831 1 1
C7832 0.1UF 0.1UF PLACE CLOSE TO L7830
MIN_LINE_WIDTH=0.6 mm NET_PHYSICAL_TYPE=POWER 270UF 270UF 10UF
10%
20%
16V
20%
16V
5% MIN_NECK_WIDTH=0.2 mm 20% 20% 2 2 CERM
1/16W 16V 2 16V 2 16V CERM
VOLTAGE=5V 2
MF-LF ELEC ELEC X5R-CERM 603 603 1 C7838 1 C7839
402 8X9-TH1 8X9-TH1 0805
5 0.001UF 0.001UF
10% 10%
50V 50V
1
C7815 2 2 X7R
R7810 1
CRITICAL X7R
C7800 1 C7801 1
10UF D 402 402
6.04K
Q7830

23
20%
4.7UF 1UF 6.3V 1%
20% 10% 2 X5R 1/16W (DDRREG_DRVH) 4 G CSD58851Q5A
6.3V 10V
2 2 V5IN V5FILT VLDOIN 603 MF-LF MIN_LINE_WIDTH=0.6 mm
CERM
603
X5R
402 402 2 MIN_NECK_WIDTH=0.2 mm C7840 MLP5X6-LFPAK-Q5A
DIDT=TRUE
0.1UF
6 COMP VDDQSNS 8 DDR_REG_BOOT_R 1 2 S
C C
89
CRITICAL
CRITICAL
DDRVTT_EN MODE 4 89 DDR_REG_VDDQSNS DIDT=TRUE
20% L7830
91 63 IN 10 S3 VTT Enable
R7840 25V
CERM
SWITCHNODE
1 2 3 1.5UH-22A-4MOHM PP1V5_S3_REG 5
63 IN =DDRREG_EN 11 S5 VDDQ/VTTREF Enable 0 603
1 2
VBST 22 89 DDR_REG_BOOT 1 2
91 63 OUT PM_PGOOD_DDRREG_S3 13 PGOOD VDDQ PGOOD
U7800 DIDT=TRUE MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm 5%
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_PHYSICAL_TYPE=POWER MSQ12111R5LF-TH NET_PHYSICAL_TYPE=POWER
1/10W
TPS51116 DRVH 21 89 DDR_REG_UGATE MF-LF NOSTUFF 1 OUTPUT BULK DECOUPLING:
C7841
89
PPVTT_S3_DDR_BUF 10mA max load
5 VTTREF
QFN 603 5
1000PF NOSTUFF
CRITICAL
(NOT USED) Vout = VDDQSNS/2 SYM (2 OF 2) LL 20 89 DDR_REG_PHASE (DDRREG_LL)
5%
25V 1 CRITICAL
1 C7837
24 VTT MIN_LINE_WIDTH=0.6 mm DIDT=TRUE D CRITICAL NP0-C0G 2 C7835
330UF-0.009OHM C7836 1 10UF
OMIT Vout = VTTREF MIN_NECK_WIDTH=0.2 mm 402 1V5_SNUBBER 20%
330UF-0.009OHM
XW7803 DRVL 19 89 DDR_REG_LGATE (DDRREG_DRVL) 4 G D7831 20% 20%
6.3V
2 X5R
SM MIN_LINE_WIDTH=0.6 mm DIDT=TRUE CTLSH3-30M833 MIN_LINE_WIDTH=0.4MM 2 2V 2V 2 603

5
POLY
5
PPVTT_S0_DDR_LDO 1 2 89 DDR_REG_VTTSNS 2 VTTSNS
MIN_NECK_WIDTH=0.2 mm
TLM833
MIN_NECK_WIDTH=0.4MM
DIDT=TRUE
CASE-D2-HF
POLY
CASE-D2-HF
NO_TEST=TRUE CS 16 89 DDR_REG_CS CRITICAL
FEEDBACK THROUGH SHORT
SHOULD NOT NEED TP NC 7 NC0 Q7831
CSD58850Q5A
S
1NOSTUFF
12 NC1 VDDQSET 9 89 DDR_REG_FB MLP5X6-LFPAK-Q5A
R7831
NC 1 2 3 0.499
CRITICAL 1% 2
CRITICAL VTTGND THRM_PAD GND PGND CS_GND 1/10W OMIT
OMIT MF
C7804 1
XW7831 XW7830

1
1
C7803
1

17
22UF
PLACEMENT_NOTE=PLACE NEXT TO Q7831
SM
2 603 SM
20%
22UF
6.3V 20% 89 DDR_REG_CSGND (DDRREG_CSGND) 1 2 1
2 6.3V
CERM-X5R 2 CERM-X5R MIN_LINE_WIDTH=0.2 mm
805-3 PLACEMENT_NOTE=PLACE NEXT TO L7830
805-3 MIN_NECK_WIDTH=0.2 mm

89 DDR_REG_PGND (DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm NO STUFF 1
2
2MIN_NECK_WIDTH=0.2 mm
C7820 1 R7832 <Ra>
C7805 1
15.0K
0.033UF XW7800 XW7801 100PF 1%
SM 5%
10% OMIT SM 1/16W
16V OMIT 50V
CERM 2 MF-LF
X5R 2
402
1
1 402 2 402
(DDRREG_FB)

B STATE S3 S5 VDDQ VTTREF VTT Vout = 0.75V * (1 + Ra / Rb)

1
R7833
15.0K
<Rb> B
AGND_DDR_REG
S0 HI HI ON ON ON MIN_LINE_WIDTH=0.6 mm
1%
1/16W
S3 LO HI ON ON OFF MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
MF-LF
2 402
S5 LO LO OFF OFF OFF

5
=PP5V_S0_P1V8_VREG 1.8 V SUPPLY
C7854 C7855 R7852 R7853
1
1 1 C7851 CRITICAL
100K 1UF 1
100K 10%
1
10UF
1
10UF 5%
5%
1/16W
16V
2 X5R VIN L7850
1/16W MF-LF 2.2UH-3.25A-68M-OHM PP1V8_S0_REG
10%
6.3V
2 X5R
10%
6.3V
2 X5R
MF-LF
2 402
2 402
402
U7850 P1V8_REG_PHASE 1 2
5

805 805
ISL8009B 89

DFN NET_PHYSICAL_TYPE=POWER MMD04BZ-SM NET_PHYSICAL_TYPE=POWER

2 EN CRITICAL LX 8
DIDT=TRUE
SWITCHNODE
1 <Ra>
1
R7850
59.0K
3 POR 120PF
89 P1V8_REG_POR VFB 6 P1V8_REG_VFB C7850 5% 50V 2 1/16W 1%
MF-LF 402
P1V8_REG_SKIP 4 SKIP RSI 5 402 CERM 2

GND THRM_PAD
A 7 9
<Rb>
1
R7851
47.0K
1 C7852
22UF
1 C7853
22UF SYNC_MASTER=K23F SYNC_DATE=11/30/2009 A
20% 20% PAGE TITLE

2
1/16W 1%
MF-LF 402
6.3V
2 CERM
805
6.3V
2 CERM
805 1.5V / 1.8V VREGS
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

REVISION
R
A.0.0
Vo=0.8*(1+ Ra/Rb) NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING: PAGE
Vo=0.8*(1+ 59/47)=1.804V I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
78 OF 110

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 71 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

89 5
PP12V_G3H
89 P3V42G3H_BOOST

C7910 1 C7900 1

3
0.22UF
10UF VIN BOOST 20% CRITICAL
10% 6.3V 2
25V 2 U7900 X5R L7900
X5R
805 LT3470A
DFN
402
33UH PP3V42_G3H_REG 5
8 SHDN* SW 4 89 P3V42G3H_SW 1 2
BIAS 2 MIN_LINE_WIDTH=0.5 mm CDPH4D19FHF-SM Vout = 3.425
C NC
7 NC CRITICAL
FB 1
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE DIDT=TRUE
250mA max output C
THRM
(Switcher limit)
GND 1
PAD
C7901 1 <Ra> R7900
348K

9
22pF 1%
353S2171 5%
50V 1/16W 1 C7902
CERM 2 MF-LF
402 2 22UF
402 20%
2 6.3V
X5R-CERM
89 P3V42G3H_FB 603

<Rb> R79011
200K
1%
1/16W
MF-LF
402 2

Vout = 1.25V * (1 + Ra / Rb)

B B

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

3.42 G3HOT SUPPLY

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

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IV ALL RIGHTS RESERVED 72 OF 92
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8 7 6 5 4 3 2 1

5V S0 FET (7A PK/2.7A AVG) 3.3V S0 FET (3.4APK / 1.9A AVG) 3.3V S3 FET (2.9A PK / 1.2A AVG)
73 64 5 =PP12V_S5_PWRCTL
=PP12V_S5_PWRCTL
1 C8000 73 64 5

=PP12V_S5_PWRCTL
0.1UF 1 C8053 73 64 5
CRITICAL 10%
16V CRITICAL 0.1UF 1 C8050
Q8000 2 X5R
402 Q8053 10%
0.1UF
FDMC8298 2 16V
X5R CRITICAL 10%
FDMC8298 402 16V
MLP3.3X3.3
MLP3.3X3.3
Q8050 2 X5R
402
PP5V_S0_FET FDMC8298
D
5

1 2 3
MLP3.3X3.3
=PP5V_S3_S0FET PP3V3_S0_FET

1 2 3
5 5

=PP3V3_S5_S0FET PP3V3_S3_FET

S
D
5 5

S
D
5

1 2 3
=PP3V3_S5_S3FET

5
5

S
D
G
=PP3V3_S0_PWRCTL

5
G
73 64 63 5
73 64 63 5 =PP3V3_S0_PWRCTL
64 5 =PP3V3_S3_PWRCTL
NOSTUFF

G
4
1
R8000

1
VCC
10K R8050

P5V_S0_EN_G
1

4
1
R8051

P3V3_S0_EN_G
5%
U8000 10K VCC

1
1/16W
10K

P3V3_S3_EN_G
MF-LF 5%
2 402
SLG5AP001 1/16W U8053 5%
VCC
5D TDFN
ON 2
MF-LF
2 402 SLG5AP001 1/16W
MF-LF U8050
5D TDFN
ON 2 2 402 SLG5AP001
7G CRITICAL S6 TDFN
5D ON 2
7G CRITICAL S6
91 63 PGOOD_P5V_S0 8 PG NC 3 7G S6
91 64 PGOOD_P3V3_S0 8 PG NC 3 CRITICAL
THRM
PAD GND PGOOD_P3V3_S3 8 PG NC 3
THRM

4
PAD GND
THRM

4
PAD GND

4
91 63 IN P5VS0_EN
91 63 IN P3V3S0_EN
91 63 IN P3V3S3_EN

1.5V S0 FET (6.2A PK / 3A AVG)

C CRITICAL C
Q8025
FDMC8298
MLP3.3X3.3
1 2 3

5 =PPDDR_S3_S0FET PP1V5_S0_FET 5 50
S
D
5

1 C8025
0.1UF
4

10%
16V
2 X5R
73 64 5 =PP12V_S5_PWRCTL 402
P1V5_S0_EN_G

73 64 63 5 =PP3V3_S0_PWRCTL
1

R8020
1
VCC
10K
5%
1/16W
U8025
MF-LF SLG5AP001
2 402 5D TDFN
ON 2
7G CRITICAL S6

91 10 PGOOD_P1V5_S0 8 PG NC 3

THRM
PAD GND
9

B B
91 63 IN P1V5_S0_EN

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

S3+S0 FETS
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

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IV ALL RIGHTS RESERVED 73 OF 92
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Page Notes
Power aliases required by this page:
- =PP3V3_S0_MXM
- =PP5V_S0_MXM
- =PPV_S0_MXM_PWRSRC

Signal aliases required by this page:

(NONE)

D BOM options provided by this page: D

- MXM

75 74 64 5 =PP3V3_S0_MXM MXM
=PP3V3_S0_MXM 5 64 74 75
MXM CRITICAL
R84001 J8400 MXM
100K B35P101-0121
5%
1/16W
MF-LF
F-RT-SM
(2 OF 4) =PP5V_S0_MXM
J8400 MXM MXM
402 2
APPLE P/N: 516S0699
5
B35P101-0121 1 C8415 1 C8416
F-RT-SM
8 MXM_CLKREQ_L 154 CLK_REQ* DP_A_AUX* 277 MXM_DP_A_AUX_N 80 87 (4 OF 4) 0.001UF 22UF
10% 20%
DP_A_AUX 279 MXM_DP_A_AUX_P 80 87 2 50V
X7R 2 6.3V
CERM-X5R
75 MXM_PCIE_STD_SWING_L 19 PEX_STD_SW* 1 278 402 805-3
DP_A_HPD 276 MXM_DP_A_HPD 80 MXM MXM 3 3V3 280
CLK_100M_MXM_P 155 PEX_REFCLK
8

CLK_100M_MXM_N 153 PEX_REFCLK* DP_A_L0* 253 MXM_DP_A_ML_N<0>

1 C8410 1 C8401 5 5V
8 80 87
0.001UF 22UF 7 =PPV_S0_MXM_PWRSRC 50
DP_A_L0 255 MXM_DP_A_ML_P<0> 80 87
10% 20%
8 MXM_RESET_L 156 PEX_RST* 2 50V
X7R 2 6.3V
CERM-X5R 9 E2
DP_A_L1* 259 MXM_DP_A_ML_N<1> 80 87 402 805-3 PWR_SRC E1
84 76 MXM_PCIE_D2R_N<0> 147 PEX_RX0* DP_A_L1 261 MXM_DP_A_ML_P<1> 80 87

84 76 MXM_PCIE_D2R_P<0> 149 PEX_RX0 DP_A_L2* 265 MXM_DP_A_ML_N<2> 80 87

MXM MXM MXM MXM
MXM_PCIE_D2R_N<1> 141 PEX_RX1* DP_A_L2 267 MXM_DP_A_ML_P<2>
84 76

MXM_PCIE_D2R_P<1> 143 PEX_RX1 DP_A_L3* 271 MXM_DP_A_ML_N<3>

80 87
1
C8400 1 C8412 1 C8413 1 C8414
84 76 80 87
22UF 0.001UF 0.001UF 0.001UF
84 76 MXM_PCIE_D2R_N<2> 135 PEX_RX2* DP_A_L3 273 MXM_DP_A_ML_P<3> 80 87 20% 10% 10% 10%
50V 50V 50V
2 35V 2 X7R 2 X7R 2 X7R
84 76 MXM_PCIE_D2R_P<2> 137 PEX_RX2
MXM_DP_B_AUX_N
MXM SPEC POWER REQUIREMENTS ELEC
6.3X5.5-SM1 402 402 402
DP_B_AUX* 270 77 87
84 76 MXM_PCIE_D2R_N<3> 121 PEX_RX3* (NOT NECESSARILY THE SAME FOR EVERY MODULE)
C DP_B_AUX 272 MXM_DP_B_AUX_P
C
PCI-E
77 87
84 76 MXM_PCIE_D2R_P<3> 123 PEX_RX3 VOLTAGE CURRENT POWER

DP
84 76 MXM_PCIE_D2R_N<4> 115 PEX_RX4* DP_B_HPD 274 MXM_DP_B_HPD 77
3V3 1.0 A 3.3 W
84 76 MXM_PCIE_D2R_P<4> 117 PEX_RX4
DP_B_L0* 246 MXM_DP_B_ML_N<0> 77 87 5V 2.5 A 12.5 W
84 76 MXM_PCIE_D2R_N<5> 109 PEX_RX5*
DP_B_L0 248 MXM_DP_B_ML_P<0> 77 87 PWR (7-20V) UP TO 10 A PLATFORM DEPENDENT
84 76 MXM_PCIE_D2R_P<5> 111 PEX_RX5
DP_B_L1* 252 MXM_DP_B_ML_N<1> 77 87
84 76 MXM_PCIE_D2R_N<6> 103 PEX_RX6*
DP_B_L1 254 MXM_DP_B_ML_P<1> 77 87
84 76 MXM_PCIE_D2R_P<6> 105 PEX_RX6
DP_B_L2* 258 MXM_DP_B_ML_N<2> 77 87
84 76 MXM_PCIE_D2R_N<7> 97 PEX_RX7*
DP_B_L2 260 MXM_DP_B_ML_P<2> 77 87
84 76 MXM_PCIE_D2R_P<7> 99 PEX_RX7
DP_B_L3* 264 MXM_DP_B_ML_N<3> 77 87
84 76 MXM_PCIE_D2R_N<8> 91 PEX_RX8*
DP_B_L3 266 MXM_DP_B_ML_P<3> 77 87
84 76 MXM_PCIE_D2R_P<8> 93 PEX_RX8
84 76 MXM_PCIE_D2R_N<9> 85 PEX_RX9* DP_C_AUX* 223 MXM_DP_C_AUX_N 80 87

84 76 MXM_PCIE_D2R_P<9> 87 PEX_RX9 DP_C_AUX 225 MXM_DP_C_AUX_P 80 87

84 76 MXM_PCIE_D2R_N<10> 79 PEX_RX10*
DP_C_HPD 234 MXM_DP_C_HPD 80
84 76 MXM_PCIE_D2R_P<10> 81 PEX_RX10
84 76 MXM_PCIE_D2R_N<11> 73 PEX_RX11* DP_C_L0* 199 MXM_DP_C_ML_N<0> 80 87

84 76 MXM_PCIE_D2R_P<11> 75 PEX_RX11 DP_C_L0 201 MXM_DP_C_ML_P<0> 80 87

84 76 MXM_PCIE_D2R_N<12> 67 PEX_RX12* DP_C_L1* 205 MXM_DP_C_ML_N<1> 80 87

84 76 MXM_PCIE_D2R_P<12> 69 PEX_RX12 DP_C_L1 207 MXM_DP_C_ML_P<1> 80 87

84 76 MXM_PCIE_D2R_N<13> 61 PEX_RX13* DP_C_L2* 211 MXM_DP_C_ML_N<2> 80 87

84 76 MXM_PCIE_D2R_P<13> 63 PEX_RX13 DP_C_L2 213 MXM_DP_C_ML_P<2> 80 87

84 76 MXM_PCIE_D2R_N<14> 55 PEX_RX14* DP_C_L3* 217 MXM_DP_C_ML_N<3> 80 87

84 76 MXM_PCIE_D2R_P<14> 57 PEX_RX14 DP_C_L3 219 MXM_DP_C_ML_P<3> 80 87

84 76 MXM_PCIE_D2R_N<15> 49 PEX_RX15*
DP_D_AUX* 230 MXM_DP_D_AUX_N 77 87
84 76 MXM_PCIE_D2R_P<15> 51 PEX_RX15
DP_D_AUX 232 MXM_DP_D_AUX_P 77 87

MXM_PCIE_R2D_N<0> 148 PEX_TX0*

B
84 76

84 76 MXM_PCIE_R2D_P<0> 150 PEX_TX0

DP_D_HPD 236 MXM_DP_D_HPD 77
B
84 76 MXM_PCIE_R2D_N<1> 142 PEX_TX1* DP_D_L0* 206 MXM_DP_D_ML_N<0> 77 87

84 76 MXM_PCIE_R2D_P<1> 144 PEX_TX1 DP_D_L0 208 MXM_DP_D_ML_P<0> 77 87

84 76 MXM_PCIE_R2D_N<2> 136 PEX_TX2* DP_D_L1* 212 MXM_DP_D_ML_N<1> 77 87

84 76 MXM_PCIE_R2D_P<2> 138 PEX_TX2 DP_D_L1 214 MXM_DP_D_ML_P<1> 77 87

84 76 MXM_PCIE_R2D_N<3> 120 PEX_TX3* DP_D_L2* 218 MXM_DP_D_ML_N<2> 77 87

84 76 MXM_PCIE_R2D_P<3> 122 PEX_TX3 DP_D_L2 220 MXM_DP_D_ML_P<2> 77 87

84 76 MXM_PCIE_R2D_N<4> 114 PEX_TX4* DP_D_L3* 224 MXM_DP_D_ML_N<3> 77 87

84 76 MXM_PCIE_R2D_P<4> 116 PEX_TX4 DP_D_L3 226 MXM_DP_D_ML_P<3> 77 87

84 76 MXM_PCIE_R2D_N<5> 108 PEX_TX5*

84 76 MXM_PCIE_R2D_P<5> 110 PEX_TX5
84 76 MXM_PCIE_R2D_N<6> 102 PEX_TX6*
84 76 MXM_PCIE_R2D_P<6> 104 PEX_TX6
84 76 MXM_PCIE_R2D_N<7> 96 PEX_TX7*
84 76 MXM_PCIE_R2D_P<7> 98 PEX_TX7
84 76 MXM_PCIE_R2D_N<8> 90 PEX_TX8*
84 76 MXM_PCIE_R2D_P<8> 92 PEX_TX8
84 76 MXM_PCIE_R2D_N<9> 84 PEX_TX9*
84 76 MXM_PCIE_R2D_P<9> 86 PEX_TX9
84 76 MXM_PCIE_R2D_N<10> 78 PEX_TX10*
84 76 MXM_PCIE_R2D_P<10> 80 PEX_TX10
84 76 MXM_PCIE_R2D_N<11> 72 PEX_TX11*
84 76 MXM_PCIE_R2D_P<11> 74 PEX_TX11
84 76 MXM_PCIE_R2D_N<12> 66 PEX_TX12*
84 76 MXM_PCIE_R2D_P<12> 68 PEX_TX12

A 84 76

84 76
MXM_PCIE_R2D_N<13>
MXM_PCIE_R2D_P<13>
60
62
PEX_TX13*
PEX_TX13 SYNC_MASTER=K23F SYNC_DATE=11/30/2009 A
84 76 MXM_PCIE_R2D_N<14> 54 PEX_TX14* PAGE TITLE

84 76 MXM_PCIE_R2D_P<14> 56 PEX_TX14 MXM PCIe, DP & Power

84 76 MXM_PCIE_R2D_N<15> 48 PEX_TX15* DRAWING NUMBER SIZE
84 76 MXM_PCIE_R2D_P<15> 50 PEX_TX15
Apple Inc. 051-8337 D
REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
84 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 74 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Page Notes
Power aliases required by this page:
- =PP3V3_S0_MXM

Signal aliases required by this page:

- =SMB_MXM_THRM_DATA - =PM_MXM_PGOOD_PULLUP PULLUPS & PULLDOWNS AT MXM CONNECTOR
- =SMB_MXM_THRM_CLK

D BOM options provided by this page: D

MXM
MXM

J8400 J8400
B35P101-0121 B35P101-0121
F-RT-SM F-RT-SM
(1 OF 4) (3 OF 4) FLOAT = NORMAL VGA MODE
75 MXM_LVDS_DDC_CLK 35 LVDS_DDC_CLK GND = SECONDARY DISPLAY CARD NOSTUFF
75 MXM_LVDS_DDC_DAT 33 LVDS_DDC_DAT VGA_DISABLE* 21 MXM_VGA_DISABLE_L 75 11 145 R8510
MXM_VGA_DISABLE_L 2
0 1
13 146 75
TP_MXM_DVI_HPD 31 DVI_HPD GPIO0 26 TP_MXM_GPIO0
15 151 MF-LF 5% 1/16W
GPIO1 28 TP_MXM_GPIO1
87 77 MXM_LVDS_A_CLK_N 176 LVDS_LCLK* 17 152 402
GPIO2 30 TP_MXM_GPIO2 MXM
87 77 MXM_LVDS_A_CLK_P 178 LVDS_LCLK 36 157 FLOAT = LOW SWING
GND = HIGH SWING R8504
MXM_LVDS_A_DATA_N<0>
HDMI_CEC 29 TP_MXM_HDMI_CEC 37 166
MXM_PCIE_STD_SWING_L 2
0 1
87 77 200 LVDS_LTX0* 74
46 173
87 77 MXM_LVDS_A_DATA_P<0> 202 LVDS_LTX0 OEM0 38 MF-LF 5% 1/16W
47 174
OEM1 39 402
87 77 MXM_LVDS_A_DATA_N<1> 194 LVDS_LTX1* 52 179
OEM2 40
87 77 MXM_LVDS_A_DATA_P<1> 196 LVDS_LTX1 53 180
OEM3 41
58 185
87 77 MXM_LVDS_A_DATA_N<2> 188 LVDS_LTX2* OEM4 42
59 186
87 77 MXM_LVDS_A_DATA_P<2> 190 LVDS_LTX2 OEM5 43
LVDS

64 191
OEM6 44
87 77 MXM_LVDS_A_DATA_N<3> 182 LVDS_LTX3* 65 192
OEM7 45
87 77 MXM_LVDS_A_DATA_P<3> 184 LVDS_LTX3 70 197

C 87 77

87 77
MXM_LVDS_B_CLK_N
MXM_LVDS_B_CLK_P
169
171
LVDS_UCLK*
LVDS_UCLK
PNL_BL_EN

PNL_BL_PWM
25

27
MXM_PNL_BL_EN

MXM_PNL_BL_PWM
77

80
71
76
198
203 C
77 GND GND 204
87 77 MXM_LVDS_B_DATA_N<0> 193 LVDS_UTX0* PNL_PWR_EN 23 MXM_PNL_PWR_EN 77 82 209
87 77 MXM_LVDS_B_DATA_P<0> 195 LVDS_UTX0 83 210
RSVD0 10
88 215
87 77 MXM_LVDS_B_DATA_N<1> 187 LVDS_UTX1* RSVD1 159
89 216
87 77 MXM_LVDS_B_DATA_P<1> 189 LVDS_UTX1 RSVD2 12
SYSTEM MANAGEMENT

94 221 =PP3V3_S0_MXM 5 64 74 75
RSVD3 161
87 77 MXM_LVDS_B_DATA_N<2> 181 LVDS_UTX2* 95 222
RSVD4 163
87 77 MXM_LVDS_B_DATA_P<2> 183 LVDS_UTX2 100 228
RSVD5 165
101 244
87 77 MXM_LVDS_B_DATA_N<3> 175 LVDS_UTX3* RSVD6 167
106 E3
87 77 MXM_LVDS_B_DATA_P<3> 177 LVDS_UTX3 RSVD7 227
107 250
RSVD8 229
112 251
64 PM_MXM_EN 8 PWR_EN RSVD9 231
POWER/THERMAL

91 75 64 PM_MXM_PGOOD 6 PWRGOOD RSVD10 233

113 256 R8500
118 257 100K 2
MANAGEMENT

47 MXM_PWR_LEVEL 18 PWR_LEVEL RSVD11 235 75 MXM_DETECT_L 1

119 262
RSVD12 237 MF-LF 5% 1/16W
49 =SMB_MXM_THRM_SCL 34 SMB_CLK 124 263 402
RSVD13 238 PULLED TO GROUND ON MXM
49 =SMB_MXM_THRM_SDA 32 SMB_DAT 125 268 WE DON’T USE CARD DETECT
RSVD14 239
47 MXM_ALERT_L 22 TH_ALERT* RSVD15 240
133 269 R8501
MXM_OVERT_L
134 275
MXM_DETECT_R 1
100K 2
47 20 TH_OVERT* RSVD16 241 75
139 282
TP_MXM_TH_PWM 24 TH_PWM RSVD17 242 MF-LF 5% 1/16W
140 283 402
RSVD18 243
E4
ANALOG DISPLAY

TP_MXM_VGA_DDC_CLK 160 VGA_DDC_CLK RSVD19 245

TP_MXM_VGA_DDC_DAT 158 VGA_DDC_DAT RSVD20 247
RSVD21 249
TP_MXM_VGA_BLUE 172 VGA_BLUE
B TP_MXM_VGA_GREEN 170 VGA_GREEN
RSVD22
RSVD23
14
16
=PM_MXM_PGOOD_PULLUP 64 B
TP_MXM_VGA_HSYNC 164 VGA_HSYNC
PRSNT_L* 281 MXM_DETECT_L 75 SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,
TP_MXM_VGA_RED 168 VGA_RED
PRSNT_R* 2 MXM_DETECT_R 75 OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR
TP_MXM_VGA_VSYNC 162 VGA_VSYNC
WAKE* 4 TP_MXM_WAKE_L
R8503
10K
91 75 64 PM_MXM_PGOOD 2 1
MF-LF 5% 1/16W
402

MXM SYSTEM INFORMATION ROM

PLACE CLOSE TO J8400

=PP3V3_S0_MXM 5 64 74 75

STUFF FOR WRITE PROTECT MXM

NOSTUFF 1 C8570
R85701 0.1UF
R85761
0 20%
10V
R85751 4.7K
8

5% 2 CERM
1/16W 402 5%
4.7K MF-LF VCC 1/16W
5% 402 2 MF-LF
1/16W
MF-LF U8570 402 2
402 2 M24C02
MXM_ROM_WP 7 WC* MLP8 SDA 5 MXM_LVDS_DDC_DAT 75
MXM

A 75 MXM_LVDS_DDC_CLK 6 SCL CRITICAL

SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE
1 E0
2 E1I2C ADDRESS: A8 MXM I/O
3 E2 DRAWING NUMBER SIZE
VSS THRM_PAD Apple Inc. 051-8337 D
REVISION
4

R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
85 OF 110

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 75 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MXM TX CAPS MXM RX CAPS

PEG_R2D_C_P<0> MXM C8600 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<15> MXM C8632 0.1UF 1
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_P<15> 2 10% 16V X5R 402 PEG_D2R_N<0> OUT 8 84
PEG_R2D_C_N<0> MXM C8601 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<15> MXM C8633 0.1UF 1
D
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_N<15> 2 10% 16V X5R 402 PEG_D2R_P<0> OUT 8 84
D
84 8 IN
PEG_R2D_C_N<1> MXM C8602 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<14> OUT 74 84 84 74 IN
MXM_PCIE_D2R_P<14> MXM C8634 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<1> OUT 8 84

PEG_R2D_C_P<1> MXM C8603 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<14> MXM_PCIE_D2R_N<14> MXM C8635 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<1>
84 8 IN OUT 74 84 84 74 IN OUT 8 84

84 8 IN
PEG_R2D_C_N<2> MXM C8604 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<13> OUT 74 84 84 74 IN
MXM_PCIE_D2R_P<13> MXM C8636 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<2> OUT 8 84

84 8 IN
PEG_R2D_C_P<2> MXM C8605 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<13> OUT 74 84 84 74 IN
MXM_PCIE_D2R_N<13> MXM C8637 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<2> OUT 8 84

84 8 IN
PEG_R2D_C_P<3> MXM C8606 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<12> OUT 74 84 84 74 IN
MXM_PCIE_D2R_P<12> MXM C8638 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<3> OUT 8 84

84 8 IN
PEG_R2D_C_N<3> MXM C8607 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<12> OUT 74 84 84 74 IN
MXM_PCIE_D2R_N<12> MXM C8639 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<3> OUT 8 84

PEG_R2D_C_N<4> MXM C8608 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<11> MXM C8640 0.1UF 1
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_P<11> 2 10% 16V X5R 402 PEG_D2R_N<4> OUT 8 84
PEG_R2D_C_P<4> MXM C8609 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<11> MXM C8641 0.1UF 1
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_N<11> 2 10% 16V X5R 402 PEG_D2R_P<4> OUT 8 84

PEG_R2D_C_N<5> MXM C8610 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<10> MXM C8642 0.1UF 1
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_P<10> 2 10% 16V X5R 402 PEG_D2R_N<5> OUT 8 84
PEG_R2D_C_P<5> MXM C8611 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<10>
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_N<10> MXM C8643 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<5> OUT 8 84

84 8 PEG_R2D_C_P<6> MXM C8612 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<9> 74 84

C
IN OUT
C 84 8 IN
PEG_R2D_C_N<6> MXM C8613 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<9> OUT 74 84
84 74 IN
MXM_PCIE_D2R_P<9> MXM C8644 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<6> OUT 8 84

84 74 IN
MXM_PCIE_D2R_N<9> MXM C8645 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<6> OUT 8 84

84 8 IN
PEG_R2D_C_N<7> MXM C8614 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<8> OUT 74 84
MXM_PCIE_D2R_P<8> MXM C8646 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<7>
84 8 IN
PEG_R2D_C_P<7> MXM C8615 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<8> OUT 74 84
84 74 IN OUT 8 84

84 74 IN
MXM_PCIE_D2R_N<8> MXM C8647 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<7> OUT 8 84

84 8 IN
PEG_R2D_C_P<8> MXM C8616 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<7> OUT 74 84

PEG_R2D_C_N<8> MXM C8617 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<7> MXM_PCIE_D2R_P<7> MXM C8648 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<8>
84 8 IN OUT 74 84 84 74 IN OUT 8 84

84 74 IN
MXM_PCIE_D2R_N<7> MXM C8649 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<8> OUT 8 84

84 8 IN
PEG_R2D_C_P<9> MXM C8618 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<6> OUT 74 84

PEG_R2D_C_N<9> MXM C8619 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<6> MXM_PCIE_D2R_P<6> MXM C8650 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<9>
84 8 IN OUT 74 84 84 74 IN OUT 8 84

84 74 IN
MXM_PCIE_D2R_N<6> MXM C8651 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<9> OUT 8 84

84 8 IN
PEG_R2D_C_N<10> MXM C8620 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<5> OUT 74 84

PEG_R2D_C_P<10> MXM C8621 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<5>

84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_P<5> MXM C8652 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<10> OUT 8 84

84 74 IN
MXM_PCIE_D2R_N<5> MXM C8653 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<10> OUT 8 84

84 8 IN
PEG_R2D_C_N<11> MXM C8622 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<4> OUT 74 84

PEG_R2D_C_P<11> MXM C8623 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<4> MXM_PCIE_D2R_P<4> MXM C8654 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<11>
84 8 IN OUT 74 84 84 74 IN OUT 8 84

84 74 IN
MXM_PCIE_D2R_N<4> MXM C8655 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<11> OUT 8 84

B 84 8 IN
PEG_R2D_C_P<12> MXM C8624 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<3> OUT 74 84
B
PEG_R2D_C_N<12> MXM C8625 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<3> MXM_PCIE_D2R_P<3> MXM C8656 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<12>
84 8 IN OUT 74 84 84 74 IN OUT 8 84

MXM_PCIE_D2R_N<3> MXM C8657 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<12>

84 74 IN OUT 8 84

PEG_R2D_C_N<13> MXM C8626 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<2> MXM C8658 0.1UF 1
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_P<2> 2 10% 16V X5R 402 PEG_D2R_P<13> OUT 8 84
PEG_R2D_C_P<13> MXM C8627 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<2> MXM C8659 0.1UF 1
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_N<2> 2 10% 16V X5R 402 PEG_D2R_N<13> OUT 8 84

PEG_R2D_C_P<14> MXM C8628 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<1>

84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_P<1> MXM C8662 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<14> OUT 8 84
PEG_R2D_C_N<14> MXM C8629 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<1>
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_N<1> MXM C8663 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<14> OUT 8 84

PEG_R2D_C_N<15> MXM C8630 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<0> MXM C8660 0.1UF 1
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_P<0> 2 10% 16V X5R 402 PEG_D2R_N<15> OUT 8 84
PEG_R2D_C_P<15> MXM C8631 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<0> MXM C8661 0.1UF 1
84 8 IN OUT 74 84
84 74 IN
MXM_PCIE_D2R_N<0> 2 10% 16V X5R 402 PEG_D2R_P<15> OUT 8 84

A SYNC_MASTER=K23F SYNC_DATE=11/30/2009 A
PAGE TITLE

MXM PCIE CAPS

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

D (NONE)
Unused MXM Interfaces D
Unused MXM DP Interfaces
87 75 MXM_LVDS_A_CLK_N NC_MXM_LVDS_A_CLK_N
MAKE_BASE=TRUE NO_TEST=TRUE 87 74 MXM_DP_B_ML_P<0..3> NC_MXM_DP_B_ML_P<0..3>
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_A_CLK_P NC_MXM_LVDS_A_CLK_P
MAKE_BASE=TRUE NO_TEST=TRUE 87 74 MXM_DP_B_ML_N<0..3> NC_MXM_DP_B_ML_N<0..3>
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_A_DATA_N<0> NC_MXM_LVDS_A_DATA_N<0>
MAKE_BASE=TRUE NO_TEST=TRUE 87 74 MXM_DP_B_AUX_P NC_MXM_DP_B_AUX_P
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_A_DATA_P<0> NC_MXM_LVDS_A_DATA_P<0>
MAKE_BASE=TRUE NO_TEST=TRUE 87 74 MXM_DP_B_AUX_N NC_MXM_DP_B_AUX_N
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_A_DATA_N<1> NC_MXM_LVDS_A_DATA_N<1>
MAKE_BASE=TRUE NO_TEST=TRUE 74 MXM_DP_B_HPD NC_MXM_DP_B_HPD
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_A_DATA_P<1> NC_MXM_LVDS_A_DATA_P<1>
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_A_DATA_N<2> NC_MXM_LVDS_A_DATA_N<2>
MAKE_BASE=TRUE NO_TEST=TRUE 87 74 MXM_DP_D_ML_P<0..3> NC_MXM_DP_D_ML_P<0..3>
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_A_DATA_P<2> NC_MXM_LVDS_A_DATA_P<2>
MAKE_BASE=TRUE NO_TEST=TRUE 87 74 MXM_DP_D_ML_N<0..3> NC_MXM_DP_D_ML_N<0..3>
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_A_DATA_N<3> NC_MXM_LVDS_A_DATA_N<3>
MAKE_BASE=TRUE NO_TEST=TRUE 87 74 MXM_DP_D_AUX_P NC_MXM_DP_D_AUX_P
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_A_DATA_P<3> NC_MXM_LVDS_A_DATA_P<3>
MAKE_BASE=TRUE NO_TEST=TRUE 87 74 MXM_DP_D_AUX_N NC_MXM_DP_D_AUX_N
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_B_CLK_N NC_MXM_LVDS_B_CLK_N
MAKE_BASE=TRUE NO_TEST=TRUE 74 MXM_DP_D_HPD NC_MXM_DP_D_HPD
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_B_CLK_P NC_MXM_LVDS_B_CLK_P
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_B_DATA_N<0> NC_MXM_LVDS_B_DATA_N<0>
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_B_DATA_P<0> NC_MXM_LVDS_B_DATA_P<0>
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_B_DATA_N<1> NC_MXM_LVDS_B_DATA_N<1>
MAKE_BASE=TRUE NO_TEST=TRUE
UNUSED MXM CONTROL SIGNALS
87 75 MXM_LVDS_B_DATA_P<1> NC_MXM_LVDS_B_DATA_P<1>
MAKE_BASE=TRUE NO_TEST=TRUE 75 MXM_PNL_BL_EN NC_MXM_PNL_BL_EN
C 87 75 MXM_LVDS_B_DATA_N<2> NC_MXM_LVDS_B_DATA_N<2>
MAKE_BASE=TRUE NO_TEST=TRUE 75 MXM_PNL_PWR_EN
MAKE_BASE=TRUE
NC_MXM_PNL_PWR_EN
MAKE_BASE=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
C
87 75 MXM_LVDS_B_DATA_P<2> NC_MXM_LVDS_B_DATA_P<2>
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_B_DATA_N<3> NC_MXM_LVDS_B_DATA_N<3>
MAKE_BASE=TRUE NO_TEST=TRUE
87 75 MXM_LVDS_B_DATA_P<3> NC_MXM_LVDS_B_DATA_P<3>
MAKE_BASE=TRUE NO_TEST=TRUE

DISPLAY AUDIO MUX NOT USED - SEND SPDIF TO CODEC

85 60 IN AUD_SPDIF_IN AUD_SPDIF_IN_CODEC OUT 56
MAKE_BASE=TRUE
78 IN DP_INT_SPDIF_AUDIO TP_DP_INT_SPDIF_AUDIO
MAKE_BASE=TRUE

B B

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

Display: Aliases
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

- =PP12V_S0_LCD
- =PP3V3_S0_DP

Signal aliases required by this page:

INTERNAL DP INTERFACE
- =SMB_DP_TCON_SCL, =SMB_DP_TCON_SDA
NOSTUFF
R9050
0 CRITICAL
BOM options provided by this page: 49 OUT =SMB_DP_TCON_SCL 1 2

D NOSTUFF
5%
1/16W
MF-LF
J9000
20455-030E D
R9051 402 F-RT-SM
31
=SMB_DP_TCON_SDA 1
0 2 32
49 BI
5% I2C MASTER ON TCON
1/16W
MF-LF I2C_TCON_SCL 1
402
I2C_TCON_SDA 2
3

87 80 DP_INT_AUX_N 4
BI
87 80 DP_INT_AUX_P 5
BI
6

87 80 DP_INT_ML_C_P<0> 7
IN
87 80 DP_INT_ML_C_N<0> 8
IN
9

87 80 DP_INT_ML_C_P<1> 10
IN
87 80 DP_INT_ML_C_N<1> 11
IN
12

87 80 DP_INT_ML_C_P<2> 13
IN
87 80 DP_INT_ML_C_N<2> 14
IN
15

87 80 DP_INT_ML_C_P<3> 16
IN
87 80 DP_INT_ML_C_N<3> 17
IN
18

77 DP_INT_SPDIF_AUDIO 19
OUT
78 DP_INT_VIDEO_ON 20
OUT
80 DP_INT_HPD 21
OUT
22

C 23
24
C
25
26
27
28
29
30

VSYNC WILL ROUTE TO BLC VIA

L9000 A SEPARATE PANEL CONNECTOR 33
220-OHM-1.4A
FUTURE BOARDS MAY ROUTE THIS VIA MLB 34
5 =PP12V_S0_LCD 1 2 PP12V_LCD
0603 VOLTAGE=12V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
C9020 1
C9001 1

10UF 0.001UF
10% 20%
16V 50V
X5R-CERM 2 CERM 2
0805 402

NOSTUFF
R9010
0
80 79 78 5 =PP3V3_S0_DP 1 2 PP3V3_DP
VOLTAGE=3.3V
5% MIN_LINE_WIDTH=0.4MM
1/16W MIN_NECK_WIDTH=0.2MM
MF-LF
402

B BACKLIGHT CONTROL SUPPORT B

guarantee backlight is
only on when Panel has valid video

80 79 78 5 =PP3V3_S0_DP
80 79 78 5 =PP3V3_S0_DP

C9000 1 1
C9005
0.1UF 22UF
20% 20%
10V 6.3V
CERM 2 2 CERM
402 805
5 U9000 5 U9000
74AUP2G14GM
SOT886
D9000
SOT23
74AUP2G14GM
SOT886 R9011
1 6 1 3 VIDEO_ON_L_DLY 3 4 1K
78 DP_INT_VIDEO_ON LCD_BKL_ON_DLY 1 2 LCD_BKL_ON OUT 5

5%
BAT54XG 1/16W
MF-LF
2 2 402
R9009
19.1K2
1
1%
1/16W
MF-LF
402
5 OUT VIDEO_ON_L
used by diag LED

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

Display: Int DP Connector

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

D D

EQ & Re-Driver for DP source

80 79 78 5 =PP3V3_S0_DP

1
C9180 1
C9181 1
C9182 1
C9183 1
C9184 1
C9185
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

11
15
21
33
40
46
20% 20% 20% 20% 20% 20%
10V 10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402
VCC
STRAPS SET FOR PIN CONTROL MODE, 1.5 DB EQ
U9180
PS8121ED
80 79 78 5 =PP3V3_S0_DP QFN
87 80 IN GPU_DP_EXT_ML_P<0> 38 IN1P OUT1P 23 RDRV_DP_EXT_ML_P<0> OUT 80 87

87 80 IN GPU_DP_EXT_ML_N<0> 39 IN1N OUT1N 22 RDRV_DP_EXT_ML_N<0> OUT 80 87

87 80 IN GPU_DP_EXT_ML_P<1> 41 IN2P OUT2P 20 RDRV_DP_EXT_ML_P<1> OUT 80 87

87 80 IN GPU_DP_EXT_ML_N<1> 42 IN2N OUT2N 19 RDRV_DP_EXT_ML_N<1> OUT 80 87

NOSTUFF 87 80 IN GPU_DP_EXT_ML_P<2> 44 IN3P OUT3P 17 RDRV_DP_EXT_ML_P<2> OUT 80 87

R91521 R91511 R91501 87 80 IN GPU_DP_EXT_ML_N<2> 45 IN3N OUT3N 16 RDRV_DP_EXT_ML_N<2> OUT 80 87
1K 1K 1K
5% 5% 5% 87 80 IN GPU_DP_EXT_ML_P<3> 47 IN4P OUT4P 14 RDRV_DP_EXT_ML_P<3> OUT 80 87
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 87 80 IN GPU_DP_EXT_ML_N<3> 48 IN4N OUT4N 13 RDRV_DP_EXT_ML_N<3> OUT 80 87
402 2 402 2 402 2

C PS8121_PC0 3 PC0/I2C_ADDR0 INT_PD AUX+ 8 RDRV_DP_EXT_AUX_P 79 87

C
PS8121_PC1 4 PC1/I2C_ADDR1 INT_PD AUX- 9 RDRV_DP_EXT_AUX_N 79 87 DISCONNECT I2C IN PIN CONTROL MODE
PS8121_I2C_EN_L 26 I2C_CTL_EN* INT_PD
NOSTUFF
R9120
25 OE* INT_PD SDA_CTL 34 RDRV_SDA 1 2 0 =I2C_DP_DRV_SDA BI 49

SCL_CTL 35 RDRV_SCL NOSTUFF

PS8121_REXT 6 REXT C9186 R9121 =I2C_DP_DRV_SCL IN 49

1 2 0
4.7UF
81 80 DP_EXT_CA_DET 27 CA_DET CEXT 10 PS8121_CEXT 6.3V
1 2 20%
IN
R9183 1 402 X5R-CERM

499 80 OUT GPU_DP_EXT_HPD 7 HPD HPD_SINK 30 RDRV_DP_EXT_HPD IN 80

1%
1/16W
MF-LF 80 79 78 5 =PP3V3_S0_DP
402 2 36 MODE 1
NC
NC 2 CFGX NC 28
NC
32 CFGY 29
NC
GND THRM_PAD

5
12
18
24
31
37
43

49
COMMON MODE BIAS FOR PS8121ED AUX INTERCEPTION
B 80 79 78 5 =PP3V3_S0_DP
B
R91901 R9191
1

100K 100K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402

87 81 80 DP_EXT_AUX_P
NO_TEST
C9190
10% 16V
1 2 0.1uF
X5R 402
RDRV_DP_EXT_AUX_P
NO_TEST
79 87

87 81 80 DP_EXT_AUX_N
NO_TEST
C9191
10% 16V
1 2 0.1uF
X5R 402
RDRV_DP_EXT_AUX_N
NO_TEST
79 87

A SYNC_MASTER=DAVE SYNC_DATE=01/07/2010 A
PAGE TITLE

DISPLAY: DP REDRIVER
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

80 79 78 5 =PP3V3_S0_DP

87 74 IN MXM_DP_A_ML_P<0> NO_TEST C9212

10% 16V
1 2 0.1uF
X5R 402
NO_TEST GPU_DP_EXT_ML_P<0> OUT 79 87

AUX/DDC SELECTION FOR EXTERNAL PORT R9215

1
FROM GPU TO REDRIVER
87 74 IN MXM_DP_A_ML_N<0> NO_TEST C9213
10% 16V
1 2 0.1uF
X5R 402
NO_TEST GPU_DP_EXT_ML_N<0> OUT 79 87
5%
100K
1/16W
MXM_DP_A_ML_P<1> NO_TEST C9214 1 2 0.1uF NO_TEST GPU_DP_EXT_ML_P<1> C9210
MF-LF

D
87 74 IN
10% 16V X5R 402
OUT 79 87

0.1UF
2 402
D
87 74 IN MXM_DP_A_ML_N<1> NO_TEST C9215 1 2 0.1uF NO_TEST GPU_DP_EXT_ML_N<1> OUT 79 87 87 74 BI MXM_DP_A_AUX_N 1 2 DP_EXT_AUX_N BI 79 81 87
10% 16V X5R 402
10%
87 74 IN MXM_DP_A_ML_P<2> NO_TEST C9216
10% 16V
1 2 0.1uF
X5R 402
NO_TEST GPU_DP_EXT_ML_P<2> OUT 79 87
16V
X5R
80 5 =PP5V_S0_DP_AUX_MUX 402

87 74 IN MXM_DP_A_ML_N<2> NO_TEST C9217

10% 16V
1 2 0.1uF
X5R 402
NO_TEST GPU_DP_EXT_ML_N<2> OUT 79 87
1
R9252

6
C9218 0.1uF SSM6N15FEAPE

D
87 74 IN MXM_DP_A_ML_P<3> NO_TEST 1 2 NO_TEST GPU_DP_EXT_ML_P<3> OUT 79 87 100K
10% 16V X5R 402 5% SOT563
1/16W Q9250
C9219 1 2 0.1uF MF-LF

G 2
87 74 IN MXM_DP_A_ML_N<3> NO_TEST NO_TEST GPU_DP_EXT_ML_N<3> OUT 79 87
2 402
10% 16V X5R 402
80 5 =PP5V_S0_DP_AUX_MUX
DDC_CA_DET_LS5V
74 OUT MXM_DP_A_HPD
MAKE_BASE=TRUE
GPU_DP_EXT_HPD IN 79
Q9251
1
R9202

G 5
SSM3K15FV
100K D 3 SOD-VESM-HF Q9250
5% SOT563
1/16W
MF-LF
SSM6N15FEAPE

S
2 402

4
G S 2
REDRIVER TO EXTERNAL CONNECTOR

DDC_CA_DET_LS5V_L
C9211
87 79 IN RDRV_DP_EXT_ML_P<0> NO_TEST C9230 1 2 0.1uF NO_TEST DP_EXT_ML_C_P<0> OUT 81 87 0.1UF
10% 16V X5R 402 Q9201 87 74 BI MXM_DP_A_AUX_P 1 2 DP_EXT_AUX_P BI 79 81 87

RDRV_DP_EXT_ML_N<0> C9231 1 2 0.1uF DP_EXT_ML_C_N<0> SSM3K15FV D 3

87 79 IN NO_TEST NO_TEST OUT 81 87
SOD-VESM-HF 10%
10% 16V X5R 402 16V
X5R
87 79 IN RDRV_DP_EXT_ML_P<1> NO_TEST C9232 1 2 0.1uF NO_TEST DP_EXT_ML_C_P<1> OUT 81 87
402
10% 16V X5R 402 R9216
1

C 87 79 IN RDRV_DP_EXT_ML_N<1> NO_TEST C9233

10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_EXT_ML_C_N<1> OUT 81 87 1 G S 2
100K
5%
1/16W
MF-LF
C
87 79 IN RDRV_DP_EXT_ML_P<2> NO_TEST C9234
10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_EXT_ML_C_P<2> OUT 81 87 81 79 IN DP_EXT_CA_DET 2 402

87 79 IN RDRV_DP_EXT_ML_N<2> NO_TEST C9235

10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_EXT_ML_C_N<2> OUT 81 87

87 79 IN RDRV_DP_EXT_ML_P<3> NO_TEST C9236 1 2 0.1uF NO_TEST DP_EXT_ML_C_P<3> OUT 81 87

10% 16V X5R 402

87 79 IN RDRV_DP_EXT_ML_N<3> NO_TEST C9237

10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_EXT_ML_C_N<3> OUT 81 87

79 OUT RDRV_DP_EXT_HPD DP_EXT_HPD IN 81

MAKE_BASE=TRUE

CRITICAL
L9170
R9170
47
FERR-220-OHM
75 MXM_PNL_BL_PWM 1 2 LCD_PWM_FILT 1 2 LCD_PWM 5
IN OUT
5% 0402
1/16W
MF-LF
402

MXM_DP_C_ML_P<0> NO_TEST C9220 1 2 0.1uF NO_TEST DP_INT_ML_C_P<0>

B
87 74 IN
10% 16V X5R 402
OUT 78 87

B
87 74 IN MXM_DP_C_ML_N<0> NO_TEST C9221
10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_INT_ML_C_N<0> OUT 78 87

87 74 IN MXM_DP_C_ML_P<1> NO_TEST C9222 1 2 0.1uF NO_TEST DP_INT_ML_C_P<1> OUT 78 87

10% 16V X5R 402

87 74 IN MXM_DP_C_ML_N<1> NO_TEST C9223

10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_INT_ML_C_N<1> OUT 78 87

MXM_DP_C_ML_P<2> NO_TEST C9224 1 2 0.1uF NO_TEST DP_INT_ML_C_P<2>

GPU TO INTERNAL CONNECTOR

87 74 IN OUT 78 87
10% 16V X5R 402

87 74 IN MXM_DP_C_ML_N<2> NO_TEST C9225

10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_INT_ML_C_N<2> OUT 78 87

87 74 IN MXM_DP_C_ML_P<3> NO_TEST C9226

10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_INT_ML_C_P<3> OUT 78 87

87 74 IN MXM_DP_C_ML_N<3> NO_TEST C9227

10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_INT_ML_C_N<3> OUT 78 87

87 74 BI MXM_DP_C_AUX_P NO_TEST C9200

10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_INT_AUX_P BI 78 87

87 74 BI MXM_DP_C_AUX_N NO_TEST C9201

10% 16V
1 2 0.1uF
X5R 402
NO_TEST DP_INT_AUX_N BI 78 87

R92001 R92011
100K 100K
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2

A =PP3V3_S0_DP 5 78 79 80

SYNC_MASTER=DAVE SYNC_DATE=01/07/2010 A
PAGE TITLE

74 OUT MXM_DP_C_HPD DP_INT_HPD

MAKE_BASE=TRUE
IN 78 DISPLAYPORT CONNECTIONS
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

R92101 REVISION
100K
1%
1/16W
R
A.0.0
MF-LF NOTICE OF PROPRIETARY PROPERTY: BRANCH
402 2
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
92 OF 110

5 =PP3V3_S0_DPCONN

CRITICAL L9400
220-OHM-1.4A
1 C9480 1 C9481 U9400 89 PP3V3_S0_DPFUSE
MIN_LINE_WIDTH=0.38 MM
1 2 89 PP3V3_S0_DPPWR
MIN_LINE_WIDTH=0.38 MM
TPS2051B 0603
10UF 0.1UF SOT23 MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
20% 20% 5 IN OUT 1
D
6.3V
2 X5R
603
2 10V
CERM
402 4 EN OC* 3 TP_DP_OC
CRITICAL D
GND
1 C9485
10UF 1
C9400
2 20%
6.3V
2 X5R 0.01UF
20%
603 2
50V
NOSTUFF
91 64 63 47 46 36 26 18 5 PM_SLP_S3_L CERM
IN 603
CRITICAL
D9410
RCLAMP0524P
SLP2510P8

5 IO IO 4
6 NC NC 7
GND

3 R9400
1 2 0
NOSTUFF
FL9400
12-OHM-100MA
TCM1210-4SM
4 SYM_VER-2 1

87 80 BI DP_EXT_ML_C_P<0>
87 80 BI DP_EXT_ML_C_N<0> 3 2
NOSTUFF
CRITICAL
D9410 R9401 R9406
RCLAMP0524P 1 2 0
SLP2510P8 OMIT_TABLE 1 2 0
C APPLE PART NO 514-0727 NOSTUFF
FL9403 C
2 IO IO 1 J9400 12-OHM-100MA
TCM1210-4SM
9 NC NC 10 MDP-PLST-K74-K75 4 SYM_VER-2 1
F-ANG-TH
GND

R9402 CRITICAL
1 2 0 1 2
3 2
3
NOSTUFF GND HPD

FL9401 NO_TEST 87 DP_ML_CONN_P<0> 3

ML_LANE0P CONFIG1 4
R9407
12-OHM-100MA NO_TEST 87 DP_ML_CONN_N<0> 5
ML_LANE0N CONFIG2 6 HDMI_CEC 1 2 0
TCM1210-4SM 7 8
4 SYM_VER-2 1 GND GND
87 80 DP_EXT_ML_C_P<1> NO_TEST87 DP_ML_CONN_P<1> 9 ML_LANE3P 10 87 DP_ML_CONN_P<3> NO_TEST DP_EXT_ML_C_P<3> 80 87
BI ML_LANE1P BI
DP_EXT_ML_C_N<1> NO_TEST 87 DP_ML_CONN_N<1> 11 12 DP_ML_CONN_N<3> NO_TEST DP_EXT_ML_C_N<3>
87 80 BI ML_LANE1N ML_LANE3N 87
BI 80 87
3 2 13 14
GND GND
R9403 NO_TEST 87 DP_ML_CONN_P<2> 15
ML_LANE2P AUX_CHP 16 DP_EXT_AUX_P BI 79 80 87

1 2 0 NO_TEST 87 DP_ML_CONN_N<2> 17
ML_LANE2N AUX_CHN 18 DP_EXT_AUX_N BI 79 80 87
19 20
RETURN DP_PWR
NOSTUFF
SHIELD PINS CRITICAL
1 D9411

22
R9425
R9404 1M
RCLAMP0524P
1 20 5%
SLP2510P8
1/16W
MF-LF
NOSTUFF 402
FL9402
12-OHM-100MA
2
5 IO IO 4
TCM1210-4SM 6 NC NC 7
4 SYM_VER-2 1
87 80 BI DP_EXT_ML_C_P<2>

GND
87 80 BI DP_EXT_ML_C_N<2>

B 3 2
CRITICAL
3
B
NOSTUFF D9400
CRITICAL R9405 RCLAMP0504F
1 2 0 SC70-6-1
D9411
RCLAMP0524P 6 DP_EXT_HPD OUT 80
SLP2510P8 DP_EXT_CA_DET 1
80 79 OUT

2 5
2 IO IO 1

9 NC NC 10
R94221 4
1M 3
GND

5%
1/16W
MF-LF
3 402
2

TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

514-0686 1 K22/K23 PROD. MDP J9400 CRITICAL METAL_IO

TABLE_5_ITEM

514-0727 1 K74/K75 MDP, PLASTIC, PD/NI J9400 CRITICAL PLASTIC_IO

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

Display: Ext DP Connector

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 81 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
K74/K75 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO

BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO

(MIL or MM) VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM NO_TYPE,BGA_P1MM MM 15.5.1 SPACING RULE SET
TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

PHYSICAL CONSTRAINTS
TABLE_SPACING_RULE_ITEM

DEFAULT * 0.1 MM ? TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_HEAD

GND * * STANDARD
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP STANDARD * =DEFAULT ? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD

DEFAULT * Y =50_OHM_SE =50_OHM_SE 100 MM 0 MM 0 MM TABLE_SPACING_RULE_HEAD

2X_DIELECTRIC * 0.150 MM ? NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_PHYSICAL_RULE_ITEM

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT 2X_DIELECTRIC TOP,BOTTOM 0.160 MM ? POWER * * STANDARD

D
TABLE_SPACING_RULE_ITEM

?
D 1.5:1_SPACING * 0.15 MM TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM
3X_DIELECTRIC * 0.220 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 2:1_SPACING * 0.2 MM ? TABLE_SPACING_RULE_ITEM

ON LAYER? 3X_DIELECTRIC TOP,BOTTOM 0.240 MM ?

TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM

35_OHM_SE TOP,BOTTOM Y 0.21 MM 0.085 MM =STANDARD 2.5:1_SPACING * 0.25 MM ? TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
4X_DIELECTRIC * 0.300 MM ?
35_OHM_SE * Y 0.19 MM 0.085 MM =STANDARD =STANDARD =STANDARD 3:1_SPACING * 0.3 MM ? TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM
4X_DIELECTRIC TOP,BOTTOM 0.320 MM ?
4:1_SPACING * 0.4 MM ? TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

5X_DIELECTRIC * 0.380 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM

ON LAYER? 5:1_SPACING * 0.5 MM ? TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

5X_DIELECTRIC TOP,BOTTOM 0.400 MM ?

39_OHM_SE TOP,BOTTOM Y 0.175 MM 0.085 MM =STANDARD TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM
6:1_SPACING * 0.6 MM ?
39_OHM_SE * Y 0.16 MM 0.085 MM =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD

ON LAYER? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_PHYSICAL_RULE_ITEM

45_OHM_SE TOP,BOTTOM Y 0.135 MM 0.085 MM =STANDARD TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM
GND * =STANDARD ?
45_OHM_SE * Y 0.12 MM 0.085 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM

GND_P2MM * 0.2 MM 1000

TABLE_SPACING_RULE_ITEM

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

PWR_P2MM * 0.2 MM 1000

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SWITCHNODE * 0.8 MM 1000

50_OHM_SE TOP,BOTTOM Y 0.1 MM 0.085 MM 15 MM
TABLE_PHYSICAL_RULE_ITEM

50_OHM_SE * Y 0.1 MM 0.085 MM =STANDARD =STANDARD =STANDARD

CONSTRAINTS FOR BGA AREA

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

55_OHM_SE TOP,BOTTOM Y 0.085 MM 0.085 MM =STANDARD TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

C 55_OHM_SE * Y 0.076 MM 0.075 MM =STANDARD =STANDARD =STANDARD

BGA_P1MM * =DEFAULT ?
TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM
C
BGA_P2MM * 0.2 MM ?

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_ASSIGNMENT_HEAD

ON LAYER? NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_PHYSICAL_RULE_ITEM

70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM
* * BGA_P1MM BGA_P1MM
70_OHM_DIFF ISL3,ISL6 Y 0.155 MM 0.085 MM =STANDARD 0.135 MM 0.1 MM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM
MEM_CLK * BGA_P1MM BGA_P2MM
70_OHM_DIFF TOP,BOTTOM Y 0.165 MM 0.085 MM =STANDARD 0.130 MM 0.1 MM TABLE_SPACING_ASSIGNMENT_ITEM

CLK_PCIE * BGA_P1MM BGA_P1MM

TABLE_SPACING_ASSIGNMENT_ITEM

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

CLK_LPC * BGA_P1MM BGA_P1MM

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

CLK_PCI * BGA_P1MM BGA_P1MM

85_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM

85_OHM_DIFF ISL3,ISL6 Y 0.115 MM 0.085 MM =STANDARD 0.2 MM 0.1 MM

TABLE_PHYSICAL_RULE_ITEM

85_OHM_DIFF TOP,BOTTOM Y 0.125 MM 0.085 MM =STANDARD 0.2 MM 0.1 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF ISL3,ISL6 Y 0.099 MM 0.085 MM 12 MM 0.200 MM 0.1 MM

TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF TOP,BOTTOM Y 0.110 MM 0.085 MM =STANDARD 0.200 MM 0.1 MM

B PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM
B
100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF ISL3,ISL6 Y 0.081 MM 0.085 MM =STANDARD 0.25 MM 0.1 MM

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF TOP,BOTTOM Y 0.091 MM 0.085 MM =STANDARD 0.25 MM 0.1 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

110_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

110_OHM_DIFF TOP,BOTTOM Y 0.075 MM 0.085 MM =STANDARD 0.320 MM 0.15 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.085 MM

TABLE_PHYSICAL_RULE_ITEM

POWER_WIDTH * Y 0.600 MM 0.200 MM 3.0 MM =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

POWER_CTL * Y 0.300 MM 0.200 MM 3.0 MM =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

RCOMP * Y 0.254 MM 0.200 MM 3.0 MM =STANDARD =STANDARD

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM

POWER BGA_P1MM POWER_CTL

TABLE_PHYSICAL_ASSIGNMENT_ITEM

POWER * POWER_WIDTH
A VR_CTL_PHY BGA_P1MM DEFAULT
TABLE_PHYSICAL_ASSIGNMENT_ITEM

SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
TABLE_PHYSICAL_ASSIGNMENT_ITEM PAGE TITLE
VR_CTL_PHY * POWER_CTL
K74/K75 RULE DEFINITIONS
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 82 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Memory Bus Constraints Memory Net Properties
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM

MEM_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM
MEM_70D MEM_CLK MEM_A_CLK_P<3..0> 11 32

MEM_39S * =39_OHM_SE =39_OHM_SE =39_OHM_SE =39_OHM_SE =STANDARD =STANDARD MEM_70D MEM_CLK MEM_A_CLK_N<3..0> 11 32
TABLE_PHYSICAL_RULE_ITEM

MEM_35S * =35_OHM_SE =35_OHM_SE =35_OHM_SE =35_OHM_SE =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF

MEM_39S MEM_CTRL MEM_A_CKE<3..0> 11 30

MEM_39S MEM_CTRL MEM_A_CS_L<3..0> 11 30

MEM_39S MEM_CTRL MEM_A_ODT<3..0> 11 30

D TABLE_SPACING_RULE_HEAD
MEM_35S MEM_CMD MEM_A_A<15..0> 11 30 D
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MEM_35S MEM_CMD MEM_A_BA<2..0> 11 30
TABLE_SPACING_RULE_ITEM

MEM_35S MEM_CMD MEM_A_RAS_L 11 30

MEM_CLK2MEM * =4:1_SPACING ?
TABLE_SPACING_RULE_ITEM
MEM_35S MEM_CMD MEM_A_CAS_L 11 30

MEM_CTRL2CTRL * =2:1_SPACING ? MEM_35S MEM_CMD MEM_A_WE_L 11 30

TABLE_SPACING_RULE_ITEM

MEM_CTRL2MEM * =2.5:1_SPACING ? MEM_45S MEM_DQ_EVEN MEM_A_DQ<7..0> 11 32

TABLE_SPACING_RULE_ITEM

MEM_45S MEM_DQ_EVEN MEM_A_DM<0> 11 32

MEM_CMD2CMD * =1.5:1_SPACING ?
TABLE_SPACING_RULE_ITEM

MEM_45S MEM_DQ_ODD MEM_A_DQ<15..8> 11 32

MEM_CMD2MEM * =3:1_SPACING ?
TABLE_SPACING_RULE_ITEM
MEM_45S MEM_DQ_ODD MEM_A_DM<1> 11 32

MEM_DQ_ODD2DQ_ODD * =3:1_SPACING ?
MEM_45S MEM_DQ_EVEN MEM_A_DQ<23..16> 11 32
TABLE_SPACING_RULE_ITEM

MEM_DQ_ODD2MEM * =3:1_SPACING ? MEM_45S MEM_DQ_EVEN MEM_A_DM<2> 11 32

TABLE_SPACING_RULE_ITEM

MEM_DQ_EVEN2DQ_EVEN * =3:1_SPACING ? MEM_45S MEM_DQ_ODD MEM_A_DQ<31..24> 11 32

TABLE_SPACING_RULE_ITEM

MEM_45S MEM_DQ_ODD MEM_A_DM<3> 11 32

MEM_DQ_EVEN2MEM * =3:1_SPACING ?
TABLE_SPACING_RULE_ITEM

MEM_45S MEM_DQ_EVEN MEM_A_DQ<39..32> 11 32

MEM_DQ_EVEN2DQ_ODD * =5:1_SPACING ?
MEM_45S MEM_DQ_EVEN MEM_A_DM<4> 11 32
TABLE_SPACING_RULE_ITEM

MEM_DQS2MEM * =3:1_SPACING ?
TABLE_SPACING_RULE_ITEM
MEM_45S MEM_DQ_ODD MEM_A_DQ<47..40> 11 32

MEM_2OTHER * =3:1_SPACING ? MEM_45S MEM_DQ_ODD MEM_A_DM<5> 11 32

MEM_45S MEM_DQ_EVEN MEM_A_DQ<55..48> 11 32

MEM_45S MEM_DQ_EVEN MEM_A_DM<6> 11 32

MEM_45S MEM_DQ_ODD MEM_A_DQ<63..56> 11 32

MEM_A_DM<7>
Memory Bus Spacing Group Assignments
MEM_45S MEM_DQ_ODD 11 32
MEMORY POWER PROPERTIES
MEM_70D MEM_DQS MEM_A_DQS_P<0> 11 32 NET_TYPE

C NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE
TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_70D

MEM_70D
MEM_DQS

MEM_DQS
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
11 32

11 32
VOLTAGE PHYSICAL SPACING C
MEM_CLK MEM_CLK * MEM_CLK2MEM MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_POWER_PHY MEM_POWER CPU_DIMM_VREF_A 11 28
MEM_70D MEM_DQS MEM_A_DQS_N<1> 11 32
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_POWER_PHY MEM_POWER CPU_DIMM_VREF_B 11 28

MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_70D MEM_DQS MEM_A_DQS_P<2> 11 32
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_70D MEM_DQS MEM_A_DQS_N<2> 11 32

MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_DQS MEM_CMD * MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_70D MEM_DQS MEM_A_DQS_P<3> 11 32

MEM_CLK MEM_DQ_ODD * MEM_CLK2MEM MEM_DQS MEM_DQ_ODD * MEM_DQS2MEM MEM_70D MEM_DQS MEM_A_DQS_N<3> 11 32

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_70D MEM_DQS MEM_A_DQS_P<4> 11 32

MEM_CLK MEM_DQS * MEM_CLK2MEM MEM_DQS MEM_DQS * MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_70D MEM_DQS MEM_A_DQS_N<4> 11 32

MEM_CLK MEM_DQ_EVEN * MEM_CLK2MEM MEM_DQS MEM_DQ_EVEN * MEM_DQS2MEM MEM_70D MEM_DQS MEM_A_DQS_P<5> 11 32

MEM_70D MEM_DQS MEM_A_DQS_N<5> 11 32

TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

MEM_70D MEM_DQS MEM_A_DQS_P<6> 11 32

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_70D MEM_DQS MEM_A_DQS_N<6> 11 32

MEM_DQ_ODD MEM_CLK * MEM_DQ_ODD2MEM MEM_DQ_EVEN MEM_CLK * MEM_DQ_EVEN2MEM MEM_70D MEM_DQS MEM_A_DQS_P<7> 11 32

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_70D MEM_DQS MEM_A_DQS_N<7> 11 32

MEM_DQ_ODD MEM_CTRL * MEM_DQ_ODD2MEM MEM_DQ_EVEN MEM_CTRL * MEM_DQ_EVEN2MEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQ_ODD MEM_CMD * MEM_DQ_ODD2MEM MEM_DQ_EVEN MEM_CMD * MEM_DQ_EVEN2MEM

MEM_DQ_ODD MEM_DQ_ODD * MEM_DQ_ODD2DQ_ODD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQ_EVEN MEM_DQ_EVEN *
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQ_EVEN2DQ_EVEN MEM_70D MEM_CLK MEM_B_CLK_P<3..0> 11 32

Memory Net Properties
NET_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_70D MEM_CLK MEM_B_CLK_N<3..0> 11 32

MEM_DQ_ODD MEM_DQS * MEM_DQ_ODD2MEM MEM_DQ_EVEN MEM_DQS * MEM_DQ_EVEN2MEM ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQ_ODD MEM_DQ_EVEN * MEM_DQ_EVEN2DQ_ODD MEM_DQ_EVEN MEM_DQ_ODD * MEM_DQ_EVEN2DQ_ODD MEM_70D MEM_DQS MEM_B_DQS_P<0> 11 32

MEM_70D MEM_DQS MEM_B_DQS_N<0> 11 32

MEM_39S MEM_CTRL MEM_B_CKE<3..0> 11 31
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

MEM_70D MEM_DQS MEM_B_DQS_P<1> 11 32

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_39S MEM_CTRL MEM_B_CS_L<3..0> 11 31
MEM_70D MEM_DQS MEM_B_DQS_N<1> 11 32
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_39S MEM_CTRL MEM_B_ODT<3..0> 11 31

MEM_CTRL MEM_CLK * MEM_CTRL2MEM MEM_CMD MEM_CLK * MEM_CMD2MEM MEM_70D MEM_DQS MEM_B_DQS_P<2> 11 32

MEM_B_A<15..0> MEM_B_DQS_N<2>
B
MEM_35S MEM_CMD MEM_70D MEM_DQS
B
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

11 31 11 32
MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_CMD MEM_CTRL * MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_35S MEM_CMD MEM_B_BA<2..0> 11 31 MEM_70D MEM_DQS MEM_B_DQS_P<3> 11 32

MEM_CTRL MEM_CMD * MEM_CTRL2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_35S MEM_CMD MEM_B_RAS_L 11 31 MEM_70D MEM_DQS MEM_B_DQS_N<3> 11 32
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_35S MEM_CMD MEM_B_CAS_L 11 31 MEM_70D MEM_DQS MEM_B_DQS_P<4> 11 32

MEM_CTRL MEM_DQ_ODD * MEM_CTRL2MEM MEM_CMD MEM_DQ_ODD * MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_35S MEM_CMD MEM_B_WE_L 11 31 MEM_70D MEM_DQS MEM_B_DQS_N<4> 11 32

MEM_CTRL MEM_DQS * MEM_CTRL2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM MEM_70D MEM_DQS MEM_B_DQS_P<5> 11 32

MEM_45S MEM_DQ_EVEN MEM_B_DQ<7..0> 11 32
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_70D MEM_DQS MEM_B_DQS_N<5> 11 32

MEM_CTRL MEM_DQ_EVEN * MEM_CTRL2MEM MEM_CMD MEM_DQ_EVEN * MEM_CMD2MEM MEM_45S MEM_DQ_EVEN MEM_B_DM<0> 11 32
MEM_70D MEM_DQS MEM_B_DQS_P<6> 11 32
TABLE_SPACING_ASSIGNMENT_HEAD

MEM_45S MEM_DQ_ODD MEM_B_DQ<15..8> 11 32 MEM_70D MEM_DQS MEM_B_DQS_N<6> 11 32

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_45S MEM_DQ_ODD MEM_B_DM<1> 11 32 MEM_70D MEM_DQS MEM_B_DQS_P<7> 11 32

MEM_CLK * * MEM_2OTHER MEM_70D MEM_DQS MEM_B_DQS_N<7> 11 32

MEM_45S MEM_DQ_EVEN MEM_B_DQ<23..16> 11 32
TABLE_SPACING_ASSIGNMENT_ITEM

I160 MEM_RCOMP_PHY MEM_RCOMP CPU_SM_RCOMP0 10

MEM_CTRL * * MEM_2OTHER MEM_45S MEM_DQ_EVEN MEM_B_DM<2> 11 32
TABLE_SPACING_ASSIGNMENT_ITEM
I159 MEM_RCOMP_PHY MEM_RCOMP CPU_SM_RCOMP1 10

MEM_CMD * * MEM_2OTHER MEM_45S MEM_DQ_ODD MEM_B_DQ<31..24> 11 32 I161 MEM_RCOMP_PHY MEM_RCOMP CPU_SM_RCOMP2 10

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_45S MEM_DQ_ODD MEM_B_DM<3> 11 32

MEM_DQ_ODD * * MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_45S MEM_DQ_EVEN MEM_B_DQ<39..32> 11 32

MEM_DQS * * MEM_2OTHER
MEM_45S MEM_DQ_EVEN MEM_B_DM<4> 11 32
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQ_EVEN * * MEM_2OTHER
MEM_45S MEM_DQ_ODD MEM_B_DQ<47..40> 11 32

MEM_45S MEM_DQ_ODD MEM_B_DM<5> 11 32

Need to support MEM_*-style wildcards!
TABLE_PHYSICAL_RULE_HEAD
MEM_45S MEM_DQ_EVEN MEM_B_DQ<55..48> 11 32

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_45S MEM_DQ_EVEN MEM_B_DM<6> 11 32
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

MEM_POWER_WIDTH * Y 0.500 MM 0.175 MM =STANDARD =STANDARD =STANDARD MEM_45S MEM_DQ_ODD MEM_B_DQ<63..56> 11 32

MEM_45S MEM_DQ_ODD MEM_B_DM<7> 11 32

TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_RULE_HEAD

A NET_PHYSICAL_TYPE

MEM_POWER_PHY
AREA_TYPE

*
PHYSICAL_RULE_SET

MEM_POWER_WIDTH
TABLE_PHYSICAL_ASSIGNMENT_ITEM
SPACING_RULE_SET

MEM_POWER
LAYER

*
LINE-TO-LINE SPACING

0.2 MM
WEIGHT

?
TABLE_SPACING_RULE_ITEM

SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

Memory Constraints
DRAWING NUMBER SIZE

TABLE_PHYSICAL_RULE_HEAD

Apple Inc. 051-8337 D

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP REVISION
ON LAYER?

MEM_RCOMP_PHY * Y 0.175 MM 0.175 MM =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
TABLE_SPACING_RULE_HEAD

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT THE POSESSOR AGREES TO THE FOLLOWING: PAGE

MEM_RCOMP * 0.2 MM ?
TABLE_SPACING_RULE_ITEM I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
101 OF 110

PCIE_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE GRAPHICS

PCIE_85D PCIE PEG_R2D_C_P<15..0> 8 76
TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD

PCIE_85D PCIE PEG_R2D_C_N<15..0> 8 76

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
PCIE_85D PCIE PEG_D2R_P<15..0> 8 76

PCIE * =4X_DIELECTRIC ? PCIE TOP,BOTTOM =4X_DIELECTRIC ? PCIE_85D PCIE PEG_D2R_N<15..0> 8 76

TABLE_SPACING_RULE_ITEM

PCIE_85D PCIE MXM_PCIE_R2D_P<15..0> 74 76

CLK_PCIE * 0.5 MM ?
MXM_PCIE_R2D_N<15..0>

D
PCIE_85D

PCIE_85D
PCIE

PCIE MXM_PCIE_D2R_P<15..0>
74 76

74 76 D
PCIE_85D PCIE MXM_PCIE_D2R_N<15..0> 74 76

CPU
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

PCIE I/O
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
PCIE_85D PCIE PCIE_MINI_R2D_P 33
TABLE_PHYSICAL_RULE_ITEM

CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD PCIE_85D PCIE PCIE_MINI_R2D_N 33
TABLE_PHYSICAL_RULE_ITEM

PCIE_85D PCIE PCIE_MINI_R2D_C_P 17 33

CPU_RCOMP_PHY * Y 0.254 MM 0.200 MM 3.0 MM =STANDARD =STANDARD
PCIE_85D PCIE PCIE_MINI_R2D_C_N 17 33

PCIE_85D PCIE PCIE_MINI_D2R_P 17 33

TABLE_SPACING_RULE_HEAD

PCIE_85D PCIE PCIE_MINI_D2R_N 17 33

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM

CPU_AGTL * =STANDARD ?
TABLE_SPACING_RULE_ITEM

PCIE_85D PCIE PCIE_FW_R2D_P 39

CPU_ITP * 0.2 MM ?
PCIE_85D PCIE PCIE_FW_R2D_N 39
TABLE_SPACING_RULE_ITEM

CPU_RCOMP * 0.2 MM ? PCIE_85D PCIE PCIE_FW_R2D_C_P 17 39

PCIE_85D PCIE PCIE_FW_R2D_C_N 17 39

PCIE_85D PCIE PCIE_FW_D2R_P 17 39

PCIE_85D PCIE PCIE_FW_D2R_N 17 39

PCIE_85D PCIE PCIE_FW_D2R_C_P 39

PCIE_85D PCIE PCIE_FW_D2R_C_N 39

SATA Interface Constraints

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

SATA_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

DMI
C SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM
PCIE_85D PCIE DMI_S2N_P<3..0> 9 18
C
SATA * =5X_DIELECTRIC ? SATA TOP,BOTTOM =5X_DIELECTRIC ? PCIE_85D PCIE DMI_S2N_N<3..0> 9 18

PCIE_85D PCIE DMI_N2S_P<3..0> 9 18

PCIE_85D PCIE DMI_N2S_N<3..0> 9 18

FDI

PCIE REF CLOCKS

CLK_PCIE_100D CLK_PCIE GPU_CLK100M_PCIE_P 8
NET_TYPE
CLK_PCIE_100D CLK_PCIE GPU_CLK100M_PCIE_N 8
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_P 17 33

CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_N 17 33

CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FW_P 17 39

CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FW_N 17 39

ENET_100D ENET_MII PCIE_CLK100M_ENET_P 17 37

ENET_100D ENET_MII PCIE_CLK100M_ENET_N 17 37

SATA
SATA_85D SATA SATA_HDD_R2D_C_P 17 42

SATA_85D SATA SATA_HDD_R2D_C_N 17 42

SATA_85D SATA SATA_HDD_R2D_P 42

SATA_85D SATA SATA_HDD_R2D_N 42

B SATA_85D

SATA_85D
SATA

SATA
SATA_HDD_D2R_P
SATA_HDD_D2R_N
17 42

17 42
B
SATA_85D SATA SATA_HDD_D2R_C_P 42

SATA_85D SATA SATA_HDD_D2R_C_N 42

SATA_85D SATA SATA_ODD_R2D_C_P 17 42

SATA_85D SATA SATA_ODD_R2D_C_N 17 42

SATA_85D SATA SATA_ODD_R2D_P 42

SATA_85D SATA SATA_ODD_R2D_N 42

SATA_85D SATA SATA_ODD_D2R_P 17 42

SATA_85D SATA SATA_ODD_D2R_N 17 42

SATA_85D SATA SATA_ODD_D2R_C_P 42

SATA_85D SATA SATA_ODD_D2R_C_N 42

CLOCKS
CPU ITP CLK_PCIE_100D CLK_PCIE FSB_CLK133M_CPU_P 10 20

CPU_50S CPU_ITP XDP_BPM_L<7..0> 10 24 CLK_PCIE_100D CLK_PCIE FSB_CLK133M_CPU_N 10 20

CPU_50S CPU_ITP CPU_CFG<17..0> 9 14 24 CLK_PCIE_100D CLK_PCIE GFX_CLK120M_DPLLSS_P 10 17

CPU_50S CPU_ITP XDP_OBSDATA_A<3..0> 24 CLK_PCIE_100D CLK_PCIE GFX_CLK120M_DPLLSS_N 10 17

CLK_PCIE_100D CLK_PCIE FSB_CLK133M_ITP_P 10 24

CLK_PCIE_100D CLK_PCIE FSB_CLK133M_ITP_N 10 24

CPU_MISC
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_CPU_P 10 17
CPU_RCOMP_PHY CPU_RCOMP CPU_PEG_COMP 9
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_CPU_N 10 17
CPU_RCOMP_PHY CPU_RCOMP CPU_PEG_RBIAS 9
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_PCH_P 17 25
CPU_RCOMP_PHY CPU_RCOMP CPU_COMP3 10
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_PCH_N 17 25
CPU_RCOMP_PHY CPU_RCOMP CPU_COMP2 10

CPU_RCOMP_PHY CPU_RCOMP CPU_COMP1 10

CPU_RCOMP_PHY CPU_RCOMP CPU_COMP0 10

CLK_PCIE_100D CLK_PCIE FSB_CLK133M_PCH_P 17 25

A CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE
FSB_CLK133M_PCH_N
PCH_CLK96M_DOT_P
17 25

17 25
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE
CLK_PCIE_100D

CLK_PCIE_100D
CLK_PCIE

CLK_PCIE
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P 17 25
PCIE/DMI/FDI/SATA CONSTRAINTS
DRAWING NUMBER SIZE
PCH_CLK100M_SATA_N
ANY OTHER LYNNFIELD CONSTRAINTS NOT COVERED ON PAGES 101 AND 107 SHOULD GO ON THIS PAGE TOO
CLK_PCIE_100D CLK_PCIE 17 25

Apple Inc. 051-8337 D

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

PCH_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

CLK_PCH_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_ITEM

CLK_PCH * 0.2 MM ?
TABLE_SPACING_RULE_ITEM

COMP_PCH * 0.2 MM ?

D D
PCI Bus Constraints
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

CLK_PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_ITEM

NET_TYPE NET_TYPE
PCI * =STANDARD ? ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
PCI_55S PCI
TABLE_SPACING_RULE_ITEM

CLK_PCI * 0.2 MM ? PCI_REQ0_L 19

PCI_55S PCI SPI_55S SPI SPI_CLK_R 17 48 55
PCI_REQ1_L 19
SPI_55S SPI SPI_CLK 55

CLK_PCI_55S CLK_PCI SPI_55S SPI SPI_MOSI_R 17 48 55

PCH_CLK33M_PCIOUT 19 27
SPI_55S SPI SPI_MOSI 55

LPC Bus Constraints CLK_PCI_55S CLK_PCI

PCH_CLK33M_PCIIN 17 27 SPI_55S SPI SPI_MISO 17 48 55

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

LPC_55S LPC SPI_55S SPI SPI_MISO_R 55

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LPC_AD<3..0> 17 46 48
TABLE_PHYSICAL_RULE_ITEM
SPI_55S SPI SPI_CS0_R_L 17 48

LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD LPC_55S LPC SPI_55S SPI SPI_CS0_L 48
LPC_FRAME_L 17 46 48
TABLE_PHYSICAL_RULE_ITEM

SPI_55S SPI SPI_MLB_CS_L 48 55

CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
SPI_55S SPI SPI_ALT_CS_L 48

SPI_55S SPI SPIROM_USE_MLB 20 48

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CLK_LPC_55S CLK_LPC SPI_55S SPI SPI_ALT_MOSI 48
LPC_CLK33M_SMC_R 19 27

C LPC * 0.15 MM ?
TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM
CLK_LPC_55S

CLK_LPC_55S
CLK_LPC

CLK_LPC
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
27 46

27 48
SPI_55S

SPI_55S
SPI

SPI
SPI_ALT_MISO
SPI_ALT_CLK
48

48
C
CLK_LPC * 0.2 MM ? CLK_LPC_55S PM HDA_55S HDA HDA_BIT_CLK 17 56
PM_CLK32K_SUSCLK_R 8 18 91
CLK_LPC_55S PM
PM_CLK32K_SUSCLK 8 46 91
CLK_LPC_55S CLK_LPC HDA_55S HDA HDA_BIT_CLK_R 17
LPC_CLK33M_LPCPLUS_R 19 27
HDA_55S HDA HDA_RST_L 17 56

USB 2.0 Interface Constraints USB_90D USB

USB_EXTA_P 34 43
HDA_55S HDA HDA_RST_R_L 17

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

USB_90D USB HDA_55S HDA HDA_SDOUT 17 56

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB_EXTA_N 34 43
USB_90D USB HDA_55S HDA HDA_SDOUT_R 17
TABLE_PHYSICAL_RULE_ITEM
USB_PORT0_P 43
USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF USB_90D USB HDA_55S HDA HDA_SYNC 17 56
USB_PORT0_N 43
USB_90D USB HDA_55S HDA HDA_SYNC_R 17
USB_EXTB_P 35 43
USB_90D USB HDA_55S HDA HDA_SDIN0 17 56
USB_EXTB_N 35 43
USB_90D USB HDA_55S HDA AUD_SDI_R 56
TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
USB_PORT1_P 43
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_90D USB HDA AUD_SPDIF_IN 60 77
USB_PORT1_N 43
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

USB_90D USB HDA AUD_SPDIF_OUT 56 60

USB * =2x_DIELECTRIC ? USB TOP,BOTTOM =4x_DIELECTRIC ? USB_EXTC_P 34 43
USB_90D USB HDA AUD_SPDIF_CHIP 56
USB_EXTC_N 34 43
USB_90D USB HDA_55S HDA AUD_SPKR_OUTLO1L_NOUT 59 60 92
USB_PORT2_P 43
USB_90D USB HDA_55S HDA AUD_SPKR_OUTLO1L_POUT 59 60 92
USB_PORT2_N 43
AUD_SPKR_OUTLO1R_NOUT
SMBus Interface Constraints USB_90D

USB_90D
USB

USB
USB_EXTD_P 35 43
HDA_55S

HDA_55S
HDA

HDA AUD_SPKR_OUTLO1R_POUT
58 60 92

58 60 92
TABLE_PHYSICAL_RULE_HEAD
USB_EXTD_N 35 43
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB_90D USB HDA_55S HDA AUD_SPKR_OUTLO2L_NOUT 59 60 92
ON LAYER? USB_D_MUXED_P 43
TABLE_PHYSICAL_RULE_ITEM

USB_90D USB HDA_55S HDA AUD_SPKR_OUTLO2L_POUT 59 60 92

SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_D_MUXED_N 43
USB_90D USB HDA_55S HDA AUD_SPKR_OUTLO2R_NOUT 58 60 92
USB_PORT3_P 43
USB_90D USB HDA_55S HDA AUD_SPKR_OUTLO2R_POUT 58 60 92
TABLE_SPACING_RULE_HEAD
USB_PORT3_N 43
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_90D USB
USB_CAMERA_P 34 44
USB_90D USB
TABLE_SPACING_RULE_ITEM

SMB * =2x_DIELECTRIC ? USB_CAMERA_N 34 44

B
USB_90D
USB_90D
USB
USB
USB_CAMERA_L_P
USB_CAMERA_L_N
44 92

44 92
CLK_XTAL

CLK_XTAL
XTAL

XTAL
PCH_CLK25M_XTALOUT
PCH_CLK25M_XTALIN
17 27

17 27
B
USB_90D USB
USB_BT_P 35 44 PCH_55S COMP_PCH
PCH_USB_RBIAS
HD Audio Interface Constraints USB_90D

USB_90D
USB

USB
USB_BT_N 35 44 PCH_55S COMP_PCH
PCH_SATAICOMP
19

17
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD
USB_BT_L_P 44 92 PCH_55S COMP_PCH
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB_90D USB PCH_XCLK_RCOMP 17
USB_BT_L_N 44 92 PCH_55S COMP_PCH
TABLE_PHYSICAL_RULE_ITEM

USB_90D USB PCH_DMI_COMP 18

HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_IR_P 34 44
USB_90D USB
USB_IR_N 34 44
USB_90D USB
TABLE_SPACING_RULE_HEAD
USB_IR_L_P 44 92
CLK_XTAL XTAL
USB_HUB1_XTAL1 34
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_90D USB
USB_IR_L_N 44 92
CLK_XTAL XTAL
USB_HUB1_XTAL2 34
TABLE_SPACING_RULE_ITEM

USB_90D USB
HDA * =2x_DIELECTRIC ? USB_SDCARD_P 35 44 PCH_55S COMP_PCH
USB_90D USB USB_HUB1_RBIAS 34
USB_SDCARD_N 35 44
USB_90D USB
USB_SDCARD_L_P 44 92
USB_90D USB
USB_SDCARD_L_N 44 92
CLK_XTAL XTAL
USB_HUB2_XTAL1 35
CLK_XTAL XTAL
USB_HUB2_XTAL2 35
PCH_55S COMP_PCH
USB_HUB2_RBIAS 35

SPI Interface Constraints

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CLK_XTAL XTAL PCH_CLK32K_RTCX1 17 27

TABLE_SPACING_RULE_ITEM

CLK_XTAL XTAL PCH_CLK32K_RTCX2 17 27

SPI * 0.2 MM ?

A CLK_XTAL

CLK_XTAL
XTAL

XTAL
CK505_XTAL_IN
CK505_XTAL_OUT
25

25 SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

XTAL Constraints CLK_PCH_55S CLK_PCH PCH_CLK14P3M_REFCLK 17 25 IBEX PEAK CONSTRAINTS

DRAWING NUMBER SIZE
051-8337 D
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
Apple Inc. REVISION
CLK_XTAL * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF
USB_90D USB
USB_HUB1_UP_P 19 34
R
A.0.0
TABLE_SPACING_RULE_HEAD
USB_90D USB
USB_HUB1_UP_N 19 34
NOTICE OF PROPRIETARY PROPERTY: BRANCH
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_90D USB THE INFORMATION CONTAINED HEREIN IS THE
USB_HUB2_UP_P 19 35 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
TABLE_SPACING_RULE_ITEM

USB_90D USB THE POSESSOR AGREES TO THE FOLLOWING: PAGE

USB_HUB2_UP_N
XTAL * =4X_DIELECTRIC ? 19 35
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
103 OF 110

ENET_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD

ENET_50S ENET_SE BCM5764_RDAC 37

ENET_50S BUF0_CLK BCM5764_CLK25M_XTALI 36 37

ENET_50S BUF0_CLK BCM5764_CLK25M_XTALO 36 37

TABLE_SPACING_RULE_HEAD

ENET_50S BUF0_CLK BCM5764_CLK25M_XTAL 36

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
ENET_100D ENET_DIFF ENET_MDI_P<3..0> 37 38

BUF0_CLK * =3:1_SPACING ? ENET_100D ENET_DIFF ENET_MDI_N<3..0> 37 38

TABLE_SPACING_RULE_ITEM

ENET_MII * 0.3 MM ? ENET_100D ENET_DIFF ENET_MDI_T_P<3..0> 38

D ENET_SE * =STANDARD ?
TABLE_SPACING_RULE_ITEM

ENET_100D ENET_DIFF ENET_MDI_T_N<3..0> 38

D
ENET_100D ENET_MII PCIE_ENET_R2D_P 37

ENET_100D ENET_MII PCIE_ENET_R2D_N 37

SOURCE:BROADCOM 5764M-DS04-RDS. PAGE 38
ENET_100D ENET_MII PCIE_ENET_D2R_P 17 37

PCIE_ENET_D2R_N
CAESAR II (ETHERNET) CONSTRAINTS ENET_100D

ENET_100D
ENET_MII

ENET_MII PCIE_ENET_R2D_C_P
17 37

17 37
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_100D ENET_MII PCIE_ENET_R2D_C_N 17 37
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

ENET_100D ENET_MII PCIE_ENET_D2R_C_P 37

ENET_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
ENET_100D ENET_MII PCIE_ENET_D2R_C_N 37

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_ITEM
SD_50S SD SDCONN_CMD 37 45

ENET_DIFF * 0.6 MM ? SD_50S SD SDCONN_CLK 37 45

SD_50S SD SDCONN_CLK_R 45

SD_50S SD SDCONN_DATA<7..0> 37 45

CAESAR IV (SD) CONSTRAINTS SD_50S SD BCM57765_CR_DATA<7..4> 37

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

SD_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD

TABLE_SPACING_RULE_HEAD
FireWire Net Properties
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_TYPE

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

TABLE_SPACING_RULE_ITEM

SD * =3:1_SPACING ?
FW_110D FW_TP FW_PORT0_TPA_P 40 41

FW_110D FW_TP FW_PORT0_TPA_N 40 41

FireWire Interface Constraints FW_110D FW_TP FW_PORT0_TPB_P 40 41

TABLE_PHYSICAL_RULE_HEAD

FW_110D FW_TP FW_PORT0_TPB_N 40 41

C PHYSICAL_RULE_SET

FW_110D
LAYER

*
ALLOW ROUTE
ON LAYER?

=110_OHM_DIFF
MINIMUM LINE WIDTH

=110_OHM_DIFF
MINIMUM NECK WIDTH

=110_OHM_DIFF
MAXIMUM NECK LENGTH

=110_OHM_DIFF
DIFFPAIR PRIMARY GAP

=110_OHM_DIFF
DIFFPAIR NECK GAP

=110_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
FW_110D

FW_110D
FW_TP

FW_TP
FW_PORT0_TPA_F_P
FW_PORT0_TPA_F_N
41

41
C
FW_110D FW_TP FW_PORT0_TPB_F_P 41
TABLE_SPACING_RULE_HEAD

FW_110D FW_TP FW_PORT0_TPB_F_N 41

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM

FW_TP * =3:1_SPACING ?
PORT 1 & 2 NOT USED
FW_110D FW_TP FW_P0_TPA_L_P 40

FW_110D FW_TP FW_P0_TPA_L_N 40

FW_110D FW_TP FW_P0_TPB_L_P 40

FW_110D FW_TP FW_P0_TPB_L_N 40

UNUSED FW NETS PHYSICAL PROPERTIES

FW_110D FW_TP FW_P1_TPA_P 39 40

FW_110D FW_TP FW_P1_TPA_N 39 40

FW_110D FW_TP FW_P2_TPA_P 39 40

FW_110D FW_TP FW_P2_TPA_N 39 40

AUDIO NET PROPERTIES

AUDIO CONSTRAINTS ELECTRICAL_CONSTRAINT_SET PHYSICAL
NET_TYPE

SPACING
TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT AUD_DIFF AUDIO AUDAMPINBLN 58

TABLE_SPACING_RULE_ITEM

AUD_DIFF AUDIO AUDAMPINBLP 58

AUDIO * =3:1_SPACING ?
AUD_DIFF AUDIO AUDAMPINLN 58

AUD_DIFF AUDIO AUDAMPINLP 58

B B
TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET AUD_DIFF AUDIO AUD_LO2_N_R 56 58

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AUD_DIFF AUDIO AUD_LO2_P_R 56 58

AUD_DIFF * 1:1_DIFFPAIR
AUD_DIFF AUDIO AUDAMPINBRN 58

AUD_DIFF AUDIO AUDAMPINBRP 58

AUD_DIFF AUDIO AUDAMPINRN 58

AUD_DIFF AUDIO AUDAMPINRP 58

AUD_DIFF AUDIO AUD_LO1_N_R 56 58

AUD_DIFF AUDIO AUD_LO1_P_R 56 58

AUD_DIFF AUDIO AUDAMPINCLN 59

AUD_DIFF AUDIO AUDAMPINCLP 59

AUD_DIFF AUDIO AUD_AMPINLN 59

AUD_DIFF AUDIO AUD_AMPINLP 59

AUD_DIFF AUDIO AUD_LO2_N_L 56 59

AUD_DIFF AUDIO AUD_LO2_P_L 56 59

AUD_DIFF AUDIO AUDAMPINCRN 59

AUD_DIFF AUDIO AUDAMPINCRP 59

AUD_DIFF AUDIO AUD_AMPINRN 59

AUD_DIFF AUDIO AUD_AMPINRP 59

AUD_DIFF AUDIO AUD_LO1_N_L 56 59

AUD_DIFF AUDIO AUD_LO1_P_L 56 59

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

ENET/SD/FW/AUD CONSTRAINTS
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ASSINGED IN CONT. MGR.
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

DP_85D * =85_OHM_DIFF =85_OHM_DIFF 0.08MM =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

I113 DP_85D DISPLAYPORT MXM_DP_C_ML_P<3..0> 74 80

I114 DP_85D DISPLAYPORT MXM_DP_C_ML_N<3..0> 74 80

TABLE_SPACING_RULE_HEAD

DP_85D DISPLAYPORT DP_INT_ML_C_P<3..0> 78 80

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
DP_85D DISPLAYPORT DP_INT_ML_C_N<3..0> 78 80

DISPLAYPORT * =3:1_SPACING ? DP_85D DISPLAYPORT MXM_DP_C_AUX_P 74 80

DP_85D DISPLAYPORT MXM_DP_C_AUX_N 74 80

D D
DP_85D DISPLAYPORT DP_INT_AUX_P 78 80

DP_85D DISPLAYPORT DP_INT_AUX_N 78 80

DP_85D DISPLAYPORT MXM_DP_A_ML_P<3..0> 74 80

DP_85D DISPLAYPORT MXM_DP_A_ML_N<3..0> 74 80

DP_85D DISPLAYPORT GPU_DP_EXT_ML_P<3..0> 79 80

PAIRS SHOULD BE WITHIN 100 MILS OF CLOCK LENGTH.
DP_85D DISPLAYPORT GPU_DP_EXT_ML_N<3..0> 79 80
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DP_85D DISPLAYPORT RDRV_DP_EXT_ML_P<3..0> 79 80
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
DP_85D DISPLAYPORT RDRV_DP_EXT_ML_N<3..0> 79 80
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

DP_85D DISPLAYPORT DP_EXT_ML_C_P<3..0> 80 81

DP_85D DISPLAYPORT DP_EXT_ML_C_N<3..0> 80 81

DP_85D DISPLAYPORT DP_ML_CONN_P<3..0> 81

DP_85D DISPLAYPORT DP_ML_CONN_N<3..0> 81

DP_85D DISPLAYPORT MXM_DP_A_AUX_P 74 80

DP_85D DISPLAYPORT MXM_DP_A_AUX_N 74 80

DP_85D DISPLAYPORT RDRV_DP_EXT_AUX_P 79

DP_85D DISPLAYPORT RDRV_DP_EXT_AUX_N 79

DP_85D DISPLAYPORT DP_EXT_AUX_P 79 80 81

DP_85D DISPLAYPORT DP_EXT_AUX_N 79 80 81

C C

UNUSED VIDEO NET PHYSICAL CONSTRAINTS

DP_85D DISPLAYPORT MXM_DP_B_AUX_P 74 77

DP_85D DISPLAYPORT MXM_DP_B_AUX_N 74 77

MXM_DP_D_AUX_P
B
DP_85D
DP_85D
DISPLAYPORT
DISPLAYPORT MXM_DP_D_AUX_N
74 77

74 77 B
DP_85D DISPLAYPORT MXM_LVDS_A_CLK_P 75 77

DP_85D DISPLAYPORT MXM_LVDS_A_CLK_N 75 77

DP_85D DISPLAYPORT MXM_LVDS_B_CLK_P 75 77

DP_85D DISPLAYPORT MXM_LVDS_B_CLK_N 75 77

DP_85D DISPLAYPORT MXM_DP_B_ML_P<3..0> 74 77

DP_85D DISPLAYPORT MXM_DP_B_ML_N<3..0> 74 77

DP_85D DISPLAYPORT MXM_DP_D_ML_P<3..0> 74 77

DP_85D DISPLAYPORT MXM_DP_D_ML_N<3..0> 74 77

DP_85D DISPLAYPORT MXM_LVDS_A_DATA_P<3..0> 75 77

DP_85D DISPLAYPORT MXM_LVDS_A_DATA_N<3..0> 75 77

DP_85D DISPLAYPORT MXM_LVDS_B_DATA_P<3..0> 75 77

DP_85D DISPLAYPORT MXM_LVDS_B_DATA_N<3..0> 75 77

A SYNC_MASTER=DAVE SYNC_DATE=01/07/2010 A
PAGE TITLE

GRAPHICS CONSTRAINTS
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

www.vinafix.vn
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 87 OF 92
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC SMBus Net Properties SMC VOLTAGE/CURRENT NET PROPERTIES
NET_TYPE NET_TYPE

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

SMB_55S SMB SMBUS_SMC_A_S3_SCL 49 THERM_DIFF THERMAL SENSE_MXM_P 50

SMB_55S SMB SMBUS_SMC_A_S3_SDA 49 THERM_DIFF THERMAL SENSE_MXM_N 50

SMB_55S SMB SMBUS_SMC_B_S0_SCL 49 THERM_DIFF THERMAL SENSE_VTT_R_P

SMBUS_SMC_B_S0_SDA SENSE_VTT_R_N
SMBus Interface Constraints SMB_55S

SMB_55S
SMB

SMB SMBUS_SMC_0_S0_SCL
49

49
THERM_DIFF

THERM_DIFF
THERMAL

THERMAL SENSE_CPU_1V5_P 50
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SMB_55S SMB SMBUS_SMC_0_S0_SDA 49 THERM_DIFF THERMAL SENSE_CPU_1V5_N 50
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

SMB_55S SMB SMBUS_SMC_BSA_SCL 49 THERM_DIFF THERMAL SENSE_CPU_VTT_P

SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
SMBUS_SMC_BSA_SDA SENSE_CPU_VTT_N

D TABLE_SPACING_RULE_HEAD
SMB_55S

SMB_55S
SMB

SMB SMBUS_SMC_MGMT_SCL
49

49 88
THERM_DIFF THERMAL
D
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SMB_55S SMB SMBUS_SMC_MGMT_SDA 49 88
TABLE_SPACING_RULE_ITEM

SMB_55S SMB SMBUS_SMC_MGMT_SCL 49 88

SMB * =2x_DIELECTRIC ?
SMB_55S SMB SMBUS_SMC_MGMT_SDA 49 88

SMB_55S SMB SMBUS_PCH_CLK 17 49

SMB_55S SMB SMBUS_PCH_DATA 17 49

SMB_55S SMB SML_PCH_0_CLK 17 49

SMB_55S SMB SML_PCH_0_DATA 17 49

SMB_55S SMB SML_PCH_1_CLK 17 49

SMB_55S SMB SML_PCH_1_DATA 17 49

CLK_XTAL XTAL SMC_EXTAL 46 47
CLK_XTAL XTAL SMC_XTAL 46 47

THERMAL GND_SMC_AVSS 46 47 50

THERMAL SMC_CPU_1V5_ISENSE 46 50

THERMAL SMC_CPU_1V5_ISENSE_R 50
TABLE_SPACING_ASSIGNMENT_HEAD

THERMAL SMC_CPU_1V5_VSENSE 46 50
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

THERMAL * * 4:1_SPACING
TABLE_SPACING_ASSIGNMENT_ITEM

THERMAL POWER * PWR_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

THERMAL GND * GND_P2MM

THERMAL SMC_CPU_VSENSE 46 50
TABLE_PHYSICAL_ASSIGNMENT_HEAD

VID_PHY VR_CTL VR_CPU_IOUT 12 65

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_ITEM
SMC THERMAL NET PROPERTIES THERM_DIFF THERMAL VR_ISNS_CPU_P 50

THERM_DIFF * 1:1_DIFFPAIR NET_TYPE THERM_DIFF THERMAL VR_ISNS_CPU_N 50

C SNS_DIFF *
TABLE_PHYSICAL_ASSIGNMENT_ITEM

1:1_DIFFPAIR
ELECTRICAL_CONSTRAINT_SET PHYSICAL

THERM_DIFF
SPACING

THERMAL SNS_T1_DP1 52
THERMAL

THERMAL
SNS_PS_CPU_ISNS
SMC_CPU_ISENSE
50

46 50
C
THERM_DIFF THERMAL SNS_T1_DN1 52

THERM_DIFF THERMAL SNS_T1_DP2_DN3 44 52

THERM_DIFF THERMAL SNS_T1_DN2_DP3 44 52

THERM_DIFF THERMAL SNS_T2_DP1 52

THERM_DIFF THERMAL SNS_T2_DN1 52

THERM_DIFF THERMAL SNS_T2_DP2 52

THERM_DIFF THERMAL SNS_T2_DN2 52

THERM_DIFF THERMAL SNS_T2_DP3 52

THERM_DIFF THERMAL SNS_T2_DN3 52

THERM_DIFF THERMAL SNS_ODD_P 52 92

THERM_DIFF THERMAL SNS_ODD_N 52 92

THERM_DIFF THERMAL SNS_CPU_H_P 52

THERM_DIFF THERMAL SNS_CPU_H_N 52

THERM_DIFF THERMAL SNS_SKIN_P 52 92

THERM_DIFF THERMAL SNS_SKIN_N 52 92

THERM_DIFF THERMAL SNS_AMB_P 52 54 92

THERM_DIFF THERMAL SNS_AMB_N 52 54 92

THERM_DIFF THERMAL SNS_MXM_P 52

THERM_DIFF THERMAL SNS_MXM_N 52

B B

THERMAL HDD_OOB_TEMP_FILT 51 92

THERMAL HDD_OOB_TEMP 51

THERMAL HDD_OOB_TEMP_R 51

THERMAL SMC_HDD_OOB_TEMP 46 51

A SYNC_MASTER=TEMP SYNC_DATE=12/09/2009 A
PAGE TITLE

SMC Constraints
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

SWITCHNODE SWITCHNODE BGA_P1MM BGA_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

SWITCHNODE POWER BGA_P1MM BGA_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

SWITCHNODE GND BGA_P1MM BGA_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

SWITCHNODE * BGA_P1MM BGA_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

SWITCHNODE POWER * 6:1_SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

VR CTRL NET PROPERTIES VR CTRL NET PROPERTIES

SWITCHNODE GND * 6:1_SPACING
TABLE_SPACING_ASSIGNMENT_ITEM POWER NET PROPERTIES SENSING NET PROPERTIES NET_TYPE NET_TYPE
SWITCHNODE * * SWITCHNODE
D PHYSICAL SPACING
NET_TYPE

VOLTAGE
NET_TYPE

SPACING
PHYSICAL SPACING PHYSICAL SPACING D
PHYSICAL
VR_CTL_PHY VR_CTL DDR_REG_CS
VR_CTL_PHY VR_CTL VR_CPU_PH1_SNUB 66 I437 71

POWER NET PROPERTIES POWER POWER 3.3V PP3V3_S0 I278 VR_CTL_PHY VR_CTL DDR_REG_FB
I216
POWER POWER 3.3V
5
I155
SNS_DIFF THERMAL VR_CPU_ISNS1_P 65 66 I338
VR_CTL_PHY VR_CTL VR_CPU_PH2_SNUB 66 I595
VR_CTL_PHY SWITCHNODE
71

I218
PP3V3_S0_CK505_F 25 VR_CTL_PHY VR_CTL VR_CPU_PH3_SNUB I439
DDR_REG_LGATE 71
I156
SNS_DIFF THERMAL VR_CPU_ISNS1_N 65 66 I339 66
VR_CTL_PHY SWITCHNODE DDR_REG_UGATE
I596 71
NET_TYPE POWER POWER 3.3V PP3V3_S0_DPFUSE SNS_DIFF THERMAL VR_CPU_ISNS1_R_P VR_CTL_PHY VR_CTL DDR_REG_BOOT
I219
3.3V
81 I157 65
I341
VR_CTL_PHY VR_CTL VR_CPU_PWM1 65 66 I443 71
PHYSICAL SPACING VOLTAGE I222
POWER POWER PP3V3_S0_DPPWR 81 SNS_DIFF THERMAL VR_CPU_ISNS1_R_N 65
VR_CTL_PHY VR_CTL VR_CPU_PWM2 65 66 I442
VR_CTL_PHY VR_CTL DDR_REG_BOOT_R 71
POWER POWER 3.3V I158 I342 VR_CTL_PHY VR_CTL
I221
PP3V3_S0_HS_F 62 VR_CTL_PHY VR_CTL VR_CPU_PWM2_R I441
DDR_REG_VDDQSNS 71
POWER SWITCHNODE 1.5V VR_CPU_PHASE1 SNS_DIFF THERMAL VR_CPU_ISNS2_P I343 65
I128 66 I160 65 66
VR_CTL_PHY VR_CTL VR_CPU_PWM3 I444
VR_CTL_PHY VR_CTL DDR_REG_VTTSNS 71
POWER SWITCHNODE 1.5V VR_CPU_PHASE2 SNS_DIFF THERMAL I344 65 66
I129
1.5V
66
I159 VR_CPU_ISNS2_N 65 66 VR_CTL_PHY VR_CTL VR_CPU_PWM3_R
I130
POWER SWITCHNODE VR_CPU_PHASE3 66 I345 65

I161
SNS_DIFF THERMAL VR_CPU_ISNS2_R_P 65
POWER SWITCHNODE 3.3V P3V3S5_REG_PHASE 70
SNS_DIFF THERMAL VR_CPU_ISNS2_R_N 65
I132 I163
POWER SWITCHNODE 5V P5VS3_REG_PHASE 3.3V VR_CTL_PHY VR_CTL VR_CPU_PWM4_R I449
VR_CTL_PHY VR_CTL P1V8_REG_POR 71
I133 70
I223
POWER POWER PP3V3_S0_PCH_VCCA_DAC 16 21 I162
SNS_DIFF THERMAL VR_CPU_ISNS3_P 65 66 I347 65
POWER SWITCHNODE 1.1V VTT_REG_PHASE VR_CTL_PHY VR_CTL VR_CPU_REF 65
I134 I348
3.3V I164
SNS_DIFF THERMAL VR_CPU_ISNS3_N 65 66 VR_CTL_PHY VR_CTL VR_CPU_SS
I226
POWER POWER PP3V3_S0_TSENS_R I349 65
VR_CTL_PHY VR_CTL P3V3S5_REG_BOOT
POWER SWITCHNODE 3.4V P3V42G3H_SW 3.3V SNS_DIFF THERMAL VR_CPU_ISNS3_R_P VR_CTL_PHY VR_CTL VR_CPU_TCOMP I450 70
I136
1.05V
72
I224
POWER POWER PP3V3_S3 5 92 I165 65 I350 65
VR_CTL_PHY VR_CTL P3V3S5_REG_BOOT_R
I137
POWER SWITCHNODE PCHCORE_REG_PHASE 69 SNS_DIFF THERMAL VR_CPU_ISNS3_R_N I353
VR_CTL_PHY VR_CTL VR_CPU_TM 65 I452
VR_CTL_PHY VR_CTL
70
I166 65
VR_CTL_PHY VR_CTL VR_CPU_BOOT1_RC 66 I451
P3V3S5_REG_FB 70
I352 VR_CTL_PHY VR_CTL P3V3S5_REG_ISEN
I351
VR_CTL_PHY VR_CTL VR_CPU_BOOT2_RC 66 I453 70
POWER SWITCHNODE 1.5V DDR_REG_PHASE POWER POWER 3.3V PP3V3_S3_BT_FLT VR_CTL_PHY VR_CTL VR_CTL_PHY SWITCHNODE P3V3S5_REG_LGATE 70
I139
1.8V
71 I557 44
I354
VR_CPU_BOOT3_RC 66 I455
I140
POWER SWITCHNODE P1V8_REG_PHASE 71 POWER POWER 3.3V PP3V3_S3_SDCARD_FLT VR_CTL_PHY VR_CTL VR_CPU_COMP I454
VR_CTL_PHY VR_CTL P3V3S5_REG_OCSET 70
I230 44 I356 65
VR_CTL_PHY VR_CTL VR_CPU_COMP_R 65
I355
POWER POWER 1.5V PP0V75_S3_MEM_VREFCA_A 28 30
I141 VR_CTL_PHY SWITCHNODE P3V3S5_REG_UGATE
POWER POWER 1.5V PP0V75_S3_MEM_VREFCA_B 28 31
VR_CTL_PHY VR_CTL VR_CPU_COMP_RC 65 I458
70
I142 3.3V I357
POWER POWER 1.5V PP0V75_S3_MEM_VREFDQ_A I235
POWER POWER PP3V3_S5 5 VR_CTL_PHY VR_CTL VR_CPU_DAC I457
VR_CTL_PHY VR_CTL P3V3S5_REG_SNUB 70
I143 28 30 I358 65
POWER POWER 1.5V PP0V75_S3_MEM_VREFDQ_B VR_CTL_PHY VR_CTL VR_CPU_DRV1_BOOT I459
VR_CTL_PHY VR_CTL P5VS3_REG_BOOT 70
I144 28 31 I359 66
VR_CTL_PHY VR_CTL VR_CPU_DRV1_GDSEL I461
VR_CTL_PHY VR_CTL P5VS3_REG_FB 70
I360 66

I363
VR_CTL_PHY SWITCHNODE VR_CPU_DRV1_LGATE 66
POWER POWER 12V PP12V_AUD_SPKRAMP_PLANE VR_CTL_PHY VR_CTL P5VS3_REG_ISEN 70
I145 I462
VR_CTL_PHY SWITCHNODE VR_CPU_DRV1_UGATE I463
VR_CTL_PHY SWITCHNODE P5VS3_REG_LGATE 70
I361 66
VR_CTL_PHY VR_CTL P5VS3_REG_OCSET
I464 70
POWER POWER 12V PP12V_S0 5 64
I148
POWER POWER 12V PP12V_S0_CPU_FLTRD VR_CTL_PHY SWITCHNODE P5VS3_REG_UGATE
I149
12V
65 66
I365
VR_CTL_PHY VR_CTL VR_CPU_DRV2_BOOT 66 I466 70
POWER POWER PP12V_S0_FAN0_L
C I175
I174
I173
POWER
POWER
POWER
POWER
12V
12V
PP12V_S0_FAN1_L
PP12V_S0_FAN2_L
53 92
53 92
54 92
3.3V
I367
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
SWITCHNODE
VR_CPU_DRV2_GDSEL
VR_CPU_DRV2_LGATE
66 C
I273
POWER POWER PPVTT_S3_DDR_BUF 71 I368 66

12V POWER POWER 3.3V PPV_S0_MXM_PWRSRC

I604
POWER POWER PP12V_G3H 5 72 I274 50
VR_CTL_PHY SWITCHNODE VR_CPU_DRV2_UGATE
I58
SNS_DIFF VR_CPU_VSEN 65 I370 66

I178
POWER POWER 12V PP12V_S5 5
I263
I265
POWER
POWER
POWER
POWER
3.3V
3.3V
PPVOUT_S0_PCH_DCPSST
PPVOUT_S5_PCH_DCPSUS
21
21
I59

I151
SNS_DIFF

SNS_DIFF
VR_CPU_RGND
VR_CPU_VSNS_R_N
65

65 I371
VR_CTL_PHY VR_CTL VR_CPU_DRV3_BOOT 66
VR VID NET PROPERTIES
POWER POWER 3.3V PPVOUT_S5_PCH_DCPSUSBYP 21 VR_CTL_PHY VR_CTL VR_CPU_DRV3_GDSEL
I266
POWER POWER 3.3V I152
SNS_DIFF VR_CPU_VSNS_R_P 65 I374
VR_CTL_PHY SWITCHNODE
66
NET_TYPE
I262
PPVOUT_G3_PCH_DCPRTC 21 I376
VR_CPU_DRV3_LGATE 66
POWER POWER 3.3V PPVOUT_SO_PCH_VCCRTC_NCTF I153
SNS_DIFF VR_CPU_VSNS_XW_P 65 PULL-UP STUB < 1-INCH
I610 SPACING VID LENGTH SKEW < 1-INCH
POWER POWER 12V FW_PORT0_VP 41
SNS_DIFF VR_CPU_VSNS_XW_N 65
PHYSICAL VID LENGTH RANGE< 1 TO 15-INCH
I267 I154
POWER POWER 12V FW_PORT0_VP_F VR_CTL_PHY SWITCHNODE VR_CPU_DRV3_UGATE
I270
POWER POWER 12V
41
POWER POWER 3.3V PPVBATT_G3_RTC SNS_DIFF
I377 66
I491
VID_PHY VR_CTL CPU_VID<0> 12 15 65
I544
PPVP_FW_PHY_CPS 40 41 I257 27
I578
CPU_VCC_PKG_SENSE_P 12 50 65 VID_PHY VR_CTL CPU_VID<1>
POWER POWER 3.3V PPVBATT_G3_RTC_R 27 I492 12 15 65
I260 SNS_DIFF CPU_VCC_PKG_SENSE_N VID_PHY VR_CTL CPU_VID<2>
I579 12 65 I521 12 15 65
POWER POWER 3.3V PP3V3_AUDIO_SPDIF_JACK I522
VID_PHY VR_CTL CPU_VID<3> 12 15 65
I207 60 92
POWER POWER 3.3V PP3V3_FW_AVDD SNS_DIFF VTT_REG_ISNS_P I523
VID_PHY VR_CTL CPU_VID<4> 12 15 65
I209 39 I615
POWER POWER 3.3V PP3V3_FW_ESD I524
VID_PHY VR_CTL CPU_VID<5> 12 15 65
I212 41
I616
SNS_DIFF VTT_REG_ISNS_N VID_PHY VR_CTL CPU_VID<6>
POWER POWER 3.3V PP3V3_FW_PLLVDD 39 I525 12 15 65
POWER POWER 1.1V I211 SNS_DIFF VID_PHY VR_CTL CPU_VID<7>
I259
PPVCORE_S0_CPU 5 POWER POWER 3.3V PP3V3_FW_VDDA I56
CPU_VTTSENSE_P 12 68 I526 12 15 65
I210 39
POWER POWER 1.1V PPVCORE_S0_CPU_REG1 VID_PHY VR_CTL CPU_PSI_L
I258
POWER POWER 1.1V
66
I57
SNS_DIFF CPU_VTTSENSE_N 12 68 I387
VR_CTL_PHY VR_CTL VR_CPU_FAN 65 I554 12 65

I563
PPVCORE_S0_CPU_REG2 66 POWER POWER 3.3V PP3V3_G3_RTC VR_CTL_PHY VR_CTL VR_CPU_FB
POWER POWER 1.1V PPVCORE_S0_CPU_REG3 I215
3.3V
17 21 23 27
I172
SNS_DIFF CPU_VTTSENSE_R_P I388 65
I564 66
I214
POWER POWER PP_ENET_CTRL12 36 I389
VR_CTL_PHY VR_CTL VR_CPU_FB_R 65
I171
SNS_DIFF CPU_VTTSENSE_R_N VR_CTL_PHY VR_CTL VR_CPU_FS
I390 65

I419 SNS_DIFF VTT_REG_VSEN I393

VR_CTL_PHY VR_CTL VR_CPU_IMON 50 65
SNS_DIFF VTT_REG_RGND
I413
I391
VR_CTL_PHY VR_CTL VR_CPU_IOUT_PD 65
POWER POWER 1.05V PP1V05_S0 VR_CTL_PHY SWITCHNODE
I177
1.05V
5
VTT_REG_RTO1 I394
PCHCORE_REG_UGATE 69
I179
POWER POWER PP1V05_S0_CK505_F 25 I617 SNS_DIFF
VR_CTL_PHY SWITCHNODE PCHCORE_REG_LGATE
POWER POWER 1.05V PP1V05_S0_PCH_VCCADPLLA I618
SNS_DIFF VTT_REG_RTR1 I396
VR_CTL_PHY VR_CTL
69
I182 16 21
I395
PCHCORE_REG_VFB 69

1.05V POWER POWER 3.4V PP3V3_G3H_SMC_AVCC

I180
POWER POWER PP1V05_S0_PCH_VCCADPLLB 16 21 I236 46
VR_CTL_PHY VR_CTL PCHCORE_REG_TON 69
I397
1.05V POWER POWER 3.3V PP3V3_G3H_AVREF_SMC I398
VR_CTL_PHY VR_CTL PCHCORE_REG_TRIP 69
I185
POWER POWER PP1V05_S0_PCH_VCCADPLLB_F I231 46 47
VR_CTL_PHY VR_CTL PCHCORE_REG_BOOT 69
POWER POWER 1.05V PP1V05_S0_PCH_VCCAPLL_EXP I399
21 23 VR_CTL_PHY VR_CTL PCHCORE_REG_BOOT_R 69
B
I184

B POWER POWER 1.05V PP1V05_S0_PCH_VCCAPLL_FDI I594 TABLE_PHYSICAL_ASSIGNMENT_HEAD

I183 21 23 POWER POWER 3.42V PP3V42_G3H 5 NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

POWER POWER 1.05V PP1V05_S0_PCH_VCCAPLL_SATA I606
I186 21 23
POWER POWER 1.05V PP1V05_S0_PCH_VCCA_CLK 21 23
TABLE_PHYSICAL_ASSIGNMENT_ITEM

I188 VR_CTL_PHY VR_CTL VTT_REG_BOOT VID_PHY * 39_OHM_SE

I403
POWER POWER 4.5V 4V5_REG_IN 56
VR_CTL_PHY VR_CTL VTT_REG_COMP 89
I577 I402
POWER POWER 4.5V PP4V5_AUDIO_ANALOG 56
VR_CTL_PHY VR_CTL VTT_REG_FB
I234 I401
I404
VR_CTL_PHY VR_CTL VTT_REG_FS
POWER POWER 1.05V PP1V05_SM_PCH_LAN POWER POWER 5V I406
VR_CTL_PHY VR_CTL VTT_REG_COMP 89
TABLE_SPACING_RULE_HEAD

I614 5
I237
PP5V_S0 5 92 VR_CTL_PHY VR_CTL VTT_REG_REF 89
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
POWER POWER 5V PP5V_S0_CPU_VCORE_VCC I405
I239 65 TABLE_SPACING_RULE_ITEM

POWER POWER 5V PP5V_S0_PCH_V5REF 21 23 VR_CTL * 0.2MM ?

I238
POWER POWER 1.1V PPVTT_S0 5 50 I408
VR_CTL_PHY SWITCHNODE VTT_REG_LGATE
I269
POWER POWER 5V PP5V_S3
I245
POWER POWER 5V
5 92
I410
VR_CTL_PHY VR_CTL VTT_REG_OCSET
I242
PP5V_S3_DDR_REG_V5FILT 71 VR_CTL_PHY VR_CTL VTT_OFS
POWER POWER 5V PP5V_S3_CAMERA_FLT I411
POWER POWER 0.75V PPVTT_S0_DDR 5 I536 44 VR_CTL_PHY VR_CTL VTT_REG_REF 89
I268 POWER POWER 5V I412
0.75V I243
PP5V_S3_IR_FLT 44 92
I613
POWER POWER PP0V75_S0 5

VR_CTL_PHY VR_CTL VTT_REG_UGATE

I415
POWER POWER 5V PP5V_S5 5
POWER POWER 1.5V PP1V5_S0 I246 VR_CTL_PHY VR_CTL VTT_REG_PH1_SNUB
I194 5 POWER POWER 5V PP5V_S5_PCH_V5REFSUS 21 23 I418
POWER POWER 1.5V PP1V5_S0_CK505_F I244
I193 25
POWER POWER 1.5V PP1V5_S0_CK505_R 25
I587

POWER POWER 1.5V PP1V5_S3

I198 5
POWER POWER 1.5V PP1V5_CPU_MEM 5 50
POWER POWER 5V PP5V_USB2_PORT0 43
I575 I247
POWER POWER 5V PP5V_USB2_PORT0_F
I250 43
POWER POWER 5V PP5V_USB2_PORT1 43
VR_CTL_PHY VR_CTL P3V42G3H_BOOST 72
I249 I607
POWER POWER 5V PP5V_USB2_PORT1_F VR_CTL_PHY VR_CTL P3V42G3H_FB
I248 43 I608 72
POWER POWER 5V PP5V_USB2_PORT2 43
I251
POWER POWER 5V PP5V_USB2_PORT2_F
I252 43
1.5V POWER POWER 5V PP5V_USB2_PORT3
I205
POWER POWER PP1V8R1V5_S0_PCH_VCCVRM 21 23 I253
POWER POWER 5V
43
POWER POWER 1.5V PP1V5_FW_VDDA 39 I255
PP5V_USB2_PORT3_F 43
I195

A I203
POWER POWER 1.5V PP1V8_S0 5
POWER POWER DDR_REG_PGND
71
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
I545 PAGE TITLE
DDR_REG_CSGND
I206
POWER POWER 1.96V
1.96V
PP1V96_FW_PLLVDD 39
I546
POWER POWER
71
POWER CONSTRAINTS
I208
POWER POWER PP1V95_FW_FWPHY 39 40 DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

D D

C C

B B

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

BLANK PAGE
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

PM NET PROPERTIES NET_TYPE

(PM, RESET, EN, PGOOD) PHYSICAL SPACING

PHYSICAL
NET_TYPE

SPACING
PM PLT_RESET_L
I2 19 27
TABLE_SPACING_ASSIGNMENT_HEAD

I82
PM 4V5_REG_EN 56
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I1
PM_VTT PLT_RESET_LS1V1_L 10
PM
I81 ALL_SYS_PWRGD_R 5 64
TABLE_SPACING_ASSIGNMENT_ITEM

I4
PM PM_ACDC_PS_ON 5
PM * * 2:1_SPACING I84
PM ALL_SYS_PWRGD_SMC 46 64
PM PM_BATLOW_L 14 18 46
TABLE_SPACING_ASSIGNMENT_ITEM
I3 PM CK505_27MHZ_EN
I83 25
PM_VTT PM_VTT * 2:1_SPACING I5
PM PM_CLK32K_SUSCLK 8 46 85
PM
I85
CPUVTT_REG_EN 63 68
TABLE_SPACING_ASSIGNMENT_ITEM

I7
PM PM_CLK32K_SUSCLK_R 8 18 85
PM_VTT CPUVTT_REG_PGOOD

D
PM_VTT

PM_VTT
*

GND
*

*
3:1_SPACING

DEFAULT
TABLE_SPACING_ASSIGNMENT_ITEM
I6
PM PM_CLKRUN_L 14 18 46 48
I86

I87
PM CPU_MEM_RESET_L
10 63 64 68

10 26 D
PM I88
PM DDRVTT_EN 63 71
TABLE_SPACING_ASSIGNMENT_ITEM

I10
PM_EXT_TS_L<0>
PM GND * DEFAULT I89
PM DEBUG_RESET_L 27 48
I9
PM PM_EXT_TS_L<1> PM
I90 FWPHY_RESET_L 39
I12
PM PM_LAN_PWRGD 14 18
I91
PM FWXIO_SNOOP_EN 39

I117
PM_VTT FSB_CPURSTOUT_L 10 24 I92
PM FW_RESET_L 27 39

I95
PM ENET_RESET_L 27 37
PM MEM_RESET_L
I97 26 30 31

I96
PM MINI_RESET_L 27 33

PM_VTT PM_MEM_PWRGD I98

PM SMC_DELAYED_PWRGD 47 64
I25 10 18
PM PM_ME_PWRGD I100
PM SMC_LRESET_L 27 46
I24 18 64

I99
PM SMC_RESET_L 46 47 48

I101
PM_VTT XDP_CPUPWRGD 10 24

PM PM_MXM_PGOOD I103
PM_VTT XDP_DBRESET_L 10 24 27
I30 64 75
PM PM_VTT XDP_PWRGD
I29 PM_PCH_PWRGD 18 64 I104 24

I31
PM PM_PGOOD_DDRREG_S3 63 71

I33
PM PM_PGOOD_PVCORE_CPU 25 64 65
PM PM_PWRBTN_L
I32 18 24 46

I35
PM PM_RSMRST_L 46 63

I34
PM PM_RSMRST_PCH_L 18 63
PM PM_SLP_M_L
I36 18 63

I37
PM PM_SLP_S3_L 5 18 26 36 46 47 63 64 81

C PM PM_SLP_S4_1_L 18 63
C
I120

I39
PM PM_SLP_S4_L 18 47

I41
PM PM_SLP_S5_L 18 47

I43
PM PM_SUS_PWR_ACK 18
PM_VTT PM_SYNC
I42 10 18

I122
PM SDCARD_PLT_RST_L 27 44

I45
PM PM_SYSRST_L 18 27 46
PM PM_SYS_PWRGD
I44 18 64

I46
PM_VTT PM_THRMTRIP_L 10 20 47

I48
PM RSMRST_PWRGD 46 64
PM RTC_RESET_L
I47 17 91

I50
PM_VTT CPU_PWRGD 10 20 24

I49
PM CPU_RESET_L 10 27

PM PGOOD_1V8_S0_G1
I52 64

I54
PM PGOOD_1V8_S0_G2 64

I56
PM PGOOD_CPU_GFX_DDR 64

I57
PM PGOOD_P1V5_S0 10 73
PM PGOOD_P1V8_S0 64
I59

B I60
PM PGOOD_P3V3_S0 64 73
B
I63
PM PGOOD_P3V3_S3 34 73

I62
PM PGOOD_P5V_S0 63 73
PM PGOOD_PCH_AND_P1V8
I64 64

I66
PM PGOOD_PCH_S0 64

I65
PM PGOOD_SYSPWROK 64
PM PGOOD_SYSPWROK_R
I67 64

I68
PM RTC_RESET_L 17 91

I69
PM P12V_S3_EN

I70
PM P1V5_S0_EN 63 73

I74
PM P3V3S0_EN 63 73

I73
PM P3V3S3_EN 63 73
PM P5VS0_EN
I76 63 73

I75
PM P5VS3_EN 63 70

I77
PM PCHCORE_REG_EN 63 69
PM PCHCORE_REG_PGOOD
I79 63 64 69

I78
PM PEG_RESET_L 8 27

I80
PM SDCARD_RESET 20 44 92

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

PM RESETS ENABLES PGOOD CONST

DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

FUNCTIONAL TESTPOINTS FOR MAC-1 & ICT

J4700 USB CAMERA

J5551 ODD TEMP SENSOR

89 5 IN PP5V_S3 FUNC_TEST=TRUE 88 52 IN SNS_ODD_P FUNC_TEST=TRUE J6601 AUDIO MICROPHONE

MIN_ALLOWED_TPS=1
88 52 IN SNS_ODD_N FUNC_TEST=TRUE GND 17 TP’S FUNC_TEST=TRUE
85 44 IN USB_CAMERA_L_P FUNC_TEST=TRUE 60 IN AUD_MIC_IN1_N_CONN FUNC_TEST=TRUE MIN_ALLOWED_TPS=17
USB_CAMERA_L_N GND_AUDIO_MIC1_CONN

D
85 44 IN FUNC_TEST=TRUE

J5600 ODD FAN

60
IN
IN AUD_MIC_IN1_P_CONN
FUNC_TEST=TRUE
FUNC_TEST=TRUE
89 5 IN PP3V3_S3 2 TP’S FUNC_TEST=TRUE
D
85 44 IN USB_BT_L_P FUNC_TEST=TRUE 1 Ground Testpoint near J6601 MIN_ALLOWED_TPS=2
53 IN FAN_0_PWR_L FUNC_TEST=TRUE
85 44 IN USB_BT_L_N FUNC_TEST=TRUE
53 IN FAN_TACH0_L FUNC_TEST=TRUE
70 5 IN PP5V_S3_REG 1 TP’S FUNC_TEST=TRUE
89 53 IN PP12V_S0_FAN0_L FUNC_TEST=TRUE J6602 AUDIO RIGHT SPEAKER MIN_ALLOWED_TPS=1
49 44 IN =SMB_ALS_SCL FUNC_TEST=TRUE
53 IN FAN_0_GND FUNC_TEST=TRUE
85 60 58 IN AUD_SPKR_OUTLO2R_POUTFUNC_TEST=TRUE
49 44 IN =SMB_ALS_SDA FUNC_TEST=TRUE
85 60 58 IN AUD_SPKR_OUTLO2R_NOUTFUNC_TEST=TRUE 89 5 IN PP5V_S0 FUNC_TEST=TRUE
MIN_ALLOWED_TPS=1
85 60 58 IN AUD_SPKR_OUTLO1R_POUTFUNC_TEST=TRUE
1 PP5V_S3_REG Testpoint near J4700
85 60 58 IN AUD_SPKR_OUTLO1R_NOUTFUNC_TEST=TRUE
1 PP3V3_S3 TESTPOINT NEAR J4700
J5700 CPU FAN
6 GROUND TESTPOINTS NEAR J4700
54 IN FAN_2_PWR_L FUNC_TEST=TRUE
J6603 AUDIO LEFT SPEAKER
54 IN FAN_TACH2_L FUNC_TEST=TRUE
J4750 USB CARD READER 89 54 IN PP12V_S0_FAN2_L FUNC_TEST=TRUE 85 60 59 IN AUD_SPKR_OUTLO2L_POUTFUNC_TEST=TRUE
54 IN FAN_2_GND FUNC_TEST=TRUE 85 60 59 IN AUD_SPKR_OUTLO2L_NOUTFUNC_TEST=TRUE
85 44 IN USB_SDCARD_L_P FUNC_TEST=TRUE
85 60 59 IN AUD_SPKR_OUTLO1L_POUTFUNC_TEST=TRUE
85 44 IN USB_SDCARD_L_N FUNC_TEST=TRUE 88 54 52 IN SNS_AMB_P FUNC_TEST=TRUE
85 60 59 IN AUD_SPKR_OUTLO1L_NOUTFUNC_TEST=TRUE
91 44 20 IN SDCARD_RESET FUNC_TEST=TRUE 88 54 52 IN SNS_AMB_N FUNC_TEST=TRUE

1 PP3V3_S3 Testpoint near J4750 1 GROUND TESTPOINT NEAR J5700

2 Ground Testpoints near J4750
J6600 AUDIO AUXILIARY CONNECTOR
2 TP’S
89 60 IN PP3V3_AUDIO_SPDIF_JACK
FUNC_TEST=TRUE
J5601 HD FAN MIN_ALLOWED_TPS=2
J4780 IR BOARD
53 IN FAN_1_PWR_L FUNC_TEST=TRUE
85 44 IN USB_IR_L_P FUNC_TEST=TRUE 60 IN AUD_LI_DET_JACK FUNC_TEST=TRUE
53 IN FAN_TACH1_L FUNC_TEST=TRUE
85 44 IN USB_IR_L_N FUNC_TEST=TRUE
89 53 IN PP12V_S0_FAN1_L FUNC_TEST=TRUE
60 AUD_LI_R_JACK FUNC_TEST=TRUE
C
IN
C 89 44 IN PP5V_S3_IR_FLT FUNC_TEST=TRUE

1 GROUND TESTPOINT NEAR J4780

53 IN FAN_1_GND FUNC_TEST=TRUE
60

60
IN AUD_LI_GND_JACK
AUD_LI_L_JACK
FUNC_TEST=TRUE
FUNC_TEST=TRUE
IN
J5400 HDD TEMP SENSOR
60 IN HS_MIC_LO_JACK FUNC_TEST=TRUE
88 51 IN HDD_OOB_TEMP_FILT FUNC_TEST=TRUE
60 IN HS_MIC_HI_JACK FUNC_TEST=TRUE
1 GROUND TESTPOINTS NEAR J5400

60 IN AUD_HP_L_JACK FUNC_TEST=TRUE
J5560 SKIN TEMP SENSOR 60 AUD_HP_GND_JACK FUNC_TEST=TRUE
IN
88 52 SNS_SKIN_P FUNC_TEST=TRUE 60 IN AUD_HP_R_JACK FUNC_TEST=TRUE
IN
SNS_SKIN_N FUNC_TEST=TRUE 60 IN AUD_HP_TYPEDET_JACK FUNC_TEST=TRUE
88 52 IN
J4520 SATA ODD (HIGH SPEED) 60 IN AUD_IP_PERPH_JACK FUNC_TEST=TRUE
60 IN AUD_HP_TIPDET_JACK FUNC_TEST=TRUE

46 42 IN SMC_ODD_DETECT FUNC_TEST=TRUE
1 PP5V_S0 Testpoint near J4520
60 IN AUD_SPDIFIN_JACK FUNC_TEST=TRUE
1 GROUND TESTPOINTS NEAR J4520
60 IN AUD_SPDIF_OUT_JACK FUNC_TEST=TRUE

4 GROUND TESTPOINTS NEAR J6600

B B

A SYNC_MASTER=K74_MASTER SYNC_DATE=N/A A
PAGE TITLE

K74/K75 ICT/FCT
DRAWING NUMBER SIZE

Apple Inc. 051-8337 D

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
III NOT TO REVEAL

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

G
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D3
D4
S3
S2
GATE
S1
D2
II NOT TO REPRODUCE OR COPY IT
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PART NUMBER
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PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
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TABLE_BOMGROU

IN
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OUT
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IN
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WH

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