Unit 4

Semiconductor Memories
 Outline
 Memory Classification
 Memory Organization: RAM
 Memory Organization: ROM
 Row and Column Decoders
 Semiconductor Memory
 Capable of storing large quantities of digital information essential to all digital
systems.
 Ever-increasing demand for larger data storage capacity has driven the fabrication
technology and memory development
 More compact design rules and, consequently, toward higher data storage densities
 Maximum realizable data storage capacity of single-chip semiconductor memory
arrays approximately doubles every two years
 Semiconductor Memory Types
 Read-Only Memory (ROM)—only the retrieval of previously stored data and do not permit
modifications
 ROMs are non-volatile memories, i.e., the data storage function is not lost even when the
power supply voltage is off
 Depending on the type of data storage (data write) method, ROMs are classified as mask-
programmed ROMs, Programmable ROMs (PROM), Erasable PROMs (EPROM)
 Electrically Erasable PROMs
(EEPROM)

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
 Semiconductor Memory Types
 Read-write (R/W) memory circuits--must permit the modification (writing) of data bits stored
in the memory array, as well as their retrieval (reading) on demand.
 Requires that the data storage function be volatile, i.e., the stored data are lost when the
power supply voltage is turned off.
 Read-write memory circuit is commonly called Random Access Memory (RAM)
 RAMs are classified as:
Static RAMs (SRAM)
Dynamic RAMs (DRAM)

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
 Typical Memory Array Organization: RAM
 Data storage structure, or core, consists of individual memory cells arranged in an array
of horizontal rows and vertical columns
 Each cell is capable of storing
one bit of binary information
 Structure has 2N rows, also called word
lines, and 2M columns, also called bit lines
 Total number of memory cells in this
array is 2M x 2N

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
 Typical Memory Array Organization: RAM
 To access a particular memory cell corresponding
bit line and the corresponding word line must be
activated (selected)
 Row decoder circuit selects one out of 2N
word lines according to an N bit
row address
 Column decoder circuit selects one out
of 2M bit lines according to an M-bit
column address
Individual memory cells can be accessed for data
read and/or data write operations in random order,
independent of their physical locations in the
memory array. Thus, the array organization
examined here is called a Random Access Memory
(RAM) structure.

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
 Read-Only Memory (ROM) Circuits
 Simple combinational Boolean network which produces a specified output value for each
input combination, i.e., for each address
 As described in the previous section, only one word line is activated (selected) at a time by
raising its voltage to VDD, while all other rows are held at a low voltage level.
 If an active transistor exists at the cross point of a column and the selected row, the column
voltage is pulled down to the logic low level by that transistor. If no active transistor exists at
the cross point, the column voltage is pulled high by the pMOS load device. Thus, a logic " 1
"-bit is stored as the absence of an active transistor, while a logic ""-bit is stored as the
presence of an active transistor at the crosspoint. To reduce static power consumption, the
pMOS load transistors in the ROM array shown in Fig. can also be driven by a periodic
precharge signal, resulting in a dynamic ROM.
 Logic " 1 “ bit is stored as the absence of an active transistor logic “0“ bit is stored as the
presence of an active transistor at the crosspoint
 To reduce static power consumption
 pMOS load transistors can also be driven by a periodic precharge signal, resulting in a
dynamic ROM

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
 Design of Row and Column
Decoders

Now we will turn our attention to the circuit structures of row and column address
decoders, which select a particular memory location in the array, based on the binary
row and column addresses.
A row decoder designed to drive a NOR ROM array must, by definition, select one of the
2 word lines by raising its voltage to VOH. As an example, consider the simple row address
decoder shown in Fig. , which decodes a two-bit row address and selects one out of four
word lines by raising its level.
NOR-based row decoder circuit for 2 address bits and 4
word lines

• A most straightforward
implementation of this decoder is
another NOR array, consisting of 4
rows (outputs) and 4 columns (two
address bits and their
complements).
• Note that this NOR-based decoder
array can be built just like the NOR
ROM array, using the same
selective programming approach
as shown in figure

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
The ROM array and its row decoder can thus be
fabricated as two adjacent NOR arrays, as shown
in Fig.
 NAND-based row decoder circuit for 2 address
bits and 4 word lines
A row decoder designed to drive a NAND
ROM, on the other hand, must lower the
voltage level of the selected row to logic
"0" while keeping all other rows at a logic-
high level.
This function can be implemented by
using an N-input NAND gate for each of
the row outputs. The truth table of a
simple address decoder for four rows and
the double NAND-array implementation
of the decoder and the ROM are shown in
Fig.
As in the NOR ROM case, the row address
decoder of the NAND ROM array can thus
be realized using the same layout strategy
as the memory array itself.
 Column Decoder circuitry
• The column decoder circuitry is designed to select one out of 2M bit lines
(columns) of the ROM array according to an M-bit column address, and to
route the data content of the selected bit line to the data output.
• A straightforward but costly approach would be to connect an nMOS pass
transistor to each bit-line (column) output, and to selectively drive one out of
2M pass transistors by using a NOR-based column address decoder, as shown in
Fig.
• In this arrangement, only one nMOS pass transistor is turned on at a time,
depending on the column address bits applied to the decoder inputs. The
conducting pass transistor routes the selected column signal to the data
output. Similarly, a number of columns can be chosen at a time, and the
selected columns can be routed to a parallel data output port.
• Note that the number of transistors required for this column decoder
implementation is 2(M+ 1), i.e., 2m pass transistors for each bit line and M 2M
transistors for the decoder circuit. This number can quickly become excessive
for large M, i.e., for a large number of bit lines.
 Dynamic Read-Write Memory (DRAM) Circuits
 Binary data is stored simply as charge in a capacitor,
 Presence or absence of stored charge determines the value of the stored bit
 Data stored as charge in a capacitor cannot be retained indefinitely
 Because the leakage currents eventually remove or modify the stored charge
 Require a periodic refreshing of the stored data to avoid unwanted modifications
 Evolution of DRAM Cell
The four-transistor DRAM cell
 Simplest and one of the earliest Dynamic memory
cells
 Derived from the six-transistor static RAM cell by
Removing the load devices
 In write operation, a word line is enabled and
complementary data are written from a pair of bit lines.
 Charge is stored in the parasitic and gate capacitances
of the node connected with a high voltage bit line.
 Since no current path is provided to the storage nodes
for restoring the charge being lost to leakage, the
cell must be refreshed periodically
In read operation, the voltage of a bit line is discharged to
the ground through the transistor where the gate node is
driven with a high voltage
 Has only a marginal area advantage over the six-
transistor SRAM cell

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
 Evolution of DRAM Cell
The three-transistor DRAM cell
 Utilizes a single transistor (M3) as the storage device (where the transistor is turned on or off
depending on the charge stored in its gate capacitance)
 One transistor each for the "read“ and "write" access switches. During the write operation, the
write word line is enabled and the voltage of the write bit line is passed onto the gate of the
storage device through the M1 transistor
 During the read operation the voltage of the read bit line is discharged to ground through M2
and M3 when the gate storage voltage is high
 Cell has two control and two I/O lines
 Separate read and write select lines
make it relatively fast
 But the four lines with their additional M2
contacts tend to increase the cell area
M3
M1

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
 Evolution of DRAM Cell
The one-transistor DRAM cell
 Has become the industry standard because of only one transistor and one capacitor, it has the
lowest component count
 The read and write operation are almost same. For write operation, after the word line is
enabled, data are written into the cell through the transistor and stored at the storage
capacitor. During the read operation the charge stored in the storage cell is shared with the bit
line.
 Cell has one read-write control line (word line)
and one I/O line (bit line)
 Unlike in the other dynamic memory cells the
storage capacitance is explicit
 Cannot Rely on the parasitic oxide and diffusion
capacitances of the transistors for data storage

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
•Capacitor store data in form of charges.
•If it is charged , the data stored on at logic 1 and if it is discharged, then it is of logic 0.
•The capacitor is accessed with the help of transistor.
•When the transistor is ON, data can be read or write with the help of capacitor and when
transistor is in off condition the charge across the capacitance should remain constant
•In an ideal case this capacitance should not loss its charge but practically there is some
leakage current and so the capacitor losses its charge gradually. That’s why DRAM is required
to be refreshed after a period
•The transistor is ON by applying the voltage to the address line and the charge across the
capacitor is made available to the bit line
•Sense amplifier is used to read the voltage available at the bit line.
•Each time when the read operation is performed, Capacitor losses its charge and need to be
refreshed. Pre charging the bit line by some finite value is also used to decrease the read
time or increase the speed.
•Write operation requires pre charging of the bit line with some finite value
•If we want to charge the capacitor C, then the bit voltage is applied to the bit line
 Static Read-Write Memory (SRAM) Circuits
 Read-write (R/W) memory circuits --designed to permit the modification (writing)
of data bits to be stored in the memory array
 Retrieval (reading) on demand
 Memory circuit is said to be static if the stored data can be retained indefinitely (as
long as a sufficient power supply voltage is provided, without any need for a
periodic refresh operation
 Various Configurations of Static RAM Cell
 Load devices may be polysilicon resistors
 Depletion-type nMOS transistors,
PMOS transistors
 The pass gates acting as data access
switches are enhancement-type
nMOS transistors

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
•We all know that computers work in binary language, so whatever input we are
giving to the computer will be converted into 1 and 1.
•Similarly outpou generated by computer is in the from of 0 and 1 and then it will be
converted into human understandable language.

•This SRAM consist of 6 transistors out of which 1 are the pass transistors which
provide access to the bit lineand other 4 are 2 cross coupled inverters among which
T1 and T2 forms a CMOS inverter pair and T3 and T4 forms another CMOs inverter
pair.
•There is also a 4 transistor SRam in which instaed of 2 tansisitors used in invertors,
2 resistors are used but is consumes lots of power. That’s why its not so popular and
so 6 transistors design is preferred over the 4 transistors design.
If we see its simplified circuit it will look like -
•For read operation transistors T1 and T2 are turned on by applying voltage
at the address lines.
•Then the voltage and point Q and Q’ are made available at the bit line
which is then sensed by the sense amplifiers connected with the bit line
•It can also sense the voltage difference at the bit line.
•The whole operation can also be accomplished by the single bit line also,
but to increase the speed, 2 bit lines are used
•Whatever data we want to insert in the memory, we will provide it to the bit
lines.
•If logic 1 is applied to the bit lines, then its complimented logic 0 is applied to B’
•This will switch on the pass transistors and the bit line voltageis applied to the
inverter circuit
Various Configurations of Static RAM Cell

(a) Symbolic representation of the two-inverter latch circuit with access switches
(b) Generic circuit topology of the MOS static RAM cell

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
Basic Operations of Resistive-Load SRAM Cell
 To perform read and write operations, two nMOS pass transistors
driven by the row select signal RS are used
 When RS is equal to logic "0," the pass
transistors M3 and M4 are turned off
 Latch circuit preserves one of its two
stable operating points
 If all word lines in the SRAM array are
inactive, voltage levels of the two
complementary bit lines (columns)
are equal during this phase

 419
• Semiconductor
• Memories

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
Basic Operations of Resistive-Load SRAM Cell
Write "1" operation:
 The voltage level of column C’ is forced to
logic-low by the data-write circuitry
 The driver transistor M1 turns off
 The voltage V1, attains a logic-high level,
while V2 goes low

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
Basic Operations of Resistive-Load SRAM Cell
Read "1" operation:
 Voltage of column C retains its precharge Level
 Voltage of column C’ is pulled down by M2
and M4
 The data-read circuitry detects the small
voltage difference (V c> Vc’)
and amplifies it as logic 1data output

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
 Full CMOS SRAM Cell
 May be designed simply by using cross-coupled CMOS inverters instead of the resistive-load
nMOS inverters
 The stand-by power consumption of the memory cell will be limited to the relatively small
leakage currents of both CMOS inverters.
 Drawback of using CMOS SRAM--cell area tends to increase
 Operation principle of the CMOS SRAM cell--identical
to that of the resistive-load nMOS cell
 Low standby power consumption been a driving force
for the increasing prominence of high- density
CMOS SRAMs

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
 Advantages of DRAM over SRAM
 Can be realized on a much smaller silicon area compared to the typical SRAM cell
 Require Access devices, or switches but this does not significantly affect the area advantage
over the SRAM cell
 No static power is dissipated for storing charge on the capacitance
 Dynamic RAM arrays can achieve higher integration densities than SRAM arrays
 Memory Classification of ROM
 Read-Only Memory (ROM)—only the retrieval of previously stored data and do not permit
modifications
 ROMs are non-volatile memories, i.e., the data storage function is not lost even when the
power supply voltage is off
 Depending on the type of data storage (data write) method, ROMs are classified as mask-
programmed ROMs, Programmable ROMs (PROM), Erasable PROMs (EPROM)
 Electrically Erasable PROMs
(EEPROM)
 Flash Memories

Source: CMOS Digital Integrated Circuits: Analysis & Design, McGraw-Hill, 3rd edition, Sung-Mo Kang & Yusuf Leblebici
 Programmable ROMs
 PROMs use fuses while EPROMs, EEPROMs, and Flash use charge stored on a floating gate
 Programmable ROMs can be fabricated as ordinary ROMs fully populated with pulldown
transistors in every position
 Each transistor is placed in series with a fuse made of polysilicon, nichrome, or some other
conductor that can be burned out by applying a high current.
 The user typically configures the ROM in a specialized PROM programmer before putting it
in the system
 As blown fuses cannot be repaired
 PROMs are also referred to as one-time programmable memories
 Flash Memory

•Flash memory is a non-volatile memory chip used for storage and for transferring
data between a personal computer (PC) and digital devices.
•It has the ability to be electronically reprogrammed and erased.
•It is often found in USB flash drives, MP3 players, digital cameras and solid-state
drives.
•Flash memory is a type of electronically erasable programmable read only memory
(EEPROM), but may also be a standalone memory storage device such as a USB
drive.
•EEPROM is a type of data memory device using an electronic device to erase or
write digital data.
•Flash memory is a distinct type of EEPROM, which is programmed and erased in
large blocks.
•Flash memory incorporates the use of floating-gate transistors to store data.
Floating-gate transistors, or floating gate MOSFET (FGMOS), is similar to MOSFET,
which is a transistor used for amplifying or switching electronic signals. Floating-gate
transistors are electrically isolated and use a floating node in direct current (DC).
Flash memory is similar to the standard MOFSET, except the transistor has two gates
instead of one.
•Flash works using an entirely different kind of transistor that stays switched on (or
switched off) even when the power is turned off.
•A flash transistor is different because it has a second gate above the first one.
When the gate opens, some electricity leaks up the first gate and stays there, in
between the first gate and the second one, recording a number one.
•Even if the power is turned off, the electricity is still there between the two gates.
That's how the transistor stores its information whether the power is on or off. The
information can be erased by making the "trapped electricity" drain back down
again.
•The transistors in flash memory are like MOSFETs only they have two gates on top
instead of one. This is what a flash transistor looks like inside. You can see it's an n-
p-n sandwich with two gates on top, one called a control gate and one called a
floating gate. The two gates are separated by oxide layers through which current
cannot normally pass
In this state, the transistor is switched off—and effectively storing a zero.
Both the source and the drain regions are rich in electrons (because they're made of
n-type silicon), but electrons cannot flow from source to drain because of the electron
deficient, p-type material between them.
But if we apply a positive voltage to the transistor's two contacts, called the bitline and
the wordline, electrons get pulled in a rush from source to drain.
A few also manage to wriggle through the oxide layer by a process called tunneling
and get stuck on the floating gate

The presence of electrons on the floating gate is how a flash transistor stores a one.
The electrons will stay there indefinitely, even when the positive voltages are removed
and whether there is power supplied to the circuit or not. The electrons can be flushed
out by putting a negative voltage on the wordline—which repels the electrons back the
way they came, clearing the floating gate and making the transistor store a zero again.
 Flash Memory
 As technology has improved, reprogrammable nonvolatile memory has largely displaced
PROMs
 These memories, include EPROM, EEPROM, and Flash
 Uses a second layer of polysilicon to form a floating gate between the control gate and the
channel
 Floating gate is a good conductor, but it is not
attached to anything

Floating gate nMOS transistor

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and David Money Harris
 Flash Memory
 Applying a high voltage to the control gate
 Causes electrons to jump through the thin oxide onto the floating gate (FN) tunneling
 Injecting the electrons induces a negative voltage on the floating gate, effectively increasing
the threshold voltage of the transistor to the point that it is always OFF

Floating gate nMOS transistor

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and David Money Harris
 NAND and NOR Flash string
 Floating gate transistors are connected in series to form strings
 Each string consists of 16 cells, a string select transistor, and a ground select transistor all
connected in series
 All attached to the bitline
 Control gate of each cell is connected to a wordline
 EEPROM – Features, Applications & Circuit
Diagram
EEPROM stands for electrically erasable
programmable read-only memory. It is a non-
volatile flash memory device, that is, stored
information is retained when the power is
removed. EEPROM generally offers excellent
capabilities and performance. In EEPROM we can
write and program the IC for many times and these
are acting as EPROM (UV erasable programmi
ng ROM).
 Principle of operation of EEPROM
The EEPROM uses the principle same as that of the UV-
EPROM. The electrons which are trapped in a floating gate
will modify the characteristics of the cell, so instead of that
logic “0” or logic “1” will be stored.
EEPROM is the memory device which implements the fewest
standards in cell design. Most of the common cells are
composed of two transistors. In this the storage transistor has
the floating gate that will trap the electrons. Apart from that
there is an access transistor which is used in the operation. In
EPROM , cell is erased when electrons are removed from the
floating gate, whereas in EEPROM , cell is erased when
electrons are trapped in the floating cell.
There are two distinct EEPROM families: serial and parallel
access. The serial access represents 90 percent of the overall
EEPROM in market, where as the parallel access EEPROMs
is about 10 percent.
Parallel EEPROM:
Parallel devices are available in higher densities
more then 256bits and are generally working faster.
Highly Reliable and these are mostly used for
military market.
They are pin compatible with EPROMs and flash
memory devices.

Serial EEPROM:
Serial EEPROMs are less dense (typically from 256
bit to 256Kbit) and are slower than parallel
devices.
They are much cheaper and used in more
“commodity” applications.
 EEPROM Cell Structure
•The floating-gate EEPROM memory cell uses two-tube cells, and its circuit
diagram is shown in Figure . One is the NMOS selection tube, which is used as the
cell address selection.
•The gate is connected to the word line (WL) and its drain bit line (BL). When
performing a read operation, add a level of about 2.5 V to the control grid of the
FLOTOX tube.
• Due to the previous erase and write operations, the turn-on voltage of the storage
tube on the selected byte is different, some are cut off, and some are turned on.
From this, it can be discriminated whether the unit stores “1” or “0”.
•In our design, the memory cell consists of two transistors. As shown in Figure , the
NMOS tube is used as a selection tube and is controlled by the word line.
•It can withstand a part of the high voltage and reduce the probability of breakdown
of the ultra-thin oxide layer of the floating gate tube.
•The floating gate transistor serves as a memory tube and stores data through a
tunnel oxide layer.
Applications of EEPROM
EEPROMs are used in many applications such
as telecom, consumer, automotive and
industrial applications. The other applications
are include:
1. The reprogrammable calibration data for test
equipment
2. Data storage from a learn function as in a
remote control transmitter.
Thank You