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Assignment 2 Unit 2

2 UNIT –II 2.1 VLSI Circuit Design Processes: 2.1.1 VLSI Design Flow, 2.1.2 MOS Layers, 2.1.3 Stick Diagrams, 2.1.4 Design Rules and Layout, and 2.1.5 Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates. 2.2 Basic circuit concepts, 2.2.1 Sheet Resistance RS and its concept to MOS, 2.2.2 Area Capacitance Units, 2.2.3 Calculations – RC Delays.

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Maharshi Sanand Yadav T
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265 views

Assignment 2 Unit 2

2 UNIT –II 2.1 VLSI Circuit Design Processes: 2.1.1 VLSI Design Flow, 2.1.2 MOS Layers, 2.1.3 Stick Diagrams, 2.1.4 Design Rules and Layout, and 2.1.5 Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates. 2.2 Basic circuit concepts, 2.2.1 Sheet Resistance RS and its concept to MOS, 2.2.2 Area Capacitance Units, 2.2.3 Calculations – RC Delays.

Uploaded by

Maharshi Sanand Yadav T
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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UNIT-2

UNIT-2
SHORT
1. Write about the layers used to create MOSFET
2. Define Rise Time, Fall Time and Delay Time
3. Define Sheet Resistance
4. What is the Scaling Effect on Resistance and Frequency of Operation?
5. Design NOR2 Logic and its Stick Diagram using CMOS Logic
6. Difference between Active Contact and Poly Contact
7. Define rise time and fall time, give its typical equation of Two Input NAND gate
8. Draw the Elmore Delay Model Circuit
9. Draw Layout of Two Transistors which are connected in series and parallel
10. Differentiate between Stick Diagram and Layout
11. Calculate the ON Resistance from VDD to Gnd for the given inverter circuit shown in figure. If
N-Channel Sheet Resistance is RSP = 2.5 x 104 ohm per square? RSN = 104 ohm per square

12. What are Lambda based Design Rules? Why should we follow them?
13. Define Rise and Fall time of a CMOS Inverter. Write the expressions for them
14. Explain Scaling Concept of MOSFET
15. Define Y=A(B+C) using CMOS Logic
16. Describe Fanout and Input Capacitance in CMOS Inverter
17. What is Propogation Delay and write the expression for the same
18. Define Delay in ICs
19. Draw the Schematic, Stick Diagram, Layout of 2-input AND Gate
20. Draw the Schematic, Stick Diagram, Layout of 2-input OR Gate

6 t h SEM ECE-VLSI Design-OU Unit-2 T Maharshi Sanand Yadav


UNIT-2
21. Draw the Schematic, Stick Diagram, Layout of 2-input NOT Gate
22. Draw the Schematic, Stick Diagram, Layout of 2-input NAND Gate
23. Draw the Schematic, Stick Diagram, Layout of 2-input NOR Gate
24. Draw the Schematic, Stick Diagram, Layout of 2-input XOR Gate
25. Draw the Schematic, Stick Diagram, Layout of 2-input XNOR Gate
26. Draw the Schematic, Stick Diagram, Layout of 3-input AND Gate
27. Draw the Schematic, Stick Diagram, Layout of 3-input OR Gate
28. Draw the Schematic, Stick Diagram, Layout of 3-input NOT Gate
29. Draw the Schematic, Stick Diagram, Layout of 3-input NAND Gate
30. Draw the Schematic, Stick Diagram, Layout of 3-input NOR Gate
31. Draw the Schematic, Stick Diagram, Layout of 3-input XOR Gate
32. Draw the Schematic, Stick Diagram, Layout of 3-input XNOR Gate
33. Draw the Schematic, Stick Diagram, Layout of HALF ADDER
34. Draw the Schematic, Stick Diagram, Layout of FULL ADDER
35. Draw the Schematic, Stick Diagram, Layout of 2x1 Multiplexer
36. Draw the Schematic, Stick Diagram, Layout of 4x1 Multiplexer

LONG
1. Sketch the stick diagram for a CMOS gate computing 𝒇 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝒂 + 𝒃 + 𝒄 + 𝒅). 𝒆
2. Draw the AOI logic gate diagram and CMOS circuit for the expression Y = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
[𝒂𝒃 + 𝒄𝒅]𝒆
3. Draw the Stick Diagram for the given function 𝒇 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝒂 + 𝒃 + 𝒄)
4. Draw the Layout of the function using CMOS Logic
a. 𝒇 = ̅̅̅̅̅̅̅̅̅̅̅
𝒂(𝒃 + 𝒄)
b. 𝒇 = ̅̅̅̅̅̅̅̅̅̅
(𝑨 + 𝑩)(𝑪 + 𝑫)
5. Write a Short Note on Scaling Theory
6. Calculate the ON Resistance of the circuit shown in the figure from VDD to GND if the n-channel
sheet resistance RSN = 104 Ohm per square and the P-channel sheet resistance RSP = 3.5 x 104
ohm per square

6 t h SEM ECE-VLSI Design-OU Unit-2 T Maharshi Sanand Yadav


UNIT-2
7. Define Active area and design n+ region, PFET. Draw the Typical structure of active contact
and poly contact
8. Define Active Contact, Poly Contact and Metal Contact and units their Characteristics
9. Draw the Stick Diagram for OAI gate
10. Explain VLSI Design Hierarchy
11. Draw the Layouts for series and parallel connected PFETs
12. Explain how the sheet resistance applied to MOS transistor when L=2 lambda, W=2 lambda
13. What is transmission gate logic? Design 4 to 1 MUX using transmission gate logic

6 t h SEM ECE-VLSI Design-OU Unit-2 T Maharshi Sanand Yadav

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