LOGICAL INSTRUCTIONS
AND, AX, BX
Causes the contents of BX to be ANDed with the content of AX. The result
is reflected by the new content of AX.
If [AX] 1234h
[BX] 000Fh
1234h . 000Fh = 000100100110100b . 0000000000001111b
= 0000000000000100
= 0004h [AX]
Mnemonic Meaning Format Operation Flags affected
AND Logical AND AND D,S [S].[D][D] OF SF ZF PF CF
AF Undefined
OR Logical OR OR D,S [S]+[D][D] OF SF ZF PF CF
AF Undefined
XOR Logical XOR D,S [S] + [D] [D] OF SF ZF PF CF
Exclusive OR AF Undefined
NOT Logical NOT NOT D [D’][D] None
For AND,OR,XOR for NOT
Destination Source Destination
Register Register Register
Register Memory Memory
Memory Register
Register Immediate
Memory Immediate
Accumulator Immediate
INSTRUCTION SET – LOGICAL AND BRANCHING 1
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Example:
Describe the result of executing the following sequence of instructions
a. Mov AL, 01010101b
b. And AL, 00011111b
c. Or AL, 11000000b
d. Xor AL, 00001111b
e. Not AL
Solution:
a. [AL] 01010101B ( 55h )
b. 01010101b . 00011111b = 00010101b = 55 h , 1Fh = 15h [AL]
c. 00010101b + 11000000 = 11010101b = 15h + C0h = D5h [AL]
d. 11010101b Exor 00001111b = 11011010b = D5h exor 0Fh = DAh [AL]
e. [AL] = 11011010b’ = 00100101b = 25 h
C:>DEBUG
-A
1076:0100 MOV AL,55
1076:0102 AND AL,1F
1076:0104 OR AL,C0
1076:0106 XOR AL,OF
1076:0108 NOT AL
1076:010A
-T
AX=0055 ,,,,,,
-T
AX=0015 …….
-T
AX=00D5 …….
-T
AX=00DA …..
-T
AX=0025…..
INSTRUCTION SET – LOGICAL AND BRANCHING 2
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SHIFT INSTRUCTIONS
Mnemonic Meaning Format Operation Flags affected
SAL/SHL
Shift arithmetic left/shift logic left
SHL/SAL D, Count
Shift the [D] left by the number of bit
Positions equal to count and fill the vacated
Bit positions on the right with zeros
CF PF SF ZF OF
AF Undefined
OF Undefined if count == 1
SHR
Shift logical Right
SHR D, Count
Shift the [D] right by the number of bit
Positions equal to count and fill the vacated
Bit positions on the left with zeros
CF PF SF ZF OF
AF Undefined
OF Undefined if count === 1
SAR
Shift arithmetic Right
SAR D, Count
Shift the [D] right by the number of bit
Positions equal to count and fill the vacated
Bit positions on the left with the original
MSB
OF SF ZF PF CF
AF Undefined
INSTRUCTION SET – LOGICAL AND BRANCHING 3
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Allowed operand Destination Count
Register 1
Register CL
Memory 1
Memory CL
In an arithmetic shift to the left SAL operation, the vacated bits at the
right of the operand are filled with zeros, whereas in an arithmetic shift to
the right, SAR operation, the vacated bits at the left are filled with the
value of the original MSB of the operand.
Thus, in an arithmetic shift to the right the original sign of the number is
extended.
Example:
SHL AX, 1
AX 0001001000110100 1234
0 001001000110100 0 0 2468
CF lsb
Bit 0
SHR AX, CL where CL = 02 h
0001001000110100 1234
0 0000010010001101 0 048D
CF
INSTRUCTION SET – LOGICAL AND BRANCHING 4
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Example:
Assume that CL contains 02 h and AX contains 091Ah.
Determine the new contents of AX and the carry flags affected
SHR AX, CL
[AX] = 0246h and [CF] = 1b
0000100100011010
0000001001000110 1
CF
C:> DEBUG
-A
1076:0100 SAR AX,CL
1076;0102
-R AX
AX 0000
:091A
-R CX
CX 0000
:2
-R F
NV UP EI PL NZ NA PO NC
-T
AX=0246 BX=0000 CX=0002 DX=0000 SP=FFEE BP=0000 SI=0000 DI=0000
DS=1076 ES=1076 SS=1076 CS=1076 IP=0102 NV UP EI PL NZ NA PO CY
1076:0102 241F AND AL,1F
-Q
INSTRUCTION SET – LOGICAL AND BRANCHING 5
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ROTATE INSTRUCTION
Mnemonic Meaning Format Operation Flags affected
ROL
Rotate left
ROL D, Count
Rotate the [D] left by the number of bit
Positions equal to count. Each bit shifted out
From the left most bit goes back into the
Rightmost bit positions
CF
OF undefined if count === 1
ROR
Rotate right
ROR D, Count
Rotate the [D] right by the number of bit
Positions equal to count. Each bit shifted out
From the right most bit goes into the left
Most bit position.
CF
OF Undefined if count === 1
RCL
Rotate left through carry
RCL D, Count
Same as ROL except carry is attached to
[D] for rotation
CF
OF Undefined if count === 1
RCR
Rotate right through carry
RCR D, Count
Same as ROR except carry is attached to
INSTRUCTION SET – LOGICAL AND BRANCHING 6
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[D] for rotation
CF
OF Undefined if count === 1
Destination count
Register 1
Register CL
Memory 1
Memory CL
Example:
What is the result in BX and CF after Execution of the following
instruction?
RCR BX, CL
Assume that, prior to execution of the instruction
[CL] = 04h, [BX] = 1234h and [CF] = 0,
Solution:
The original contents of BX are
[BX] = 0001001000110100b = 1234 h
Execution of the RCR instruction causes a 4 bit rotate right through carry
to take place on the data in BX. Therefore, the original content of bit 3,
which is zero, resides in carry; CF=0 and 1000b has been reloaded from bit
15. The resulting contents of BX are
[BX] = 1000000100100011 b = 8123h
[CF] = 0b
[BX] 0100000100100011 b = 4123h
INSTRUCTION SET – LOGICAL AND BRANCHING 7
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C:>DEBUG
-A
1076:0100 RCR BX, CL
1076:0102
-R BX
BX 0000
:1234
-R CX
CX 0000
:4
-R F
NV UP EI PL NZ NA PO NC –
-T
AX=0000 BX=8123 CX=0004 DX=0000 SP=FFEE BP=0000 SI=0000 DI=0000
DS=1076 ES=1076 SS=1076 CS=1076 SP=0102 NV UP EI PL NZ NA PO NC
1076:0102 241F AND AL,1F
-Q
FLAG CONTORL INSTRUCTIONS
Mnemonic Meaning Operation Flags affected
LAHF Load AH from Flags [AH] [flags] None
SAHF Store AH into Flags [flags] [AH] SF ZF AF PF CF
CLC Clear carry flag [CF] 0 CF
STC Set carry flag [CF] 1 CF
CMC Complement carry flag [CF] [CF’ ] CF
CLI Clear interrupt flag [IF] 0 IF
STI Set interrupt flag [IF] 1 IF
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Example:
Write an instruction sequence to save the current contents of the 8086
microprocessors flags in memory location MEM1 and the reload the flags
with the contents of memory location MEM2
Solution:
LAHF
MOV MEM1, AH
MOV AH, MEM2
SAHF
Start at memory address 00110 h
MEM1 --- 00150h
MEM2 --- 00151h
Initialize MEM1 = FF h and MEM2 = 01 h
C:>DEBUG
-A 0:0110
0000:0110 LAHF
0000:0111 MOV [0150],AH
0000:0115 MOV AH, [0151]
0000:0119 SAHF
0000:011A
-E 0:0150 FF 01
-R CS
CS 1076
:0
-R IP
IP 0100
:0110
-R DS
DS 1076
:0
-R
…..
….
-T
-T
INSTRUCTION SET – LOGICAL AND BRANCHING 9
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-T
-T
-Q
COMPARE INSTRUCTIONS
Mnemonic Meaning Format Operation Flags affected
CMP Compare CMP D, S [D] – [S] is used in setting or resetting the
Flags( 2’s Complement arithmetic)
CF AF OF PF SF ZF
Destination Source
Register Register
Register Memory
Memory Register
Register Immediate
Memory Immediate
Accumulator Immediate
Example:
Describe what happens to the status flags as the sequence of instructions
that follows is executed.
MOV AX, 1234 h
MOV BX, 0ABCD h
CMP AX,BX
Assume that flags ZF SF CF AF OF AND PF are all initially reset.
Solution:
[Ax] – [Bx] = 0001001000110100b – 1010101111001101b
= 0110011001100111b
The result is non zero and positive ZF and SF are ‘0’
INSTRUCTION SET – LOGICAL AND BRANCHING 10
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Overflow has not occurred OF is ‘0’
Carry and Auxiliary have occurred CF and AF ‘1’
Result has odd parity PF is ‘0’
JUMP INSTRTUCTION
Unconditional Jump Instruction
Mnemonic Meaning Format Flags affected
JMP Unconditional Jump JMP operand None
Operand
Short label
Near label
Far label
Memptr 16
Regptr 16
Memptr 32
Example: Verify the operation of the instruction JMP BX
Let BX be 0010h
C:>DEBUG
-A
1076:0100 JMP BX
1076:0102
-R BX
BX 0000
:10
-R
-T
-Q
INSTRUCTION SET – LOGICAL AND BRANCHING 11
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JMP [BX]
Assume that the pointer held in BX is 1000h and the value held at memory
location DS:1000 is 200h
C:> DEBUG
-A
1076:0100 JMP [BX]
1076:0102
-R BX
BX 0000
:1000
-E 1000 00 02
-D 1000 1001
1076:1000 0002
-R
………..IP = 0100
-T
…… IP = 0200
-Q
The inter-segment unconditional jump instruction correspond to far-label
and Memptr 32 operand. Four consecutive memory bytes contain the offset
and code segment address
Ex. JMP DWORD PTR [DI]
CONDITIONAL JUMP INSTRUCTION
JCC Conditional Jump JCC operand None
If the specified condition CC
Is true the jump to the address
Specified by the operand is initiated
Otherwise the next instruction is executed
INSTRUCTION SET – LOGICAL AND BRANCHING 12
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Mnemonic Meaning Condition
JA ABOVE CF=0 AND ZF =0
JAE ABOVE OR EQUAL CF=0
JB BELOW CF=1
JBE BELOW OR EQUAL CF=1 OR ZF=1
JC CARRY CF=1
JCXZ CX REGISTER TO ZERO ( CF OR ZF ) =0
JE EQUAL ZF=1
JG GREATER ZF=0 AND SF=0F
JGE GREATER OR EQUAL SF=OF
JL LESS (SF XOR OF) = 1
JLE LESS OR EQUAL ((SF XOR OF) OR ZF) = 1
JNA NOT ABOVE CF =1 OR ZF =1
JNAE NOT AVOVE NOR EQUAL CF=1
JNB NOT BELOW CF=0
JNBE NOT BELOW NOR EUQAL CF=0 AND ZF=0
JNC NOT CARRY CF = 0
JNE NOT EQUAL ZF = 0
JNG NOT GREATER ((SF XOR OF) OR ZF) = 1
JNGE NOT GREATER NOR EUQAL (SF XOR OF) =1
JNL NOT LESS SF = OF
JNLE NOT LESS NOR EUQAL ZF=0 AND SF=OF
JNO NOT OVERFLOW OF = 0
JNP NOT PARITY PF = 0
JNS NOT SIGN SF = 0
JNZ NOT ZERO ZF = 0
JO OVERFLOW OF = 1
JP PARITY PF = 1
JPE PARITY EVEN PF = 1
JPO PARITY ODD PF = 0
JS SIGN SF = 1
JZ ZERO ZF = 1
INSTRUCTION SET – LOGICAL AND BRANCHING 13
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BLOCK TRANSFER PROGRAM.
MOV AX, DATASEGADDR
MOV DS, AX
MOV SI, BLK1ADDR
MOV DI, BLK2ADDR
MOV CX, N
NXTPT: MOV AH, [SI]
MOV [DI], AH
INC SI
INC DI
DEC CX
JNZ NXTPT
HLT
INSTRUCTION SET – LOGICAL AND BRANCHING 14
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SUBROUTINE HANDLING INSTRUCTIONS
Mnemonic CALL
Meaning Subroutine call
Format CALL operand
Flags affected None
Operation Execution continue from the address of the subroutine
specified by the operand. Information required to return back to the main
program such as IP and CS are saved on the stack.
Operand Near_proce, Far_proce, Memptr 16, Regptr 16, Memptr 32.
• Just like JMP instruction, CALL allows implementation of two types of
operations --- the inter-segment call
The intra-segment call
• Near_proc, Memptr 16, Regptr 16, intra-segment call to a subroutine
IP is saved on stack.
SP is decremented by two
Then IP is loaded with new address
• In a Near_proc operand, ( immediate operand) the offset of the first
instruction of the subroutine in the current code segment is supplied
directly
CALL LABEL ( label is 16 bit offset)
Subroutine can reside anywhere in the current code segment
• Memptr 16 and Regptr 16 operands provide indirect subroutine
addressing by specifying a memory location or an internal register.
CALL BX
Contents of BX are loaded onto IP
CALL [BX]
Has its subroutine offset address at the memory location whose physical
address is derived from the contents of DS and BX subroutine in the
same code segment as the call statement.
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• Inter-segment Call
Far_proc and Memptr 32 operand
These specify both the new Ip and New segment address of CS
CALL DWORD PTR [DI]
Here the physical address of the first byte of the 4-byte pointed in
memory is derived from the content of DS and DI
Mnemonic RET
Meaning Return
Format RET or RET operand
Flags affected None
Operation Return to the main program by restoring IP ( and CS for
far_proc). If operand is present, it is added to the contents of SP
Operand None
Disp 16
RET2 When executed adds 2 to the SP after restoring the return
address
PUSH AND POP INSTRUCTIONS
PUSH AX, [ [SP ] – 1 ] [AH]
[ [SP] – 2 ] [AL]
[SP] [SP] – 2
POP AX
[AL] [ [SP] ]
[AH] [ [SP] +1 ]
[SP] [ SP ] + 2
INSTRUCTION SET – LOGICAL AND BRANCHING 16
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Mnemonic Meaning Format Operation Flags affected
PUSH Push word on to stack PUSH S [ [SP] ] [S] None
POP Pop word off stack POP D [D] [ [SP ] ] None
Operands ( S or D)
Register
Seg-reg ( CS illegal )
Memory
Example:
SUM PROC NEAR
PUSH DX
MOV DX, TOTAL
ADD DX, 31h
MOV TOTAL, DX
POP DX
RET
SUM ENDP
Mnemonic Meaning Operation Flags affected
PUSHF Push flags onto stack [ [SP] ] [FLAGS] None
POPF Pop flags from stack [flags] [ [ SP ] ] OF DF IF TF SF
ZF AF PF CF
INSTRUCTION SET – LOGICAL AND BRANCHING 17
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Mnemonic Meaning Format Operation
LOOP Loop LOOP short_label [CX] [CX]-1
Jump is initiated to location defined by
Short label if [CX] != 0; otherwise execute
Next sequential instruction
LOOPE/ Loop while LOOPE short_label [CX] [CX] -1
LOOPZ equal/loop LOOPZ short_label
While zero
Jump to location defined by short label if
[CX] != 0 and [ZF] = 1; otherwise execute
next sequential instruction
LOOPNE/ Loop while LOOPNE short_label [CX] [CX] -1
LOOPNZ not equal/ LOOPNZ short_label
Loop while
Not zero Jump to location defined by short label if
[CX] != 0 and [ZF] =0; otherwise, execute
next sequential instruction
Example:
MOV AX, DATASEGADDR
MOV DS, AX
MOV SI, BLK1ADDR
MOV DI, BLK2ADDR
MOV CS, N
NXTPT: MOV AH, [SI]
MOV [DI], AH
INC SI
INC DI
LOOP NXTPT
HLT
INSTRUCTION SET – LOGICAL AND BRANCHING 18
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STRING INSTRUCTIONS
MOVS Move string MOVS operand None
[ [ES]0 + [DI] ] [ [DS]0 + [SI] ]
[SI] [SI] +/- 1 or 2
[DI] [DI] +/- 1 or 2
MOVSB Move String byte MOVSB None
[ [ES]0 + [DI] ] [ [DS]0 + [SI] ]
[SI] [SI] +/- 1
[DI] [DI] +/- 1
MOVSW Move string word MOVSW None
[ [ES]0 + [DI] ] [ [DS] 0 + [SI] ]
[ [ES]0 + [DI] +1 ] [ [DS]0 +[SI] + 1]
[SI] [SI] +/- 2
[DI] [DI] +/- 2
CMPS Compare string CMPS operand CF PF AF ZF SF OF
Set flags as per
[ [DS]0 + [SI] ] – [ES]0 + [DI] ]
[SI] [SI] +/- 1 or 2
[DI] [DI] +/- 1 or 2
SCAS Scan String SCAS Operand CF PF AF ZF SF OF
Set flags as per
[ AL or AX ] – [ [ES]0 + [DI] ]
[DI] [DI] +/- 1 or 2
LODS Load String LODS Operand None
[AL or AX] [ [DS]0 + [SI] ]
[SI] [SI] +/- 1 or 2
STOS Store String STOS operand None
[ [ES]0 + [DI] ] [AL or AX] +/- 1 or 2
[DI] [DI] +/- 1 or 2
INSTRUCTION SET – LOGICAL AND BRANCHING 19
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INSTRUCTION SET – LOGICAL AND BRANCHING 20
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