HARDWARE DESCRIPTION LANGUAGE

PRACTICAL FILE
SUBJECT-CODE: ECLR 71

SUBMITTED BY: SUBMITTED TO.

DANISHBIR SINGH DR. TRAILOKYA NATH
12015084 SASAMAL
ECA1 ASSISTANT PROFESSOR
7th SEMESTER

ELECTRONICS AND COMMUNICATION

ENGINEERING DEPARTMENT, NIT
KURUKSHETRA
Date: 07-08-2023
 Experiment – 1

Objective:
Write a VHDL program to implement and simulate 3:8 decoder.
Resources Required:
Hardware Requirement: Computer
Software Requirement: XILINX Software
Theory:
A binary decoder is a combinational logic circuit that converts a binary integer
value to an associated pattern of output bits. They are used in a wide variety of
applications, including data de- multiplexing, seven segment display, and
memory address decoding. Decoder is with multiple data inputs and multiple
outputs that converts every unique combination of data input states into a
specific combination of output states.
Example: Imagine you are a mall security guard. In your office is a very
important and unique public announcement (PA) phone. The phone has three
dialing buttons (A, B, C) and is connected to eight different speakers, as shown
in Table 1. Consequently, you get to choose which section of the mall hears your
announcement based on the set of buttons you press. For example, if you press
A and B and start speaking into the phone (ABC = 110), the Food Court (D6) is
the only place that can hear you. However, if you press A and C (ABC = 101)
then the Lady’s Room (D5) is the only place that can hear you. Such a public
announcement phone (or PA system) is an example of a 3-to-8 decoder. Since
the phone has three buttons each of which can either be in one of two possible
states — pressed (=1) or not pressed (= 0) — then the phone can dial eight
possible different numbers (23 = 2*2*2 = 8) as shown below:

A B C Mall Area
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

Application: The Decoders were used in analog to digital conversion in analog

decoders, Used in electronic circuits to convert instructions into CPU control
signals, also used in logical circuits, data transfer.
Truth Table:
Inputs Outputs
EN A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0

Boolean Expression :
Y0 = A’B’C’
Y1 = A’B’C
Y2 = A’BC’
Y3 = A’BC
Y4 = AB’C’
Y5 = AB’C
Y6 = ABC’
Y7 = ABC

VHDL Code:
Behavioral Modelling
entity decoder is
Port ( a : in STD_LOGIC_VECTOR(2 DOWNTO 0);
a1 : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end decoder;
architecture Behavioral of decoder is
begin
process(a)
begin
case a is
when "000"=>a1<="10000000";
when "001"=>a1<="01000000";
when "010"=>a1<="00100000";
when "011"=>a1<="00010000";
when "100"=>a1<="00001000";
when "101"=>a1<="00000100";
when "110"=>a1<="00000010";
when "111"=>a1<="00000001";
when others=>null;
end case;
end process;
end Behavioral;

Output and Observation:

RTL Schematic of 3:8 Decoder:
 Fig:1.1

Circuit Diagram of Decoder:

Fig: 1.2

This is the circuit diagram of 3 to 8 decoder. Here we are providing a 3 bits

input at input port and getting the corresponding 8 bits output at the output port.
Behavioral Simulation Result at time period 1-microsecond and
frequency 1-MHz:
 Fig: 1.3

Fig: 1.3 is showing the behavioral simulation result of 3 to 8 decoder at time

period 1micro second and frequency 1MHz. The output result is satisfying the
truth table. No time delay is observed in this case.

Post Route Simulation Result at time period 1-microsecond and

frequency 1-MHz:
 Fig:1.4

Fig: 1.4 is showing the post route simulation result of 3 to 8 decoder at time
period 1micro second and frequency 1MHz. The output result is satisfying the
truth table. Here a time delay of 5ns is observed between the input and output
signal.
Observed Time Delay is 5ns.
Timing Details:

Results:
VHDL codes of 3:8 decoder is implemented and simulated successfully.
Resulting output is satisfying the truth table of decoder. Observed time delay is
9.239ns from timing details and 5ns from post route simulation.