AN797

TC4426/27/28 System Design Practice

The system design practices needed are not difficult to apply.

Author: Scott Sangster,
The simple good engineering practice of bypassing the power
Microchip Technology, Inc.
supply, minimizing stray lead inductance, and grounding unused
driver inputs will solve most system problems. Nothing new
required — just a little careful application of techniques common
INTRODUCTION to any high speed CMOS system.
The TC4426/4427/4428 are high-speed power MOSFET drivers
built using Microchip Technology's tough CMOS process. They The TC4426 family outputs are CMOS. Low quiescent power
are improved versions of the earlier TC426/427/428 family of and high output voltage drive (very important with 5V supply
high-speed power MOSFET drivers (with which they are pin operation) result. Since the outputs are CMOS the potential for
compatible) and are capable of giving reliable service in far more activating a parasitic SCR exists. This must be avoided to
demanding electrical environments. They will not latch up under prevent potential device destruction. If the TC4426 output,
any conditions within their power and voltage ratings. They are not like any CMOS chip, is driven below ground or above the
subject to damage when up to 5V of noise spiking (of either positive power supply an internal parasitic SCR can be
polarity) occurs on the ground pin. They can accept, without turned on. The high current flow can damage the device.
damage or logic upset, up to 500mA of reverse current (of either The actual TC4426 output stage is shown in Figure 1. The
polarity) being forced back into their outputs. All terminals are fully IC layout and simplified equivalent SCR circuit are shown
protected against up to 4kV of electrostatic discharge. in Figures 2 and 3.
As a result, the TC4426/4427/4428 are much easier to use, more VCC (Pin 6)
flexible in operation, and much more forgiving than any other
drivers (CMOS or bipolar) currently available. Because they are P-Channel
fabricated in CMOS, they dissipate a minimum of power and
provide rail-to-rail voltage swings to ensure the logic state of any
load they are driving.
Output
The TC4426/27/28 fast switching times are made possible by
Internal
a low impedance CMOS output stage. The high peak currents
make 30nsec rise/fall times possible.
N-Channel
The rapid rise/fall times do, however, require systems be de-
signed with adequate power supply decoupling and stray lead Ground (Pin 3)
inductance minimization. Practices which are adequate for 1µsec
rise/fall times and 20mA peak currents will not be adequate with FIGURE 1: TC4426 output.
the TC4426 family. The same laws of physics apply in both
systems. The results may be negligible in one and of prime
Internal TC4426 TC4426
importance in another. VCC Gate Drive Output

For example, a 0.1µH power lead inductance (4" of 0.025"

diameter wire) can cause a voltage spike 1000 times larger in a
Ground
fast system with an unbypassed supply.
S G D D G S

Low Speed System High Speed System

LS = 0.1µH LS = 0.1µH
Q2
∆VOUT = 18V ∆VOUT = 18V Q1
R2

t = 1µsec t = 30nsec P-Well

IPK = 20mA IPK = 600mA R1
CL = 1000pF CL = 1000pF
∆VSUPPLY = L di/dt ∆VSUPPLY = L di/dt
= 2mV = 2.0V
P-Channel N-Channel

FIGURE 2: Output stage IC layout.

© 2002 Microchip Technology, Inc. DS00797A-page 1

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VCC Make Connections
VCC (Pin 6) Close to Device Pins

R1
1µF 0.1µF
Ceramic Disk
Q1 Schottky
DP Diodes

Connect
Make Connections
Q2 DN to Pin 3
Close to Device Pins
R2 Input TC4426/ Output
27/28
3
Ground (Pin 3)
Minimize Lead
The Unused Length to
Power Mosfet
FIGURE 3: Equivalent SCR circuit. Input to Ground

The IC parasitic SCR can be turned on if DP is raised above FIGURE 4: Equivalent SCR circuit.
VCC or if DN is forced below ground. An inductive load at the
output can also create a voltage swing at the output that ex-
ceeds the positive supply or undershoots ground. Stray Inductance
in Power Supply

If the output is raised above the positive supply, current is VS = 18V

LS = 50nH
injected into the emitter of Q1 and swept into the collector. The
V+
Q1 collector feeds the base of Q2 and R2. When the base of Q2 6
reaches 0.6V Q2 turns on. This forces Q1 on. The SCR is now Assume:
"fired" shorting the positive power supply to ground. A similar ∆IOUT = 0.6A
situation exists when the output is driven below ground. ∆t = 20nsec
VIN
3
The internal SCR can also be triggered by excessive voltage on
the power supply that results in internal voltage breakdown. The
current injected can trigger the SCR action. 0.6
∆V = L di = 50 (10-9) = 1.5V
dt 20 x 10-9
By limiting the current injected into the TC4426 output when the
Stray inductance in power supply can cause voltage at V+ to exceed absolute
output is above the positive power supply latch up is avoided. maximum rating. Solution is to bypass supply as close to pins 6 & 3 as possible.
The limiting current is:
FIGURE 5: Stray supply lead inductance can decrease reliability.
VBE
I≤
R2 II RONP
VS
where:
RONP = ON resistance of P channel device (12Ω max) 0.1µF
1µF
VBE = Q2 base emitter turn on voltage (Approx. 0.6V) Ceramic
R2 = Bulk resistance Capacitor

Assuming the ON resistance dominates, the current should be 6

limited to 40mA. A similar analysis with the output below ground Tie Unused
indicates the current pulled out of the TC4426 output should be TC4426/
Inputs to Ground 27/28
limited to 60mA. The maximum allowable latch current is tem-
3
perature sensitive. At high chip temperature the base emitter
voltages are reduced. A 1°C rise lowers VBE by 2.2mV.

Current limiting with a series output resistor may not be practical

in all systems. The output rise and fall times may increase. An
alternate solution uses low forward voltage output clamp diodes
to bypass the SCR trigger current around the device. Notes: 1. Low inductance 0.1µF ceramic disk or monolithic capacitor.
2. Bypass as close to Pin 6 & 3 as physically possible.
3. Remember unused inputs should be grounded.
4. Bypassing is important.

FIGURE 6: Suggested bypass procedure.

DS00797A-page 2 © 2002 Microchip Technology, Inc.

 AN797

VS
C

TC4426 RL 10-15Ω

VIN VIN
DS0026
R 1µF 0.1µF AVX
Ceramic MLC
WIMA
MKS-2

FIGURE 7: TC4426 has CMOS inputs. Speed up capacitors 6

are not required. TC4426/
Input Output
27/28
External output clamp diodes prevent the TC4426 output from Tie Unused 3
being pulled far enough outside the power supply range to turn on Inputs to Ground
the parasitic SCR. (See App. Note 763).

The external diodes must have a lower forward on base to FIGURE 8: RL current limiting protects device and will not
emitter voltage than the parasitic transistor junctions. Schottky degrade switching speed.
small signal diodes are suitable. Several possible types are:
• Panasonic: P/N MAZH735
• ON Semiconductor: P/N BAS40-04LTI (dual series) The output N and P channel devices should not be forced to
• Zetex: P/N ZHCS1000 conduct current simultaneously. This can happen if an unused
input is left floating. Unused inputs must be connected to ground
To be effective the output clamp diodes must be connected close to or the positive supply. A ground connection will minimize steady
the output, supply and ground device pins. state supply current. This is common engineering practice fol-
Supply bypass capacitors must also be connected between VCC lowed in CMOS logic system design but is sometimes over-
(Pin 6) and Ground (Pin 3). Connections must be close to the looked during a "quick" bench evaluation. Floating inputs cause
actual device pins (approx. 0.5"). A 0.1µF ceramic disk capacitor excessive current flow and may potentially destroy the driver.
in parallel with a 1µF low ESR film capacitor is suggested.
Without supply bypassing, power supply lead inductance can The input drive signal should also have rise and fall times less
cause voltage breakdown. The bypass capacitors also supply than 1µsec. This minimizes time spent in the output stage transi-
the transient current needed during capacitive load charging. tion region.

A 10Ω to 15Ω resistor in series with the power supply filters Package Power Dissipation
voltage spikes present at the TC4426/27/28 supply terminal.
Should latch up occur, this will also limit current. Rise and fall Input signal duty cycle, power supply voltage, and capacitive load
times will not be affected if the recommended supply bypassing influence package power dissipation. Given power dissipation and
is used. See Figure 8. package thermal resistance the maximum ambient operation tem-
perature is easily calculated. The CerDIP 8-pin package junction to
The DS0026 has a bipolar input. A speed up capacitor is normally ambient thermal resistance is 150°C/W. At 25°C the package is
used to decrease switching time. Base storage time is reduced. rated at 800mW maximum dissipation. Maximum allowable chip
The capacitor causes a voltage spike drive at the input that temperature is 150°C.
extends beyond VCC or ground. The TC4426 input is CMOS and
does not require a speed up capacitor. In converting DS0026 Three components make up total package power dissipation:
sockets to the TC4426/27/28 the capacitor should be remove. 1. Capacitive load dissipation (PC)
This will maximize drive to the device and minimize transition 2. Quiescent power (PQ)
time. Benefits include fewer components and reduced insertion 3. Transition power (PT)
costs. See Figure 8.
The capacitive load caused dissipation is a direct function of
frequency, capacitive load, and supply voltage. The package
The TC4426/27/28 outputs feature a low impedance P-channel
power dissipation per driver is:
pull-up MOS device and low impedance N-channel pull-down
MOS device. The low resistance outputs are responsible for the
30nsec rise and fall times. The CMOS construction minimizes
current drain.

© 2002 Microchip Technology, Inc. DS00797A-page 3

AN797
Eq. 1: PC = f C VS2 Table 1 gives the total package power dissipation for several
different cases using the formulas previously developed. If only
where: f = Switching frequency one driver is active divide the package power dissipation numbers
C = Capacitive load by two in Table 1.
VS = Supply voltage
Package Power Dissipation
Quiescent power dissipation depends on input signal duty cycle. CerDIP Package (θJA = 150°C/W)
Max
A logic low input results in a low power dissipation mode with only Ambient
0.6mA total current drain. Logic high signals raise the current to Capacitive Input Supply Operating
8mA maximum. The quiescent power dissipation is: Load Frequency Voltage PQ PC PT PD Temp
(pF) (kHz) (V) (mW) (mW) (mW) (mW) (°C)
Eq. 2: PQ = (VS)(D)(IH) + (VS)(1 – D)(IL) 1000 50 18 77 32 3 112 125
1000 100 18 77 65 6 148 125
where: IH = Quiescent current with both inputs high (8mA Max) 1000 200 18 77 130 12 219 117
IL = Quiescent current with both inputs low (0.6mA Max) 1000 400 18 77 259 23 359 96
1000 1000 18 77 648 59 784 32
D = Duty cycle 1000 50 12 52 14 2 68 125
1000 100 12 52 29 4 85 125
Transition power dissipation is normally not significant. It arises
1000 200 12 52 58 8 118 125
because the output stage N and P channel MOS transistors are 1000 400 12 52 115 16 183 123
on simultaneously for a very short period when the output changes. 1000 1000 12 52 288 39 379 93
The transition package power dissipation power driver is approxi- 2000 50 18 77 65 3 145 125
mately: 1000 1800 12 52 518 70 640 54
50 4000 18 77 130 235 442 84
Eq. 3: PT = f VS (1.63nA x s) 1000 100 18 77 65 6 148 125
500 100 18 77 32 6 115 125
An example shows the relative magnitude for each term. Both 500 200 15 65 45 10 120 125
drivers are driven with a 50% duty cycle signal at the same 500 100 15 65 23 5 93 125
frequency. Capacitive load is the same for each driver. Notes: 1. Duty Cycle = 50%
2. Each input driven
Example 1: 3. Each output with capacitive load
4. Ambient operating temperature should not exceed 85°C for
C = 1000pF "EOA" and "EPA" devices or 125°C for "MJA" devices.
VS = 18V
D = 50% TABLE 1: TC4426 package power dissipation.
f = 200kHz
PD = Package power dissipation = PC + PQ + PT
= 130mW + 77mW + 11.7mW
= 219mW
Max. operating temperature = TJ – θJA (PD)
= 117°C
where:
TJ = Max. allowable junction temperature (150°C)
θJA = Junction to ambient thermal resistance (150°C/W, CerDIP)

DS00797A-page 4 © 2002 Microchip Technology, Inc.

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NOTES:

© 2002 Microchip Technology, Inc. DS00797A-page 5

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NOTES:

DS00797A-page 6 © 2002 Microchip Technology, Inc.

 AN797

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© 2002 Microchip Technology, Inc. DS00797A-page 7

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03/01/02

*DS00797A*

DS00797A-page 8  2002 Microchip Technology Inc.