PIC 16F877A MICROCONTROLLER:

High Performance RISC CPU:

• Only 35 single word instructions to learn
• All single cycle instructions except for program branches, which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM)
• Pin out compatible to PIC16C72/72A and PIC16F872
• Interrupt capability
• Eight-level deep hardware stack
• Direct, Indirect and Relative Addressing modes

Peripheral Features:

• High Sink/Source Current: 25 mA

• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
• Capture, Compare, PWM (CCP) module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 8-bit, 5-channel analog-to-digital converter
• Synchronous Serial Port (SSP) with SPI™ (Master/Slave) and I2C™ (Slave)
• Brown-out detection circuitry for Brown-out Reset (BOR)

CMOS Technology:
• Low power, high speed CMOS FLASH technology
• Fully static design
• Wide operating voltage range: 2.0V to 5.5V
• Industrial temperature range
• Low power consumption:
- < 0.6 mA typical @ 3V, 4 MHz
- 20 A typical @ 3V, 32 kHz
- < 1 A typical standby current

PIN DIAGRAM
Special Microcontroller Features:
• 1,000 erase/write cycle FLASH program memory typical
• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• In-Circuit Serial Programming™ (ICSP™) via 2 pins
• Processor read access to program memory

MEMORY ORGANIZATION
There are two memory blocks in the PIC16F72 device. These are the program memory
and the data memory. Each block has separate buses so that concurrent access can occur.
Program memory and data memory are explained in this section. Program memory can be read
internally by the user code. The data memory can further be broken down into the general
purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control
the “core” are described here. The SFRs used to control the peripheral modules are described in
the section discussing each individual peripheral module.

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral modules for
controlling the desired operation of the device. These registers are implemented as static RAM.
The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those
registers associated with the core functions are described in detail in this section. Those related to
the operation of the peripheral features are described in detail in the peripheral feature section.
TIMER0 MODULE
The Timer0 module timer/counter has the following features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescale
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock

TIMER1 MODULE
The Timer1 module timer/counter has the following features:
• 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• RESET from CCP module trigger
Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>).

Timer1 Operation in Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized.
The timer continues to increment asynchronous to the internal phase clocks. The timer will
continue to run during SLEEP and can generate an interrupt on overflow, that will wake-up the
processor. However, special precautions in software are needed to read/write the timer. In
Asynchronous Counter mode, Timer1 cannot be used as a time base for capture or compare
operations.

READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L while the timer is running from an external asynchronous
clock will ensure a valid read (taken care of in hardware). However, the user should keep in
mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the
timer may overflow between the reads. For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer
registers, while the register is incrementing. This may produce an unpredictable value in the
timer register. Data in the Timer1 register (TMR1) may become corrupted. Corruption occurs
when the timer enable is turned off at the same instant that a ripple carry occurs in the timer
module. Reading the 16-bit value requires some care. Family Reference Manual (DS33023)
show how to read and write Timer1 when it is running in Asynchronous mode.

Timer1 Oscillator
A crystal oscillator circuit is built between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low
power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. The Timer1 oscillator is identical to the LP oscillator. The user
must provide a software time delay to ensure proper oscillator start-up

Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls
over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow, which is latched in
interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting clearing
TMR1 interrupt enable bit TMR1IE (PIE1<0>).

Resetting Timer1 Using a CCP Trigger Output

If the CCP module is configured in Compare mode to generate a “special event trigger"
signal (CCP1M3:CCP1M0 = 1011), the signal will reset Timer1 and start an A/D conversion (if
the A/D module is enabled). Timer1 must be configured for either Timer or Synchronized
Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter
mode, this RESET operation may not work. In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take precedence. In this mode of operation, the
CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1.
 Since each resonator/crystal has its own characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.The special event
triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
TIMER2 MODULE
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to generate clock shift
Timer2 can be shut-off by clearing control bit TMR2ON (T2CON<2>) to minimize power
consumption.

READING PROGRAM MEMORY

The FLASH Program Memory is readable during normal operation over the entire VDD
range. It is indirectly addressed through Special Function Registers (SFR). Up to 14-bit wide
numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit
ASCII, etc. Executing a program memory location containing data that forms an invalid
instruction results
in a NOP. There are five SFRs used to read the program and memory:
• PMCON1
• PMDATL
• PMDATH
• PMADRL
• PMADRH
The program memory allows word reads. Program memory access allows for checksum
calculation and reading calibration tables. When interfacing to the program memory block, the
PMDATH:PMDATL registers form a two-byte word, which holds the 14-bit data for reads. The
PMADRH:PMADRL registers form a two-byte word, which holds the 13-bit address of the
FLASH location being accessed. This device has up to 2K words of program FLASH, with an
address range from 0h to 07FFh.

CAPTURE/COMPARE/PWM (CCP) MODULE

The CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as :
• 16-bit capture register
• 16-bit compare register
• PWM master/slave duty cycle register.

ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The analog-to-digital (A/D) converter module has five inputs for the PIC16F72. The A/D
allows conversion of an analog input signal to a corresponding 8-bit digital number. The output
of the sample and hold is the input into the converter, which generates the result via successive
approximation. The analog reference voltage is software selectable to either the device’s positive
supply voltage (VDD) or the voltage level on the RA3/AN3/VREF pin. The A/D converter has a
unique feature of being able to operate while the device is in SLEEP mode. To operate in
SLEEP, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. The
A/D module has three registers:
• A/D Result Register ADRES
• A/D Control Register 0 ADCON0
• A/D Control Register 1 ADCON1
A device RESET forces all registers to their RESET state. This forces the A/D module to be
turned off and any conversion is aborted. The ADCON0 register, shown in Register 10-1,
controls the operation of the A/D module. The ADCON1 register, shown in Register 10-2,
configures the functions of the port pins. The port pins can be configured as analog inputs (RA3
can also be a voltage reference) or a digital I/O.

SPECIAL FEATURES OF THE CPU

 These devices have a host of features intended to maximize system reliability, minimize
cost through elimination of external components, provide power saving Operating modes and
offer code protection:

• Oscillator Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial Programming
These devices have a Watchdog Timer, which can be enabled or disabled using a
configuration bit. It runs off its own RC oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to
keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to
keep the part in RESET while the power supply stabilizes, and is enabled or disabled using a
configuration bit. With these two timers on-chip, most applications need no external RESET
circuitry. SLEEP mode is designed to offer a very low current Power-down mode. The user can
wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an
interrupt. Several oscillator options are also made available to allow the part to fit the
application. The RC oscillator option saves system cost while the LP crystal option saves power.
Configuration bits are used to select the desired oscillator mode.

Interrupts
 The PIC16F72 has up to eight sources of interrupt. The interrupt control register
(INTCON) records individual interrupt requests in flag bits. It also has individual and global
interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all
unmasked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will vector immediately. Individual
interrupts can be disabled through their corresponding enable bits in various registers. Individual
interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits the interrupt routine, as well as sets the
GIE bit, which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral
interrupt flags are contained in the Special Function Register, PIR1. The corresponding interrupt
enable bits are contained in Special Function Register, PIE1, and the peripheral interrupt enable
bit is contained in Special Function Register INTCON. When an interrupt is serviced, the GIE bit
is cleared to disable any further interrupt, the return address is pushed onto the stack, and the PC
is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software
before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as
the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction
cycles. The exact latency depends when the interrupt event occurs, relative to the current Q
cycle. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are
set, regardless of the status of their corresponding mask bit, PEIE bit, or the GIE bit.