Proceedings of the Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV 2021).

IEEE Xplore Part Number: CFP21ONG-ART; 978-0-7381-1183-4

Design and Verification of Advanced

2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV) | 978-1-6654-1960-4/20/$31.00 ©2021 IEEE | DOI: 10.1109/ICICV50876.2021.9388549

Microcontroller Bus Architecture-Advanced

Peripheral Bus (AMBA-APB) Protocol

Padmaprabha Jain Satheesh Rao

PG Student, Dept. of ECE Asst. Professor, Dept. of ECE
NMAM Institute of Technology NMAM Institute of Technology
Nitte, India Nitte, India
[email protected] [email protected]

Abstract— Advanced Peripheral Bus (APB) is the piece of has been expanded. Subsequently, time spent in verification
Advanced Microcontroller Bus Architecture (AMBA) family additionally been expanded. System on Chip (SoC)
conventions. It is an easy interface and the arrangement is to correspondence, significantly affects framework execution,
improve the plan for the least possible power intake and power scattering, and time to advertise. Low power dissipation
diminished interface unpredictability. In contrast to AHB, it is a is the main focus for system designer as well as the
Non-Pipelined convention, used to associate low-data transfer researcher’s community. The design of Advanced Peripheral
capacity peripherals to the S oC. The 32-bit model is developed Bus regulator deals the exchanges between the master and
for communication between Master and S lave devices. The slave devices. The APB show relates an indication of progress
Testbench acts as a Master APB and Design acts as a S lave APB.
The Master originates transports on the Peripheral Bus which
to the positive edge of the clock, to improve the joining of
supports Write, Read, and Idle exchanges. It likewise validates
APB peripherals into any arrangement stream. Each move
the most extreme number of slaves. S lave memory reaction takes in any event two cycles. The Master and Slave AMBA
displayed by arrangement. It upholds stand by states utilizing APB (Advanced Peripheral Bus) is an exceptionally adaptable
READY sign additionally bolsters error reaction utilizing and configurable confirmation IP that can be handily
ERROR signal. The fundamental point of the proposed work is coordinated into any SOC check environment. The plan and
to plan and examine the different functional aspect of the usage of APB convention utilizing Verilog Language and
protocol. i.e. information read from a specific system area is the verification utilizing Verilog Testbench.
similar as the information written to the given system area and
In transport based SoC design, the framework incorporates
the protocol verifies the functionality by passing random value to
same indexed address, random value for randomly indexed one or more normal transports to which all modules
address and grouping write and read values together. The system interconnect, and all framework correspondence is overseen
embraced for the proposed work uses Verilog language and by the transport interface conventions [13]. Fig. 1, shows the
Verilog Testbench to extract synthesis, design usage synopsis. AMBA bus Architecture. Fundamentally, it comprises of two
The design utilized Verilog programming which greatly enhances segments in particular namely Advanced high performance
reusability of the Testbench components such as creating Tasks bus (AHB), or Advanced System bus (ASB) and Advanced
for various Test cases. peripheral bus (APB). So the parts requiring higher
transmission capacity like Higher information transmission
Keywords—AMBA, APB, S oC, Verilog, Design, Verification. rate, High- performance processors, High Bandwidth system
Interface, and Direct Memory Access transport pro are related
with the AHB or ASB. AMBA APB is low bandwidth and low
I. INT RODUCT ION execution transport. Subsequently, the sections requiring
The immense advancement of VLSI innovation empowers lower move speed like the periphery contraptions, for
the coordination of millions of semiconductors on a solitary instance, devices are related with the APB. [14] These
chip called System on chip (SoC). The absolute Design and peripherals are associated independently dependent on various
Verification of AMBA APB Protocol for SoC Applications data transmission with an extension as the medium.
are performed. AMBA Bus essentially has a large number of
components like AHB, ASB and AXI, and so forth which are
elite transports used to interface with low-performance
execution transports like APB. APB uses low peripheral
bandwidth and is used to connect with slaves like UART,
TIMER, Keypad and INTERRUPT CONTROLLER etc.
The traditional way of verification is simulation-based. As
the innovation in technology improved unpredictability of IC's

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 Proceedings of the Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV 2021).
IEEE Xplore Part Number: CFP21ONG-ART; 978-0-7381-1183-4

Random Universal Time

slave and APB ace interfaces and supports up to 16 APB
ARM Processor
Access Asynchronous Manage peripherals. The READY sign which means sit tight for states
Memory Transmitter/ ment
Receiver System
on AXI and a blunder on any exchange brings about SLVERR
as the AXI read/compose a reaction.
Memory B Muhammad Hafeez, et.al.,[8] proposed IP center to get
Interface R information from a solitary slave and proficient APBSPI
I regulator with adaptable information width and recurrence.
D The SPI is duplicated by ModelSim, QuartusLite 16, and will
G be incorporated to convey the gdsii record for tape out. The
Direct Memory Access Bus E Keypad Peripheral discoveries of the SPI interface to send or get information
Input/ Output
Master from a solitary slave and proficient APB-SPI regulator with
adaptable information width and recurrence are demonstrated
for a most extreme recurrence of 16 MHz.
Fig. 2, AMBA Bus Architecture diagram.

II. LIT ERAT URE SURVEY A. Summary of the Literature Survey

The AHB2APB connection has been synthesized by
performing extraction of synthesized netlist with proper delays The modern SOC design contains many IP cores with different
and confirmed by correlating the gate extent simulation [1]. communication protocols [11]. The growing unpredictability
Functional correctness of the protocol is verified using of Systems-on-Chip (SOC) has actuated the fundamental "plan
Verilog, System Verilog and UVM (universal verification efficiency hole" issue [6]. On-chip correspondence designs
methodology) [2]. significantly affect system performance, execution, power
dispersal, and time-to-showcase [1]. The ARM created
N. Bobade, et.al.,[3] proposed APB protocol and its slave Advanced Microcontroller Bus Architecture (AMBA)
verification, The plan has dealt with the harmony between
interlinks convention. AMBA bus protocol has become the de
zone overhead and speed. The read-compose activity is
cultivated with zero stands by states from the outer ROM and facto standard SoC bus [7]. It also helps to design the
the compose activity with zero states to the outside RAM. embedded processors who possess one or more CPUs and
several peripherals [15]. What’s more, it is the true business -
M. Kiran Kumar, et.al.,[4] proposed clock skew minimization standard on-chip interconnects detail that fills in as a system
technique for AMBA APB connect which portrays both for SoC plans, successfully giving the "computerized stick"
transport determination and an innovation autonomous that ties IP measures together. It is additionally the foundation
technique for planning, actualizing and testing altered high - of ARM's plan reuse procedure. AMBA determines a pecking
joining installed interfaces. [10] Clock skew minimization has order of transport types, custom-made to contrasting needs
been proposed for the better operation of the APB Bridge. The found across the interconnect construction of SoC plans [9].
design of protocol in Xilinx VIVADO IDE tool for synthesis System designers, as well as the research community, have
and simulation and verified the APB Bridge with one master focused on the issue of exploring, evaluating, and designing
and two slaves. SOC communication architectures to meet the targeted design
objectives. System on-chips (SoCs) plans are moving towards
Kiran Rawat, et.al.,[5] proposed RTL Implementation for nanometer reaches and it watches out for more modest
AMBA ASB APB protocol at System on Chip (SoC) level. the element measures now-a-days [10]. Improving the bridging
synthesis and simulation of the complex interface between and signal translation between these protocols has become a
AMBA ASB and APB are performed. The Design can critical factor for the performance of the whole system [11].
accomplish RTL perspectives on the ASB APB module at the
System on chip level. Additionally, the power report shows These may cause the presentation of higher plan complexities
the enhanced design of each plan.
in the new plan to draw near. The complexities likewise will
Roopa. M, et.al.,[6] proposed the plan of low data transfer in general expand the power utilization of the actualized plans.
capacity peripherals utilizing superior transport engineering. Along these lines, the principle assignment of the plan
The plan of the APB regulator handles the exchanges between engineer is to comprehend and accomplish the right usage of
the expert and bus peripherals. Advanced Peripheral Bus the force of the SoC parts. Low power configuration
convention planned with low transmission capacity slave approaches are proposed for better plan execution. APB can
devices. The peruse and compose activity is done with slave also be used to access the programmable control registers of
devices and constrained by APB Controller. Two transport the peripheral devices [12]. The APB convention relates a sign
cycles are needed to complete peruse or compose exchange, change to the rising edge of the clock, to improve the
when select line selects particular slave. combination of APB peripherals into any plan stream [4].
Chenghai Ma, et.al.,[7] proposed design and Each move takes in any event two cycles. A solid on -chip
implementation of APB bridge which translates the AXI4.0- correspondence standard is an unquestionable requirement in
lite transactions into APB 4.0 transactions. The extension any SOC [6]. The AMBA 2.0 APB is a peripheral transport
gives interfaces between the elite AXI transport and the low- standard for low data transfer capacity peripheral. The APB
power APB area. The component incorporates 32-cycle AXI transport is planned to utilize the Verilog HDL, as indicated

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 Proceedings of the Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV 2021).
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by the detail, and is checked to utilize Verilog Testbench for IV. APB OPERAT ING ST AT US
all the usefulness of the convention. Fig. 3, Shows the operating status of an APB which
represent the activity of peripherals. It operates in three states.
III. APB BLOCK DIAGRAM
APB is a part of the AMBA Hierarchy Bus and it is x IDLE: This will be the default state where there is no
utilized to associate with the low peripheral devices. AMBA transfer of data.
APB as a rule comprises of APB Bridge/expert and APB slave x SETUP: Inside this state suitable Select signal is
and it tends to be utilized to interface with numerous affirmed, transport remains in the SETUP state for only
quantities of slaves. Fig. 2, shows the block graph of APB one clock cycle and will consistently move to the
connect/Master and APB slave. APB Bridge is simply a ENABLE state for next positive edge of the clock.
transport ace on AMBA APB. What's more, the APB Bridge is
additionally a slave on the elevated level system transport. x ENABLE/ACCESS: In this state, when select input is
up and write signal is also up, and ready signal is also
Select 1
up then Master wants to write data into the slave
devices, after that transaction ready signal goes low,
System
Select 2
indicating slave is not ready to take further transfer. If
Bus
ready signal is up but select signal is low and write
. signal is low then no transfer take place, bus remain in
.
wait state. For next clock cycle, ready signal is up and
Select N SLAVE
select signal also and write is equal to one, which
MASTER Advanced indicates that read operation can perform. Master
Read
data
Advanced Enable Peripheral reads data from slave devices from specified memory
Peripheral B us Read
Data
area.
B us
Address

Reset
Write
IDLE No
select=0 Transfer
enable=0
Write Data

Ready
Clock Ready=1
& No
Error Transfer
Ready=1 & Transfer
SETUP
select=1
Fig. 2, Interfacing of APB Master and Slave enable=0

A. APB Master Description Ready=0

The Master originates transports on the Peripheral Bus
which supports Write, Read, and Idle exchanges. It likewise ACCESS
select=1
validates the most extreme number of slaves. APB Bridge enable=1
changes over the information and addresses from System
transport move to APB and execution the accompanying Fig. 3, APB Operating Status
capacities. Hook the location and holds it legitimate all
through the exchange. Translates the location and produces a V. VERIFICAT ION ST RAT EGY FOR APB
fringe select, Select. Only one select sign can be dynamic
Confirmation, i.e. verification is the significant component
during an exchange. It drives the information onto APB for
in the VLSI innovation. Since it is utilized to discover the
composing the move. It drives the APB information onto the
bugs in the RTL plan at the most punctual stage so the overall
system transport for a read move.
design should not to demonstrate damaging. Hence the
Testbench created using Verilog for the APB design. The
B. APB Slave Description principle reason for creating verification environment is to
APB Slave has a basic, yet adaptable interface and it tends generate the stimulus to DUT (design under test), and check
to be utilized to interface numerous slaves and ensuing the outcomes to check that the work is right. this demonstrates
capacities. When the positive edge of clock, when select sign what slave peripheral is chosen for data move. The RTL
is up and enable is also up, the address address, and the write verification design flow is shown in Fig. 4.
signal is also up, write can be consolidated to figure out which
register ought to be refreshed by the write activity. For reading
exchanges, the information can be driven onto the information
bus when the write signal is low, and both select and enable
are HIGH. While PADDR is utilized to figure out which
register ought to be perused.

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 Proceedings of the Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV 2021).
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Customer Requirement

Specification

Design & Development

Failure mode
analysis
Fig. 5, APB Write Cycle
Fabrication

B. Read Cycle
Fig. 6, shows APB Read cycle. The read move begins with
Manufacturing & Testing
the sign reset, address (addr), read information (rdata),
Faulty Chip
compose signal (WR), select sign (sel) and prepared sign
Good chip to customer
(ready). All sign changing after the positive edge of the clock.
When reset is high all signals goes to low and ready signal
Fig. 4, VLSI verification design flow (pready) will be high after reset, ready signal waits for the
command. Once command comes, that means sel=1, wr=0 and
VI. APB SIGNAL DESCRIPT ION ready=1 that indicates to slave for read transfer. For next cycle
ready goes to low to indicate slave is not ready. Following
cycle ready goes to up and master reads data (rdata) from
AMBA APB signals and its description is shown in Table
I. slave along with ready=1.

TABLE I. LIST OF SIGNALS AND ITS DESCRIP TION

SIGNALS DESCRIPTIO N

Clock (clk) For positive edge clock all signs changes.

Reset (reset) Dynamic high reset signal.

Address Address bus can be 4 bits or 8 bits wide.
(addr) Fig. 6, APB Read Cycle
Selectsignal Select. Each slave device has a this signal, this
(sel) demonstrates what slave gadget is chosen for information
move. C. Error Cycle
Write (wr) Direction. This signal high indicates a write access when it Signal Error (mistake) to demonstrate a mistake condition
is low indicates read access.
Writedata T his can be 32 bits wide and is driven by the fringe on an exchange. Mistake conditions can occur on any
(wdata) transport unit during compose cycles when wdata is high. transactions, i.e., read and write. For both transactions when
Ready T he slave utilizes this sign to expand an exchange. command sel is high for more than one clock cycle then error
(ready) signal goes high as shown in Fig. 7. When a write transaction
ReadData T he chose slave drives this transport during read cycles receives an error this does not mean that the register within the
(rdata) when wr is low T his transport is 32-bits wide. peripheral has not been refreshed. Read transactions that
Error (error) T his sign shows an exchange disappointment.
receive an error can return invalid data. There is no
prerequisite for the peripheral to drive the information bus to
each of the 0s for a read mistake. If the address overflows then
VII. RESULT AND DISCUSSION protocol shows error as shown in Fig. 8.

A. Write Cycle
Fig. 5, shows APB Write cycle. The first clock cycle reset
goes to high which clears all the signals, Ready signal
(pready) is high after reset. When a command comes Ready
signal (pready) goes to low to indicate that Slave is not ready.
After a clock Ready signal goes to high indicate that slave is
ready for next command. When sel signal (sel), write signal
(wr), write data (wdata) is high and ready signal is also up
then master will start writing into the slave. Once writing is Fig. 7, APB Error Cycle when select signal repeats for two cycles
done the select signal (sel) goes to low and Ready signal
(pready) also goes to low to indicate that Slave is not ready for
next command.

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 Proceedings of the Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV 2021).
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location. Fig. 11. Shows the protocol verifies functionality by

passing random value to random indexed address.

Fig. 8, APB Error Cycle when address overflows

D. Functional Verification
Fig. 11, APB Protocol Functional Verification- Random Value and
The functional correctness of the protocol is performed for Random Index
four parameters.
The information read from a specific memory area is the
same as the information written to the given memory area The functional verification is performed and the write data
shown in Fig. 9. In addition to that protocol verifies and a read data from a specific memory area are grouping
functionality by passing random value to same indexed together as shown in the Fig. 12.
address shown in Fig. 10. Together it checks functionality by
passing random value to random index shown in Fig. 11. Also
verifies the protocol by grouping write and read value shown
in Fig. 12.

Fig. 12, APB Protocol Functional Verification Grouping Write and Read
Values

Fig. 9, APB Protocol Functional Verification

CONCLUSION
The Advanced Peripheral Bus protocol is designed
Functional verification is similar to the above procedure utilizing the Verilog programming language and utilizing
adding to that value inserting to the slave by random fashion. Verilog Testbench for verification purpose. The benefits of
The random value generated using $random command and Verilog HDL programming is that it can significantly improve
inserted to the particular memory location. Fig. 10. Shows the the reusability of testbench segments, such as creating Tasks
protocol verifies functionality by passing rando m value to for different test cases. The upside of Verilog writing
same indexed address. computer programs is that it can significantly improve the
reusability of testbench segments, The interface is used to join
the DUT and the Verilog Testbench which includes the test
program. Testbench verifies for Write cycle, Read cycle and
Error cycle and total functionality of protocol for four
different parameters. Test cases covers for Read cycle, Write
cycle, Error cycle, functional correctness of the protocol by
Random value passing with same index, Random value
passing with Random index verification, grouping write value
and read value together and Self error checking blocks. The
reenactment results indicates that the information read from a
specific system area is similar as the information kept in touch
Fig. 10, APB Protocol Functional Verification- Random Value Passing
with the given memory area. Consequently, the design is
practically right. The AMBA APB design and verification is
Functional verification is similar to the above procedure performed using Xilinx ISE Design tool. Future work
adding to that value inserting to the slave by random fashion incorporates power advancement procedures can be app lied
to random address location. The random value generated using for different parts of APB modules, which significantly
$random command and inserted to the particular memory upgrades generally exhibitions of the transport convention.

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