A COMPARITIVE STUDY AMONG

LECTOR, LCNT AND ONOFIC BASED

APPROACHES FOR LEAKAGE POWER
REDUCTION
Abstract c) GIDL and GIBL leakage currents: it is
caused by high electric field induced by gate
potential, in gate drain overlap region.
d)Gate oxide Tunneling current: if there is high
Introduction electric field across a thin gate oxide layer, this
leakage occurs.
With the progress of research in the field of
The short circuit power dissipation is caused
CMOS Technology, an increased number of
due to short circuit between the pull up and
transistors on a single die with better
pull-down network.
performance is the need of the hour. More
number of transistors on a single chip allows Due to decrease in transistor size it is mainly
the manufacturers to accommodate more the static power dissipation that increases (the
components in a single package which further sub threshold and gate oxide tunneling leakage
decreases its cost too. To aid this integration current increase).
the size of the transistor has to be made small In this paper we compare the techniques used to
which leads to high power dissipation. Now a reduce power leakage which are LECTOR
days the demand of portable devices like smart technique, LCNT technique and ONOFIC
phones, tablets, laptops has increased technique.
drastically. More power dissipation causes
heating up of the system which as a result
reduces its performance, durability and
reliability. Hence low power designing has
RELATED WORK
come into picture.
LECTOR Technique: In this technique we
The power consumption is given by:
connect the pull up and pull-down network by
P(total)= P(dynamic)+P (short circuit) two transistors (leakage control transistors)
+P(switching)+P(static) within logic blocks. We use NMOS for pull
down network and PMOS for pull up network.
Dynamic power dissipation occurs when the The basic concept behind this technique is
MOS transistor switches to charge and stacking of transistors from supply voltage to
discharge the output load capacitance at a ground. The gate terminal of the transistor is
particular node (that is mainly due to the controlled by the source terminal of the LCT.
switching activity). The circuit is as shown below:

The major components of static power are:

a) Reverse biased pn-junction leakage current:

it is caused due to the minority carrier diffusion
and drift near the depletion region.
b) Sub threshold leakage: weak inversion
current between source and drain in MOS
transistor, which occurs when gate voltage is
lower than threshold voltage.
 LCNT Technique: In this technique two NMOS
leakage control transistors are inserted
between the pull up and pull-down networks.
The gate terminal of both leakage control
terminals (LCT1 & LCT2) are linked to node
NP which is output node.
WORK DONE IN THIS PAPER

INVERTER: CMOS inverter is used to generate

logic functions in the circuit. Here we have
shown how power reduction can be done by
lector and ONOFIC and LCANT techniques in
the following circuit layouts. In lector
technique we introduce a LCT ‘s between
NMOS and a PMOS. In ONOFIC technique a
ONOFIC block is introduced between the
NMOS and the PMOS. And lastly in LCNT
technique two NMOS transistors are
introduced between NMOS and PMOS.

ONOFIC Technique: In this technique we

employ an extra logic block called the
ONOFIC block. In this block a NMOS and
PMOS are connected in such a way so that the
block is either on or off irrespective of the
input. In ON condition the block provides a
conducting path while in OFF condition it has
very high impedance so it blocks the path.
 4. XOR Conventional 2.2027E-09 117.32

Proposed 2.0766E-09 291.70

LCNT 2.0595E-09 332.54

LECTOR 2.0239E-09 709.52

5. XNOR Conventional 2.4391E-09 190.41

Proposed 2.3063E-09 461.66

LCNT 2.8821E-09 619.03

LECTOR 2.2540E-09 992.34

We have also implemented the NAND NOR

XNOR and XOR logic using all three techniques
and further compared the results.

Results and Discussion

The following table shows the comparison for
22nm technology
The following table shows the comparison of
S. Logic Technique Total Power Delay (PS)
the techniques for 130nm technology No. Circuits Used Dissipation (Watt)

S. Logic Technique Total Power Delay (PS)

No. Circuits Used Dissipation (Watt)
1. INVERTER Conventional 8.5003E-09 21.28

Proposed 2.6510E-09 9.888

1. INVERTER Conventional 774.1975E-12 26.4818
LCNT 3.4110E-09 98.609
Proposed 668.7475E-12 57.388
LECTOR 3.5338E-09 147.51
LCNT 668.7473E-12 64.152

2. NAND Conventional 9.1103E-09 136.69

LECTOR 678.1566E-12 4.0723
Proposed 4.6357E-09 299.77
2. NAND Conventional 236.4163E-12 97.983

LCNT 5.2848E-09 115.96

Proposed 229.7137E-12 192.931

LECTOR 5.4689E-09 186.26

LCNT 229.7137E-12 175.400

3. NOR Conventional 1.6982E-08 7.2031

LECTOR 229.3317E-12 117.140

Proposed 5.0486E-09 196.70

3. NOR Conventional 1.5484E-09 26.4818
LCNT 6.3727E-09 131.70
Proposed 1.3162E-09 57.388

LECTOR 6.7398E-09 72.899

LCNT 1.3162E-09 64.152
4. XOR Conventional 9.1816E-08 87.175
LECTOR 1.3369E-09 4.0723
 Proposed 3.5998E-08 41.084Following
is the graphical representation of
delay results for 22 nm technology.
LCNT 7.9502E-08 120.48

LECTOR 7.5925E-08 226.71

5. XNOR Conventional 1.0204E-07 161.00

Proposed 6.4428E-09 272.52

LCNT 8.5074E-08 431.93

LECTOR 8.0593E-08 397.75

Following is the graphical representation of

power results of22nm technology.

Following is the graphical representation of

power results for 130nm technology.

Following are the delay results for 22nm

technology.

Conclusion

Conclusion
Lately Power reduction has become a
major feature. The work presents a
comparison between the different
techniques. From the results we can infer
that the ONOFIC technique is the best for
power reduction. These techniques are also
very easy to implement as they just need
two extra transistors with same threshold
voltage.