VBIT COURSE MATERIAL VLSI DESIGN-2019

UNIT – II
VLSI CIRCUIT DESIGN
PROCESSES: VLSI Design Flow,
MOS Layers, Stick Diagrams, Design
Rules and Layout, 2μm CMOS
Design rules for wires, Contacts and
Transistors Layout Diagrams for
NMOS and CMOS Inverters and
Gates, Scaling of MOS circuits.

VLSI DESIGN VIDYA SAGAR P

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VLSI Design Flow :

The major steps in the design of VLSI chip are shown in the figure. The starting point of a
VLSI design is the systems specification. At this point the product is defined in both
general and specific terms that provide design targets such as functions, speed, size, etc.,
for the entire project. This is the ‘Top’ level of the design hierarchy. The system
specifications are used to create an obstruct, high level model. Digital design is usually
based on some type of Hardware Description Language (HDL) that allows abstract
modeling of the operation. VHDL and verilog are the most common HDLS in practice. The
abstract model contains information on the behaviour of each block and the interaction
among the blocks in the system. The model is subjected to extensive verification steps
where the design is checked and rechecked to ensure that it is correct.
VLSI design style mainly uses three domains of design description, viz. the behavioral, the
description of the function of the design; the structural, the description of the form of the
implementation; and the physical, and the description of the physical implementation of
the design. There are many possible representations of a circuit in each description, and
judicious choice of representations is important in tool design.
A simplified view of design flow is shown in Fig. Regardless of the actual size of the project,
the basic principles of structured design will improve the prospects of success.
1.System Specification:
 The first step of any design process is to lay down the specifications of the system.
System specification is a high level representation of the system. The factors to be
considered in this process include: performance, functionality, and physical dimensions
(size of the die (chip)). The fabrication technology and design techniques are also
considered.
 The specification of a system is a compromise between market requirements,
technology and economical viability. The end results are specifications for the size,
speed, power, and functionality of the VLSI system.
2. Architectural Design:
 The basic architecture of the system is designed in this step. This includes, such
decisions as RISC (Reduced Instruction Set Computer) versus CISC (Complex Instruction
Set Computer), number of ALUs, Floating Point units, number and structure of pipelines,
and size of caches among others.
The outcome of architectural design is a Micro-Architectural Specification (MAS).
While MAS is a textual (English like) description, architects can accurately predict the
performance, power and die size of the design based on such a description.
3. Behavioral or Functional Design:
 In this step, main functional units of the system are identified. This also identifies the
interconnect requirements between the units. The area, power, and other parameters of
each unit are estimated.
 The behavioral aspects of the system are considered without implementation specific
information. For example, it may specify that a multiplication is required, but exactly in
which mode such multiplication may be executed is not specified. We may use a variety
of multiplication hardware depending on the speed and word size requirements. The
key idea is to specify behavior, in terms of input, output and timing of each unit,
without specifying its internal structure.

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 The outcome of functional design is usually a timing diagram or other relationships

between units. This information leads to improvement of the overall design process and
reduction of the complexity of subsequent phases. Functional or behavioral design
provides quick emulation of the system and allows fast debugging of the full system.
Behavioral design is largely a manual step with little or no automation help available.

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4. Logic Design:
 In this step the control flow, word widths, register allocation, arithmetic operations,
and logic operations of the design that represent the functional design are derived and
tested.
 This description is called Register Transfer Level (RTL) description. RTL is expressed in
a Hardware Description Language (HDL), such as VHDL or Verilog. This description
can be used in simulation and verification. This description consists of Boolean
expressions and timing information. The Boolean expressions are minimized to achieve
the smallest logic design which conforms to the functional design. This logic design of
the system is simulated and tested to verify its correctness. In some special cases, logic
design can be automated using high level synthesis tools. These tools produce a RTL
description from a behavioral description of the design.
5. Circuit Design:
 The purpose of circuit design is to develop a circuit representation based on the logic
design. The Boolean expressions are converted into a circuit representation by taking
into consideration the speed and power requirements of the original design. Circuit
Simulation is used to verify the correctness and timing of each component.
 The circuit design is usually expressed in a detailed circuit diagram. This diagram shows
the circuit elements (cells, macros, gates, transistors) and interconnection between these
elements. This representation is also called a netlist. Tools used to manually enter such
description are called schematic capture tools. In many cases, a netlist can be created
automatically from logic (RTL) description by using logic synthesis tools.
6. Physical Design:
 In this step the circuit representation (or netlist) is converted into a geometric
representation. As stated earlier, this geometric representation of a circuit is called
a layout. Layout is created by converting each logic component (cells, macros, gates,
transistors) into a geometric representation (specific shapes in multiple layers), which
perform the intended logic function of the corresponding component. Connections
between different components are also expressed as geometric patterns typically lines in
multiple layers.
 The exact details of the layout also depend on design rules, which are guidelines based
on the limitations of the fabrication process and the electrical properties of the
fabrication materials. Physical design is a very complex process and therefore it is
usually broken down into various sub-steps. Various verification and validation checks
are performed on the layout during physical design.
 In many cases, physical design can be completely or partially automated and layout can
be generated directly from netlist by Layout Synthesis tools. Layout synthesis tools,
while fast, do have an area and performance penalty, which limit their use to some
designs. Manual layout, while slow and manually intensive, does have better area and
performance as compared to synthesized layout. However this advantage may dissipate
as larger and larger designs may undermine human capability to comprehend and
obtain globally optimized solutions.
7. Fabrication:
 After layout and verification, the design is ready for fabrication. Since layout data is
typically sent to fabrication on a tape, the event of release of data is called Tape Out.

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 Layout data is converted (or fractured) into photo-lithographic masks, one for each
layer. Masks identify spaces on the wafer, where certain materials need to be deposited,
diffused or even removed. Silicon crystals are grown and sliced to produce wafers.
Extremely small dimensions of VLSI devices require that the wafers be polished to near
perfection. The fabrication process consists of several steps involving deposition, and
diffusion of various materials on the wafer. During each step one mask is used. Several
dozen masks may be used to complete the fabrication process.
A large wafer is 20 cm (8 inch) in diameter and can be used to produce hundreds of
chips, depending of the size of the chip. Before the chip is mass produced, a prototype is
made and tested. Industry is rapidly moving towards a 30 cm (12 inch) wafer allowing
even more chips per wafer leading to lower cost per chip.
8. Packaging, Testing and Debugging:
 Finally, the wafer is fabricated and diced into individual chips in a fabrication facility.
Each chip is then packaged and tested to ensure that it meets all the design
specifications and that it functions properly. Chips used in Printed Circuit Boards
(PCBs) are packaged in Dual In-line Package (DIP), Pin Grid Array (PGA), Ball Grid
Array (BGA), and Quad Flat Package (QFP). Chips used in Multi-Chip Modules (MCM)
are not packaged, since MCMs use bare or naked chips.
MOS layers :
MOS circuits are formed on four basic layers:
o N-diffusion
o P-diffusion
o Polysilicon
o Metal
These layers are isolated by one another by thick or thin silicon dioxide insulating layers.
Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel.

Ox3

Via
Metal2

Ox2
Active contact
Metal1

Ox1

n+ n+ n+ n+ Poly Si

P-substrate

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Stick Diagrams:
VLSI design aims to translate circuit concepts onto silicon, stick diagrams are a means of
capturing topography and layer information - simple diagrams, Stick diagrams convey
layer information through color codes .A stick diagram is like a layout Contains the basic
topology of the circuit, each wire is assigned a color (layer) Crossing wires must be on
different layers. Wires are drawn as sticks with no width. The size of the object is not to
scale.
Stick diagrams are Cartoon of a layout. Shows all components. Does not show exact
placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of
compliance with layout or design rules.
Useful for interconnect visualization, preliminary layout compaction, power/ground
routing, etc.

layer color stick notation color code

n-diffusion Green

p-diffusion yellow

polysilicon red

metal-1 blue

metal-2 dark blue or purple

contact cut black

via black
demarcation line --------------------------- brown

Buried Contact green

Rule 1. When two or more ‘sticks’ of the same type cross or touch each other that
represents electrical contact.

Rule 2: When two or more ‘sticks’ of different type cross or touch each other there is no
electrical contact. (If electrical contact is needed we have to show the connection
explicitly).

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Rule 3. When a poly crosses diffusion it represents MOSFET. If contact is shown it is not
transistor.
nMOSFET pMOSFET nMOSFET Depletion Mode

Rule 4.
In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS
must lie on one side of the line and all nMOS will have to be on the other side.

When polysilicon crosses n-diffusion a transistor forms, when poly (red) crosses
diffusion (green or yellow).

Nmos enhancement transistor Nmos depletion transistor

nMos Invrter :

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Stick diagram for O3AI and estimate area

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F=(AB+AC+BC)’ = (AB + C(A+B))’

BiCmos inverter:

Encodings for NMOS process:

Figure 1: NMOS encodings

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Figure shows the way of representing different layers in stick diagram notation and mask layout
using nmos style.Figure l shows when a n-transistor is formed: a transistor is formed when a
green line (n+ diffusion) crosses a red line (poly) completely. Figure also shows how a depletion
mode transistor is represented in the stick format.
Encodings for CMOS process:

Figure 2 shows when a n-transistor is formed: a transistor is formed when a green line
(n+ diffusion) crosses a red line (poly) completely. Figure 2 also shows when a p-
transistor is formed: a transistor is formed when a yellow line (p+ diffusion) crosses a
red line (poly) completely.
Encoding for BJT and MOSFETs:

Figure 3: Bi CMOS encodings.

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LAYOUT DESIGN RULES:

The design rules are formed to translate the circuit design concepts, (usually in stick
diagram or symbolic form) into actual geometry in silicon.
The physical mask layout of any circuit to be manufactured using a particular process
must conform to a set of geometric constraints or rules, which are generally called
layout design rules. These rules usually specify the minimum allowable line widths for
physical objects on-chip such as metal and polysilicon interconnects or diffusion areas,
minimum feature dimensions, and minimum allowable separations between two such
features. If a metal line width is made too small, for example, it is possible for the line
to break during the fabrication process or afterwards, resulting in an open circuit. If
two lines are placed too close to each other in the layout, they may form an unwanted
short circuit by merging during or after the fabrication process.

The main objective of design rules is to achieve a high overall yield and reliability while
using the smallest possible silicon area, for any circuit to be manufactured with a
particular process.

The design rules are usually described in two ways:

1. Absolute Design Rules (Micron rules e.g. μ-based design rules):
In this approach, the design rules are expressed in absolute dimensions (e.g.0.75μm
micrometers or nano meters) and therefore can exploit the features of a given process
to a maximum degree.
2. Scalable Design Rules (e.g. SCMOS, λ-based design rules): The MOSIS rules are
defined in terms of a single parameter λ.
The rules are so chosen that a design can be easily ported over a cross section of
industrial process, making the layout portable. Scaling can be easily done by simply
changing the value.
Well Rules The n-well is usually a deeper implant (especially a deep n-well) than the
transistor source/drain implants, and therefore, it is necessary for the outside
dimension to provide sufficient clearance between the n-well edges and the adjacent n+
diffusions. The inside clearance is determined by the transition of the field oxide across
the well boundary.
Mask Summary The masks encountered for well specification may include n-well, p-
well, and deep n-well. These are used to specify where the various wells are to be
placed. Often only one well is specified in a twin-well process (i.e., n-well) and by
default the p-well is in areas where the n-well isn't.
Design rules for the diffusion layers and metal layers:
Metal Rules: Metal spacing may vary with the width of the metal line (so called fat-
metal rules). That is, above some metal wire width, the minimum spacing may be
increased. This is due to etch characteristics of small versus large metal wires.

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Figure shows the design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n
and p diffusion lines is having a minimum width of 2λ and a minimum spacing of 3λ.
Similarly it shows for other layers.
Mask Summary: Metal rules may be complicated by varying spacing dependent on
width: As the width increases, the spacing increases. Metal overlap over contact might
be zero or nonzero.

Transistor Design Rules:

CMOS transistors are generally defined by at least four physical masks. These are active
(also called diffusion, diff, or thinox), n-select (also called n-implant, nimp, or nplus),
p-select (also called p-implant, pimp, or pplus) and polysilicon (also called poly or
polyg). The active mask defines all areas where either n- or p-type diffusion is to be
placed or where the gates of transistors are to be placed. The select layers define what
type of diffusion is required, n-select surrounds active regions where n-type diffusion is
required, p-select surrounds areas where p-type diffusion is required, n-diffusion areas
inside p-well regions define nMOS transistors (or n-diffusion wires), n-diffusion areas
inside n-well regions define n-well contacts, p-diffusion areas inside n-wells define
pMOS transistors (or p-diffusion wires), p-diffusion areas inside p-wells define
substrate contacts (or p-well contacts).

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Figure shows the design rule for the transistor, and it also shows that the poly should
extend for a minimum of 2λ beyond the diffusion boundaries. (gate over hang distance)
Mask Summary: The basic masks (in addition to well masks) used to define
transistors, diffusion interconnect (possibly resistors), and gate interconnect are active,
n-select, p-select, and polysilicon. These may be called different names in some
processes. Sometimes n-diffusion (ndiff) and p-diffusion (pdiff) masks are used to
alleviate designer confusion.

Contact Rules: There are several generally available contacts:

Metal to p-active (p-diffusion)
Metal to n-active (n-diffusion)
Metal to polysilicon
Metal to well or substrate
Depending on the process, other contacts such as buried polysilicon-active contacts
may be allowed for local interconnect. Because the substrate is divided into well
regions, each isolated well must be tied to the appropriate supply voltage; that is, the n-
well must be tied to VDD and the substrate or p-well must be tied to GND with well or
substrate contacts. Metal makes a poor connection to the lightly doped substrate or
well. Hence, a heavily doped active region is placed beneath the contact.
A split or merged contact is equivalent to two adjacent contacts to n-active and p-
active strapped together with metal. This structure is used to tie transistor sources to
the substrate or n-well and simultaneously to GND or VDD. Whenever possible, use
more than one contact at each connection. This significantly improves yield in many
processes because the connection is still made if one of the contacts is malformed.
Mask Summary: The only mask involved with contacts to active or poly is the contact
mask, commonly called CONT Contacts are normally of uniform size.

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Via Rules: VIA is used to connect higher level metals from metal1 connection.
Processes may vary in whether they allow stackedVias to be placed over polysilicon and
diffusion regions. Some processes allow vias to be placed within these areas, but do not
allow the vias to straddle the boundary of polysilicon or diffusion.
Contact Cuts:
While making contacts between poly-silicon and diffusion in nMOS circuits it should
be remembered that there are three possible approaches—1.poly to metal then metal to
diff.
2. Buried contact poly to diff.
3. Butting contact (poly. to diff. using metal).
Among the three the latter two, the buried contact is the most widely used, because of
advantage in space and a reliable contact. At one time butting contacts were widely
used, but now a days they are superseded by buried contacts.
Other Rules: The passivation or overglass layer is a protective layer of Si02 (glass)
that covers the final chip. Appropriately sized openings are required at pads and any
internal test points. Some additional rules that might be present in some processes are
as follows:
Extension of polysilicon in the direction that metal wires exit a contact.
Extension of metal end-of-line region beyond a via.

Differing pMOS and nMOS gate lengths.

Differing gate poly extensions depending on the device length or the device
construction.

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MOSIS Scalable CMOS Design Rules: Academic designs often use the λ-based
scalable CMOS design rules from MOSIS because they are simple and freely available,
and they allow designs to easily migrate from one process to another. These advantages
come at the expense of being conservative because they must work for all
manufacturing processes.
MOSIS actually has three sets of rules: SCMOS, SUBM, and DEEP.
The SUBM rules are somewhat more conservative than SCMOS rules. DEEP rules are
even more conservative. The more conservative rules allow you to use a slightly smaller
value of λ while still satisfying all of the micron design rules for a process.
Table 2 lists some of the foundry processes MOSIS has offered and the associate value
of λ for the different rule sets. For example, the AMI 0.5 µm process can use the
SCMOS rules with λ = 0.35 µm or the SUBM rules with λ = 0.30 µm. SUBM rules are a
good choice for class projects because they are somewhat easier to use than DEEP (no
half-λ rules), while still being compatible with most processes. Some processes offer a
second polysilicon layer for floating-gate transistors and poly-insulator-poly capacitors
used in analog circuits.

For design rules where the minimum drawn gate length exceeds the feature size,
MOSIS applies a polysilicon bias to shrink the gates by a uniform amount before masks
are made.
For example, in the SUBM rules for the AMI 0.5 µm process with λ = 0.3 µm, a bias of-
0.1 µm is applied to all polysilicon. Thus, a 2 λ transistor gate is 0.5 µm rather than 0.6
µm and a 4 λ gate is 1.1 µm rather than 1.2 µm.

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CMOS Lambda-based Design Rules:

The CMOS fabrication process is more complex than nMOS fabrication. In a CMOS
process, there are nearly 100 actual set of industrial design rules. The additional rules
are concerned with those features unique to p-well CMOS, such as the p-well and p+
mask and the special 'substrate' contacts. The p-well rules are shown in the diagram
below.

In the diagram above each of the arrangements can be merged into single split
contacts.

From the above diagram it is also clear that split contacts may also be made with
separate cuts.

Fig. Particular rules for p-well CMOS Process.

The CMOS rules are designed based on the extensions of the Mead and Conway
concepts and also by excluding the butting and buried contacts.

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General Observations on the Design Rules:

The microscopic dimensions of Silicon circuits always cause some problems in the
design process. The major problem is presented by possible deviation in line widths
and in interlayer registration. If the line widths are too small, it is possible for lines to
be discontinuous in places. If separate paths in a layer are placed too close together, it
is possible that they will merge in places or interfere with each other.
For the lambda-based rules , the design rules are formulated in terms of a length unit λ
which is related to the resolution of the process λ may be viewed as a limit on the width
deviation of a feature from its ideal 'as drawn' size and also as a bound on the
maximum misalignment of any one mask. In the worst case, these effects may combine
to cause the relative position of feature edges on different mask levels to deviate by as
much as 2λ in their interrelationship. Inevitably, a consequence of using the lambda-
based concept is that every dimension must be rounded up to whole λ values and this
leads to layouts which do not fully exploit the capabilities of the process.
Similar concepts underlie the establishment of 'micron-based' rule sets, but actual
dimensions are given so that full advantage can be taken of the fabrication line
capabilities and tighter layouts result.
Layout rules, therefore, provide strict guidelines for preparing the geometric layouts
which will be used to configure the actual masks used during fabrication and can be
regarded as the main communication link between circuit/systems designers and the
process engineers engaged in manufacture. The goal of any set of design rules should
give optimize yield while keeping the geometry as small as possible without
compromising the reliability of the finished circuit. On the questions of yield and
reliability, even the conservative nature of the lambda based rules can stand
reevaluation when these two factors are of paramount importance. In particular, the
rules associated with contacts can be improved upon in the light of experience. Fig.(a)
sets out aspects that may be observed for high yield and in high reliability situations. In
our proposed scheme of events in creating stick layouts for CMOS, it is assumed that
poly and metal can both freely cross well boundaries and this is indeed the case, but we
should be careful to try to exclude poly from areas which lie within p+ mask areas
where possible. The reason for this is that the resistance of the poly. layer is reduced in
current processes by n- type doping. Clearly the p+ doping which takes place inside the
p+ mask will also dope the poly. which is already in place when the p+ doping step
takes place. This results in an increase in the n- doping poly. resistance which may be
significant in certain parts of a system.

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The 3λ. metal width rule is a conservative one but is implemented to allow for the fact
that the metal layer is deposited after the others and on top of them and several layers
of silicon dioxide, so that the surface on which it sits is quite 'mountainous' . The metal
layer is also light-reflective and these factors combine to result in poor edge definition.
In double metal the second layer of metal has an even more uneven terrain on which to
be deposited and patterned. Hence metal 2 is often wider than metal 1.
Metal to metal separation is also large and is brought about mainly by difficulties in
defining metal edges accurately during masking operations on the highly reflective
metal. All diffusion processes are such that lateral diffusion occurs as well as impurity
penetration from the surface. Hence the separation rules for diffusion allow for this and
relatively large separations are specified. This is particularly the case for the p-well
diffusions which are deep diffusions and thus have considerable lateral spread.
Transitions from thin gate oxide to thick field oxide in the oxidation process also use
up space and this is another reason why the lambda-based rules require a minimum
separation between thinox regions of 3λ. In effect, this implies that the minimum
feature size for thick oxide is 3λ.The simplicity of the lambda-based rules makes this
approach to design an appropriate one for the novice chip designer and also, perhaps,
for those applications in which we are not trying to achieve the absolute minimum
area and the absolute maximum performance. Because lambda-based rules try 'to be all
things to all people', they do suffer from least common denominator effects and from
the upward rounding of all process line dimension parameters into integer values of
lambda.
.

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Orbit 2µm CMOS process:

In this process all the spacing between each layers and dimensions will be in terms
micrometer. The 2µm here represents the feature size. All the design rules whatever we
have seen will not have lambda instead it will have the actual dimension in micrometer.
In one way lambda based design rules are better compared micrometer based design
rules, that is lambda based rules are feature size independent.
Figure below shows the design rule for BiCMOS process using orbit 2um process.

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Double metal MOS process rules:

In the MOS design rules a powerful design process is achieved by adding a second metal
layer. This gives a much greater degree of freedom, in distributing global VDD and
Vss(GND) rails in a system. From the overall chip inter-connection aspect, the second
metal layer in particular is important and, although the use of such a layer is readily
envisaged, its disposition relative to its connection. To other layers using metal1 to metal
2 contacts, called vias, can be readily established.
Usually, second level metal layers are coarser than the first (conventional) layer and the
isolation layer between the layers may also be of relatively greater thickness. To
distinguish contacts between first and second metal layers, they are known as vias rather
than contact cuts. The second metal layer representation is color coded dark blue (or
purple).
The important process steps for a two-metal layer process are given below.
The oxide below the first metal layer is deposited by atmospheric chemical vapor
deposition (CVD) and the oxide layer between the metal layers is applied in a similar
manner. Depending on the process, removal of selected areas of the oxide is
accomplished by plasma etching, which is designed to have a high level of vertical ion
bombardment to allow for high and uniform etch rates. Similarly, the bulk of the process
steps for a double polysilicon layer process are similar in nature to those already
described, except that a second thin oxide layer is grown after depositing and patterning
the first polysilicon layer (Poly.1) to isolate it from the now to be deposited second poly.
Layer (Poly.2). The presence of a second poly. Layer gives greater flexibility in
interconnections and also allows Poly.2 transistors to be formed by intersecting Poly. 2
and diffusion.
The important features of double metal process are summarized as follows:
 Use the second level metal for the global distribution of power buses, that is, VDD
and GND (Vss), and for clock lines.
 Use the first level metal for local distribution of power and for signal lines.
 Lay out the two metal layers so that the conductors are mutually orthogonal
wherever possible.

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CMOS Inverter Layout :

GND In VD D

A A’

Out

(a) Layout

A A’
n
p-substrate Field
+ + Oxide
n p
(b) Cross-Section along A-A’

VDD Contact Cut VDD

X n-well

X
x x
x x X

X
Gnd

Gnd

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Alternate Layout of NOT Gate : VDD

VDD

X X

x x

X X

Gnd
x Gnd
x

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NAND2 Layout:
VDD VDD

X X X

a.b

Gnd a.b
a b
X X

Gnd
a b
NOR2 Layout :
VDD
VDD

X X

ab
ab

a b X X X
Gnd
a b
Gnd

TRANSMISSION GATE :

Symbol schematic

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stick diagram
layout

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Scaling of MOS Circuits:

1. What is Scaling?
Proportional adjustment of the dimensions of an electronic device while maintaining the
electrical properties of the device, results in a device either larger or smaller than the un-
scaled device.
2. Why Scaling?
Scale the devices and wires down, Make the chips ‘fatter’ – functionality, intelligence,
memory – and – faster, Make more chips per wafer – increased yield, Make the end user
Happy by giving more for less and therefore, make MORE MONEY!!
Impact of scaling is characterized in terms of several indicators:
 Minimum feature size
 Number of gates on one chip
 Power dissipation
 Maximum operational frequency
 Die size
 Production cost

Types of scaling:

Scaling Models

1. Full Scaling (Constant Electrical Field): Ideal model – dimensions and voltage scale
together by the same scale factor. Requires to reduce power supply voltage with the
reduction of feature size. The electric field across the gate-oxide does not change when
the technology is scaled.

2. Fixed Voltage Scaling (Constant voltage scaling): Most common model until
recently – only the dimensions scale, voltages remain constant. Increasing electric field
leads to velocity saturation, mobility degradation, and sub threshold leakage

3. General Scaling: Most realistic for today’s situation – voltages and dimensions scale
with different factors

Scaling Factors for Device Parameters

Device scaling modeled in terms of generic scaling factors: 1/αand 1/β
• 1/β: scaling factor for supply voltage VDD, and gate oxide thickness D
• 1/α: linear dimensions both horizontal and vertical dimensions
Why is the scaling factor for gate oxide thickness different from other linear horizontal
and vertical dimensions? Consider the cross section of the device as in Figure 6, various
parameters derived are as follows.

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Limiting factors of scaling:

1) Hot Carrier Effect
2) Punch Through
3) Drain Induced Barrier Lowering (DIBL)
4) Gate Induced Barrier Lowering (GIBL)

• Gate Area
• Gate Capacitance per unit area
• Gate Capacitance
• Charge in Channel
• Channel Resistance
• Transistor Delay
• Maximum Operating Frequency
• Transistor Current
• Switching Energy
• Power Dissipation Per Gate (Static and Dynamic)
• Power Dissipation Per Unit Area
• Power - Speed Product

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Implications of Scaling:
 Improved Performance
 Improved Cost
 Interconnect Woes
 Power Woes
 Productivity Challenges
 Physical Limits
Limitations of Scaling
Effects, as a result of scaling down- which eventually become severe enough to prevent
further miniaturization.
o Substrate doping
o Depletion width
o Limits of miniaturization
o Limits of interconnect and contact resistance
o Limits due to sub threshold currents
o Limits on logic levels and supply voltage due to noise
o Limits due to current density

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OR 3-inputs, AND, then Inverter:

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CMOS TG BASED 4 -INPUT MUX

1 BIT CMOS SHIFT REGISTER CELL

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BICMOS 2 INPUT NAND GATE

BICMOS 2 INPUT NOR GATE

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