10/24/202

Ho Chi Minh City University of Technology

Department of Electrical and Electronics

ECE391 Computer System Engineering

Chapter 3:
Interrupts and Handlers - ARM Processor
1. ARM Cortex - Operation Modes
2. ARM Cortex Interrupts and Exceptions
3. ARM Cortex NVIC

1. ARM Cortex – Operation Modes

ARM Cortex has 2 modes and 2 privilege levels
• Thread mode: Used to execute application software
• Handler mode: Used to handle exceptions
• Unprivileged:
– has limited access to the MSR and MRS instructions, and cannot
use the CPS instruction
– cannot access the system timer, NVIC, or system control block
– might have restricted access to memory or peripherals
• Privileged: can use all the instructions and has access to all
resources

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1. ARM Cortex – Operation Modes

• Mode transitions

Allowed Operation Mode Transitions

1. ARM Cortex-M3 – Operation Modes

• Software in a privileged access level can switch the program into the
user access level using the Control register

• Switching Processor
Mode at Interrupt

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2. ARM Cortex Interrupt

• The Built-In Nested Vectored Interrupt Controller
(NVIC) provides a number of features:
– Nested interrupt support: different priority levels
– Vectored interrupt support: interrupt vector table in
memory
– Dynamic priority changes support: Priority levels of
interrupts can be changed during run time.
– Reduction of interrupt latency: automatic saving and
restoring some register contents, reducing delay in
switching
– Interrupt masking: Interrupts and system exceptions
can be masked

2. ARM Cortex-M3 - Interrupt

• Control[1] = 0: Both Thread Level and Handler Use Main Stack

• Control[1] = 1: Thread Level Uses Process Stack and Handler Uses Main Stack

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2. ARM Cortex – Memory Map

• The 4 GB memory space can be divided into the ranges shown in
Figure:

2. ARM Cortex-M3 – Memory Access

• Default memory access permissions

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ARM Cortex - Exceptions

• The interrupt features in the Cortex-M3 are implemented in the NVIC

ARM Cortex - Exceptions

• The number of external interrupt inputs is defined by chip

manufacturers.
• A maximum of 240 external interrupt inputs can be supported

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3. Interrupt - NVIC
Nested Vectored Interrupt Controller (NVIC)
• Handles exceptions and interrupts
• 8 programmable priority levels, priority grouping
• 7 exceptions and 65 Interrupts
• Automatic state saving and restoring
• Automatic reading of the vector table entry
• Pre-emptive/Nested Interrupts
• Tail-chaining
• Deterministic: always 12 cycles or 6 with tail-chaining

Motor control ISRs (e.g. PWM, ADC)

Communication ISRs (e.g. CAN)

Main application (foreground)

t

Tail Chaining...

Interrupt Latency - Tail Chaining

Highest
Priority IRQ1

IRQ2

PUS PO PUS
Typical processor ISR 1 ISR 2 POP
H P H

Tail-chaining
PUS PO
Cortex-M4 ISR 1 ISR 2
Interrupt handling in HW H P
12 6 12
Cycles Cycles Cycles

Pre-emption …
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Interrupt Latency – Pre-emption

Highest
Priority IRQ1

IRQ2

Typical processor PO PUS PO

ISR 1 ISR 2
P H P

P
PO
Cortex-M4 ISR 1 O ISR 2
P
P
1- 6 12
12 Cycles
Cycles Cycles

Late arrival...

Interrupt Latency – Late Arrival

Highest IRQ1
Priority

IRQ2

PUS PUS PO PUS PO

Typical processor ISR 1 ISR 2
H H P H P

PUS PO
Cortex-M4 ISR 1 ISR 2
H P
6 12
Cycles Cycles

Interrupt handling...
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Cortex-M4® Interrupt Handling

Interrupt handling is automatic. No instruction overhead.

Entry
Automatically pushes registers R0–R3, R12, LR, PSR, and PC onto the stack
In parallel, ISR is pre-fetched on the instruction bus. ISR ready to start
executing as soon as stack PUSH complete

Exit
Processor state is automatically restored from the stack
In parallel, interrupted instruction is pre-fetched ready for execution upon
completion of stack POP

Exception types...

Cortex-M4® Exception Types

Vector Exception Priority Vector Descriptions
Number Type address
1 Reset -3 0x04 Reset
2 NMI -2 0x08 Non-Maskable Interrupt
3 Hard Fault -1 0x0C Error during exception processing
4 Memory Programmable 0x10 MPU violation
Management
Fault
5 Bus Fault Programmable 0x14 Bus error (Prefetch or data abort)
6 Usage Fault Programmable 0x18 Exceptions due to program errors
7-10 Reserved - 0x1C - 0x28
11 SVCall Programmable 0x2C SVC instruction
12 Debug Monitor Programmable 0x30 Exception for debug
13 Reserved - 0x34
14 PendSV Programmable 0x38
15 SysTick Programmable 0x3C System Tick Timer
16 and above Interrupts Programmable 0x40 External interrupts (Peripherals)

Vector Table...
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Cortex-M4® Vector Table

• After reset, vector table is located at
address 0
• Each entry contains the address of
the function to be executed
• The value in address 0x00 is used as
starting address of the Main Stack
Pointer (MSP)
• Vector table can be relocated by
writing to the VTABLE register
(must be aligned on a 1KB boundary)
• Open startup_ccs.c to see vector
table coding

GPTM...

Interrupt Configuration
• Interrupt Enable
– void IntDisable (unsigned long ulInterrupt)
– void IntEnable(unsigned long ulInterrupt)
– tBoolean IntMasterDisable (void)
– tBoolean IntMasterEnable (void)
– void TimerIntEnable (unsigned long ulBase, unsigned long
ulIntFlags)
• Example
– IntEnable(INT_TIMER0A);
– TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
– IntMasterEnable();

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Interrupt Handler
Interrupt handler sample: toggle a LED at GPIO_PIN2
void Timer0IntHandler(void)
{
// Clear the timer interrupt
TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
// Read the current state of the GPIO pin and
// write back the opposite state
if(GPIOPinRead(GPIO_PORTF_BASE, GPIO_PIN_2))
{
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, 0);
}
else
{
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, 4);
}
}

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Class Assignment
• Write a program to toggle the LED on the LM4F120
kit with the frequency 20Hz using Timer1 and
interrupt

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