8086 Microprocessor

 The 8086 is a 16-bit microprocessor. The term “16-bit” means that its arithmetic logic
unit, internal registers and most of its instructions are designed to work with 16-bit binary
words.
 The 8086 has a 16-bit data bus, so it can read data from or write data to memory and
ports either 16 bits or 8 bits at a time.
 The 8086 has a 20-bit address bus, so it can directly access 220 or 10,48,576 (1Mb)
memory locations. Each of the 10, 48, 576 memory locations is byte Therefore, a sixteen-
bit words are stored in two consecutive memory locations.
 The Features of 8086 Microprocessor can generate 16-bit I/O address, hence it can access
216 = 65536 I/O ports.
 The 8086 provides fourteen 16-bit registers.
 The 8086 has multiplexed address and data bus which reduces the number of pins
needed, but does slow down the transfer of data (drawback).
 The Features of 8086 Microprocessor is possible to perform bit, byte, word and block
operations in 8086. It performs the arithmetic and logical operations on bit, byte, word
and decimal numbers including multiply and divide.
 The Intel 8086 is designed to operate in two modes, namely the minimum mode and the
maximum mode. When only one 8086 CPU is to be used in a microcomputer system, the
8086 is used in the minimum mode of operation. In this mode the CPU issues the control
signals required by memory and I/O In multiprocessor (more than one processor in the
system) system 8086 operates in maximum mode. In maximum mode, control signals are
generated with the help of external bus controller (8288).
 The Intel 8086 supports multiprogramming. In multiprogramming, the code for two or
more processes is in memory at the same time and is executed in a time-multiplexed
fashion.
 An interesting feature of the 8086 is that it fetches up to six instruction bytes from
memory and queue stores them in order to speed up instruction execution.
 The 8086 Microprocessor provides powerful instruction set with the following addressing
modes : Register, immediate, direct, indirect through an index or base, indirect through
the sum of a base and an index register, relative and implied.
Architecture of 8086 Microprocessor

8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit)
and BIU (Bus Interface Unit).

EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and
then decode and execute those instructions. Its function is to control operations on data
using the instruction decoder & ALU. EU has no direct connection with system buses as
shown in the above figure, it performs operations over data through BIU.

Let us now discuss the functional parts of 8086 microprocessors.

ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.

Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the
result stored in the accumulator. It has 9 flags and they are divided into 2 groups −
Conditional Flags and Control Flags.

It is a 16-bit register. 9-bit are used as different flags, remaining bits unused

OF DF IF TF SF ZF AF PF CF

Fig: 16-bit flag register

Out of 9-flags, 6 are conditional (status) flags and three are control flags

Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is
the list of conditional flags −

 Carry flag − This flag indicates an overflow condition for arithmetic operations.
 Auxiliary flag − When an operation is performed at ALU, it results in a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then
this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The processor uses this
flag to perform binary to BCD conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e. when the
lower order 8-bits of the result contains even number of 1’s, then the Parity Flag is
set. For odd number of 1’s, the Parity Flag is reset.
 Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is
zero else it is set to 0.
 Sign flag − This flag holds the sign of the result, i.e. when the result of the
operation is negative, then the sign flag is set to 1 else set to 0.
 Overflow flag − This flag represents the result when the system capacity is
exceeded.

Control Flags
Control flags controls the operations of the execution unit. Following is the list of control
flags −

 Trap flag − It is used for single step control and allows the user to execute one
instruction at a time for debugging. If it is set, then the program can be run in a
single step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and set to 0
for interrupt disabled condition.
 Direction flag − It is used in string operation. As the name suggests when it is set
then string bytes are accessed from the higher memory address to the lower
memory address and vice-a-versa.
General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These
registers can be used individually to store 8-bit data and can be used in pairs to store 16bit
data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It
is referred to the AX, BX, CX, and DX respectively.

 AX register − It is also known as accumulator register. It is used to store operands

for arithmetic operations.
 BX register − It is used as a base register. It is used to store the starting base
address of the memory area within the data segment.
 CX register − It is referred to as counter. It is used in loop instruction to store the
loop counter.
 DX register − This register is used to hold I/O port address for I/O instruction.

Pointer and Index registers:

SP (Stack Pointer), BP (Base pointer), SI (Source Index), DI (Destination index)

 Pointer Registers:
The two pointer registers, SP and BP are used to access data in the stack segment.
The SP is used as offset from current Stack Segment during execution of instruction that
involve stack. SP is automatically updated. BP contains offset address and is utilized in
based addressing mode. Overall, these are used to hold the offset address of the stack
address.
 Index Registers:
EU also contains a 16-bit source index (SI) register and 16-bit destination index
(DI) register. These registers can be used for temporary storage of data similarly as the
general purpose registers. However they are specially to hold the 16-bit offset of the data
word. SI and DI are used to hold the offset address of the data segment and extra segment
memory respectively.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending
addresses, fetching instructions from the memory, reading data from the ports and the
memory as well as writing data to the ports and the memory. EU has no direction
connection with System Buses so this is possible with the BIU. EU and BIU are connected
with the Internal Bus.

It has the following functional parts −

 Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of
next instructions and stores them in the instruction queue. When EU executes
instructions and is ready for its next instruction, then it simply reads the instruction
from this instruction queue resulting in increased execution speed.

Fetching the next instruction while the current instruction executes is

called pipelining.

 Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the
addresses of instructions and data in memory, which are used by the processor to
access memory locations. It also contains 1 pointer register IP, which holds the
address of the next instruction to executed by the EU.
o CS − It stands for Code Segment. It is used for addressing a memory
location in the code segment of the memory, where the executable program
is stored. holds the upper 16-bits of the starting addresses of the segment from
which BIU is currently fetching instruction code bytes.
o DS − It stands for Data Segment. It consists of data used by the program
and is accessed in the data segment by an offset address or the content of
other register that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store data and
addresses during execution.
o ES − It stands for Extra Segment. ES is additional data segment, which is
used by the string to hold the extra destination data.
 Instruction pointer − It is a 16-bit register used to hold the address of the next
instruction to be executed.

Pin Diagram
Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its
operation.

Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.

Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.

Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it
carries 4-bit address and later it carries status signals.

S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer
of data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it
is active.

Read
It is available at pin 32 and is used to read signal for Read operation.

Ready
It is available at pin 32. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready
to transfer data. When it is low, it indicates wait state.

RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.

INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an interrupt
or not.

NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered
input, which causes an interrupt request to the microprocessor.

TEST
This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.

MN/MAX
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-a-
versa.

INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.

ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a
valid address on the address/data lines.

DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver
8286. The transreceiver is a device used to separate data from the address/data bus.

DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the transreceiver. When it is high, data is transmitted out
and vice-a-versa.

M/IO
This signal is used to distinguish between memory and I/O operations. When it is
high, it indicates I/O operation and when it is low indicates the memory operation. It is
available at pin 28.

WR
It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.

HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.

HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide
the status of instruction queue.

S0, S1, S2
These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26,
27, and 28. '

LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave
the system bus. It is activated using the LOCK prefix on any instruction and is available at
pin 29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the CPU to
release the system bus. When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
INTERRUPTS IN 8086
Interrupts are signals generated by external devices or internal conditions that require the
immediate attention of the microprocessor. When an interrupt occurs, the microprocessor
temporarily suspends its current execution and transfers control to a specific interrupt handler
routine.
The interrupt handler routine, also known as the Interrupt Service Routine (ISR), handles the
interrupt and performs the required task. After completing the interrupt handling, the
microprocessor resumes the execution of the interrupted program.
When a microprocessor receives an interrupt signal it stops executing current normal
program, save the status (or content) of various registers (IP, CS and flag registers in case of
8086) in stack and then the processor executes a subroutine/procedure in order to perform the
specific task/work requested by the interrupt.

The subroutine/procedure that is executed in response to an interrupt is also called Interrupt

Service Subroutine (ISR). At the end of ISR, the stored status of registers in stack is restored to
respective registers, and the processor resumes the normal program execution from the point
(instruction) where it was interrupted.

There are two types of interrupts:

Hardware Interrupts
Hardware interrupts are the types of interrupts which are caused by any peripheral device
and sends signals through a specified pin to the processor. Hardware interrupt is used to handle
external hardware peripherals , such as key boards, mouse, hard disks , floopy disks, DVD
drivers and printers.

 The 8086 has two hardware interrupt pins, i.e. NMI and INTR.
 NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority.
 One more interrupt pin associated is INTA called interrupt acknowledge.
Non-Maskable Interrupt(NMI)
This interrupt has high priority than maskable interrupt. This cannot be replaced by any
software and it is also used by the processor to handle in case of any emergency.
Non-Maskable interrupts
 Used during power failure
 Used during critical response time
 Used during non-recoverable hardware errors
 Used watchdog interrupt
 Used during memory parity errors

Maskable Interrupt
The 8086 microprocessor has a dedicated hardware interrupt input pin called INTR (Interrupt
Request). When a hardware interrupt occurs, the INTR pin is activated, and the microprocessor
acknowledges the interrupt by executing the interrupt acknowledge cycle. The programmer can
choose to mask specific interrupts and re-enable them later.
When a maskable interrupt occurs… These actions are taken by the microprocessor –
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the return address are
pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0

Software Interrupts
The software interrupts are program instruction. These instructions are inserted at desired
location in a program. While running a program , if software interrupt instruction is
encountered then the processor initiates an interrupt.

It can be interrupted by internal abnormal conditions and a programmer can also interrupt at
the required point while debugging a program. The 8086 processor has 256 types of software
interrupts. The software interrupt instruction is INT n , where n is the type number in the range 0
to 255.

These 256 interrupts of 8086 are divided into 3 groups

1. Type 0 to type 4 interrupts-
These are used for fixed operations and hence are called dedicated interrupts

2. Type 5 to type 31 interrupts

Not used by 8086, reserved for higher processors like 80286, 80386 etc.

3. Type 32 to type 255 interrupts

Available for user, called user defined interrupts . these can be hardware interrupts and
Activated through Interline or can be software interrupts.
Examples of Software Interrupts are as below
 Type 0 (division by zero)
 Type 1 (Single step interrupt:- used for executing the program in single step mode by
setting Trap flag)
 Type 2 (Non Maskable interrupt:-failure of power condition) it represents NMI
 Type 3 (break point interrupt):- When this interrupt occurs a program would execute up
to its break point.
 Type 4 (overflow interrupt:- used to handle any overflow error)