Check the 0-TC point in your FETs.

Experiments show that theoretical values of

_
bias current for 0-TC are not accurate.
A zero-temperature-coefficient (0-TC) point ent of the drain-to-source voltage. V asz, on · the
that is inherently present in junction- and MOS- other hand, is dependent on the drain-to-source
FETs is the devices' ideal operating point because voltage, a variable known only in the final circuit
no changes due to temperature take place there. configuration.
The theoretical explanation of this phenomenon From practical considerations, therefore, the best
is already well documented. 1 • 2 • 3 • •· 5 Experience way to establish the 0-TC point is experimentally.
shows, however, that theoretical expressions I oz , being a unique value, should be determined
cannot be relied on for detailed circuit design. In first. A -second test should then be performed to
fact, to use the 0-TC point in practical circuits, a determine V asz at I oz and the proper drain-to-
designer must determine it for every FET type, source voltage. The 0-TC point can be determined
and, quite often, for each FET of the same type. easily by making a plot of V as vs I 0 for various
The purpose of this article, then, is to describe temperatures, using the circuit shown in Fig. la.
the 0-TC measuring techniques, to present test The equipment needed is an X-Y recorder, two
data for several commercially available FETs, and
to review briefly applications where the 0-TC 100
N CHANNEL P CHANNEL
J-FET
point can be used advantageously. PRECISION
MOS(DEPL.}
+Voe
-VGG
-Voe
+Voo
Voo
IOVOLTS TO RECORDER MOS(ENH.) +Voe -Voe
Y-AXIS Io +Voo -VGG
Theoretical model may give imprecise results
Voo
The temperature variation of drain current in IOVOLTS TO RECORDER
X-AXIS VGs
J-FETs is largely due to two opposing factors. IOk
FET
WW
The first is the change in width of the thermally 10
UNDER
TEST
TURN
generated depletion layer at the gate-channel
junction. The second is the majority-carrier
mobility between the source and drain. 0
In the references cited above it is shown that
the first factor tends to increase the drain current 3.0
at a rate equivalent to a change of 2.2 mV /° C at
the gate. The second factor tends to decrease the
gate current at a rate of approximately 0.7 %/° C.
These two factors combined result in the follow-
ing equations: 1
l oz= 0.4 l oss/ V /= drain current <(
E
fo r zero TC (1)
V asz = V 11 -0.63 = gate-source voltage ..
0

for zero TC (2)

These equations, having been developed from a
theoretical model, often do not give correct results
in practice. The semiconductor doping and
diffusion account for most of the differences
between the actual and theoretical results. Of the
two foregoing equations, the first is the more 1.0 2..0 3.0
meaningful because the result, I oz , is independ- VGs - VOLTS
@
1. 0-TC point of a FET can be quickly determined using a
Thomas H. Lynch, Systems Engineer, Perkin Elmer simple test setup (a). A sample curve (b) has been
Aerospace Systems, Pomona, Calif. obtained for the 2N2609 FET.

230 ELECTRONIC DESIGN 9, April 26, 1967

low-voltage de suppJies, and an environmental +4
oven. A ten-turn potentiometer is used to control
the gate-to-source voltage so that a smooth curve ~
.... +2
is produced .on the X-Y recorder. A sample Vo s- >
E
I
vs-I D plot of a p-channel FET is shown in Fig. lb. ....:J
In lieu of using an oven, a simpler and possibly Q.
~ 0
quicker method would be the use of ice water and g
0
boiling water. This method would produce both an w
Ir
Ir -2
accurate temperature reference and a very good w
"-
w
heat sink. Ir
....
It is frequently impractical to bias the FET at "-
ii: --4
0
exactly I Dz· In order to determine the tempera-
ture drift errors at other drain currents, a plot -6
0.2 0.5 l.O 2.0 5.0
similar to that of Fig. 2 can be used. It was devel-
1o 11 oz
oped by determining graphically the drift at vari-
2. Maximum allowable drift for condition when a FET
ous drain currents with the V 08-vs-I 0 plot of Fig. must be biased at an 10 different from l 0 z can be deter-
lb. It can be seen that for moderate drift require- mined from the data of Fig. lb. Devices of four manufac-
ments (less than 1 mV /° C) the J-FET is well turers were used for this photo.
behaved over a wide range of currents.
A large spread in I oz values often occurs from
one sample to the next of a particular type of J- 3.0
FET. This is a result of the many device condi-
tions that affect I Dz· When production require-
ments necessitate a specific loz, the J-FETs can
l
/J,'f
usually be specially ordered from a manufacturer.
<l
2.0 f---+---+---+---+-----+---+---+-7---w+-l -----1

MOS-FET characteristics are hard to determine E

I
_o KMC 1501
The temperature dependence of MOS-FET
1.0 t---+---+--......----+---+---+-j--,---+---i
characteristics is much more difficult to define
than that of J-FETs'. For this reason, an easily 5~C
handled mathematical model has not as yet been
developed. One of the most difficult factors to
control· in MOS-FET fabrication is the interface
structure between the silicon drain-source channel VG<-VOLTS
and the silicon dioxide gate insulator. Large 3. MOS-FETs also possess a 0-TC point, as can be seen
changes in the surface properties of the transistor from the plot above. Yet it is more difficult to predict and
are to be expected as a result of variations in may vary from unit to unit. The existing theoretical models
cooling rate, in atmospheric purity, and in general are not accurate.
cleanliness during the formation of the gate
insulator.
A theoretical explanation of the temperature-
dependent properties can, however, be made. 2 It
can be theorized that there is a particular drain
current for which a 0-TC exists. But iri practice,
this drain current, I oz, is impossible to predict
and requires experimental determination.
The same method outlined for J-FETs can be
<l
used to determine the 0-TC point of MOS-FETs E
I
experimentally. Fig. 3 shows the results of a 0

temperature-dependent V os-vs-ID plot for a p-

channel enhancement-mode MOS-FET. For a
closer analysis of the 0-TC point, it is advanta-
geous to use zero suppression in the X-Y recorder.
This quickly demonstrates nonlinearities (Fig. 4).
One problem seldom admitted, yet sometimes VGS - VOLTS
encountered, is sodium ion drift. 3 This can compli- 4. A blown-up view of the 0-TC shown in Fig. 3, obtained
cate the search for a 0-TC point because the gate through zero suppression in the X-Y recorder, demon-
voltage may not be a true indication of drain strates the nonlinearities in the V08 -vs-1 n plot. Note the
current. The ion drift rate is very temperature- large variations in In.

ELECTRONIC DESIGN 9, April 26, 1967 231

dependent. At 100° C the mobility of sodium ions conventional circuitry requires the J-FET's I oz
through the silicon dioxide gate insulator is many to be near its I oss· From Eq. 2, Vv must be about
times greater than at room temperature. The 0.63 volt if I nz is to equal I oss· Devices such as
magnitude of the drift is vividly portrayed in Fig. the Union Carbide 2N3687 and 2N3698 satisfy
5, a plot of the drain current versus time. This this requirement. Equation 1 shows that low I oz
defect is present in varying degrees in all MOS- operation can be obtained from J-FETs that have
FETs presently manufactured and depends on the a Vv of 4 to 6 volts. However, the stage gain will
purity of the manufacturing conditions. The suffer unless techniques like that shown in Fig. 6
problem can be alleviated by first making the V as- are used. In this application, a constant-current
vs-1 0 plot at the highest temperature after the load at I oz is used to give the highest possible
drift has gone to its limit under biased conditions; stage gain. A temperature-compensated power
then, while maintaining the gate bias voltage, supply regulator combination (QI and CR1) and
cooling the device down for its lower-temperature Rl comprise the current source. The composite
runs. The result will be a true indication of I oz stage gain can easily exceed several thousand.
alone, if a significant drift is present. The use of MOS-FETs in de amplifiers, because
Most MOS-FETs that were tested possessed a O- of the difficulties involved, is usually limited to
TC point. Several units checked are listed below: high-input-impedance applications. The small
with their approximate I oz: number of different types available often limits
Sprague TXF200 50 µ,A the circuit design. Some of the problems that have
Fairchild FllOO 100 µ,A to be considered are:
General MEM520 0.5mA • The unpredictability of the 0-TC point.
Instrument MEM551 0.5mA • The 0-TC point variability with the tempera-
KMC 1501 1.5 mA ture range.
TRW 2N4308 2.5mA • Gate voltage drift due to ion migration.
Siliconix 2N3631 4.0mA It is therefore necessary to design the circuit
around the device once the MOS-FET's limitations
Because of variations in the manufacturing condi- have been thoroughly investigated.
tions, however, these approximate values must not Large-swing open-loop de amplifiers should be
be relied on as constant. avoided. This is to prevent drift errors when a
MOS-FETs, as a rule, will not perform as well signal causes operation at a point far removed
as J-FETs under wide ranges of temperature from the I oz value. The magnitude of this drift
because of the complex temperature compensation error can be calculated with a curve similar to
present at the 0-TC point. Of the types tested, the those in Fig. 2. The effects of drift can be reduced
General Instrument MEM520, MEM 551 and the by limiting 0-TC biased FET stages to low signal
KMC 1501 exhibited the most stable 0-TC point levels or by going to closed-loop operation. Closed-
over a temperature range of 0° C to 100 ° C. loop amplifiers are the best approach since they
have the advantage of reducing the drift error by
Where to use FETs the loop gain.
J-FETs offer the widest latitude in design
FETs for amplifiers and current sources
because of the diversity of the types available.
Since the transconductance, g,,,, of a FET is The FET version of the differential amplifier
proportional to the drain current, high gain in poses a problem (absent with transistors) because

RCA TA 2644
T = 100° C RI
VGs = l.B VOLTS

100>-----+----+----+-----<f-----+----+----< IN ------oouT

0
~---+----+---~----<'-----'-----'-----'

0 50 100 150 200 250 300 350

TIME - S
5. Drift due to ~he sodium ion migration is demonstrated 6. Stage gain of several thousands can be obtained by
in this graph. This effect renders theoretical predictions "feeding" the FET from a simple constant-current (equal
of FET behavior very difficult. to I oz) source.

232 ELECTRONIC DESIGN 9, April 26 , 1967

of the 0-TC point. When a de signal is applied to a
0-TC biased differential FET stage, differential BIAS ADJUST
drift errors will occur. These drift errors, which Rl~---i

appear only when a signal is applied, are caused

by one FET operating above, and the other oper-
ating below, the 0-TC bias point. To reduce dy-
namic-differential drift errors, the bias points
should be a little below the 0-TC values, depending
on the signal swing. This can be deduced from an INPUT
analysis of the curves of Fig. 2. If high input
impedances are not required, a good differential
l- BIAS RESISTORS-

transistor such as the 2N 4044 should be used + Voo

instead of a FET. 7. Stable single-ended de amplifier results when a dual

It has been implied that the operating point of a MOS-FET unit is used.
FET preceding a transistor can be adjusted to
compensate for the drift in the transistor. A
circuit of this nature should not be designed for
production-line fabrication, however, because of RI
D
the setup time required. Each circuit has to be G
individually trimmed to minimize drift, since drift s
rates of the FET and transistor vary from unit to R2
unit.
POWER SUPPLY LINE
MOS-FETs can easily be adapted for use in a
de-coupled cascode amplifier. Because of the 8. Enhancement-mode MOS-FET can be used to build a
compound connection, both MOS-FETs should simple constant-current source.
have nearly the same 0-TC point. Rather than
match two units that have the same 0-TC point,
-1. 0
use a dual-monolithic MOS-FET. Tests were •
performed on a General Instrument MEM551 -o .B •
dual unit to verify the similarity between the O- -o .~ . tz.
TC points of each MOS-FET. On the whole, they
were virtually identical. When properly biased in
.
u
..... -o.4 ~
the circuit, as shown in Fig. 7, the result is an
<l
::l
I
-0.2 L•
~
exceptionally stable de-input amplifier. u
>- 0
Due to the constant-current nature of FETs in
the pinch-off region, they lend themselves to use as
o.2
300
• 400 500 600
simple current sources. When using J-FETs for
LIMITING CURRENT - µ.A
this application, a low Vv is desirable. This will
9. Tests on a number of current-limiting FET diodes
minimize the voltage drop for current-limiting in indicate that they also possess 0 -TC points. They can be
the circuit of Fig. 7. R1 can be adjusted to produce obtained on special orders only.
the I Dz current. Enhancement-mode MOS-FETs
make simple current sources in the circuit of Fig.
8. The ratio of R1 and R2 can be adjusted to give diodes selected to this current at an additional
the proper current level. The big advantage of cost. All the same, of course, this particular I oJ.
FET current sources over conventional transistor- value will vary, depending upon the manufactur-
Zener combinations is their low minimum voltage
ing control. • •
drop for current-limiting.
Motorola is producing a series of current-limit- References:
ing diodes (type number MCL 1300) that are 1. James S. Sherwin, "The Fet as an Amplifier," 1966
actually J-FETs with gate and source shorted. WESCON Convention R ecord (New York: IEEE, 1966) ,
Session 11 / 2.
When FETs are used in this configuration, I Dss 2. F. P. Heiman and H. S. Miller, "Temperature De-
current is limited. If these current-limiting diodes pendence of n-Type MOS Transistors," IEEE Trans. on
Electron Devices, Vol. ED-12, No. 3 (March, 1965), 142.
are to have a 0-TC current level, the J-FET 3. A. S. Grove, P. Lamond et al., "Stable MOS Transis-
used must have a VP of about 0.63 volt. Since no tors," Electro T echnology, LXXVI, No. 6 (Dec., 1965 ), 40.
data on temperature stability were supplied, tests 4. Lee L. Evans, "Biasing FETs for Zero de Drift,"
E lectro T echnology, LXXIV, No. 2 (Aug., 1964 ) .
were run on enough diodes to verify the possible 5. James S. Sherwin, "Take the Fog out of Field-Effect
existence of I Dz current level. The results, shown Design ," ELECTRONIC DESIGN, XIV, No. 13 (May 24, 1966)'
in Fig. 9, indicate that the I Dz current level exists 38-44; "Gain Insight into FET Amplifiers," Op. cit., No.
14 (June 7, 1966), 40-45; "Simplify Low Frequency FET
at approximaely 0.37 mA. Motorola can supply Designs," Op. cit., No. 15 (June 21, 1966), 86-90.

ELECTRONIC DESIGN 9, April 26, 1967 233