INDIAN INSTITUTE OF TECHNOLOGY ROORKEE

ECN-333

Active Components

Prof. Darshak K Bhatt

Assistant Professor
Department of Electronics & Communication
Generic Three Terminal Device

2
Large Signal Equations

3
Generic DeviceBehavior

• slope is output resistance of device

• resistor (triode) region (very small output voltage)
non-linear resistor region (small output voltage)
• “constant” current region (large output voltage, current nearly
independent of output)
4
Large Signal Models

+
Vi
−

I = f (Vi)

Resistors and capacitors are non-linear

Rπ and Ro depend on bias point
Rg (intrinsic) depends on channel inversion level
Rb can change due to current spreadingeffects
Cgs varies from accumulation to depletion to inversion
Junction capacitors vary with bias

5
Small Signal Models
rx Cµ ry

+
rπ Cπ vπ gmvπ ro
−

rz

In small signal regime, R and C linear about a bias point:

1
Rg =R nqs + R
For For a d poly
d =3 ↔
BJT: FET Cgs
12 1
rx = rb input: R nqs ∼
5g m

6
Various Figures of Merit

• Intrinsic Voltage Gain (a0)

• Power Gain
• Unilateral Gain
• Noise
• Noise figure (NF and Noise Measure M)
• Flicker noise corner frequency
• Unity Gain Frequency
• fT
• Maximum Osc Freq fmax
• Gain (normalized to current): gm/I
• Gain Bandwidth

7
Other Important Metrics

• Complementary devices
– Device with same order of magnitude of fT / fmax
– Lateral pnp a “dog” compared to vertical npn
• Availability of Logic
– Low power/high density
– Useful with S/H (sample hold) and SC (switch capacitor) circuits
– Important for calibration
• Breakdown voltage
– Power amplifiers, dynamic range of analog circuitry
• Thermal conductivity
– Power amplifiers
• Quality and precision of passives
– Inductors, capacitors, resistors, and transmission lines

8
RF Semiconductors

9
SiGe vs RF CMOS

10
Current Gain
gmvgs
i o= g m
v gs =
jω(Cgs + Cgd)

io
ii Ai =
ii

Since id = gmvgs , and vgs j ω(Cgs + Cgd ) = is , taking the ratio

we have
id gm
Ai = =
is j ω(Cgs + Cgd )
Solving for |Ai = 1|, we arrive at the unity gain frequency
gm
ωT = 2πfT =
Cgs + Cgd
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Gain/Bandwidth Product

• In most applications, we intend to embed this amplifier in a

feedback loop, so the gain-bandwidth product is of interest.
• For a feedback system, we know that we can approximately trade
gain for bandwidth. So if we place the amplifiers in a feedback loop,
we have

Gain = A0

BW = ω0

12
Bipolar Junction Transistors

13
BJT Cross Section
n+poly contact
base n+ emitter collector

p+
n fieldoxide

n+ buriedlayer

p-type substrate

• Most transistor “action” occurs in the small npn sandwich under

the emitter. The base width should be made as small as possible in
order to minimize recombination. The emitter doping should be
much larger than the base doping to maximize electron injection
into the base.
• A SiGe HBT transistor behaves very similarly to a normal BJT,
but has lower base resistance rb since the doping in the base can be
increased without compromising performance of the structure.

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Bipolar Small-Signal Model
Cµ rc
rb
B C
+
Rπ Cπ vi n gm vi n ro Ccs
−
re
E

• The resistor Rπ dominates the input impedance at low

frequency. At high frequency, though, Cπ dominates.
• Cµ is due to the collector-base reverse biased diode
capacitance.
• Ccs is the collector to substrate parasitic capacitance. In some
processes, this is reduced with an oxide layer.
• Cπ has two components, due to the junction capacitance
(forward-biased) and a diffusion capacitance

15
Bipolar Exponential

• Due to Boltzmann statistics, the collector current is described

very accurately with an exponential relationship
qVBE
IC ≈ IS e kT (1)
• The device transconductance is therefore proportional to current

dIC q qVBE = qIC (2)

gm = = IS e kT
dV BE kT kT
• where kT /q = 26mV at room temperature. Compare this to the
equation for the FET. Since we usually have kT /q < Vgs − V T , the
bipolar has a much larger transconductance for the same current.
This is the biggest advantage of a bipolar over a FET.

16
Control Terminal Sensitivity

17
Bipolar Unity Gain Frequency

• The unity gain frequency of the BJT device is given by

gm gm
ωT = = (3)
Cπ + C µ Cdiff + 2Cje0 + Cµ

• where we assumed the forward bias junction has Cje ≈2Cje0

• Since the base-collector junction capacitance Cµ is a function of
reverse bias, we should bias the collector voltage as high as possible
for best performance.
• The diffusion capacitance is a function of collector current,
• Cdiff = gmτF gm
ωT = = 1
2Cje0+Cµ
(4)
gmτF + 2Cje0 + Cµ τF + gm

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Bipolar Optimum Bias Point
220
No KirkEffect

160

f T (GHz)
1
80 ωT →
τF
40

0
10− 4 10− 3 10− 2
IC
• We can clearly see that if we continue to increase IC , then gm ∝
IC increases and the limiting value of fT is given by the forward
transit time ωT ≈ 1/τ F
• In practice, though, we find that there is an optimum collector
current. Beyond this current the transit time increases. This
optimum point occurs due to the Kirk Effect. It’s related to the
“base widening” due to high level injection.
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CMOS FETTransistors

20
CMOS Cross Section
PMOS NMOS
VD D

S G D S G D

n+ p+ p+ p+ n+ n+
L ov L
n-well

p-type substrate

• Modern CMOS process has very short channel lengths

• (L < 100nm). To ensure gate control of channel, as opposed to
drain control (DIBL), we employ thin junctions and thin oxide (Tox
< 5nm).
• Due to lithographic limitations, there is an overlap between the
gate and the source/drain junctions. This leads to overlap
capacitance. In a modern FET this is a substantial fraction of the
gate capacitance (up to half).
21
FET Small Signal Model
Rg Cgd

G D
+
Cgs vgs gmvgs gmbvbs r o Cdb
−
S
RS
Cgb Csb

• The junctions of a FET form reverse-biased pn junctions with the

substrate (well), or the body node. This is another form of parasitic
capacitance in the structure, Cdb and Csb .
• At DC, input is an open circuit. The input impedance has a small
real part due to the gate resistance Rg (polysilicon gate and NQS)
and Rs,d account for junction and contact resistance.

22
FET Simplified Models

• In the forward active (saturation) region, the input capacitance is

given by Cgs= 2/3 W · L · Cox + Cov
• Don’t forget that layout parasitics increase the capacitance in the
model, sometimes substantially (esp in deep submicron
technologies). Ro is due to channel length modulation and other
short channel effects (such as DIBL).
Cgd
Cgd
G D
G D
+
Cg s vg s gm vg s g mb v bs r o Cdb +
− Cg s vg s gm vg s ro Cdb
−
S
S
Cgb Csb

• For low frequencies, the resistors are ignored. But these

resistors play an important role at high frequencies.
• If the source is tied to the bulk, then the model simplifies.
23
FET Extrinsic Model
G

Rge

C gse C gde

R se R de
S D

C bse C bde

R s,bs R s,bd

R be

Substrate parasitics, gate resistance, source/drain resistances,

extra metal and contact resistance and capacitance. At very
high frequencies, the distributed inductance of the leads.

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Intrinsic Voltage Gain

• Important metric for analog circuits

• Communication circuits often work with low impedances in

order to achieve high bandwidth, linearity, and matching.

25
Voltage Gain for Tuned Amplifiers

• Inductive loads are also common to tune out the load

capacitance and form a resonant circuit. The gain is thus given
by
• Av = gmRp = gmω0QL
• In a given process, there’s a maximum Q that we can obtain,
usually Q ∼ 10 at 1 GHz in a typical 90nm process with thick metal
options. The inductance cannot be increased without bound due to
area limitations and ultimately due to the tuning requirements

26
Normalized Gain

• For a bipolar device, the exponential current relationship results in

a high constant normalized gain
gm q 1
= ≈
IC kT 26mV
For a square law MOSFET, in saturation wehave
gm 2
=
IDS VGS − V T
In weak inversion, the MOSFET is also exponential
gm q 1 1
= ≈
IDS nkT 26mV n
The factor n is set by the ratio of oxide to depletion
capacitance

27
MOSFET in Subthreshold

In sub-threshold, the surface potential varies linearity with VG

The surface charge, and hence current, is thus exponentially
related to VG

28
MOS Transconductor Efficiency

• Since the power dissipation is determined by and large by the DC

current.
• From this perspective, the weak and moderate inversion
region is the optimal place to operate.
• The price we pay is the speed of the device which decreases with
decreasing VGS
• Current drive is also very small.

29
Scaling Speed Improvements
100

10

fT

0
1980 1985 1990 1995 2000 2005
year

CMOS transistors have steadily improved in performance just

as predicted by theory. In the short channel regime the
improvements are linear with scaling.
At the same time, the decreasing supply voltage has led to a
reduced dynamic range. Also the maximum gain has not
improved as much· · ·
30
f T versus Dimension

fT

Vgs=1.2V
1e-07 2e-07 3e-07 4e-07 5e-07 6e-07 7e-07 8e-07 9e-07 1e-06 L (m)

The well known improvement in fT with channel scaling is

shown here. Since both gm and Cgs depend linearity on the
width, only the channel length L matters.
Shorter channel lengths improve both the gm and lower the
capacitance of the device. In the velocity saturated limit, only
the drop in capacitance plays a role.

31
High Frequency

32
SiGe HBT and CMOS FinFETs

33
SiGe Technology

• Higher Performance: Demonstrations of fT > 500GHz and approach

1THz.

• Problem:As W B decreases → rb increases

Solution: SiGe base allows for higher fT
without reducing W B

34
SiGe HBT Action

• A SiGe BJT is often called an HBT (heterojunction bipolar

transistor)
• Ge epitaxially grown in base
• Causes strain in crystal
• Causes extra potential barrier for holes (majority carrier) in the base from
flowing into emitter
• Beneficial effects
• W B decreases, N B increases, rb low
• NE decreases, C j decreases

35
GaAs/InP Technology

• One of the primary advantages of the III-V based transistors is the

higher peak mobility compared to Si.
• Direct band gap.
• The insulating substrate also allows higher Q passives.
• The extra cost of these technologies limits it to niche
applications such as very high frequencies, high performance, and
power amplifiers.
36
FinFETs and Multigate Transistors

• To combat the problems with scaling of MOSFETs below 45nm,

Berkeley researchers introduced the “FinFET”, a double gate
device. (Intel uses this technology at the 22nm node)
• Due to thin body and double gates, there is better “gate
control” as opposed to drain control, leading to enhanced output
resistance and lower leakage in subthreshold.

37
FinFET Structure and Layout

Gate straddles thin silicon fin, forming two conducting

channels on sidewall
Multi-finger layout very similar to RF layout.

38
An Aside on Thermal Conductivity

• GaAs
❑ Semi-insulating substrate
❑ Not very good conductor of heat
❑ High quality passive elements
• Si
❑ Semi-conducting substrate Good conductor of
heat
❑ Lossy substrate leads to lower quality passives

39
An Aside on Thermal conductivity (2)

Also depends onpackaging

Example: in flip-chip bonding, thermal conductivity function of
number of bumps rather than substrate
Back-side of die can lose heat through radiation or convection
through air but thermal contact is much more effective

Flip chip bonding

Wire bonding

40
FET/BJT Comparisons

41
High BJT Transconductance

dIC q qVBE = qIC

gm = = IS e kT
dV BE kT kT

• For fixed current, BJT gives more gain

• Precision
– Important in multiplication, log, and exponential functions
– More difficult in FETs due to process/temp. dependence
– Is process dependent in BJT ... use circuit tricks

42
Advantages of BJT

gm q 1
= = For high-speed
IC kT 25mV
applications, need to bias
gm 2 1 in strong
= ≈
ID V GS − V T 250mV inversion...Results in ∼10x
IC ∝ e−E /kt = eqVBE /kT lower efficiency

• For a BJT, this relationship is fundamental and related to the

Boltzman statistics (approximation of Fermi-Dirac statistics)
• For a MOSFET, this relationship is actually only valid for a
square-law device and varies with V T (body bias) and temperature

43
Advantage of BJT over FET (2)
log(I C )
Better precision
About 4 decades
(420mV) of linearity
Example:
VBE 1 + VBE 2 = VBE 3
. Σ
IC
V BE = VT ln
IS
IC 1 · IC 2 IC 3
=
IS1 · IS2 IS3 420mV
V B E (V)

Can build exp, log, roots, vector mag

Lower 1/f noisecorner
Lower offset voltage
VOS ∼ 1mV
44
Disadvantage of BJT

• rb hurts gain (power), NF

▪ SiGe allows fast transistors with low rb
• Exponential transfer function (advantage and
disadvantage)
▪ Exponential → non-linear
• Expensive in high volumes, cheaper in low
volumes Absence of a switch
▪ Old CMOS gets cheaper!
▪ 45nm ∼ $1M mask → 0.25µm $50k mask

45
Advantage of FET overBJT

• Cheaper and more widely available (many fabs in US, Asia,

and Europe)
• Square law → less distortion
• PMOS P-FET widely available, only ∼ 2× less performance.
Triode region → variable resistor
• Widely available digital logic Low leakage in gates
• Sample and hold (S/H) and switch cap filters (SCF)
• Dense digital circuitry / DSP for calibration
• Offset voltages and mismatches can be compensated
digitally
• Dense metal layers allows MIM (“MOM”) capacitors for free

46
References and Further Reading

• Analysis and Design of Analog Integrated Circuits, Paul R. Gray,

Robert G. Meyer. 3rd ed. New York : Wiley, c1993.
• Manku, T. “Microwave CMOS-device physics and design,” IEEE
Journal of Solid-State Circuits, vol.34, (no.3), March 1999. p.277-
85. 32

47
DIODES AND DIODE CIRCUITS

• Schottky Diodes (Detectors Diode)

• PIN Diodes
• Varactor Diodes
• Other Diodes
– Gunn diodes
– IMPATT diodes
– Tunnel diodes
– BARITT diodes

48
Schottky Diodes

• The classical pn junction diode is commonly used at low

frequencies.
• It has a relatively large junction capacitance that makes it
unsuitable for high-frequency applications.
• The Schottky barrier diode -> semiconductor–metal junction
results in a much lower junction capacitance.
• Schottky diodes generally use n-type gallium arsenide
(GaAs) or n-type silicon
• Application of Schottky Diodes:
– Rectification (conversion to DC),
– Detection (demodulation of an amplitude-modulated signal),
– mixing (frequency shifting).

49
Application of Schottky Diodes

50
• A junction diode can be modeled as a nonlinear resistor.
• A small-signal V –I relationship expressed as

• Taylor series expansion

51
• First Derivative of Taylor expansion:

• Second Derivative of Taylor expansion

• small-signal approximation,

52
• The leads or contacts of the diode package are modeled as
a series inductance, Ls, and shunt capacitance, C p.
• The series resistor, Rs, accounts for contact
and current-spreading resistance.
• The junction capacitance, C j, and the junction resistance,
R j, are bias dependent.

53
Diode rectifiers

• If applied voltage at diode is:

• Diode current is given by:

• current sensitivity, βi,: It can be defined as a measure of the

change in the DC output current for a given RF input power.

• In terms of voltage, open circuit voltage sensitivity:

54
Diode Detectors

• In a detector application the nonlinearity of a diode is used to

demodulate an amplitude modulated (AM) RF carrier.

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