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Tutorial 8 Solution

This document discusses adder circuits and solutions to problems involving different types of adders. It compares ripple carry adders to carry lookahead adders. Ripple carry adders have lower area and power usage but higher delay, while carry lookahead adders have higher speed but use more area and power. The document provides solutions to problems calculating propagation delays for ripple carry adders with different gate delays and implementations. It explains that ripple carry adders are preferred when area or power are constraints and performance is not critical, while carry lookahead adders are used for high-performance designs where area and power are not limiting factors.

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46 views4 pages

Tutorial 8 Solution

This document discusses adder circuits and solutions to problems involving different types of adders. It compares ripple carry adders to carry lookahead adders. Ripple carry adders have lower area and power usage but higher delay, while carry lookahead adders have higher speed but use more area and power. The document provides solutions to problems calculating propagation delays for ripple carry adders with different gate delays and implementations. It explains that ripple carry adders are preferred when area or power are constraints and performance is not critical, while carry lookahead adders are used for high-performance designs where area and power are not limiting factors.

Uploaded by

sama abd elgelil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Advanced Digital Systems Tutorial Sheet 8 + Solutions S.

Nasser, 2022/2023

Tutorial Sheet 8 Solution

Adder Circuits

1. The following sequences of bits (right-most bit first) appear on the inputs to a 4-bit
parallel adder. Determine the resulting sequence of bits on each sum output:

Solution:
𝐴4 𝐴3 𝐴2 𝐴1 𝐵4 𝐵3 𝐵2 𝐵1 Σ4 Σ3 Σ2 Σ1 𝐶𝑜𝑢𝑡
1 1 0 0 1 0 1 1 0 1 1 1 1
0 0 0 1 0 0 1 0 0 0 1 1 0
1 1 1 0 0 0 0 0 1 1 1 0 0
1 0 1 1 0 0 1 1 1 1 1 0 0

2. In the process of checking a 74HC283 4-bit parallel adder, the following logic levels are
observed on its pins: 1-HIGH, 2-HIGH, 3-HIGH, 4-HIGH, 5-LOW, 6-LOW, 7-LOW, 9-
HIGH, 10-LOW, 11-HIGH, 12-LOW, 13-HIGH, 14-HIGH, and 15-HIGH. Determine if the IC
is functioning properly.

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Advanced Digital Systems Tutorial Sheet 8 + Solutions S. Nasser, 2022/2023

Solution:

Given Values:
𝐶𝑖𝑛 (7) 𝐴4 (12) 𝐴3 (14) 𝐴2 (3) 𝐴1 (5) 𝐵4 (11) 𝐵3 (15) 𝐵2 (2) 𝐵1 (6) Σ4 (10) Σ3 (13) Σ2 (1) Σ1 (4) 𝐶𝑜𝑢𝑡 (9)
0 0 1 1 0 1 1 1 0 0 1 1 1 1
Correct Values:
0 0 1 1 0 1 1 1 0 0 1 0 0 1

3. What is the delay for a 64-bit ripple carry adder? Assume that a full adder delay is 450 ps.
Solution:
𝑡𝑟𝑖𝑝𝑝𝑙𝑒 = 𝑁𝑡𝐹𝐴 = 64(450 ∗ 10−12 ) = 28.2 𝑛𝑠

4. A 16-bit ripple carry adder is realized using 16 identical full adders. The carry propagation
delay of each full adder is 12 ns and the sum propagation delay of each full adder is 15 ns. What
is the worst-case propagation delay?
Solution:
𝑡𝑤𝑜𝑟𝑠𝑡 𝑐𝑎𝑠𝑒 = (𝑛 − 1)𝑡𝑐 + max{𝑡𝑠 , 𝑡𝑐 }
= (15)(12) + 15
= 195 𝑛𝑠
5. Following figure shows the implementation of full adders in a 16-bit ripple carry adder
realized using 16 identical full adders. The propagation delay of the XOR, AND and OR
gates are 20 ns, 15 ns and 10 ns respectively. What is the worst-case delay?

Solution:
𝑡𝑐 = 𝑡𝑂𝑅 + 𝑡𝐴𝑁𝐷 = 15 + 10 = 25 𝑛𝑠
𝑡𝑠 = 20 𝑛𝑠
𝑡𝑤𝑜𝑟𝑠𝑡 𝑐𝑎𝑠𝑒 = (𝑛 − 1)𝑡𝑐 + max{𝑡𝑠 , 𝑡𝑐 }
= (15)(25) + 25
= 400 𝑛𝑠

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Advanced Digital Systems Tutorial Sheet 8 + Solutions S. Nasser, 2022/2023

6. Each of the eight full-adders in an 8-bit parallel ripple carry adder exhibits the
following propagation delay:

Determine the maximum total time for the addition of two 8-bit numbers.

Solution:
𝑡𝑤𝑜𝑟𝑠𝑡 𝑐𝑎𝑠𝑒 = (𝑛 − 1)𝑡𝑐 + max{𝑡𝑠 , 𝑡𝑐 }
= (7)(25) + 30
= 205 𝑛𝑠
7. Explain why a designer might choose to use a ripple-carry adder instead of a carry-
lookahead adder.

Solution:

Compared to the ripple-carry adder, the carry-lookahead adder is larger and uses more power
but is also a lot faster. Thus for performance-limited designs where area and power are not
constraints, the carry-lookahead adder is the clear choice. On the other hand, if either area or
power are the limiting constraints, one would choose a ripple-carry adder if performance were
not a constraint.

8. Build 16-bit adder using: 1) ripple carry adder 2) 4x4-bit CLA blocks. Assume that all gates
have the same delay. Compare the gate delays in each case, then briefly explain the trade-
offs in using each design.

Solution:

Ripple-carry adder:

Delay: 33 gate delays

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Advanced Digital Systems Tutorial Sheet 8 + Solutions S. Nasser, 2022/2023

4x4-bit CLA blocks:

Delay: 13 gate delays


A 16-bit (or more) carry lookahead adders are usually implemented as the above architecture
of CLA blocks cascaded.
Like the above problem, compared to the ripple-carry adder, the carry-lookahead adder is larger
and uses more power but is also a lot faster. Thus, for performance-limited designs where area
and power are not constraints, the carry-lookahead adder is the clear choice. On the other hand, if
either area or power are the limiting constraints, one would choose a ripple-carry adder if
performance were not a constraint.

Page 4 of 4

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