MINDANAO STATE UNIVERSITY
ILIGAN INSTITUTE OF TECHNOLOGY
COLLEGE OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING AND TECHNOLOGY
NAME:_____________________________________ COURSE AND YEAR:________
INSTRUCTOR: ______________________________ 1st Semester S.Y. 2023-2024
EEE 180.1 LABORATORY ACTIVITY
ACTIVITY 2: THE AND GATE
Objective:
To demonstrate and simulate the basic functions of the AND Gate.
Materials Needed:
1 unit 5V Power Supply Hook-up Wires (AWG #22)
1 pc 74LS08 IC 8 pcs 2kΩ ¼-watt Resistors
Breadboard 8 pcs LEDs
Introduction:
The AND gate is a basic logic gate whose output is a high logic level only when all inputs are
high. The symbol, truth table, and the pin configuration of the AND gate IC are illustrated in
Figure 2-1.
Figure 2-1. The AND gate (a) logic symbol, (b) truth table, and (c) 74LS08 IC pin configuration.
Procedure:
1. Construct the circuit shown in Figure 2-2.
LED indicators
L1 L2 L3 L4 L5 L6 L7 L8
D0 A B
D1
C D
D2
D3
Figure 2-2. Example of an AND gate circuit configuration.
2. Set all Data Switches (D0 – D3) to logic “0” or LO. What happen to the LED L1 – L8?
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3. Vary the Data Switches one at a time. What did you observe on the LED indicators?
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4. Fill-up the table below with their respective input combinations.
INPUT OUTPUT
D0 D1 D2 D3 L1 L2 L3 L4 L5 L6 L7 L8
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
Based on the data in the truth table, what did you observe on the result of D0 – D3 and
L1 – L4? Why? ________________________________________________________________
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5. Again fill-up the table below to verify the AND gate truth table using inputs D0 & D1. Check
the outputs of L1, L2, L5 and L7.
INPUT OUTPUT
D0 D1 L1 L2 L5 L7
0 0
0 1
1 0
1 1
Notice that the input of AND gate B are tied together. Based on the circuit, what can you observe on the
behavior of this gate based in the data of L5 and L7?
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6. The second set of gates is composed of AND gates C and D. Again, fill-up the table below to determine
the function of the circuit.
INPUT OUTPUT
D2 D3 L3 L4 L6 L8
0 0
0 1
1 0
1 1
What did you observe from the above table?
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Observation:
If the delay of each gate in Figure 2-2 is 15 ns, draw the signal waveform as indicated.
Conclusion:
