Freescale Semiconductor, Inc.

HC805P18GRS/D
REV 1.0

68HC805P18
SPECIFICATION
(General Release)
Freescale Semiconductor, Inc...

 December 7, 1995

CSIC System Design Group

Austin, Texas

For More Information On This Product,

Go to: www.freescale.com
 Freescale Semiconductor, Inc.

TABLE OF CONTENTS

Paragraph Title Page

SECTION 1
INTRODUCTION

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
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1.3 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.4 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4.2 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4.3 Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4.4 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.4.5 Port A (PA0 through PA7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.4.6 Port B (PB5/SDO, PB6/SDI, and PB7/SCK). . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4.7 Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1,
PC6/AD0, and PC7/VREFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4.8 Port D (PD5/CKOUT and PD7/TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4.9 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4.10 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

SECTION 2
MEMORY

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 User Mode Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3 I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.4 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.5 EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.6 User EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

SECTION 3
CENTRAL PROCESSING UNIT

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.2 Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Rev. 1.0 iii

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3.2.3 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

SECTION 4
INTERRUPTS

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

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4.2 Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2.1 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.2 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.3 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

SECTION 5
RESETS

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 External Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.3 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3.3 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

SECTION 6
OPERATING MODES

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 User Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2.1 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2.2 Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.4 STOP Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.4.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.4.3 WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.5 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

MC68HC805P18
iv Rev. 1.0
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SECTION 7
INPUT/OUTPUT PORTS

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.4 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.6 I/O Port Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
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SECTION 8
EEPROM

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 EEPROM Programming Register (EEPROG). . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.3 Programming/Erasing Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.4 Mask Option Registers (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

SECTION 9
ANALOG-TO-DIGITAL CONVERTER

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.1 Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.2 VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.3 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.4 Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.3 Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.3.1 Conversion Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.3.2 Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.3.3 Multi-Channel Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.4 A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.5 A/D Conversion Data Register (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.6 A/D Subsystem During Wait/Halt Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.7 A/D Subsystem Operation During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

Rev. 1.0 v
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SECTION 10
16-BIT TIMER

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.4 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.5 Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.6 Timer Status Register (TSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.7 Timer Operation During Wait/Halt Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
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10.8 Timer Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

SECTION 11
SERIAL INPUT/OUTPUT PORT

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.2 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.3 Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3.1 SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.3.2 SIOP Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.3.3 SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

SECTION 12
INSTRUCTION SET

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2.1 Inherent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.4 Extended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.2.8 Relative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3 Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.3.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.3.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

MC68HC805P18
vi Rev. 1.0
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12.3.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

12.3.4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.3.5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.4 Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

SECTION 13
ELECTRICAL SPECIFICATIONS
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13.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.2 Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.4 Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.5 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.6 Active Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.7 A/D Converter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.8 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.9 OSC Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.10 Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7

SECTION 14
MECHANICAL SPECIFICATIONS

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

14.2 28-Pin Dual In-Line Package (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.3 28-Pin Small Outline Package (Case #751F) . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

SECTION 15
ORDERING INFORMATION

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.2 MC Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

APPENDIX A
EMULATION

Rev. 1.0 vii

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LIST OF FIGURES

Figure Title Page

1-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1-2 User Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1-3 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
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2-1 MC68HC805P18 User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2-2 MC68HC805P18 I/O and Control Registers Memory Map . . . . . . . . . . . . . . 2-4
2-3 MC68HC805P18 I/O and Control Registers $0000–$000F . . . . . . . . . . . . . 2-5
2-4 MC68HC805P18 I/O and Control Registers $0010-$001F. . . . . . . . . . . . . . 2-6

3-1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3-2 Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

4-1 Interrupt Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4-2 IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

5-1 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5-2 Unimplemented Vector and COP Watchdog Timer Register . . . . . . . . . . . . 5-2

6-1 Bootloader Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6-2 STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

7-1 Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7-2 Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7-3 Port C I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7-4 Port D I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

8-1 EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8-2 Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8-3 Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

9-1 A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9-2 A/D Conversion Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

10-1 16-Bit Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10-2 Timer Registers (TMRH/TMRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10-3 Alternate Counter Registers (ACRH/ACRL) . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10-4 State Timing Diagram for Timer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10-5 State Timing Diagram for Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

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Figure Title Page

10-6 Output Compare Registers (OCRH/OCRL) . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10-7 Output Compare Software Initialization Example . . . . . . . . . . . . . . . . . . . . 10-7
10-8 Input Compare Registers (ICRH/ICRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10-9 State Timing Diagram for Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10-10 Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10-11 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

11-1 SIOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11-2 SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11-3 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
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11-4 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11-5 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

13-1 SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13-2 OSC Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13-3 Power-On Reset and External Reset Timing Diagram . . . . . . . . . . . . . . . . 13-8

A-1 MC68HC705P3 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-5

A-2 MC68HC705P6 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-5
A-3 MC68HC705P9 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-5
A-4 MC68HC805P18 Mask Option Registera . . . . . . . . . . . . . . . . . . . . . . . . . .A-5

MC68HC805P18
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LIST OF TABLES

Table Title Page

4-1 Vector Addresses for Interrupts and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

6-1 Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6-2 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
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6-3 COP Watchdog Timer Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

7-1 Port A I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7-2 Port B I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7-3 Port C I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7-4 Port D I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

8-1 Erase Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8-2 SIOP Clock Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

9-1 A/D Multiplexer Input Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . 9-5

12-1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12-2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12-3 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12-4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12-5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12-7 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14

15-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

A-1 Elements of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-2

A-2 Memory Breakdown by Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-3
A-3 P-Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-4
A-4 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-4

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GENERAL RELEASE SPECIFICATION

8
2
SECTION 1
INTRODUCTION 3
4
1.1 Introduction

The Motorola MC68HC805P18 microcontroller is a member of the M68HC05 5

microcontroller family with a 4-channel, 8-bit analog-to-digital (A/D) converter, a
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16-bit timer with output compare and input capture, a serial communications port 6
(SIOP), a computer operating properly (COP) watchdog timer, and 21 input/output
(I/O) pins (20 bidirectional, one input-only). The memory map contains 192 bytes 7
of RAM, 8064 bytes of program EEPROM (for user code), 512 bytes of boot ROM,
and128 bytes of EEPROM (for data storage). This device is available in a 28-pin
dual in-line package (DIP) or a small outline (SOIC) package. A functional block 8
diagram of the MC68HC805P18 is shown in Figure 1-1.
9
1.2 Features
10
• Low-cost HC05 core running at 2 MHz bus speed
• 28-pin DIP or SOIC package 11
• 4 MHz on-chip crystal/ceramic resonator oscillator
12
• 8064 bytes of user EEPROM including 48 bytes of page zero EEPROM and
16 bytes of user vectors
13
• 192 bytes of on-chip RAM
• 128 bytes of EEPROM 14
• Low-voltage reset
• 4-channel, 8-bit A/D converter
A
• SIOP serial communications port 16
• COP watchdog timer with active pulldown on RESET
• 16-bit timer with output compare and input capture 17
• 20 bidirectional I/O lines and one input-only line
18
• High current sink and source on two I/O pins (PC0 and PC1)
19
20
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8 COP PH2
÷2 OSC
OSC 1
OSC 2

2
÷4 16-BIT TIMER PD7/TCAP
CPU CONTROL ALU
1 INPUT CAPTURE
3 RESET
68HC05 CPU 1 OUTPUT COMPARE
TCMP
PD5/CKOUT
PORT D LOGIC
IRQ
4 CPU REGISTERS
ACCUMULATOR
PC7/VREFH

A/ D CONVERTER
INDEX REGISTER

DATA DIRECTION REGISTER

5 PC6/AD0

MUX
0 0 0 0 0 0 0 0 1 1 STK PNTR PC5/AD1

PORT C
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PC4/AD2
6 PROGRAM COUNTER
PC3/AD3
COND CODE REG 1 1 1H I NZC PC2
7 PC1
PC0
8 SRAM — 192 BYTES
PA7

DATA DIRECTION REGISTER

9 USER EEPROM — 8064 BYTES
PA6
PA5

PORT A
PA4
10 PA3
PA2
11 EEPROM — 128 BYTES
PA1
PA0
12 PB5/SDO PORT B AND
SIOP
VDD
PB6/SDI VSS
REGISTERS
13 PB7/SCK AND LOGIC

14 Figure 1-1. Block Diagram

A
16
17
18
19
20
INTRODUCTION MC68HC805P18
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1.3 Mask Options

EEPROM mask option register (MOR) selectable options include the following. For 8
additional information, refer to 8.4 Mask Option Registers (MOR).
• IRQ is edge- and level-sensitive or edge-sensitive only.
2
• SIOP most significant bit (MSB) first or least significant bit (LSB) first 3
• SIOP clock rate set to oscillator divided by 2, 4, 8, or 16
• COP watchdog timer enabled or disabled 4
• Stop instruction enabled or converted to halt mode
5
• Option to enable clock output pin to replace PD5
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• Option to individually enable pullups/interrupts on each of the eight port A 6

pins
• LVR reset enabled or disabled 7
8
NOTE
A line over a signal name indicates an active low signal. For example,
9
RESET is active high and RESET is active low.
10
Any reference to voltage, current, or frequency specified in the
following sections will refer to the nominal values. The exact values 11
and their tolerance or limits are specified in SECTION 13
ELECTRICAL SPECIFICATIONS. 12
13
14
A
16
17
18
19
20
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1.4 Functional Pin Description

8 The following paragraphs describe the functionality of each pin on the
MC68HC805P18 package. Pins connected to subsystems described in other
2 sections provide a reference to the section instead of a detailed functional
description.The pinout is shown in Figure 1-2.
3
4 RESET 1 28 VDD
IRQ 2 27 OSC1

5 PA7
PA6
3
4
26
25
OSC2
PD7/TCAP
PA5 5 24 TCMP
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6 PA4 6 23 PD5/CKOUT
PA3 7 22 PC0
7 PA2 8 21 PC1
PA1 9 20 PC2

8 PA0
SDO/PB5
10
11
19
18
PC3/AD3
PC4/AD2
SDI/PB6 12 17 PC5/AD1
9 SCK/PB7 13 16 PC6/AD0
VSS 14 15 PC7/VREFH

10
Figure 1-2. User Mode Pinout
11
1.4.1 VDD and VSS
12
Power is supplied to the MCU through VDD and VSS. VDD is connected to a
regulated positive supply and VSS is connected to ground.
13
Very fast signal transitions occur on the MCU pins. The short rise and fall times
14 place very high short-duration current demands on the power supply. To prevent
noise problems, take special care to provide good power supply bypassing at the
A MCU. Use bypass capacitors with good high-frequency characteristics, and
position them as close to the MCU as possible. Bypassing requirements vary,
depending on how heavily the MCU pins are loaded.
16
17
18
19
20
INTRODUCTION MC68HC805P18
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1.4.2 OSC1 and OSC2

The OSC1 and OSC2 pins are the control connections for the on-chip oscillator. 8
The OSC1 and OSC2 pins can accept the following:
1. A crystal as shown in Figure 1-3(a)
2
2. A ceramic resonator as shown in Figure 1-3(a) 3
3. An external clock signal as shown in Figure 1-3(b)

The frequency, fosc, of the oscillator or external clock source is divided by two to
4
produce the internal PH2 bus clock operating frequency, fop. The oscillator cannot
be turned off by software if the stop-to-halt conversion is enabled via mask option 5
register 1. Refer to 8.4 Mask Option Registers (MOR).
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6
1.4.3 Crystal
7
The circuit in Figure 1-3(a) shows a typical oscillator circuit for an AT-cut, parallel
resonant crystal. Follow the crystal manufacturer’s recommendations, as the 8
crystal parameters determine the external component values required to provide
maximum stability and reliable startup. The load capacitance values used in the
oscillator circuit design should include all stray capacitances. Mount the crystal and 9
components as close as possible to the pins for startup stabilization and to
minimize output distortion. 10
Ceramic Resonator 11
In cost-sensitive applications, use a ceramic resonator instead of a crystal. Use
the circuit in Figure 1-3(a) for a ceramic resonator and follow the resonator 12
manufacturer’s recommendations, as the resonator parameters determine the
external component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should include
13
all stray capacitances. Mount the resonator and components as close as
possible to the pins for startup stabilization and to minimize output distortion. 14
External Clock A
An external clock from another CMOS-compatible device can be connected to
the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b). 16
17
18
19
20
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TO VDD (OR STOP) MCU TO VDD (OR STOP) MCU

8
2
OSC1 OSC2 OSC1 OSC2

3 4.7 MΩ
UNCONNECTED

4
EXTERNAL CLOCK
5
37 pF 37 pF
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6
(a) (b)
External Clock Source
7 Crystal or Ceramic
Resonator Connections Connections

8 Figure 1-3. Oscillator Connections

9 1.4.4 Reset (RESET)

10 Driving this input low will reset the MCU to a known startup state. As an output,
the RESET pin indicates that an internal MCU reset has occurred. The RESET pin
11 contains an internal Schmitt trigger to improve its noise immunity. Refer to
SECTION 5 RESETS.
12
1.4.5 Port A (PA0 through PA7)
13 These eight I/O pins comprise port A. The state of any pin is software
programmable and all port A lines are configured as inputs during power-on or
14 reset. The pullups and interrupt options (active low) on the port A pins can be
individually programmed in the mask option register 2 (MOR2). For further
A information, refer to SECTION 4 INTERRUPTS and SECTION 7 INPUT/OUTPUT
PORTS.
16
17
18
19
20
INTRODUCTION MC68HC805P18
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1.4.6 Port B (PB5/SDO, PB6/SDI, and PB7/SCK)

These three I/O pins comprise port B and are shared with the SIOP 8
communications subsystem. The state of any pin is software programmable and all
port B lines are configured as inputs during power-on or reset. For further 2
information, refer to SECTION 7 INPUT/OUTPUT PORTS and SECTION 11
SERIAL INPUT/OUTPUT PORT. 3
1.4.7 Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH) 4
These eight I/O pins comprise port C and are shared with the A/D converter
subsystem. The state of any pin is software programmable and all port C lines are
5
configured as inputs during power-on or reset. Port pins PC0 and PC1 are capable
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of sourcing and sinking high currents. For further information, refer to SECTION 7 6
INPUT/OUTPUT PORTS and SECTION 9 ANALOG-TO-DIGITAL CONVERTER.
7
1.4.8 Port D (PD5/CKOUT and PD7/TCAP)
8
These two I/O pins comprise port D, and one of them is shared with the 16-bit timer
subsystem. The state of PD5/CKOUT is software programmable and is configured
as an input during power-on or reset (unless clock output has been selected). PD7
9
is always an input; it may be read at any time, regardless of the mode of operation
the 16-bit timer may be in. For further information, refer to SECTION 7 10
INPUT/OUTPUT PORTS and SECTION 10 16-BIT TIMER. The PD5/CKOUT pin
can be turned into a clock output pin by programming mask option register 1. Clock 11
output is a buffered OSC2 signal with a CMOS output driver.
12
1.4.9 TCMP

This pin is the output from the 16-bit timer’s output compare function. It is low after
13
reset. For further information, refer to SECTION 10 16-BIT TIMER.
14
1.4.10 Maskable Interrupt Request (IRQ)
A
This input pin drives the asynchronous interrupt function of the MCU. The MCU will
complete the current instruction being executed before it responds to the IRQ 16
interrupt request. When IRQ is driven low, the event is latched internally to signify
an interrupt has been requested. When the MCU completes its current instruction, 17
the interrupt latch is tested. If the interrupt latch is set and the interrupt mask bit
(I bit) in the condition code register is clear, the MCU will begin the interrupt
sequence. 18
19
20
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Depending on the programming option selected in the mask option register 1

8 (MOR1), the IRQ pin will trigger this interrupt on either a negative-going edge at
the IRQ pin and/or while the IRQ pin is held in the low state. In either case, the IRQ
pin must be held low for at least one tILIH time period. If the edge- and
2 level-sensitive edge is programmed in the MOR1,the IRQ input requires an
external resistor connected to VDD for wired-OR operation. If the IRQ pin is not
3 used, it must be tied to the VDD supply. The IRQ pin contains an internal Schmitt
trigger as part of its input circuitry to improve noise immunity. For further
4 information, refer to SECTION 4 INTERRUPTS.

5
NOTE
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6 If the voltage level applied to the IRQ pin exceeds VDD, it may affect
the MCU’s mode of operation. See SECTION 6 OPERATING
7 MODES.

8
9
10
11
12
13
14
A
16
17
18
19
20
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GENERAL RELEASE SPECIFICATION

8
2
SECTION 2
MEMORY 3
4
2.1 Introduction

The MC68HC805P18 utilizes 14 address lines to access an internal memory space 5

covering 16 Kbytes. This memory space is divided into I/O, RAM, EEPROM, and
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boot ROM areas. 6

2.2 User Mode Memory Map 7
When the MC68HC805P18 is in the user mode, the 32 bytes of I/O, 192 bytes of 8
RAM, 128 bytes of EEPROM, 8000 bytes of program EEPROM, 48 bytes of user
page zero EEPROM, and 16 bytes of user vectors EEPROM are all active as
shown in Figure 2-1. 9

2.3 I/O and Control Registers

10
Figure 2-2 through Figure 2-4 briefly describe the I/O and control registers at 11
locations $0000–$001F. Reading unimplemented bits will return unknown states,
and writing unimplemented bits will be ignored. 12
2.4 RAM 13
The user RAM consists of 192 bytes (including the stack) at locations $0050
through $010F. The stack begins at address $00FF. The stack pointer can access 14
64 bytes of RAM from $00FF to $00C0.
A
NOTE 16
Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking 17
from an interrupt or subroutine call.
18
19
20
MEMORY
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2.5 EEPROM
8 The EEPROM is located at address $0140 and consists of 128 bytes.
Programming the EEPROM can be done by the user on a single byte basis by
2 manipulating the programming register, located at address $001C. Refer to
SECTION 8 EEPROM for a discussion of the EEPROM.
3
2.6 User EEPROM
4
There are 8064 bytes of user EEPROM available, consisting of 8000 bytes at
locations $1FC0 through $3EFF, 48 bytes in page zero locations $0020 through
5 $004F, and 16 additional bytes for user vectors at locations $3FF0 through $3FFF.
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6 This EEPROM can be programmed only in bootloader mode. Refer to 6.2.2

Bootloader Mode for more details.
7
8
9
10
11
12
13
14
A
16
17
18
19
20
MEMORY MC68HC805P18
2-2
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$0000 0000 $0000

I/O
$001F 32 BYTES 0031 8
$0020 0032
USER EEPROM I/O REGISTERS
$004F 48 BYTES 0079 SEE FIGURE 2-2
2
$0050 0080
INTERNAL RAM
192 BYTES
$00BF
$00C0 STACK
0191
0192 $001F
3
$00FF 64 BYTES 0255
$010F
UNUSED
0271
0272
4
$013F 48 BYTES 0319
0320 COP CONTROL REGISTER $3FF0
$0140
EEPROM UNIMPLEMENTED $3FF1 5
$01BF 128 BYTES 0447 UNIMPLEMENTED $3FF2
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$01C0 0448
UNUSED
UNIMPLEMENTED $3FF3 6
7728 BYTES UNIMPLEMENTED $3FF4

$1FBF 8127 UNIMPLEMENTED $3FF5 7

$1FC0 8128 UNIMPLEMENTED $3FF6
USER EEPROM
8000 BYTES
UNIMPLEMENTED
TIMER VECTOR (HIGH BYTE)
$3FF7
$3FF8
8
$3EFF 16127
TIMER VECTOR (LOW BYTE) $3FF9
$3F00
$3F01 MASK OPTION REGISTER
16128
IRQ VECTOR (HIGH BYTE) $3FFA
9
$3F02 16130 IRQ VECTOR (LOW BYTE) $3FFB
UNUSED
238 BYTES
SWI VECTOR (HIGH BYTE) $3FFC 10
$3FEF 16367 SWI VECTOR (LOW BYTE) $3FFD
$3FF0 16368
USER VECTORS EEPROM RESET VECTOR (HIGH BYTE) $3FFE 11
$3FFF 16 BYTES 16383 RESET VECTOR (LOW BYTE) $3FFF

12
Figure 2-1. MC68HC805P18 User Mode Memory Map
13
14
A
16
17
18
19
20
MEMORY
Rev. 1.0
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PORT A DATA REGISTER $0000

8 PORT B DATA REGISTER $0001
PORT C DATA REGISTER $0002
$0003
2 PORT D DATA REGISTER
PORT A DATA DIRECTION REGISTER $0004
PORT B DATA DIRECTION REGISTER $0005
3 PORT C DATA DIRECTION REGISTER $0006
PORT D DATA DIRECTION REGISTER $0007
$0008
4 UNIMPLEMENTED
UNIMPLEMENTED $0009
SIOP CONTROL REGISTER $000A
5 SIOP STATUS REGISTER $000B
SIOP DATA REGISTER $000C
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6 UNIMPLEMENTED
UNIMPLEMENTED
$000D
$000E
UNIMPLEMENTED $000F
7 UNIMPLEMENTED $0010
RESERVED $0011

8 TIMER CONTROL REGISTER

TIMER STATUS REGISTER
$0012
$0013
INPUT CAPTURE MOST SIGNIFICANT BIT $0014
9 INPUT CAPTURE LEAST SIGNIFICANT BIT $0015
OUTPUT COMPARE MOST SIGNIFICANT BIT $0016

10 OUTPUT COMPARE LEAST SIGNIFICANT BIT

TIMER MOST SIGNIFICANT BIT
$0017
$0018
TIMER LEAST SIGNIFICANT BIT $0019
11 ALTERNATE COUNTER MOST SIGNIFICANT BIT $001A
ALTERNATE COUNTER LEAST SIGNIFICANT BIT $001B

12 EEPROM PROGRAMMING REGISTER

A/D CONVERTER DATA REGISTER
$001C
$001D
A/D CONVERTER CONTROL AND STATUS REGISTER $001E
13 RESERVED $001F

14 Figure 2-2. MC68HC805P18 I/O and Control Registers Memory Map

A
16
17
18
19
20
MEMORY MC68HC805P18
2-4
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READ
ADDR REGISTER
WRITE
7 6 5 4 3 2 1 0
8
PORT A DATA R
$0000
PORTA W
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
2
PORT B DATA R 0 0 0 0 0
$0001 PB7 PB6 PB5
PORTB W 3
PORT C DATA R
$0002 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PORTC W
4
PORT D DATA R PD7 0 1 0 0 0 0
$0003 PD5
PORTD W
PORT A DATA DIRECTION R
5
$0004 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRA
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W
PORT B DATA DIRECTION R 1 1 1 1 1 6
$0005 DDRB7 DDRB6 DDRB5
DDRB W

$0006
PORT C DATA DIRECTION R
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
7
DDRC W

$0007
PORT D DATA DIRECTION R 0 0
DDRD5
0 0 0 0 0 8
DDRD W

$0008
UNIMPLEMENTED R
W
9
UNIMPLEMENTED R
$0009
W
10
SIOP CONTROL REGISTER R 0 0 0 0 0 0
$000A
SCR W
SPE MSTR
11
SIOP STATUS REGISTER R SPIF DCOL 0 0 0 0 0 0
$000B
SSR W 12
SIOP DATA REGISTER R
$000C SDR7 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0
SDR W
13
UNIMPLEMENTED R
$000D
W
UNIMPLEMENTED R
14
$000E
W
UNIMPLEMENTED R A
$000F
W
16
UNIMPLEMENTED RESERVED
17
Figure 2-3. MC68HC805P18 I/O and Control Registers $0000–$000F
18
19
20
MEMORY
Rev. 1.0
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READ
8 ADDR REGISTER
WRITE
7 6 5 4 3 2 1 0

UNIMPLEMENTED R
2 $0010
W
RESERVED R
3 $0011
W
TIMER CONTROL REGISTER R 0 0 0
$0012 ICIE OCIE TOIE IEDG OLVL
4 TCR W
TIMER STATUS REGISTER R ICF OCF TOF 0 0 0 0 0
$0013
TSR
5 W
R ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0
INPUT CAPTURE MSB
$0014
ICRH
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W
6 INPUT CAPTURE LSB R ICRL7 ICRL6 ICRL5 ICRL4 ICRL3 ICRL2 ICRL1 ICRL0
$0015
ICRL W
7 OUTPUT COMPARE MSB R
$0016 OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
OCRH W
8 $0017
OUTPUT COMPARE LSB R
OCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0
OCRL W

9 $0018
TIMER MSB
TMRH
R TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0
W
R TMRL7 TMRL6 TMRL5 TMRL4 TMRL3 TMRL2 TMRL1 TMRL0
10 $0019
TIMER LSB
TMRL W
ALTERNATE COUNTER MSB R ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0
11 $001A
ACRH W
ALTERNATE COUNTER LSB R ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0
12 $001B
ACRL W
EEPROM Programming R 0 0
$001C CPEN ER1 ER0 LATCH EERC EEPGM
13 Register W
A/D CONVERSION DATA R AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
$001D
ADC
14 W
R CC 0 0
A/D STATUS AND CONTROL
$001E ADON CH2 CH1 CH0
ADSC W
A RESERVED R
$001F
W
16
UNIMPLEMENTED RESERVED
17
Figure 2-4. MC68HC805P18 I/O and Control Registers $0010-$001F
18
19
20
MEMORY MC68HC805P18
2-6
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8
2
SECTION 3
CENTRAL PROCESSING UNIT 3
4
3.1 Introduction

This section describes the CPU registers. 5

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3.2 CPU Registers

6
The five CPU registers are shown in Figure 3-1 and the interrupt stacking order are 7
shown in Figure 3-2.
8
7 0
A ACCUMULATOR 9
7 0
X INDEX REGISTER 10
12 0

PC PROGRAM COUNTER 11
12 7 0
0 0 0 0 0 1 1 SP STACK POINTER 12
CCR
H I N Z C CONDITION CODE REGISTER
13

Figure 3-1. Programming Model 14

A
16
17
18
19
20
CENTRAL PROCESSING UNIT
Rev. 1.0
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7 0 STACK
8 1 1 1 CONDITION CODE REGISTER I
N
R ACCUMULATOR T
2 INCREASING
MEMORY
E
T
INDEX REGISTER
E
R
DECREASING
MEMORY
U
ADDRESSES R ADDRESSES
R U
3 N PCH P
T
PCL
UNSTACK
4 NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
5
Figure 3-2. Stacking Order
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6
3.2.1 Accumulator (A)
7 The accumulator is a general-purpose 8-bit register used to hold operands and
results of arithmetic calculations or data manipulations.
8 7 0
A
9
10 3.2.2 Index Register (X)

11 The index register is an 8-bit register used for the indexed addressing value to
create an effective address. The index register may also be used as a temporary
12 storage area.
7 0
13 X

14
A
16
17
18
19
20
CENTRAL PROCESSING UNIT MC68HC805P18
3-2
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3.2.3 Condition Code Register (CCR)

The CCR is a 5-bit register in which four bits are used to indicate the results of the 8
instruction just executed, and the fifth bit indicates whether interrupts are masked.
These bits can be individually tested by a program, and specific actions can be 2
taken as a result of their state. Each bit is explained in the following paragraphs.
CCR 3
H I N Z C
4
Half Carry (H)
5
This bit is set during ADD and ADC operations to indicate that a carry occurred
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between bits 3 and 4. 6

Interrupt (I)
When this bit is set, the timer and external interrupt are masked (disabled). If an
7
interrupt occurs while this bit is set, the interrupt is latched and processed as
soon as the interrupt bit is cleared. 8
Negative (N) 9
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was negative. 10
Zero (Z) 11
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was zero. 12
Carry/Borrow (C)
13
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit
(ALU) occurred during the last arithmetic operation. This bit is also affected
during bit test and branch instructions and during shifts and rotates.
14
A
16
17
18
19
20
CENTRAL PROCESSING UNIT
Rev. 1.0
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3.2.4 Stack Pointer (SP)

8 The stack pointer contains the address of the next free location on the stack.
During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer
2 is set to location $00FF. The stack pointer is then decremented as data is pushed
onto the stack and incremented as data is pulled from the stack.
3 When accessing memory, the seven most significant bits are permanently set to
0000011. These seven bits are appended to the six least significant register bits to
4 produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the
5 stack pointer wraps around and loses the previously stored information. A
subroutine call occupies two locations on the stack; an interrupt uses five locations.
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6
12 7 0
0 0 0 0 0 1 1 SP
7
8
3.2.5 Program Counter (PC)
9 The program counter is a 13-bit register that contains the address of the next byte
to be fetched.
10 12 0
PC
11
12
NOTE
13 The M68HC05 CPU core is capable of addressing a 64-Kbyte
memory map. For this implementation, however, the addressing
14 registers are limited to an 8-Kbyte memory map.

A
16
17
18
19
20
CENTRAL PROCESSING UNIT MC68HC805P18
3-4
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8
2
SECTION 4
INTERRUPTS 3
4
4.1 Introduction

The MCU can be interrupted six different ways: 5

• Non-maskable software interrupt instruction (SWI)
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6
• External asynchronous interrupt (IRQ)
• Input capture interrupt (TIMER) 7
• Output compare interrupt (TIMER)
• Timer overflow interrupt (TIMER)
8
• Port A interrupt (if selected via MOR2, bits 0 through 7). 9
Interrupts cause the processor to save the register contents on the stack and to set
the interrupt mask (I bit) to prevent additional interrupts. Unlike reset, hardware 10
interrupts do not cause the current instruction execution to be halted, but are
considered pending until the current instruction is completed. 11
When the current instruction is completed, the processor checks all pending
hardware interrupts. If interrupts are not masked (I bit in the condition code register 12
is clear) and the corresponding interrupt enable bit is set, the processor proceeds
with interrupt processing. Otherwise, the next instruction is fetched and executed. 13
The SWI is executed the same as any other instruction, regardless of the I bit state.

When an interrupt is to be processed, the CPU puts the register contents on the 14
stack, sets the I bit in the CCR, and fetches the address of the corresponding
interrupt service routine from the vector table at locations $3FF0 through $3FFF. If A
more than one interrupt is pending when the interrupt vector is fetched, the
interrupt with the highest vector location shown in Table 4-1 will be serviced first. 16
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the CPU state to be recovered from the 17
stack and normal processing to resume at the next instruction that was to be
executed when the interrupt took place. Figure 4-1 shows the sequence of events 18
that occurs during interrupt processing.
19
20
INTERRUPTS
Rev. 1.0
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Table 4-1. Vector Addresses for Interrupts and Reset

8 Register Flag Name Interrupts CPU Interrupt Vector Address

2 N/A N/A Reset RESET $3FF3–$3FFF

N/A N/A Software SWI $3FFC–$3FFD

3 N/A N/A External Interrupt IRQ $3FFA–$3FFB

TSR ICF Timer Input Capture TIMER $3FF8–$3FF9

4
TSR OCF Timer Output Compare TIMER $3FF8–$3FF9

5 TSR TOF Timer Overflow TIMER $3FF8–$3FF9

N/A N/A Unimplemented N/A $3FF6–$3FF7

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6 N/A N/A Unimplemented N/A $3FF4–$3FF5

7 N/A N/A Unimplemented N/A $3FF2–$3FF3

N/A N/A Unimplemented N/A $3FF0–$3FF1

8
4.2 Interrupt Types
9
The interrupts fall into three categories: reset, software, and hardware.
10
4.2.1 Reset Interrupt Sequence
11 The reset function is not in the strictest sense an interrupt; however, it is acted upon
in a similar manner as shown in Figure 4-1. A low level input on the RESET pin or
12 internally generated RST signal causes the program to vector to its starting
address which is specified by the contents of memory locations $3FFE and $3FFF.
13 The I bit in the condition code register is also set. The MCU is configured to a
known state during this type of reset as described in SECTION 5 RESETS.
14
4.2.2 Software Interrupt (SWI)
A The SWI is an executable instruction. It is also a non-maskable interrupt since it is
executed regardless of the state of the I bit in the CCR. As with any instruction,
16 interrupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address for the SWI instruction is
17 specified by the contents of memory locations $3FFC and $3FFD.

18 4.2.3 Hardware Interrupts

19 All hardware interrupts are maskable by the I bit in the CCR. If the I bit is set, all
hardware interrupts (internal and external) are disabled. Clearing the I bit enables
the hardware interrupts. Four hardware interrupts are explained in the following
20 paragraphs.

INTERRUPTS MC68HC805P18
4-2
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FROM RESET
8
Y IS I BIT
SET?
2

IRQ
N
CLEAR IRQ
3
Y
INTERRUPT? REQUEST

N
LATCH
4
TIMER Y
INTERRUPT? 5
N STACK
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PC, X, A, CC 6
SET
I BIT IN CCR
7

LOAD PC FROM:
8
SWI: $3FFC, $3FFD
IRQ: $3FFA-$3FFB
TIMER: $3FF8-$3FF9
9
10
FETCH NEXT
INSTRUCTION 11
SWI
INSTRUCTION?
Y 12
N
RTI Y
RESTORE RESISTERS 13
INSTRUCTION? FROM STACK
CC, A, X, PC
N 14
EXECUTE INSTRUCTION
A
Figure 4-1. Interrupt Processing Flowchart 16
External Interrupt (IRQ) 17
The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector
flip-flop is latched on the falling edge of IRQ. If either the output from the internal 18
edge detector flip-flop or the level on the IRQ pin is low, a request is
synchronized to the CPU to generate the IRQ interrupt. If the edge-sensitive 19
only option is selected, the output of the internal edge detector flip-flop is
sampled and the input level on the IRQ pin is ignored. If port A interrupts are 20
INTERRUPTS
Rev. 1.0
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programmed as an option, a port A interrupt will use the same vector. The
8 interrupt service routine address is specified by the contents of memory
locations $3FFA and $3FFB.
2
3 NOTE
The internal interrupt latch is cleared 9 PH2 clock cycles after the
4 interrupt is recognized (after location $3FFA is read). Therefore,
another external interrupt pulse could be latched during the IRQ
5 service routine.
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6
7 NOTE
When the edge- and level-sensitive option is selected, the voltage
8 applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed.
9
10 The IRQ pin is one source of an IRQ interrupt and a mask option can also enable
the port A pins (PA0 through PA7) to act as other IRQ interrupt sources. These
11 sources are all combined into a single ORing function to be latched by the IRQ
latch.
12
IRQ PIN
13 TO BIH & BIL
INSTRUCTION
PA0 SENSING
DDRA0
14 PA0 IRQ INHIBIT
(MASK OPTION) VDD

A : :
IRQ
: :
: : LATCH TO IRQ
16 : : PROCESSING
IN CPU
PA7 : R
DDRA7
17 PA7 IRQ INHIBIT
(MASK OPTION) RST

18 IRQ VECTOR FETCH

MASK OPTION
(IRQ LEVEL)
19
Figure 4-2. IRQ Function Block Diagram
20
INTERRUPTS MC68HC805P18
4-4
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Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of the
IRQ pin or a port A pin if port A interrupts have been enabled. If edge-only 8
sensitivity is chosen by a mask option, only the IRQ latch output can activate a
request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ
interrupt sensitive to the following cases: 2
1. Falling edge on the IRQ pin with all enabled port A interrupt pins at a high
level.
3
2. Falling edge on any enabled port A interrupt pin with all other enabled 4
port A interrupt pins and the IRQ pin at a high level.
If level sensitivity is chosen, the active high state of the IRQ input can also 5
activate an IRQ request to the CPU to generate the IRQ interrupt sequence.
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This makes the IRQ interrupt sensitive to the following cases:

6
1. Low level on the IRQ pin
2. Falling edge on the IRQ pin with all enabled port A interrupt pins at a high 7
level
3. Low level on any enabled port A interrupt pin 8
4. Falling edge on any enabled port A interrupt pin with all enabled port A
interrupt pins and the IRQ pin at a high level 9
This interrupt is serviced by the interrupt service routine located at the address
specified by the contents of $3FFA and $3FFB. The IRQ latch is automatically
10
cleared by entering the interrupt service routine.
11
Optional External Interrupts (PA0–PA7)
The IRQ interrupt can be triggered by the inputs on the PA0 through PA7 port 12
pins if enabled by individual mask options. With pullup enabled, each port A pin
can activate the IRQ interrupt function and the interrupt operation will be the 13
same as for inputs to the IRQ pin. Once enabled by mask option, each individual
port A pin can be disabled as an interrupt source if its corresponding DDR bit is 14
configured for output mode.
A
NOTE
16
The BIH and BIL instructions apply to the output of the logic OR
function of the enabled PA0 through PA7 interrupt pins and the IRQ 17
pin. The BIH and BIL instructions do not test only the state of the IRQ
pin.
18
19
20
INTERRUPTS
Rev. 1.0
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8 NOTE
If enabled, the PA0 through PA7 pins will cause an IRQ interrupt only
2 if these individual pins are configured as inputs.

3
Input Capture Interrupt
4
The input capture interrupt is generated by the 16-bit timer as described in
SECTION 10 16-BIT TIMER. The input capture interrupt flag is located in
5 register TSR and its corresponding enable bit can be found in register TCR. The
I bit in the CCR must be clear in order for the input capture interrupt to be
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6 enabled. The interrupt service routine address is specified by the contents of

memory locations $3FF8 and $3FF9.
7
Output Compare Interrupt
8 The output compare interrupt is generated by the 16-bit timer as described in
SECTION 10 16-BIT TIMER. The output compare interrupt flag is located in
register TSR and its corresponding enable bit can be found in register TCR. The
9 I bit in the CCR must be clear in order for the output compare interrupt to be
enabled. The interrupt service routine address is specified by the contents of
10 memory locations $3FF8 and $3FF9.

11 Timer Overflow Interrupt

The timer overflow interrupt is generated by the 16-bit timer as described in
12 SECTION 10 16-BIT TIMER. The timer overflow interrupt flag is located in
register TSR and its corresponding enable bit can be found in register TCR. The
13 I bit in the CCR must be clear in order for the timer overflow interrupt to be
enabled. This internal interrupt will vector to the interrupt service routine located
at the address specified by the contents of memory locations $3FF8 and $3FF9.
14
A
16
17
18
19
20
INTERRUPTS MC68HC805P18
4-6
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8
2
SECTION 5
RESETS 3
4
5.1 Introduction

The MCU can be reset from four sources: one external input and three internal 5
reset conditions. The RESET pin is an input with a Schmitt trigger as shown in
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Figure 5-1. The CPU and all peripheral modules will be reset by the RST signal 6
which is the logical OR of internal reset functions and is clocked by PH2.
7
5.2 External Reset (RESET)
The RESET input is the only external reset and is connected to an internal Schmitt
8
trigger. The external reset occurs whenever the RESET input is driven below the
lower threshold and remains in reset until the RESET pin rises above the upper 9
threshold. The upper and lower thresholds are given in SECTION 13
ELECTRICAL SPECIFICATIONS. 10

TO IRQ
11
IRQ
LOGIC
D
MODE
12
LATCH
SELECT
RESET
13
R
(PULSE WIDTH =4 x E-CLK)
PH2
CLOCKED
ONE-SHOT 14
OSC
COP WATCHDOG
A
DATA
(COPR)
ADDRESS

VDD
LOW-VOLTAGE CPU 16
RESET (LVR)
S

VDD
POWER-ON RESET
(POR)
D
LATCH
TO OTHER 17
PERIPHERALS
RST
PH2
18
Figure 5-1. Reset Block Diagram 19
20
RESETS
Rev. 1.0
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5.3 Internal Resets

8 The three internally generated resets are the initial power-on reset (POR), the COP
watchdog timer, and low-voltage reset (LVR) functions.
2
5.3.1 Power-On Reset (POR)
3
The internal POR is generated at power-up to allow the clock oscillator to stabilize.
4 The POR is strictly for power turn-on conditions and should not be used to detect
a drop in the power supply voltage. There is a 4064 PH2 clock cycle oscillator
stabilization delay after the oscillator becomes active.
5
The POR will generate the RST signal and reset the MCU. The POR will also pull
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6 the RESET pin low at the same time, allowing external devices to be reset with the
MCU. If any other reset function is active at the end of this 4064 PH2 clock cycle
7 delay, the RST signal will remain active until the other reset condition(s) end.

8 5.3.2 Computer Operating Properly (COP) Reset

When the COP watchdog timer is enabled (by MOR1, bit 0), the internal COP reset
9 is generated automatically by a timeout of the COP watchdog timer. This timer is
implemented with an 18-stage ripple counter that provides a time-out period of
10 65.5 ms when a 4-MHz oscillator is used. The COP watchdog counter is cleared
by writing a logical zero to bit zero at location $3FF0.
11 The COP register is shared with the most significant bit (MSB) of an
unimplemented user interrupt vector as shown in Figure 5-2. Reading this location
12 will return the MSB of the unimplemented user interrupt vector. Writing to this
location will clear the COP watchdog timer.
13
Bit 7 6 5 4 3 2 1 Bit 0
14
Read: 0 0 0 0 0 0 0 0
$3FF0
A Write: R COPR

Reset: — — — — — — — —
16 = Unimplemented R = Reserved

Figure 5-2. Unimplemented Vector and

17 COP Watchdog Timer Register

18
19
20
RESETS MC68HC805P18
5-2
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5.3.3 Low-Voltage Reset (LVR)

If the LVR has been enabled via MOR1, the internal LVR reset is generated when 8
the supply voltage to the VDD pin falls below a nominal 3.80 Vdc. The LVR
threshold is not intended to be an accurate and stable trip point, but is intended to 2
ensure that the CPU will be held in reset when the VDD supply voltage is below
reasonable operating limits. If the LVR is tripped for a short time, the LVR reset 3
signal will last at least two cycles of the CPU bus clock, PH2.

The LVR will generate the RST signal which will reset the CPU and other 4
peripherals. Also, the LVR will establish the mode of operation based on the state
of the IRQ pin at the time the LVR signal ends. If any other reset function is active 5
at the end of the LVR reset signal, the RST signal will remain in the reset condition
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until the other reset condition(s) end. 6

7
NOTE
The voltage of the IRQ pin must be between 0–VDD volts to stay in 8
the normal operation mode.
9
10
11
12
13
14
A
16
17
18
19
20
RESETS
Rev. 1.0
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8
2
SECTION 6
OPERATING MODES 3
4
6.1 Introduction

This section describes the user, bootloader, and low-power modes. In addition the 5
computer operating properly (COP) timer considerations are discussed.
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6
6.2 User Modes
7
The MC68HC805P18 has two modes of operation available to the user:
• User mode 8
• Bootloader mode
9
The mode of operation is determined by the voltages on the IRQ and PD7/TCAP
pins on the rising edge of the external RESET pin. Table 6-1 shows the condition 10
required to go into each mode.

Table 6-1. Operating Mode Conditions 11

RESET IRQ TCAP Mode
12
0–5 V 0–5 V User

2 x VDD 5V Bootloader 13
14
6.2.1 User Mode

The user mode allows the MCU to function as a self-contained microcontroller with A
maximum use of the pins for on-chip peripheral functions. All address and data
activity occurs within the MCU and is not available externally. User mode is entered 16
on the rising edge of RESET, if the IRQ pin is within the normal operating voltage
range. In the user mode, there is an 8-bit I/O port, a second 8-bit I/O port shared 17
with the analog-to-digital (A/D) subsystem, one 3-bit I/O port shared with the serial
input/output port (SIOP), and a 2-bit I/O port shared with the16-bit timer
subsystem. 18
19
20
OPERATING MODES
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6.2.2 Bootloader Mode

8 Bootloader mode is entered upon the rising edge of RESET if the IRQ pin is twice
the VDD voltage and the TCAP/PD7 pin is at logic one. In bootloader mode, the
2 user EEPROM and mask option register (MOR) bytes can be erased and
programmed. Figure 6-1 shows the bootloader circuit. PTC4 determines whether
3 erasing or programming will occur as shown in Table 6-2.

4 Table 6-2. Bootloader Functions

5 PTC4 Function

0 Bulk Erase/Blank Verify

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6 1 Bulk Erase/Program/Verify

7
Bulk Erase/Blank Verify
8 To use the bootloader circuit to bulk erase the user EEPROM, follow this
sequence:
9 1. Close RESET switch and PTC4 switch so these pins are held low.
2. Apply 12 V power to IRQ.
10 3. Release RESET.

11 4. Programming LED will turn on while bulk erase is occurring.

5. When bulk erase is finished, programming LED will turn off.
12 6. When blank verify is finished, verify LED will turn on.
7. Close RESET switch.
13
8. Remove 12 V from IRQ, then remove power.
14
A
16
17
18
19
20
OPERATING MODES MC68HC805P18
6-2
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12 V

1 KΩ
27C128 MC14040B 8
IRQ
PA0 DQ1 A11 Q12
OSC1 PA1 DQ2 A10 Q11
2
4 MHz
PA2 DQ3 A9 Q10
OSC2 3
PA3 DQ4 A8 Q9

10 MΩ
PA4 DQ5 A7 Q8 4
PA5 DQ6 A6 Q7
20 pF 20 pF
PA6 DQ7 A5 Q6 5
PA7 DQ8 A4 Q5
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VDD
CE A3 Q4
6
10 KΩ OE A2 Q3

A1 Q2
7
RESET
PC6 A12 A0 Q1
8
1 µF PC7 A13

RST CLK
VDD PC5 (SYNC) 9
4.7 KΩ VDD
10
4.7 KΩ
PROG
PB7
TCAP 11
PC1
390 Ω
PC2
VDD
12
VERF

390 Ω
PB6 10 KΩ 13
PC4
VDD = 5.0 V
PC3
14
4.7 KΩ A
16
17
Figure 6-1. Bootloader Circuit
18
19
20
OPERATING MODES
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Bulk Erase/Program Verify

8 To use the bootloader circuit to bulk erase, program, and verify the user
EEPROM, follow this sequence:
2 1. Close RESET switch so RESET is low upon power up.
2. Open PTC4 switch so PTC4 remains high during reset sequence.
3
3. Make sure code to be loaded into user EEPROM is in the external
4 EPROM (shown as 27C128).
4. Apply 12 V power to IRQ.
5 5. Release RESET.
6. Programming LED will be on during bulk erase and programming. (The
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6 code in the 27C128 will be loaded into the user EEPROM and MOR.)
7. When programming is finished, the programming LED will turn off.
7
8. When the verify is finished, verify LED will turn on.
8 9. Close RESET switch.
10. Remove 12 V from IRQ, then remove power.
9
10 NOTE

11 Bootloader mode is the only mode in which the user can program the
8K user EEPROM and MOR. The 128-byte EEPROM can be
programmed in user mode.
12
13
14
A
16
17
18
19
20
OPERATING MODES MC68HC805P18
6-4
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6.3 Low-Power Modes

The MC68HC805P18 is capable of running in a low-power mode in each of its 8

configurations. The WAIT and STOP instructions provide modes that reduce the
power required for the MCU by stopping various internal clocks and/or the on-chip 2
oscillator. The STOP and WAIT instructions are not normally used if the COP
watchdog timer is enabled (MOR1, bit 0). The stop conversion to halt option 3
(MOR1, bit 5) is used to modify the behavior of the STOP instruction from stop
mode to halt mode. The flow of the stop, halt, and wait modes is shown in
Figure 6-2.
4
5
6.4 STOP Instruction
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The STOP instruction can result in one of two modes of operation depending on 6
the option programmed in the mask option register 1. If the stop conversion to halt
option (MOR1,bit 5) is not chosen, the STOP instruction will behave like a normal 7
STOP instruction in the M68HC805 Family and place the MCU in the stop mode.
If the stop conversion to halt option is chosen, the STOP instruction will behave like 8
a WAIT instruction (with the exception of a brief delay at startup) and place the
MCU in the halt mode.
9
6.4.1 Stop Mode
10
Execution of the STOP instruction (without conversion to halt) places the MCU in
its lowest-power consumption mode. In the stop mode, the internal oscillator is 11
turned off stopping all internal processing including the COP watchdog timer. The
RC oscillator that feeds the EEPROM and the A/D converter is also stopped. 12
Execution of the STOP instruction automatically clears the I bit in the condition
code register so that the IRQ external interrupt is enabled. All other registers and
memory remain unaltered. All input/output lines remain unchanged. 13
The MCU can be brought out of the stop mode only by an IRQ external interrupt 14
(or port A, if selected as an option in the MOR2) or an externally generated reset.
When exiting the stop mode, the internal oscillator will resume after a 4064 PH2
clock cycle oscillator stabilization delay.
A
16
17
18
19
20
OPERATING MODES
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STOP HALT WAIT

8
STOP EXTERNAL OSCILLATOR ACTIVE
2 TO HALT
Y AND
OPTION? INTERNAL TIMER CLOCK ACTIVE

3 N
STOP RC OSCILLATOR
EXTERNAL OSCILLATOR ACTIVE
STOP EXTERNAL OSCILLATOR, STOP INTERNAL PROCESSOR AND
STOP INTERNAL TIMER CLOCK,
4 RESET START-UP DELAY
CLOCK, CLEAR I BIT IN CCR INTERNAL TIMER CLOCK ACTIVE

5 STOP RC OSCILLATOR
STOP INTERNAL PROCESSOR
Y
LVR OR
EXTERNAL
STOP INTERNAL PROCESSOR
CLOCK,
RESET? CLEAR I BIT IN CCR
CLOCK, CLEAR I-BIT IN CCR
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6 N

IRQ Y LVR OR
LVR OR
7 EXTERNAL
Y Y EXTERNAL
INTERRUPT?
EXTERNAL
RESET?
RESET?
N
8 N N
IRQ
IRQ TIMER Y
Y EXTERNAL
EXTERNAL Y INTERNAL
9 INTERRUPT? INTERRUPT?
INTERRUPT?

N
N RESTART EXTERNAL OSCILLATOR, N
10 START STABILIZATION DELAY
Y
TIMER
COP INTERNAL
Y
INTERNAL INTERRUPT?
11 RESET?
N
END N
Y
OF STABILIZATION
12 DELAY? Y
COP
INTERNAL
N RESET?

13 RESTART INTERNAL
PROCESSOR CLOCK
N

14 1. FETCH RESET VECTOR

OR
2. SERVICE INTERRUPT
A A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT ROUTINE
16
Figure 6-2. STOP/WAIT Flowcharts
17
18
19
20
OPERATING MODES MC68HC805P18
6-6
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NOTE 8
Execution of the STOP instruction without conversion to halt (via
MOR1) will cause the oscillator to stop, and therefore disable the 2
COP watchdog timer. If the COP watchdog timer is to be used, the
stop mode should be changed to the halt mode by programming the
appropriate option in MOR1.
3
4
6.4.2 Halt Mode 5
Execution of the STOP instruction with the conversion to halt places the MCU in
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this low-power mode. Halt mode consumes the same amount of power as wait 6
mode (both halt and wait modes consume more power than stop mode).
7
In halt mode the PH2 clock is halted, suspending all processor and internal bus
activity. Internal timer clocks remain active, permitting interrupts to be generated
from the 16-bit timer or a reset to be generated from the COP watchdog timer.
8
Execution of the STOP instruction automatically clears the I bit in the condition
code register enabling the IRQ external interrupt. All other registers, memory, and 9
input/output lines remain in their previous states.

If the 16-bit timer interrupt is enabled, it will cause the processor to exit the halt
10
mode and resume normal operation. The halt mode also can be exited when an
IRQ external interrupt (or port A, if selected as an option in the MOR2) or external 11
RESET occurs. When exiting the halt mode, the PH2 clock will resume after a
delay of one to 4064 PH2 clock cycles. This varied delay time is the result of the 12
halt mode exit circuitry testing the oscillator stabilization delay timer (a feature of
the stop mode), which has been free-running (a feature of the wait mode). 13
14
NOTE
The halt mode is not intended for normal use. This feature is provided A
to keep the COP watchdog timer active in the event a STOP
instruction is executed inadvertently. 16
17
18
19
20
OPERATING MODES
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6.4.3 WAIT Instruction

8 The WAIT instruction places the MCU in a low-power mode which consumes more
power than the stop mode. In wait mode the PH2 clock is halted, suspending all
2 processor and internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer and reset to be generated from the
3 COP watchdog timer. Execution of the WAIT instruction automatically clears the I
bit in the condition code register enabling the IRQ external interrupt. All other
4 registers, memory, and input/output lines remain in their previous state.

If the 16-bit timer interrupt is enabled it will cause the processor to exit the wait
5 mode and resume normal operation. The 16-bit timer may be used to generate a
periodic exit from the wait mode. The wait mode may also be exited when an IRQ
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6 or RESET occurs. Note that if port A interrupts (if programmed as an option in the
mask option register 1) will also exit wait mode. However, when exiting the wait
mode, the internal oscillator will not need to wait for 4064 PH2 clock cycles to
7 stabilize as in the stop and halt modes.

8
6.5 COP Watchdog Timer Considerations
9 The COP watchdog timer is active in user mode of operation when programmed
as an option in MOR1. Executing the STOP instruction without conversion to halt
10 (via mask option register1) will cause the COP to be disabled. Therefore, it is
recommended that the STOP instruction be modified to produce halt mode (via
MOR1) if the COP watchdog timer will be enabled.
11
Furthermore, it is recommended that the COP watchdog timer be disabled for
12 applications that will use the halt or wait modes for time periods that will exceed the
COP time-out period.
13 COP watchdog timer interactions are summarized in Table 6-3.

14 Table 6-3. COP Watchdog Timer Recommendations

A IF the following conditions exist: THEN the COP Watchdog

Timer should be:
STOP Instruction Mode Wait Period
16 Halt Mode Selected WAIT Period Less than Enable or Disable COP
via MOR1, Bit 5 COP Time Out via MOR1, Bit 0
17 Halt Mode Selected WAIT Period More Than Disable COP
via MOR1, Bit 5 COP Time Out via MOR1, Bit 0
18 Stop Mode Selected Disable COP
Any Length Wait Period
via MOR1, Bit 5 via MOR1, Bit 0
19
20
OPERATING MODES MC68HC805P18
6-8
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8
2
SECTION 7
INPUT/OUTPUT PORTS 3
4
7.1 Introduction

In user mode, 20 bidirectional input/output (I/O) lines are arranged as two 8-bit I/O 5
ports (ports A and C), one 3-bit I/O port (port B), and one 1-bit I/O port (port D).
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These ports are programmable as either inputs or outputs under software control 6
of the data direction registers (DDRs). An input-only pin is associated with port D.
7
7.2 Port A

Port A is an 8-bit bidirectional port which can share its pins with the IRQ interrupt
8
system as shown in Figure 7-1. Each port A pin is controlled by the corresponding
bits in a data direction register and a data register. The port A data register is 9
located at address $0000. The port A data direction register (DDRA) is located at
address $0004. Reset clears the DDRA, thereby initializing port A as an input port. 10
The port A data register is unaffected by reset.
11
VDD
MOR 2
(PULLUP INHIBIT) 12
READ $0004

WRITE $0004
13
DATA DIRECTION

WRITE $0000
REGISTER BIT
I/O
14
DATA OUTPUT PIN
REGISTER BIT

READ $0000
A

100 µA
16
PULLUP
INTERNAL HC05
DATA BUS
RESET
17
(RST)
TO IRQ INTERRUPT
SYSTEM 18
Figure 7-1. Port A I/O Circuitry
19
20
INPUT/OUTPUT PORTS
Rev. 1.0
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7.3 Port B
8 Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with the SIOP
communications subsystem. The port B data register is located at address $0001
2 and its data direction register (DDR) is located at address $0005. Reset does not
affect the data registers, but clears the DDRs, thereby setting all of the port pins to
3 input mode. Writing a logic one to a DDR bit sets the corresponding port pin to
output mode (see Figure 7-2).
4 Port B may be used for general I/O applications when the SIOP subsystem is
disabled. The SPE bit in register SPCR is used to enable/disable the SIOP
5 subsystem. When the SIOP subsystem is enabled, port B registers are still
accessible to software. Writing to either of the port B registers while a data transfer
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6 is under way could corrupt the data. See SECTION 11 SERIAL INPUT/OUTPUT
PORT for a discussion of the SIOP subsystem.
7
READ $0005
8 WRITE $0005
DATA DIRECTION
RESET REGISTER BIT
9 WRITE $0001
(RST)
DATA OUTPUT
I/O
PIN
REGISTER BIT

10 READ $0001

11 INTERNAL HC05
DATA BUS

12 Figure 7-2. Port B I/O Circuitry

13
14
A
16
17
18
19
20
INPUT/OUTPUT PORTS MC68HC805P18
7-2
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7.4 Port C

Port C is an 8-bit bidirectional port which can share pins PC3–PC7 with the A/D 8
subsystem. The port C data register is located at address $0002 and its data
direction register (DDR) is located at address $0006. Reset does not affect the 2
data registers, but clears the DDRs, thereby setting all of the port pins to input
mode. Writing a logic one to a DDR bit sets the corresponding port pin to output 3
mode (see Figure 7-3). Two port C pins, PC0 and PC1, can source and sink a
higher current than a typical I/O pin. See SECTION 13 ELECTRICAL
SPECIFICATIONS regarding current specifications.
4
Port C may be used for general I/O applications when the A/D subsystem is 5
disabled. The ADON bit in register ADSC is used to enable/disable the A/D
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subsystem. Care must be exercised when using pins PC0–PC2 while the A/D 6
subsystem is enabled. Accidental changes to bits that affect pins PC3–PC7 in the
data or DDR registers will produce unpredictable results in the A/D subsystem. See
SECTION 9 ANALOG-TO-DIGITAL CONVERTER. 7
8
READ $0006
HIGH CURRENT
WRITE $0006
DATA DIRECTION
CAPABILITY, PC0
AND PC1 ONLY
9
RESET REGISTER BIT
(RST)
WRITE $0002
DATA OUTPUT
I/O
PIN 10
REGISTER BIT

READ $0002 11
INTERNAL HC05
DATA BUS 12
Figure 7-3. Port C I/O Circuitry
13
14
A
16
17
18
19
20
INPUT/OUTPUT PORTS
Rev. 1.0
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7.5 Port D
8 Port D is a 2-bit port with one bidirectional pin (PD5/CKOUT) and one input-only
pin (PD7). Pin PD7 is shared with the 16-bit timer. PD5 can be replaced with a
2 buffered OSC2 clock output via MOR1. The port D data register is located at
address $0003 and its data direction register (DDR) is located at address $0007.
3 Reset does not affect the data registers, but clears the DDRs, thereby setting
PD5/CKOUT to input mode. Writing a one to DDR bit 5 sets PD5/CKOUT to output
4 mode (see Figure 7-4).

Port D may be used for general I/O applications regardless of the state of the 16-bit
5 timer. Since PD7 is an input-only line, its state can be read from the port D data
register at any time.
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6
READ $0007
7 WRITE $0007
DATA DIRECTION
RESET REGISTER BIT
8 WRITE $0003
(RST)
DATA OUTPUT
I/O
PIN
REGISTER BIT
9 READ $0003

10 INTERNAL HC05
DATA BUS

11 Figure 7-4. Port D I/O Circuitry

12
13
14
A
16
17
18
19
20
INPUT/OUTPUT PORTS MC68HC805P18
7-4
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7.6 I/O Port Programming

Each pin on ports A through port D (except pin 7 of port D) may be programmed 8
as an input or an output under software control as shown in Table 7-1, Table 7-2,
Table 7-3, and Table 7-4. The direction of a pin is determined by the state of its 2
corresponding bit in the associated port data direction register (DDR). A pin is
configured as an output if its corresponding DDR bit is set to a logic one. A pin is 3
configured as an input if its corresponding DDR bit is cleared to a logic zero.
4
Table 7-1. Port A I/O Functions
5
Access to DDRA Access to Data
@ $0004 Register @ $0000
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DDRA I/O Pin Mode 6

Read/Write Read Write

0 Input, High Impedance DDRA0–DDRA7 I/O Pin * 7

1 Output DDRA0–DDRA7 PA0–PA7 PA0–PA7

*Does not affect input, but stored to data register

8
9

Table 7-2. Port B I/O Functions 10

Access to DDRA
@ $0005
Access to Data
Register @ $0001 11
DDRB I/O Pin Mode
Read/Write Read Write
12
0 Input, High Impedance DDRB5–DDRB7 I/O Pin *

1 Output DDRB5–DDRB7 PB5–PB7 PB5–PB7 13

*Does not affect input, but stored to data register
14
A
Table 7-3. Port C I/O Functions
16
Access to DDRA Accesses to Data
@ $0006 Register @ $0002
DDRA I/O Pin Mode
Read/Write Read Write
17
0 Input, High Impedance DDRC0–DDRC7 I/O Pin * 18
1 Output DDRC0–DDRC7 PC0–PC7 PC0–PC7

*Does not affect input, but stored to data register 19

20
INPUT/OUTPUT PORTS
Rev. 1.0
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Table 7-4. Port D I/O Functions

8
Access to DDRA Accesses to Data
@ $0007 Register @ $0003
DDRA I/O Pin Mode
2 Read/Write Read Write

3 0 Input, High Impedance DDRD5 I/O Pin *

1 Output DDRD5 PD5/CKOUT PD5/CKOUT

4 *Does not affect input, but stored to data register
**PD7 is input-only
5
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6 NOTE
To avoid generating a glitch on an I/O port pin, data should be written
7 to the I/O port data register before writing a logical one to the
corresponding data direction register.
8
9
10
11
12
13
14
A
16
17
18
19
20
INPUT/OUTPUT PORTS MC68HC805P18
7-6
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8
2
SECTION 8
EEPROM 3
4
8.1 Introduction

This section describes the EEPROM which is located at address $0140 and 5
consists of 128 bytes. Programming the EEPROM can be done by the user on a
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single byte basis by manipulating the programming register located at address 6

$001C.

Also, the mask option register (MOR), which consists of two additional EEPROM 7
bytes, is discussed.
8
8.2 EEPROM Programming Register (EEPROG)
9
The contents and use of the programming register are discussed here.
10
Bit 7 6 5 4 3 2 1 Bit 0

Read: 0 0
11
EEPROG
CPEN ER1 ER0 LATCH EERC EEPGM
$001C Write:
12
Reset: 0 0 0 0 0 0 0 0

= Unimplemented 13
Figure 8-1. EEPROM Programming Register
14
CPEN — Charge Pump Enable
A
When set, CPEN enables the charge pump which produces the internal
EEPROM programming voltage. This bit should be set concurrently with the
LATCH bit. The programming voltage will not be available until EEPGM is set.
16
The charge pump should be disabled when not in use. CPEN is readable and
writable and is cleared by reset. 17
ER1 and ER0 — Erase Select Bits 18
ER1 and ER0 form a 2-bit field which is used to select one of three erase modes:
byte, block, or bulk. Table 8-1 shows the modes selected for each bit 19
configuration. These bits are readable and writable and are cleared by reset.
20
EEPROM
Rev. 1.0
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In byte erase mode, only the selected byte is erased. In block mode, a 32-byte
8 block of EEPROM is erased. The EEPROM memory space is divided into four
32-byte blocks ($140–$15F, $160–$17F, $180–$19F, $1A0–$1BF), and doing
a block erase to any address within a block will erase the entire block. In bulk
2 erase mode, the entire 128-byte EEPROM section is erased.

3 Table 8-1. Erase Mode Select

4 ER1 ER0 Mode

0 0 Program (no Erase)

5 0 1 Byte Erase
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6 1 0 Block Erase

1 1 Bulk Erase
7
LATCH — Latch Bit
8 When set, LATCH configures the EEPROM address and data bus for
programming. Writes to the EEPROM array cause the data bus and the address
9 bus to be latched. This bit is readable and writable, but reads from the array are
inhibited if the LATCH bit is set and a write to the EEPROM space has taken
10 place.
When clear, address and data buses are configured for normal operation. Reset
11 clears this bit.

12 EERC — EEPROM RC Oscillator Control

When this bit is set, the EEPROM section uses the internal RC oscillator instead
13 of the CPU clock. The RC oscillator is shared with the A/D converter, so this bit
should be set by the user when the internal bus frequency is below 1.5 MHz to
14 guarantee reliable operation of the EEPROM or A/D converter. After setting the
EERC bit, delay a time, tRCON, to allow the RC oscillator to stabilize. This bit is
readable and writable. The EERC bit is cleared by reset. The RC oscillator is
A disabled while the MCU is in stop mode.

16 EEPGM — EEPROM Programming Power Enable

EEPGM must be written to enable (or disable) the EEPGM function. When set,
17 EEPGM turns on the charge pump and enables the programming (or erasing)
power to the EEPROM array. When clear, this power is switched off. This will
18 enable pulsing of the programming voltage to be controlled internally. This bit
can be read at any time, but can only be written to if LATCH = 1. If LATCH is not
19 set, then EEPGM cannot be set. LATCH and EEPGM cannot both be set with
one write if LATCH is cleared. EEPGM is cleared automatically when LATCH is
cleared. Reset clears this bit.
20
EEPROM MC68HC805P18
8-2
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8.3 Programming/Erasing Procedures

To program a byte of EEPROM, set LATCH = CPEN = 1, set ER1 = ER0 = 0, write 8
data to the desired address and then set EEPGM for a time, tEPGM.
2
NOTE 3
Any bit should be erased before it is programmed. However, if
write/erase cycling is a concern, the following procedure will
4
minimize the cycling of each bit in each EEPROM byte.
5
If PB • EB = 0, then program the new data over the existing data
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without erasing it first. If PB • EB ≠ 0, then erase the byte before 6

programming where PB = byte data to be programmed and
EB = existing EEPROM byte data. 7
8
To erase a byte of EEPROM, set LATCH = 1, CPEN = 1, ER1 = 0 and ER0 = 1,
write to the address to be erased and set EEPGM for a time, tEBYT. 9
To erase a block of EEPROM, set LATCH = 1, CPEN = 1, ER1 = 1 and ER0 = 0,
write to any address in the block, and set EEPGM for a time, tEBLOCK. 10
For a bulk erase, set LATCH = 1, CPEN = 1, ER1 = 1, and ER0 = 1, write to any 11
address in the array, and set EEPGM for a time, tEBULK.
To terminate the programming or erase sequence, clear EEPGM, delay for a time 12
tFPV to allow the program voltage to fall, and then clear LATCH and CPEN to free
up the buses. Following each erase or programming sequence, clear all 13
programming control bits.
14
NOTE A
Erased/programmed state of the programming EEPROM (128 bytes)
and the user EEPROM (8064 bytes) is opposite. An erased 16
EEPROM memory location is a logic zero for user EEPROM, while it
is a logic one for programming EEPROM. 17
18
19
20
EEPROM
Rev. 1.0
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8.4 Mask Option Registers (MOR)

8 The MOR consists of two EEPROM bytes located at $3F00 and $3F01. The MOR
holds the 16 option bits for:
2
• The SIOP data format, interrupt sensitivity
3 • COP enable/disable
• SIOP clock rate
4 • LVR enable/disable

5 • Stop conversion to halt, pullup/interrupt enable on port A

• Clock output option to replace PD5
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6 When in the erased state, the EEPROM cells will read as logic zeros. These
registers are refreshed every 256 µs during power-on reset and every 16 ms after
7 the part is out of reset (assuming fOSC = 4 MHz).

8 Bit 7 6 5 4 3 2 1 0

9 MOR1 Read: CLKOUT LVRE SWAIT SPR1 SPR0 LSBF LEVIRQ COPEN
$3F00 Write:

10 Reset: Unaffected by reset

= Unimplemented
11 Figure 8-2. Mask Option Register 1
12
Bit 7 6 5 4 3 2 1 0

13 MOR2 Read: PA7PU PA6PU PA5PU PA4PU PA3PU PA2PU PA1PU PA0PU
$3F01 Write:
14 Reset: Unaffected by reset

A = Unimplemented

Figure 8-3. Mask Option Register 2

16
COPEN — COP enable/disable
17 COPEN may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
18 0 = The COP is disabled (erased state).
1 = The COP is enabled.
19
20
EEPROM MC68HC805P18
8-4
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LEVIRQ — Interrupt request option

LEVIRQ may be read at any time. In user mode, writing has no effect. It has to 8
be programmed in bootloader mode.
0 = The IRQ pin is edge-sensitive (erased state). 2
1 = The IRQ pin is edge- and level-sensitive.

LSBF — SIOP MSB or LSB first 3

LSBF may be read at any time. In user mode, writing has no effect. It has to be
programmed in bootloader mode.
4
0 = The SIOP sends/receives MSB (bit 7) first (erased state).
1 = The SIOP sends/receives LSB (bit 0) first. 5
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SPR1 and SPR0 — SIOP Rate Select Bits 6

These bits may be read at any time. In user mode, writing has no effect. It has
to be programmed in bootloader mode. 7
Table 8-2. SIOP Clock Rate Selection 8
SPR1 SPR0 Frequency
9
0 0 fOSC divided by 16

0 1 fOSC divided by 8 10
1 0 fOSC divided by 4

1 1 fOSC divided by 2
11
12
SWAIT — STOP conversion to WAIT
SWAIT may be read at any time. In user mode, writing has no effect. It has to 13
be programmed in bootloader mode.
0 = STOP instruction puts MCU in stop mode. 14
1 = STOP instruction puts MCU in halt mode.

LVRE — LVR enable/disable A

LVRE may be read at any time. In user mode, writing has no effect. It has to be
programmed in bootloader mode.
16
0 = The LVR is disabled (erased state).
1 = The LVR is enabled. 17
CLKOUT — CLKOUT enable/disable 18
CLKOUT may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode. 19
0 = The CLKOUT is disabled (erased state).
1 = The CLKOUT is enabled. 20
EEPROM
Rev. 1.0
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PA7PU through PA0PU — Port A pullups/interrupt enable/disable

8 These bits may be read at any time. In user mode, writing has no effect. It has
to be programmed in bootloader mode.
2 0 = Port A (bits 0 through 7) pullups/interrupt is disabled (erased state).
1 = Port A (bits 0 through 7) pullups/interrupt is enabled.
3
4
5
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6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
EEPROM MC68HC805P18
8-6
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8
2
SECTION 9
ANALOG-TO-DIGITAL CONVERTER 3
4
9.1 Introduction

The MC68HC805P18 includes a 4-channel, multiplexed input, 8-bit successive 5

approximation analog-to-digital (A/D) converter. The A/D subsystem shares its
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inputs with port C pins PC3 through PC7. 6

9.2 Analog Section 7
The following paragraphs describe the operation and performance of analog 8
modules within the analog subsystem.
9
9.2.1 Ratiometric Conversion

The A/D converter is ratiometric, with pin VREFH supplying the high reference 10
voltage. Applying an input voltage equal to VREFH produces a conversion result of
$FF (full scale). Applying an input voltage equal to VSS produces a conversion 11
result of $00. An input voltage greater than VREFH will convert to $FF with no
overflow indication. For ratiometric conversions, VREFH should be at the same 12
potential as the supply voltage being used by the analog signal being measured
and referenced to VSS.
13
9.2.2 VREFH 14
The reference supply for the A/D converter shares pin PC7 with port C. The low
reference is tied to the VSS pin internally. VREFH can be any voltage between VSS A
and VDD; however, the accuracy of conversions is tested and guaranteed only for
VREFH = VDD. 16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
Rev. 1.0
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9.2.3 Accuracy and Precision

8 The 8-bit conversion result is accurate to within ± 1 1/2 LSB, including quantization;
however, the accuracy of conversions is tested and guaranteed only with external
2 oscillator operation.

3 9.2.4 Conversion Process

4 The A/D reference inputs are applied to a precision digital-to-analog converter.

Control logic drives the D/A and the analog output is successively compared to the
selected analog input which was sampled at the beginning of the conversion cycle.
5 The conversion process is monotonic and has no missing codes.
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6
9.3 Digital Section
7 The following paragraphs describe the operation and performance of digital
modules within the analog subsystem.
8
9.3.1 Conversion Times
9
Each input conversion requires 32 PH2 clock cycles, which must be at a frequency
equal to or greater than 1 MHz.
10
11 9.3.2 Internal versus External Oscillator

If the MCU PH2 clock frequency is less than 1 MHz (2 MHz external oscillator), the
12 internal RC oscillator (approximately 1.5 MHz) must be used for the A/D converter
clock. The internal RC clock is selected by setting the EERC bit in the EEPROG
13 register.

14
NOTE
A The RC oscillator is shared with the EEPROM module. The RC
oscillator is disabled while the MCU is in stop mode.
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER MC68HC805P18
9-2
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When the internal RC oscillator is being used, these limitations apply:

1. Since the internal RC oscillator is running asynchronously with respect to the 8
PH2 clock, the conversion complete bit (CC) in the A/D status and control
register must be used to determine when a conversion sequence has been 2
completed.
2. Electrical noise will slightly degrade the accuracy of the A/D converter. The 3
A/D converter is synchronized to read voltages during the quiet period of the
clock driving it. Since the internal and external clocks are not synchronized 4
the A/D converter occasionally will measure an input when the external clock
is making a transition.
5
3. If the PH2 clock is 1 MHz or greater (for instance, external oscillator 2 MHz
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or greater), the internal RC oscillator should be turned off and the external
oscillator used as the conversion clock.
6
7
9.3.3 Multi-Channel Operation

An input multiplexer allows the A/D converter to select from one of four external 8
analog signals. Port C pins PC3 through PC6 are shared with the inputs to the
multiplexer. 9
10
11
12
13
14
A
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
Rev. 1.0
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9.4 A/D Status and Control Register (ADSC)

8 The ADSC register reports the completion of A/D conversion and provides control
over oscillator selection, analog subsystem power, and input channel selection.
2 See Figure 9-1.

3
Bit 7 6 5 4 3 2 1 Bit 0

4 ADSC Read: CC
R ADON
0 0
CH2 CH1 CH0
$001E Write:
5 Reset: 0 0 0 0 0 0 0 0

= Unimplemented R = Reserved
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6
Figure 9-1. A/D Status and Control Register
7
CC — Conversion Complete
8 This read-only status bit is set when a conversion sequence has completed and
data is ready to be read from the ADC register. CC is cleared when a channel is
9 selected for conversion, when data is read from the ADC register, or when the
A/D subsystem is turned off. Once a conversion has been started, conversions
10 of the selected channel will continue every 32 PH2 clock cycles until the ADSC
register is written to again. During continuous conversion operation, the ADC
register will be updated with new data and the CC bit set every 32 PH2 clock
11 cycles. Also, data from the previous conversion will be overwritten regardless of
the state of the CC bit.
12
Reserved
13 This bit is not used currently. It can be read or written, but does not control
anything.
14 ADON — A/D Subsystem On
A When the A/D subsystem is turned on (ADON = 1), it requires a time, tADON, to
stabilize before accurate conversion results can be attained.
16 CH2-CH0 — Channel Select Bits

17 CH2, CH1, and CH0 form a 3-bit field which is used to select an input to the A/D
converter. Channels 0 through 3 correspond to port C input pins PC6 through
PC3. Channels 4 through 6 are used for reference measurements. In user mode
18 channel 7 is reserved. If a conversion is attempted with channel 7 selected the
result will be $00. Table 9-1 lists the inputs selected by bits CH0 through CH3.
19
20
ANALOG-TO-DIGITAL CONVERTER MC68HC805P18
9-4
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If the ADON bit is set and an input from channels 0 through 4 is selected, the
corresponding port C pin’s DDR bit will be cleared (making that port C pin an input). 8
If the port C data register is read while the A/D is on and one of the shared input
channels is selected using bit CH0 through CH2, the corresponding port C pin will
read as a logic zero. The remaining port C pins will read normally. To digitally read 2
a port C pin, the A/D subsystem must be disabled (ADON = 0) or input channel 5
through 7 must be selected. 3
Table 9-1. A/D Multiplexer Input 4
Channel Assignments
Channel Signal
5
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0 AD0 — Port C, Bit 6 6

1 AD1 — Port C, Bit 5

2 AD2 — Port C, Bit 4 7

3 AD3 — Port C, Bit 3
8
4 VREFH — Port C, Bit 7

5 (VREFH + VSS)/2 9
6 VSS

7 Reserved
10
11
12
13
14
A
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
Rev. 1.0
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9.5 A/D Conversion Data Register (ADC)

8 This register contains the output of the A/D converter. See Figure 9-1.

2
Bit 7 6 5 4 3 2 1 Bit 0
3 ADC Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
$001D Write:
4 Reset: X X X X X X X X

5 = Unimplemented

Figure 9-2. A/D Conversion Data Register

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6
9.6 A/D Subsystem During Wait/Halt Modes
7
The A/D subsystem continues normal operation during wait and halt modes. To
decrease power consumption during wait or halt, the ADON bit in the ADSC
8 register and the EERC bit in the EEPROG register should be cleared if the A/D
subsystem is not being used.
9
9.7 A/D Subsystem Operation During Stop Mode
10
When the stop mode is enabled, execution of the STOP instruction will terminate
11 all A/D subsystem functions. Any pending conversion is aborted. When the
oscillator resumes operation upon leaving the stop mode, a finite amount of time
passes before the A/D subsystem stabilizes sufficiently to provide conversions at
12 its rated accuracy. The delays built into the MC68HC805P18 when coming out of
stop mode are sufficient for this purpose. No explicit delays need to be added to
13 the application software.

14
A
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER MC68HC805P18
9-6
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8
2
SECTION 10
16-BIT TIMER 3
4
10.1 Introduction

The MC68HC805P18 MCU contains a single 16-bit programmable timer with an 5

input capture function and an output compare function. The 16-bit timer is driven
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by the output of a fixed divide-by-four prescaler operating from the PH2 clock. The 6
16-bit timer may be used for many applications including input waveform
measurement, while simultaneously generating an output waveform. Pulse widths 7
can vary from microseconds to seconds depending on the oscillator frequency
selected. The 16-bit timer is also capable of generating periodic interrupts. See
Figure 10-1. 8
Because the timer has a 16-bit architecture, each function is represented by two 9
registers. Each register pair contains the high and low byte of that function.
Generally, accessing the low byte of a specific timer function allows full control of
that function; however, an access of the high byte inhibits that specific timer
10
function until the low byte is also accessed.
11

NOTE 12
The I bit in the condition code register (CCR) should be set while 13
manipulating both the high and low byte registers of a specific timer
function. This prevents interrupts from occurring between the time
the high and low bytes are accessed. 14
A
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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INTERNAL HC05 BUS

8
OUTPUT INPUT
2 COMPARE BUFFER
PH2 CAPTURE
CLOCK

3 OCRH OCRL
FREE-
ICRH ICRL
RUNNING
COUNTER
4
TMRH/ TMRL/ ÷4
5 ACRH ACRL
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6
7
COMPARE OVERFLOW EDGE
TCAP
8 DETECTOR DETECTOR DETECTOR

9
10 R R TCMP
>

11 TIMER
R

STATUS OCF TOF ICF RESET

12 REGISTER

13
14 INTERRUPT
TIMER INTERRUPT
GENERATOR
A
TIMER
OCIE TOIE ICIE IEDG OLVL CONTROL
16 REGISTER

17
18
19 Figure 10-1. 16-Bit Timer Block Diagram

20
16-BIT TIMER MC68HC805P18
10-2
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10.2 Timer

The key element of the programmable timer is a 16-bit free-running counter, or 8

timer registers, preceded by a prescaler which divides the PH2 clock by four. The
prescaler gives the timer a resolution of 2.0 microseconds when a 4-MHz crystal is 2
used. The counter is incremented to increasing values during the low portion of the
PH2 clock cycle. 3
The double byte free-running counter can be read from either of two locations: the
timer registers (TMRH and TMRL) or the alternate counter registers (ACRH and 4
ACRL). Both locations will contain identical values. A read sequence containing
only a read of the LSB of the counter (TMRL/ACRL) will return the count value at 5
the time of the read. If a read of the counter accesses the MSB first (TMRH/ACRH),
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it causes the LSB (TMRL/ACRL) to be transferred to a buffer. This buffer value 6

remains fixed after the first MSB byte read, even if the MSB is read several times.
The buffer is accessed when reading the counter LSB (TMRL/ACRL), and thus
completes a read sequence of the total counter value. When reading either the 7
timer or alternate counter registers, if the MSB is read, the LSB must also be read
to complete the read sequence. See Figure 10-2 and Figure 10-3. 8

Bit 7 6 5 4 3 2 1 Bit 0
9
Read: TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0
TMRH
$0018
10
Write:

Reset: 1 1 1 1 1 1 1 1 11

Bit 7 6 5 4 3 2 1 Bit 0
12
Read: TMRL7 TMRL6 TMRL5 TMRL4 TMRL3 TMRL2 TMRL1 TMRL0
TMRL
$0019
13
Write:

Reset: 1 1 1 1 1 1 0 0 14
= Unimplemented

Figure 10-2. Timer Registers (TMRH/TMRL)

A
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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Bit 7 6 5 4 3 2 1 Bit 0
8
ACRH Read: ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0
$001A
2 Write:

Reset: 1 1 1 1 1 1 1 1
3
Bit 7 6 5 4 3 2 1 Bit 0
4 Read: ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0
ACRL
$001B
5 Write:

Reset: 1 1 1 1 1 1 0 0
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6 = Unimplemented

Figure 10-3. Alternate Counter Registers (ACRH/ACRL)

7
The timer registers and alternate counter registers can be read at any time without
8 affecting their value. However, the alternate counter registers differ from the timer
registers in one respect: Aread of the timer register MSB can clear the timer
9 overflow flag (TOF). Therefore, the alternate counter registers can be read at any
time without the possibility of missing timer overflow interrupts due to clearing of
10 the TOF. See Figure 10-4.

11
PH2
CLOCK
12
16-BIT
FREE-RUNNING $FFFE $FFFF $0000 $0001 $0002
13 COUNTER

TIMER
OVERFLOW
14 FLAG (TOF)

NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status
A register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register pair (TCRL).

16 Figure 10-4. State Timing Diagram for Timer Overflow

17
18
19
20
16-BIT TIMER MC68HC805P18
10-4
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The free-running counter is initialized to $FFFC during reset and is a read-only

register. During power-on-reset (POR), the counter is initialized to $FFFC and 8
begins counting after the oscillator startup delay. Because the counter is 16 bits
preceded by a fixed divide-by-four prescaler, the value in the counter repeats every
262,144 PH2 clock cycles (524,288 oscillator cycles). When the free-running 2
counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) in register
TSR is set. An interrupt can also be enabled when counter rollover occurs by 3
setting the timer overflow interrupt enable bit (TOIE) in register TCR. See
Figure 10-5. 4
5
PH2
CLOCK
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6
INTERNAL
RESET
7
16-BIT
$FFFC $FFFD $FFFE $FFFF
FREE-RUNNING
COUNTER 8
RESET
(EXTERNAL
OR OTHER)
9
NOTE: The counter and control registers are the only 16-bit timer registers affected by reset. 10
Figure 10-5. State Timing Diagram for Timer Reset
11
12
13
14
A
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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10.3 Output Compare

8 The output compare function may be used to generate an output waveform and/or
as an elapsed time indicator. All of the bits in the output compare register pair
2 OCRH/OCRL are readable and writable and are not altered by the 16-bit timer’s
control logic. Reset does not affect the contents of these registers. If the output
3 compare function is not utilized, its registers can be used for data storage. See
Figure 10-3.
4
Bit 7 6 5 4 3 2 1 Bit 0
5 OCRH Read:
OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
$0016
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Write:
6
Reset: X X X X X X X X

7
Bit 7 6 5 4 3 2 1 Bit 0
8 OCRL Read:
OCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0
$0017 Write:
9
Reset: X X X X X X X X

10 Figure 10-6. Output Compare Registers (OCRH/OCRL)

11 The contents of the output compare registers are compared with the contents of
the free-running counter once every four PH2 clock cycles. If a match is found, the
12 output compare flag bit (OCF) is set and the output level bit (OLVL) is clocked to
the output latch. The values in the output compare registers and output level bit
should be changed after each successful comparison to control an output
13 waveform or to establish a new elapsed timeout. An interrupt can also accompany
a successful output compare if the output compare interrupt enable bit (OCIE) is
14 set.

A After a CPU write cycle to the MSB of the output compare register pair (OCRH),
the output compare function is inhibited until the LSB (OCRL) is written. Both bytes
must be written if the MSB is written. A write made only to the LSB will not inhibit
16 the compare function. The free-running counter increments every four PH2 clock
cycles. The minimum time required to update the output compare registers is a
17 function of software rather than hardware.

The output compare output level bit (OLVL) will be clocked to its output latch
18 regardless of the state of the output compare flag bit (OCF). A valid output compare
must occur before the OLVL bit is clocked to its output latch (TCMP).
19
20
16-BIT TIMER MC68HC805P18
10-6
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Since neither the output compare flag (OCF) nor the output compare registers are
affected by reset, care must be exercised when initializing the output compare 8
function. The following procedure is recommended:
1. Block interrupts by setting the I bit in the condition code register (CCR). 2
2. Write the MSB of the output compare register pair (OCRH) to inhibit further
compares until the LSB is written. 3
3. Read the timer status register (TSR) to arm the output compare flag (OCF).
4. Write the LSB of the output compare register pair (OCRL) to enable the
4
output compare function and to clear its flag (and interrupt).
5
5. Unblock interrupts by clearing the I bit in the CCR.
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This procedure prevents the output compare flag bit (OCF) from being set between 6
the time it is read and the time the output compare registers are updated. A
software example is shown in Figure 10-7. 7

SEI
8
9B BLOCK INTERRUPTS
. . . . .
. . . . .
9
B6 XX LDA DATAH HI BYTE FOR COMPARE
BE XX LDX DATAL LO BYTE FOR COMPARE 10
B7 16 STA OCRH INHIBIT OUTPUT COMPARE
B6 13 LDA TSR ARM OCF BIT TO CLEAR 11
BF 17 STX OCRL READY FOR NEXT COMPARE
. . . . .
12
Figure 10-7. Output Compare Software Initialization Example 13
14
A
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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10.4 Input Capture

8 Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input capture.
They are used to latch the value of the free-running counter after a defined
2 transition is sensed by the input capture edge detector.

3
NOTE
4 The input capture edge detector contains a Schmitt trigger to improve
noise immunity.
5
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6
The edge that triggers the counter transfer is defined by the input edge bit (IEDG)
7 in register TCR. Reset does not affect the contents of the input capture registers.
See Figure 10-3.
8
Bit 7 6 5 4 3 2 1 Bit 0

9 ICRH Read:
ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0
$0014 Write:
10 Reset: X X X X X X X X

11
Bit 7 6 5 4 3 2 1 Bit 0

12 ICRL Read:
ICRL7 ICRL6 ICRL5 ICRL4 ICRL3 ICRL2 ICRL1 ICRL0
$0015 Write:
13 Reset: X X X X X X X X

14 Figure 10-8. Input Compare Registers (ICRH/ICRL)

A The result obtained by an input capture will be one more than the value of the
free-running counter on the rising edge of the PH2 clock preceding the external
transition (see Figure 10-9). This delay is required for internal synchronization.
16 Resolution is affected by the prescaler, allowing the free-running counter to
increment once every four PH2 clock cycles.
17
The contents of the free-running counter are transferred to the input capture
18 registers on each proper signal transition regardless of the state of the input
capture flag bit (ICF) in register TSR. The input capture registers always contain
the free-running counter value which corresponds to the most recent input capture.
19
20
16-BIT TIMER MC68HC805P18
10-8
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After a read of the MSB of the input capture register pair (ICRH), counter transfers
are inhibited until the LSB of the register pair (ICRL) is also read. This characteristic 8
forces the minimum pulse period attainable to be determined by the time required
to execute an input capture software routine in an application.
2
Reading the LSB of the input capture register pair (ICRL) does not inhibit transfer
of the free-running counter. Again, minimum pulse periods are ones which allow 3
software to read the LSB of the register pair (ICRL) and perform needed
operations. There is no conflict between reading the LSB (ICRL) and the
free-running counter transfer, since they occur on opposite edges of the PH2 clock.
4
5
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PH2 6
CLOCK

7
16-BIT
FREE-RUNNING $FFEB $FFEC $FFED $FFEE $FFEF
COUNTER 8
TCAP
PIN 9
INPUT (SEE NOTE) 10
CAPTURE
LATCH

INPUT 11
CAPTURE $???? $FFED
REGISTER
INPUT
12
CAPTURE
FLAG
13
NOTE: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture
flag is set during the next T11 timer state.
14
Figure 10-9. State Timing Diagram for Input Capture A
16
17
18
19
20
16-BIT TIMER
Rev. 1.0
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10.5 Timer Control Register (TCR)

8 The timer control (TCR) shown in Figure 10-3 and free-running counter (TMRH,
TMRL, ACRH, and ACRL) registers are the only registers of the 16-bit timer
2 affected by reset. The output compare port (TCMP) is forced low after reset and
remains low until OLVL is set and a valid output compare occurs.
3
Bit 7 6 5 4 3 2 1 Bit 0
4 Read: 0 0 0
TCR
ICIE OCIE TOIE IEDG OLVL
$0012
5 Write:

Reset: 0 0 0 0 0 0 X 0
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6 = Unimplemented

Figure 10-10. Timer Control Register (TCR)

7
ICIE — Input Capture Interrupt Enable
8
Bit 7, when set, enables input capture interrupts to the CPU. The interrupt will
9 occur at the same time bit 7 (ICF) in the TSR register is set.

OCIE —Output Compare Interrupt Enable

10
Bit 6, when set, enables output compare interrupts to the CPU. The interrupt will
occur at the same time bit 6 (OCF) in the TSR register is set.
11
TOIE — Timer Overflow Interrupt Enable
12 Bit 5, when set, enables timer overflow (rollover) interrupts to the CPU. The
interrupt will occur at the same time bit 5 (TOF) in the TSR register is set.
13
IEDG — Input Capture Edge Select
14 Bit 1 selects which edge of the input capture signal will trigger a transfer of the
contents of the free-running counter registers to the input capture registers.
A Clearing this bit will select the falling edge; setting it selects the rising edge.

OLVL — Output Compare Output Level Select

16
Bit 0 selects the output level (high or low) that is clocked into the output compare
output latch at the next successful output compare.
17
18
19
20
16-BIT TIMER MC68HC805P18
10-10
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10.6 Timer Status Register (TSR)

Reading the timer status register (TSR) satisfies the first condition required to clear 8
status flags and interrupts. See Figure 10-3. The only remaining step is to read (or
write) the register associated with the active status flag (and/or interrupt). This 2
method does not present any problems for input capture or output compare
functions. 3
However, a problem can occur when using a timer interrupt function and reading
the free-running counter at random times to, for example, measure an elapsed 4
time. If the proper precautions are not designed into the application software, a
timer interrupt flag (TOF) could unintentionally be cleared if: 5
1. The TSR is read when bit 5 (TOF) is set, and
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2. The LSB of the free-running counter is read, but not for the purpose of
6
servicing the flag or interrupt.
7
The alternate counter registers (ACRH and ACRL) contain the same values as the
timer registers (TMRH and TMRL). Registers ACRH and ACRL can be read at any 8
time without affecting the timer overflow flag (TOF) or interrupt.
9
Bit 7 6 5 4 3 2 1 Bit 0

TSR Read: ICF OCR TOF 0 0 0 0 0 10

$0013 Write:

Reset: X X X 0 0 0 0 0
11
= Unimplemented
12
Figure 10-11. Timer Status Register (TSR)
13
ICF — Input Capture Flag
Bit 7 is set when the edge specified by IEDG in register TCR has been sensed
14
by the input capture edge detector fed by pin TCAP. This flag and the input
capture interrupt can be cleared by reading register TSR followed by reading the A
LSB of the input capture register pair (ICRL).
16
OCF — Output Compare Flag
Bit 6 is set when the contents of the output compare registers match the 17
contents of the free-running counter. This flag and the output compare interrupt
can be cleared by reading register TSR followed by writing the LSB of the output 18
compare register pair (OCRL).
19
20
16-BIT TIMER
Rev. 1.0
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TOF — Timer Overflow Flag

8 Bit 5 is set by a rollover of the free-running counter from $FFFF to $0000. This
flag and the timer overflow interrupt can be cleared by reading register TSR
2 followed by reading the LSB of the timer register pair (TMRL).

3 10.7 Timer Operation During Wait/Halt Modes

During wait and halt modes, the 16-bit timer continues to operate normally and may
4 generate an interrupt to trigger the MCU out of the wait/halt mode.

5
10.8 Timer Operation During Stop Mode
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6 When the MCU enters the stop mode, the free-running counter stops counting (the
PH2 clock is stopped). It remains at that particular count value until the stop mode
7 is exited by applying a low signal to the IRQ pin, at which time the counter resumes
from its stopped value as if nothing had happened. If stop mode is exited via an
8 external RESET (logic low applied to the RESET pin), the counter is forced to
$FFFC.
9 If a valid input capture edge occurs at the TCAP pin during stop mode the input
capture detect circuitry will be armed. This action does not set any flags or “wake
10 up” the MCU, but when the MCU does “wake up” there will be an active input
capture flag (and data) from the first valid edge. If the stop mode is exited by an
external RESET, no input capture flag or data will be present even if a valid input
11 capture edge was detected during stop mode.

12
13
14
A
16
17
18
19
20
16-BIT TIMER MC68HC805P18
10-12
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8
2
SECTION 11
SERIAL INPUT/OUTPUT PORT 3
4
11.1 Introduction

The simple synchronous serial input/output port (SIOP) subsystem is designed to 5

provide efficient serial communications between peripheral devices or other
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MCUs. The SIOP is implemented as a 3-wire master/slave system with serial clock 6
(SCK), serial data Input (SDI), and serial data output (SDO). A block diagram of the
SIOP is shown in Figure 11-1. 7
The SIOP subsystem shares its input/output pins with port B. When the SIOP is
enabled (SPE bit set in register SCR), port B data direction registers (DDR) and 8
data registers are modified by the SIOP. Although port B DDR and data registers
can be altered by application software, these actions could affect the transmitted 9
or received data.
10
HCO5 INTERNAL BUS
11

SPE
12
13
7 6 5 4 3 2 1 0
BAUD
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
14
8-BIT SDO SDO/PB5
STATUS I/O
CONTROL
RATE SHIFT
REGISTER
GENERATOR
REGISTER
REGISTER SDI
CONTROL
LOGIC SDI/PB6
A
$0A $0B $0C
16
SCK SCK/PB7

PH2 CLOCK 17
Figure 11-1. SIOP Block Diagram 18
19
20
SERIAL INPUT/OUTPUT PORT
Rev. 1.0
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11.2 SIOP Signal Format

8 The SIOP subsystem is software configurable for master or slave operation. No
external mode selection inputs are available (such as the slave select pin).
2
11.2.1 Serial Clock (SCK)
3
The state of the SCK output normally remains a logic one during idle periods
4 between data transfers. The first falling edge of SCK signals the beginning of a
data transfer. At this time the first bit of received data is accepted at the SDI pin
and the first bit of transmitted data is presented at the SDO pin (see Figure 11-2).
5 Data is captured at the SDI pin on the rising edge of SCK, and the first bit of
transmitted data is presented at the SDO pin. The transfer is terminated upon the
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6 eighth rising edge of SCK.

7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

SDO
8
9 SCK

100 ns 100 ns
10
SDI
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
11
Figure 11-2. SIOP Timing Diagram
12
The master and slave modes of operation differ only by the sourcing of SCK. In
13 master mode, SCK is driven from an internal source within the MCU. In slave
mode, SCK is driven from a source external to the MCU. The SCK frequency is
14 programmable via the mask option register 1 (MOR1). Available rates are OSC
divided by 2, 4, 8, or 16.
A
16 NOTE
OSC divided by 2 is four times faster than the standard rate available
17 on the 68HC05P6.

18
Refer to 8.4 Mask Option Registers (MOR) for a description of available mask
19 option registers.

20
SERIAL INPUT/OUTPUT PORT MC68HC805P18
11-2
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11.2.2 Serial Data Input (SDI)

The SDI pin becomes an input as soon as the SIOP subsystem is enabled. New 8
data is presented to the SDI pin on the falling edge of SCK. Valid data must be
present at least 100 nanoseconds before the rising edge of SCK and remain valid 2
for 100 nanoseconds after the rising edge of SCK. See Figure 11-2.
3
11.2.3 Serial Data Output (SDO)
4
The SDO pin becomes an output as soon as the SIOP subsystem is enabled. Prior
to enabling the SIOP, PB5 can be initialized to determine the beginning state.
While the SIOP is enabled, PB5 cannot be used as a standard output since that pin
5
is connected to the last stage of the SIOP serial shift register. The data can be
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transmitted in either MSB first format or the LSB format by programming the 6
MOR1.

On the first falling edge of SCK, the first data bit will be shifted out to the SDO pin.
7
The remaining data bits will be shifted out to the SDI pin on subsequent falling
edges of SCK. The SDO pin will present valid data at least 100 nanoseconds 8
before the rising edge of the SCK and remain valid for 100 nanoseconds after the
rising edge of SCK. See Figure 11-2. 9
11.3 SIOP Registers 10
The SIOP is programmed and controlled by the SIOP control register (SCR) 11
located at address $000A, the SIOP status register (SSR) located at address
$000B, and the SIOP data register (SDR) located at address $000C.
12
13
14
A
16
17
18
19
20
SERIAL INPUT/OUTPUT PORT
Rev. 1.0
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11.3.1 SIOP Control Register (SCR)

8 This register is located at address $000A and contains two bits. Figure 11-3 shows
the position of each bit in the register and indicates the value of each bit after reset.
2
3 Bit 7 6 5 4 3 2 1 Bit 0

SCR Read: 0 0 0 0 0 0
SPE MSTR
4 $000A Write:

Reset: 0 0 0 0 0 0 0 0
5 = Unimplemented
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6 Figure 11-3. SIOP Control Register

7 SPE — Serial Peripheral Enable

When set, the SPE bit enables the SIOP subsystem such that SDO/PB5 is the
8 serial data output, SDI/PB6 is the serial data input, and SCK/PB7 is a serial
clock input in the slave mode or a serial clock output in the master mode. Port
9 B DDR and data registers can be manipulated as usual (except for PB5);
however, these actions could affect the transmitted or received data.
10 The SPE bit is readable and writable at any time. Clearing the SPE bit while a
transmission is in progress will 1) abort the transmission, 2) reset the serial bit
11 counter, and 3) convert the port B/SIOP port to a general-purpose I/O port.
Reset clears the SPE bit.
12 MSTR — Master Mode Select
When set, the MSTR bit configures the serial I/O port for master mode. A
13 transfer is initiated by writing to the SDR. Also, the SCK pin becomes an output
providing a synchronous data clock dependent upon the oscillator frequency.
14 When the device is in slave mode, the SDO and SDI pins do not change
function. These pins behave exactly the same in both the master and slave
A modes.
The MSTR bit is readable and writable at any time regardless of the state of the
16 SPE bit. Clearing the MSTR bit will abort any transfers that may have been in
progress. Reset clears the MSTR bit, placing the SIOP subsystem in slave
17 mode.

18
19
20
SERIAL INPUT/OUTPUT PORT MC68HC805P18
11-4
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11.3.2 SIOP Status Register (SSR)

This register is located at address $000B and contains two bits. Figure 11-3 shows 8
the position of each bit in the register and indicates the value of each bit after reset.
2
Bit 7 6 5 4 3 2 1 Bit 0
3
SSR Read: SPIF DCOL 0 0 0 0 0 0
$000B Write: 4
Reset: 0 0 0 0 0 0 0 0

= Unimplemented
5
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Figure 11-4. SIOP Status Register 6

SPIF — Serial Port Interface Flag 7
SPIF is a read-only status bit that is set on the last rising edge of SCK and
indicates that a data transfer has been completed. It has no effect on any future 8
data transfers and can be ignored. The SPIF bit is cleared by reading the SSR
followed by a read or write of the SDR. If the SPIF is cleared before the last rising 9
edge of SCK, it will be set again on the last rising edge of SCK. Reset clears the
SPIF bit.
10
DCOL — Data Collision
DCOL is a read-only status bit which indicates that an illegal access of the SDR
11
has occurred. The DCOL bit will be set when reading or writing the SDR after
the first falling edge of SCK and before SPIF is set. Reading or writing the SDR 12
during this time will result in invalid data being transmitted or received.
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed 13
by a read or write of the SDR. If the last part of the clearing sequence is done
after another transfer has started, the DCOL bit will be set again. Reset clears 14
the DCOL bit.
A
16
17
18
19
20
SERIAL INPUT/OUTPUT PORT
Rev. 1.0
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11.3.3 SIOP Data Register (SDR)

8 This register is located at address $000C and serves as both the transmit and
receive data register. Writing to this register will initiate a message transmission if
2 the SIOP is in master mode. The SIOP subsystem is not double buffered and any
write to this register will destroy the previous contents. The SDR can be read at any
3 time; however, if a transfer is in progress, the results may be ambiguous and the
DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause
4 invalid data to be transmitted and/or received. Figure 11-3 shows the position of
each bit in the register. This register is not affected by reset.
5
Bit 7 6 5 4 3 2 1 Bit 0
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6 SDR Read:
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
$000C Write:
7
Reset: Unaffected by reset

8 Figure 11-5. SIOP Data Register

9
10
11
12
13
14
A
16
17
18
19
20
SERIAL INPUT/OUTPUT PORT MC68HC805P18
11-6
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SECTION 12
INSTRUCTION SET

12.1 Introduction

This section describes the addressing modes and instruction types.

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12.2 Addressing Modes

The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative

12.2.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent
instructions require no memory address and are one byte long.

12.2.2 Immediate

Immediate instructions are those that contain a value to be used in an operation

with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.

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12.2.3 Direct

Direct instructions can access any of the first 256 memory addresses with two
bytes. The first byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are 3-byte instructions that use direct
addressing to access the operand and relative addressing to specify a branch
destination.

12.2.4 Extended

Extended instructions use only three bytes to access any address in memory. The
first byte is the opcode; the second and third bytes are the high and low bytes of
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the operand address.

When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.

12.2.5 Indexed, No Offset

Indexed instructions with no offset are 1-byte instructions that can access data with
variable addresses within the first 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.

Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.

12.2.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are 2-byte instructions that can access data with
variable addresses within the first 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.

Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the first 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.

INSTRUCTION SET MC68HC805P18

12-2
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12.2.7 Indexed, 16-Bit Offset

Indexed, 16-bit offset instructions are 3-byte instructions that can access data with
variable addresses at any location in memory. The CPU adds the unsigned byte in
the index register to the two unsigned bytes following the opcode. The sum is the
conditional address of the operand. The first byte after the opcode is the high byte
of the 16-bit offset; the second byte is the low byte of the offset. These instructions
can address any location in memory.

Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.

As with direct and extended addressing, the Motorola assembler determines the
shortest form of indexed addressing.
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12.2.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte
following the opcode to the contents of the program counter. If the branch condition
is not true, the CPU goes to the next instruction. The offset is a signed, two’s
complement byte that gives a branching range of –128 to +127 bytes from the
address of the next location after the branch instruction.

When using the Motorola assembler, the programmer does not need to calculate
the offset because the assembler determines the proper offset and verifies that it
is within the span of the branch.

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12.3 Instruction Types

The MCU instructions fall into five categories:

• Register/Memory instructions
• Read-Modify-Write instructions
• Jump/Branch instructions
• Bit Manipulation instructions
• Control instructions

12.3.1 Register/Memory Instructions

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Most of these instructions use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in memory.
Table 12-1 lists the register/memory instructions.

Table 12-1. Register/Memory Instructions

Instruction Mnemonic
Add Memory Byte and Carry Bit to Accumulator ADC

Add Memory Byte to Accumulator ADD

AND Memory Byte with Accumulator AND

Bit Test Accumulator BIT

Compare Accumulator CMP

Compare Index Register with Memory Byte CPX

EXCLUSIVE OR Accumulator with Memory Byte EOR

Load Accumulator with Memory Byte LDA

Load Index Register with Memory Byte LDX

Multiply MUL

OR Accumulator with Memory Byte ORA

Subtract Memory Byte and Carry Bit from Accumulator SBC

Store Accumulator in Memory STA

Store Index Register in Memory STX

Subtract Memory Byte from Accumulator SUB

INSTRUCTION SET MC68HC805P18

12-4
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12.3.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 12-2 lists the
read-modify-write instructions.

Table 12-2. Read-Modify-Write Instructions

Instruction Mnemonic
Arithmetic Shift Left ASL
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Arithmetic Shift Right ASR

Clear Bit in Memory BCLR

Set Bit in Memory BSET

Clear CLR

Complement (One’s Complement) COM

Decrement DEC

Increment INC

Logical Shift Left LSL

Logical Shift Right LSR

Negate (Two’s Complement) NEG

Rotate Left through Carry Bit ROL

Rotate Right through Carry Bit ROR

Test for Negative or Zero TST

12.3.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is met.
If the test condition is not met, the branch is not performed. All branch instructions
use relative addressing.

Bit test and branch instructions cause a branch based on the state of any readable
bit in the first 256 memory locations. These 3-byte instructions use a combination
of direct addressing and relative addressing. The direct address of the byte to be
tested is in the byte following the opcode. The third byte is the signed offset byte.
The CPU finds the conditional branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its condition
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(set or clear) is part of the opcode. The span of branching is from –128 to +127 from
the address of the next location after the branch instruction. The CPU also
transfers the tested bit to the carry/borrow bit of the condition code register.
Table 12-3 lists the jump and branch instructions.

Table 12-3. Jump and Branch Instructions

Instruction Mnemonic
Branch if Carry Bit Clear BCC

Branch if Carry Bit Set BCS

Branch if Equal BEQ

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Branch if Half-Carry Bit Clear BHCC

Branch if Half-Carry Bit Set BHCS

Branch if Higher BHI

Branch if Higher or Same BHS

Branch if IRQ Pin High BIH

Branch if IRQ Pin Low BIL

Branch if Lower BLO

Branch if Lower or Same BLS

Branch if Interrupt Mask Clear BMC

Branch if Minus BMI

Branch if Interrupt Mask Set BMS

Branch if Not Equal BNE

Branch if Plus BPL

Branch Always BRA

Branch if Bit Clear BRCLR

Branch Never BRN

Branch if Bit Set BRSET

Branch to Subroutine BSR

Unconditional Jump JMP

Jump to Subroutine JSR

INSTRUCTION SET MC68HC805P18

12-6
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12.3.4 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the first 256 bytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the first 256 bytes of memory. The CPU can also test and branch based on
the state of any bit in any of the first 256 memory locations. Bit manipulation
instructions use direct addressing. Table 12-4 lists these instructions.

Table 12-4. Bit Manipulation Instructions

Instruction Mnemonic
Clear Bit BCLR
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Branch if Bit Clear BRCLR

Branch if Bit Set BRSET

Set Bit BSET

12.3.5 Control Instructions

These register reference instructions control CPU operation during program

execution. Control instructions, listed in Table 12-5, use inherent addressing.

Table 12-5. Control Instructions

Instruction Mnemonic
Clear Carry Bit CLC

Clear Interrupt Mask CLI

No Operation NOP

Reset Stack Pointer RSP

Return from Interrupt RTI

Return from Subroutine RTS

Set Carry Bit SEC

Set Interrupt Mask SEI

Stop Oscillator and Enable IRQ Pin STOP

Software Interrupt SWI

Transfer Accumulator to Index Register TAX

Transfer Index Register to Accumulator TXA

Stop CPU Clock and Enable Interrupts WAIT

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12.4 Instruction Set Summary

Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect
of each instruction on the condition code register.

Table 12-6. Instruction Set Summary

Operand
Address
Effect on

Opcode

Cycles
Mode
Source Operation Description CCR
Form
H I N Z C
ADC #opr IMM A9 ii 2
ADC opr DIR B9 dd 3
ADC opr EXT C9 hh ll 4
A ← (A) + (M) + (C)
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Add with Carry ↕ — ↕ ↕ ↕

ADC opr,X IX2 D9 ee ff 5
ADC opr,X IX1 E9 ff 4
ADC ,X IX F9 3
ADD #opr IMM AB ii 2
ADD opr DIR BB dd 3
ADD opr EXT CB hh ll 4
Add without Carry A ← (A) + (M) ↕ — ↕ ↕ ↕
ADD opr,X IX2 DB ee ff 5
ADD opr,X IX1 EB ff 4
ADD ,X IX FB 3
AND #opr IMM A4 ii 2
AND opr DIR B4 dd 3
AND opr EXT C4 hh ll 4
Logical AND A ← (A) ∧ (M) — — ↕ ↕ —
AND opr,X IX2 D4 ee ff 5
AND opr,X IX1 E4 ff 4
AND ,X IX F4 3
ASL opr DIR 38 dd 5
ASLA INH 48 3
Arithmetic Shift Left
ASLX C 0 — — ↕ ↕ ↕ INH 58 3
(Same as LSL)
ASL opr,X b7 b0 IX1 68 ff 6
ASL ,X IX 78 5
ASR opr DIR 37 dd 5
ASRA INH 47 3
ASRX Arithmetic Shift Right C — — ↕ ↕ ↕ INH 57 3
b7 b0
ASR opr,X IX1 67 ff 6
ASR ,X IX 77 5
Branch if Carry Bit
BCC rel PC ← (PC) + 2 + rel ? C = 0 — — — — — REL 24 rr 3
Clear
DIR (b0) 11 dd 5
DIR (b1) 13 dd 5
DIR (b2) 15 dd 5
DIR (b3) 17 dd 5
BCLR n opr Clear Bit n Mn ← 0 — — — — —
DIR (b4) 19 dd 5
DIR (b5) 1B dd 5
DIR (b6) 1D dd 5
DIR (b7) 1F dd 5
Branch if Carry Bit
BCS rel PC ← (PC) + 2 + rel ? C = 1 — — — — — REL 25 rr 3
Set (Same as BLO)
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? Z = 1 — — — — — REL 27 rr 3

INSTRUCTION SET MC68HC805P18

12-8
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Table 12-6. Instruction Set Summary (Continued)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source CCR
Operation Description
Form
H I N Z C
Branch if Half-Carry
BHCC rel PC ← (PC) + 2 + rel ? H = 0 — — — — — REL 28 rr 3
Bit Clear
Branch if Half-Carry
BHCS rel PC ← (PC) + 2 + rel ? H = 1 — — — — — REL 29 rr 3
Bit Set
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — — REL 22 rr 3
Branch if Higher or
BHS rel PC ← (PC) + 2 + rel ? C = 0 — — — — — REL 24 rr 3
Same
Branch if IRQ Pin
BIH rel PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL 2F rr 3
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High
Branch if IRQ Pin
BIL rel PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL 2E rr 3
Low
BIT #opr IMM A5 ii 2
BIT opr DIR B5 dd 3
Bit Test
BIT opr EXT C5 hh ll 4
Accumulator with (A) ∧ (M) — — ↕ ↕ —
BIT opr,X IX2 D5 ee ff 5
Memory Byte
BIT opr,X IX1 E5 ff 4
BIT ,X IX F5 p 3
Branch if Lower
BLO rel PC ← (PC) + 2 + rel ? C = 1 — — — — — REL 25 rr 3
(Same as BCS)
Branch if Lower or
BLS rel PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — — REL 23 rr 3
Same
Branch if Interrupt
BMC rel PC ← (PC) + 2 + rel ? I = 0 — — — — — REL 2C rr 3
Mask Clear
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? N = 1 — — — — — REL 2B rr 3
Branch if Interrupt
BMS rel PC ← (PC) + 2 + rel ? I = 1 — — — — — REL 2D rr 3
Mask Set
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? Z = 0 — — — — — REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? N = 0 — — — — — REL 2A rr 3
BRA rel Branch Always PC ← (PC) + 2 + rel ? 1 = 1 — — — — — REL 20 rr 3
DIR (b0) 01 dd rr 5
DIR (b1) 03 dd rr 5
DIR (b2) 05 dd rr 5
DIR (b3) 07 dd rr 5
BRCLR n opr rel Branch if bit n clear PC ← (PC) + 2 + rel ? Mn = 0 — — — — ↕
DIR (b4) 09 dd rr 5
DIR (b5) 0B dd rr 5
DIR (b6) 0D dd rr 5
DIR (b7) 0F dd rr 5
DIR (b0) 00 dd rr 5
DIR (b1) 02 dd rr 5
DIR (b2) 04 dd rr 5
DIR (b3) 06 dd rr 5
BRSET n opr rel Branch if Bit n Set PC ← (PC) + 2 + rel ? Mn = 1 — — — — ↕
DIR (b4) 08 dd rr 5
DIR (b5) 0A dd rr 5
DIR (b6) 0C dd rr 5
DIR (b7) 0E dd rr 5
BRN rel Branch Never PC ← (PC) + 2 + rel ? 1 = 0 — — — — — REL 21 rr 3

INSTRUCTION SET
Rev. 1.0
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Table 12-6. Instruction Set Summary (Continued)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source CCR
Operation Description
Form
H I N Z C
DIR (b0) 10 dd 5
DIR (b1) 12 dd 5
DIR (b2) 14 dd 5
DIR (b3) 16 dd 5
BSET n opr Set Bit n Mn ← 1 — — — — —
DIR (b4) 18 dd 5
DIR (b5) 1A dd 5
DIR (b6) 1C dd 5
DIR (b7) 1E dd 5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
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Branch to
BSR rel — — — — — REL AD rr 6
Subroutine SP ← (SP) – 1
PC ← (PC) + rel
CLC Clear Carry Bit C←0 — — — — 0 INH 98 2
CLI Clear Interrupt Mask I←0 — 0 — — — INH 9A 2
CLR opr M ← $00 DIR 3F dd 5
CLRA A ← $00 INH 4F 3
CLRX Clear Byte X ← $00 — — 0 1 — INH 5F 3
CLR opr,X M ← $00 IX1 6F ff 6
CLR ,X M ← $00 IX 7F 5
CMP #opr IMM A1 ii 2
CMP opr DIR B1 dd 3
Compare
CMP opr EXT C1 hh ll 4
Accumulator with (A) – (M) — — ↕ ↕ ↕
CMP opr,X IX2 D1 ee ff 5
Memory Byte
CMP opr,X IX1 E1 ff 4
CMP ,X IX F1 3
COM opr M ← (M) = $FF – (M) DIR 33 dd 5
COMA A ← (A) = $FF – (M) INH 43 3
Complement Byte
COMX X ← (X) = $FF – (M) — — ↕ ↕ 1 INH 53 3
(One’s Complement)
COM opr,X M ← (M) = $FF – (M) IX1 63 ff 6
COM ,X M ← (M) = $FF – (M) IX 73 5
CPX #opr IMM A3 ii 2
CPX opr DIR B3 dd 3
Compare Index
CPX opr EXT C3 hh ll 4
Register with (X) – (M) — — ↕ ↕ 1
CPX opr,X IX2 D3 ee ff 5
Memory Byte
CPX opr,X IX1 E3 ff 4
CPX ,X IX F3 3
DEC opr M ← (M) – 1 DIR 3A dd 5
DECA A ← (A) – 1 INH 4A 3
DECX Decrement Byte X ← (X) – 1 — — ↕ ↕ — INH 5A 3
DEC opr,X M ← (M) – 1 IX1 6A ff 6
DEC ,X M ← (M) – 1 IX 7A 5
EOR #opr IMM A8 ii 2
EOR opr DIR B8 dd 3
EXCLUSIVE OR
EOR opr EXT C8 hh ll 4
Accumulator with A ← (A) ⊕ (M) — — ↕ ↕ —
EOR opr,X IX2 D8 ee ff 5
Memory Byte
EOR opr,X IX1 E8 ff 4
EOR ,X IX F8 3

INSTRUCTION SET MC68HC805P18

12-10
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Table 12-6. Instruction Set Summary (Continued)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source CCR
Operation Description
Form
H I N Z C
INC opr M ← (M) + 1 DIR 3C dd 5
INCA A ← (A) + 1 INH 4C 3
INCX Increment Byte X ← (X) + 1 — — ↕ ↕ — INH 5C 3
INC opr,X M ← (M) + 1 IX1 6C ff 6
INC ,X M ← (M) + 1 IX 7C 5
BC
JMP opr DIR C dd 2
JMP opr EXT C hh ll 3
JMP opr,X Unconditional Jump PC ← Jump Address — — — — — IX2 D ee ff 4
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JMP opr,X IX1 C ff 3

JMP ,X IX EC 2
FC
BD
JSR opr DIR C dd 5
PC ← (PC) + n (n = 1, 2, or 3)
JSR opr EXT D hh ll 6
Push (PCL); SP ← (SP) – 1
JSR opr,X Jump to Subroutine — — — — — IX2 D ee ff 7
Push (PCH); SP ← (SP) – 1
JSR opr,X IX1 D ff 6
PC ← Conditional Address
JSR ,X IX ED 5
FD
LDA #opr IMM A6 ii 2
LDA opr DIR B6 dd 3
LDA opr Load Accumulator EXT C6 hh ll 4
A ← (M) — — ↕ ↕ —
LDA opr,X with Memory Byte IX2 D6 ee ff 5
LDA opr,X IX1 E6 ff 4
LDA ,X IX F6 3

LDX #opr IMM AE ii 2

LDX opr DIR BE dd 3
LDX opr Load Index Register EXT CE hh ll 4
X ← (M) — — ↕ ↕ —
LDX opr,X with Memory Byte IX2 DE ee ff 5
LDX opr,X IX1 EE ff 4
LDX ,X IX FE 3

LSL opr DIR 38 dd 5

LSLA INH 48 3
Logical Shift Left
LSLX C 0 — — ↕ ↕ ⋅ INH 58 3
(Same as ASL) b7 b0
LSL opr,X IX1 68 ff 6
LSL ,X IX 78 5

LSR opr DIR 34 dd 5

LSRA INH 44 3
LSRX Logical Shift Right 0 C — — 0 ↕ ↕ INH 54 3
b7 b0 IX1 64 ff 6
LSR opr,X
LSR ,X IX 74 5

MUL Unsigned Multiply X : A ← (X) × (A) 0 — — — 0 INH 42 11

INSTRUCTION SET
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Table 12-6. Instruction Set Summary (Continued)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source CCR
Operation Description
Form
H I N Z C
NEG opr M ← –(M) = $00 – (M) DIR 30 ii 5
NEGA A ← –(A) = $00 – (A) INH 40 3
Negate Byte
NEGX X ← –(X) = $00 – (X) — — ↕ ↕ ↕ INH 50 3
(Two’s Complement)
NEG opr,X M ← –(M) = $00 – (M) IX1 60 ff 6
NEG ,X M ← –(M) = $00 – (M) IX 70 5

NOP No Operation — — — — — INH 9D 2

ORA #opr IMM AA ii 2
ORA opr DIR BA dd 3
Logical OR
ORA opr EXT CA hh ll 4
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Accumulator with A ← (A) ∨ (M) — — ↕ ↕ —

ORA opr,X IX2 DA ee ff 5
Memory
ORA opr,X IX1 EA ff 4
ORA ,X IX FA 3
ROL opr DIR 39 dd 5
ROLA INH 49 3
Rotate Byte Left
ROLX C — — ↕ ↕ ↕ INH 59 3
through Carry Bit b7 b0
ROL opr,X IX1 69 ff 6
ROL ,X IX 79 5
ROR opr DIR 36 dd 5
RORA INH 46 3
Rotate Byte Right
RORX C — — ↕ ↕ ↕ INH 56 3
through Carry Bit b7 b0
ROR opr,X IX1 66 ff 6
ROR ,X IX 76 5
RSP Reset Stack Pointer SP ← $00FF — — — — — INH 9C 2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
RTI Return from Interrupt SP ← (SP) + 1; Pull (X) ↕ ↕ ↕ ↕ ↕ INH 80 6
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
Return from SP ← (SP) + 1; Pull (PCH)
RTS INH
Subroutine SP ← (SP) + 1; Pull (PCL)
SBC #opr IMM A2 ii 2
SBC opr DIR B2 dd 3
Subtract Memory
SBC opr EXT C2 hh ll 4
Byte and Carry Bit A ← (A) – (M) – (C) — — ↕ ↕ ↕
SBC opr,X IX2 D2 ee ff 5
from Accumulator
SBC opr,X IX1 E2 ff 4
SBC ,X IX F2 3
SEC Set Carry Bit C←1 — — — — 1 INH 99 2
SEI Set Interrupt Mask I←1 — 1 — — — INH 9B 2
STA opr DIR B7 dd 4
STA opr EXT C7 hh ll 5
Store Accumulator in
STA opr,X M ← (A) — — ↕ ↕ — IX2 D7 ee ff 6
Memory
STA opr,X IX1 E7 ff 5
STA ,X IX F7 4
Stop Oscillator and
STOP — 0 — — — INH 8E 2
Enable IRQ Pin

INSTRUCTION SET MC68HC805P18

12-12
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Table 12-6. Instruction Set Summary (Continued)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source CCR
Operation Description
Form
H I N Z C
STX opr DIR BF dd 4
STX opr EXT CF hh ll 5
Store Index
STX opr,X M ← (X) — — ↕ ↕ — IX2 DF ee ff 6
Register In Memory
STX opr,X IX1 EF ff 5
STX ,X IX FF 4
SUB #opr IMM A0 ii 2
SUB opr DIR B0 dd 3
Subtract Memory
SUB opr EXT C0 hh ll 4
Byte from A ← (A) – (M) — — ↕ ↕ ↕
SUB opr,X IX2 D0 ee ff 5
Accumulator
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SUB opr,X IX1 E0 ff 4

SUB ,X IX F0 3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SWI Software Interrupt — 1 — — — INH 83 10
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Transfer
TAX Accumulator to X ← (A) — — — — — INH 97 2
Index Register
TST opr DIR 3D dd 4
TSTA INH 4D 3
Test Memory Byte
TSTX (M) – $00 — — — — — INH 5D 3
for Negative or Zero
TST opr,X IX1 6D ff 5
TST ,X IX 7D 4
Transfer Index
TXA Register to A ← (X) — — — — — INH 9F 2
Accumulator
Stop CPU Clock
WAIT and Enable — ↕ — — — INH 8F 2
Interrupts
A Accumulator opr Operand (one or two bytes)
C Carry/borrow flag PC Program counter
CCR Condition code register PCH Program counter high byte
dd Direct address of operand PCL Program counter low byte
dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte
EXT Extended addressing mode SP Stack pointer
ff Offset byte in indexed, 8-bit offset addressing X Index register
H Half-carry flag Z Zero flag
hh ll High and low bytes of operand address in extended addressing # Immediate value
I Interrupt mask ∧ Logical AND
ii Immediate operand byte ∨ Logical OR
IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR
INH Inherent addressing mode () Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX1 Indexed, 8-bit offset addressing mode ← Loaded with
IX2 Indexed, 16-bit offset addressing mode ? If
M Memory location : Concatenated with
N Negative flag ↕ Set or cleared
n Any bit — Not affected

INSTRUCTION SET
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Table 12-7. Opcode Map

12-14
Bit Branc Read-Modify-Write Control
Manipulation h Register/Memory
DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX
MSB MSB
0 1 2 3 4 5 6 7 8 9 A B C D E F LSB
LSB
5 5 3 5 3 3 6 5 9 2 3 4 5 4 3
0 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI SUB SUB SUB SUB SUB SUB 0
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 6 2 3 4 5 4 3
1 BRCLR0 BCLR0 BRN RTS CMP CMP CMP CMP CMP CMP 1
3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 11 2 3 4 5 4 3
2 BRSET1 BSET1 BHI MUL SBC SBC SBC SBC SBC SBC 2
3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 10 2 3 4 5 4 3
3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI CPX CPX CPX CPX CPX CPX 3
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 3 4 5 4 3
4 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR AND AND AND AND AND AND 4
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 2 3 4 5 4 3
5 BRCLR2 BCLR2 BCS/BLO BIT BIT BIT BIT BIT BIT 5
3 DIR 2 DIR 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 3 4 5 4 3
6 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR LDA LDA LDA LDA LDA LDA 6
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 4 5 6 5 4
7 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR TAX STA STA STA STA STA 7
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 2 3 4 5 4 3
8 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL CLC EOR EOR EOR EOR EOR EOR 8
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 2 3 4 5 4 3

INSTRUCTION SET
9 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL SEC ADC ADC ADC ADC ADC ADC 9
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 2 3 4 5 4 3
A BRSET5 BSET5 BPL DEC DECA DECX DEC DEC CLI ORA ORA ORA ORA ORA ORA A
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 2 2 3 4 5 4 3

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B BRCLR5 BCLR5 BMI SEI ADD ADD ADD ADD ADD ADD B
3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 2 3 4 3 2

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C BRSET6 BSET6 BMC INC INCA INCX INC INC RSP JMP JMP JMP JMP JMP C
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
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5 5 3 4 3 3 5 4 2 6 5 6 7 6 5
D BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR D
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 2 2 3 4 5 4 3
E BRSET7 BSET7 BIL STOP LDX LDX LDX LDX LDX LDX E
3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 2 4 5 6 5 4
F BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA STX STX STX STX STX F
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

INH = Inherent REL = Relative MSB

0 MSB of Opcode in Hexadecimal
IMM = Immediate IX = Indexed, No Offset LSB
DIR = Direct IX1 = Indexed, 8-Bit Offset 5 Number of Cycles
LSB of Opcode in Hexadecimal 0 BRSET0 Opcode Mnemonic
EXT = Extended IX2 = Indexed, 16-Bit Offset 3 DIR Number of Bytes/Addressing Mode

MC68HC805P18
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GENERAL RELEASE SPECIFICATION

8
2
SECTION 13
ELECTRICAL SPECIFICATIONS 3
4
13.1 Introduction

This section contains electrical and timing specifications for the MC68HC805P18. 5
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13.2 Maximum Ratings

6
Rating Symbol Value Unit 7
Supply Voltage VDD –0.3 to +7.0 V

Input Voltage VIN VSS –0.3 to VDD + 0.3 V

8
Factory Mode (IRQ Pin Only) VIN VSS –0.3 to 2 x VDD V
9
Current Drain Per Pin Excluding VDD and VSS I 25 mA

Storage Temperature Range TSTG –65 to +150 °C 10

NOTE: Voltages referenced to VSS
11
13.3 Operating Temperature Range
12
Rating Symbol Value Unit

Operating Temperature Range TL to TH

13
MC68HC805P18 (Standard) 0 to +70
TA °C
MC68HC805P18 (Extended)
MC68HC805P18 (Automotive)
–40 to +85
–40 to +125
14
A
NOTE
16
This device contains circuitry to protect the inputs against damage
due to high static voltages or electric fields; however, it is advised 17
that normal precautions be taken to avoid application of any voltage
higher than maximum-rated voltages to this high-impedance circuit.
For proper operation, it is recommended that VIN and VOUT be
18
constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of
operation is enhanced if unused inputs are connected to an 19
appropriate logic voltage level (for instance, either VSS or VDD).
20
ELECTRICAL SPECIFICATIONS
Rev. 1.0
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13.4 Thermal Characteristics

8 Characteristic Symbol Value Unit

2 Thermal Resistance
Plastic θJA 60 °C/W
SOIC 60
3
13.5 Power Considerations
4
The average chip-junction temperature, TJ, in °C, can be obtained from:
5 TJ = TA + (PD × θJA) (1)
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6 where:
TA = Ambient temperature, °C
7 θJA = Package thermal resistance, junction to ambient, °C/W.
PD = PINT + PI/O
PINT = IDD × VDD watts (chip internal power)
8 PI/O = Power dissipation on input and output pins (user-determined)

9 For most applications, PI/O « PINT and can be neglected.

The following is an approximate relationship between PD and TJ (neglecting PI/O):

10
PD = K ÷ (TJ + 273 °C) (2)
11 Solving equations (1) and (2) for K gives:

12 K = PD × (TA + 273 °C) + θJA × (PD)2 (3)

where K is a constant pertaining to the particular part. K can be determined from

13 equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of
K, the values of PD and TJ can be obtained by solving equations (1) and (2)
14 iteratively for any value of TA.

A
16
17
18
19
20
ELECTRICAL SPECIFICATIONS MC68HC805P18
13-2
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13.6 DC Electrical Characteristics (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C)

Characteristic Symbol Min Typ Max Unit

8
Output Voltage VOL — — 0.1
ILoad = 10.0 µA VOH VDD –0.1 — —
V
2
Output High Voltage
(ILoad = –0.8 mA) PA0–PA7, PB5–PB7,
PC0–PC7, PD5/CKOUT
VOH VDD –0.8 — — V 3
Output Low Voltage
(ILoad = 1.6 mA) PA0–PA7, PB5–PB7, VOL — — 0.4 V 4
PC0–PC7, PD5/CKOUT
Input High Voltage
PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT, VIH 0.7 x VDD — VDD V
5
TCAP/PD7, IRQ, RESET, OSC1
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Input Low Voltage 6

PA0–PA7, PB5–PB7, PC0–PC7, PD5, VIL VSS — 0.2 x VDD V
TCAP/PD7, IRQ, RESET, OSC1
Supply Current
7
Run — 4.75 7.50 mA
Wait (see Note 3) — 2.75 5.00 mA 8
Stop (see Note 8)
IDD
25 °C — TBD 350 µA
0 °C to +70 °C (Standard) — TBD 400 µA 9
–40 °C to +85 °C (Extended) — TBD 500 µA
–40 °C to +125 °C (Automotive — TBD 500 µA
I/O Ports Hi-Z Leakage Current
10
PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT, IIL — — ±10 µA
TCAP/PD7 11
I/O Ports Switch Resistance
RPTA 62 — 102 k
(Pullup Enabled PA0–PA7)
A/D Ports Hi-Z Leakage Current
12
IIL — — ±1 µA
PC3–PC7
Input Current
IIN — — ±1 µA
13
RESET, IRQ, OSC1
Capacitance
Ports (as Input or Output) COUT — — 12 pF
14
RESET, IRQ CIN — — 8
EEPROM Program/Erase Time (128 Byte Array) A
Byte — 2 10
ms
Block (Erase Only) — 5 15
Bulk (Erase Only) — 10 50 16
Low Voltage Reset Voltage 3.6 3.8 — V
NOTES: 17
1. All values shown reflect average measurements.
2. Typical vlaues at midpoint of voltage range, 25 °C only.
3. Wait IDD with active systems: Timer, SIOP, and A/D.
18
4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source (fosc = 4.2 MHz), all
inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2
5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V
19
6. Stop IDD measured with OSC1 = VSS
7. Wait IDD is affected linearly by the OSC2 capacitance.
8. Stop IDD maximum values given with LVR option enabled.
20
ELECTRICAL SPECIFICATIONS
Rev. 1.0
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13.7 Active Reset Characteristics

8 CLoad
Rise Time Fall Time Pulse Width Pullup

2 0.5 µs 13 ns 2.4 µs 50 pF 10 K

1.0 µs 20 ns 2.7 µs 100 pF 10 K

3 2.5 µs 20 ns 2.7 µs 250 pF 10 K

NOTE: VDD = 4.5 Vdc, VSS = 0 Vdc, TA = 125 °C

4
5 13.8 A/D Converter Characteristics
(VDD = 4.5 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise noted)
Freescale Semiconductor, Inc...

6 Characteristic Min Max Unit Comments

Resolution 8 8 Bits
7
Absolute Accuracy
— ± 1 1/2 LSB Including quantization
(VDD ≥ VREFH > 4.5)
8 Conversion Range VSS VREFH A/D accuracy may decrease proportionately as
V
VREFH VSS VDD VREFH is reduced below 4.5
9 Input Leakage
AD0, AD1, AD2, AD3 — ±1 µA
10 VREFH — ±1 µA

Conversion Time
32 32 tAD*
11 (Includes Sampling Time)

Monotonicity Inherent (Within Total Error)

12 Zero Input Reading 00 01 Hex Vin = 0 V

Full-Scale Reading FE FF Hex Vin = VREFH

13 Sample Time 12 12 tAD*

Input Capacitance — 12 pF
14
Analog Input Voltage VSS VREFH V

A *tAD = tcyc if clock source equals MCU

16
17
18
19
20
ELECTRICAL SPECIFICATIONS MC68HC805P18
13-4
For More Information On This Product,
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13.9 SIOP Timing

(VDD = 4.5 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise note)
8
Number Characteristic Symbol Min Max Unit
Operating Frequency 2
Master fSIOP(M) 1 1 fOP
Slave fSIOP(S) dc 1
3
Cycle Time
1 Master tSCK(M) 1 1 tCYC
Slave tSCK(S) — 1 4
2 SCK Low Time tCYC 238 — ns
3 SDO Data Valid Time tv — 200 ns 5
4 SDO Hold Time tHO 0 — ns
Freescale Semiconductor, Inc...

5 SDI Setup Time tS 100 — ns 6

6 SDI Hold Time tH 100 — ns
NOTES: 7
1. fOP = fOSC ÷ 2 = 2.1 MHz max; tCYC = 1 ÷ fOP
2. In master mode, the SCK rate is determined by the programmable option in MOR1.
8
9
t1 t2

10
SCK

11
t5 t6

12
SDI SDI SDI SDI

t3 t4
13

SDI
14
SDI SDI BIT 7

A
Figure 13-1. SIOP Timing Diagram 16
17
18
19
20
ELECTRICAL SPECIFICATIONS
Rev. 1.0
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GENERAL RELEASE SPECIFICATION

13.10 OSC Out Timing

8 Characteristic Symbol Min Max Unit
Cycle Time 1* 476 — ns
2 Rise Time 4* 3.5 12 ns
Fall Time 5* 7.5 27.5 ns
3 Pulse Width 2 and 3* 200 — ns
*Refer to Figure 13-2
4
5 (1)
(2) (3)
Freescale Semiconductor, Inc...

6
OSC OUT
7
8 (4) (5)

9 Figure 13-2. OSC Out Timing

10
NOTE
11 All timing is shown with respect to 20% and 70% VDD. Maximum rise
and fall times assume 44% duty cycle. Minimum rise and fall times
12 assume 55% duty cycle

13
14
A
16
17
18
19
20
ELECTRICAL SPECIFICATIONS MC68HC805P18
13-6
For More Information On This Product,
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GENERAL RELEASE SPECIFICATION

13.11 Control Timing

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise note)
8
Characteristic Symbol Min Max Unit
Frequency of Operation 2
Crystal Option fOSC — 4.2 MHz
External Clock Option dc 4.2
3
Internal Operating Frequency
Crystal (fosc ÷ 2) fOP — 2.1 MHz
External Clock (fosc ÷ 2) dc 2.1 4
Cycle Time tCYC 476 — ns
Crystal Oscillator Startup Time tOXOV — 100 ms 5
Stop Recovery Startup Time (Crystal Oscillator) tILCH — 100 ms
Freescale Semiconductor, Inc...

RESET Pulse Width tRL 1.5 — tCYC 6

Interrupt Pulse Width Low (Edge-Triggered) tILIH 125 — ns
Interrupt Pulse Period tILIL * — tCYC 7
OSC1 Pulse Width tOH, tOL 200 — ns
A/D On Current Stabilization Time tADON — 100 µs 8
RC Oscillator Stabilization Time (A/D) tRCON — 5.0 µs
* The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service 9
routine plus 21 tCYC.

10
11
12
13
14
A
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
Rev. 1.0
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 Freescale Semiconductor, Inc...

9
8
7
6
5
4
3
2
8

20
19
18
17
16
14
13
12
11
10

13-8
t
VDDR
V
DD V
DD THRESHOLD (1–2 V TYPICAL)

OSC12

4064 tCYC

t
GENERAL RELEASE SPECIFICATION

CYC
INTERNAL
PROCESSOR
CLOCK1

INTERNAL
ADDRESS 3FFE 3FFF NEW PC NEW PC 3FFE 3FFE 3FFE 3FFE 3FFF NEW PC NEW PC
BUS1

INTERNAL
DATA NEW NEW OP PCH PCL OP
PCH PCL CODE CODE
BUS1
tRL

ELECTRICAL SPECIFICATIONS

Go to: www.freescale.com
RESET NOTE 3

For More Information On This Product,

Freescale Semiconductor, Inc.

NOTES:
1. Internal timing signal and bus information not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the PH2 clock following the rising edge of RESET initiates the reset sequence.

Figure 13-3. Power-On Reset and External Reset Timing Diagram

MC68HC805P18
 Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION

8
2
SECTION 14
MECHANICAL SPECIFICATIONS 3
4
14.1 Introduction

This section provides package dimension drawings for the 28-pin dual in-line (DIP) 5
or 28-pin small outline (SOIC) packages.
Freescale Semiconductor, Inc...

6
To make sure that you have the latest case outline specifications, contact one of
the following:
7
• Local Motorola Sales Office
• Motorola Mfax 8
– Phone 602-244-6609
– EMAIL [email protected] 9
• Worldwide Web (wwweb) at http://design-net.com
10
Follow Mfax or wwweb on-line instructions to retrieve the current mechanical
specifications.
11
14.2 28-Pin Dual In-Line Package (Case #710) 12

! 
13
  ! !   
  #!  %%  !
$" ! ! 
! ! !   14
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28 15     ! !  
#  
B
     ! "
  
A
 
1 14  
 


A C L



 
    

   
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N 



  

 


   


  

17
    
H G J    
F D 
 


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°  °
   
°  °
18
      

19
20
MECHANICAL SPECIFICATIONS
Rev. 1.0
For More Information On This Product,
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 Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION

14.3 28-Pin Small Outline Package (Case #751F)

8
-A-
2 28 15 ! 
    ! 
14X P   %   
-B-        !   !

3 1 14
       ! " 
!" 
 $"  !"  
   
     ! "

4 28X D
M
 !"  #
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  !!  $  
    !     ! $" !
R X 45° !

5 -T- C  


 




      
-T-       
26X G
Freescale Semiconductor, Inc...


      

6 K



F



 
 





       
    

7 J


°


°


°
 

°
 
    

8
9
10
11
12
13
14
A
16
17
18
19
20
MECHANICAL SPECIFICATIONS MC68HC805P18
14-2
For More Information On This Product,
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 Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION

8
2
SECTION 15
ORDERING INFORMATION 3
4
15.1 Introduction

This section contains instructions for ordering the MC68HC805P18. 5

Freescale Semiconductor, Inc...

15.2 MC Order Numbers

6
Table 15-1 shows the MC order numbers for the available package types. 7
Table 15-1. MC Order Numbers 8
Operating
MC Order Number Temperature Range 9
MC68HC805P18P (Standard) 0 °C to 70 °C
10
MC68HC805P18DW (Standard) 0 °C to 70 °C

MC68HC805P18CP (Extended) –40 °C to +85 °C 11

MC68HC805P18CDW (Extended) –40 °C to +85 °C

MC68HC805P18MP (Automotive) –40 °C to +125 °C 12

MC68HC805P18MDW (Automotive) –40 °C to +125 °C
13
P = Plastic Dual In-Line Package
DW = Small Outline (Wide Body) Package
14
A
16
17
18
19
20
ORDERING INFORMATION
Rev. 1.0
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 Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION

8
2
APPENDIX A
EMULATION
3
4
This appendix discusses the functional differences between the P-series devices.
The MC68HC805P18 can be used to emulate the following devices: 5
MC68HC05P1A MC68HC05P7
Freescale Semiconductor, Inc...

MC68HC05P2 MC68HC05P7A 6
MC68HC05P3 MC68HC05P8
MC68HC05P4 MC68HC05P9
MC68HC05P4A MC68HC705P9
7
MC68HC05P6 MC68HC05P10
MC68HC705P6 MC68HC05P18 8
These functional differences will be summarized in: 9
Table A-1. Elements of Memory
Table A-2. Memory Breakdown by Types 10
Table A-3. P-Series Features
Table A-4. Mask Options
11
12
13
14
A
16
17
18
19
20
EMULATION
Rev. 1.0
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GENERAL RELEASE SPECIFICATION

8 Table A-1. Elements of Memory

User ROM
Device RAM User ROM EPROM EEPROM
2 EEPROM Security
R 2320 b
128 b
3 P1A
0080-00FF
0020-004F
0100-08FF*
N N N N

4 P2
96 b
R 3088 b
0020-004F N N N N
00A0-00FF
1300-1EFF
5 128 b
R 3072 b
128 b
P3 0020-004F N N N
0080-00FF 0100-017F
Freescale Semiconductor, Inc...

0300-0EFF
6
3072 b
128 b 128 b
705P3 N 0020-004F N N
7 0080-00FF
0300-0EFF
0100-017F

R 4160 b
8 P4/P4A
176 b
0050-00FF
0020-004F N N N N/Y
0100-10FF

9 P6
176 b
R 4672 b
0020-004F N N N N
0050-00FF
0100-10FF*
10 4672 b
176 b
705P6 N 0020-004F N N N
0050-00FF
11 0100-12FF*

R 2112 b
128 b
12 P7/P7A
0080-00FF
0020-004F
0100-08FF*
N N N N/Y

112 b R 2064 b 32 b
13 P8
0090-00FF 1680-1E7F
N
0030-004F
N N

R 2112 b
14 P9/P9A
128 b
0080-00FF
0020-004F N N N N/Y
0100-08FF

A 128 b
2112 b
705P9 N 0020-004F N N N
0080-00FF
0100-08FF*
16 R 4160 b
128 b
P10 0020-004F N N N N
0080-00FF
17 0100-10FF

R 8064 b
192 b 128 b
18 P18
0050-010F
0020-004F
1FC0-3EFF
N
0140-01BF
N N

19 805P18
192 b
N N
128 b
8064 b
0020-004F Y
0050-010F 0140-01BF
1FC0-3EFF
20
EMULATION MC68HC805P18
A-2
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GENERAL RELEASE SPECIFICATION

Table A-2. Memory Breakdown by Types 8

P3/ P4/ 705 P7/ P9/ 805
Range P1a P2 P6 P8 P10 P18
705P3 P4a P6 P7a 705P9 P18
2
0020–004F ROM ROM ROM/E ROM ROM ROM ROM ROM/E ROM ROM UEE

0030–004F EE 3
0050–007F RAM RAM RAM RAM RAM

0080–008F RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM
4
0090–009F RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM
5
00A0–00FF RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM
Freescale Semiconductor, Inc...

0100–010F ROM EE ROM ROM E ROM ROME ROM RAM RAM 6

0110–013F ROM EE ROM ROM E ROM ROME ROM

0140–017F ROM EE ROM ROM E ROM ROME ROM EE EE

7
0180–01BF ROM ROM ROM E ROM ROME ROM EE EE
8
01C0–02D1 ROM ROM ROM E ROM ROME ROM ROM

02D2–02FF ROM ROM ROM E ROM ROME ROM 9

0300–08FF ROM ROME ROM ROM E ROM ROME ROM

0900–0EFF ROME RON ROM E ROM 10

0F00–0FEF ROM ROM ROM E ROM
11
0FF0–10FF ROM ROM E ROM

1100–12FF ROM E 12
1300–167F ROM

1680–1EFF ROM ROM 13

1F00 ROM ROM ROM ROM ROM ROM
14
1F01–1FBF ROM ROM ROM ROM ROM ROM ROM ROM

1FC0–1FEF ROM ROM ROM ROM ROM ROM ROM ROM ROM UEE A
1FF0–3EFF ROM UEE

3F00–3F01 UEE 16
3F02–3FEF ROM

NOTE: I/O registers are common to all parts so they are not included in the table. There are an additional 16 bytes
17
of user vectors in the memory map for each device.
18
E = EPROM
EE = EEPROM
PEE = User EEPROM 19
20
EMULATION
Rev. 1.0
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GENERAL RELEASE SPECIFICATION

8 Table A-3. P-Series Features

Devices Mask Option MOR A/D LVR High Current
2 P1A Y N N N Y

3 P2 Y N N N N

P3/705P3 Y/N N/Y N N N

4 P4/P4A Y N N N N/Y

P6/705P6 Y/N N/Y Y N N

5 P7/P7A Y N N N N/Y
Freescale Semiconductor, Inc...

P8 Y N Y N N
6
P9/705P9/P9A Y/N/Y N/Y/N Y N N/N/Y

7 P10 Y N N N N

P18/805P18 Y/N N/Y Y Y Y

8
9 Table A-4. Mask Options

10 Devices XTAL/RC SIOP

Clock Rate
SIOP
MSB/LSB
Port A
PU/INT
STOP
to HALT

11 P1A Y N N Y Y

P2 Y N N N N

12 P3 N N N N N

P4/P4A Y N Y N/Y N/Y

13 P6 Y Y Y N Y

P7/P7A Y N Y N/Y N/Y

14
P8 N N N N N

A P9/P9A N N Y N/Y N/Y

P10 Y N Y Y N
16 P18 N Y* Y Y Y

* The MC68HC05P18 and MC68HC805P18 have selectable clock rates that are four times as fast as the
17 MC68HC05P6 selectable rates.

18
19
20
EMULATION MC68HC805P18
A-4
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GENERAL RELEASE SPECIFICATION

Bit 7 6 5 4 3 2 1 Bit 0 8
$0F Read: 0 1 0 0 1 0 OPTCOP OPTIRQ

Write: 2
Reset: Unaffected by reset
3
Figure A-1. MC68HC705P3 Mask Option Register 4

Bit 7 6 5 4 3 2 1 Bit 0
5
Freescale Semiconductor, Inc...

$900 Read: — RC SWAIT SPR1 SPR0 LSBF IRQ COP

6
Write:

Reset: Unaffected by reset 7

8
Figure A-2. MC68HC705P6 Mask Option Register
9
Bit 7 6 5 4 3 2 1 Bit 0

$900 Read: — — — — — SIOP IRQ COP

10
Write:
11
Reset: Unaffected by reset

12
Figure A-3. MC68HC705P9 Mask Option Register
13
Bit 7 6 5 4 3 2 1 Bit 0 14
Read: CLKOUT LVRE SWAIT SPR1 SPR0 LSBF LEVIRQ COPEN
MOR1
Write: A
Reset: Unaffected by reset
16
Bit 7 6 5 4 3 2 1 Bit 0 17
Read: PA7PU PA6PU PA5PU PA4PU PA3PU PA2PU PA1PU PA0PU
MOR2
Write: 18
Reset: Unaffected by reset
19
Figure A-4. MC68HC805P18 Mask Option Register 20
EMULATION
Rev. 1.0
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 Freescale Semiconductor, Inc.

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68HC805P18GRS/D
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