8255 Programmable Peripheral Interface
8255 Programmable Peripheral Interface
INTEL-8255
The 8255 is a general purpose programmable, Parallel I/O device designed for use with Intel
microprocessors. It consists of three 8-bit bidirectional I/O ports (24 I/O lines) that can be
programmed to transfer data under various conditions from simple I/O to interrupt I/O.
The three ports are PORT A, PORT B & PORT C.
Port A contains one 8-bit output latch/buffer and one 8-bit input buffer. Port B is same as PORT
A. However, PORT C can be split into two parts PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word. The three ports are divided in two groups Group A (PORT A
and upper PORT C) Group B (PORT B and lower PORT C).
Block Diagram:
Pin Diagram:
Read write control logic:
The function of this block is to manage all the internal and external transfers of both data and
control or status word. The details of each pin connected with this block are described below.
𝑪𝑺 (Chip Select)- A “Low” on this input pin enables the communication between the 8085 and
MPU.
A0 and A1- These are the address lines of 8255 which are directly connected to the MPU lower
address lines (A0, A1). The bit combination of these signals are shown below.
Mode 1: In this mode, input or outputting of data is carried out by taking the help of handshaking
signals, also known as strobe signals. The basic features of this mode are:
Ports A and B can function as 8-bit I/O ports, taking the help of pins of Port C.
I/Ps and O/Ps are latched.
Interrupt logic is supported.
Handshake signals are exchanged between CPU and peripheral prior to data transfer.
In this mode, Port C is called status port.
There are two groups in this mode—group A and group B. They can be configured
separately. Each group consists of an 8-bit port and a 4-bit port. This 4-bit port is used for
handshaking in each group.
Mode 2: In this mode, Port A can be set up for bidirectional data transfer using handshake signals
from Port C. Port B can be set up either in mode 0 or mode 1.
The basic operations of the three modes are shown below:
The control word format, when 8255 is operated in I/O mode, is shown below. For 8255 PPI to
be operated in I/O mode, D7 bit must be 1.
The three ports are divided into two groups—Groups
A and B. Group A consists of Port A and CU ( PC4–PC7 ) . Port A can be operated in any of the
modes—0, 1 or 2. Group B consists of Port B and CL( PC0–PC3 ). Here Port B can be operated in
either mode 0 or 1.
• It is a programmable device.
T T L compatible.
• 8255A has three ports
• PORT A
• PORT B
• PORT C
ACK’
Busy
• The data is sent by CPU through this port , when the peripheral request it.
• In the INPUT mode , When RESET is High all 24 pins (3-ports) be a input mode.
• i.e all flip flops are cleared and the interrupts are rest.
• This can be avoid by writing single control word to the control registers , when
required.
Pin Diagram
Function of Pins
• Data bus(D0-D7):These are 8-bit bi-directional buses, connected to 8085
data bus for transferring data.
• CS: This is Active Low signal. It stands for Chip Select. A LOW on this
input selects the chip and enables the communication between the 8255 and
the CPU.
• Read: This is Active Low signal, when it is Low the microprocessor reads
data from a selected I/O port of 8255A.
A1 A0 Select
0 0 PA
0 1 PB
1 0 PC
Control
1 1
reg.
• RESET: This is used to reset the device. That means clear control
registers.
• PA0-PA7: It is the 8-bit bi-directional I/O pins used to send the data to
peripheral or to receive the data from peripheral.
• PB0-PB7: Similar to PA
• PC0-PC7:This is also 8-bit bidirectional I/O pins. These lines are divided
into two groups.
1. PC0 to PC3(Lower Groups)
2. PC4 to PC7 (Higher groups)
• The internal data bus and Outer pins D0-D7 pins are
connected in internally.
PORT A:
• This is a 8-bit buffered I/O latch.
• It can be programmed by mode 0 , mode 1, mode 2 .
PORT B:
• This is a 8-bit buffer I/O latch.
• It can be programmed by mode 0 and mode 1.
PORT C:
• This is a 8-bit Unlatched buffer Input and an Output
latch.
• It is splitted into two parts.
• It can be programmed by bit set/reset operation.
Operation modes in 8255
Two operating modes:
– I/O mode( mode 0, mode 1, mode2)
– Bit set/Reset mode
I/O MODES:
• MODE 0 (Simple input / Output)
• In this mode , port A, port B and port C is used as individually (Simply).
• Features:
• Outputs are latched , Inputs are buffered not latched.
• Ports do not have Handshake or interrupt capability.
Control words
• Two control words:
– I/O mode set control word(MSW)
– Bit set/reset control word(BSR)
• For setting I/O functions and mode of operation the I/O mode
set control word is send to control register.
X X X BIT SET/RESET
1=SET
Don’t care 0=RESET
Bit select
0 1 2 3 4 5 6 7
0 B
10 0 1 0 1 0 1
0 B
01 1 1 0 0 1 1
0 B
02 0 0 1 1 1 1
• Example:
– PC3 is Set then control register will be 0XXX0111.
• X is a don’t care.
FORMAT OF I/O MODE:
The mode format for I/O as shown in figure
D7 D6 D5 D4 D3 D2 D1 D0
Group A Group B
Port C Upper
1=Input Port C Lower
Mode set
0=Output 1=Input
1-I/O mode
0-BSR mode Port B 0=Output
1=Input Port B
0=Output 1=Input
Mode selection 0=Output
00=mode 0 Mode selection
01=mode 1 0=mode 0
1x=mode 2 1=mode 1
• The control word for both mode is same.
• Bit D7 is used for specifying whether word
loaded in to Bit set/reset mode or Mode
definition word.
• D7=1=Mode definition mode.
• D7=0=Bit set/Reset mode.