KCS 302H

COMPUTER ORGANIZATION AND ARCHITECTURE

Course Outcome ( CO)
Bloom's KnowledgeLevel (KL)
At the end of course , the student will be able to
understand
Study of the basic structure and operation of a
CO2 Analysisof the design of arithmetic & logic unit digital computer system.
and understanding of the fixed point and floating
K, Ky
point arithmetic operations. Kz, K4
CO3
CO 4
Implementation of control unit techniques and the concept of Pipelining
Understanding the hierarchical memorysystem, cache memories and virtual K3
COS Understanding different ways of communicating with I/O devices and standard I/O
the memory Kz
interfaces Kz Ki
DETAILED SYLLABUS 3-1-0
Unit
Topie Proposed
Introduction: Functional units of digital system and their Lecture
types of buses and bus arbitration. Register, bus
interconnections, buses, bus architecture,
general registers organization, stack organization andand memory transfer. Processor organization,
08

Arithmetic and logic unit: Look ahead carriesaddressing modes.

adders. Multiplication: Signed operand
multiplication, Booths algorithm and array multiplier. Division and logic 08
arithmeticoperation, Arithmetic &logic unit design. IEEE operations. Floating point
Control Unit: Instruction types, formats, instruction cyclesStandard for Floating Point Numbers
micro operations, execution of a complete and sub cycles (fetch and execute etc),
instruction.
Computer, Pipelining. Hardwire and micro programmed Program Control, Reduced Instruction Set
control: micro programme sequencing, 08
concept of horizontal and vertical
microprogramming.
Memsry: Basic concept and hierarchy. semiconductor RAM
IV organization. ROM memories. Cache memories: concept and design memories, 2D & 2 1/2D memory
mapping and replacement Auxiliary memories: magnetic disk, issues & performance, address 08
Virtual memory: concept implementation. magnetic tape and optical disks
Input /Output: Peripheral devices. I/O
interrupts and exceptions. Modes of Data interface, I/O ports, Interrupts: interrupt hardware, types of
Direct Memory Access., I/O channels and Transfer: Programmed I/0, interrupt initiated VO and 08
processors. Serial Communication: Synchronous &
asynchronous communication, standard communication
Text books: interfaces.
1. Computer System Architecture - M. Mano
2. Carl Hamacher. Zvonko
Vranesic, Safwat Zaky Computer Organization,
3. John P. Hayes, Computer McGraw-Hill, Fifth Edition, Reprint 2012
Architecture and Organization, Tata McGraw Hill,
4. William Stallings, Computer Organization and Third Edition. 1998. Reference books
edition. 2006. Architecture-Designing for Performance, Pearson Education, Seventh
5. Behro0z Parahami, "Computer
6. DavidA. Patterson and John L. Architecture", Oxford University Press, Eighth Impression, 2011.
Hennessy, "Computer Architecture-A Quantitative
of reed India Private Limited, Fifth
edition, 2012 Approach", Elsevier, a division
7. Structured Computer Organization,
Tannenbaum(PHI)
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254
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274

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Note the
7.3 Following
nine F F F F F
Decrement
that, Auto
Increment
Auto
Addressing
Indexed
AddressingRegister
Indirect
Relative Mode
Register Mode Immediate
ModeIndirectDirect
Mode ModeNurnerical
location
execution The incremented The
Base-register operand the In address Content
instruction In
addressing table instruction the the
mode autodecrement autoincrement
indirect-addressing relative-addressing
=500
Exarnple 7.3 399, located or
field of localied PC
modes lists i.e., the
to mode +
401 and 200 and
specifies instruction. at
the 450.
gives 600 the =702. the
: aftermode INSTRUCTIONS
at COMPUTER
values mode
content
i.e., 200
address
the AC 450 AC 700
the AC 900 AC 325 The
decrement is the and mode,
mode of execution the same
900 mode, operand
the Thus,
is of 201. part
399 400 600 702 400 800 500 201 same
of effective the result loaded the the
index ofthe
address effective atthe
accumulator the of as 702 effectivethe
as into content
content the the register
address indexed instruction.
is
used. reqister
instruction. the address 325.
=399)
(EA 400)
(EA = 600)
(EA = 702)
(EA = address
of
and ACof
accumulatoI i.e., so PC
addressing AC
register indirect
the is EAthe is
iswillAfter is
300 800 500
loaded =500+
450 700 900 325 700 400 operand sum
loaded obtained
be
R1 mode accessing
mode. AC. of 202.
with to 100 with
loaded the So, after
399 except =600.
the address operana
the the
contentsprior adaing
into that Ihus, two-WOru
errecuve
to part 3e.
AC R1 275
the ue
for at 1s O1
e
DESIGN
PROCESSOR