ANALOG CIRCUIT DESIGN

Department of Electronics and Communication

Engineering
 ANALOG CIRCUIT DESIGN
Unit 1: Physics of MOS transistors and MOSFET biasing
➢ MOSFET Structure,
➢ MOS Symbols,
➢ MOS I/V Characteristics, Derivation of I/V Characteristics,
➢ MOS Transconductance,
➢ Second-Order Effects,
➢ MOS Device Capacitances,
➢ MOS Small Signal Model,
➢ MOS SPICE models,
➢ NMOS Versus PMOS,
➢ Devices General Considerations, Biasing,
➢ DC and Small – signal analysis,
➢ Operating point analysis and design
ANALOG CIRCUIT DESIGN
Structure of MOSFET

3D view of an NMOS transistor 2D view

• Leff is the distance between the source and the drain regions
• LD is the side diffusion length due to the diffusion of S and D regions during
fabrication
• Ldrawn is the dimension drawn in the layout of the transistor, actual length of the gate
• Leff = Ldrawn – 2LD
ANALOG CIRCUIT DESIGN
CMOS structure

• Both NMOS and PMOS devices are fabricated on the same substrate
• The PMOS device is fabricated in a “local substrate” called an “n-well”
• The p-substrate is normally connected to the highest negative
potential and n-well to the highest positive potential.
• P-substrate - ground and n-well - VDD.
• Ensures S/Sub and D/Sub pn junctions are reverse-biased at all times
ANALOG CIRCUIT DESIGN
Symbols

•In Analog circuits symbols in (b) are most often used

•Symbols in (a) are used only when substrate terminals are connected
to potentials other than the supply rails
•Symbols depicted in (c) are never used in analog circuits
ANALOG CIRCUIT DESIGN
Threshold Voltage

• Gate and the Substrate terminals form a Capacitor

• An increase in VG causes the holes in the p-substrate to be repelled from the gate
area leaving behind negative ions
• The positive charge on the gate is mirrored by the negative charge in the substrate.
 ANALOG CIRCUIT DESIGN
Threshold Voltage

• As VG becomes sufficiently positive, free electrons are attracted to the oxide-

silicon interface, forming a conductive channel.
• The electrons are readily provided by the n+ source and drain regions and not
by the substrate.
The channel is called
‘Inversion layer’

• The gate potential at which the channel begins to appear is called the
“threshold voltage,” VTH . MOSFET is now turned ON.
 ANALOG CIRCUIT DESIGN
Threshold Voltage

• Threshold voltage of NFET is defined as “the gate voltage for which

the interface is as much n-type as the substrate is p-type”
Q dep
VTH =  MS + 2 F +
C ox
• ɸMS is the work function difference between the polysilicon gate
and the Si substrate
• Qdep is the charge in the depletion region Q dep = 4qε si N sub |  F |
• εsi is electrical permittivity of Si = 1.05 x 10-10F/m
• Cox is the gate-oxide capacitance per unit area
 ANALOG CIRCUIT DESIGN
Threshold Voltage
KT N sub
• ɸF is the fermi potential given by  F = ln
q ni

• K – Boltzmann constant
• Nsub – substrate doping density
• ni – intrinsic carrier concentration = 1.5 x 1010/cm3
 ANALOG CIRCUIT DESIGN
Threshold Voltage

• Threshold voltage is adjusted by implantation of dopants into the

channel area during device fabrication

• Implantation of p+ dopants in the channel area alters the doping

level of the substrate.
• Gate voltage required to deplete the interface increases. Hence
VTH increases
 ANALOG CIRCUIT DESIGN
Threshold Voltage – PMOS device

• In PMOS device, all polarities are reversed

• The channel/Inversion layer is made up of holes.

• Gate voltage and hence VTH is negative

ANALOG CIRCUIT DESIGN
MOS Current Equation - I/V Characteristics

Let ‘I’ be the current flowing through a semiconductor bar

I = Qd. v …………………………………(1)
Qd – carrier charge density along the current flow – C/m
v – velocity of the charges – m/s
Now, consider an NFET with S and D terminals grounded

Source: “Design of CMOS Analog Integrated Circuits” by Razavi

ANALOG CIRCUIT DESIGN
MOS Current Equation - I/V Characteristics

There is an Uniform charge distribution in the channel

The channel charge density (charge/unit length), Qd, is

proportional to VGS – VTH since the inversion layer is formed only

when VGS ≥ VTH.

Qd = WCox(VGS – VTH)………………………(2)
ANALOG CIRCUIT DESIGN
MOS Current Equation - I/V Characteristics

Now, let D be made positive w.r.t the source

The effect of drain voltage at the source end = 0

The effect of drain voltage at the drain end = VDS
The net positive voltage at the source end = VGS
The net positive voltage at the drain end = VGS - VDS
Source: “Design of CMOS Analog Integrated Circuits” by Razavi
 ANALOG CIRCUIT DESIGN
MOS Current Equation - I/V Characteristics

The positive potential decreases from Source to drain

The channel width decreases from S to D. Non-uniform channel

The positive potential at any point ‘x’ along the channel is [VGS – V(x)]
V(x) is the effect of VDS at point ‘x’
Source: “Design of CMOS Analog Integrated Circuits” by Razavi
ANALOG CIRCUIT DESIGN
MOS Current Equation - I/V Characteristics

The channel charge density at point ‘x’ is

Qd = WCox(VGS – V(x) – VTH ) ………………………(3)
From equation (1)
ID = - WCox(VGS – V(x) – VTH ).v ………………………(4)
For semiconductors, v = μE ………………………………………………….(5)
where μ = mobility of charge carriers
and E = - dv/dx
Combining the equations
ID = WCox(VGS – V(x) – VTH )μ dv/dx ……………..…(6)
ANALOG CIRCUIT DESIGN
MOS Current Equation - I/V Characteristics

ID = WCox(VGS – V(x) – VTH )μ dv/dx ……………..…(6)

As ‘x’ varies from 0 to L, V(x) varies from 0 to VDS
Integrating this equation
L VDS
..….(7)
 I Ddx =
0
 ox n GS
WC
0
μ (V − V(x) − VTH )dV

2
W VDS
I D = μ n C ox [(VGS − VTH )VDS − ] …….(8)
L 2

For different values of VGS, the parabolas represented by eqn.(8) are

shown
ANALOG CIRCUIT DESIGN
MOS Current Equation - I/V Characteristics

ID increases with VGS

I D
At maximum ID, =0
VDS
Differentiating eqn. 8 and equating to ‘0’ , we get VDS = VGS – VTH

Source: “Design of CMOS Analog Integrated Circuits” by Razavi

ANALOG CIRCUIT DESIGN
MOS Current Equation - I/V Characteristics

1 W
This gives I D, max =  n C ox (VGS − VTH ) 2 ……………(9)
2 L
VGS – VTH is called ‘Overdrive voltage’
For VDS ≤ VGS – VTH the device operates in the ‘triode’ or ‘linear’ region

Source: “Design of CMOS Analog Integrated Circuits” by Razavi

 ANALOG CIRCUIT DESIGN
MOS Current Equation - I/V Characteristics

Eqn. 8 can be rewritten as

1 W
ID = μ n C ox VDS [2(VGS − VTH ) − VDS ] .............(10)
2 L

If VDS << 2(VGS – VTH), then

W .....................(11)
I D = μ n C ox (VGS − VTH )VDS
L
ID is a linear function of VDS, for small values of VDS
The portion of the characteristics near the origin depicts this
linear relationship
ANALOG CIRCUIT DESIGN
MOS Current Equation - I/V Characteristics

This region is the ‘Deep triode region’

MOSFET is equivalent to a resistor with resistance
1 ..................(12)
R on =
W
 n C ox (VGS − VTH )
L

Source: “Design of CMOS Analog Integrated Circuits” by Razavi

ANALOG CIRCUIT DESIGN
I/V Characteristics – Channel pinch-off

What happens when VDS > (VGS-VTH)?

ID does not follow the parabolic path. It becomes a constant

Drain characteristics
of NMOS

MOSFET operates in the saturation region

Source: “Design of CMOS Analog Integrated Circuits” by Razavi

ANALOG CIRCUIT DESIGN
I/V Characteristics – Channel pinch-off

What causes saturation of ID?

We know that the inversion charge density at point ‘x’ is given by
Qd = WCox (VGS - V(x) – VTH)......from eqn.(3)
V(x) is the effect of VDS at point ‘x’
If V(x) = VGS – VTH, then Qd = 0 inversion layer disappears

Source: “Design of CMOS Analog Integrated Circuits” by Razavi

 ANALOG CIRCUIT DESIGN
I/V Characteristics – Channel pinch-off

Source: “Design of CMOS Analog Integrated Circuits” by Razavi

ANALOG CIRCUIT DESIGN
I/V Characteristics – Channel pinch-off

Channel is ‘pinched-off’
If VDS > VGS – VTH, then inversion layer stops at x < L since
VGS – VDS < VTH . Thus the pinch-off moves towards the source
“No channel is formed if the net positive potential at a point
‘x’ is less than VTH”
Electrons are swept towards the drain terminal from the
channel, as they pass through the pinch-off point, due to large
VDS. Hence current continues to flow
ANALOG CIRCUIT DESIGN
I/V Characteristics – Channel pinch-off

Current equation in saturation

Consider eqn. (6)
ID = WCox(VGS – V(x) – VTH )μ dv/dx ……………..…(6)
As ‘x’ varies from 0 to L’, V(x) varies from 0 to VGS – VTH
where L’ is the point at which Qd drops to zero
Integrating this equation
L' VGS − VTH

I  WC
............(13)
D dx = ox μ n (VGS − V(x) − VTH )dV
0 0
ANALOG CIRCUIT DESIGN
I/V Characteristics – Channel pinch-off

Current equation in saturation

L' VGS − VTH

I
0
D dx =  WC
0
ox μ n (VGS − V(x) − VTH )dV ............(13)

1 W
I D =  n C ox (VGS − VTH ) 2 ..............................(14)
2 L'
Eqn. (14) is identical to ID,max eqn. (9)

ID is independent of VDS when VDS≥ (VGS-VTH)

In saturation region, ID is a constant

 ANALOG CIRCUIT DESIGN
I/V Characteristics

Summary:
4 regions of operation of MOSFET
Sl. No. Region Condition Current eqn.
1. Cut-off VGS < VTH ID = 0
2. Deep-triode VGS > VTH; W
I D = μ n C ox (VGS − VTH )VDS
VDS << 2(VGS-VTH) L
2
3. Triode / Linear VGS > VTH; W V
I D = μ n C ox [(VGS − VTH )VDS − DS ]
VDS < (VGS-VTH) L 2
4. Saturation VGS > VTH; 1 W
VDS ≥ (VGS-VTH) ID =  n C ox (VGS − VTH ) 2
2 L'
 ANALOG CIRCUIT DESIGN
I/V Characteristics

A saturated MOSFET behaves like a current source between its

source and drain terminals

Transconductance gm:
A figure of merit that indicates how well a MOSFET converts its
gate-source voltage into current in the saturation region
I D
gm = |VDS,const
VGS
 ANALOG CIRCUIT DESIGN
Transconductance

Differentiating eqn. (14) w.r.t VGS

W ........................(15)
g m =  n C ox (VGS − VTH )
L
W
Alternate equations: g m = 2 n C ox I D .....................(16)
L

2I D
gm = ....................(17)
VGS − VTH

Source: “Design of CMOS Analog Integrated Circuits” by Razavi

 ANALOG CIRCUIT DESIGN
Transconductance – Triode region

Consider the arrangement shown below:

Since gm decreases in the

triode region, MOSFET is
operated as an amplifier
only in saturation region
To plot gm vs VDS
a. For VDS > (Vb – VTH), M1 is in saturation. Hence gm is constant
b. For VDS < (Vb – VTH), M1 is in triode region.

2
W VDS
gm = {μ n C ox [(VGS − VTH )VDS − ]}
VGS L 2
W
g m =  n C ox VDS gm varies linearly with VDS
L
 ANALOG CIRCUIT DESIGN
Channel-length Modulation – 2nd Order effect

We know that transistor enters saturation region once pinch-off occurs

The effective channel length is L’.

As VDS increases, the pinch-off point moves towards the source.
In other words, L’ decreases as VDS increases.
This effect is called ‘Channel-length Modulation’

Source: “Design of CMOS Analog Integrated Circuits” by Behzad Razavi

 ANALOG CIRCUIT DESIGN
Channel-length Modulation
1 1
L’= L – ΔL. Hence =
L' L − L
Rationalising and assuming L2 >> (ΔL)2 , we get
1 L + L
=
L' L2
L
1+
1 L
=
L' L

Assuming a 1st order relationship between ΔL/L and VDS such as

ΔL/L =λVDS,.........................................(18)
1 W
we can rewrite eqn. (14) which is I D =  n C ox (VGS − VTH ) 2 as
2 L'
ANALOG CIRCUIT DESIGN
Channel-length Modulation

1 W
I D =  n C ox (VGS − VTH ) 2 (1 + VDS ) ...............(19)
2 L
where λ is the channel-length modulation co-efficient

Eqn. (19) suggests that ID depends on VDS. As VDS increases, ID increases.

ID/VDS characteristics has a non-zero slope in the saturation region

Source: “Design of CMOS Analog Integrated Circuits” by Razavi

ANALOG CIRCUIT DESIGN
Channel-length Modulation

Inference:
Since ID is no longer constant, MOSFET behaves as a non-
ideal current source in saturation.
This effect is pronounced when λ is large or L is small
In other words, channel-length modulation effect is
predominantly seen in short-channel devices
Long-channel devices – negligible slope – v.high impedance
– ideal current source
Short -channel devices – finite slope – lesser impedance
- non-ideal current source
 ANALOG CIRCUIT DESIGN
Channel-length Modulation

Transconductance gm:
Differentiating eqn. (19) w.r.t VGS
W
g m =  n C ox (VGS − VTH )(1 + VDS ) .....................(20)
L
Alternate equation:
W ....................(21)
g m = 2 n C ox I D (1 + VDS )
L

Eqns. (20) and (21) are modified forms of eqns. (15) and (16)
Eqn. (17) remains unchanged
2I D
gm =
VGS − VTH
 ANALOG CIRCUIT DESIGN
Channel-length Modulation

Ex: Keeping all parameters constant, plot ID/VDS characteristics of

MOSFET for L=L1 and L=2L1
Soln: The drain current equation, in the saturation region as
given by eqn. (19)
1 W
ID =  n C ox (VGS − VTH ) 2 (1 + VDS )
2 L
The slope of the drain characteristics I D  
VDS L

But λ α 1/L . Hence the slope of the drain characteristics

I D 1
 2
VDS L
 ANALOG CIRCUIT DESIGN
Channel-length Modulation

This implies, when L doubles, the slope gets divided by 4

Inference: A large L gives a more ideal current source but degrades

the current capability of the device.
To increase ID, W can be increased. But this increases the slope
Thus for a given overdrive voltage and a required ID, an increase in L
and W will increase the slope and make it a non-ideal current source
Source: “Design of CMOS Analog Integrated Circuits” by Razavi
 ANALOG CIRCUIT DESIGN
Body effect – 2nd order effect

Normally, Bulk and Source are tied together.

What happens if Bulk and Source are not at the same potential?
Assume VB is negative and VG < VTH.

Width of depletion region formed beneath the gate is wider since

more holes are attracted towards the substrate.
Qdep is more VTH increases
Diagrams courtesy “Design of CMOS Analog Integrated Circuits” by Razavi
 ANALOG CIRCUIT DESIGN
Body effect – 2nd order effect

Large depletion region implies, higher VG is required to pull out electrons from
the source VTH increases
Q dep
Thus as VB drops, Qdep increases and hence VTH increases As VTH =  MS + 2 F +
C ox
This phenomenon is called “Body effect” or “back-gate effect”
With body effect
VTH = VTH0 + γ( 2φF + VSB − |2φF |) ...............(1)
where VTH0 is the threshold voltage when source-bulk potential difference VSB = 0
 is the body effect co-efficient
2q si N sub
= ...........(2)
C ox
 ANALOG CIRCUIT DESIGN
Body effect

 lies in the range of 0.3 - 0.4 V1/2

Bulk potential influences VTH and hence ID
Bulk behaves as a 2nd gate
The dependence of ID on VBS is expressed by gmb
I D
g mb = VBS .......................................(3)
In saturation, gmb is expressed as
W VTH
g mb =  n C ox (VGS − VTH )(− ) ................(4)
L VBS

VTH V
= − TH
VBS VSB
 ANALOG CIRCUIT DESIGN
Body effect

Differentiating eqn. (1),

VTH  ....................................(5)
=−
VBS 2 2 F + VSB
Substituting in eqn. (4)
W 
g mb =  n C ox (VGS − VTH )
L 2 2 F + VSB
This is written as gmb = ηgm .......................................(6)
g mb 
where  = = ..............................(7)
gm 2 2 F + VSB
η = 0.25
Source: “Design of CMOS Analog Integrated Circuits” by Razavi
 ANALOG CIRCUIT DESIGN
MOS Device Capacitances

Capacitance exists between every 2 of the 4 terminals of a MOSFET.

Capacitance between S and D is negligible.

The value of the capacitance depends on the bias conditions of the
transistor.
Source “Design of CMOS Analog Integrated Circuits” by Razavi
 ANALOG CIRCUIT DESIGN
MOS Device Capacitances

Considering the physical structure of the MOSFET, the following

capacitances can be identified

i. C1 – Oxide capacitance between the gate and channel = WLCox

ii. C2 – Depletion capacitance between the channel and the

substrate = WL (𝑞ε𝑠𝑖𝑁𝑠𝑢𝑏/4ϕ𝐹
 ANALOG CIRCUIT DESIGN
MOS Device Capacitances

iii. C3 & C4 - Capacitance due to the overlap of the gate poly

with the source and the drain areas. The overlap of the
gate capacitance/unit width is denoted by Cov
iv. C5 & C6 - Junction capacitance between the source/drain
areas and the substrate.
Junction capacitance is decomposed into 2 types -
Cj – Bottom plate capacitance associated with the bottom of
the junction.
Cjsw – Sidewall capacitance due to the perimeter of the
junction
 ANALOG CIRCUIT DESIGN
MOS Device Capacitances

The capacitances between the terminals of a MOSFET in different

regions of operation are:
1) Cut – off region: There is only overlap capacitance between G and
D/S since no channel is formed in this region of operation.
Hence CGD and CGS = COVW.
CGB is the series combination of Gate-oxide capacitance and
WLCox Cd
depletion capacitance = .
WLCox + Cd
The values of CSB and CDB are a function of the source and drain
voltages w.r.t the substrate.
 ANALOG VLSI / ANALOG IC
MOS Device Capacitances

2) Triode and Deep – triode regions: If S and D have approximately equal

voltages, then the gate-channel capacitance, WLCox, is divided equally
between the gate and source terminals and the gate and drain
terminals.
This capacitance adds-on to the overlap capacitance which is
present in all regions of operation.
Hence CGD = CGS = (WLCox)/2 + COVW
 ANALOG CIRCUIT DESIGN
MOS Device Capacitances

3) Saturation region: Due to pinch – off, CGD is only equal to the

overlap capacitance = WCov.
The channel becomes non-uniform in the saturation region since
the potential difference between the gate and the channel varies
from VGS at the source end to Vth at the pinch – off point.
The capacitance of such a structure is found to be (2/3)WLCox
This capacitance adds-on to the overlap capacitance and forms CGS
Thus CGS = (2/3)WLCox + WCov
ANALOG CIRCUIT DESIGN
MOS Device Capacitances

The behavior of CGD and CGS in different regions of operation is

plotted below

The gate-bulk capacitance is usually neglected in the triode and

saturation regions because the inversion layer acts as a “shield”
between the gate and the bulk.

Source “Design of CMOS Analog Integrated Circuits” by Razavi

 ANALOG CIRCUIT DESIGN
MOS Small-Signal model

Small-signal model of a MOSFET is its equivalent circuit, used in an

amplifier when the amplitude of the applied ac input is small when
compared to the dc bias voltage.

MOSFETs are biased in saturation for most analog circuits.

Hence the small-signal model is derived for this region of operation
 ANALOG CIRCUIT DESIGN
MOS Small-Signal model

Basic small-signal model:

In saturation, ID depends on VGS. Hence a small increment in VGS
causes an increment in ID.
ΔID = gm ΔVGS
iD = gmvGS where ΔID = iD and ΔVGS= vGS
This is represented as a voltage-dependent current source
between the S and D terminals

Source:“Design of CMOS Analog Integrated Circuits” by Razavi

 ANALOG CIRCUIT DESIGN
MOS Small-Signal model

Small-signal model for short-channel devices:

Owing to channel-length modulation effect, in saturation, ID not
only depends on VGS but also on VDS.
The linear dependence of ID on VDS is represented by a resistor, ro
between the S and D terminals
VDS 1
r0 = =
I D I D / VDS
1
Differentiating eqn.(19) r0 =
1 C W
2 n ox
(VGS − VTH ) 2 
L
 ANALOG CIRCUIT DESIGN
MOS Small-Signal model

Small-signal model for short-channel devices:

1
r0 =
1 C W
2 n ox
(VGS − VTH ) 2 
L
1 + VDS
r0 =
I D
1
Assuming λVDS<<1 r0 = ......................... (20)
I D
r0 is the output resistance of the MOSFET

Source: “Design of CMOS Analog Integrated Circuits” by Razavi

 ANALOG CIRCUIT DESIGN
Body effect – Small-signal equivalent circuit

Body effect exists in devices where the substrate and the source are not shorted.
This leads to an increase in VTH.
This phenomenon is called “Body effect”
With body effect VTH = VTH0 + γ( 2φF + VSB − |2φF |)
where VTH0 is the threshold voltage when source-bulk potential difference VSB = 0
 is the body effect co-efficient
Owing to Body effect, in saturation, ID not only depends on VGS, but also on VBS
 ANALOG CIRCUIT DESIGN
Body effect – Small-signal equivalent circuit

Modeling the dependence of ID on VBS by a current source, the small-

signal equivalent of a MOSFET in saturation, for a short- channel
transistor is shown

Note: gmbVBS has the same direction as gmVGS since raising the gate
voltage has the same effect as raising the bulk voltage
The product gm.ro is referred to as the Intrinsic gain of the device.
Source:“Design of CMOS Analog Integrated Circuits” by Razavi
General Considerations

• The general aspects of amplifiers are

i. Power dissipation
ii. Speed
iii. Noise
Input and Output impedances

One more important aspect along with the existing three is input and output
impedance

Input Output

Characteristics of Ideal Amplifier

1. At the input the circuit must operate as voltmeter therefore Input impedance
of an amplifier is infinity
2. At the output circuit must operate as voltage source hence Output impedance
should be zero
EXAMPLE 1
An Amplifier with a gain of 10 and is modeled as in figure a
Determine the signal level sensed by amplifier if circuit has a input
impedance of 2Kohm or 500 ohm
Determine the signal level delivered to speaker if it has an output impedance
of 10ohm or 2ohm
Solution

By using Voltage divider rule

𝑅𝑖𝑛
𝑉1 = 𝑉 =0.91 𝑉𝑚 for Rin=2KΩ [ 9% less]
𝑅𝑖𝑛 +𝑅𝑚 𝑚

𝑅𝑖𝑛
𝑉1 = 𝑉 =0.71 𝑉𝑚 for Rin=500Ω [30% less]
𝑅𝑖𝑛 +𝑅𝑚 𝑚
Thus input impedance should be “HIGH”

𝑅𝐿
𝑉𝑂𝑈𝑇 = 𝑉 =0.44 𝑉𝑎𝑚𝑝 for 𝑅𝑎𝑚𝑝 =10 Ω
𝑅𝐿 +𝑅𝑎𝑚𝑝 𝑎𝑚𝑝

𝑅𝐿
𝑉𝑂𝑈𝑇 = 𝑉 =0.8 𝑉𝑎𝑚𝑝 for 𝑅𝑎𝑚𝑝 =2 Ω
𝑅𝐿 +𝑅𝑎𝑚𝑝 𝑎𝑚𝑝
Thus output impedance should be “LOW”
Procedure to find the I / O impedance
Assuming that the transistor operates in the saturation region,
determine the input impedance of the circuit shown in Fig.
Calculate the impedance seen looking into the drain of M1 in Fig.

Setting the input voltage to zero and using the small-signal model in Fig., we note
that v1 = 0, gmv1 = 0, and hence Rout = rO.
DC and Small-Signal Analysis
• First, we compute the operating (quiescent) conditions (terminal voltages and currents) of
each transistor in the absence of signals. Called the “dc analysis” or “bias analysis,” this step
determines both the region of operation (saturation or triode) and the small-signal
parameters of each device.
• Second, we perform “small-signal analysis,” i.e., study the response of the circuit to small
signals (superimposed on bias levels) and compute quantities such as the voltage gain and
I/O impedances.
In drawing circuit diagrams hereafter, we will employ some simplified
notations and symbols.
Illustrated in Fig. is an example where the battery serving as the supply
voltage is replaced with a horizontal bar labeled VDD.5 Also, the input
voltage source is simplified to one node called vin, with the understanding
that the other node is ground.
A student familiar with MOS devices constructs the circuit shown in Fig.
and attempts to amplify the signal produced by a microphone. The
microphone generates an output signal having a peak value of 20 mV with a
zero dc (average) level.
Explain what has happened.
Unfortunately, the student has forgotten to bias the transistor.
Since the microphone does not produce a dc output, a peak
input of 20 mV fails to turn the transistor on.
Consequently, the transistor carries no drain current and hence
its transconductance is zero.
The circuit thus generates no output signal.
Having realized the bias problem, the student modifies the circuit as
shown in Fig., connecting the gate to VDD to allow dc biasing for the gate.
Explain why the student needs to learn more about biasing.

The fundamental issue here is that the signal generated by the

microphone is shorted to VDD.
Acting as an ideal voltage source,VDD maintains the gate
voltage at a constant value, prohibiting any change introduced
by the microphone.
Since VGS remains constant, so does Vout, leading to no
amplification.
Unfortunately, this arrangement necessitates one battery for each amplifier stage.
(Different stages may operate with different gate-source voltages.) We must therefore
seek a simple replacement for the battery
SIMPLE BIASING

Now consider the topology shown in Fig. (a), where the gate is tied to VDD through
a relatively large resistor, RG, so as to provide the gate bias voltage. With zero
current flowing through RG, the above circuit yields VGS = VDD, a relatively large
and fixed value.
RESISTOR DIVIDER BIASING Most amplifier designs, on the other
hand, require flexibility in the choice
of VGS

Our objective is to analyze this circuit and determine its bias current
and voltages.
We begin by assumingM1 operates in the saturation region and
neglect channel-length modulation in bias calculations.

Thus, proper choice of the resistor divider ratio and W/L can establish the required bias current.
RESISTOR DIVIDER BIASING
Noting that RD carries a current equal to ID and hence
sustains
a voltage of RDID, we write a KVL around the supply
voltage and the output branch:
VDS = VDD − RDID
For operation in saturation, the drain voltage must be no
more than one threshold below the gate voltage,
VDS ≥ VGS − VTH:
Biasing with Source Degeneration
In some applications, a resistor may be placed in series with the source of the transistor, thereby
providing “source degeneration.” As Illustrated in Fig., where the gate voltage is defined by R1 and
R2. We assumeM1 operates in saturation and neglect channel-length modulation. Noting that the
gate current is zero, we have
Biasing with Source Degeneration
Self Biased stage
MOSFET CHARACTERISTICS – Different Regions of Operation
Determine ‘Region of Operation’ for the following?
Let VTH = 0.4 V
Q.1

➢ VGS = 0.
➢ Therefore the device is OFF.

Q.2
➢ VGS = 1V, VGS > VTH
➢ The Device is ON.
➢ VDS > VGS – VTH => 1.5 V > 0.6 V
➢ The device is in Saturation
MOSFET CHARACTERISTICS – Different Regions of Operation
How to Determine ‘Region of Operation’ for the following?
Let VTH = 0.4 V
Q.3

➢ VGS = VG – VS = 0 V– (-0.5)V = 0.5V

➢ VGS > VTH , M1 is ON.
➢ VGS – VTH = 0.1V
➢ VDS = 0 V - (-0.5) V = 0.5V
➢ Therefore the device is in SATURATION.
MOSFET CHARACTERISTICS – Different Regions of Operation
How to Determine ‘Region of Operation’ for the following?
Let VTH = 0.4 V
Channel-Length Modulation
Q. A MOSFET carries a drain current of 1 mA with VDS = 0.5 V
in saturation. Determine the change in ID if VDS rises to 1V
and λ = 0.1V−1.What is the device output impedance?
We write

And hence
MOSFET CHARACTERISTICS – Drain Current
Q2. The drain of an n – channel MOSFET is shorted to the gate so
that 𝑉𝐺𝑆 = 𝑉𝐷𝑆. The threshold voltage (VT) of MOSFET is 1 V. If the
drain current (ID) is 1 mA for VGS = 2 V, then for 𝑉𝐺𝑆 = 3 𝑉,
determine the drain current ID?
➢ Given, 𝑽𝑮𝑺 = 𝑽𝑫𝑺
➢ Then the device is in saturation.
➢ So, 𝑰𝑫 = 𝑲 (𝑽𝑮𝑺 − 𝑽𝑻 ) 𝟐 , Where K =
➢ For 𝑰𝑫 = 𝟏 𝒎𝑨 , 𝑽𝑮𝑺 = 𝟐𝑽 , 𝑽𝑻 = 𝟏𝑽
➢ 𝟏 = 𝑲 (𝟐 − 𝟏) 𝟐 𝒐𝒓, 𝑲 = 𝟏 𝒎𝑨 /𝑽 𝟐
➢ Again, 𝑰𝑫 = 𝑲 (𝑽𝑮𝑺 − 𝑽𝑻 ) 𝟐
➢ For 𝑽𝑮𝑺 = 𝟑 𝑽
➢ 𝑰𝑫 = 𝟏 × (𝟑 − 𝟏) 𝟐
➢ 𝑰𝑫 = 𝟒 𝒎A
MOSFET CHARACTERISTICS – Drain Current
Q3. Calculate the total charge stored in the channel of an NMOS device if
Cox = 10 fF/μm2, W = 5 μm, L = 0.1 μm, and VGS − VTH = 1 V. Assume VDS = 0.
MOSFET CHARACTERISTICS
Q4. An NMOS device carries
1 mA with VGS − VTH = 0.6 V
and 1.6 mA with
VGS − VTH = 0.8 V. If the
device operates in the
triode region, calculate VDS
and W/L.

In the following problem, unless

otherwise stated, assume μnCox = 200
μA / V2, μpCox = 100 μA / V2, and
VTH = 0.4 V for NMOS devices and
−0.4 V for PMOS devices.
MOSFET CHARACTERISTICS – Drain Current
An NMOS device operating in saturation
Q5. with λ = 0 must provide a transconductance
of 1/(50 ).
(a) Determine W/L if ID = 0.5 mA.
(b) Determine W/L if VGS − VTH = 0.5V.
(c) Determine ID if VGS − VTH = 0.5V.
MOSFET CHARACTERISTICS – Drain Current
Q5.
MOSFET CHARACTERISTICS – Drain Current
An NMOS device operating in saturation
Q5. with λ = 0 must provide a transconductance
of 1/(50 ).
(a) Determine W/L if ID = 0.5 mA.
(b) Determine W/L if VGS − VTH = 0.5V.
(c) Determine ID if VGS − VTH = 0.5V.
MOSFET CHARACTERISTICS – Drain Current
Q5.

An NMOS device operating in saturation

with λ = 0 must provide a transconductance
of 1/(50 ).
(a) Determine W/L if ID = 0.5 mA.
(b) Determine W/L if VGS − VTH = 0.5V.
(c) Determine ID if VGS − VTH = 0.5V.
THANK YOU

Department of Electronics and Communication

Engineering