Module 2

CHAPTER
Bipolar Junction Transistor
2
University Prescribed Syllabus
Structure and 1-V characteristics of a BJT; BJT as a switch. BJT as an amplifier.
DC Circut Analysis Types of biasing circuits, load line (Numerical); themal runaway, stability factor
analysis, thermal stabilization.
AC Circuit Analysis : Small signal anailysis of CE configurations with different biasing network using
hybrid-pi model.
Amplification derivation of expression for voltage gain, current gain, input impedance and output
impedance of CC, CE amplifiers (Numerical); Study of frequency response of BJT amplifier.

2.1 INTRODUCTION. . . . . . . ......... ...ono. *********** n************************************.2-5

2.1.1 Constructional Details of Transistors.. **.*..***********************************************'********"***************************** 2-5
2.1.2 Basic Comparison between n-p-n and p-n-p BJT 2-6
2.2 DIFFERENT REGIONS OF OPERATION OF BJT. . -. . ... .2-7
************************************""****************

What are different regions of operations of BJT ? 2-7

GQ. ....... .. **.*.**.******s*******************"*******
2.3 DIFFERENT CONFIGURATIONS OF TRANSISTOR... . . . 2-7
2.4 COMPARISON OF DIFFERENT CONFIGURATIONS OF TRANSISTOR.
Compare different configurations of transistor..
2-8
GQ.
2.5 OPERATION OF NPN TRANSISTOR (CB). .2-8

GO. Explain operation of NPN transistor. *** **************"

***'******** "**************""'***
*****. 210

2.6 OPERATION OF PNP TRANSISTOR (CB) .********************************************** *****************************************

2-11
2-11
GQ. Explain operation of PNP transistor. .... .. *******************************.**.***. ****************"******"***
2.6.1 Current Relations for Common Base (CB) Configuration (npn Transistor)... ***.*******.*************************** 2-12

GQ. Why collector is largest in size? (as shown in Fig. 2.6.3)..

Why base is very thin and lightly doped ? . ****** ******************. .2-12
GQ. ******************** ********

Why emitter is heavily doped ? . 2-13

GQ.
EARLY EFFECT OR BASE WIDTH
MODULATION 2-13
2.7
. .

What is early effect ? Explain how it affects the BJT characteristics in CB configuration. 2-13
GQ.
COMMON EMITTER cONFIGURATION. ********** **************.
*************""****** 2-13
2.8
Common Emitter (CE) configuration is frequently used ? 2-13
GQ. Why ******************"****************************""******"*****
.

GQ. Explain operation of Common Emitter (CE) configuration of BUT.... .2-13

2.9
CURRENT RELATIONS IN COMMON EMITTER (CE) CONFIGURATION.. 2-15

OF COMMON EMITTER (CE) CONFIGURATION..

INPUT AND OUTPUT CHARACTERISTICS
2-15

2.10 .*************
Explain graphical method to obtain parameters of CE configuratio.. *.. .*o************************* 2-15
Ga.
Draw Input and output characteristics of BuT in common emitter configuration.. 2-15
GO.
1 . * * * * * * * * * * * * * * * * * * * * * * . * * * * * * * * * * * * * * * * * * * .

UQ. Explain the

input and output characteristics of CE BJT amplifier. (MU-O.20), May 18, 10 Marks). 215
2-16
2.10.1 Input Characteristics... *********************************************** e . * *****************************

2.10.2 Output characteristic of Common Emitter (CE) Amplifier. ******************a*******.* ****************************

2-16
2-17
2.11 CE CONFIGURATION AS VOLTAGE AMPLIFIEA. ***********************.** . . ********************

....2-17
How CE configuration be used as voltage amplifier ? Why transistor is known as transistor ? ***********"
Ga.
 Analog Eloctronics (MU-Sem.3-Electrical) 2-2
Bipolar Junction Transistor
2.12 COMMON BASE CONFIGURATION
Ga. Draw circuit diagram of common Baso 2-18
(CB) amplitier. Writo function of component used. ...
2.13 CHARACTERISTICS OF COMMON BASE (CB) 2-18
GQ. Draw input and output charactoristics of CONFIGURATION.. ***ssse*gs*.*****s*********enn* 2-19
common Base (CB)
can obtain from these amplifier. What are the parameters we
GQ.
characteristics 7 ****************s**sn**ntsnasas*
.
What are the drawbacks, it BJT is .* **.*.se*sas***nn.*.*******.** . . ..2-19
used in common Base (CB)
Base (CB) be used
efficiently ?. configuration ? where can common
GQ. With numerical values, ******************************tnses.*********.********s*nnsssne**sssessss*************s************************
explain how a transistor can be
C20
Common Base (CB) configuration ?...*********sesssers**tsssaroused as voltage amplifier when connected in
2.14 CONCEPT OF LOADING EFFECT AND **.***ssee***sss**************t.trs************************..2-20C°L0
COMMON COLLECTOR CONFIGURATION OF BJT
2.15 COMMON COLLECTOR . .2-21
.****************.*****..

GQ.
AMPLIFIER/
UNITY GAIN AMPLIFIER/BUFFER AMPLIFIER 2-22
Why do we prefer CE configuration as an amplifler ?.
GQ. Why we don't 2-24
prefer
CB to be used as an
amplirier
2.16 LOAD LINE *********"*'****'''******************'***********************"*******'********2-24

GQ. Write short note on DC load line and 2-25

GQ. Write short note on : DC load line significance of Q-point. . .
line and fixed?...
concept in BJT. Why Q point should be at the middle of DC load
GQ. Write short note on DC load line. What is a
Ua. Explain DC load line in common emitter point ? Where it should be located on DC load line ?.. 2-25
BJT. (MU -Q. 1(b),
2.16.1 DC Load Line and
Q-point of Amplifier..******
May 18, 5 Marks) ********************************
..2-25
****************************"*******"****************** *
2.16.2 Selection of Q-point *******.. 2-25
GO.
(VcEQ
What is DC bias line ? Or What is
ca) ****************"***********************"****"***
******* .*.*.
... ... . E°L0
input DC load line ? Write steps to draw it for a simple CE
working as voltage amplifie.. configuration
2.17 SELECTION OF Q-POINT ON DC LOAD LINE .2-26
GQ. Where should we locate
(GRAPHICAL APPROACH). .2-27
Q-point on DCLL ? Why ? Explain graphically.
2.17.1 Q Point Near
Saturation.. . * ***********'********* .2-27
2.17.2 Q-point Near Cut-off *******************"************** ***** **** ****"*** ***"**
2-27
. ********.****.
2.17.3 Q-Point in the Centre of DC Load .2-28
Line (DCLL) Active
Region...
-

2.18 BIAS
UQ.
STABILIZATION.. ****"**********""***************"******"******"***""****"*****
**** .. 2-28

Explain thermal runaway and stabilization. (MU -O. 1(a), Dec. 13, 5 Marks, May 19,10
.2-29 *****"*****"****************

UQ. What is Thermal stabilization ?(MU -O.1(b), May Marks). .2-29

UQ. Explain thermal stabilization and compensation. (MU 14, . 1(c), Dec. 14, 5 Marks). 2-29
Ua. Explain the different thermal compensation techniques-Q. 6, May 15, Q. 1(c), Dec 15, 5 Marks.
in BJT ..2-29
UQ. Write short note on: Thermal runaway in BJT. amplifiers.(MU -Q. 4(a), May 16. 8
1(a), Dec. 14, Q. 6(a), Dec. 18, 5 Marks).Marks)..
2-29
GQ. Draw circuit diagram of a conventional (MU-Q.
common emitter (CE)
amplifier with wavefoms 2-29
Explain function of components used in circuit..... at different nodes.
2.19 STABILITY FACTOR. .2-31
GQ. Define stability factor. Derive the 2-32
equation for stability factor. State which biasing technique
Justify your
answer. . * **
is more stable.
GQ. What is stability factor ? Why it is defined ? . ******"******************************"*************************************** ******.2-32
.

GQ. Define different stability 2-32

2.19.1
factors...
Steps to Find Stability Factor of any Biasing Circuit.. ********'** ***"****** *****
**
.
232
2.19.2 Biasing of Amplifiers.
********** ** **** ********************************************"***********
************
***. 232
GQ. What is biasing ? Why do we need .2-32
biasing in BJT
need of biasing in BJT. (MU Q,1(c),Mayamplifiers
? or What are functions of
GQ. Explain 14, a.
biasing circuit ?. 2-32
2.20 DIFFERENT BIASING METHODS. 1(d), Dec. 14, 5 Marks)... *****""**""*** 2-32
********************************""** '**
Ga. Write a short note stability factors of various biasing techniques****
on ***"*"**************"******"*********** 2-33
of BJT..
UQ. Explain Different biasing techniques in BJT. (MU * "**** ******************** 2-33

2.20.1 Fixed Bias... a. 2(b), May 18,10 Marks) ammes******" 2-33

GQ. Draw circuit diagram of CE amplifier with Fxed Blas. Find . . 2-33
Q point. Draw DCBL
Finally find stability factors. and DCLL
GQ. What are important disadvantages of fixed bias ?.. 2-33

***********"****"
2.20.2 Fixed bias with Self **
Bias or Emitter Feedback Bias.. ** '**** *************""***"2-34
********.
2-35
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GQ. Write advantages of fixed bias with emitter bias or self bias. **********************************
2 - 3 7

What is the function of Bypass capacitor CE in CE amplifier .? (MU Q.1(d), Dec. 13, 4 Marks
** *****************
UQ. 2-38
2.20.3 Collector to Base Bias..****************************.******.*. ... . . * ***********************************. ***
2-38

GQ. Draw circuit diagram of CE

amplifier with Collector to Base (C-B) bias. Find Q-point.
Draw its DCBL and DCLL. .2-38
. **************************. .***************************************************
GQ Write advantages and disadvantages or limitations of
collector to base bias. * * *
40
* * * * * * * * n o * * * i * . * * * * * * * * . * * * * * * * * * e * * .

GQ. How do we avoid AC

negative feedback in collector to base bias to increase AC gain?.. *************************.
2-41

2.20.4 Collector to Base Bias with Self Bias or Emitter ..2-41

GQ. Bias.. .****************
* * * . * * *

Draw circuit diagram of C to B bias with self bias. Find its Q point. Derive equation for stability tactor S.
Draw DCBL and
DCLL. ************

2.20.5 Potential Divider Biasing with Emitter Bias..

"***** ******* . .s. . . .* * ** **********"********
..2-41 Module
..2-43
2.21 DIFFERENT BlASING METHODS AT A GLANCE
(COMPARIsON).. .2-45 2
UQ. Compare different biasing method of BJT.
2.21.1 Important Theory Questions on
(MU-0.2(b), Dec. 19,5 Marks). 2 - 4 5

Biasing.. -46
GQ. Which biasing is the best biasing ? Justify your answer. OR why do we use PD bias normally ? OR
what are the advantages of PD bias ?.. 2-46
GQ. What are advantages of fixed bias ?
Why it is rarely used ?.. .2-47
GQ Why collector to base bias is rarely used ?..******* ********"** **** ********************************** 2-47
GQ. Why self bias with RE is not used ?..
***************°******************************"**""******""*****************************°°** °****** 2-47

2.22 KEY FORMULAE TO SOLVE PROBLEMS (PD BIAS

UNIPOLAR).. 2-477

2.23 EXAMPLES ON BIASING (CE CONFIGURATION)... ***** .

2483
UEx. 2.23.6(MU-0. 2(b), Dec. 19,5 Marks). 2-54
2.24 EXAMPLE ON DESIGN OF BIASING CIRCUITS... 2-57
2.25 EXAMPLES ON BIASING OF COMMON BASE (CB) CONFIGURATION .2-65
.
2.26 BJT MODEL OR SMALL SIGNAL EQUIVALENT
CIRCUIT.. **** ************* .2-67
Ga. What is model or small signal equivalent circuit
?.. ****

2.26.1 Definition of Modeling.*************************""******** ** *** .. 2-688

2.27 HYBRID PARAMETERS (h-PARAMETER). ****.... .. 2-68
*********** ***********
GQ. Write a short note on : Hybrid parameters... .. . .. .. annonanon. Co0
8
UQ. Write a short note on: h-parameter model. (MU-0.6, May 14, 0.6(a), May 19,5Marks) 2-68

GQ. Can we use h-parameters for different configurations (CE, CB and CC) of transistor ?. ************
2-69
2.28 EXACT HYBRID MODELS FOR BJT.. ************* 2-69
-b

GQ. Draw h-parameter model for C, Cg and C transistor configurations.. ** .. 2-69

UQ. Write a short note on: h-parameter model. (MU - 0.6, May 14, 5 Marks). *************
.. 2-69
2.28.1 Hybrid Model for CB... 2-69
2.28.2 Hybrid Model for CE. **********sisnsssnnu***********s********nsnn.. . . . . ....2-70O
70
Ga. Draw small signal hybrid parameter equivalentcircuit for CE amplifier and define the same... . . 2-70
UQ. Draw and explain the h-parameter model of BJT and derive the expression for Ay, A, R. Consider CE
configuration. (MU -Q. 5(a), Dec.18,10 Marks, O.6(a), May 19, 5 Marks).. *******************************. . 2-70
2.28.3 Hybrid Model for CC.
**********************************************************************....*oo ... .. .. . . . . . . . 22-70
2.29 HYBRID MODELS AND EQUATIONS IN TABULAR FORM..
************************************** s. 2-71
2.30 CONVERSION OF HYBRID MODEL OF CE AMPLIFIER INTO APPROXIMATE MODEL **********************************"**
**. 2-72

Ga With proper approximations explain step by step, how can you convert exact hybrid model of CE
amplifier into approximate model. 2-72
2.31 UTILITY ADVANTAGE AND DRAWBACKS OF h-PARAMETERS. 2-73
***********************e**************************s**************. CTO
GQ. Explain utility of h-parameter.... . *
Write advantages and
* .**e.**.****** .***.*******.**************.************* Ei9
utility of h-parameters. A l s o w r i t e s o m e i m p o r t a n t d r a w b a c k s o f h - p a r a m e t e r s2
. -7
2-7
3 3

GQ.
GQ. What are the advantages of h parameters? . ************************ ** "e*so******* ****** ***************** 2-73
2.32 GRAPHICAL DETERMINATION OFh-PARAMETERS..****************************************"***** ** . 2-73
GQ. Explain Graphical determination of h-parameters.. . . ** .***************************
.2-73
GQ. Determine 'h' parameters using input and output characteristics of CE transistor. * *********.***********************
2-73

2.32.1 Determination of h a . 2-73

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2.32.2 Detemination of hro . * ****"******"******""******"*************************************"*** *** - . . . .2-73
2.32.3 Determination of hie . . . .
********************************************************* *****
e......... 2-74
2.32.4 Determination of h,e * * *********************************************************** *~-. .....2-74
2.33 HYBRID T ORr -
MODEL OF BJT. ****.**************************""***********************************.*. . ..
2.33.1 Key Poinis... . 74
***************** *** ******"*********************************************. .. ..2-74
2.33.2 Step by Step Development of h-t Model ... .. . 2-75
GQ. Draw and explain small signal hybrid-Pi model of BJT including early effect.... 2-75
GQ. Draw small signal hybrid n equivalent circuit for npn transistor... *********e************o**********
2-75
GQ. Explain the Hybrid pi model of BJT.. *********** ****.************** .***************************************.*** 2-75
GQ. Draw and explain hybrid-t common emitter transistor model..
********** ****°"'******************************************** 2-75
2.33.3 h-n Model with Current Gain Parameter
* . . . . ....... ..*....o..... ..**.*.o**.********************************* C 2-77
°I[

2.33.4 Hybrid n Model for PNP Transistors. 77

2.33.5 Expanded Hybrid-t-Model. ********** 2-77 ************* *******

2.34 APPROXIMATE HYBRID- T - MODEL AT LOW FREQUENCY (LF) AND MID FREQUENCY (MF).. . . .2-77

2.35 HYBRID PARAMETERS IN TERMs OF HYBRID-T PARAMETERS (RELATION BETWEEN h AND h-T
PARAMETERS).. ... **************.***.****************************************************************** 2-78
*

2.36 KEYPOINTS FOR AC ANALYSIS... 30

GQ. Give the steps to find output impedance of any two port network... 2-80
GQ. How to draw MF AC equivalent circuit ? .*****************************'*******************************************************************
. 2-80

2.37 SAMPLE EXAMPLES ON DC AND AC ANALYSIS OF CE AMPLIFIER WITH GUIDE LINES GL)....... *o*******2-84
2.38 AC ANALYSIS USING EXACT h-MODEL... ********* *************** *************** **************.**. 2-93 4

** *****
UQ. Derive the expression for voltage gain, current gain, input impedance and output impedance of CE

amplifier. (MU -Q. 2(b), Dec. 14, Q. 3(a), Dec. 15, 10 Marks).. .. . .
Draw the hybrid equivalent model of voltage divider bias CE amplifier with RE bypassed and derive the
9
UQ.
expression for voltage gain and input impedance.
Explain the modeling of CE BJT in h-parameter and hence derive the expression for voltage gain.
(MU-Q.2b), May 16, 12 Marks). ********************
2-93

UQ.
2-93
(MU-Q.5(b), May 18, 10 Marks).. * * * * * * *

Give the complete AC analysis of CE amplifier using h parameter model....

* * * * * . * . * * * . * . * . . .
**************************************

............
********.

***. 2-93
Ga.
2-95
2.39 AC ANALYSIS OF CE AMPLIFIER USING EXACT H-MODEL.
2.40 AC ANALYSIS OF CE AMPLIFIER USING APPROXIMATE AND EXACT MODEL * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * " 2-99

2.41 COMMON COLLECTOR AMPLIFIER OR UNITY GAN AMPLIFIER OR EMITTER FOLLOWER OR IMPEDANCE
...2-101
MATCHING AMPLIFIER OR BUFFER AMPLIFIER..
Write short note on: Emitter follower...
********************************* .******.*****o***********i *****
2-101
GQ.
How can we reduce loading effect? Why buffers are required ? . . . ******************e** *** 2-102
GQ.
****************** 2-102
2.42 IMPORTANT PROPERTIES OF CC AMPLIFIER AND ITS APPLICATIOn.. **************.

****°****°*****°***********2-102
GQ. Why common collector amplifier is used as buffer ? Why buffers are required ?..
***********"*****°******°******"****°**°*******"******""******************2-102
GQ. Explain small signal common collector anplifier. 2-102
GQ. Draw a diagram of an emitter follower and describe its working and advantages.
GQ. In which applications the common collector configuration can be used ?. . . o
How can CC amplifier can be used as a buffer or impedance matching amplifier ? Explain. .. 2-104
GQ.
2-104
2.43 AC ANALYSIS OF cC AMPLIFIER OR EMITTER FOLLOWER OR BUFFER.
Derive the expression for voltage gain, current gain, input impedance, output impedance of common
UQ. ***********°*****°****°*********************************************2-104

collector amplifier.(MU-Q. 3(a), May 15,10 Marks).. 2-107

Ga. Input impedance at the base of an emitter follower is -***********************************.**************************.****

2-108
2.44 Comparison of CB, CE and CC Configuration of BJT
2 - 1 0 8

Compare CE and CC configuration.

***************.** e******a*.* **********************************"***********
GQ ****************
2 **
- *1 0 9
245 Frequency response of BJT amplifier (working of CE amplifier with itsfrequency response).
-10
Ua. Explain the working of CE amplifier with its frequency
response.
Write short note on frequency response of BJT amplifier.
(MU 0. 4d), May 19, 10Marks).
Ua. *J*****°°********.*** s * . * * * * * * * * * * * * * * * * * *.
**2**
-109

C(IMU-O.6, Dec. 15, O. 6ta). Dec.19, 10 Marks). ... 2-111

CHAPTER ENDS. ****°****°*.*********. e** ***************

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 Analog Electronics (MU-Sem.3-Electrical) 2-5 Bipolar Junction ransISO

Part (A): Construction, Working and Characteristics of BJT

2.1 INTRODUCTION Metal layer
E

BJT is a three terminal component, namely Emitter (E), Sio2 layer

Base (B) and collector (C).

n
It is three layer device; the layers are normally doped Si
5P
or Ge crystals i.e. either n-type or p-type. 3 mm
Module
If a p-layer is sandwiched between two n-layer, we get
npn transistor, while n-layer sandwiched between two
p-layer provides pnp transistor.

2.1.1 Constructional Details of (Ice) (c) Diffusion type

Transistors (1C1) Fig. 2.1.1: Different techniques
Different types of techniques used to construct Diffusion type is nowadays being used to fabricate
transistors, are (Fig. 2.1.1(a), (b) and (c).
transistors in integrated circuits.
(a) Grown type (b) Alloy type Transistors are available in different packages. Some
(c) Diffusion type low power packages are shown in Fig. 2.1.2.
The symbols for the PNP and NPN transistors are
Heavily shown in Fig. 2.1.3. Direction of arrow on Emitter
doped and 3 mm
argest in size
terminal serves to distinguish a PNP or NPN transistor.

npn
B
Lightly
doped and
very thin

Moderately- pnp Jc
doped and
moderate in size

(1C1) (a) Grown type (IC) (b) Alloy type

E B C

Low power transistor packages Symbols

(ic3) Fig. 2.1.2 Fig. 2.1.3

NOTES

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 Analog Electronics (MU-Sem.3-Electrical) 2-6 Bipolar Junction Transistor
BJT
2.1.2 Basic Comparison between n-p-n and p-n-p
pnp Transistor
npn Transistor
Construction
AC BE BC

Moderate Largest Moderate --- Largest

in size in size in size Smallest in size
Smallest
in size (very thin) in size (very thin)

BE Junction between Base and Emitter JBE Junction between Base and Emitter
JBCJunctlon between Base and Collector JBC Junction between Base and Collector
(a) (b)
Doping level
E Heavily doped
E- Heavily doped
C Moderately doped CModerately doped
B Very lightly doped B Very lightly doped

Symbol

Arow on E indicates conventional emitter current (E)|

Arow on emitterindicates conventional emitter curent
E). It is in opposite direction to that of npn BJT

(c) (d)
Two Diode Anology
BE BC BE Bc
E n Pn oc EO P c
B
E D C
JBE BE
EK D-oc EO-
KKoc

E
(e) Horizontal
(9 Horizo

A Bc V 'ec
P
B
Y BE
E E
E

1C4
8) Vertical
(h) Vertical

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 Analog Electronics (MU-Sem.3-Electrical)
2-7 Bipolar Junction Transistor
Note 1. ounderstand Biasing concept of NPN
transistor it can be represented by two diodes wnere
anodes are shorted to form the
base.
2. o
understand biasing concept of PNP transistor it can be represented by two diodes where
cathodes are shorted to form the base.
2.2 DIFFERENT REGIONS OF
OPERATION OF BJT
GQ. What are diferent regions of
operations of BJT?
-------
Depending upon forward or
Module
biasing of base emitter junction (JRE)
reverse
can be operated in four regions of operations. Please refer Table 2.2.1.
and base collector junction (Bc» a transisTO 2
Table 2.2.1: Different
regions of operations of BJT
Sr. Base Emitter Junction Base Collector Junction
No. Region of operation Normally used in
(Jsc)
Reverse Biased Reverse Biased Cut off
1.
Forward Biased BJT as switch
Forward Biased Saturation
2. Forward Biased Reverse Biased Active or Forward Active Amplifier
3. Reverse Biased Forward Biased Inverted or Reverse active Used in IC

Note : For us the important region is Input curent Output current

ACTIVE Region where BJT works as
an amplifier with base emitter junction
BE) forward biased (FB) and base Amplifier or three
terminal network (Load
collector junction (Jpc) reverse biased reslstor)

(RB). Weak input Amplified

signal Z (Input (Output Output signal
impedance) Common impedance)
2.3 DIFFERENT CONFIGURATIONS terminal
Inputport>1-1 Output port >2-2
OF TRANSISTOR
(ic9) Fig. 2.3.1: AC Equivalent Circuit
In electronic circuits BJT can be connected in three
different configurations namely common base (CB), Step 3 Now if
common emitter (CE) and common collector (CC).
(a) Base is common to input and output ports, the
To find in which configuration transistor is connected,
configuration is Common Base (CB).
following steps can be used:
(b) Emitter is common to input and output ports, the
mid frequency equivalent circuit of
Step 1: Draw ac
configuration is Common Emitter (CE).
amplifier by (c) Collector is common to input and output ports,
(a) Shorting DC voltages the configuration is Common Collector (CC).
and opening all stray
(b) Shorting all (uf) capacitors The basic circuits of CB, CE and CC are as shown in
capacitors (in pf) Figs. 2.3.2.(a), (b), (c)
Step 2: implementing Step (1) any amplifier
After
circuit (or BJT) gets converted to three terminal
teminal of
network, shown in Fig. 2.3.1, with one
transistor common to input and output ports.

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Analog Electronics (MU-Sem.3-Electrical)

Base is common to input & output to input & output

Collector is common

Common Collector
(1ca) (c)
(1C6) (a) Common Base Fig. 2.3.2

2.4 COMPARISON OF DIFFERENT

CONFIGURATIONS OF
TRANSISTOR

oftransistor.
a. Compare different configurations- -****
Emitter is common to input & output - * ****-
no. 2-6.
Please Refer Table 2.5.1 on page

(1C7) (b) Common Emitter

Fig. 2.3.2 continue..

)2.5 oPERATION OF NPN TRANSISTOR (CB)

(DR), etc. is shown.
depletion region
In Fig. 2.5.1, an unbiased transistor with all majority carriers, minority carriers,

PB e (maj car)
p (min car) e (maj car) P (min car)
e (maj car)-

Collector
Emitter C
E

Immobile positive
ion
-DR Base
DR- PBPotential Barrier
P (majcar) eElectrons
BImmobile negative P Holes
ion
DRDepletion region or
space charge region

(1c9Fig. 2.5.1: Unbiased transistor

1. Since both junctions, JpBE and Jgc are unbiased, there depletion region (DR) and potential barrier (PB).
exists

Due to presence of potential barrier (PB),

diffusion of majority carriers across the junctions is opposed and stopped.
2.
and Collector (C) regions are due to addition of donors or acceptor atoms.
3. Majority carriers in Emitter (E), Base (B)
4. Presence of minority carrier is due to thermal agitation.
of potential barrier (PB) is both
5. Since junctions are unbiased, width of depletion region (DR) and height high across

junctions
to maxe
Now for transistor to work as an amplifier, it should be operated in Active region. For this, we use DC voltages
pE forward biased and JgcTeverse biased.

Ventu
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 Bipolar Junction Transistor
Analog Electronics (MU-Sem.3-Electrical) 2-9

Table 2.5.1

Parameters Common Base Common Emitter Common Collector

Basic circuit
RE
with Bias ww-
Voltage
w
Module
EE Vcc VBB VcC BB TVEE 2
(IciOFig. 2.5.2(a) (1C1)Fig. 2.5.2(b) (1C12)Fig. 2.5.2(c)

AC
equivalent
circuit with ww
DC shorted RE Rg
ww*
V

Emitter common Collector common

Base common

(IC14Fig. 2.5.2(e) (IC15)Fig. 2.5.2()

(1C13Fig. 2.5.2(d)
AC input Low (20 to 100 2) Moderate (1k to 3k) High (Mega 2)
Resistance
(Z)
AC output High (1 to 3 M2) Moderate (40 to 80 kS2) Very low (in ohms)
resistance
(7)
= current gain B= current gain Y= current gain
Current gain

Y=1+B
b

Very low<1 Medium (20 to 300) Large (21 to 301)

Phase shift 0° (in phase) 180 (out of phase) 0° (in phase)

between
V, and V
<1 el (unity)
Voltage gain 1, But low power gain 1 , But high power gain

and Voltage amplifier Buffer or Impedance matching

Applications High Bandwidth amplifier
constant current source.
amplifier.

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 Analog Electronics (MU.Sem.3-Electrical) 2-10 Bipolar Junction Transistor
GO.
*--**-**
Explain operation of NPN transistor.

Operation
In the
Fig. 2.5.3, VEE and Vcc are used to make,
(a)baseemitter junction g ) forward biased and (b) base collector junction Osc) reverse biased.
2. Since base emitter junction is forward biased, width of depletion region (DR) and height of potential bamier (PB),
across it, will decrease and will be negligible (not shown). While with base-collector junction reverse biased, width of
depletion region and height of potential barrier across it, will increase.
Increased PB Uncovered
Helght of PB and min car e (drift) positive ions

Conventonal
emitter curent
width of DR negligible
h Leakage curent

Conventional

cao or lco
O9 OO

maj car
(diffuse)
min car e (drit)
/ BE
Increased
maj car e
(excess)
Current due to
recombination DR

Electronic emitter VEE Conventional Electronic Electronic

current CC
(1 to 2V) (5 to 20V)
(Ec B) B
E
C

(1C16) Fig. 2.5.3 :Operation of NPN transistor

3. Since base emitter junction
() is forward biased (FB), electrons () will diffuse from
(B) region. This will create deficiency of electrons Emitter (E) region towards Base
() in Emitter (E) region. This
supplied by negative (-ve) terminal of VEE. This constitutes deficiency is filled by Electrons ()
electronic emitter current. The
IE will be in opposite direction. conventional emitter current
4. As soon as the electrons (¬) (diffused from Emitter E) enter in
P type). Base, they become minority carriers
(because base is
(a)
Few of these electrons
() recombine with holes in base. "Few"
the
duration for which these electrons because base is very thin and
() remain in base is very small. lightly doped. Also
holes causes
deficiency of holes in base. This deficiency is fulfilled The recombination of few electrons () with
thermal agitation. Once holes are by electron-hole pair
absorbed by base, respective generated in base due to
(+ve) terminal of VEE: These are few remaining
electrons. Hence base current is in electrons () are attracted by
(b) Now most of uA. positive
electrons () (diffused from emiter
of
internally generated region) are drifted from B and C. This
electric
field or potential barrier (PB) across happens under influence
5. base collector
Drifted electrons in
collector region become excess and are collected junction (Uc).
electronic collector current. by positive (+ve) terminal of Vce. This constitute
Conventional Ie will be in opposite direction.

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 Analog Electronics (MU-Sem.3-Electrical) 2-11
Bipolar Junction Transistor
6. Leakage current
ICBo or lco) Conventional

Refer Fig. 2.5.4. Base region is CBO

P type and is at room
will be thermal temperature. Therefore there
agitation in it. This generates
electrons-hole pair. Open
The generated electrons () are minority carriers. These
from base to collector under influence of
electrons (e)
potential barrier
are drifted
base collector
L
junction (JBc).
across VEE Vce
(1C17 Fig. 2.5.4
This causes an electronic current from B to C and
is known as
Leakage current.
Conventional leakage curent with emitter open
The conventional leakage current is abbreviated as Module
IcBo Or Ico
It is flowing from collector to base with
third terminal
to base
from collector
2
Emitter) open. (IC18) Fig. 2.5.5
Since thermal agitation increases with
temperature, IceO is temperature dependent. It doubles for every 10°C increase
in temperature. It is very small i.e.
10 "to 10"A. Hence, IepO is normally neglected.
)2.6 OPERATION OF PNP TRANSISTOR (CB)
Ga. Explain operation of PNP transistor.
Leakage curent
(due to min car)

+ +++ + +

++++++ ++
eco
ale

K
BE JBC
Recombination of holes

E
hole current
(Conventional)
(conventional)
(IC19) Fig. 2.6.1: Operation of PNP transistor

1. JE is forward biased using VEE while JBc is made Due to this, vacancy of holes is created in E, which is
reverse biased (RB) with Vcc. This makes the operation fulfilled by +ve terminal of VEE This causes I
of BJT to be in active region. (conventional) to flow as shown in Fig. 2.6.1.
2. Since JBE is forward biased (FB), width of DR and Since base is very thin and lightly doped, few holes
height of potential barrier (PB) across it is (diffused from E) gets recombine with electron in base
approximately zero. region. This creates deficiency of few e in B region,
3. Due to forward biasing (FB) of Jpg the majority carier which is fulfil by negative terminal of VEB. Hence the
(hole) diffuses from emitter (E) to Base region. conventional current due to few holes flows out of base
lead.

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Analog Electronics (MU-Sem.3-Electrical) 2-12 Bipolar Junction Transistor
5. Remaining most of holes in base region (diffused from As temperature increases, thermal agitation will
E to B) are minority carriers in n-type base. These increase.
holes get drifted from B to C under influence of PB Due to increase in thermal agitation, minority carriers
across Jac. This causes the main current due to in base will increase. This causes increase in leakage
majority
carries. current lcBo
6. These holes drifted from B to C become excess in C.
Therefore they are attracted by -ve terminal of Vec -IcBO or lco

Causing conventional Icto flow as shown in Fig. 2.6.. a le

7. Leakage Current : Out of thermally agitated electron-

hole pair in base region, holes (minority carrier) get
drifted from B to C region. This causes hole current lcBl lcBo
(conventional) from B to C. This current is known as
(1c2) Fig. 2.6.3
Leakage Current (pc
The leakage current (lcBO) doubles for every 10°C.
C

Increase in CBO Will increase Icbecause

Bco Therefore power dissipated (Pp) in
Open le =
og +
IcBO
collector region (in terms of heat) increases. This

VEE Vcc causes collector to become very hot and finally

transistor to get damaged. This is the reason collector
(1c20) Fig. 2.6.2 is largest in area, so that it remain cool.

2.6.1 Current Relations for Common Ga. Why base is very thin and lightly doped ?
Base (CB) Configuration (npn
From Fig. 2.6.4 we define emitter or injection
Transistor) ()
From Fig 2.6.1,first equation that we can write is, efficiency (Y)
Current of injected carrier at
c+l» BaseTotal
Emitter Junction UaE)= -
Further from operation of n-p-n transistor
As VEE increases base emitter junction (JBE) becomes
Y emitter current IaE+Ip
1.
more forward biased. Number of electrons diffuse from Where, IE indicates holes diffused from Base (B) to

emitter to base increases. Emitter (E)

For the proper operation of Bi-junction Transistor, Y
Vacancy of electrons in emitter region increases,
electrons supplied by VEE increases. Therefore Emitter should be as high as possible, for that IE should be as
Current ( ) increases. low as possible. This is the reason base is lightly doped.
3. Since electrons diffused to base increases, electrons In short base is lightly doped to increased Emitter
drifted and reaching to Emitter (E) region increases efficiency (y).
also electrons (E) attracted by Vccincreases.
nC
4. Therefore, Ie increases. It means as I increases, Ic also nE
increases. Hence we can say Ie is proportional to Ig EO
e l or le= a l_. Where a is proportionality constant. BE BC

Ga Why collector s largestin size

(as shown in Fig. 2.6.3) EE
. (1c23)Fig. 2.6.4
From Fig. 2.6.3 we see that one of the components of
(i) From Fig. 2.6.4 we can define one more factor a
collector current is the leakage current, Icuo This leakage
current is function of thermal agitation. Transport factor ß*.
Yentur
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 Analog Electronics (MU-Sem.3-Electrical)
Injected carrier current reaching Base Collector Junction
2-13 Bipolar Junction Transistor
Injected carrier current at Base Emitter Junction (Jgg) (ec) | PB

BE h ec
nE

For proper operation of transistor, B* should be as large Wg

as possible. For this, recombination of electrons ( e") in
base should be minimum. This is the BWOR
reason, why Base
(B) is very thin and lightly doped.
In short Base (B) is thin and
lightly doped to have
Module
high value of B.
VEB VcB
If Base (B) is thin and lightly doped then Large
Signal
(To FB JBE) (To RB Jgc 2
Current Gain (a) of transistor will be
high. (1c24)Fig. 2.7.1: Early effect or base width modulation
-Sinc
-.- Y ß*
A s VcB increases, height of potential barrier across
GQ. Why emitter is heavily doped?
---- JBC increases, number of drifted to collector
To have high current gain of transistor, the number of increases, number of e in base decreases,
electrons (majority carriers) diffused from emitter concentration gradient across emitter-base junction
should be as high as possible. This increases, more number of electrons
is the reason, BE are

Emitter (E) is heavily doped. diffused to base from emitters. Deficiency of

It means again heavy doping of Emitter (E) results high electrons () in emitter increases. Therefore,
electrons supplied by VEE increases hence Emitter
Yand ' . In other words high o.
Current 1) increases.
2.7 EARLY EFFECT OR BASE Therefore, due to early effect, Ig decreases, Ig and Ic
WIDTH MODULATION increases.

Ga. What is early effect ? Explain how it affects the BJT

2 . 8 COMMON EMITTER
CONFIGURATION
characteristics in CB configuration.
-- -----'--
Referring Fig. 2.7.1. As Ven ie. reverse bias voltage Ga. Why Common Emiter (CE) configuration isfrequently
across base collector junction JBc varies, width of used ?
depletion region (WpR) varies; due to this width of base Common Emitter (CE)
(W) will vary. This is known as early effect or base width
configuration is frequently used
because:
modulation (modulation means variation). 1. It provides high current gain. 2. Highest voltage gain.
3. Highest power gain.
Effect of Early Effect (EE) on different transistor
4. Loading effect is moderate.
currents is as follows
As Vce increases, W(width of Base) decreases, GO. Explain operation of Common Emitter (CE)
number of electrons () recombining in base configuration of BJT
- -

region decreases.
This decreases base current Iy.
RB
lc Number of electrons ( ) drifted to collector
DCLoad
increases (assuming electrons diffused from ww resistance
(2 to 5 k2)
Emitter to Base are constants), hence lc
VBB
increases. L Vcc T 10V

(Iczs) Fig. 2.8.1: CE configuration of transistor

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eAnalog Electronics (MU-Sem.3-Eloctrical) 2-14 Bipolar Junction Transistor

Collector
C
c
N

Rg
RBBc
R Recombination-
maj. ca
VBB B BE 10V (exess)

1V E Vcc Depletion region armer

Potential

Base e min.
BB Carrier
(Ica)Fig. 2.8.2: Two diode analogy of NPN BJT
(drift)
BE
1. In this configuration, Emitter (E) is common to input
and output ports. Input voltage v, is applied between
base and emitter and output is developed between e maj
Carier
collector and emitter. VBB (diffusion) Vcc
2. BJT is operated in active region by making base emitter (1 to 2V) E (5 to 20V)
junction (B) forward biased (FB) with VBB and base Emitter

collector junction pc) reverse biased (RB) with Vcc

Voltage at collector (V)is kept higher than voltage at
base (V), so that base collector junction Uac) is (IcznFig. 2.8.3: Construction and different currents
of NPN BJT (Common Emitter (CE) configuration)
reverse biased (RB).
6. If forward biasing of JpE is slightly reduced, the number
Ve-Va2+0.7 V]
of electrons () diffused from emitter to base region
. Forward biasing of base emitter junction pE) allows
electrons from emitter (E) region to get diffused to
will decrease. Therefore number of electrons
recombining with holes in base region decreases. Due
base region. Hence there will be deficiency of electrons
to which deficiency of holes in base region decreases
i n emitter region which is replenished by electrons
Hence holes supplied by VBB decreases. Therefores
supplied by Vcc decreases, which is in uA.
A. Approximately 98% of electrons in base (diffused form At same time since diffused electrons in base
emitter) are drifted through base collector junction (Jsc) decreases, electrons drifted to collector decreases, this
and are collected by collector and attracted by Vc will decreases Ie which is in mA.
This causes large collector current (I) to flow. It means by controlling base current 1, which is in

. Remaining 2% of (E) recombine with holes in p-type HA, we can control I which is in mA. In other words
base. VBB Serves to replenish these holes and constitute with a small current at input, we can control arg
base current Ig current at output.
This is MAGIC of TRANSISTOR.
Also this is the reason why BJT is known as Currep
Control Device.

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Analog Electronics(MU-Sem.3-Electrical) 2-15 Bipolar Junction Transistor
)2.9 CURRENT RELATIONS IN Typical values for Ieo are 500 A for Ge and 20 uA
COMMON EMITTER (CE) for Si. Since it is very small, it is normally neglected.
CONFIGURATION Neglecting CE in Equation (2.9.7) we get,

For CB, we saw utput current of CE

2.9.1)
Poc T Input current of CE
It means. Bpc is current gain of common emitter (CE).
(2.9.2) Let pc 0.98 then Equation (2.9.4),
le = p c , (neglecting lcao) (2.9.3)
pc
Where Icis output current and I is input current. Pbc -pc1-0.98 49
0.98 Module
Similarly for common emitter (CE), we must find
It means, current gain of common emitter (CE) is
relation between output current Ic and input current Ig.
much higher than common base (CB). This is one of
Substituting Equation (2.9.2) in Equation (2.9.1) we the reasons why common emitter is preferred. Ppc
get, ranges from 20 to 300 in practice.
Lc pcde + lcBO= Ope c t Ig) + IcBo Example: Let for a BIT IcBO is 1 wA, the resulting
le-oc he=L(1-Gpc)=lcBo + Gpcp leakage current for common emitter (CE).

DC CBO CBO IA
Or Ie 1-dnc*1-Gpbc .(2.9.4) CEO 1-Gpc 1-0.98

Equation (2.9.4) can be converted to an equation in = 50 uA =50 IcBo

which output current c and input current Ip (of It means leakage current in common emitter (CE) is
common emitter) can be related. much larger than common base (CB).

Let, Poc 1-dpc dpc .2.9.5) This is undesired condition for a given amplifier.
ceo is defined with I =0. Therefore, for linear (least
and
CEO CBO
1-pc 2.9.6)
distortion) amplification purpose, cutoff for common
emitter (CE) configuration will be defined by Ic =
lEo
Equation (2.9.4) becomes, Relation between apc and Ppc
2.9.7)
Opc
This is important relation of common emitter (CE)
relating its input and output currents.
BDc1-dpc
Where lcEo is conventional leakage current flowing Cpc
Ppc
1 +Poc
from collector to emitter with base open.
(Refer Fig. 2.9.1) 1-Cpc
1+Ppc
2.10 INPUT AND oUTPUT
'CEO
R
CHARACTERISTICS OF
COMMON EMITTER (CE)
Base
open CONFIGURATION
Vcc

GQ. Explain graphical method to obtain parameters of CE

(IC28 Fig. 2.9.1 Reverse leakage current
configuration.
Conventional leakage current- base Open Ga. Draw Input and output characteristics of BUT in
to Emitter common emitter configuration.
- from Collector UQ. Explain the input and output characteristics of CE BJT;
(Ic2) Fig. 2.9.2 ampliier. (MU-Q.2(a), May 18, 10 Marks)

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 Bipolar Junction Transistor
Analog Electronics (MU-Sem.3-Electrical) 2-16
forward biased
and Jpc is reverse biased
When JaE is
2.10.1 Input Characteristics 0.7V more than VBE), transistor works
at least
(VCE is this mode as VcE ROes
mode. In
(Refer Fig. 2.10.1) in active
increases more sharply compared to
To plot this characteristics, I, is measured at different increasing, Ic also
values of VBE, keeping VcE COnstant. This is separated with common base (CB). This is because of early effect
ect and
much larger than a.
various values of VcE(as shown in Fig. 2.10.1). also since ß is very
Current (1e. fixed V,.)it
value of base
2. For a fixed
configuration, there exists a junction
VCE c decreases; but as soon
A
tne
input of CE we go on decreasing
equal to 0.7 v ;ie.
is greater than
or
(diode) which is forward biased (active region). V
as (V
Therefore input characteristics is nothing
but V), gc becomes forward biased.This
(V-Ve 0.7
at 0.3 to 0.6 V of Vep. Sinoe
characteristics of forward biased diode. happens approximately
forward biased, transistor enters in
decreases due to early effect, both junctions are
(6) As VCE increases, Ia
more saturation.
becomes more and
hence characteristic becomes more forward
If VcE is reduced futher, Jpc
across Jgc vanishes,
and Potential Barrier (PB)
horizontal.
biased
with VcE constant (at any
(C)Inverse of slope of curve
of BJT in common
value of VBE gives input resistance IcmA) IcmA vis VcE (
emitter (CE) configuration. Saturation @Ig Constant
region Active region
30AB3
== hie
AVcE 4MA

Range 1 k2 to 3 k2
*y* **********. *Yrssseses*y s****se*g********y********* 3mA

e(uA) v/s VBE(V)

20 pA=Ig2
2mA

VCE 0 V
2V
10Al
1mA
0.6 ********************

*******" ********g********"******* ***

****

'cEO OAl
04
VcE(sat) = 0.25 V
Cut off region

0.2t
0.6 0.7 0.8
VBEV (1c31)Fig. 2.10.2: Output characteristics of CE
configuration
(1c30A) Fig. 2.10.1 : Input characteristics of CE
This stops drift of electrons from Base to Collector
configuration
which reduces Ie to zero.
a2.10.2 Output characteristic of Common 3. If we decreasing VpE/ g, forward biasing oflt
start
Emitter (CE) Amplifier reduces, this reduces diffusion of electrons from emite
to base. Hence, recombination in base reduces whic
(Refer Fig. 2.10.2). To plot output characteristics of CE
configuration we keep I VBE Constant. The collector
reduces I. With VgE =0, diffusion of electrons fro
emitter to base stops. Drift of electrons from base
voltage VCE is varied to measure
collector ceases.
If this exercise is repeated for different values of
can obtain family of output characteristics Therefore, collector current remains only consisting
IpVBE we

shown in Fig. 2.10.2. From these output

minority carriers in B i.e. IcEo
curves as
IfVBE iS further reduced (change of polarity), both
characteristics curve following points can be concluded.
and JBC becomes reverse biased sistor
(RB) and tr
enters in cut-off region.
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 Analog Electronics (MU-Sem.3-Electrical) 2-17 Bipolar Junction Transistor
4 If compare characteristics of common base (CB)
we

and common emitter (CE) in active region, slope in

common emitter (CE) case is more. 2 k
AC input
Therefore, output resistance of common emitter (CE)
or
amplification
Rc or R
To convert
will be less compare to common base (CB). output curent to
output voltage

ie. 2mvV and limit lcC

Alc laM,=0 ho T VB8
Range40 to 80 k2. To make JaE FB To make JgBc RB
Module
5. The other parameter which can be obtained from output
Emitter (E) common to input and output port
23
characteristic is current gain ß or he
Refer Fig. 2.10.3) (IC3) Fig. 2.11.1 : Basic voltage amplifier

B he
IB2eVCE const Rc
TV%
Ale
AlpAVCE V 2m
1 k o80ka
c(mA) lclmA)vis Vae) (1 to 3 k2) (40 to 80 k2)

-Is2(uA)
(Ic34Fig. 2.11.2: AC equivalent circuit of Fig. 2.11.1
Ic2
le1(HA) Circuit shown in Fig. 2.11.1 is basic voltage amplifier
Ic to convert input voltage to amplified output voltage.
Fig. 2.11.2 provides ac equivalent circuit by shorting dc, so
that from this circuit we can find ac output voltage with ac
VcE VcEV)
constant voltage applied at input.
100
(1C32) Fig. 2.10.3

6. Comparing common base (CB) and common emitter

(CE). 2mv 1 ka

Parameter Common Common

Base (CB) Emitter (CE)
(Icas Fig. 2.113 : Equivalent circuit on input side
T

(1+)
20 to 100 2 Ik to 3 k2

I MQ to3 M2 40k2 to 80 k2 80k

Current gain a =0.95 to 0.99 B=20 to 300

2.11 CE CONFIGURATION AS
vOLTAGE AMPLIFIER (1ca Fig. 2.114 : Equivalent circuit at output side

Ga. How CE configuration be used as voltage ampifier

From circuit (Fig. 2.11.3),
Why transistor is known as transistor?
V,iX

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 Analog Electronics (MU-Sem.3-Electricl) 2-18 Bipolar Junction Transistor
OR

From circuit above

(Fig. 2.11.4), R,= R;lI r,
Since r,>>R we have
R R; and i =i, =Bi,
Therefore, Iv= io R= i, R; = Bi,RL

100x x2 kQ = 400 mV wOW!

k2
Input voltage 2mV while output voltage 400 mV. This is
amplification.
For any voltage amplifier we define a figure of merit, to indicate how good amplifier is to amplify input voltage.
That is,

Voltage Amplification factor or voltage gain lAyl =

=
ln our case lAyl =-400
2 mmV
V = 200. It means our amplifier has voltage gain of 200.

A y V , = 200 x V,

From above discussion that, for

we see
providing amplification input current (i,) is
flowing through low resistance
= 1 k2) and controlled output current
(i, Bi,) is flowing through high resistance (R 2 ks2)
=
=

It means current is getting transferred from low resistance at input to high resistance at output, to
provide voltage
amplification.
It means there is TRANsfer of
reSISTER. Hence it is known as TRAN+ SISTER =
TRANSISTER.
2.12 cOMMON BASE
CONFIGURATION
Common Base Amplifier Circuit
GO.
----
Draw circuit diagram of common Base (CB) amplifier. Write function of component used.
----** - -

wwt Rs

RE Rc o
-VEE Vcc
Source
Amplifier Load

(IC221) Fig. 2.12.1

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 Bipolar Junction Transistor
Analog Electronics(MU-Sem.3-Electrical) 2-19
1
Circuit shown in Fig. 2.12.1 is of typical Common Base EB
CB) amplifier where, R, I CBost
(a) VEE and Voc are used to make Base Emitter
Junction (BE) Forward Biased and Base Collector AVE
Junction Bc) Reverse Biased respectively. Hence lava=®
BJT is biased in active region. Range ofR,> 20 to 100 2
b) Input coupling capacitor (Cci) is used to block DC
From input characteristics we conclude:
coming from source, so that DC biasing of BIT is
(a) As input of CB is nothing but a diode (BE) which is Module
intact. Output Coupling Capacitor (Cc) is used to
is
block DC from amplifier. forward biased. Hence the input characteristics 2
(c) Emitter Resistance (R) is selected to control Io diode.
nothing but characteristics of a forward biased
while Rc is DC load.
2. In Common Base (CB), input signal (V,) and output EmA) Meal ) vs lE(mA)
signal (V) are in phase.
6V 4V Ycs 2
3 Common Base (CB) amplifiers are designed such that
for AC operation, base is common to input and output
ports.
4. AC input V, is applied between Emitter (E) and Base
B), while output (V,) is collected between Collector
-AVEB
'E
C) and Base (B). 0.8 1 VEBlV

5. Load Resistance (R) is input resistance of load while

VEB
Source Resistance (R) is output resistance of source.
(1c223) Fig. 2.13.2

2.13 CHARACTERISTICS OOF (b) As VCB increases, slope of characteristics also

COMMON BASE (CB) increases; this is due to early effect.
CONFIGURATION (c) Since at the input a forward biased diode is present,
input resistance is very small (20 to 100 2).
Ga. Draw input and output characteristics of common
From input characteristics we can find input resistance
Base (CB) amplifier. What are the parameters we can:|
of CB configuration as (Refer Fig. 2.13.2)
obtain from these characteristics?
BOutput characteristics
Input characteristics Refer Fig. 2.13.3. This chara teristics is drawn by
Refer Fig. 2.13.2.To draw input characteristics, input measuring output current Ie while output voltage VcB is
voltage VEB is varied and at different values of VeB we
varied. This is done keeping input voltage constant.
measure Emitter Current T). During this step, output
Different members in family of output characteristics
voltage VcB is kept constant. are drawn at different values of constant VEB /ME
From output characteristics we can conclude following
points
VEB VcB 1. Active region: In this region JBE is Forward Biased
(FB), Jc is Reverse Biased (RB) and Ic is slightly less
than Ie This is due to recombination of electrons in thin
and lightly doped base region. In this region, as VCB
(1C22) Fig. 2.13.1
increases Ie also increases slightly. This is due to early
aree
Different members in family of input characteristics effect (EE).
drawn at different values of constant VCB

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 Analog Electronics (MU-Sem.3-Electrical) 2-20 Bipolar Junction Transistor
Ga. What are the drawbacks, if BJT is used in common
c(mA) Base (CB) configuration ? where can common Bas
VcB(V) v/s lo(mA)
Active (CB) be used efficiently ?
region
Ic IE= 3mA
Drawbacks
(mA)
2mA (a) Since current gain of common base (a) is less than 1,
common base can't be used as current amplifier.
1mA
(b) Refer Fig. 2.13.4.

cBO On input side, since r, is very low, common base loads

E0 the source.
8 VcB) On output side, since r of Common Base (CB) is very
high, it itself gets loaded by load.
Cutoff region
Hence severe loading problem.
(c) It can be used as voltage amplifier but due to low
(1C25) Fig. 2.13.3
current gain voltage gain is low.
For a particular output characteristics (e.g. at Ig = 3mA)
(d) Power gain is low since a is low.
if we go on reducing VcB Lc decreases (due to EE). But
with VCB = 0, Ic is not zero. This is due to the fact that uAdvantage
even though Jsc is shorted there exists PB (Potential Since stray capacitances at input of common base (CB)
barrier) due to depletion region across it, which is configuration is low, its bandwidth (BW) is large.
enough to drift electrons from B to C. These drifted Therefore in applications like radio and TV, common
electrons are collected by positive terminal of VEB. This base is efficiently used because of its high Bandwidth
will constitute I. Hence with Vcs= 0, Ie #0
(BW).
2. Saturation region : If VcB is reduced further (change
Source CB amplifier Load
of polarity) then at 0.3 to 0.6V, Jsc becomes Forward
Biased (FB). PB across JBc vanishes. Hence drift of ww-
electrons from B to C stops. Ic becomes zero. Since R o

both junctions now are forward biased, transistor enters

in saturation region.
20 to 1002 o 1 to 3 MS2
3. Cut-off region: If we start with higher value of I and
reduce it by reducing VEB then number of electrons (1cz26) Fig. 2.13.4
diffused from E to B reduces which causes reduction
in number of electrons drifted to C. It means with GO. With numerical values, explain how a transistor can be
decrease in VEB both le and Ie decrease. If VEB = 0, used as voltage amplífier when connected in
diffusion of electrons from E to B becomes zero. Common Base (CB) configuration ?
because of emitted electrons (from E) becomes
zero. But since Jgc is RB, leakage curent does flow C B as voltage Amplifier
(i.e. IcBo). In other words with VEB = 0, IE = 0, but (Refer Fig. 2.13.5) In circuit diagram VEB is used to
L IcsoIf we reduce VEB further (reverse polarity) make JBE forward bias, while Vcc is used to make JBc
JBE becomes RB (ac is already RB) and transistor reverse bias. Therefore BJT is inactive region. V is ac
enters in cut off. voltage to be amplified.
4. Output Resistance: Since characteristics in active
region is as good as horizontal (slope = 0), the output

resistance is very large (1 MQ to 3 M2).

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Analog Electronics (MU-Sem.3-Electrical) Bipolar Junction Transistor
2-21

2mV S i 1002
rmS
R2V 2mV

VE cC (IC2mFig. 2.13.7: AC equivalent circuit on input side

100 o 3 MO

Output side
(1c220Fig. 2.13.5 Module
Since r >>Re r,I Re R¢ 2
IV,I =
i,Rc= 20x 10 x 2x 10° = 40 mV
V,2mv
T c
2K V
Voltage gain =
Ay =
= =20

(c230)Fig. 2.13.6: AC equivalent circuit

AC equivalent circuit of CB voltage amplifier can be drawn

3M
by shorting DC sources. (Refer Fig. 2.13.6)

Input side : Refer Fig. 2.13.7)

(1c29) Fig. 2.13.8: AC equivalent circuit on output side

Hence we conclude that even though CB amplifier

2 mV 20 uA
i =00 cannot work as current amplifier, it can work as voltage
amplifier within its own limitations.
Since CB, ie ie

2.14 CONCEPT OF LOADING EFFECT AND COMMON COLLECTOR

CONFIGURATION OF BJT

EAC Equivalent circuits of Amplifiers

1. Voltage amplifier Ay (voltage gain) Current amplifier A (current gain)

w
R
A

Ay A
(1c240) Fig. 2.14.1 (IC241) Fig. 2.14.2

Since at output we get amplified voltage, the output Since at output we get amplified current, the output
2.
resistance R, is in parallel with output current source.
resistance R, is in series with output voltage source.

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 Analog Electronics (MU-Sem.3-Electrical) 2-22
Bipolar Junction Transistor
Loading effect and ldeal characteristics of an
Preventive Steps to avoid Loading Effect
amplifler
If we assume both source and load as amplifiers then
In our house when we connect iron or fridge to 230V . Input resistance of amplifier (R;/R) should be as high
(mains) all lights become dim.
as possible. This decreases I, therefore IR, decreases.
As your CPU of computer is made ON
soon as Since the drop across R, is low reduction in V, is less.
lights in
the house glow with less intensity. Therefore, loading is less.
When output of CE
amplifier is connected at the input
a 2. R/R, should be as low as possible i.e. output resistance
of next amplifier, output voltage of first amplifier of amplifier (source) should be very low. In this case,
reduces. even though I is high IR, will be low and reduction in
All this is because of V will be low. This decreases loading.
a very important but undesired
effect known as LOADING EFFECT. . Gain of amplifier should be very large. So that even
Source Load with loading, required output voltage (Vo) can be
loop
Rs.Ro obtained.
w From above discussion, we can conclude that
AC characteristics of an ideal amplifier should be as follows
Dc
(A) Input Resistance should be infinite.
(B) Output Resistance should be zero.
C)Voltage gain should be infinite.
(1c242) Fig. 2.14.3
2.15 cOMMON cOLLECTOR
230Vsupply Ironor fridge AMPLIFIER/ UNITY GAIN
Battery Bulb AMPLIFIER/ BUFFER
Microphone Speaker AMPLIFIER
Antenna Radio () Circuit diagram
- DCsupPply in college -CRO c
-Amplifier - Amplifier
In the Fig. 2.14.3 we note that an amplifier can work as
load as well as source. Source, when it provides amplified RE
signal, Load when it receive amplified signal. In Fig. 2.14.3.
Rg or R, is output resistance of source or amplifier
R or Rz is input resistance of load or amplifier
Source i s electronic (or electrical) point, device or VBB VEE
Circuit of cc amplifier
appliance which supplies energy.
Load i s a point, circuit, device or appliance which (IC243) (a)
consumes energy.
In Fig. 2.14.3 when load (R) is not connected, loop

(consists of source and load) is open. Hence current I = 0.

V=V,
Now if load is connected, the loop is closed, hence I
flows. This causes voltage drop across output resistance (R)
of sourcei.e.IR,).Therefore, output voltage [ V = Vs -I Rs
R R
] will decrease.
AC Equivalent Circuits
This reduction in output voltage vo of source when load
is connected is known as LOADING EFFECT. (1C244) (b) (1c245) (c)
Fig. 2.15.1
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 Analog Electronics (MU-Sem.3-Electrical) 2-23 Bipolar Junction Transistor
(i) Current relation

We know pc Current gain of CB V=Vp Je

VE=Vo
Poc Current gain of CE =
V
VBE
Let
YocCurent gain of CcC =
For CB we derived equation (a) (b) Module
(1C246) Fig. 2.15.2
Ic= CpclE +lcBo 2.15.1)
Where IcBO is leakage current Important characteristics of CCconfiguration
Since, Ic = Ie-I (1) Input Resistance very high (because at input Jsc is
present, which is RB)
Equation (2.15.1) becomes,
(2) Output Resistance very low (because at output JBE
IE-I GpclE + lcCBO is present which is FB)
lCBO (3) Voltage gain unity.
1-a 1-c (4) Current gain highest. (y = 1+B)
Let Ypc 1 - d e= (1 Above three properties of CC amplifier make CC
+ Ba)
configuration suitable to be used as buffer or impedance
IeYoclp+(1 + Ba) ICBo matching network.

If we neglect leakage current (1 +P IcBo then (vi) Application of CC amplifier as Buffer or Impedance
matching network.
Ypc B
=(1+Ppe
YDc 1 + Ppc
AV
RRs VAv- 1R
D C current gain in CC is maximum.

ii) CC as emitter follower

CE R high R, low CE
From circuit shown in Fig. 2.15.2(b) we see that
VV-VBE Since VBE is normally very smal. (1c247) Fig. 2.15.3
If Fig. 2.15.3, two CE amplifier are cascaded to get
V . V Since in CC, V, V, as input at base will
more amplification. Cascading (connecting output of one
vary, output at emitter (V) will also vary in accordance. In
amplifier to input of other) of CE amplifiers shown in
other words, emitter follows base. Hence CC is also known Fig. 2.15.3 reduces the total gain due to loading effect as
as EMITTER FOLLOWER. explained below.

(iv) CC as unity gain amplifier 1. Since output resistance (R,) of CE amplifier (A,) is
high (40 to 80 k2), when current I flows through it,
Since V. =V, drop across R, (IR,) is large.

Voltage Gain A, = yVo =l=unity

Hence input to Az reduces, because V, AV, -IR
=

Since input voltage of Az decreases, gain of amplifier

Hence CC is also known as UNITY GAIN AMPLIPIER. decreases.
Technically, We say A is getting loaded.

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 LAnalogElectronics (MU-Sem.3-Electrica) 2-24 Bipolar Junction Transistor
2. Input resistance of CE amplifieris always low (Let 1| output resistance of A, is high while input resistance
of
k2). When output of A, is low.
A
is connected to input of Az
again I increases because R, of A is low. Therefore To overcome above problem of loading and impedance
drop IR, will be more and V, decreases. This reduces mismatching, we connect CC amplifier between
two
gain. Technically, we say A, is loading A CE amplifier (source and load) Fig. 2.15.4. The Cc
. From above two points we conclude that total gain of amplifier (Buffer) provides impedance matching and
amplifier reduces due to impedance mismatch. i.e. also it reduces loading problem. This is possible
only
with special properties of CC configuration.

CE CC CE

ww
R Ro
AM
Source Buffer Load
R high R high R, low R, low

(1c248) Fig. 2.15.4

GQ. Why do we prefer CE configuration as an amplifier ?

--- ----
CE configuration is preferred due to its following properties.
1. High current gain. 2. High power gain.
3. Good stability of input and output resistance with changes in load and source resistances (Rs and R)
4. Much better, for R, and R, compared to CB and CC. 5. Impedance matching is efficient.
Ga. Why we don't prefer CB to be used as an amplifier ?

CB is not used as an amplifier because of following reason.

Since R, of CB is low, current drawn by it is large. Due to this

source gets loaded, and output voltage of source reduces. Also since
output resistance of CB is large, current drawn by load will cause Source co Load

more drop across R, of CB. In other words, CB gets loaded by load.

It means there is twofold loading effect. Low Ri Low Ro

(1C249) Fig. 2.15.5

Due to these reasons, CB is not preferred as a
voltage amplifier.

NOTES

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Analog Electronics (MU-Sem.3-Electrical) 2-25 Bipolar Junction Transistor

Part (B): DC Circuit Analysis

2.16 LOAD LINE
mA)

Ga Write short note on DC load line and Saturation

significance of DC load line
Q-point.
Rc /
GQ. Write short note on : DC load line
concept in BJT. clsat) (Slope R
Why Q point should be at the middle of DC Ioad
and fixed?
line Active - Cutoff
Module
Write short note on DC load line. What is Q
2
GQ.
point ?
Where it should be located on DC Ioad line ?
(Vcc0) VCEV)
Ua. Explain DC load line in common emitter BJT. VcE(sat)= 0.25V

(MU-O. 1(b), May 18, 5Marks):

-------- (1c38) Fig. 2.16.2

2.16.1 DC Load Line and Q-point of If we see output characteristics of CE amplifier we

Amplifier
have same axes. It means this line can be drawn on output
Refer circuit shown in Fig. 2.16.1 where,
Vcc and VBB characteristics. Two points for line can be obtained as
are
used to bias transistor in active region. Rc is used to follows:
convert output current I) into output voltage Vo Rp is to| (A)
limit in
Let transistor be in saturation then
Ig uA range and it provides adequate voltage to JBE
to make it forward biased. VCE VCEsa)OV,
This condition of amplifier is known as quiescent (B) Let transistor be in cut off then
condition, where only DC voltages are applied. In this
condition of amplifier, all voltages and currents are written VCE VcC
with suffix Q, e.g. leo. Ico and Refer Fig. 2.16.2.
VCEQ etc
Now if we apply KVL in C-loop we get
Voc-e Re-VcE = 0
Vcc
which can be written in the form of equation of line as Rc D C load line

Vcc Ico, (Slope:

y = mx + c

Icag
c
00p CEQCEa, CEQ Vcc VcE
Rc
Rp (DC load)
VCE
ww
BQ
(1C39) Fig. 2.16.3

VBE So two points are(0, VccR) and (Vcco 0); joining

these points on output characteristics of CE amplifier we get
a line with Y intercept Vc/R¢ and negative slope (1/R
VBB Vcc Since slope of the line is inversely proportional to DC
load (R), it is known as de load line (DCLL).

(1c37) Fig. 2.16.1

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 ~ Analo g Electronics (MU-Sem.3-Electrical) 2-26 Bipola r Junction Tranaisto,
If we assume Vcc and Re as constant then all values
of
le
~l and VCB (satisfying equation of DC load line) will r-
_!e~J · • --' J , . : ' . . --~ ~- . •-· -· - -·~..:.,_;

' intersect on DC load line. Refer Fig. 2.16.3. .

' All the points at which le and VCB intersect on DCLL

are known as Operating Points.
.. _-_.::~:: Sk>pe =- ~B ~--i~- ·::·==~-~-V~-~~.:,
: __ . __ ___ Input characlenat1c
If VCE and le are measured while amplifier ······---.
is in !- ...._,:,__ --
quiescent condition then intersection of lco and V
CEQ 1ea -
' I
on DCLL is known as Quiescent point / Opera 4 j --·--- -~

ting DC bias llne _

' '
Point/Q-point / DC operating point or DC condi
tion
point.

a. veEM
2.16.2 Selection of Q-point (Vcea, lea) ••-•m ,, _ _ _ _ _,
1

While designing _B IT amplifier, values of differ (1C41) Fig. 2.16. 5: Input Char acter istics
ent
resistance and DC voltages must be selected in such
way le
that
(I) Q point should be in active region.
(2) It should be in centre of DC load line.
(3) It should not be toward saturation, otherwise
positive
peak of amplified signal gets clipped.
(4) If Q point is towards cut off, negative peak of ampli
fied
signal is clipped (1C42) Fig. 2.16. 6: DC equivalent circuit
(5) In both conditions (3) and (4), signal at outpu
t will be DC Bias line is drawn on input characteristics.
distorted. Input
characteristics is nothing but characteristics of forwa
,---- -------------------------------------,
I diode, with V CE constant. Refer Fig. 2.16.6. Follow
rd bias
ing are
: GQ. ·, What is DC bias line ? Or What is input I
DC load line ? : the steps to draw DC bias line.
:· Write steps to draw it for a simpl e CE config
I , uration: (1) Draw DC equiv alent circuit by shorti ng ac
source
working as voltage amplifier.
·
: , I

·---·-- · -- __ ---- ---- ---- ---- ---- --- __ __ ...,~

·,-.;;
, ·,
Fig. 2.16.6.
(2) Draw input characteristic.
(3) Apply KVL in B-loop.
+
ie
Vee - le Re - V BE
= 0
+
(4) Write it in the form of y = mx + C

Vee
le = ( - i:.e) VBE +
(1 to 2V) L... ,-J y
(1C40)Fig. 2.16. 4: CE amplifier
y = m X + C
(5) · To draw line we require two points, which
can be
calculated as follows :
With 18 = O; V8 E = V 88
and with VBE = O;
8
18 = :: with slope (- i:_ )
8

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~ Analog Electronics (MU-Sem.3-Electrical) 2-27 Bipolar Junction Transistor

(6) Joining these two points on graph (Fig. 2.16.6) we get

DCBL or input DC load line. 1• Note : The suffix a stands for au~rit ''!~lcl1
✓;·- • /..

(7) Intersection of DCBL and input characteristic means oonstant or no change.

(at constant value of VcE) is at point known as Q-point Any parameter written with suffix 0, lndtcates ·
or Quiescent point or DC point or operating point. The
DC value of that par~er.
respective current and voltage are l 8 Q and V BEQ· •'

I 2.17 SELECTION OF Q-POINT ON DC LOAD LINE (GRAPHICAL APPROACH)

a
Module
• .. ~,,. , - - - - . - - - - - - - - . - - - y . - ""' - .;, .. ' - - - - - - - - ., - - ~
:oa;;·' Where should we· locate a-~nt on DCL!,- ? Whf_? Expl~n'gr~phlcally; . . < . , ,,. ,. . , . , . . , , , :
--
•.. - --- ------ - - ---- - ----- - - ----- - - - - - - - _,-- . - - --- . - - - -- - -- -- -------------- - --- -
..;- ._ . ' "

VBB -VBE
..: ', , . . .
. . .
Refer Fig. 2.16.5. If we select V88 and R 8 we decide I8 Q = R . By selecting BIT we can decide ~. which is
B
fixed . I:. Ico = ~ IaQ Iis decided.
Now refer Fig. 2.16.1. Once V cc and Re is selected by us, we can decide, VCEQ = Vcc - ICQ Re
It means location of Q-point on DCLL is in our hand. We can have it near saturation, near cut off or in centre of DCLL.
Let us see graphically where should the Q point be located.

'a. 2.17.1 Q Point Near Saturation

Refer Fig. 2.17 .1. If Q-point is selected near saturation region then for a part of positive half cycle of input. transistor
enters in saturation and stops working as an amplifier.
Hence a part of positive peak gets clipped and output signal gets distorted.

(1ca)Flg. 2.17.1

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stor

~ 2.17.2 Q-point Near Cut-off

lc(mA)
If Q-point is selected near cut t·-··-·- :
off region then for a part of negative
half cycle of input, transistor enters
s1aturiltio~ region ·-'-··- -
in cut-off and stops working as an I
I

amplifier. - - - [_ f--

Hence a part or negative peak

gets clipped and output gets
distorted.

Q-polnt selected towards cut off region negative peak of Input signal
gets cllpped
.l .l

(1C44JFig. 2.17.2

~ 2.17.3 Q-Point in the Centre of DC Load Line (DCLL) - Active Region

In this case if the amplitude of - _Ic(mA)

input signal is small then for both half

cycles we get amplification without
any distortion. ·Satu'ratio:n region!
• J

:. We should select Q point in

active region, if possible in centre or
active region on DC Load Line
(DCLL).

(1C45) Fig. 2.17.3

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 ['1 Analog Electronics (MU-Sem.3-Electrical) 2-29 Bipolar Junctiqn Transistor

J 2.18 BIAS STABILIZATION

;--- ---- ---- ----al ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- --~:
•UQ. Explain therm runaway and stabilization.
I ,I
:uo. What is Thermal stabilization ? a. 1 c. Dec. 14, 5 Marks)
MU - a. 1 b . Ma 14.
I

:uo. Explain th~rmal stabiliz~tion and compensation . MU - a. 6. Ma 15. a. 1(c. Dec 15. 5 Marks)
I
iers. MU - a. 4 a. Ma 16, 8 Marks)
:uo. Explain the differ:ent thermal compensation techniques in BJT amplif
:uo. Write short note on : Thermal runaway in BJT. MU - a. 1 a. Dec. 14. a.____ ____ ____
Marks
6 a . Dec. 18, 5 ____ _J
I

I ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
, ____ ____ ____ ____ ____ ____ ____ Module
Once location of Q-point is finalized on DC load line, then
The Q point should remain stable under all circumstance
Q-point shifts on DC Load Line (DCLL) towards satura

r:r Following are the reasons due to which Q

point shifts
following points should be taken care of.
s. Unfortunately this doesn't happen.
tion or cutoff region and we get distorted output. -
ri •

Variation in device parameters.

This happens when one BIT is replaced
with BIT of same type. (e.g. f3 changes
from one BJT to other)
Due to increase in temperature Ico doubles for every 10°C increase
V8 E decreases by 2.5 mV/°C and 18 increases.
f3 increase.
equation) increasing with temperature, le increases
Since le = f3 I8 + (1 + f3) leo· With all parameters (in
to enter in thermal runaway.
and Q point shift to-:vards saturation. This also causes BIT

1. Variation in device parameter

parameters don't remain same, but they vary.
If we pickup two transistors of same code number, there
e.g. In data sheet, ~ of BJT BC l 47 A is given as
,·,
Poc
Minimum :TYJlical Maximum
Jl5 180 220

um and maximum.
transistors is replaced with other, f3 will vary between minim.
It means due to any reason I'f one tion or cutoff.
• change ('f
. , le will · kept constant) and Q point.will either go towards satura
1 I8 1s
As f3oc vanes
. . .
This will cause clipping and distortion in output signal. tor 1s rare.
· ally not taken into account because failure of transis
Variation in device parameter is norm

2. Variation in temperature
, y eE and t3 of BJT changes. This causes shift in Q-point.
. , Iceo or -co•
As temperature vanes

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" ' Analog Electronics (MU-Sem.3-Electrical) 2-30

Bipolar Junction T ~ ° '
(a) Increase In lceo with temperat ure and thermal runaway

r -- - -- - - -- - --~ .----- - --- -- -- --,

,
- - - - - - - - - - -...!
Temperature
further rncrease
: f . Process t>e:oomea : ,;:•
r - - - _,,
I
·
. ,. -nerative or ..•. ,.L
·-- ,I
- - - - - - -I
, ._..________ ____ ___ • I
I I I , ,, c;:umulative ' "'· ' I

As temperature Number of I
Increases minority carriers
in Base increases
(BJT)'
Device enters In
Power THERMAL RUNAWAY
dissipation is
in tenns of heat I Iceo or Ico increases ·1
. - - - - - __ .J_ - - - - - . I I
:: ..As lea increases ;· : ·: lcEo = ( 1 + PX 1ceol

~'°+-·~
, power dissipation in ,
:, BJT Pr= lea Vcea :
l~ · inaeases __· .:i'.I
I ·· ___________

• 1.
·: le = Pie + 1ceo

Output signal
gets distorted
Q-point shifts towards saturation

(1C46) Fig. 2.18.1 : Thermal Runaway

(b) Decrease in V 8 E with increase in Temperature

This causes Q-point to shift towards saturation.
VBE of transistor is nothing but voltage across fo·rward (c) Increase in pas temperature increases
biased base emitter junction (J8 s). As temperature T
It can be seen from Fig. 2.18.3 that as temperature
increases, V BE decreases by 2.5 mV per °C.
increases, 13 increases with I 8 Q constant, ICQ will
In the circuit shown, applying KVL in B-loop we get,
increase. This will shift Q point towards saturation.
VBB - VBE
IBQ = Rs
... (2.18.1) As it can be seen from (a), (b) and (c), that increase in
temperature causes Ico and 13 to increase, while Vse
and IcQ = . 13 I8 Q ... (2.18.2)
decreases.
:. From Equations (2.18.l) and (2.18.2) as T increases,
Also we can conclude that effect of all these parameter
V BE decreases, I8 Q increases .·. IcQ increases.

1ca
is additive in nature i.e. all are responsible to cause
increase in 1c ; hence Q point shifts towards saturation,
C
as shown in Fig. 2.18.4.

E +

Vee

(100)Fig. 2.18.2

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;
-, -1
I
2-31 Bipolar Junction Transistor

I
··-· I

As
temperature ~
Ina-eases
I.
~Increases 1ea

10 i 100
'ifee 1
I
;, .... _ ...... ;. .. .... .l .. . .J . l . .. L•• - .J.. .. ..... 1

(tC41)Fig. 2.18.3: Variation in Pwith temperature for a (tC49) Fig. 2.18.4

typical Ge BJT
: ' .- ,/ _,, , . . . ----------------------- --------.-----.-----~.:.::':-----------:--~- 0.-:;•:-.:~~
,GQ. Draw circuit diagram of a conventional common emitter (CE) amplifier .with waveforms at different ·noctes. ·Exptatn·,
, . function of com~o~ents use<Hn circuit. _ · · ·_- .. ' ,. , ' .:
·----------------------------~--------------------------------------· ~~--- -- ----- ·---

DC voltage I vb
O
,v1
v,
t
Re

E
C

0
v~v F\. v ~ v o
T
Veal 0
(Load
Resistor) t
t

_j_
Source Amplifier Load
(tC50) Fig. 2.18.5

Source ➔ It can be a signal generator or previous

B' Ce2 (output Coupling capacitor)
amplifier where ~ is equivalent output
resistance seen from its output terminal known This is connected to block any DC component coming
as Source Resistance ~). from amplifier (V CQ)
load ➔ It can be a speaker or next amplifier working as ~ Re {DC load)
load. ~ is equivalent input resistance of load.
It is used to convert output current into output voltage
q- Cc1(1nput coupling capacitor) so that circuit works as voltage amplifier.
It also controls ~ and VCQ·
This is connected to block any DC component coming
from source. If Cc, is. not connected then the DC voltage S' R8 (Blasing resistance)
corning from source will change biasing condition of
To control l 8 Q and VBQ , so that BIT is in forward -
amplifier. This will shift Q point on DC load line and cause active region.
distortion at output.

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r
liJ Analog Electronics (MU-Sem.3-Electrical) 2-32 Bipolar Junction Transistor

I 2.19 STABILITY FACTOR

,----- I

:Go. Define stability factor. Derive the equation for stability! ··s-~
. - a1co
factor. State which biasing technique is more stable.:
I
Justify your answer. - ... (2.19.3)
I
:Go. What is stability factor? Why it is defined?
:ao. Define different stability factors.
, _________________________________________ J,

There are different biasi~g circuits to keep Q point ~ 2.19.1 Steps to Find Stability Factor of
stable on DC load line in active region. any Biasing Circuit
Stability factor is a parameter which decides to
Step 1: Apply KVL in B loop
what extent a biasing method is successful to keep Q
point stable. Step 2: Write equation for Is
Change in Ic is function of change in Ico, VBE and ~-
Step 3:
. (ais)
Differentiate w.r.t. le to get dlc
This can be mathematically written as
Mc = f ( Ico • V BE • ~ ) dIB)
Step 4: Finally put ( die in equation (I) to get
This equation can be expanded by using Taylor' s series
as total change in collector current ( Ic ) stability factor.
i.e. Mc can be given as,
~ 2.19.2 Biasing of Amplifiers
die dic dic
~Ic = ~ X ~o + ~ X ~ VBE+ a'A X ~~
CO BE ~ :aa.
I
What is biasing ? Why do we need biasing In e.rri '

... (2.19. 1) amplifiers ? or What are functions of biasing circuit ? .:

I
From Equation (2.19. l) we can define three stability :Ga. Explain need of biasing in BJT. 1

I
factors. I
(MU - a. 1 c , Ma 14, a. 1 d , Dec. 14, 5 Marks)
'----- -- -- - --------------------------- · • __ 1

~ Biasing
.s1 = S=
aZ: /•v.......,., = s'co ; The process of applying desired DC voltage at different

die I
terminal (E, B, C) and establishing desired DC current in
Sv = s' =
dV BE ~
Afcoand =0 different leads of BJT is known as Biasing. For doing
biasing, we use a set of R, C and DC po_:-ver supplies.

S1:1 = s" = "lei

a13 Afcoand,WBE=O
~ Function of biasing or need for biasing

(1) To make JsE forward biased and J 8 c reverse biased.

Variation in Ic due to change in Ico is very large This is desired to·operate BIT in active region.
(compared to change in le due to VsE and /3). Hence
(2) The established voltage is known as V CEQ and current
nonnally stability factor is defined as S or S1•
as leQ- These, current and voltage, are called Quiescent
~ General formula for stability factor (S1 or S) values, which detennine operating point or Q-point for
the transistor.
leo +....JLI (3) Toe circuit consisting of R, C and power supplies to get
le= I-a 1-a s
desired Q point is known as Bi~ing Circuit or
le = (l + P)lco + pIs ...(2.19.2)
Biasing Network.
I a
··· t+A=-and-=P
,., I-a I-a (4) The Q-point shifts or drifts.
(a) When one transistor is replaced by other.
Differentiating Equation (2.19.2) w .r.t. le we get,
- - - - - - ---=:--~-:---:---:--:---.::-::-----___;_---------~-=
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!'1 Analog Electronics (MU-Sem.3-Electrical) 2-33 Bipolar Junction Transistor

(b) When there is change in IcQ due to change in ► Step 3 : Calculation for IcQ and V cEQ
temperature. Tttis is because.
To find l 8 Q:
(i) lco doubles for every 10°C change in
temperature. Apply KVL in base loop (Fig. 2.20.3).

(ii) VeE decreases with 2.5 mV/°C rate. Vcc - IeQ Re - V BE = 0

Ycc-VeE
(iii) 13 increases with temperature. IeQ = Re
It is the ~nction of biasing circuit to keep Q-point
stable agamst variation in all parameters i.e. Ico or lceo,
V8 E and l3. Re Re
+ +
J 2.20 DIFFERENT BIASING METHODS - Vee

---------------------
I E
:Ga, Write a short note on stability factors of various:I
: biasing techniques of BJT:
I

:ua. Explain Different bi~slng techniques in BJT. (1C52) Fig. 2.20.2

(MU - 0. 2(b), Ma 18, 10 Marks
----------------- - - - ---------- - -- - ------- I Since V BE << Vcc
Different biasing methods are as follows Vee Fixed
1eQ = R8 = Fixed
I. Fixed Bias
2. Fixed bias with self bias or Emitter feedback bias Hence the name of biasing is fixed bias.
3. Collector to Base Bias and ICQ = Pl 8 Q , IEQ = IcQ + I 8 Q
4. Collector to Base Bias with Self Bias or Emitter Bias To find VCEQ :

5. Potential divider biasing with emitter bias

Apply KVL in Collector loop (Fig. 2.20.3).
~ 2.20.1 Fixed Bias :. Ycc- IcQ Rc-VcEQ = 0
.------ ---- ~------ ------- ------- ------- - --, VCEQ = Vcc-IcQ Rc
:Ga. Draw circuit diagram of CE amplifier with Fixed Bias.:
Find Q point. Draw DCBL and DCLL. Finally find: Q Point is (VCEQ• lcQ) ·
: ► Step 4 : Phase relationship between v; and v0
·- -- ------- - --- ---- -- ---- - -- - - --- _,_---- ..,
, stability factors. ,
' ., .,.
As V; increases, i8 increases, :. ic = 13 i 8 increases.
► Step 1 : Circuit diagram (Refer Fig. 2.20.1)
► Step 2 : DC analysis Hence Vcc =vO =Vcc - ic Re decreases.
Refer Fig. 2.20.2 and 2.20.3. To find Q point we have It means as v; increases, vO decreases .
to perform DC analysis. For that we have to draw DC Therefore in CE configuration, input and output
equivalent circuit by opening all capacitor s, and connecting
voltages are out of phase.
DC power supplies with proper polarity.
► Step 5 : DC Bias Line (DCBL)
Apply KVL in base loop and write it in' the form of
equation of a line (to be ~ rawn on input character istics)

(ICSl)Fig. 2.20.1 : Fixed Bias

Authors impire i11110.-ation .....A SACHIN Sl/,4// J'eature

--L N
Tcco- eo Publ'1can·om-......... "'
mr..ere
8
 ~ Analog Electronics (MU-Sem.3-Electrical) 2-34
Bipolar Junction Transistor
...
Find two points to draw DCLL
lea
with le =O , VcE =Vcc

111 + ,----, Vee.

and with VCE=0, le=~
I

lea+Rs - e
C •I
I
I
I
I
:. Two points for DCLL will be (Vcc.• 0)

~
I +
I
Vee ~) ith slope (- ) . Refer DCLL in
c··----,,,Yee -
+
e
I
I
I
and ( O , Re w '''C

,
I
+ I

Vee - :_ __ _______
I '1
, __ .,.II Fig. 2.20.5
L-----Base
-----4~ ----'r-- ► Step 7: Stability factor 'S'
loop Collector
'¥° Following steps given in section 2.19. l.
Loop
Apply KVL in b~ loop and differentia te it w.r.t. Ic.

:jl FT t7.,:v,j
(tcs.1) Fig. 2.20.3

Vcc - le
· (
Rs - V BE = 0 ,~~ (t )·-t
le= -RsI ) Vee
VeE+ Rs ; y= m x+c Vee . 1 • ' i •
- - · · Slope=- - - l ' 1 !
Find two points to draw DCBL . Re Re ······,,' ········1!
f· ···1' .. ... .. i , 1'

with 18 =0 , V BE =V cc and I
... r .. f. ................. ,
'
Vee 'ca DCLL •·1 ··· ···· I
with VBE = 0 , le = Re
., ·-r···· I
:. Two points for DCBL will be (Vcc., 0) !
j
I I

and ( 0 , ~~) with slope (- ~ ) . Vceal . ,i Vee .. I. . . J. ~.c::1:~~l. . .

Refer DCBL fo Fig. 2.20.4. (tC55) Fig. 2.20.S
,•-r• , ._ ., ~"--••- • ---~- I - Vcc - le Re - V BE = 0
p e(~ ). __ ; -:---; !-- :J lg vis Vee j~-- --, a le

L~ i- (,.,,, ,

i.
.

: ! I ; -·<-:- ' '

o- a1c Re - o =

= 0
o

... (2.20.l)
). -) . -- . : ' ' :~--~-- ,;-'---+--
r· · ;ea- _,_
i s_lope "Rs
_._ .-..._- ......._......,-_-•·~·-_···-_···_···-_-:_.,._-,_:
Putting Equation (2.20. l) in formula

1····-:.r· · -· · , i : i . l + f3
s =
al 8
f ~ ! l
i---·1···
i .•. _t - _j _ _ _,_,
I- f3 ale
We get. stability factor for fixed biasing as,! S = l + ~
(1C54) Fig. 2.20.4

► Step 6: DC Load Line (DCLL)

Apply IO/L in collector loop (Fig. 2.20.3) and write it
in the fonn of eQUation of line (to be draw~ on output c:r Disadvantages of fixed blaa
characteristics). ,,.
(i) LOGICAL LY if we see equation for "S" of fixed bias
Vcc-IcRc -VcE = 0
a1c
a1co
le = (-~)vce + ~c
S= = (1 + f3). If f3 varies from 20 to 300 then the

stability factor S varies from 21 to 301 ............OMG.

y = m X + C
'1
- Analog Electronics (MU-Sem.3-Electrical)

"S" should be as low as possible. In this case with such .

a high value of 'S' , stability of Q-point will be poor. In
2-35

a.
Bipolar Junction Transistor

2.20.2 Fixed bias with Self Blas or Emitter

Feedback Bias
other words, a slight change in temperature will cause
large change in le- This will result in thermal runaway (a) Circuit diagram (Refer Fig. 2.20.7)

till transistor gets damaged.

(ii) MATHEMATICALLY,
Re
I,,, = ~[ v~v.,]" ~x~
This equation indicates that, if transistor of amplifier is
replaced with different P, the Q point will drift.
(iii) PHYSICALLY if we see, as temperature will increase,
leakage current (lco) from base to collector will (1C57) Fig. 2.20.7
increase, this will increase le- The power dissipation in
(b) DC analysis : To do de analysis, open all caps and
collector in terms of heat will increase . This will further
short ac sources.
increase le- This process becomes regenerative and
Apply KVL in base loop
BJT enters lo thermal runaway.
Ycc - leQ Re - YBE - ~ + leQ) RE = 0
(iv) If we study equations
Putting lcQ = Pc1c leQ
are
a1e = Q Or ale = 0 X a1c Ycc - leQ Re - YeE - leQ (1 + P) RE= 0
Y cc - 18 Q [R8 + (1 + P) RJ - Y88 = 0
then it will be clear that if le increases due to any
reason the change in 18 is zero. Yee-Yee
.. IeQ =
Re+ (1 +P) RE
Therefore corrective step to reduce le is absent. Hence
stability is poor.
Find lcQ• ieQ IcQ = Poe leQ
This becomes regenerative
/ and leads to thermal runway
lEQ = leQ + lcQ

Apply KYL in collector loop

Ycc - lcQRc-YCEQ-IEQRE = 0
rlY
_c_EQ
__=_ Y_c_c __ _lc_Q_Rc_-_l_EQ_R_~...,

(c) DC Bias Line (DCBL)

Apply KVL in base loop, write it in the fonn of
equation of line.
Ycc - le Re - Yee - Oe + le) Re = 0
le = Ple
(1CII) Fig. 2.20.6 : Fixed bias circuit leads to thermal Y cc - le [ Re + (1 + P) Re J- Y BE = 0
runaway of transistor Assuming l + p ~ p
(v) PICTORALLY, above point of thennal runaway is Y cc - Is [ Re + PRe J - Y BE = 0
clear from Fig. 2.20.6.
le= (- Re+lPRe) YeB+ Re:;Re
~Ly--1 ~
y = m x + C

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 Analog Electronic s (MU-Sem .3-Electrlcal) 2-36 Bipolar Junction Transistor

r-
1ea 1ca

I
+
I
I Ra C-loop
I I
I
I
I I y = m X + C
I
I

~
•
I
I
I Now to draw DCLL we require two points.
I + I
Y.cc
+
Vee
I
I
I
I +
Let, V cE = 0 , .. le = Rc+RE
I : - Vee
I I

Yee =
I
I
I
I
I le = 0 Yee
I
4I f i
1:____ . . , __ _ _ :1EQ jl0(7"1A)
I
,_,! ••~N•n• •

·~-1, I~ v/s Vee !-•- --'.

f .,.,,_} .•• 1
8 -loop 1ea = 1ea + 1ca
.j . .. !..
(Ve~
(tC58) Fig. 2.20.8 !
Rc•~e i DCLL
1-- r .,'.
Refer Fig. 2.20.8. . ~

Now to draw DCBL we require two points.

. ..! '
;
Let, V8E = 0,
1ca
Yee

' j ... j J Vcc VceM

.L V~ec(

YeE = Vee (tC&O)Fig. 2.20.10

Two points for DCBL will be (Vcc, 0) and
Two points to draw DCLL are,

Re ~ RE
( 0, Rs:rRE ) with slope ( Rs+ lf3 Re )
(V CC• 0) and ( 0, Re~c t ) with slope ( - )

(e) Stability factor

Ra+ PRe Refer circuit in Fig. 2.20.7 . Apply KVL in base loop.
Vcc - Is Rs - VBE - le Re - Is Re = 0
, . ·•~f- •••-
,
I
.. . ... ,........ ,.........,......... , ....
- (ea- pe-
(Vcc - VBE) - le (Re + RE) - le RE = 0
·····
Different iating this w.r.t. Ic-
. ;

_l~. .......,....,,...,~ . .-.. ais

arc (Ra + Re) - RE = 0
<

0 -
i ; Vee(V) .
..L -~-, C ·•~n,,: .. ,,._-.,,.,,
dls Re
(tcss1Fig. 2.20.9 arc = Re + Rs - - k ... (2.20.2)

(d) DC Load Line (DCLL) Putting this in general formula for S.

Apply KVL in collector loop. Write it in the form of ( l + 13)
equation of Line.
We get, s =
RE
le Re - l+J3R
Vcc - VcE- (le + 1s) Re = O e+ R B

Using 18 = i and I + J3 ~ 13 =

Vcc - le [ Re + RE ] - VCE = O

- - ------ :=---: --:---: -~---- :---=::-::---------------.-._.,4li.£441C,i'HINOOSJl,4/IOOii~

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 ~ Analog Elect ronics (MU-S em.3- Elect rical) 2-37 Bipol ar Junct ion Trans istor

(I' Advantages
,--- -- - - - - -- - - - - -- - - --
or self:
:Go. Write advantaQ9s of fixed bias with emitter bias
bias. ____ ____ ____ ____ ____ ____ ____ ____ _ J•I I
I

I
____ ____ I
l
\

'
for self bias
(i) L~IC ALL Y if we see equat ions of 'S' Rising IMde ocyJ - - - -- _ __,,
in comp ariso n with fixed bias, they are is checked

1+13 1+13 Fig. 2.20.1 2 : Stabi lity in Q point due to chan

ge in
13
f2il
(1CS2J
S =I+ and S RE - x respectively temp eratu re
l+l3 R E+ RB

Wher e x is > I . It mean s •S' for self bias is small

that of fixed bias. There fore good stability of
comp ared Lo fixed bi as.
er than
Q point,
Rising tendency \
is checke d ~ ,/
I
l

''
'
__ _
-
(2.20.1) for
(ii) MA TIIEMA Tl CALLY from equat ion
self bias
ole - Re Fig. 2.20.13 : Stabi lity in Q-po int due to varia
tion in
:i1 = RH + RII - - k or Ole = - k die (1C63)
Q e j3 when one transistor is replaced by other
that as le
Nega tive sign in the equat ion indica tes
~ Drawback of self bias
eter or in
increases due to variat ion in devic e param
le to bring For self bias stability facLOr is given as,
tempe rature , 18 decre ases. This will decre ase
Q point to origin al positi on appro ximat ely .
Therefore (1 +~ ...(2.20 .3)
S = ( I + 13)
stabil ity ofQ point incre ases .
(I +13)+(~)
(Iii) PHYSICALLY the impro veme nt m stability of
differ ent
Q point can expla ined referr ing Fig. 2.20. 11 . Also practical ly if we plot a graph of S for
se in lco,
As T incre ases, Ico incre ases, with increa values of(~ ) we get the graph as shown in Fig.
2.20.10.
across
leo = (leo + 180 ) incre ases, i.e. drop
ses emitt er voltag e
RE ( = Ieo R 6 ) incre ases. This increa s i
rd bias.
V EQ• whic h make s le e to becom e less forwa . ····j.
.l

chang e in leo or
This decreases 18 and le- This keeps ~ - - P=: 100

drift in Q point as small .as possi ble. , ~ - - - P=40

(iv) PICTORIA LY, repre senta tion of impro veme nt in ~ - - - P=10

rature
stabil ity of Q point again st variations in tempe
and devic e param eter (chan ge in 13) when transi
stor is

repla ced can be show n as follow s .

(1CM)Fig. 2.20.1 4
as low as
For better stability of Q point. "S" shoul d be
Equat ion (2.20 .3) and graph in
possible. Study of
¾:) shoul d be
Fig. 2.20. 14 indicates that for "S" to be low(
- Vee
~ as low as possible.
1sa

11001Fig. 2.20.11

ntioa ""...4 SACH/NSP J n u

nAn ,enture
Tedi-Neo Publications---···· Here Aut/Jon inspire U11JO
 lil Analog Electronics (MU-Sem.3-Electrical) 2-38 Bipolar Junction Tra~

To make (t) very low, either Rs should be as low as CE works as open circuit for DC. Hence, DC ncgatj~
feedback is present (Refer Fig. 2.20.17).
possible or Rt; should be as high as possible. In both cases But the same capacitor (CJ works as sbon for ac.
we face following problems. (Refer Fig. 2.20.18).
H RE is high, larger collector supply voltage (Vcc> is
needed. This will increase input power to amplifier.
Finally power efficiency will decrease.
Also if Rt; is high, drop across it will increases, which B

will provide more negative feedback. More negative

f~back will reduce voltage gain of circuit
H R 8 is low, a separate base supply voltage is required
which will make circuit complicated and also not
feasible. '
ProYiding DC negative feedbadt
For DC

B" Concept of negative Feedback In self Blas (1 C86)Fig. 2.20.16 (1C81) Fig. 2.20.17

In self bias (due to increase in temperature), as ~

C
(output current) increases, presence of R E causes I (input
80
current) to decrease. In other words increase in output
parameter (lcQ) is causing decrease in input parameter ([ll ). E
0
In any system this is poss ib le only if there ex ists negative
Re short Re short
feedback from outpu t to inpu t. It means in self bias there
exists negative feedbac k. This negative feedback is present
due to presence of RE. For AC

(IOO)Fig. 2.20.18

Therefore A C negative feedbac k is avoided. Hence

1sa 1ca
presence of Ci:: keep Q -poln t stable without decrease In
(Input (Output
current) Amptifier with current) gain.
self bias
r ...____
Feedback
..,V,.FV" \.r-----
a 2.20.3 Collect or to Base Blas
RE
(Providing feed back)
,--- ----- --------- ---- --------- -------~- ~~,
;GO. Draw circuit diagram of CE amplifier with Collector 191
(1C15)Fig. 2.20.15: Negative feedback via RE Base (C-8) bias. Find Q-polnt. Draw Its OCBL and;
,I _ _ _ _ _DCLL.
_ __ _ _ __ _ _ _ ________ ___ ____ _ _ _ ___ _ ____ ·:j
Hence, in self bias, RE provides DC negati ve
feedback to keep Q-point stable.
.
(a) Circuit diagram
·------~------------ - - ------- -- ------- --
I
I Refer Fig. 2.20.19. In this type of biasing the base
•UQ. .. What is .the function of Bypass capacitor Ce in CE•
I · I resistance Ra is connected to collector instead of V ~-
, ampllfter ?
·~----------------- ----------- --------- ---~: (b) DC analysis
.., Use of Bypass Capacitor (CJ

In self bias DC negative feedback by Rt; is des~le for Refer Fig. 2.20.20. To perform DC analysis, draw DC
stability. But when ac signal (to be amplified) is applied at equivalent circuit by opening all capacitors and showing
input, RE also provides ac negative reedback. This is -not supply voltage with proper polarity.
desirable beca'™: it reduces voltage gain (Av). To overcome To find Q point. Apply KVL in B loop.
this, a bypass capacitor CE is connected across Rt;. (Refer
Fig. 2.20. 16)

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.._.A SACHINSll4ll r.-
'1 AnaJog Electronics (MU-Sem.3-Electrical) 2-39 Bipolar Junction Transistor

•Vee Vcc - 0c + le) Re - le Re - VBE = 0

Vcc - le (1 + P) Re - le Re - VBE = 0
Vex: - Vec le [ Re + (1 + P) Re ] = 0

R. Ce1 CC2
T -- - -
Is I Vee v/s le J· -.
I\ Vo
vi Vee

l Re (1 +fl)+Rg

ra
Module
- - Isa

(1CMA)Fig. 2.20.19 Vee Vee

Replace lco = ~ 180 , also Let, () + ~) =~- (1C70)Fig. 2.20.21

Re - Ia R11 - Vet
Vcc - (le + Ia) = 0
le= (- Re +( /+P)Rc) Yes +
Vex: - lo (I + P) Re - Io Ro - VBE = 0 \. __1 y
Vcc - le [ RB + ( I + f3) Re] - YeE = 0 y
y = m X + C
Vcc- V ■ E
) IQ = To draw DCBL fi nd two points
R1 + (l + P) Re
With 10 = 0, V8 E = Yee
ICQ = p )IQ I and IEQ = ~ + IBQ .
and with V8 E = 0, 18 -
Yee
Re + (I + P) Re
Now Apply KVL in C-loop
:. Two points to draw DCBL are (Vcc, 0) and
Vcc - (le + lo) Re- - Vcr:0 =0
1.-. V CltQ = V cc - (le + I.,) Re (o. R9+(~:tnd withslope ( Ro+Ol+P)Rc)

---------------
- ~- ------,
I
:------~
- I
+ ',
(d) DC load line (DCLL)

i
I
I I I I Refer Fig. 2.20.22. To draw DC load line apply KVL in
I I Re I

t ~ ____ ..,. ___ ,

I
I t C-loop. Write equation in terms of le and VCE with proper
I
I
I
I
I le• lc substitution. Finally write equation in terms of line.
I
I
I le - Re I
I
I
+ I
.. 'T . . ,..
,♦
I I
I

I
I

J
I
I
+ I +'I
I
I
I
le Vee (V)v/a lc(mA)
I
Vee I
I
- ;" Vee
I
I
I
i
I le
VCE.
•
I
I
I
I

t
I
I
I

: Vee -
+
l_
I
I
I
I
I
I
I
I
i
I.. ···t.
I
I ·----~-, I I
I
I
------------ I
------- -) __ J
C-o,p
8-IOOP
lea
(1C11B)Fig. 2.20.20

Q point is (VCliQ• ~)

(c) DC Bia• llne

Refer Fig. 2.20.21. Apply KVL in B-loop. Write
equation in terms of 18 and VeE· Write it in the form of (1C71A)Flg. 2.20.22

equation of line.
---4 s.4CHJNSll4JI Ye11ture
r ~ Analog Electronics (MU-Sem.3-Electrical ) 2-40 Bipolar Junction Transistor

Y cc - Cle + Ia) Re - Y cE = 0 I + f3
s
,l where x > I
I = X
· · .(2.20.5)
Yee -(le+ ~)Rc-YcE = 0
Therefore, compared to fixed bias, 'S' is reduced
Hence stability of Q point is improved.
Yee-Ice ;f3)Rc-YCE = 0 (2) MA THEMATICALLY from Equation (2.20.5),
Let I + f3 = f3 010
= - Re = - k :. ol 8 = - k x oic
y cc - le Re- y CE = 0 ale Re+ Ra
Toe negative sign indicates that as le increases (due lo
:. le = ( -Re
I )
YCE+
Yee
Re temperature), 18 decreases, which then decreases ~
To find two points to draw DCLL Like this. le comes to approximate original value
Let le = 0, :. Q point remains stable.
: . VCE = Yee (3) PHYSICALLY the Q point remains stable as follows :
and with Y CE = 0, If Ico increases due to either increase in temperature or
change of transistor then (ICQ + l 80) increases.
Yee
le = Re Therefore V CEO decreases because

Therefore two points for DCLL are YcEQ = Ycc - Re (ICQ + Iuo).
~
( 0, ~:c) and (V cc, 0) and slope ( - ~ ) Since 180 =
Y c EQ - Vll ll
Ru = RH
V CEQ

(e) Stability factor (S) l 80 will also decrease.

Thi s decrease in l 80 will compensate for the original
To find stability factor apply KVL in 8-loop, write in
increase in lco· Hence drift in Q point is less. IL~
terms of Ia and le, differentiate it w.r.t. to le to get
stability is improved.
(o Ia Io Ic)-
(4) PICTORIALLY the improvement in stability factor in
y cc - le Re - Ia CRc + Ra) - Y BE = 0
collector to base bias can be shown as shown as in
Differentiating w.r.L le we get,
Fig. 2.20.23 .
o I8
0- Re - al (Re + R 8 ) - 0 = 0
C
o18 Re
o1c = Rc+Re =-K .. .(2.20.4)

Putting Equation (2.20.4 )_ in standard equation for ''

' ',
stability factor. We get,

s =
1+6
=~
X
where x > I
Rising tendency
is checked here
J
(1CHJ Fig. 2.20.23 : Collector to base bias circuit checks
,-~-- - " '.:.... -. ----- -------------- , the rising tendency of collector current
:Ga. · W~e advantages and disadvanta.Qf1t5 ~r frmitations ot: rr 'Disadvantages or !Imitations
~ · ooltector to base bias: .. -_ . :
' - - · - - - - - · - - - - - - - - - - - - - - - - - - - - -- - - - - - · - - - - - - ~- J
(1) From Equation (2.20.5) of 'S' we see that for •s· to be
r:r Advantages R
low or stability of Q point to be high, ~ should be
(l) LOGICALLY if we see equation for 'S' of collector to
base bias, very small; for this Re should be high. If this is the
(1 + fl) 1 +(Ra/ Re) case, then this biasing can't be used for transformer
s = Re = (l + f3) (I +fl)+ CRalRc) coupled amplifier, where in place of Re we have

1 +f3Rc+Ra primary winding Fig. 2.20.24 with very low de

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['1 Analog Electronics (MU-Sem.3-Electrical) 2-41 Bipolar Junction Transistor

resistance. This will increase stability factor and will

detoriate stability.
C
(2) Since R 8 is connected between input and output
terminals, it provides ac negative feedback. This B
E
RcllRa1
negative feedback decreases gain of amplifier. Ra2
+Vee

(1C74) Fig. 2.20.27 : ac equivalent

As shown in Fig. 2.20.25. the amplified ac signal at

point I, (i.e. output) is fed back and provides ac
negative feedback. This ac negative feedback reduces
ac voltage gain of amplifier. This is not desirable.
B
E To overcome this as shown in Fig. 2.20.26, resistance
R8 is di vided in two parts, R 81 and Re2·
(1CH1) Fig. 2.20.24 8
( Normall y RB1 = RB2 = ~ ) . An ad~itional capacitor
(3) Normally the value of Rll used in coll ector to base bias
CB is added as shown .
is of small value compared to fix ed bias or emi tter bias.
With capac ito r C8 , the amplified signal at point I (i.e.
Therefore in collector to base bi as . base current
ou tput tenninal) wi ll reach to point 3 via R 81 and will
changes more with temperature. Hence the advantage
get bypassed through capac itor Cu-
of better stability factor offered by C to B bias is
Hence ac signal at output wi ll not reach at input i.e.
offset by larger variation in base currenL
,- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . point 2. Therefore ac negative feedback will be
:ao.
I
How do we avoid AC negative feedback in collector 10:
I avoided . C 8 is selected such that, for operating
: base bias to Increase AC gain ? ,
-------- ------------------ ---------------- frequency it works as short.
rr Drawbacks of above scheme of biasing are as
follows:
(Refer ac equivalent circuit in Fig. 2.20.27)
1. R8 2 will reduce input resistance of amplifier. Hence
amplifier with load source.
2. Re 1 will come in parallel with RL, this will reduce load
resistance of amplifier. Hence amplifier will get loaded
which will reduce voltage gain.

(1C72)Fig. 2.20.25
a 2.20.4 Collector to Base Bias with Self
Bias or Emitter Bias
.-----------------------------------------,
!GQ.
I
Draw circuit diagram of C to B bias with ,self.. bias. Find!I
• its a point. Derive equa\f"
for s1abillty factor· •s·.:
Draw DCBL and DCLL. !
•-----------------------------------------~
(a) Circuit diagram (Refer Fig. 2.20.28)
(b) DC analysis
To find Q point, we will have to draw DC equivalent
circuit for which open all capacitors. With CE open, RE
will remain between E and GND. With Ce open, R 81
and R82 will be in series.
(1C73l Fig. 2.20.26

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 ~ Analog Electronics (MU-Sem.3-Electrical) 2-42 Bipolar Junction Transistor

Let R 81 + R 82 = R 8 . Therefore the equivalent circuit Refer Fig. 2.20.30. Apply KVL in base loop. Write it in
will be as in Fig. 2.20.29. terms of 18 _an_d V BE convert it in the form of line

To calculate Iai, we will apply KVL in B-loop. equation y = mx + c.

V cc - V BE - (le + 18 )(Rc + RE) - 18 R8 = 0 or

V cc - Oc + le) (Re + RJ - le Re - V BE = 0

(Vcc - V BE) - (1 + f3)1e (Re + RE) - le Re = 0

Vcc - (1 + P) 18 (Re + RE) - 18 R 8 - V BE = 0
Vcc - 18 [ (1 + f3)(Rc + RJ + R8 ] - V BE = 0
._. le = p le 1 V
+Vee
.-., le = - Re+ (1 + P) (Re+ RJ BE

c~1
Re1 Re2 + Re + (1 + f3)(Rc + RE)
1\ Now to find two points for DCBL
.Ce Let le= 0, then V8 E = V cc
Ce1

r
V1
2 B Vo
Let V8 E= 0, -then
·•· ..•1···~--~,--·····
le - Re+ (1 + P) (Re+ RJ

(1C75)Fig. 2.20.28
'
.. ! le(µA) _,1.,, ..,,•,,,,, .. , .. ,, ....,
f
,,,,. ;,,,,_l--.,--+--;-- 1•·-·
Vee If · r-1
· - r- - -4

P) (Re + RJ + Re] = 0
• I

(Vcc - V eJ - 18 [( 1+ ... (2.20.6)

Re +(1 + II) (Re+ Re)i

!· !····!· ++,,-1
_I
i VeeM I
. ••· . ···•----- ~-.. -.!
lco = Pleo I (1C77) Fig. 2.20.30
To find V CEQ apply KVL in collector loop.
:. Two points, on input characteristics, for DCBL are :
Vcc - VcE - (le + le) (Re + RJ = 0

I .-. VCEQ = Vcc - (Ic + le) (Re + RJ ( 0, Re + ( I +;~c(Rc + RE)) and (Vcc, 0) with slope

(c) DC bias line ( Re + (1 + ;)(Re + RE))

...-----------------------,
. , ~ ..\ :
,-----~---------,

t ,:• ♦

Re · :
I
I !
T
I I
I
:
(d) DC Load Line
I I I I I
Refer Fig. 2.20.31 . Apply KVL in colJector loop. Write
: ,----------~.,• - : : :
: : le - Ra + le+ I~= le : : with V CE and le as parameter convert it in the fonn of
: ·: I : :
I I : I I y =mx :+-C.
: : I ♦ I
=
Vee
+
1 ½ c + ~ -~ Vee
Vcc - (le + le) (Re + RJ - VCE 0

t •,'
I I
+B
Vee :I
I
'
:
I
Vcc-(Ic+ i)<Rc+RE)-VCE = 0
, , Vee - : :
I:

(1 ; p) <Re
:, _________ _...,_, -+ E II II

I
I
I
I
I
I
I
I V cc - le + Rs) - V CE = 0
: : Re : :
I I ' ... _,._,
It p ·
'---~:---------' - _le+::~ Let-p-= I

.-. V cc - le (Re+ R 6 ) - V CE = 0
(1C71) Fig. 2.20.29

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 ,_
~ Analog Electronics (MU-Sem.3-Electrical) 2-43 Bipolar Junction Transistor

Hence both DC negative feedback try to keep Q point

more stable in centre of DC load line.

~ 2.20.5 Potential Divider Blasing with

Emitter Blas

(a) Circuit diagram

Refer Fig. 2.20.32. In this type of biasing R 1 and R2 (as
shown) works as potential divider, such that voltage at base
is enough to make JBE forward biased and keep Q-point in
1211
. . 1. . .

le
1 ..

(1cnA)
Veea:

= -
Vee

Fig. 2.20.31
1
Re + RE VCE+ Re + RE
Yee
centre of DCLL. Function of RE and CE same as explained
in emitter feedback biasing.

-
r
To find two points for DCLL,
Rs Cc1
Let VcE= 0 then
RL
Let le = 0 then V CE= V cc. Vo

L
V1
:. Two points to plot DCLL are R2 Ce

( 0, u V+ccR_l and (V cc, 0) with slope (- R I R )

\ ''C ;J C+ E 11cnsJFig. 2.20.32
(e) Stability factor 'S'
(b) DC analysis
Apply KVL in base loop. Write it in terms of le and IB.
(i) Exact de analysis (considering IBQ)
IB a
Differentiate w.r.t le to get le. Draw DC equivalent circuit by opening an capacitors
O
and showing DC sources with their polarity.
(V cc - V Bl!) - le (Re + RI!) - IB (Re + RB + RE) = 0
Let Ru, = RB and Vth= V (Refer Fig. 2.20.33)
Differentiating w.r.t le
By Thevenising circuit on LHS of BG we get.
d IB
o- <Re + RJ - ale <Re + RB + RJ = o Ru, = RB = R1 II R2 -
R2
0 IB and V th= V = R + R Vcc (using voltage division rule)
I 2
ale Replacing circuit on LHS of BG with thevenins
Putting it in standard equation of 'S' we get, equivalent circuit the circuit in Fig. 2.20.33, will become as
in Fig. 2.20.34.
t+ B C

(I> Advantage of C to B bias with E bias Re

Compared to collector to base bias, stability of Q point
G
is improved. This is because Vlh,Rit,
(a) There is DC negative feedback via R8 from out to input 11cnc,Fig. 2.20.33 ·
i.e. from C to B. Applying KVL in B-loop and replacing 1 with
8
(b) One more DC negative feedback via RE. (1 + f}) JB

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 lil'Analog Electronics (MU-Sem.3-Electrical)
we get,
V - IB RB - VBB - Is RE = 0
2-44
V - 18 [ R8 + (1 + 13) RE ] - Vee= 0
Writing in the form of y = mx + c
Bipolar Junction Transistor
-
V - VBB - IB [ RB + (1 + f3) RE 1= O
_ _-!..1--y + V
le = Re+ (1 + 13) RE BE Re+ (1 + 13) RE
V-VBE
... (2.20.7) Now to get two points for DCBL
V
= f3 leQ ... (2.20.8)
IEQ = ICQ + IeQ

Applying KVL in C-loop we get,

: · V cc - V CE - le Re - IE Rs = 0

V CEQ = V cc - ICQ Re - IEQ RE

VCEQ _ Vcc-ICQ<Rc+Rt:>

:. Q point is (V CEQ• lcQ).

le
,..__
I
I
I
I
C I (1cm)Fig. 2.20.35
lea Rtt,=Re 'e B :T
Vcea
I
I +
_Vee
+
,------,Ve - -=..L
I I
E
+
I
I
I
:. Two points to plot DBCL are (o, Re+ (lv+ l3) RE) and
, 1 le I
+ I I
I
I
I
I
I
I
I
(V, 0) with slope (-Re+ (l l+ l3) R)
,__
I I
'-~' (e) DC Load Line (DCLL)
Refer Fig. 2.20.36. Apply KVL in C-loop. Write it in
B-loop C-Ioop
terms of le and VCE convert it to represent equation of line.
(1CT7D)Fig. 2.20.34

(c) Appro~lmate DC analysls

In practice if PRE~ lOR2, then we can assume IBQ = 0.
, r r •.•. ·1· -· . . -i .• F :·r:·.;;: •.:·-.
······· , · •! · /•r! ··············L··
l
.. :
•1.•.•.·:.··.•·.•.·.·.:!:_1,•.·..•:.·.:.:.•.··.

I
:,1 : !.

In that case we don't have to thevenise circuit on LHS of , , .i

i ' .
1
Re + Re
·+1· .....1··i
Li
l - \
BG in Fig. 2.20.33. We can directly write,
R2 ; r · l I· 1
VBQ = R1 +~ Vee , VEQ 1
1•
1
Vee/ 18 constant!
=,,._.:llir---!-- +
'I - ': l
:

..
= VeQ-VBE
VEQ ~1. . . ·1. ~-1 + ··· '· 1L~Lli=jj
IEQ = leQ= RE
VCEQ = Vcc - leQ <Re + Rs)
c~~~r=-·
' l
l --··r · 1---·· . t-·· t· --i-• .
I ' • 1
I

·
'

+---!·---~
' '

f__ j ...... , .J · L ... · _J_ ~~EC:, ..... L..L .. L~~~--~9~-~>j

(d) DC bias fine (DCBL)
(1C77F)Fig. 2.20.36
Refer Fig. 2.20.35. Applying KVL in B-loop and Vcc - le Re- IE RE - VCE= 0
writing equation in terms of 18 and VBE·
V - 18 R8 - V BE - IE RE = 0 IE = ( pl+f3) le== le
V - 18 R8 - V BE - ( 1+ f3) 18 RE= 0 : · V cc - le (Re+ RE) - V CE= 0
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- Analog Electronics (MU-Sem.3-Electrical)

le -
_ (
Re + RE
1 ) Vee
VCE + Re + RE
2-45 Bipolar Junction Transistor

To find two points to draw DCLL

first Jet le= 0, this gives VCE= Vcc
. . Vee
then Jet VCE = 0, this gives, le - Re + RE a1B = -Kxolc ... (2.20.9)

:. Two points for DCLL will be Substituting this in standard formula for 'S' we get,
I+ 8
( O, Re:~j and (Vcc, 0) with slope ( Re ~ RJ s= RE Module

iil
l+l3R+RE 8
(f) Stablllty factor "S" .

For "S", apply KVL in B-loop. Write equation in terms (1 +~)

. .
of le and I8. Differentiate w.r.t. le to get (a~)
ale . = (I+ 13) x R
(I+ 13) +Ra
E
V - I8 R8 - VBE - le RE - 18 RE = 0
V - la (Ra + RE) - VBE - le RE = 0

J 2.21 DIFFERENT BIASING METHODS AT A GLANCE (COMPARISON)

I •' .<. ·, . I

•UQ.. .
, . __ .., .• Coin~re. _ • • ,~ _ _ _ _biasing
- -- - ·' ••. -different _ .~ - , _method
_ _ ·<- _ _ _ BJT.
of_ _ _______________________________________________ , _ _ _ _ _ _ _:
,,
. Parameters Fixed bias Fixed b•'with Rx Potential divider bias Collector to base bias
(FB) (FB .with Rg) (PD bias) (C to B bias) .

Circuit - - - - - +Vee - - - - - +Vee

diagram
Re
1ea 1ea

(1CII)
(1Cl5) (1Cl8) (1Cl7)

Base current Vcc-VaE Vee- VaE Vee- VaE

1aQ- R8 IaQ - Ra + (1 + 13) RE IaQ Ra + (1 + 13) RE IaQ Ra+ (1 + 13) Re
WhereR 8 = R8 WhereR8 = R8 Where R8 = R1 II R2 Where R8 = R 1 + R2
R,
V=VccX R +R
I 2

Q-point lv=~•BQ . ~=~IBQ lcQ = ~IBQ ~=~IBQ

(VCEQ,~) VCEQ=Vcc-~Rc VcEQ = Vee - lcQ Re VCBQ = Vee - ~ Re VCEQ
-IEQ RE -IEQ RE =Vee-Re~+ IaQ)
Where IEQ = ~ + 18 Q Where IEQ = ~ + I8 Q

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r
liJ Analog Electronics (MU-Sem.3-Electrical) 2-46 Bipolar Junction Transistor

Fixed bias with RK PotentJal divider bi~ CoDector to base:- bta.:.

Parame'ters· Fixed bias
(C to _B bias),

nc
(FB with R1 ) (PD bias)
(FD)

Stability factor S == ( I + ~)
~+~ j S- I
1+ ~ ~Re + RJ
~
S-
~
s I +p 8
- 1+ ~ (R Rj
(S)
: J+ R +
8 8

provides DC Rs provides DC
provides DC R8
Stability of S is very high. Slability R8 feedb ack.
S is negative feedback. S is negative
Q-point of Q-point poor. BJT negative feedback. um. Slow er than fixed bias.
rd minim
enters in is lhermal lower than forwa
bias. S ~ 6 to 10
runaway. , •. I

DC load line le : J I i /

(DCL L) Vee
. Rc+RE : : .. f
. \~ : / .: .j
·-· : _____.,_, DCLL J
• ·f.':_
DCLL
1 • "'; Slope= l'(c ➔ -.J- /
• Slo pe= --- ,
Rc+RE
. 1 1

/O -'---' --~/ Vee VcE I

0 Vee /

(1C88C) (1C880)
(1C88A) (1C88B)

ld high or
For this either ,R8 should be ]ow or RE shou
~ 2.21.1 Important Theory Que
stions on comb ination of R1 •
both. In PD bias since RB is parallel
'3iasing and R2, we can very we11 have RB low.
:.:p.i;;i_<:r: .. . -/°~f/:?:{:},'. :> ,' . \-~:-: .t :?" \,::, « -~ ., :, . . ·,, ~· . ·:

I ¥, ' ', .
g;r?, Justify,.,.yo ur; n S from 6 to
:GQ. _wfi'ictf /gf:ls the d lest ,.biasin
·- . < it";~-:';·":_. ----:··. .. , . • (c) With RB low, S will be low. We can ob~
-aiiwefi,
:;.,_,_:,.,. ,., _..·,.';' .·._.. _,... ..,,.,_,,

f:l'iwhy do we,use PD ~'~-·11.onnally

.- ::'
?
_ OR: 10, which is v~ry small.
:
:---,-Vt'b~,:;,re:ffi;-~~~~~~,~~e,~~.:?i:.':.:"j;_ I
(d) Points (b) and (c) indicate that in PD bias,
stability of
high.
(a) (Refer Fig. 2.21.1) Q point against variation in temperature is
follows
(e) If we write expression for Ico and VCEQ as

(b) For PD bias, S == (1 + f3) ICQ == L1 +;)-R: 8

: R x~
8
]

(1 + ~) Rs,
Now, if we $elect (1 + ~) RE » R8 or R8 = 0.1
be as ]ow
' To have better stabiJity of Q point, S shou]d and since V » VBB aJso (1 + f3) ~ f3. Com
bining these
RB
as possibJe. This require RE to be ]ow.
+Vee
points

I1co = :. I . (2.21.1)

Re Re VCEO = Vcc - le (Re + Rs) Assuming 18 =le·

IYc6Q
C
R8 = R1 II R2
⇒
B
= Ycc- (f. )rRc+R,JI . (2.21 .2)
Vee
Q point
Equations (2.21.l) and (2.21.2) indicate that
Vee'¼ efore even if one
v -- ~1+ R2 Re (Vcso• lc0) is independent of ~- Ther
remain stable.
transistor is rep]aced with othe"r, Q point wi11
(0 From above points we conclude that
PD bias keeps Q
point stable against varia tion in temp erature as weJJ
""
(a) (b) as device parameter. These are the reasons,
(tClt) Fig. 2.2J .J prefer to use PD bias.
-- -- -- -- -- -- --
-- -- -- -- --H...A -- ---'
--Ye1nu
-=---: -- -- -- -= --
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['1 Analog Electronics (MU-Sem.3-Electrlcal) 2-47 Bipolar Junction Transistor

Worawback of PD bias ll means, to have bias stability 'either we must have

Th~ only drawback of PD bias is its loading problem. high RR or low Rn- High R8 will cause IBQ ~ lcQ to
.
of currcitt supp . d by
. 2.21.2 we see that most
from Fig. . 11e reduce. This will take Q point towards cutoff.
source. 1s taken by RB (because
. . 1t is tow) · Input current to
Therefore to bring Q point in centre, we have to
BJT 1.e. 81 decreases . This ts known as loading effect.
increase V cc· This decreases power efficiency of
Vs amplifier.
Is= Rs
On the other hand if Ru is low, a separate low voltage
supply has to be used in base .circuit. Both above
alternatives are not practical.
Hence this biasing is seldom used.

I 2.22 KEY FORMULAE TO SOLVE

Current Amplifier wilh PROBLEMS (PD BIAS
source PD bias
UNIPO LAR)
(1C901 Fig. 2.21.2
+Vee
To avoid loading problem, in practice we have to use
buffer amplifier between source and load. (Refer Re
R1 Re
Fig. 2.21.3).
C
Vee

(1C91) Fig. 2.21.3 R2 Re

RE
• . _- -:,., -- Gt-:- - ~~-- - - - : -:>r - - ~- :--_·- - ~ ~-~ - - ~ -:: "l" - - -- - ~,

:GQ. w:!? '~d~!lt~g,es of ~~ed bias ·? 'lfhY ·if is, rar~ly:

:_ - - - - u - - - • - - - - c>, / -- ------- ------ , --- : i;.J M
"i" vlh = v. Ru,= Re
l. Fixed bias is a simple circuit, it uses few components, it (1C96I Fig. 2.22.1 (1C971 Fig. 2.22.2
is very easy to fix Q point on DC load line in active
le
region simply by changing value of R 8 .
2. It provides maximum flexibility in design.
+
Re :
------: .
With all above advantag es also, this biasing is seldom ' ':
- V :
used as there is no check on increase in collector w::
,- __ current. The operating point is not stable. _______ __ ~ le Rs 8
+
VcEa:
' '
:
-,.J\JV\/\, _..:::.1
!GO. Why collector to base bias'is'· ranjiy,!:ised ? . '. .. + - + : : +
·--------- '"¥ ------- - . ----- _,,:= _ _ .:.;,._:<:-:·-.-~-- - -&·'' - - - ,_,_. ___ J VeE - -=-o:
E Ve :
:
t'
- Vee
: ------ le
· This circuit has tendency to stabilize the operating + ,'
i
,I ♦
I
I
'I II

V - ~
point against temperatu re and ~ variation.
I I I

:___________ :
I ' Re :L..._J:
The circuit is seldom used because the biasing resi.stor
R not only provides de negative feedback but also B-loop C-loop
8

provides ac negative feedback which reduces gain. (1C91) Fig. 2.22.3

.------ ------- ------- ------- ------- ------- i R2
;oo. Why self bias with Re is not used ? ______ j
------- ------- ------- ------- ------- (I)
fixed bias with
To design bias stable circuit using
(2) ~ = RB =R, RI + R2
RE, we should have (I +~)RE> > Re·
= V = le Re + V BE + IE RE

8
(3) V,h
Or Vee
(4) R1 = yxR 8

.. ...A SACHJN SHAH Venture

Tedi-Neo Publiutiom........... W!,ere Aut/Jon inapire innovation
 L.n:J "'' 'a,og t1ectronics (MU-Sem.3-Electrical) 2
-49 Bipolar Junction T r ~

V (16) While designing amplifiers, following assumpti ona::

(5) R2 = V
cc-V x R 1 be made.
(6) le= Total known voltage in base loop (a) S=6to IO
sum of all resistances through which le flows+ (l + 13) Vee.
(sum of resistance through which IE flows) (b) V cc =2 V CEQ or V CEQ =-2-
= Total known voltage in base loop
(c) VRE=0.l Vee.
(resiSlance in base) + (1 + f3) (resistance in emitter)
(d) Value of RE= 0.1 ldl ·to l ldl
V-VBE
(e) Value of Re= 2ldl to 5ldl.
Re -f (1 + f3) ~
(7) le = f3 le I 2.21 EXAMPLES ON BIASING
(8)
(CE CONFIGURATION)

(9) Apply KVL in C-loop Ex. 2~23.1 : Find ~ and VcEQ for the circuit shown in
V CE = total known voltage in collector loop - drop Fig. Ex. 2.23.1 iff3= 100.
+2 V +10 V
across Re -
drop across RE.
V cE = Vcc-IcR c-IERE R1
35 k
(1 O) Vc = V cc - le Re
( l l) VE = + IE RE
(12) VcE = Ve-VE
R2
(13) Stability factor (S = s, = s,co) 20 k

-5V -1 0V
I + f3 (l + f3)
s
ar0 ) = Re (1 C1 14) Fig. Ex. 2.23.l
l - f3 ( cllc l + f3 ~ + Re @ Soln. :
► Step 1 : Draw circuit with all power supplies shown
and named properly.
( 14)
I
I
I 1 (15)
R 1 = 35 k
B
This formula indicates that the change in ~ or drift in
Q point (on DCLL) mainly depends upon f3. If we can +
Vee
= 10V
make.
R8 << ( I + f3) RE, the equation for lcQ will be
v,
·0
2V
Re

Vee

~ [c~;;~J • 10V

= f3
Ri,,• Re, Vtt, C V
Since V >> VeE and (1 + f3) =f3 (1C115) Fig. Ex. 2.23.l(a)
V
IcQ = R :. ~ will be independent of f3. Thevenise circuit on LHS of BG.
E

Hence while designing amplifiers we can assume Re = R, II Rz =(351120) k = 12.72 kn

R8 = 0.1 (1 + f3) RE V = V -
B - -
V
BB + Rz · I = - 5 + 20 k x
Vee+V,
R
R, + 2
V = - 5 + 20 k x 557 k =
- 2.45 V
~UUl~o~;;;,tio.;a~-- --- --- --- - - -- - - - - -- -
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-;
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'1
-
►
Analog Electronics (MU-Sem.3-Electrical)

Step 2 : Replace circuit on LHS of

Theveni n' s equivale nt circuit.
BG
2-49
with
.--------r-- +Vee= 24 v +
Bipolar Junction Transistor

,,---~- ... ,
+
'
I
I
'
I
I C-loop
-- -'ca-=4mA
-Ve
Re= 0.8kn I t
I
I I
+
I I B
I
I '
I
p = 110
Re=
le 12.72 kn
+ - +
B
Vee:
=~ tI
I

'I +
----Ve
Module

•
:" --------- ---Yee I
I : + VRe=3V Re
: ......... e: I
Vee
: ♦ I - =10V G
I I
I
' :
V = 2.45 V 'II y
+ I

'' t I
p = 100
'' 'I
I ' ~cc= 10v l (1C1&a) Fig. Ex. 2.23.2
''.. ____ -~----- -' ... ____ ......,,
' '
Draw circuit diagram with separated power supply and
B-loop polarity shown Fig. Ex. 2.23.2(a).
(1C118) Fig. Ex. 2.23.l(b)
Re
Now using our short cut and applying KVL in B loop.
-V-Ve e+Ycc -2.45-0 .7+10
1
e = Rg + (I + f3) Re - [12.72 + (101) 0.5] k
Vee
l 8 Q = 108.35 µA p = 110
Vee
lcQ = f3 l 80 = l 0.835 mA Re
IEQ = l 8 Q + ~ = 10.94 mA

► Step 3 Vlh = V, Re= Ru,

To find VcEQ : Apply KVL in C-loop. Use shortcut. (1C1e) Fig. Ex. 2.23.2(a)

YcEQ = <Vcc+ Vcd-Ic Rc-IeR e Thevenise circuit on LHS of BG we get.

:. VCEQ = 20 - 8.668 - 5.47 24V=Ve e lca=4mA
Vee= 24 v
VCEQ = 5.862 V + ,,------ ... ,
I I

r:r Results : : C4oop

Re I I

I~ = 10.835mA , VCF.Q = 5.862 V I 1---:-eVe

♦ I
i
I

le Reh= Re I I

V~=8V :
+ - + I
Vcc=24V
I

Ex. 2.23.2 : Design a voltage divider bias network using a _..,___ , 1----_-eV e t
supply of 24 V, a transistor with f3 = 110 and an operating
I '
I ' + : :
1 : ': Re I
I V
I
I
p= 110
point of~ = 4 mA and V CEQ = 8 V. Assume Ve = 8 Vcc· V=Vlh I I
v~ =...££= iv
: t
I
·c 8 I
I

... _......, __ ,, I
I I

~ Soln.:
I I
•--4------- \

► Step 1 : Draw circuit diagram with all data given. 8-loop

(1C1Jl)Flg. EL 2.23.l(b)

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r
[il Analog Electronics (MU-Sem.3-Electrical) 2-50 Bipolar Junction Transistor

► Step 2 : Calculation for ~ and Re- V = le Rg + V8 E +IE~= (36.36 µA) (8.25 kil) + 0.7 v
le = 4 mA (given) + (4.036 mA X 743.3 Q)

~i [E = 1~61c
111
V = 4V

r:r Using standard formulae

IE = 110 x4mA=4.036mA Vee 24
Ri = y x Rs : 4 X 8.25 k.Q
le 4mA
Is = ff =IIO = 36.36 µA
IR, = 49.S ldl I
V
~ = V cc - V x R1
3V 4
RE = 4.036 mA = 743.3 Q = ~x49.5 k.Q

IRE = 743.3 al R2 = 9.9 ldl I

► Step 4 : Designed Circuit
Ve ➔ is the voltage at collector w.r.t GND. So start - - - . . . -- +Vee= 24 v
from GND and reach up to C.
R1 =4!U kn Re· 3.25 lul
Ve = VRE + VeEQ
le =4mA
I = (3 + 8) V = 11 V I C +
Yee -Ve 24- 11 Vee= av
Re =
le = 4mA E -

IRe = 3.isw l R2 • 9.904 kn Re• 743.3 kn

► Step 3 : Calculation for R 1 and Ri
To calculate R 1 and Ri we require Rs = Rm- To
(1cm Fig. Ex. 2.23.2(c)
calculate Rs students can use either of followi ng two
methods. Ex. 2.23.3 : For the circuit shown in Fig. Ex. 2.23.3,
Method I: assume ~ = l 00
Assume stability factor 'S ' between 6 to 10 and use (i) Find Thevenin's equivalent voltage V 11, and resistance
following formula to calculate Rg. Rm for base circuit.
(ii) Determine leo and V CEQ ·

Rs
= [ [ ¥-1 ]-I ]
~ -1 x RE
+SV +15V

Then proceed.
OR C

Method n: +3V
E
To calculate Rs for a bias stable circuit, we can
Assume, Rs = 0.1 (I + ~) RE Sk

We use "Method II" - SV

Re = 0. 1 (I+~)~ (1C120) Fig. Ex. 2.23.3

= 0.1 (111 ) x 743.3 k.Q @ Soln. :
RB = 8.2SW From given circuit, draw basic or simple DC
Apply KVL in 8-Ioop Fig. Ex. 3.2Q.5(b). equivalent circuit (Fig. Ex. 2.23.3 (a)).

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-
~ Analog Electronics (MU-Sem.3-Electrical) 2-51 Bipolar Junction Transistor

Now using Rm and Vth the circuit will become as shown

in Fig. Ex. 2.23.3(c).
'ca
B' B
+ Vee 50 k Re

+
7
V3
- 15V
C +
Veea
E -
+
Vee
- = 15V
- JV le
G
vlh
+ = 3.031V
Rtti,, vlh,
11c1211 Fig. Ex. 2..23.J(a)

Toevenise circuit on LHS of B' G' (1C123) Fig. Ex. 2.23.3(c)

Ru, 1 = I½ II R 1 = (500 II 500) k = 250 kQ
Using direct method
11 will flow from positive terminal of higher voltage source.
Applying KVL in Base loop
2 Total voltage in Base loop ]
Vtb 1 = V2 - I,R 1 =V 2 - ( ; :~:)R, 1co = 13 [ Base Resistance+ (l + 13) (Emitter Resistance)

= 5-(~~) 500 X
= 13 [
-VTH - VBE + VEE ]
Rm + o + 13) RE
vth 1 = +4V
- 3.031 - 0.7+5] 226
Now replacing circuit on LHS of s'G' with R.i, 1 and V lh i :.Ico= !OO [ (54.637 + 101 x 5) k = 0· mA
we get Fig. Ex. 2.23.3(b),
1 + 13) 10 1
[EQ = (- - lco = lOO X 0.226 mA = 0 ? 28 mA
Now Thevenise circuit on LHS of BG we get 13
Rm 2 = Ro, 1 II R2 = (250 k) II (70 k) = 54.687 kil = Ru, VCEQ= ( Total known voltage in Collector loop
- drop across Re- drop across RE)
= (Vcc + VeJ - le Re - JERE
= (15 + 5) -(0.226 mA x 50 kQ) - (0,228 mA x5 kQ)
Rtti1 B
VcEQ= 7.56 V
250K + :. Q point is (7.56V, 0.226mA)
Vee
Ex. 2.23.4 : Find Ico and V CEQ for circuit shown in

+
Fig. Ex. 2.23.4, if j3 = 100.
+5 V +16 V
4V - Vlh1
G

Rtti2, vth2
(1C122) Fig. Ex. 2.23.3(b)

Vlhl = Voltage at Base with respect to Ground= - V ,+ 12 R2 +5V B

(V,+Vlh1) (5 + 4 ) x 70k
=-V,+ Roi1+R2 xR2=-5+(250+70)k

9
Vt1i2 = - 5 + 320 x 7~ =- 3.031 V = V111 -5V

(1C121) Fig. Ex. 2.23.4

· · V111 = - 3.031 V

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 !'1 Analog Electronics (MU-Sem.3-Electrical) 2-52 Bipolar Junction Transistor
@' Soln.:
► Step 4 : Now draw circuit_of Fig. Ex. 2.23.4(c) With
► Step 1 : Draw circuit diagram with all power supplies Ru, and V(h· le
with their polarity as shown in +
Re . ,- --,
'
Fig. Ex. 2.23.4(a). 0.5k0 : t.
Name all resistances and power supplies. . I
'
'
VeE ' '''
''
_-_VE:' +
- E : _ 16V
.,-•--------,'. '
I

.'
I'
R 3 =60 k
B'

Vee
+
Vlh = 2.SV .' •.'
'
I
'
t'

r7- ''
+
I
' '''
l[ - 16V :s
,__ _..,_ ____ ..,,_.
' VEE ~ __ ,
'

+ V +
5V
B-loop G C-loop
+
5V (tCt32) Fig. Ex. 2.23.4(c)

G To calculate IcQ we can use shortcut method.

Ru.1, V1111 Ru, , Vth Total known voltage in Base loop ]
(tCt30) Fig. Ex. 2.23.4(a)
~=[ Resistance in Base+ (l + [3) Resistance in Emitter x ~

► Step 2: Thevenin's circuit on LHS of B'G' to - [ + Vth - VBE + VEE] X

calculate Ru, 1and V th 1.
IcQ - Rm+(l+~)R E ~
Ru, 1 = R 1 II R 3 =(30 II 60) k.Q = 20 kQ 2 .s-o. 7 + 6 100 25 82 mA
= [IO + (IOI) x 0.2] k x = •
(V-V)
V lhl = + V - l1R1 = + V - RI + Ri
IEQ = [ ~ ] lcQ =[ (~~~)] X 25.8 mA = 26.05 mA
= 5-0=5V
VcEQ = (Total known voltage in C-loop - Re drop - RE drop)
► Step 3: Redrawing circuit in Fig. Ex. 2.23.4(b) with
= ( + Vcc + VEE - le Re - IE RE) .
Ru, 1 and V th I.
= (16 + 6)-(25.82mA X 0.5 kQ)-(26.05 mA X 0.21"2)
Now Thevenising circuit on L.H.S. of BG we get. = 22-12.91 -5.21
Ru, = Rm 1 II R 2 = (20 k II 20 k) = 10 k Q :. VCEQ = 3.88 V

=
Rz
Ri + Ru.1
r:r Results
V th V lhl X
i.e. using voltage division ru~e.
I 1c9 = 25.82 mA, VCEQ = 3.88 V

20 k 2)( Ex. 2.23.5 : Determine Q-point and draw DC load line for
V111 = 5 x (20 + 20) k = 5 X )( = 2.5 V
4 amplifier shown-in Fig. Ex. 2.23.5.

Vee

Ra,,V11,
(tC1~l Fig. Ex. 2.23.4(b)
(1Ct37) Fig. Ex. 2.23.S
Teeh-Neo Publialiom-·- -·- Here Author, iDIJlire iDDoYatioa _...,4 SACH/N SHAii Ye11turt
~ ,AnaloQ Electronics (MU-Sem.3-Electrica l) 2-53 Bipolar Junction Transistor

~ I = 13 x [ Total known voltage In Base loop ]

g1 sc,1n.: 00 Resistance in Base+ (1 + 13) Resistance i/1 Emitter
To find Q point, Draw DC equivalent circuit
► supt: - V 1h - V BE + VEE]
by opening all capacitors and showing all DC
lcQ = [ Rm + (l + fl) RE X fl
supply with proper polarity.
= [ - 3.57 - 0.7 + 5V ] OO _ I 398 mA
[1.71 + (101) X 0.5) kQ X I - .

IEQ =
!..±Ji
fl X lcQ IOI
= JOO X 1.398 mA = 1.41 mA

For VcEQ : Apply KVL in C-loop. Using our direct

Vee formulae.
V cEQ = (Total known voltage in C-loop - drop across Re
~ drop across RJ
- Vee = (Vcc + V EJ - IcRc - IERE

Rtt,, Vlh = (5 + 5)-(1.398 mA X 5 K)-(1.41 mA X 0.5 kQ)

(1C140)Fig. Ex. 2.23.S(a) VcEQ = IO - 6.99 - 0.705 = 2.305 V

Qp1 = (2.305 V, 1.398 mA)
► Step 2 : Calculating Ru, and V th looking from LHS of
BG. = (V CEQ• lcQ)
Refer Fig. Ex. 2.23.5 (a) ► Step 4 : To draw DC load line : Apply KVL in C-loop
Rm= (R 1 II~) =(l2ll2)kQ=l.7lk Q and write it in the form of y = mx + C.
VEE+ Yee Vee+ VEE-IcRc-IE~ - VcE = 0
Vdi = - VEE + IR2 = - VEE + R ,+ R2 X R2
Let Vcc + VEE = V' = l ov
lO
Vdl = - 5 + 02 + 2 ) )( X 2 )( V' - lcRc - I ~ t} lcRE - VCE = 0
= -3.57V
le V' -le[ Re +(lj1i) ~J -VcE = 0

Re
Let I+ fl = fl
V' - le [Re + ~] - VCE = 0
I
v'
I
!I + le= (-Rc;~R) VCE +
,-----,,
I
I
I
5V
~y ~
I
I
I
'
'
',
♦ :
I
y= ffi X
v"' I
I
I
I I
I

=3.57V
♦ I
I
I
I
I
I
Now two points for DCLL
t : .
,I ___
I
I
I
I
I
Let le = 0, then V CE = V' = IO V
I I
,_ -~----'
I '
+ I = Re+l RE V' = 1.818 mA
Let VCE = 0, then -c
B-loop C-loOP
: . Two points to plots to plot DCLL are
(1C141) Fig. Ex. 2.23.S(b)
(0, 1.818 mA) and ( l 0V, 0) with Slope =
► Step 3 : Replace circuit on LHS of BG by Thevenins 5.5lcQ
equivalent circuit consisting of Ru, and V m·
Refer Fig. Ex. 2.23.5(b) using our shortcut method,
ipplying v,." . B
~.... v L m ase loop, we get

Tei:!i-Ne. Pub•=--·' · --4 SACHJN SHAH ~ature

- - - ~ Autl,on uupi~ ilJDOffllOD
 Analo g Electr onics (MU-S em.3-Electrical) 2-54 Bipolar Junction TranSi
stor

lc(mA) .i
Vee (V) vis tc(mA)
r
' ► Step 3 : Apply KVL in Colle ctor loop using
shortc ut formu la
oUr '
;
Y ceQ = (Tota l know n voltag e in C-loo p
2
DCLL slope = - 1 ' - Re drop - Re drop)
1ca=
1.818
5 .5 X 10
3 i
1.39mA Q =.(2.3V, 1:39mA ) [ y ce = V cc - IcRc - l e Re but Re = 0
1.... t = IO - 3 x IO - 3x 2 x 103 = 10 - 6 = 4V
I Vee = 4V

V'
rr Results
l 0 2: 4 6 8 10 i Vee (V) ( Io = 15 µA, le = 3mA , VCE = 4 V
V CE~-=- 2.JV l
r (1C142 )Fig. Ex. 2.23.5 (c) Ex. 2.23.7 : Find 1 ,
8 le and Y ce for circui t shown in

UEx. 2.23. 8 MU - a. 2 b . Dec. 19. 5 Marks

Fig. Ex. 2.23.7 .
· +5V
Calcu late le, le and Ycs for circui t shc_:>wn, i!} Fi,g.
};:x. 2.23.6.
Re= 0.5 k!l

Is

v88 =4V
-5V
{1C146) Fig. Ex. 2.23.7
(1C143l Fig. Ex. 2.23.6
@ Soln. :
@ Soln .:
► Step 1 : Draw circui t diagr am with all voltage sources
► Step 1 : Draw circu it diagr am with all voltage sourc
es show ing their polar ity and name s e.g. Vcc.VEE
show ing polar ity and name e.g. Y cc, Y 88 etc.
as show n in Fig. Ex. 2.23.6 (a) below . etc. Fig. Ex. 2.23 .7(a)
le
,---. le
Re : :
2k : :
:' +'
Vee :'' '
:' +
B
f I + 10V ....... -, Vee + Vee
e-=- : : I \ _ =5V
I
I
I
I
- Vee I \
I \
I I +
I I
B-foop C-loop tI ·
T
I -
I I
(1C144) Fig. Ex. 2.23.6(a) I I -
--◄-- Vee= 5V
► Step 2 : Apply KYL in B-loo p and use our formu
la ·
Total voltage in Base loop B-loop
]
le == [ Resistance in Base+ (I + f3) (Resistance in Emitte (1C147) Fig. Ex. 2.23.7(a)
r)
Y88-Yae 4-0. 7
Is =Ra +(l+ f3)(0 ) -220 k.Q= 0.01 5mA =l5µ
A
► Step 2 : Apply KYL in Base loop and use our sborte 01
formu la
18 = 0.015 mA f3 [ . T~al known voltage in Base loop . -]
le = p1 = 200 x 0.015 mA = 3 mA. = 3 mA Resistance m Base+ (I + f3) (Resistance in Emitter)
- --::--Public
-:---:----
8
- --; ;;;s~= ,:-tioa::= =~ == --- --- --- --- --- --- ---
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>

~ Analog Electronics (MU-Sem.3-Electrical) 2_55 Bipolar Junction Transistor

- le= _~[ 0-+~;•:~~J =ICJOx[-l~l7:nmA

le
100 X 4.3
le = 101 mA = 4.25 mA, -+ V :----i
C I I
le + Re
IE
1.±J! 101
= ~ le = l OO x 4.25 mA, +
VcE
I

:
I
I

:
I
200k --VE: :
,------, IE : :
IE = 4.29 mA I \ I I
I ' I I
I \ I I
1c 4.25 mA I I

le = "'if - 100 = 0.0425 mA I I Module

-
♦ l :
I '
' I
:I I
1
20V ,I
► Step 3 : Using shortcut method : :vEE - I
: : + I :
VCE = (Total known voltage in Collector loop - Re drop 1I __ _ ...,_ ___ 1I
le+ le I
I --4-'
I

=IE
- RE drop) C
A E
= (V cc + V EJ - (leRc) - (IERJ B-loop 'i" p = 90 C-loop

= 10- (4.25 X 0.5) - (4.29 X 1) (1C155) Fig. Ex. 2.23.S(b)

:. VCE = 3.58V
Step 2 : Calculations for le, le and IE :
►
er Results
Apply KVL in Base loop, use shortcut method to find le,
I 1B = 42.S µA, le = 4.25 mA, VCE = 3.58 V le = [ Total known voltage in Base loop ]
~
(Base Resistance)+ (1 +~)(Emitter Resistance) x
Ex. 2.23.8 : For the circuit shown in Fig. Ex. 2.23.8,
-VeE+VEE]
calculate le, le, V cE• Ve and S1co· Find region of operation le = [ Re + (1 + ~) RE x~
of BIT. -0.7+20 ]
4 4
= [ 200 k + 91 x 2 k = mA .s
.!..,tl 91
IE = ~ · lea = 90 X 4.54 mA = 4.59 mA

le 4.54 mA
le= J3 - 90

le = 50.44 µA
► Step 3 : Calculations for Vc, VE• V BE• V CE :
-20V V is voltage at Base with respect to ground, so start
8
(1C153) Fig. Ex. 2.23.8 from A and reach upto Base.
@ Soln.: -le Re=+ Ve =.-(50.44 µAx 200 k) =-10 V = V11
► Step 1 : Since DC analysis is to be performed, open all VE is voltage at Emitter with respect to ground; so start
capacitors. Because at DC (f = 0), Xe is •
00
from ground and reach upto Emitter.
Then draw circuit diagram with suitable name :. VE = - VEE + IE RE
and value of supplies and resistances. = - 20 + (4.59 mA X 2k)
= -10.82 V
200 k VcE = Yc-VE=0-(-10.82)
B = + 10.82 V
VeE = Ve-VE
= -10-(-10.82)
= -10+ 10.82=0.82 >+0.7V
p = 90 - 20V

11c1M)Fig. Ex. 2.23.S(a)

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 /'1 Analog Electronics (MU-Sem.3-Electrical) 2-56 Bipolar Junction TranSistar

J9E junction is Forward Biased (FB) ~ Soln.:

= Ve - Vc =- 10 - 0
id
I
VBC
= -IOV
Since we have to find all DC parameters, we lllUst
perfonn DC analysis.
Since V ec is negative. lee junction is Reverse Biased ► Step 1 : DC analysis
(RB). With leE Forward Biased (FB) and lee Reverse Biased To do DC analysis we should draw DC equivalent
(RB) transistor is in active region. circuit (Refer Fig. Ex. 2.23.9(a)(i)), with all DC s011rcea
► . Step 4 : Stability factor S =S 1eo =s, shown with proper polarity and named.
1+6 le
= ale ... (t>
1-ftaf
Apply KVL in Base loop. Using shortcut method.
(Total known voltage in Base loop) - [lex (Resistance 8

through which component le flowing)] - [18 x (Resistance

Vee
through which component 18 is flowing)] = 0
(- VBE + VEE)-le RE-le (Re+ RJ = 0
20V
Differentiating with respect to le Vee VEE
+
ale
o- RE - ale (Re + RE) = o, G
Rtti=Re
R . V1h=V
R
B
~ RE
+
, Substituting this in Equation (1)
(2F2)(i)

We get, l+B
S = _ _.;a._......_ _ =

l+P .R +R
RE
E
91

B
2
I +90 X 202
-----=--- + ..
, -,
le

I
I
- I
I
= 48.12 C -Ve I
I
B
r:r Results + Vee
~-- - \
I VeE - -E VE
18 = 50.44 µA, le = 4.54 mA, V8 = -10 V I
I
' I . IE
: : +
vCE = 10.82 V, S = 48.12 V I I
I I
I I

Ex. 2.23.9 : For the circuit shown in Fig. Ex. 2.23.9. Find '--◄----·

VcEQ• ~. Ye and VE.

Vee= 20v
(2f'3)(ii)
R1 Fig. Ex. 2.23.9(a) : DC equivalent circuit
Re= 2.7 kn
8.2 k
Now thevenising the circuit on LHS of BG
p = 120V
(Fig. Ex. 2.23.9(a)(i)) we 8et final DC equivalent
VeE =0.7V
circuit of Fig. Ex. 2.23.9(a)(ii). Where
R2
RE= 1.8 kfl Re = R1 II R2 =(8.2 II 2.2 ) k =1.73 kQ
2.2 k
VEE+ Vee
-VEE= 20V
V = - VEE + I R2 =- VEE + R2 . R
1+
R
2
2.2
(2F1)Fig. Ex. 2.23.9 : Circuit diagram = - 20 + JOA X 40 =- 11.53 V

1T;;_;ee;.;h::;-Ni::w:-iP~u~blii:ica:;t;:io:m-:_,-_,...==.. IFln~e.~'ITl~,4i,;u;j,tJ,~on~im;'P';~~ill~110~,-.~ll~o;a-----------------------::-::---
_-4 SACHJNSJ/AH Yuhll'
p

['1 Analog Electronics (MU-Sem.3-Electrieal)

-
► Step 2 : Calculation for DC parameters using our
standard method.
2-57 Bipolar Junction Transistor

-V-VeE +VEE
- le = Re + (I + 13) RE
- 11.53 - 0.7 + 20 Vee
== 1.73 + (121) (1.8) X 10-3= 35.39 µA fl= 110,

le = 13 le = 4.24 mA Vee

IE = le + le = 4.28 mA
Ve is voltage at C w.r.t. GND, so start from GND and •
reach upto C. Vc = Vcc - le Re= 20 - (4.24 x 2.7) = 8.55 V vth =V, R8 =Rtt,

VE is voltage at E w.r.t. GND, so start from GND and 11e189JFig. Ex. 2.24.l(a)
reach upto E.
Thevenise circuit on LHS of BG we get,
VE= -VEE+I ERE=-2 0+(4.28 xl.8)
24 v = Vee Ica=4 mA
= -12.29 V Vee =24 v
VcE =Ye-VE = 8.55- (-12.29) = 20.84 V + ,------ ... \
Now, I
I I
I I C-loop
Re I
I
I
I
er Results I I
I I
+ Ve fI
Vc= 8.55 .V, VE= -12.29 V, I
I I
I I
Veea= av :
Vo:= 20.84 + - + I
I Vee= 24V
Vee= 0.7V - - v ♦
J 2.24 EXAMPLE ON DESIGN OF ,----,,
I
I
'
'
+
i
I
I
E I
I
I fl= 110
BIASING CIRCUITS V= Vth
:
,
:
: Re
I Ve
vR' =___Q_ = iv
I

: t ~ 8 :
I I
,_,.. _____ ,. ... __. __ .,, I
I -
Ex. 2.24.1 : Design a voltage divider ·bias network using a
I
I I \

supply of 24 V, a transistor with 13 = 110 and an operating

8-loop
point of~= 4 mA and VcEQ = 8 V. Assume VE=½ Vee·
(1C170)Fig. Ex. 2.24.l(b)
@ Soln.:
► Step 2 : CaJculation for RE and Re-
► Step 1 : Draw circuit ·diagram with all data given. le = 4 mA (given)
- - - - - - - +Vee= 24 v l±Jf 111
' + IE = l3 le=uoX 4 mA = 4.036 mA
Re
4mA
- 1ea=4mA le = ple = 110 = 36.36 µA
- - - - Ve
+
. B
fl= 110
3V
RE = 4.036 mA = 7433 ,a
Re
I RE = 743.30 I
Vc ➔ is the voltage at collector wrt GND. So start
y from GND and reach upto C.
(1C1U) Fig. Ex. 2.24.1
Ve = · VRE + VCEQ
Draw circuit diagram with separated power supply and
Polarity shown Fig. Ex: 2.24.1 (a). = (3 + 8) V = 11 V

· .. _,,, ... rraen: ~ -~ lll6plrt: --4 SACHJN Sll,48 Yeatum

Tech•Neo PUbl"1Ution1, mi. /IUWOnl • • • ,:
lll.DOYlluOD
r
I
~ Analog Electronics (MU-Sem.3-Electrical)

Yee-Ve 24-11
_
2 58
Ex. .2 . : Find ~. Re for circuit shown in Fig. Ex. 2. 24_2
2 42
Bipolar Junction Tranaiato,
a....

Re= le =4mA to get V CE = 5V and le =2 mA. ~ =1OO • VBE = 0.7 V.

11 I I Re = 3.25W I +Vee= 10v

► Step 3 : Calculation for R 1 and R2

To calculate R 1 and R 2 we require RB = Ru,. To Re
Re
calculate RB students can use either of following two
methods.
Method I : Assume stability factor ' S' between 6 to 10 and
use following formula to calculate RB.

RB = [ [ ~~ ]-I ]
S - l - 1 x RE
(1C159) Fig.

@ Soln. : Draw circuit diagram with all currents and

Ex. 2.24.2

Then proceed. OR voltages shown in Fig. Ex. 2.24- 2 (a).

IB
Method Il : To calculate RB for a bias stable circuit, we can Ie = 2mA
+
Assume, RB = 0.1 (I + ~) RE r--, +
I Re ,... ----,I
I
I I I

We use "Method Il"

I
I ,_ I I
Vee
Vee
I I :+
I
♦I +
RB = 0.1 (I+~) REO = 0.1 (111) x 743.3 kQ I
I Vee= SV '-
I
10V
10V
I I
'
I

t
I
RB = 8.25 kil i
♦

•,_ __'
I
I
·--,,,Vse
I
', - E ,
I

Apply KVL in B-loop Fig. Ex. 2.24.l(b). I

I ~ I I

V = IB RB + V BE+ IE RE= (36.36 µA) (8 .25 kQ) + 0.7 V

~------ --- --·
+ (4.036 mA X 743.3 Q ) 8-loop C-loop

V = 4V
11c1&0) Fig. Ex. 2.24.2(a)
er Using standard formulae
KVL in B-loop. Using shortcut method
Yee 24
R 1 = ~ x RB =7 x 8.25 kQ Yee-VBE 10-0.7
or
9.3
RB= -1-
IB = RB + ( 1 + ~) RE - RB
R1 = 49.5 kil I 2mA
B

V 4
R2 = Vee-V XR1 = 24-4 x49.5 kQ
where, IB = fi"le = 100 = 20 µA
9.3
R 2 = 9.9 ld2 RB = 20 µA = 465 kil

Step 4 : Designed Circuit KVL in C-loop, V CE =

►
- - - - - . . - - +Vee= 24 v
Re =
Re. 3.25k!l r:r Results
le =4 mA
C +
RB= 465 kQ, Re = 2.5 kQ I
Vee= av - ~ - - - - - - Vee
B = 10V
E -
Ra
~ • 743.3 k!l •465kfl
R2 • 9.904 k!l
c-+-
B
Vce= SV
+
, 1e111)Fig. Ex. 2.24.l(c) Vee E ..=_
fl= 100
(1C111) Fig. E:x. 2.24.2(b)
-;;:--:--::---::-::-:----:--- -;;~~:, ::====
Tech-Neo PubliarioDI-•-····· Jf'/Jere ,4ut/Jon impire lllDOYatioa
::=---- -------- --=----~ ---~
•• -4 SACHIN sJJ,411 re11fdl'
►

-
~ Analog Electronics (MU-Sem.3-Electrical)

fX. 2.24-? : Determine the value of

and~= 50.
Re such
2-59

that V c = 5V
Bipo~r Junction Transistor

Ex. 2.24.4 : Detennine the values of biasing components for

a CE configuration if Vee= 12V, VCE = 6V, R 1 = 1 ill ,
V BE = 0.6 V, ~ = 180 for the following circuit.
(i) Fixed bias without RE.
(ii) Voltage divider bias with V RE = 10 % of V cc and
100 kn
S; = 8.
li:'.f Soln.:
In this problem we have to deal with two types of biasing s_o Module
Fig. Ex. 2.24.3 we divide problem in two parts. .
0

Part (A) for fixed bias and part (B) for voltage divider bias.
@' Soln.:
Part A
► Step 1 : Draw DC equivalent circuit properly with -
Data given, Vee = 12 V, VCE = 6V, R 1 = l kQ ,
correct polarity of DC supply and named.
V BE = 0.6 V and ~ = 180
Refer Fig. Ex. 2.24.3(a).
► Step 1 ·+Vee= 10V
► Step 2 : Calculate Re
Using this data draw
Use our short cut method to find 18 Re Re
circuit diagram of CE
Total known voltage in B-loop
10 amplifier with fixed bias
= Resistance in B + (1 +~)(Resistance in E)
without RE.
= VEE-VEB 10-0.7 mA
Refer Fig. Ex. 2.24.4(a).
R 8 + (1 + ~) (0) 100
18 = 93 µA
Fig. Ex. 2.24.4(a)
le · ~ 18 = 50 x 93 µA
► Step 2 : Draw DC equivalent circuit.
:. le = 4.65 mA
Refer Fig. Ex. 2.24.4(b)
Vc = 5V (given)
Apply KVL in c - loop
Ve is the voltage at collector w.r.t GND. So start from le
GND and reach upto C.
+
.-----.:
:
:. Ve = +leRc 1k Re i !
I
Ve +5V :
:. Re = T = 4.65 ill = 1.07 kQ Re + I

+ - +
Vee T
i------. :
I I
,------,,VBE - I
I
+
!
I
:
I
I

+ :
I

t
I
I
I
I Vee
Vei= 5V l Vee - ,________ ,
I I
I
.:_ = 12V

'
I I

=12VL---4----------,-......
:
I
I
t
I
I
I 8-loop C-loop
f---------- I
I
I
I
I
I
I
I Fig. Ex. 2.24.4(b)
1
I
+Vee: :
I I I
1___ ..... - - - ~ _ 10V :-- ◄- , Vcc-lcRc-VcE = 0

C-loop
Vcc-VCE 12-6
8-loop le = Re --1-mA
Fig. 2.24.3(a): DC equivalent circuit le =6mA
le
r:ir Result 18 =p= 33.33 µA
Re = 1.07W

Teeb-Neo Publieationa ........... When' Aut/Jon ia,pil't' iaaontioa .....A SACHINSHAH J'cnture
r
[ii Analog Electronics (MU-Sem.3-Electrical) 2-60 Bipolar Junction Transistor

Apply KVL in ~-loop Now VRE = 16 Re

VRE 1.2
V cc - le Re - V BE = 0 :. Rs = T
= 4.82 kn= 0.248 k.Q
Ycc-VCE 12-0.6
Re = le = 33.33 µA - 342 k.Q ► Step 4: CatculatiQn for R, and R2
r,
,.-. _R_e_ =_34
_ 2____::_
W___, Formula for stability factor S1 can be written as

PartB
Data given
Yee= 12 V, YcE= 6V, R6 = 1 k.Q, VeE = 0.6 V
~ = 180, V RE = 10 % of V cc = 1.2 V, S; = 8
Re = [[ ~-'J'-J,
1~1)80-]]-I ]
► Step 1 +Vee = [[
- 1 X 0.248 kn= 1.816 k.Q

Using this data draw Applying KVL in B-loop

circuit ·diagram of CE amplifier
B V- IB"RB + VBE + VRE = (26.66 µAx] .816 k) + 0.6 + 1.2
with voltage divider bias with
R E. Refer Fig. Ex. 2.24.4 (c). = I.848 V

Now using our direct formulae

Fig. Ex. 2.24.4(c) R, = ~ c: Re= l.~!

8 x J.816 k.Q = 11.79 kQ
► Step 2 V 1.848
R2 = Vcc_ vxRi=1 2 -I.848xll. 79kQ
Thevenising circuit on LHS of BG.
We get the circuit of Fig. Ex. 2.21 .4(c). = 2.146 ill
R2 [:. R1 = 11.79 k.O, Ki= 2.146 k.O ]
Where Re =R 1 IIR2 andV=Vcc · R I +R
2
Designed circuits
I ►
Step 3 : Calculate RE
Jc
------- +Vee

I
.- ---,
I R1 Re=
Re=
• Rs 1k!l
I
11.79k
= 339k!l 1k!l

Rs +
Js
+
Vee T
I R2 Re=

,--
I
- -- , , Vee
-
+
I
I +
Vee
2.46k 0.2A8k

+ I
I
I
tVRe Re
V - ,__I Fig. Ex. 2.24.4(e)

8-loop C-loop Ex. 2.24.5 : Design a voltage divider bias circuit for
Fig. Ex. 2.24.4(d) Vee= 12V, Vee = 6V, le= lmA, S = 20, ~ = 100 and
VE= 1 V.
Apply kVL in C-loop
Ycc-IcRc- VcE-VRE = O @ Soln.:
V cc - V CE - V RE 12 - 6 - 1.2 mA ► Step 1 : Draw circuit diagram with all given
le= Re = l
parameters shown on it. (Refer
le= 4.8 mA Fig. Ex. 2.24:S(a)(i)). Then draw our usual
le 4.8 mA diagrams for further analysis and design.
le= p= 180 = 26.66 µA

l e = le +le= 4.82 mA
- = - - - - - - ---==- ~ --;---;-- - - : - ~ - - - - - - - - - - - - - - - - ~
Tec:b-Neo PublicalioDI-••······· Here Authon in6pire innoration ··-.A SACHIN sJl,4JI YeD~
-
['1 Analog Electronics (MU-Sem.3-Electrical)
Vee=12V
2-61

Re = SkO
Bipolar Junction Transistor

VE J
Re = -I- = ImA = J kO
CQ
le=1mA
C +
Vee =6V R,: = l kO
B
E -
► Step 3 : Calculation for R 1 and R2

,1il
'(I)

Re
OR R, =[1i!-J-l]R,=[~~ if- llill
:. RB = 23.69 W
-
In Fig. Ex. 2.24.5 (a)(iii), V is voltage at B' w.r.t.
R1 ground G'. :. start from G' and reach up to B'. We get
+
B
V = IBRB+VBE+Ve=[\~x23.69k'2+0.7+ 1]v

Vee
l R2
+
Re = 1.936V
Using our shortcut formulae,
Yee 12
Rs= Rlh R1 = yX RB= 1.936 x 23.69 kQ
V=V1h

,I.
(ii) IR1 = 146.77W I
le V 1.936
R2 = Ycc-V x R1 -12-1.936 x 146.77 kQ
+ _.,._,
I
I
I
I
I
I
·:. I R = 28.233kQ
2

C +
t: Designed ctrcuit
I
I

+
:
,+
<
-----+Vee= 12V
I
E -
-------, l- Vee R, • 148.77 kn ffc•5kn

V
+ I
I
IE t :
I I
C
: + I
I
I
I

: VR Re: :
: e I.. _ _ II

----- -----· E

B-loop G' C-loop 'i' R2•28.23 kn

(iii)
(1C213), (1C214J a (1C215) Fig. Ex. 2.24.S (a)
(1C211) Fig. Ex. 2.24.S (b)
► Step 2 : Apply KVL in C-loop.
(Refer Fig. Ex. 2.24.5 (a)(iii))
Vcc-IcRc-Vce-VE = O
12-6- J
I =SkO

Tetb-Neo Publication, ........... Here Aut/Jon in6pire inno.-ation ••...A SACHJN Sl/,4// renture
r ~ Analog Electronics (MU-Sem.3-Electrical) 2-62
Bipolar Junction Transistor

Ex. 2.24.6 : Design bias-stable amplifier using circuit in @ Soln.:

jl Fig. Ex. 2.24.6 such that Q-point is in the centre of load line.
Let 13 = 125. Determine 1cQ• VcEQ• R 1 and~-
Apply KVL in C-loop
Assuming le =
IE. Refer Fig. Ex. 2.24.6(a). Since
Vee = sv
Vee+ VEE
Q-point is in the centre of DCLL, VcEQ = 2 . Since
2Vcc 2x6
Vcc= VEE• V Cf.Q = -i-- = ~ = 6V
t---<>vo Apply KVL in C-loop (Fig. Ex. 2.23.7(b))
C +T (V cc + VEE) - le (Re + Re) - V cEQ = O
6V
1cQ = (Vee+ ~)-VCEQ= 1;_;6 mA = 2.73 mA
E - j_

1e -
_..!f _2.73 mA _ 21 84 µA
l3 - 125 - .
J3 = 125 For stability of Q point
VEE= -6V
Let R8 = 0.1 (1 + 13) Re
11e217) Fig. Ex. 2.24.6 = 0.1 X 126 X 0.2 k = 2.52 kQ
.@ Soln.: le
.
Amplifier given _is bipolar with PD biasing. Therefore, . (mA) . . .
!
·: ........ 1.....,• ..
i ! I ....! ......
I

first we draw our standard two circuits with all data given I

and capacitors open. le

.,, ~····
I

·:
Re
lea ----·
2.73imA
C
VeEa = 6V
8
E
1E" 1c VeEa 2Vee VcE

7
+
_ 2Vee Ir. = 12v · (V)
R2 RE ---=6V

VeeT :rEE 7 JYEE

Vee I- + 2

(1C220)Fig. Ex. 2.24.6 (c)

!
!'

Ru,. V
Refer Fig. Ex. 2.24.6 (b). V is voltage at B' w.r.t. G'.
(1C218) Fig. Ex. 2.24.6 (a) So start from G' and reach upto B'. We get,

----,
I I
V = - VEE + 1c RE + V BE + le Re
I
I
I
I
I
I
I
= - 6 + (2.73 x 0.2) + 0.7 + (21.84 µAx 2.52 kO)
I
I
o
I
I
= - 6 + 0.546 + 0.7 + 0.055
'
: I

19 :
I
I
V = -4.7V
e••,.--'VVvv-- =i : +
+ I Referring Fig. Ex. 2.24.6 (a)
___ _.,. - ---, .. , ..VeE -
I '
I
I

I
Vee
+
,Vrt, =V i
I I
I

·i°i +
I
I
4 6
·-------------# I
= - = 0.1079

8-loop
l
G' C-loop R1 R2
Re= R 1 +R2
c1e21t>Fig. Ex. 2.24.6 (b)
-=--- - - - - - - - - - : ----:---::--:---:----- - - - - - - - - - - - - - -- ------- 11
Tec:b-Neo Publiwion•·········- Jf/Je~ Authon inq,i~ innon,tion •. -.A SACHIN SJ/,411 Ye IIP'
p

['1 Analog Electronics (MU-Sem.3-Electrical) 2-63 Bipolar Junction Transistor

OR Re
Re 2.52 k.Q R1 = 9k
Ri = 0.1079 0.1079
B Vee

23.354 kQ
v~ ~ - I¼ Re
12V = 1k'1
+
'e
l
r2il
--
l l ( l 1 )
Rz = il;- Ri = 2.52 - 23.354 G
Vtt,=V
Rtt, = Re
= 2.s2 w 1

•
(i)
Designed ampllfler le

+Vee r - - --1
I I
I I

Re ! I C-loop
I

R1 = 23.35 kn Re= 2.2 kn I

C Rtt, = Re le
+
C - 'I
I
I
I
I

,-- ..
VEe - Vee
- + - B
-- - -,, Vee E + I +
E + I

V = V111 -
I
'' I

R2 = 2.82 kn RE= 0.2 kn = 1.2V +

t I
''
: 0.1K
I
Re
I
I
I
I
I I
+
.,... ____.
I

·---- __
I I
I I

1E = fc + le

B-toop
(1C220A)Fig. Ex. 2.24.6(d) (ii)
(1C204i &(1C205)Fig. Ex. 2.24.7(a)
Ex. 2.24.7: For the circuit shown in Fig. Ex. 2.24.7, design V
the circuit such that the Q point is in the centre of DCLL. ► Step 2 : Q point in centre of DCLL means = ~c as

Find lcQ and V ECQ also. shown in Fig. Ex. 2.24.7 (b).
+Vee =-12V
:. VECQ = 6V

9K R, ► Step 3: Re= R 1 II R 2 = (9111) k.Q = 0.9 k

-Vee -12 .
V = - I Rz - Ri + R • Rz = W x 1 = 1.2 V = - 1.2 V
2
:· ·r ·
, Ic(mA) ..

1K R2 I
• j
,:--·T-
'
····•··••·; .....
I
- I
.....,.r.···--
~= 75
;·• leaI ·r ~---:--~
11<:202) Fig. Ex. 2.24.7 --- +- . -
:. I' I
@' Soln. : :·· ·1· ++ _; v- l :
► Step 1 : Since biasing is PD bias first we draw our two
usual circuits as shown in Fig. Ex. 2.24.7(a)(i) and
:_i
'
_L: .
;,.... ,1"" i !

j_J_ __1v 6V - Ve~

e~a-- ~
; . cc :
~-2'✓-_ IVec:MI. ---
I J '. ---
!

Fig. Ex. 2.24.7(a)(ii).

(1C2111) Fig. Ex. 2.24.7(b)

Tedi-Neo Publicatiom--··-- "1,ere Authon ioapire ioooW1tioo --...4 SACHJNSHA/I Yeoture

r
Ii] Analog Electronlcs (MU-Sem.3-Electrlcal) 2-64 Bipolar Junction Transl
Btor
► Step 4: lc=0.5mA

Refer Fig. Ex. 2.24.7 (a)(ii)

'j
I Using our standard fonnula. Apply KVL in B-loop +

le = 13 [ . Total voltage in B-loop ]

Resistance in B + (I + Jl) (Resistance in E)
+
Vee +
+ le
= l3 [Rs+~1-+V;; (R )]
6
= 75 fl.2 - 0.7]
Re
[0.9 + (? 6 x 0 . l)] mA = 4.41 mA + + Vee + Vee

IE =
.l.±J}. 76
13 ·le= 75 x 4.41 mA V1 TL-- -v1_:r.L--...H-t-..r_
. . ....---=fov
IE = 4 .47 mA Vlh,Ru,

► Step S: Now apply KVL in C-loop (1C185) Fig. Ex. 2.24.8 (a)
If we thevenis circuit on LHS of BG in
Vcc - IE RE - V EC - le Re = 0
Fig. Ex. 2.24.8(a), we get Fig. Ex. 2.24.8(b).
V cc - 16 RE - V EC 12 - (4.47 mA x 0.1 k) - 6
Re = le = 4.41 mA
le= 0.5mA
Re = 1.259 kil +
---- .
Re .'I ~I
er Result I I
- I I

I Re = 1.2S9 kil le
I
I
:
I
I
I
I
I
I
I

Ex. 2.24.8 : Design the circuit shown to be bias stable I

I

(Fig. Ex. 2.24.8) and to provide nominal Q point values of

t
Ico = 0.5 mA, VECQ = 8 V. The maximum current through
R 1 and R 2 to be limited to 40 µA, 13 = 60.
+SV +10V

(1c1ee)Fig. Ex. 2.24.8 (b) : DC equivalent circuit

1. Ref. Fig. Ex. 2.24.8(b)
1=40µA Apply KVL in C-loop; Let IE =le
(VEE + Vcc) - le (Re + ~) - V EC = 0
20 - le (Re + RE) - V EC = 0
-SV -10V
20-8
(1C1M)Flg. Ex. 2.24.8
Rc+RE = ~__;;'---
0.5mA
=24K

@ Soln.: Let, IRe = 14 k.Q I then I R 6 = lO ~

Draw DC equivalent circuit with E down and 2. For bias stablllty Let Re =RTH =0.1 (l + ~) Re
c up. Show all DC sources with proper polarity and named.
R1 R2
=Re= 61 X lO k x 0.1 = 61 k = R, + R2
R1R2
R,.H = RI+ Ri = 61 k ... (1)

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-
Bipolar Junction Transistor
['1 Analog Electronics (MU-Sem.3-Electrlcal) 2-66
-.&
J. Refer Fig. Ex. 2.24.8 (a) I 2.25 EXAMPLES ON BIASING OF
COMMON BASE (CB)
vlh = - V,+2v,(R : 2R
I 2
)=-5+ ,o( R, R2+ R2) CONFIGURATION
~ ti R2
From ( l ),Bul RI - R +R Ex. 2.25.1 : For BJT shown in Pig. Ex . 2.25. 1, the Common
I 2
Base (CB) current gain (ex) = 0.9920. Find Errutter
Ro Resistance (RH) such that Emitter Current IE = I mA. Also
:. v 111 = - s+ 10Ri ... (2)
find fu , le and Yue·
4. Refer Fig. Ex. 2.24.8 (b) Re = 1k!l Module

le Ra
le
l3
=
0.S mA
= le = ~ = 8.33 ~LA

8.33 µA x 61 k = 0.S08 V
.ii
IE = ( I+ 13) 10 = 0.S08 mA a= 0.9920
IE RE = 0 .508 m x lO k = S.081 V
(1C231} Fig. Ex. 2.25.l
Apply KVL i.n B-loop (Fig. Ex. 2.24.S(b)) @ Soln.:
le Re - V111 = 0
► Step l : Always try to draw circuit such that Emitter (E)
10 - IE RE- V EB -
is downward and Collector is upward, so that we can use
Which gives V th
our direct short cut formulae .
.'. Vlh = l0-5 .081 - 0.7-0.508 =3.711
Put this value in Equation (2),
Ra
3.711 = -5+lOR
I

lORa IOx61 k
= 3.711 + 5 = 8.711
Vee
R, = 70 kil I + 5V

l I l I
Now, Ri = Ra - R, = 61-70
: . R 2 = 474.44 kQ G
Now current I flowing through R 1 + Ri will be
(1C232}Fig. Ex. 2.25.l(a)
IO lO
18
I = R + Ri =70 + 474 = .4 µA 1 ► Step 2:
Cl 0.992
40 µA current limit is met. 124
f3 = l- Cl= l - 0.992 =
Designed amplifier Now using our normal step of Common Emitter (CE)
+5V + 10V
analysis. With IE= I mA
Re• 10 kn IE lmA
R 1 • 70 kn 111 = 1+13 = 125 =8µA

I= 18.4 µA I lu
= Total known voltage in Base (B) loop
Base Resistance + ( I + 13) (Emitter Resistance )
V1111 - VBB
= 0 + ( I + 13) RE
R 2 • 474.4 kn
Vaa-VEB 4-0.7
:. Ra : . Rg = 3.3W
- 5V - 10V = (I + 13) IR = I 25 X 8 µA :
11 c111A)Flg. Ex. 2.24.8 (c)
le = (31 0 = 124 X 8µA lc=0.992mA

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r
[ii Analog Electronics (MU-Sem. 3-Electrical) 2-66 Bipolar Junction Transistor
► Step 3: Using our short-cut formulae to find Base Current (1 ) ._
8
V EC = [Total known voltage in C-loop - V - V ] Total known voltage in Base (B) loop
RE Re 1e - Resistance in Base+ (1 +~)(Resis
V EC = ( + V cc+ Vee) - lcRc - [ERE tance in Emitter (E))
= 9-(0.99 2x 1)-(l x3.3)=4 .7V; V =0V -VeE + Yee -0.7 +2
8
V c is voltage at C w.r.t ground G. So start from G and = Re+ (1 + P) ~ (10 + 76 x 1) kQ
reach upto C.
I 8 = 15.1 µA
:. V c = - V cc+ le Re= - 5 + (0.992 x 1) = -4.01
Yee = Ye-Ye= 0-(-4.0 1)=4.0l V le ~ Pie = 1. 13 mA

► Step 4 : Designed circuit with calcul~ted parame~ rs IE = (1 + 13)1e= 76 x 15.l µA; IE= 1.15 mA
le=
0.992mA 1 kn ► Step 2:
+ Ye = -IeRe= -15.l µAx lOk =-0.15V
Re Vea _ + Vee
= 0 .7V = 4.01 V VE = - Yee + IE ~ = - 2 + ( 1.15 x 1)
Ie Vcc=5V + VE = -0.85 V

(1C233)Fig. Ex. 2.25.l(b) Ye = Vcc - le Re = 8 - ( 1.13 x 2.5) = 5.175 V

VCE = Vc - VE= (5.175 - 0.85)
Ex. 2.25.2 : For the circuit shown in Fig. Ex. 2.25.2.
Calculate different current voltages. VCE = 6.03V

Re= 1 kn Re= 2.5k

YeE = Ye - VE= - 0.15 - (- 0.85) = - 0.15 + 0.85
YeE = 0.7V

Vee= 2v
+
Vcc=BV
Yee = Ve - Vc = -0. l 5 - 5.175 ;
+ Re= 10 kn Vac = -5.325 V

p = 75 • Note : Students should note· that Vac is n~~

(1C234) Fig. Ex. 2.25.2 (-ve). Therefore , Jee (Base Collector Junction) Is RB

@ Soln.: (Reverse Biased) and -Vee is positive. Therefore B~

Emitter Junction (Jee) Is Forward Biased (FB). Hence
► Step 1 Draw circuit diagram with Emitter (E)
downwar d and all voltage current shown with proper transistor is in active region which Is requirement to
polarity and direction respectively. act as an ampllfjer
Refer Fig. Ex. 2.25.2 (a)
le Circuit with calculate d currents and voltages is as
.,--,
I
shown in fig Ex. 2.25.2(b)
I
I
I
I C-loop Ve= 5.175V
I
Re=
~--ovc : Re= 1kn
10 Kn - + I
I
+ Vee ,
le -B : + Vee= -5.32 v 1 kn le
Vee + = 1.13mA
Vee E Ve: Vee =0.7V
+
Ve= --0.15 V
r--~--- . . ,
I
+ : av · + v 88 =2v +
', I
: ', + t ♦ ffe= 10 k!l
: : + Vcc•BV -
I I
I I : :
18 = 15.1µA
+ .' - : :
: : + V88 = 21/, :
I I I f
"-------- ---~ le ',..,.,
(1CZ31)Flg. Ex. 2.25.2 (b)
B-loop p = 75
(1CZN}Flg. Ex. 2.25.2 (a)

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l'1 Analog Electronics (MU-Sem.3-Electrical) 2-67 Bipolar Junction Transistor

Ex. 2.25.3 : Draw DC load line for the circuit shown in ► Step 3 : To draw DC load line
2 25 3
Fig. Ex. · · · Re= 2.65 kn Re= 4 kn Apply KVL in c-loop [Fig. Ex. 2.25.3(a)], Write it in
the form of y = mx + C,

Vee= 10v
where y =le and x =Yca·
+
Yee-le Re -Vea =0
~ = 100
y

(1C237) Fig. Ex. 2.25.3 Module

Two points for DCLL can be obtained as follows :
@ Soln.: :. With le = 0 Vca = Vcc = 20 V
► Step 1 : Circuit diagram Yee 20
Re le and Yee = 0 le = Re = 4k =5 mA
+
le L. l
Vee= + f' 1 (mA)

10V
·----~---·
I I Vee=.
20V

E-loop C-loop

(1C231) Fig. Ex. 2.25.3(a) DCLL slope = _ _j__ = _j__

Re 4kn '
► Step 2 : Find le .
Apply KVL in,E-loop. Fig. Ex. 2.25.3(a) .
0 10 VceM .
-Yee - le Re+ VEE = 0
- Yee+ Yee -0.7 + 10 mA
le = Re 2.65
(1C239)Flg. Ex. 2.25.3(b)
le = 3.51 mA ~ le

Part (C): AC Circuit Analysis ·

Now suppose you are told to find output ac voltage v0

I 2.26 BJT MODEL OR SMALL SIGNAL -
in the Fig. 2.26.2.
EQUIVALENT CIRCUIT
L
:,.- - - ::;-:~.~L7 7-~ I' - - - : -: - ;. ~ ~- 7•.- - - - - - - - - -:.- - - - -.- ~ - - -1
,Qea• . Wh.~ , •. Is ~el or: small signal equtvalent,
:- . .' cir:cult -? "'
'.. ' -'~. ·. . ; .
•----------------- A-----------------------~
~',, •.
." ..

Suppose in Fig. 2.26.1 it is required to find current I.

- For this, we have many methods, theorems, etc.
e.g. we can use mesh analysis, nodal analysis or (1D1)Fig. 2.26.1
Thevenin' s theorem etc.
- We are able to use these theorems or methods because Here you cannot use different methods or theorems of
we are aware of the behavior of used (two terminal) network analysis.
components (like L, C, or R) for applied de (or ac) This is because the behavior of three tenninal device
signal. BIT is not known to us when ac is applied at the input.

u, __ ._. DI--·-· mr.

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~ A~alog Electronics (MU-Sem.3-Electrical) 2-68 Bipolar Junction Transi·
stor

To overcome this problem, componen ts like diode, . Also for the network shown, if following conditions ::
transistors or FET etc. are replaced with a circuit true:
consisting of R, C, L, voltage source and current ( 1) One terminal from input and one terminal from output
source. should be common.
Thi . . . should
s circuit which replaces the active componen ts is · (2) Components ~sed in two port network (TPN)
known as model, AC equivalent circuit or small have linear characteristic.
signal equivalent circuit. (3) ii and i0 should flow in inward direction of two PCln
network (TPN).
C
Then out of four parameters (ii, io, vi and vo) we can
AC take ii and vO as independe nt parameters and we can
vi
E
write,
(1D2)Fig. 2.26.2: AC equivalent circuit'
vi = I\ ii+ h,. V 0
• •• (2.27.J)
i0 = hr ii + h0 VO ••• (2.27.2)
'a.. 2.26.1 Definition of Modeling Where I\, hr, hr, ~ are known as hybrid parameters.
(II) Can we write equations I and II for BJT ?
Modeling is a mean used for representation of active
devices like diodes, transistor, etc. Models represents Yes, because in BIT circuits, one terminal is common
terminal behaviour of active device by using simplified to input and output port and also if BJT is operated in
or idealized circuit elements suitably interconnected. active region, it will be a linear component.

lf model of a device is too simple, it will not accurately (Ill) Exact h-model for CE configuration
predict the performan ce of device.
On the other hand if model is too detailed, it will be
C
complicate d and also difficult to use.
Hence model should be accurate enough to predict
E
essential feature of device performance and it should be
simple to be used quickly.
(1D4)Fig. 2.27.2
J 2.27 HYBRID PARAMETERS Considering Equation (2.27. l) and (2.27.2) _above, for
(h-PARAMETER) CE configuration of BIT, we can write.
----------------~----------
I Vbe = hie ib + hrc Vcc •.• (2.27.3)
! GQ. Write a short note on : Hybrid parameters. ... (2.27 .4)
ic = hre ib + hoe vcc
: UQ. Write a short note on : h-paramete r model.
where 1\ 0 , h.-c, h,e and hoe are hybrid parameters defined
'·I (MU - a. 6 . Ma 14. a. G(a). Ma 19. 5 Marks)
for CE configuration. Suffix 'e' represents common
~---------------------------------------- emitter.
(I) For the TPN (Two Port Network) sh~wn In
Hybrid parameters for CE are defined as follows :
Rg. 2.27.1.
io and 4 are ac output and input currents. l\e =
V1,c 1 • AvBE I
vo and vi are ac output and input voltages respectively. 7;;"" vcc=O = Ale .1vcE=O

i1 --------, io
= vbe
1b
I
outputshoned
1wo Port Network Vo
(TPN) = Input resistance for common emitter
with output shorted or V CE constant.
Common It is measured in ohm.
(103)Fig. 2.27.1
Range is l W ro 3W.

Tech-Neo Publicatiom.- ..-- Here Audlon i,upire ianov6tioa _..4 SACHIN SHAii Ye111Jdf
 [i1 Analog Electronics (MU-Sem.3-Electrical) 2-69 Bipolar Junction Transistor

ftte =
ic
~
I Mc
= Me
I &VcE=O
ic
=~
I
outputshoncd = ~
J 2.28 EXACT HYBRID MODELS FOR
vcc=O
BJT
= forward current transfer ratio defined ;---------- ---------------~---------------
Draw h-parameter model for Cp C and Cc
: GQ. 8
for commo n emitter, with output shorted .
I
transistor configurations.
➔ h,e doesn't have a unit. I

: UQ. Write a short note on : h-parameter model.

➔ Range is 20 to 300 I
(MU - a. 6. Ma 14. 5 Marks)

hre = vbe I ilVeE

= ,1_ VCE
I 419 = 0 = Vcc
vbe I
input open
·-----------------------------------------
Module
V cc ib = 0
a. 2.28.1 Hybrid Model for CB
= reverse voltage transfer ratio defined for common f 2 <;■
Writing hybrid equations assuming ie and vcb as
emitter with input open.
independent parameter (Fig. 2.28. 1), we get
11111111
➔ Doesn' t have any unit.
4 V,b = ¾ ie -+:- l\t, vpb ...(2.28.1)
➔ Typical value 2.5 x I0- •

ic = hfb ie + hob Vcb ... (2.28.2)

ib=O r - - - - - - - .

r•.
Measured
Common
_ r-J
_l_tte
be--..._ _E_m

Applied by
t } ~. E
ie
•
ic

us L Common terminal
(1D5)Fig. 2.27 3 : Set up to find ~
(106JFig. 2.28.1

hoc =
ic
V cc
Iib = 0
Mc
= i lVCE
I419 = 0 = V cc
ic I
input open
Converting Equations (2.28.1) and (2.28.2) in circuit
we get, Fig. 2.28.2 and Fig. 2.28.3.
= output admittance for commo n emitter with input
open. Measured in "rnho". ic
ie h1b
+
➔ Typical value 25 µA/V. +T + 1
➔ I/hoe is output resistance of commo n emitter, hob
Vcb
Veb
➔ Typical value is 40 k.Q.
➔ Range is 40 to 80k.Q.
(1Dl)Fig. 2.283
r---- ----- ----- -- - ----- ----- ----- ----- - --, (1D7)Fig. 2.28.2
: GQ. Can w~ for <ftffe~nt :
h-parameters
use I
hib ic C
I
COf)fig4rations (CE, CB and CC) of transis tor? _ .! E ie +
•
~--------- ----------------------------- +
+ +
Yes
1
That is because one terminal of transistor in different veb vc:b hob
vcb

configurations is commo n to input and output pOrt and

also transistor can work as linear device. (If operated in B B
active region with small signal)
(1Dl)Fig. 2.28.4 : Exact h-model for CB
Since conditions required for h-param eter is satisfied,
we can use h-param eter for BIT. Combining Fig. 2.28.2 and Fig. 2.28.3 and making base
When h-parameters are used for BIT then depending common (CB), we get exact hybrid model for CB.
upon configurations we can add suffix e.g. "e" for CE (Refer Fig. 2.28.4)
<hie,~. hre• hoe, etc.)

._.,4 SACH/N SIUH Ye11ture

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 Analog Electronics (MU-Sem.3-Electrical) 2-70 Bipolar Junction Tran.,;
..,stor
:-
Converting Equation (2.28.3) and (2.28.4) in ci rcu11
1
•Note: .
and making E terminal common, we get exact model.

Ii
I
1. When we define a, we take actual direction of curre~t

positive.
ic
'• (outward) and ic (inward) i.e. a = i . Therefore a is e
+
B ib
+
h;e ic C

1
2. But in hybrid model we have to follow the vbe hoe
Vee

rule that both input and output current should

flow inward (Fig. 2.28.1 ). Hence i8 is in
opposite direction to actual current. E E E E
3. This is the reason hlb, hybrid current gain is
(1D12)Fig. 2.28.6 (IDl3)Fig. 2.28. 7
negative (- ve) .

B ib h;e C

+ +
Range for different parameters are as shown in Table 2.28.1. 1
Vee
vbe hoe
~ Range for Different Parameters
Table 2.28.1
Range E
Parameter E
(1D14)Fig. 2.28.8
h;b ➔ Input resistance of CB 20Q to I00Q

hfb ➔ Current gain of CB (a) - 0.95 to - 0.98Q ~ Range for Different Parameters

IMQto3M Q Range
tf- ➔ Output resistance CB (r 0
)
Parameter
ob
hie ➔ input resistance of CE I kQ to 3 kQ
hrt, ➔ Reverse voltage transfer Typical value
➔ 2 .9x 10-
4 hre ➔ current gain of CE(~) 20 to 300
ratio
.
hI ➔ output resistance of CE
40 kQ to 80k.Q
~ ~2.28.2 Hybrid Model for CE oe
r----- .- --,- ~,-: -,-: . .,,-:-: - ----- . - -- ,.. -- '"I
I GQ. braw smaifsignai hybrid parameter equivalent : ~ ➔ reverse voltage transfer 1.5 x I0-4 to 2.5 x I0-4
: clrcuiHor CE.amplifier and define the same. .. : ratio
: UQ. ·oraw and explain the h-parameter mode/ of .B~.T :
and derive the expression .for Av, ~. R,. Consid~r :
,.
I
. '
• I
I
~ 2.28.3 Hybrid Model for CC
1 CE configuration. d

I MU - a. s a. Dec. 18. 10 Marks. a. 6 a . Ima 19. 1 Writing hybrid equations assuming ib and vrA
: ____ }iiWffld _'" , _,: . " -· . ---··-·--- ~ ---- ~ .J independent parameters we get,
Assuming ib and vcc as as independent parameters, vbc = I\: ib + l\c Voe ... (2.28.5)
hybrid equation for CE can be written as, ie = lire ib + hoc Voe ... (2.28.6)
... (2.28.3)
vbe = ~e ib +~Vee
...(2.28.4) ie E
jc = hre ib +~Yee

ic E
B ib
Vee
C B
B jb C

Vt,e
B
E
Vee vbc
C l
C C
E
E t E (1D15)Fig. 2.28.9
Common tenninal
(1D11JFJg. 2.28.5
['1
- Analog Electronics (MU-Sem.3-Electrical)

Converting Equations (2.28.5) and (2.28.6) in circuit

we get,
2-71

l(i" Range of Different Parameters

Bipolar Junction Transistor

hie Parameter Typical value

ie E
hie ➔ Input resistance of CC 1 to 6.5 kQ
+
+ 1 40 kQ to 200 kQ
1
Vee
hoc ➔ Output resistance of CC
vbc Vee hoc
hrc➔ Reverse voltage transfer ratio =I
C C C C hrc ➔ Current gain of CC - 50 to-250 Module
(1D16)Fig. 2.28.10 (1D17)Fig. 2.28.11
11
• Note : When we define current gain of CC as y then
ie E actual direction of current is taken. : . y = ~ is positive.
1 ..
B
+
+ But when rule for hybrid model is used, we have to take
1
vbc Vee current i8 flowing inward (which is in opposite direction to
hoc
actual current). Hence h,c is always negative (- ve). i.e.
- ic
C C h1c=---
1b

(1D18)Fig. 2.28.12

I 2.29 HYBRID MODELS AND EQUATIO~ IN TABULAR FORM

Configuration Circuit Exact Hybrid Model

Common ie C B jb hie ie
Equations +
Emitter +
C Vt,e = hie ib + h,., Vee
B ib 1
Vee Vbe Vee
B ic= hre ib + hoe Vee hoe
vbe E
+
E *
E E
11020)Fig. 2.29.l(b)
(1D19)Fig. 2.29.l(a)

E hib ie ie C
Common Base
ie ie - Equations +
• • +

} I +:
Veb= h;b ie + ~ Vcb
jc = hlb ie + hob V cb
Veb
+ 1
hob
vcb

!
11021)Fig. 2.29.l(c) B B ·e
(1D22)Fig. 2.29.l(d)

Bib hie ie E
Common ie E Equations +
Collector +

E Vbc = h;c ib + hrc Vee 1

ib vbc Vee
B hoc
Vee je = hrc jb + hoc Vee

vbc
B
C
i !
C C
C C (1D24)Fig. 2.29.l(f)
(1023)Fig. 2.29.l(e)

·
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['1 Analog Electronics (MU-Sem.3-Electrical) 2-72 Bipolar Junction Transistor

I 2.30 CONVERSION OF HYBRID MODEL OF

Ii CE AMPLIFIER INTO APPROXIMATE MODEL

: GQ. With proper approximations explain step by step, how :I

I

: can you convert exact hybrid model of CE ampllfier : RL=

10 kn
into approximate model.
~---------- -- ------ ---- ----- ------ ----------·
¢ Step 1 (a) CE ampllfler
Draw circuit diagram of CE amplifier and also draw AC
equivalent circuit with exact hybrid model. (Fig. 2.30.1(a), (b)
i.
1!
ti
I
and (c)) C

Re RL
TVo
Step 2 : Approximations B
¢ +
. I
(a) Resistance R~ = (RL II Re) is always in parallel with hoe '
V;
♦
E
l
(b)AC equivalent circuit by shorting DC
1
Since R is much smaller than _hi in approximate analysis rn
L oe V
f oe
is neglected.
1 R' L
u• Note : , A~= AL II Ac if AL is given, o~herwise A~ = Ac; . · hoe =1.67 kn

(b) l\eVce = l\eVo=l\e jc R~ (c) AC equivalent

= l\e ( hfe ib ) R~
(1D25,26,27)Fig. 2.30.1
h;e C
Using typical values of hre and hre with ib in µA , we get
3 Short Open v~
= 2.5 X 10- 4 (50 X 10-6 ) X 10
7
h
ce
' 're V
= 2.5 X 10- : 0 E E

Hence 1\-e vce can be shorted.

¢ Step 3 : Using above approximations model will be as

shown in Fig. 2.30.2.

E
(1D28)Fig. 2.30.2: Approximate model
-
•NOTES•
-
--
--
--
~
----
- - - H•.A SACHIN SHAH Yea/lift
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[ii] Analog Electronics (MU-Sem.3-Electrical) 2-73 Bipolar Junction Transistor

j 2.31 UTILITY ADVANTA GE AND a. 2.32.1 Determination of h,e

DRAWBACKS OF
We get h c by drawing a line tangent to the input
h-PARAMETERS 1
characteristic curve corresponding to Vceo at Q-point.
r------- ----------- -------~ The value of parameter h1c is given by the slope to this
,I GO, explain utility of h-parameter.
I
line.
: GO, Write advantages and utility of h-parameters. Also : In other wo{()s, h;c is the ratio of small change in the
write some important drawbacks of h-parameters. ' value of emitter base voltage to the small change jn the
: GQ. Wha~ ar~ the advantages of h parameters·? , value of base current around Q-point.
-~----------- - ------------------------ --- I
a" Advantages of h-parameters
[ J8 (µA) v/s Vee(V)
J. h-parameters are real numbers at AF (20 Hz to 18 (µA)

2.
20 kHz).
Since hybrid model of transistors 'consists of all linear
1 .J .i. i . , V C ' Vee a Vee~
VcE2
elements, if transistor is r~placed with this model,
analysis of transistor circuit becomes easy by KVL,
KCL, etc.
3. h-parameters are easily obtainable from static
characteristics of transistor. ·
4. h-parameters are normally specified by most of Bias line (DCBL)
transistor manufacturers. .... .. ~· .. ~- ·)

5. At low frequency and mid frequency , reactance offered ... - - · - -+---- ! --

ee ,.--l
by internal capacitance of transistor is very high.
Therefore they will not affect transistor operation,
VBE ~ Vaeo 'vB~2 · 1-- .Vsg02
Determination of h18
Because, h-parameter model is purely resistive model,
therefore is valid for low frequency and mid frequency (1D29)Fig. 2.32.1
both.
Therefore value of h;. wi11 be given by,
IGr' Disadvantages of h-parameters

Since h-parameter doesn' t take internal capacitance of

VBEI -VBE2 I
1. h,e = I B2 -IBl VCE = VCEQ
transistor into account, it is not suitable for HF
analysis. hie =
ll.VBE I
fl.le VcE=VcEQ
2. h-parameter changes with change in temperature, with
change in Q point and with change in device.
a. 2.32.2 Determination of h ...
3. h-parameter model cannot represent an actual
operation of transistor. A horizontal line is drawn for 18 = IBQ·
Then change in V BE is detennined for small ch".mge in
I 2.32 GRAPHICAL DETERMINATION
VcE·
Of h-PARAMETERS
The h,0 is given as,
~---------- ------------------------------~
: GQ. Explain Graphical determination of h-parameters.
: VBl!2 -VBEI
fl. V BE I
: GO.
I
Determine 'h' parameters using Input and output :
I
h,e =
VC E2 - V CB I I e ~ eQ = fl.V
1 1 CE 18 = 1 Q
8
: characteristics of CE transistor. :
L. ____________ _____ • • • - - - - - - - - - - - - - - - - - - - ~

The first step to find h-parameters is to determine the

Q-point.

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!il Analog Electronics (MU-Sem.3-E lectrical) 2-74 Bipelar Junction TranSi$10r

'a.. 2.32.4 Determination of hoe '

Ii
J8 (µA) v/s V8 eM

(Refer Fig. 2.32.4)

I

;. I
h is obtained by finding slope of output charac•....: .
~
around Q point, with Ia = Iao·
-~
I
i
------- - .--·--·--·-t
.i Afc
'I h~ = /lVCE Ia=IaQ •
... I
l

I l ,

DC Blas line -· -~
,-· I , , -t ·1· +--;
. -+-1·· 6VeE ~ -•· • r,·· ·
! I . I I I

-· .. ...' ·- ···- ....

\
l L
(1D30)Fig. 2.32.2

~ 2.32.3 Determination of h,.

Draw a vertical line correspondin g to VCEQ·
Talce a small change in Ia (i.e . .rub). (1D32)Fig. 2.32.4

Find correspondin g change in le· (i.e . .rue). ) 2.33 HYBRID - 1t OR 1t • MODEL OF

Ie2 - le, I Afc I BJT
hr. = Ia2 -Ia, vcE=VcEQ = Afa vCE =VcEQ
~ 2.33.1 Key Points
(Refer Fig. 2.32.3)
Before we start developing 1t-model of BIT, some important
points to be considered are as follows :
(a) If a junction is forward biased then current flowing
through junction is given as,

I = Is exp~ with T) =1 ... (2.33.1)

T
I

~
VT = 26 mV (thermal voltage)
f. 1e2 · Is = Reverse saturation current V
or lealcage current. 11032A)Fig. 2JJ.l
.~le lea -
(b) When transistor is in forward active region, lsE is
!:le( •
forward biased; then using Equation (2.33.1).
.
IE = Is exp
(V95)
VT
... (2.33,2)

Veea · I Vee(V)
I ..•
.. •-· - ·-

(1D31)Fig. 2.32.3

(1D328)Fig. 2.33.2 _..-:

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~ Analog Electronics (MU-Sem.3-Electrical) 2-75 Bipolar Junction Transistor

(c) Since we have seen that during operation of transistor, ~ 2.33.2 Step by Step Development .of h-n
ic = ex iE Model
therefore using Equation (2.33.2)
-------------------------------------- -·
GQ. Draw and explaln small signal hybrid-Pl model of
BJT including early effect .
ic = a Is exp ( ~;) . . . (2.33.3)
GQ. Draw small signal hybrid n equivalent circuit for npn
ex ➔ DC current gain of CB configuration transistor.
ic GQ. Explain the Hybrid pi model of BJT.
(d) Since we know i8 = f3 then using Equation (2.33.3) GQ. Draw and explain hybrid--n: common emitter
,_____ transistor model. _______________________ _
ic ex (VBE)
i8 = 13=j315 exp VT . . . (2.33.4) ¢ Step 1 : For the transistor shown in Fig. 2.33.4 if we
look into B-E terminal of BJT, we see JBE
13 ➔ DC current gain of CE which is forward biased.
(e) Fig. 2.33 .3 shows an exaggerated view of the current Therefore at input we see a resistance r 11 , Refer
voltage characteristic with V BE constant. Fig. 2.33 .6, which is Sl~pe of input characteri~tics of CE
transistor. Refer Fig. 2.33.5.
i . ic(mA) . : : .. . 1l:Vc~(V) vis Ic(m~ )f
~-·,·-·········· ..-·····;······ ,-······ >··-··•------r----•:·-··--·r--~ _-· ---··· -~;·-----, -----1------;
L VBEJ o ; lej B ib
Vee
,,; ,, ,,.,,,, '
,,,_,~,
vbe
r ·•
.
; · Extrapol~ted : .,
.

i
..,,,., ,----·+----· ; E E

·~-+=:1-::;;;1:r~
- Ve~ -VA ;
VBE1 or 101

, VcE(V) That is
1 i)i 8
(1D35)Fig. 2.33A

.1 le I .,.(2.33.6)
(Early voltage
rn =dVeE Q point = .1 VBE Q•point

+50 to 300V)

(1D33)Fig. 2.33.3 From Equation (2.33.2), iE= I. exp (;TE),

We know as V CE goes on increasing ic increases due to
Since iE = ( I + 13) i 8
early effect.
When the current in the characteristics are extrapolated ie = (1 :• 13) exp( ;TE) ... (2.33.7)
to zero current, they meet at a point on the negative
voltage axis at V CE= - VA·
The voltage VA is positive quantity, called as Early (~) ·.__,__;,.,....,,.,,...,,,_;,:IY~e(V)v/s I9(µA)I
voltage. It is of the range 50 < VA < 300. . -.;.. ··--··r .... ... ---- -~
(f) Now current ic taking early voltage into account can be
written as,

ic = a Is [ exp• ( ~;) ] ( 1 + J:) I Q point

, ... (2.33.5)

where, 18 and ex are constant.

(1D34)Flg. 2.33.5

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 -~--A•n•a.log=.iiEiiiilect~ro~nic~s~(M:;U~-~s::e~m;.3~-.;E!:;le~ct~ri~ca~I~)---...!2~-7 ~6~-------- --~B;::iip~ o~la:r~J~ u:_::nct~i~ 8
on~Tr~an ~1Stor
·
Using Equation (2.33.6) Putting this in Equation (2.33.8) Z:.....
lco
t a:., [o ~ Pl exp(~•)]
=
Q point
i, = v;· v,.

= I. (VBB) 1
x-
(] + 13) exp VT Where, gm is known as transconductanu.
Q point VT
ie = gm vbe indicates that output current ie is controlled
Using Equation (2.33.7),
by input voltage.
l IBQ This indicates that BJT is voltage control device.
rn = VT
This fact is shown in model by connecting current
source gm vbc on output side. As shown in Fig. 2.33.7.
:. rn

Where . ~ =· 13oc and VT= 26 mV (1D36JFig. 2.33.6

at input of CE configuration we see a dynamic (ac)

resistance r11 •

¢ Step 2 (1D38)Fig. 2.33.8

Now for output equivalent circuit.

¢ Step3
We know that output current ie changes with v88 as
Combining input and output circuit we get initial
well as vcE· This can be mathematically written and
hybrid 1t-model as shown in Fig. 2.33 .8.
expanded as (using Taylor' s series).
rue = f (VeE, vcr) ¢ Step 4 : Considering early effect
1: oie In step 2, we neglected early effect. Observing the
+ax !!.VcE
Ole
rue= -0-x AVeE output characteristics in Fig. 2.33.9 of transistor, sl~pe of
VeE ~
characteristic can give output resistance· r0 of transistor.
second term indicates early effect From Fig. 2.33.9,
Neglecting early effect portion.
11.c. J ..... ··•········•·······••I••·······'·· .r·lc~;~V~e.:l--l.
Afc = - oie I XilVeE
. . : ;. .. r·-l
oVeE Qpoinl T : --,--·:

We have, ie = ~ic
OVeE
IQpoint
X /lvbe
.. .(2.3~.8)

from Equation (2.33.6) ic = <X exp ( ~:) x Is

(1D39)Flg. 2.33.9

:. slope= ~
oic I
uV CE Q point

= aSCE [ al,[ exp(•~:•)] (1 +~)] \._.

(1D31AJF'il· 2.33.7
~---::--- =-:-::--: -----:-:; ;;--:-:-;~ ~-:---::- ---- ---------------
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►

Analog Electronics (MU-Sem.3-Electrical) 2-77 Bipolar Junction Transistor

= ex ls exp ( 'jE)IT Qpolnt

x f
A
= ~Q
A
a. 2.33.5 Expanded Hybrld-n-Model
The hybrid model shown in Fig. 2.33.14 includes two
1 VA
slope =• r 0 = lco more resistances .
(I) r or r' ➔ This is series resistance of semicondu ctor
b bb
_ Inclucling r0 in equivalent circuit, the hybrid-1t-model material between external base terminal B and internal
now becomes as shown in Fig. 2.33.10, where r is base region B' Fig. 2.33.15. rb is very small (5 to
0
small signal output resistance of transistor. 1OOQ). This resistance is also known as Base
Model in Fig. 2.33.10 is known as transcondu ctance Spreading resistance.
model.
B ~ ~ C

r" ro Vee
Vee 1 to 3kn 40- 80kn
E
E E
(1D40)Fig. 2.33.10 : Transconductance model

a. 2.33.3 h-n Model with Current Gain (1D45JFig. 2.33.14

Parameter C B E B C
We also know that ic = f3i b. Therefore modified hybrid-
1t-model is as shown in Fig. 2.33.11.

~
r;,,.~~ ±p;, ! ,o·;, ·l
n p n o E'

o B'

o C'

p substrate
(1D42)Fig. 2.33.11 : Current gain model
(1 D46)Fig. 2.33.15 : Cross_section or npn transistor
• Note : The above models (gm and ~ models) ar~
known as hybrid model because the parameters which (2) rµ ➔ Reverse biased diffusion resistance of base
we have evaluated have different u'!lts like , collector junction. This is very high (in M!l), hence
rx-+ n, ~ ➔ no unit,, r0 ➔ '2, 9m -+U. ·
normally assumed to be open. This resistance indicates
the effect of V cc on ib. i.e. change in input quantity due
'&. 2.33.4 Hybrid n Model for PNP Transistors
to change in output. This is nothing but feedback. We '
know very well, this feedback phenomen on within
transistor is due to Early Effect. It means r" indicates
early effect.
Veb v" r" ro Vee

+ I 2.34 APPROXIMATE HYBRID- 1t •

E +
+
MODEL AT LOW FREQUENCY
(1D43)Fig. 2.33.12
ib ic (LF) AND MID FREQUENCY
(MF)

Resistance s rµ _and ro are of high value, they are taken

as open (Refer Fig. 2.33.14).
+L--1 --....L --~-- -+
(11M4)Flg. 2.33.13

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r ~ Analog Electronics (MU-Sem.3-Electrical)

All internal capaci..-• are in pf. Therefore u,eir

2-78

,eactance at low trequency (Lfl and mid frequency

Vt,e
(MF) is very high 1ience they are assumed to be open.
Therefore approximate h-ff model will be as shown in
110S2)Fig. z.35.Z: b-ff model
Fig. 2.34.1 .
Approximate h-model is also given for comparison in

Fig. 2.34.2. _ _--o C

a) h- ==~, . Refer fig. 2.35.2

with vtt ~ 0 (output shorted) as shown

( ie lb Vce"'o
B o---- ])raW h-ff model

I in Fig. 2.35.3 and 2.35.4.

i I~ I E o---.__ --.&.--- -o E
B C

\
v:v r,

E
d gmV•
(1053)Fig. 2.35.3
(1D49)Fig. 2.34.1 : Approximate Mt-model
B o---- _ _.-.n C

(1D54)Fig. 2.35.4

From Fig. 2.35.4,

rn << rµ and
E
(1D50JFig. 2.34.2 : Approximate b-model Vbe :: jb fn

I 2.35 HYBRID PARAMETERS IN

TERMS Of HYBRID-1t
PARAMETERS (RELATION I
(b) hre= ic Refer Fig. 2.35.2,
BETWEEN h AND h-1t 1b Vce"'o

PARAMETERS) . h-1t
Draw . model w,'di Vu = 0 assuming· r11 ve,Y hiil
·1
F'open r, very low (short circuit). ]!.efe
( c1rcu1t) and
1g. 2.35.5.

vbe +
Vbe V11 f 11

(1D51)Fig. 2.35.1 : b-model

- r •" JDDor•lloo
______
(1D55)Fig. 2.35.S ___-:::
....A SACRINsJJA/1 reafllld
Teeb-Neo P bl'iealaone...........
· ere Autlion jnn,j- · .
►

~ Analog Electronics (MU-Sem.3-ElectricaJ) 2-79 Bipolar Junction Transistor

iC =

hte = ~ic I Vce=O = gm r!t = ~ac

Using voltage division rule. Fig. 2.35.8

1---
tire = gm r!t = ~ac I Va,

(c) ~=:be I. . Refer Fig. 2.35.2

ce 'b = 0

r2il
With ib = 0, ib rb = 0. Therefore rb is short. Now h-1t
equivalent circuit will be as shown in Fig. 2.35 .6 .
vn

ic
=

=
(1058)Fig. 2.35.8

--v
rll
rn: + rµ ee
Vee
--+g .--+-
rn: + rµ
Vee r!t

m rn: + rµ r0
Vo,
-
rit
But gm rn: ='3
Vee Vee Vee
--+'3--+-
jc = rn: + rµ rn + rµ r0
(1D56)Fig. 2.35.6
(I + '3)
Now using voltage division rule
ic I = hoc = rn: + rµ
+-
I
ro
Vee ib=0
( I + '3) I
+-
ro

Iib
Since rµ >> rn
1--- ~ - tI
(d) h = -ic
oc Vee =0 c:r Summary
Again with ib = 0, ibrb = 0 . Therefore rb is short. Now h-
1t model will be as in Fig. 2.35.7.

5. hte = P= g,,. r.
1 l+P
7. ro -
hoe=-+ r. +-
r 11

(t057)Fig. 2.35.7

eNOTES•

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r
~ Analog Electronics (MU-Sem.3-Electrical) 2-80 Bipolar Junction Tr
iatar

,i J 2 •36 KEYPOINTS FOR. AC .ANALYSIS '

:·GQ~., ~lve -;- - .- - - - - - - - - - - - - - - - - - - - - - - - - - 7 - - - - - - - - - - - - - - - - - - - . - -: - - - - .- - - - - ,.. - - - - - - - - - - - _
•_____ ..: __ -~ _ ~~ps to find output in,pedanc.e,of any two pPrt network. . •
-------------~-----~------ ~------------------------ ~~ -~---~------- - - ._..,
--, I

+Vee

Source R1 Re
resistance +Vee

( Rs R1
Ce1 ·

1
B

'\., vs
R2
RL
~
Load
resistance
r
vi
R2
Vo

Bypass capacitor

(1E1)(a) RE byp~, source and Load Resistances (1E2)(b) RE unbypassed (without C,:) without source and
(Rg and RJ present Load resistors

Fig. 2.36.1
To find output impedance of any two port network (TPN). Following are the steps :

Short (Vi= 0)

(1E3)(a) (1E4J(b)
Fig. 2.36.2

Remove RL (Load Resistance)

► Step 1
Short input (i.e. V; = 0 or Vs = 0)
► Step2
Apply known voltage (Vx) across output terminals.
► Step3

► Step4 Measure Ix
vx
Now, Z 0 =-1-
► StepS X

Refer Fig. 2.36.2.

. -. -~~ - - / .I"; - - ,. :- -: - - - .- - • "':" ,,.. - , ' , . .
-------------------------
----, I
:"oa. . How-to -dr~w MF AC.equlval.ent,drct.1lt-?, · . ·. ;
I

·----- -· ------------------------------------------------ - - - .: ._ • ..;, - - - - - - - - - - - - - - - - - - - - • J

To draw AC equivalent circuit :

► Step 1 : All D_C sources must be shorted.

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>

~ Analog Electronics (MU- Sem .3-Electrical) 2-81 Bipo lar Junction Tran sisto r

frequency (MF) their

capa citor s) must be short ed because, at mid
► Step 2: All capa citor s in µF ~coupling and bypa ss · ·
react ance is very smal l (in ohms ).
frequ ency (MF) their
BJT) must be open. This is beca use at mid
► Step 3 : All capa citor s in pF (inte rnal capa citor s of
react ance is very high.

► Step 4 : Repl ace trans istor with its AC model.

table 2.36.1 ).
Step s to draw AC equiv alent circu it (Ref er
Circu it
Tabl e 2.36.1 : Steps to draw AC equivalent

sr. No. Amplifier with RE bypassed Amplifter with R~un b~

' Circuit given
(a) Circu it given

Rs Ce1

(1E12)Fig. 2.36. 4
(1E5)Fig. 2.36. 3
name d _and
n separately. Draw given circu it'wit h all powe r supp lies
(b) Draw circu it with all powe r supplies show
shown properly.

Vee
Vee .I. R1 Vee +
W'

Rs Ce1
RL
B
µF ~

R2 Ce

(1 Et 3)Flg. 2.36. 6
(1El)F lg. 2.36. 5

Neo publicah.on•-· -··-- W/,ert! Authon in1pirt1 innon

,tioa -A SACH/N SHAH f'eature
-T~-L-
,;ai
r
!i1 Analog Electronics (MU-Sem.3-Electrical) 2-82 Bipolar Junction T
.ransist
Sr. No. Amplifier with R6 · bypassed
·-
Ampllfter witbR
. Eu
nbYJ>lissed ~
~I
I
(c)
Short all DC sources, short capacitors in µF, open
capacitors in pF.
Short all DC sources, short capacitors which
.
seen (µF), open all unseen capacitors (pF).
can be

:
R1 Re
~ Short
Short
Rs

'
Rs C
RL B
B
E

'v vs "v Vs
R2 -Short R2 RE

~ '= y ~

(1E7)Fig. 2.36.7 (1E14)Fig. 2.36.8

(d) In this circuit, Re and RL are in parallel will be In this amplifier, (Re II RJ = RL' will be connected
connected between C and GND. E will be directly between C and GND. E will NOT be connected to
connected to GND (Re gets bypassed). R 1 and R2 in GND. Re will be between Eand GND.
parallel will be between B and GND.
(e)

Rs C

B
E RL'

(IE8)Flg. 2.36.9
(1El5JFig. 2.36.10
Where, R8 =R 1 II R2 and RL' =Re II~
Where, R8 =R 1 II R 2 and RL' =Re II Rt_

(t) Replace transistor with given model. (Suppose model Replace transistor with given model. (Suppose given
given is in transconductance form) model is in current gain form).
B C
B

E E
(1E9)Flg. 2.36.11
(1E111)Fig. 2.36.12

-=--::-:-:~-:--;:----::-- When: Authors inapin: innovation - - -- -- --

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~ Analog Electronics (MU-Sem.3-Electrical) 2-83 Bipolar Junction Transistor

Sr. No. Amplifier with R8 bypassect Amplltler with R8 :unbypused

Tran scon ducta nce fonn of h-1t mode l Curr ent gain fonn of h-1t model
C
Rs
C

Rs
R'
L
Rs
R' Module
r2_..
L
Rs

2.36.13 (IE17 )Fig. 2.36.14

111111111
(IEIO )Fig.

(g) Draw circu it prop erly Draw circu it prop erly

Rs Is B C
Rs C
r"

(1E11)Fig. 2.36.15

(1E18)Fig. 2.36.16

l, but if ~ is unby passe d, it is

we can use transconductance form of h-1t mode
(h) If given prob lem is with RE bypa ssed,
model.
conv enien t to use curre nt gain form of h-1t B, it is multiplied by (1 + P) or
h IE is flowing) is transferred from E to
(i) Whe neve r a resis tanc e (through whic
tance in Base (through which le is flowing).
(1 + h,J and is conn ected in series with resis
Fig. 2.36.17.
Proof : Appl ying KVL in the loop show n in
le Is
+ ---------.
--- .. + I

:I r"
I
I Is
~-----,,+
I

l
I
RE (1 + 13)Re
I
.., ____ ____ 1- IE

Zs Loop
(1E20)Fig. 2.36.18
(1Ef9)Fig. 2.36. 17: Impedance seen at base
l +l3) RsJ= leZe
V; = ler,.+I BRE =le r,.+ (l +l3) leRs =le[ r,.+(
Z8 = Resistance in base + (l + 13) (Resi stanc
e in Emit ter)
Where, z8 = r,. + (l + 13) RE ;
E, it is divid ed by (1+ l3) and is
Whe neve r resis tanc e (thro ugh whic h le is flowing) is transferred from B to
(j) 8
connected betw een Emit ter and GND .
Proo f for this will cove red while dealing with
ac analysis of comm on colle ctor amplifier.

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 ~ Analog Electronics (MU-Sem.3-Electrical) 2-84 Bipolar Junction Tranatst
Or
I 2.37 SAMPLE EXAMPLES ON DC
AND AC ANALYSIS OF CE
AMPLIFIER WITH Vee -i
+
R1

GUIDE LINES (GL)

Ex. 2.37.1 : For the Fi g. shown in Fig. Ex . 2.3 7. 1

Calculate :
(a) Q po int
(b ) Find small signal hybrid-n and hybrid parameters.
11
I (c) Find input and output resistances.
i
(d) Calculate voltage gain
(e ) Find current gain .
(f) Draw DC and AC load line.
B
+Vee= +sv Vee

R1=
6kll

Rs= 0.2k.Q G
Rth = Rs
Vth =V
(1E22-23)
Fig. Ex. 2.37.l(a) and (b)

Thevenising the circuit on LHS of BG.

J3 = 180, r0 =oo R8 = Rm = R 1 II R2 = (611 1.5) k = 1.2 k

R2 5
(1E21)Fig. Ex. 2.37.1
V = V th = Vcc . RI + R2 = 7.5 X 1.5 = l V

Now DC equivalent circuit for further analysis will be

@Soln.:
as shown in Fig. Ex. 2.37.l(c). lea
r:r DC Analysis
+
DC analysis to find Q-point ( VcEQ and lco) Re= . ----~
► Step 1 : Draw DC equivalent circuit. (Refer 1 kn ''
''
Fig. Ex. 2.37. l(a) & (b)). For this open all i---..o v : '
capacitors and Connect all DC sources le Re = 1.2 kn Ve
+t Ci t
named properly. VcEa : +
+ + B

*v)
Vee
.,__--a
+

---
''

B-loop C-IOOP
(1E24)Ftg. Ex. 2.37.l(c)

k Tech-Nfle PUu,- I__•.

OIU- .. , .....
1/11,ertJ Autl,on i111pim innor•liua
 Bl olar Junc tion Tran sisto r
['1 Analog Electronics (MU-Sem.3-Electrical 2-85

-
e r GUIDE LINE ► Step 3: AC ANA LYS IS

To find lco· we can use direc t form ulae r:r GUIDE LINE

Tota l know n volta ge in Buse loop Ask ques tions in mind ?

ce ih Emi ller) Is RE bypassed ? OR
leo = Resistance in Bus e+ ( I + t}) (Res istan
Is c,,. conn ected 'l OR
i Is E conn ected to GND for AC ?
MUG UP!
If answ er is YES, draw 3 lines .
Apply KVL in 8 loop
If answ er is NO, draw 4 lines.
V - VBI, I - 0.7 B C
Ieo = R 8 + ( I + J3) R 6 = [ 1.2 + I 81 x 0.1 ] kQ C
B
E_...,.._ E
= 0.0155 mA =IBQ
~ = l3 I80 = 0.0155 mA x 180
E
= 2.79 mA = ICQ •E •
E

lEO = I8 o + lco
(1E21)(e) For RE unbypassed
= 2.8 mA =IEQ (1E25)(d) For RE bypa ssed
Fig. Ex. 2.37.1
= Total know n voltage in C loop - Drop acro ss
V CEO
lines .
Re - Drop acro ss RE In our case , RE is bypa ssed . '!'herefore 3
i For following step s : Refe r Fig. Ex. 2.37
. I (g).
MU G UP!
es.
► Step 4 : Draw mod el. Writ e tenninil-1 nam
= Yee - IcR c-IE RE thing s : volta ge
► Step 5 : Com e on base side . Writ e three
VeEQ = 5 - (2.79 X 1)-( 2.8 X 0.1)
= 1.93 V (V), Curr ent (le) and impe danc e seen at base
(Ze) -
side. Writ e two
VCF.Q = 1.93 V ► Step 6 : Conn ect Re = R 1 II ~ on Base
things (Zi and V;).
.. Q-point = (VeEQ• lco) =(1.93 V, 2.79 mA)
r r:r GUm E LINE
► Step 2 : Calc ulati on for trans istor para mete
VT 26m V Plea se refer Fig. Ex. 2.37. l(f).
r,. = I80 = 0.0155 mA defin ed.
If R 5 and Vs are give n then Is and Ii ·can 't be
= 1.67 k.Q = r,. also ~ ~ r,. = 1.67 kil To defin e I; and Is , we will have to
conv ert volta ge

sour ce (Vs , Rs) to curr ent sour ce (Is, Rs)

Ip = 180 =~ !"Given
lco 2.79 mA
gm = VT = 26 mV

= 0.10730 U or 107.3 mA N

,0 =-given/t=•.=-1
.. r,. = h1, = 1.67 kQ, 13 = hr, = 180 (1E%71F1&, Ex. 2.37 .l(t)

► Step 7: Com e on colle ctor side. Con nect Re

I and RL.
glll = 107.JmU , ro = hoc =00

o JdtH> t'llion .....,4 £4CHJN SHA// Yeature

Teda-Nti11 Publica1ion1..,........ 111/,ero Autlion ia1pir
 ['1 Analog Electronics (MU-Sem.3-Electrlcal) 2-86 Bipola r Junction Tra .
118iator

~j
er GUIDE LINE
If RL is
·. given,
· ~ flows throug h R , Otherw ise throug h
z:
Z 0 =lki l
"
~- 1
.
and = z 11 RL= I kQ II 1.2 k .
0

z: .
I

Using a.II steps from 3 to 7 und GUIDE LIEN . Now = 0.545 kil
AC equiva lent circuit t·or given· amplif ier is ready in ► Step to: Voltag e gain
Fig.' Ex. 2.37. l (g).
Rs r:r GUIDE LINE
7ttl If source (Rs and V5 ) is given then find
- + VO _Vox -V'
tRL
lo +
Vo Avs = v'; = V; Vs ... (I)

If R and Vs not given then find

Z;n Z;
E
zo
7Z'
0
s

Av =
Vo
V. I

(1E28)Fig. Ex. 1.37.l( g) : MF AC equivalent circuit of given Using Equati on (I), voltag e gain with Rs can be
amplifier- V;
► Step 8 : From Fig. 2.37. I (g) written as Avs = Av X
s
v·
Rs
Zs = r" = 1.67 k.Q From Fig. Ex. 2.37.1 0), using PD formul a

zi =
=
=
R 8 11 Z 8
( 1.2 II 1.67) k.Q

0.698 k.Q
For~ Refer Fig. Ex. 2.37.l (h)
£D Zin

(1E29)Fig. Ex. 2.37.l(b)

rO I
Z;n
Rs

Zin = Rs+ Z; = (0.2 k + 0.698 k) (1E31)Fig. 2.37.l( j)

= 0.898 k.Q zi z,
► Step 9 : To find Z 0 , short input, remove RL, apply = Z; + Rs Vs = zm Vs
known voltag e V x across output terminals and
measu re I,,. zZ; and Equati on (1) becom es

I~
ID

Zo = I AyX ~ MUG UP!

•
with Vs = 0, Is = ~ = I8 = 0 Now for given proble m Fig. Ex. 2.37.1 (g), the polarity
of output voltage due to I anct polarit y of assumed Vo arc
0
:. V" = I8 r" =0 opposi te.
gm V" = 0 . It means curren t source open :. With V0 we will have negati ve sign.
r:r GUIDE LINE
Theref ore from diagra m (Pig. Ex. 2.37. I(i)).
lf curren t source is g V then
m "
talce formul a for V; and V such that
Current O

source open Re it contain V" in it. But if curren t

source is Pl8 or h,clo, the formu la
for V 1 and V O should contai n 1 in it. 9mv,.
8
(1D2)Flg.Ex. 2.37.t(k)
(1DO)Flg. Ex. 2.37.1(1)
In our case VO = - gm V" R~ (Refer Fig. Ex. 2.37. I (k))
-Tedi-Nw
----Publica
---= :--- :--.- -:-- --:~ =-::--- - - - - - - -- - - - --- ---: -:-: ----

b_ tion• .........- 11'/,l!l't1 ,4ull,on iuNpire iu11on1tiou _•..,4 SA CHIN - Sll4ll Ye•hll'
>
l§iJ Analog Electronics (MU-Sem.3-Electrical) 2-87 Bipolar Junction Transistor

-- and V; = Vn
Vo -gm Vn R1,'
:. Vo= - gm V; R1,'

Av = V. = I

= _ gm R~ =- 0. 107 x 0.545 kQ
Z; , Z1 (1E35)Flg. Ex. 2.37.l(n)
and Avs = Av X z. tn
= - gm R1, X -Zin
Using current division Rule, Fig. Ex. 2.37.1(n)
0.698 XV(
= - 0.107 X 0.545 X I OJ X _ _ ___:__ Rs 11 Rs
.. . (4)
0.898 XV( l1 = R S + zI x Is Ts = Rs+ Z;

1~s = -45 .32 1 Substituting Equations (I), (2), (3) and (4) in (A),
lo Re Ra Rs
► Step 11 : Current gain A,s = -Is = Re + R L x ~ x R B + r" x •--s o + z I

r:r GUIDE LINE 1 1.2 0.2

Io Io = 2.2 X 180 X 2.87 X 0.898
If Rs and Vs given, find A,s = ""i; otherwise A 1 = ""i;"
➔ Result (A)
AIS = 7.62
In our case Rs, Vs is given, therefore we find A,s·
er GUIDE LINE (Shortcut for A 15 )
First method to find A1s
(Refer Fig. Ex. 2.37.l(f) and (g)) Io
A,s =
Io Io le Ia I; Is
A,s = Ts = 1~? Ts r; Ts X X
... (A)
( VO ) ( Rs) ( Vo) Rs
= RL X Vs = Vs X RL

Rs
A,s = IAvslXR +- MUG UP!
L

0.2
(1E33)Fig. Ex. 2.37.1(1)
A,s = 45.32 xl.2 = 7.6

Using current division Rule, Fig Ex. 2.37.1( l) ( Wow ! Same 8$ result (A))
Re lo Re ... (]) ,
Io = Re+ R1, x le .. le = Re+ R1, Ex. 2.37.2 Draw circuit diagram of common emitter
amplifier with voltage divider bias with bypassed emitter
le
... (2) resistance and derive expression for voltage gain, current
le = ~18 and T= ~
B
gain, input resistance, output resistance using hybrid-1t
model which includes early effect.
@ Soln.:
► Step 1 : Circuit diagram
Refer Fig. Ex. 2.37 .2(a).
(1E34)Fig. Ex. 2.37.l(m)

Using current division Rule, Fig. Ex. 2.37.l(m),

Re le Rn
... (3)
Ia = Re+ r,. x I; T; = Re+ r,.

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 ~ Analog Electronlcs MU-Sem.3-Electrical) 2-88 Bipolar Junction Tra .
nslS1or
+Vee ► Step 4 : Impedances

~i Re

C
Z8 = r,, Z1

Zo
=
=
R8 IIZe

ZcllRc

► Step 5 : Voltage and current gain

E From Fig. Ex. 2.37.2(c),

Since assumed voltage due to iL and actual voltage d11e
to i0 are with opposite polarity, with v0 we will have
negative sign. •

'I' Bypass VO = - gmV n Z 0 and V,,=V;

capacitor

(1E44)Fig. Ex. 2.37.2(a)

► Step 2 : What is the meaning of "model with early Hence
effect" ?
Av

where Z0 = r0 II Re
Io Vo Z; Vo Z;
A, = T = Re X V; = v;-
X Re

Ex. 2.37.3 : Derive the expressions for Av, A 1, R; and R,, for
a NPN transistor in CE mode voltage divider biased
(1E45)Fig. Ex. 2.37.2(b) configuration with RE unbypassed.

Without considering e~ly effect, le remains constant @soln.:

with V CE· But if early effect is considered then (due to ► Step 1 : Circuit diagram
effect) as V CE increases le also increases. It means early
First draw circuit diagram (Refer Fig. Ex. 2.37.3(a)).
effect provides slope.
The ( sJ~pe) at Q point gives r0 • It mean~ if early
effect is considered we have to connect r0 with BIT model.
► Step 3 : Draw AC equivalent circuit with DC supply and
capacitor short. Replace transistor with h-1t model. ·

r
Ce1 C

11 B le gmV,. C B
+ + E V0 ·
+ vi
v,. r,. R2 Re
E +

gmV~
z, Ze Zc Zo

(IE48)F1g. Ex. 2.37.2(c) : AC equivalent circuit (1E47)Fig. Ex. 2.37.J(a)

Teda-Neo Publiealion8........... rn,erc Autl10n lnNpirc /11noY•lio11 .....A SA CHIN SJIA// Yea~
►

~ Analog Electronics (MU-Sem.3-Electrical) 2-89 Bipolar Junction Transistor

► Step 2 : AC equivalent circuit 11• Note : Since we have used current gain form of h-n
Draw AC equivalent circuit (assuming ro -- oo) • s·tnce
model. :. For convenience use formulae for
R is unbypassed draw 4-line (Refer Fig. Ex. 2.37.3(b)).
6 VO and V1 such that they contain 18 •
Is file= 10
8 +
Vo -PRc
r,. Ills :. Av = V - I
Ze

► Step 5 : Current gain,

V1
(1 + 1])1 8 =le 1of
Vo Module
Re Io

Is
Re

131 8
+
j A1 =

From Fig. Ex . 2.37.3(b),

T I

ii
Zs Ro= 2a
(1e48)Fig. Ex. 2.37.3(b): AC equivalent circuit and Fig. Ex. 2.37.3(c),

• Note : Since problem is of 4-lines, for our convenience

we have used current-gain form of h-n model.

► Step 3 : Impedances
To find~ (impedance seen at Base), transfer R 6 from
E to B. For this multiply Re with (I + f3) and connect in
series with r71 Fig. Ex. 2.37.3(c).
~ Analysis of collector to base bias with C 8

Ex. 2.37.4 : For the network shown in Fig. Ex. 2.37.4(a)

determine ~ , Z 0 and Av-

+12V

Re
3 kn
~VV'-l/'v-"T"""'-'V'll\ /\........-+---1~ Vo
Ri = ~ Zs ls
10 µF
(1E49)Fig. Ex. 2.37.3(c)
Cs T 0.01 µF
~ = Tn + (I + P) RE 10µF T C
~t--_.___ _ _ __:B~ 13 = 140
Z = R; = Ra IIZa Where, Ra= R1 II R2
I
E

For Z0 =Ra ·, short input (Vi= 0) :. I;= le= Ple= 0

Ex. 2.37.4(a)
... 1 zo = Re = Ra 1 (1E51)Fig.

► Step 4 : Voltage Gain ( Av ) ji1 Soln.:

Vo ► Step l : DC Analysis
Av = V. I
Open all capacitors and draw circuit diagram again.
.. .Fig. 2.37.3(b)
Output voltage V O = - I Re =PIa Re
0

... Fig. 2.37.3(c)

Input voltage V; = 18 Zn

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r .,;~ iiiii.... 111
A.nal.,o~g.;E;,;;le;;c;tr~o;:,;n~ic~sJ(:;
M~U:,;,-s;;e
: rn
~.3!;,-E~l~;;•~-~ ~12._ _ _ _ .,!2;;;-~o~----------.. !B~-~I:,.;;~~~~
tpo ar Junction Tr .
ansistor
12-0.7 1'
19
= -12 AA
Vce = 12 v 10 0 = [ 168 +141 x 3] kQ

fj r,,..._ _ _/\-..__ _ __
Re Re =3 kn Ico = fH 80 = 140 x 19.12 µA

Ra1 =120 kQ Ra2 =68 kri Ico = 2.67 mA

► Step 2 : Calculation for r,. and gm

C
B VT 26 mV
13 = 140 r,. = 1 =19.12µA =l. 36 kQ
E 80

,8.
.----.....;.----.... -- - - ,
lco 2.67 mA
gm = VT - 26 mV = 102.7 ms
'e + le :
►

-------·
I I
I I I Step 3 : AC Analysis
I Re I
Draw AC equivalent circuit to short all capacitors and
I I
I
l Rs+ I
I
DC sources. (Refer Fig. Ex. 2.37.4(d))
19 le I +
Vee+
T - Vee Re
C + I
B I Ra2
I
ls + I
Vee - E - I
I
_____ _______ .,
1I ---------I I
I
I
I
L...----...----..--l- - -- -' .
I
vi o-......
B
------1
8-loop
E
(1E58)(b) and (c)
Fig. Ex. 2.37 .4 (1E59)Fig. Ex. 2.37A(d)
With C 6 open R 61 and Re 2 will be in series
Since E is directly connected to GND, we draw 3 lines.
Let. Re = Re 1 + Re 2 = (120 + 68) kQ = 188 kQ
Re 1 connected between B and GND while R82 and Ro
To find Ieo• apply KVL in B-loop. Using our standard
between C and GND. (Refer Fig. Ex. 2.37.4(e))
method,
Total known voltage in 8-loo~
Isa= [ Resistance through which le is flowing+ (1 + f3) I-' . ls 9mV1r
I B C
x ( Resistance through which (le + le) is flowing ) ] +
Vee - VeE v,r f II Rs2
... (1) 68 kil
Ieo= R +
e + (l+f3)Rc

•• Note : Formula (1) can be prbved as follows~ :·'.' ' E E

'
9mVn
zi T Zo
Apply KVL In B loop. \ ·. ,,, Zs Zc
·----------------- -- - -------
V cc - Oc + le) Re - le Rn - V
: Proof: = 0 BE
(1E60)Fig. Ex. 2.37.4(e)

Vcc - (13 le + In) Re - 18 R8 - VB E = 0 "" Impedances

(V cc - V 8 J - (le + 18 ) Re - 18 R 0 = 0 zll = r" = 1.36 kQ

With le== ~le Z1 = Re, II Z 8 = (120 111.36) kQ

(V cc - V B E) - 18 [ R 0 + ( I + ~) Re ] = 0 = 1.34kQ =Z,
Vee- Vo e
le = Ru + ( + l3) Re ... same as Equation (I) ~o find output impedances Zc and Zo, short input.
1
---------- ---------------------
1
Y i = Vn=0
-;;-:-
tt-;-h-;
-N:;-~~ P~uh;-;la-.u ici:n•=--..-...-...-...•JFJ
:-=:,-;-: ~'l,=
ere
~ Aluu~
t/J;:o-n-;;;;,it~
16p;,ire
:;,"jin;,n:o:r•;;.ti:11n=--- -- -- - - - - - - -- - - -..-....A- SA_ al
_ rJN
- S~
1
►

[§i1 Analog Electronics (MU-Sem.3-Electrical) 2-91 Bipolar Junction Transistor

-- :. gm V" = 0 and current source will be open.

Hence, Zc, = Re2 =68 kQ
Z0 = Zc,11 Re = (68113) kQ = 2.87 kQ
er Voltage gain
Vo
Av - V1
Since we have used transconductance form of model
write V O and V; intenns of V 11 • '

Since output voltage V O (across Re) due to actual

current l 0 and due to assumed current IL are of opposite
polarity, with V O we use negative sign.

► Step 2: Voltage gain

-l0 Rc V 0 -[l+gm V 11 )Rc
Av = Av = le r,. =V; = le r,.
3 3
= - (10.27 X 10- ) X (2.87 X 10 ) But I < < gm V,. because normally Re is of the order of

:. Av = - 29.47 few lOO's of kQ or MQ.

r:r Results

Zi = 1.34 Jill' zo = 2.87 Jill, Av =-29.47

B' Analysis of C to B bias without C 8

Ex. 2.37.5 : Derive the expression for voltage gain, current

Av = -g,,,Rc
gain input and output resistance of CE amplifier with ► Step 3 : Current gain
collector to base bias without bypass capacitor Ce. Io
A1 = ~

Apply KVL in outer loop (shown in Fig. Ex. 2.37.5(b))

V1 + I R 8 + ~ Re = 0
From circuit, 18 = I; + I

V1 + (1 8 - I;) Re + l 0 Re = 0
From circuit, V 1 = V = le r 11 11

le r11 + 18 R8 -I; R8 + 1 Re = 0 0

y le (r" + Re) + Io Re = I; Re
From circuit, 10 = I + gm V 71
(1E14)Fig. Ex. 2.37.S(a)
But I is very small therefore
~ Soln.:
► Step 1 : Draw AC equivalent circuit by shorting
capacitors and Vcc· Replace transistor with
h-n model.

.. L Neo publ'JCallODl-••·•m•
• _ _,4 SACHJN SILU/ J'mture
TIXII• ,,D
rrA.err, ,4utlion i,upin, inaur11tiun
 Rs= Re=
470 kfl 2.2 kfl
C2 = 10 µF
r11 << Re +~Re

Then A1
A1 ~Re
= _..;.._~-
Re+ ~ Re
if we make ~ Re>> Re

I
c 1 = 10 µF
7
► Step 4 : Input impedance ( z, ) v,
z. = _V., . .. ( I )
1 I; 13 = 120
Let us find what I; is ?
(1E78)Fig. Ex. 2.37.6(a)
le = I; + I
I, = le - I
0 Soln. : For doing AC analysis, to calculate Z;, Z., and Av
we require r,. and gm. To get these parameten;, l8 Q is

. rll
required. Therefore we have to do DC analysis .

Av V ;- Y;=~ (Av - I ) V ; ► Step 1 : DC Analysis

Re r11 Re Draw DC eqoivalent ci rcuit by opening capacitors and
showing all DC so urces separately and named
correctly. Refer Fig. Ex . 2.37.6(b).
Using our shortcut method
. . . (2) (20- 0.7) V
Yee - YeE
Ieo = Re + ( I + ~) RE = [ 470 + ( 121) (0.56)] kQ
V; r11 Re
Put Z; = T = R e + A,, r,. Ieo = 35.89 µA
Since gain Av is negative we normally write Ieo = ~ l 80 = 120 x 35.89 µA = 4.3 mA
le

.
r,. RB
Z1 = RB + I A., I r,. + +
---,I
I Rs= Re=
I I
► Step 5 : Output impedance (Z0 ) I I 470 kn 2.2 kfl
,-
I
To find output impedance, according to rule, remove
load, short input . As soon as input is shorted r11 = 0, V11 = 0,
I
I
I
I
C + t
+ +
V = O and current source will be open. The ac equivalent Vee=
I
VeE
g m II I

circuit will be as shown in Fig. Ex. 2.37.S(c). 20V - "'-~-, + B

E
- Vee=
I
I VeE - 20v
I
I
I IE
I
I
+
I RE=
I I
I I 0.56 lul
I I

-------
I I
IE= le+ Is

Base loop
(1E79)Fig. Ell:. 2.37.6(b)

Ex. 2.37.6: Determine Z;, Z0 and Av for the circuit given in ► Step 2 : Calculation for transistor parameters
_ VT 26mV
Fig. Ex. 2.37.6(a). r" - Ieo = 35.89 µA ; r. = 724.4 g
_ 1co 4.3 mA
gm - VT = 26 mV = 0.165 S
--;-;,-~;-;:-:-:------.~-z;i.=====-;;::::--- - - - - -- - - - -------::
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p

~ Analog Electronics (MU- Sem .3-Electrical) 2-93 Bipolar Junction Tran sisto r

-;= Step 3 : AC Analysis :la = r" + (I + f3) RE (Refer Fig. Ex. 2.37.4(d)).
Refer Fig. Ex. 2.37.6(c). = [0.7 244+ ( 121 )x0. 56Jk Q
I;
1e Pie
_+_..,;..-,-----.-- •+- . B ~- --- r+ --. + :la = 68.48 kQ

v" r"
~ = Ra II Za = (470 1168.48) kQ
~ = 59.77 kQ
To find Z 0 , make V; = 0, with which Ia = 0
Ra + :. f3Ia = 0 and current source will be open.
Z = Re = 2.2 kQ (Refer Fig. Ex. 2.37.6(e)).
0

Z8 f3Ie = lo
Z;
(1E80)Fig. Ex. 2.37.6(c)

Step 4 : Calculation for AC Parameters

►
To calculate Za we use our shortcut.
ter to (1E82)Fig. Ex. 2.37.6(e)
Whenever a resistance is transferred from Emit
ected in
Base, it is multiplied by (1 + f3) and is conn Since the output voltage due to I0 and assumed
IL are
series with base resistance ( r" ).
with opposite polarity, with V 0 we use negative sign.
Refer Fig. Ex. 2.37.6(d).
l1 Is Vo =- loR c=-f HaR c :. V;= IaZ a

-~ x Re -120 x 2.2 kQ ,
r,, Av = )(Zs = 68.48 kQ = - 3.855

17 Results
(1 + fi) RE
Z1 = 59.77 ldl , Z = 2.2 ldl,
0
Av= - 3.855

z1 Zs
(1E81)Fig. Ex. 2.37.6 (d)

J 2.3 8 AC ANALYSIS USING EXACT h-MODEL ---- ---- ---- ---- ---- ---- ---- ---- --,
~- ------------------------------------------------ output Impedance of CE amplifier.
'· UQ. Derive the expression for voltage gain,
current gain, input impedance and
:
1 o Mark s) 'f II
(MU - a. 2(b). Dec. 14. a. 3 a), Dec. 15,
and derive the expre ssion for
e divider b~ CE amplifier with RE bypassed
UQ. Draw the hybrid equivalent model of voltag (MU 0. 2 b. Ma 16. 12 Mark s)
-
voltage gain and input impedance. voltage gain.
ameter and hence derive the expression for
UQ. Explain the modeling of CE BJT In h-par b), Ma 18. 10 Mark s
MU - 0. 5

:· GQ. Give the complete AC..a ~lys is of

CE amplifier uslf'.lg h parameter model.
► ---s~;-1-=-~i~; i; di:;;;;- -----------
·-+~~~ - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - ·- - - - - - - - - - - -

Rs
B
Vs V;

(1E118A)Fig. 2.38. ]

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ltioa --.A SACRJN SHAH f'enture
r liJ Analog Electronics (MU-Sem.3-Electrical) 2-94

► Step 2 : Draw AC equivalent circuit

lo
Rs h1
+ .-.. IL +
1
f
ho
Vo RL
i Vo
IL

~
f.- Sou rce_
ZI ..__
__ _ _ Voltage amplifier -- --- -!- -- Load --J
Writ e important equation by using KVL at
KCL at outpu t.
input and
(1E117)Flg. 2.38,2 : AC equivalent circuit

-
V; = h; ~+h r Vo
h, h,
Io = hrI;+ ho Vo Z; = h; - ho + RL

Also V O = IL RL V O = - I0 RL Vo
► Step 5 : Voltage gain Av = v. (neglecting Rs)
I

► Step 3 : Current gain

Io
A, = -T I

I0 = hf ~ + ho V = hf ~ + h
O 0 (- I0 RJ
I0 (1 + h0 RL) = hf ~
Io hr hf
~ = 1 + ho RL = - A,

= h; + h; ho RL- ~ ht- Ri.

- bi-RL
Step 4 : Input impedance Av = h; + [h; h,, - ~ bi- ) RL
►
V;
Let Afl = [h; ~ - ~ hrl
Z; =T I

V; = h; I; + hr (- I RL) =h; ~ + ~ RL (A,~)

0

= h; I; + hr RL I; A,
► Step 6 : Output impedance
V;
= h1+ h, RLAI 1
~ V0
-h,
y =~=-
0 l\l
:. [zj = h + hr RL A,]
1
but A1 = I+ ho RL c· .
1rcu1t shown in Fig. 2.38.2 is nothing bl~11 ,
network.
- hr h, RL . salt di'
= - To find Zo of any two port network, folloW 108
Z1 h,1 - I t ho RI,
steps :
~ N
- eo
-::-
Pu-:-li~liu
- ,-:-
;-
008
a,n,vi::e:rr:~Ai:u,;ho,:n;;;,ia~.,p;i:rc-;;,iaa
-....-...-....
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►

'1 Analog Electronics (MU-Sem.3-Electrical) 2 _95 Bipolar Junction Transistor

--
► Step (a) Remove load RL
► SteP (b) Short output, Vs or Vi = o
V1
Vs =
zi
Z1 + Rs
Vo Vo V1
► Step (c) Apply known voltage (V 0) across output Now, Avs = -V = V
S I
x VS
terminals.
► Step (d) Measure l 0

► Step (e) Therefore Z 0 =V O / l0 . ► Step 8 : Current gain with source resistance Rs in A,s

Using these steps, Fig. 2.38.2 will become as shown in To find A,s, convert input voltage source to current
source. From the circuit shown in Fig. 2.38.5, using current
Fig. 2.38.3.
division rule,

ho
·1 (1E120)Fig. 2.38.5
Output short V 5 = 0
Zo= y0
Applied
~ Rs
voltage Is = Rs+Zi
(1E118)Fig. 2.38.3

From Fig. 2.38.3, applying KVL at input

~ (Rs + h;) + h,. Vo =0 Rs
A,s = A, x Rs+ zi

hr h,. Vo
J 2.39 AC ANALYSIS OF CE
Io = hr ~ + ho Vo = ho Vo + Rs + h; AMPLIFIER USING EXACT
H-MODEL
I0 hr h,.
Vo = yo = ho - Rs + h;
Ex. 2.39.1 : For the circuit shown in Fig. Ex. 2.39.l ,
I I determine input impedance, output impedance, voltage gain
Or Zo =y= hrh,
o h - and current gain. The h-parameters for BIT are :
o-Rs+hi 4
hie = l.5 k.Q, hrc = l 00, h,.,, = 1 X 10-
► Step 7: Voltage gain with source resistance Rs and hoc = 25 µA N
i.e. Avs
Rs
R 8 =400 kn

Rs'= 0.5kn

B
21
(1E1111)Fig. 2.38.4

Prom the circuit shown in Fig. 2. 3s.4 , using voltage z, lo

division rule
(1E121)Fig. Ex. 2.39.1

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;,;;,~
3~-E~le~c;tn;·c;al~---..,;2;..;·9;,;6_ _ _ _ _ _ __ _....,=B""'i..,PO""'la""'r""'J""'u==nct.i,_on.,.T.;.;r::an~stor
~ ~
~ Soln.:

fI Since we have to perform AC analysis, we will draw AC

equivalent circuit by shorting 1111 capacitors and DC source. Then we
will replace transistor with its exact model. [Refer Fig. Ex. ,2.39.1 (a)
and (b)]
C

E Re V
r 0

21 zo
.J
(1E122)Fig. Ex. 2.39.l(a)

B
•,:-----r
Ra V1 hteIB 1 Re= RL Vo

.___ _ __._+-_.,__ _ _ _ _ _...__ ___..__h_te_ri_...__

ho_e_-+-_ +
......__ ______ !_
G

(1E123)Fig. Ex. 2.39.l(b)

Convert Fig. Ex. 2.39.1 (b) to standard form, for which we have standard derived formulae. This will help us to use
formulae directly.
Thevensing circuit on LHS of BG (Fig. Ex. 2.39. l(b)) we can get our standard circuit.

R5 = ~ =R; II R8 =(400 / 0.5).kQ ~ 0.5 kQ

R5 =0.5 kn 11 =18 hie= 1.5 kn

+ _n~----------f+
htels 1 _ 1
100!
8
h00 - 25 µU Re= 4 kn Vo

+ -~:-~ ___ _J_

,__- ~ ------------------+--'
~
(1E124)Fig. Ex. 2.39.l(c)

Now using standard formulae = 2 X 10· 5 U

A, =
Jo - hrc
~ - 1 + hoe RL - I + 25 µ X 4 k
- 100
:. ·zo = y1 =so kQ
0

A, = -90.91 Now if we consider source resistance

z, = hie + hre A, RL =1.5 k- IX 10· ◄ X 4k X 90.91 A Rs 0.5 kQ _
IS = A1 . Rs + zi = - 90.91 X 0.5 k + 1.46H
z. = 1.463 kQ
R,_ - 90.91 x4)( A18 = -23.16
Av = A, ·z= I 1.463 )( Z1 l.463 k_
Also Avs = Av x z + Rs = -248.55 x l.463 k + 0.5 k
1
Av = -248.55
:. Avs = - 185.24
100 XIX 10· 4
0.5 k + 1.5 k
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p

_ Bipo lar Junction Transistor

[i1 Analog Electronics (MU-Sem.3-Electrical) 2 97

~ Note : Students should note that

when Rs was not
248.34): but
r:r Reaulta
considered, Av was high (Av = - z, = 1.463 kil
when Rs is taken in calculation,
voltage gain A, = -90 .91
s Is due to zo
decreases (Avs = - 185). (Thi Av = -24 8.5 5, = 50 kil
LOADING EFFECT).
Avs = -18 5.2 4
Hence if we want loading effe
ct as less as A,s = -23 .16 ,
stance of source (Rs)
possible then output resi
, In voltage
should be as low as possible
amplifiers.
Vee = 20 v
Fig. Ex. 2.39 .2.
ex. 2.39.2: For tran sist or circ uit sho w n in
4
I 0- , l\,c = 25 µU .
h;, = 1.5 kQ, hfc = I 00, h,., = 3 x Re=
and voltage , curr ent gains. 5.1 kn
Calculate inpu t outp ut resi stan ces
0 Soln .: C

B
► Step 1 : AC equ ival ent circ uit E
Rt_'=
rtin g cap acit ors and DC sources.
Draw AC equ ival ent circ uit by sho 10 kn

Let, Re = R 1 IIR 2 =(4 115 .l)k Q

= 4.6 kQ
(1E125)Fig. Ex. 2.39 .2
RL = Re II R~ = (5.1 II 10) kQ

= 3.38 kQ lo
+
~ IL
C
R'
s
B lof Rt_ Vo
E
+
Rs IE

~ 2c
uit
(1E126)Fig. Ex. 2.39 .2(a ): AC equivalent circ

► Step 2 : Exa ct AC anal ysis this we get Fig. Ex. 2.39.2(b).

· · h c t hyb rid model in Fig. Ex. 2.39.2(a). Doi ng
Repla ce tran sist or wit exa
Io
+
1
hoe

rid model
(1f127)Fls, Ex. 2.39.2(b) : Exact hyb
dire ctly ·
whut we can use stan dard fonn ulae
. . . . p·
1g. Ex · 2 ·39.2 (b) to standard circuit so
Now con vert ing circ uit in
Thevenising circ uit an LHS of BG

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Rs = ~ II R 11
Rs = 0.821 kn le h1e=1.5kfl
"
II = (I 114.6) k.Q

= 0.821 k.Q
,,
Jx10
h,.Vce
.....
xVce
hoe
1

1
= 25µu
Vo
~-t
+

f\::
3.37 k{l
, Ro +
Vs= V x
s Ro+~
Also, RL = R~ II Re = (10 II 5.1) k.Q
z, (1E128)Flg. Ex. 2.39.2(c)

RL - 3.37 k.Q

Ii Now, Using standard formulae Ex. 2.39.3 : The transistor in the given circuit is connected
If I '
_ -hrc -100 as a common emitter amplifier. Calculate Av, R;, R.,.
I + ~ RL = 1 + 25µ X 3.37 k.Q
Ar -
Assume h;e = I. I k.Q, hrc =50, h,c = 2.5 X
-4
l 0 • hoc = 401 ldl
A, = -92.23
Vee
Z; = h;. + ~ RL A,

= 1.5 k.Q + 3 X 10- 4 X 3.37 k.Q X (- 92.23)

z, = 1.406 kil
RL - 92.23 x 3.37~
Av = A, . ~ = l.406~

Av = -221.06
hr.~ 100x3x 10 - 4
yo == hoc - Rs + h;. == 25µU - (0.821 k.Q + 1.5k)
(1E129JFig. Ex. 2.39.3
::: 1.207 X 10- 5 S
I . @soln.:
and zo == y= 82.8]8k.Q
0
Name resistances as given in Fig. Ex. 2.39.3
If source resistance is taken into account. ► Step 1 : AC equivalent circ uit
Z; 1.406 k.Q
Draw AC equivalent circuit by shorting all capacito~
Avs = Av. Z; +Rs== -221.06 x 1.406 k.Q + 0.82 k.Q
and DC sources.
Avs = 139.6
R'
s C
Rs 0.821 .B
A,s = Ar . Rs+ Z; =- 92.23 x 0.821 + J.406
E
V'
s Re
AJS = -34
C7 Results

A,= -92.23 A18 =-34

Av = -221.06, Avs =-139.6 (1E130)F1g. Ex. 2.39.J(a)

z, = 1.406 k'1, zo =82.818 k'1

Tedi-Neo Publication,_.,_,_, fl'/Jere Aut/Jon iaapire irmoYlllioa __,4 SACHJNSJl4// Yatutt

►

['1 Analog Electronics (MU-Sem.3-Electrlcal) 2-99 Bipolar Junction Transistor

Rs = R; II RH= R~ II R 1 II f½

= ( I0klllOO klll0k )

= 4.76 kQ

(1E131)Flg. Ex. 2.39.J(b)

► Step 2 : AC analysis
Now replace Transistor in Fig. Ex . 2.39.3(b) with exact hybrid model.

Rs= 4.76k.Q B h18 = 1.1k.Q

+
hreVce 1
-4
2.5 x 10 V06 hoe
= 40 k.Q

E
~
(1E132)Fig. Ex. 2.39.J(c)

-hrc - 50 er Results
A1 = I + h D = l = - 44.44
oc •'L 1 + - - x 5 )( A15 = -36.44
40)( A1 = -44.44
Av = -212.83 Avs = -38.28
Z = h;. + 11,. RL A1
4
z, = 1.044W zo = 43.73 W
= 1.1 k+2.5x 10- x 5kx(-44 .44)
z = l.044kQ J 2.40 AC ANALYSIS OF CE
RL -1L AMPLIFIER USING
Av = A,z=- 44 .44 x 1.044k
I APPROXIMATE AND EXACT
Av = - 212.83
-4
MODEL
hrc 11,.
50 X 2.5 X 10 l
Yo = hoc-Rs+ h;. =4ok- 4.76k+l .l k Ex. 2.40.1 : For the amplifier shown in Fig. Ex . 2.40. l (a)
5 calculate current and voltage gain. Also calculate input
= 2.286 X 10- U and . output resistances using exact analysis and
l approximate analysis.
20 = 43.73 kQ =y0 -4
If h;. = lkQ, 11,. = 2 x 10 , hrc = 50 and l\.c = 25µs.
If source resistance is taken into account,
+Vee
Z;
Avs = Av . Z + Rs
1.044
= - 212.83 X J.044 + 4.76
Rs= 0.8 kn
:. Avs = - 38.28
B
Rs
Ais = A, . Rs + Z;
4.76
= - 44 .44 X 4.76 + J.044
(1E133)Flg. EL 2.40.l(a)
A1s = -36.44
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aris,sto
~
@s01n.: ~
r:r Exact analysla ►
. Approximate Analyals

Step 3 : Approximate AC analysis

► Step 1 : AC equivalent circuit Now replace transistor with approximate model.

Draw AC equivalent circuit of given amplifiers, by [Let ~ = hoc = 0]

shorting AC source and replacing BJT with exact
model. (Fig. Ex. 2.40.1 (b))
Rs

► Step 2 : Exact AC analysis +

Vs
Rs= 0.8 kn
I,,
i71L + +
+
hraVo
v, '\,
1
Rc=RL
Vo
2 X 10~ X V0 hoe
= 1kn
~ 2a
+
(1E135)Fig. Ex. 2.40.l(c) : Approximate model
'i'
Zi Zo In all exact formulae·replace hre = hoe = 0
(1E134)Fig. Ex. 2.40.l(b): Exact hybrid model -hr.
A1 = l + ~ RL hrc =- 50
- hre lo -50
A, = -
1 + h0 e RL :-- ~ - 1 + 25µs X 1 kQ
Z; = h;e + A1 RL b.,., = hie = lk.Q
I 1
A~ = -48.78 zo = hre hre =0 = 00 Q (Open)
-hfe ~RL hoc Rs+ l\e
~ = l\c 1 + h R = h;e + A1 hre RL
oc L
4 - 50 X 1kQ = _
= lkQ + (- 48.78) X 2 X 10- X lk.Q Av= lkQ
50
Z1 = 990.240
<T Results
-hr. RL
Av - hie+ Af1 RL , Where dh = l\e hoe - h,. hre
Parameters Exact •. ·Appro~ate
A1 RL -48.7 x 1 kQ IA11 48.78 50
Or Av = ~ = 0.990 kQ
Z; 0.99 kQ lkn
Av = -49.18
zo 51.42kQ 00
20 = hrchre - 50x2x10- 4
25
hoc - Rs + h;c µs 0.8 kQ + 1 kQ IAvl 49.18 50

zo = 51.42 kn
)~ '.·~t;j.~~\t~~~~is should .compare qmd i~am from
}\J;f 't)ii i:f{results~t·

•NOTES•
~

---
--
----
----
Tech-Neo Publication,,_",_ lnere Authon impire iaaoratioo
 Bipolar Junction Transistor
GAnalog Electronics (MU-Sem.3-Electrical) 2-101

OR
2.41 COMMON COLLECTOR AMPLIFIER OR UNITY GAIN AMPLIFIER
OR
EMITTER FOLLOWER OR IMPEDANCE MATCHING AMPLIFIER
BUFFER AMPLIFIER

GO. Write short note on : Emitter follower.

- - - - -

Module
Key Points
2
AC equivalent circuits of amplifiers
1.
Current amplifier with gain A
(1) Voltage amplifier with gain Ay

Ro Vo
R AVi

A
A (1E209)Fig. 2.41.10b)

(1E208)Fig. 2.41.1(a)
current
is Since at output we get amplified current,
Since at output we get amplified
voltage, voltage source
in parallel. (Norton's
(2) source is shown with R,
with Ro in series. (Thevenin
equivalent).
shown
equivalent).

minimized ?
How it can be
I 2. What is loading effect ?
Load
Source
wwt
Ror

(1E210
Fig. 2.41.2

which supplies energy.

(instrument, circuit)
Source: Source is electronic (or
electrical) point
which consumes energy.
Load: Load is a point (circuit,
device or appliance)
can work as load
as well as source. Source, when it provides amplified
note that an amplifier
In the Fig. 2.41.2 we
receives amplified signal.
Signal; load, when it
In Fig. 2.41.2.
or amplifier
is output
resistance of source
Rs Or R, amplifier
resistance of load or

R or R is input
1S not conneeicd, l00p (conSIsts or source and load) is open. Hence current

In Fig, 2.41.2 when

load (R)
(a)
I=0.
innovation SACHIN SHAH Venture
here Authors inspire
ech-Neo Publications..
 Analog Electronics (MU-Sem.3-Electrical) 2-102 Bipolar Junction Transistor
'V = Vs
Now if load is connected, the loop is closed, hence I flows; there is voltage drop
across output resistance of source (R
Since, V = Vs -I Rs there will be reduction in Vo
This reduction in output voltage of source when load is connected is known as loading ertect.

b) Since Vo Vs -IRs
=

If Rs (output resistance of source) is high, drop across Rs

(I Rs) will be high therefore, reduction in V, will be high
which is responsible for high loading effect. Should be Should be as
high low as possible
(c) Again since V =Vs -

IRs ww
If R (input resistance of load) is low, I wil be high and R R
again I Rs will increase. This will again cause reduction in R-R3 A
therefore loading.
(d) If above two points are considered then to minimize
loading effect, dutput resistance of source should be as Working as load Working as source
low as possible (ldeally Rs = 0), while input resistance of
(1E211)Fig. 2.41.3
load should be as high as possible (ideally R= )
Since any voltage amplifier works as load from input side, its input resistance R, (= R) should be high while fron
(e)
output side voltage amplifier works as source therefore, output resistance R, (= Rg) should be as low as possible.

GQ. How can we reduceloading effect ? Why buffers are required ?

Ay1
High Low
Rs
o

V Vo Vo

Source Buffer or impedance Load

matching output

(1E212)Fig. 2.41.4
To reduce loading effect, we can connect an amplifier
between source and load. This amplifier should have high 2.42 IMPORTANT PROPERTIES OF
low output resistance.
input resistance and
With high input resistance, 4 on input side will be low CC AMPLIFIER AND ITS
be low, hence
APPLICATION
therefore drop across Rs (= , Rs) will
reduction in V, reduces.
Ga. Why common collector amplifier is used as bufer
With low output resistance R, (on output side), drop
Why buffers are required ?
across it (=1, R,) will be low therefore reduction in V, will
|: Ga. Explain small signal common collector amplitier.
be less.
Therefore overall reduction in voltage gain reduces. Ga. Drawa diagram of an emitter follower and descu
Such amplifier with high R, and
low R, is known as Buffer its working and advantages.
resistance of sources
amplifier. Since it matches high output
and its own low output
GQ. In which applications the common cou
resistance
with its own high input
impedance with low input impedance
of load, it is also configuration can be used ?
known as Impedance matching amplifier. - .

innovation
Tech-Neo Publications...ww.Where Authors inspire A SACHIN SHAH
Veature
 AnalogElectronics (MU-Sem.3-Electrical) 2-103 Bipolar Junction Transistor

Circuit and equivalent circuit

1.
C Z whichis verylow.
3. Current relation

c e p + lepo> for CB
also e = lp-ls

Re
Vo - I = pce +lCBo
lcBO Module
2
Let Y 1-dpc
=
(1 +Prc)
(1E213 a) Common collector configuration

Yoc I +(1 +Bpc) lcso

If we neglect leakage current (1 + Ppc) lcBo then

Yoc ( 1 +B)ie. forwardcurrent

gain of CC configuration.

ZRE Vo D C current gain of CC is maximum.

4. CC as emitter follower
see that
From circuit shown in Fig. 2.42.1(d) we

Z V, VBE» since VBE is normally very small, we can

V. = -

(1E214)(b) Circuit to find input resistance of CC amplifier

write

VVB J
Short- E E VeVo V=Ve VBE
RE Vo
RE: RE
ZE
resistance of CC amplifier (1E216) Fig. 2.42.1(d)
(1E215c) Circuit to find output
Fig. 2.42.1 V.= V, It means in CC, V,= V,. As input at base (V)
because
Fig. 2.42.1a) indicates CC amplifier. It is CC, will vary, output at emitter (V) will also vary accordingly.
from emitter and
input is given to base, output is taken In other words, emitter follows base. Hence CC is also
collector is common to input, output ports.
known as Emitter follower.
2. Impedances 5. CC as unity gain amplifier
resistance of CC
Fig. 2.42.1 (b) shows that input
Since V = V, voltage gain Ay =*
amplifier is
B) R which is very high.
R =
Zg = , +(1 +
That is the reason CC amplifier is known as unity gain
resistance of CC
Fig. 2.42.1(c) indicates that output amplifier.
amplifiers is

innovntion A SACHIN SHAH Venture

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AAnalog Electronics (MU-Sem.3-Electrical) 2-104
Bipolar Junction Transistor
CE amplifier
(0) Since output resistance (R,) of
GO. How can CC amplifier can be used as a
buffer or
k2) when current I flows through it
(40 to 80
impedance matching amplifier ? Explaln. across R (of A)
is large. Hence input to A, rededuces
***-~-- - -------
i.e. because V, =A V,-IR,.
In Fig. 2.42.2(a), two CE amplifier are cascaded to get
of A, decreases, gain of ampliífe.
more amplification. Since input voltage
decreases. Technically Az loads A:
A A2 of CE always low
amplifier is
(2) Input resistance connected to
(= 1k2). When output
of A, 1s
input of
R Rs I increases because Ri of A, is low. Therefo
Az again
and V decreases. This further
drop IR, will be
more

V reduces gain.
To overcome above problem of loading and impedance
we connect CC amplifier between two
mismatching
The CC amplifier
R high R low CE amplifiers refer Fig. 2.42.2(6).
and also it
(Buffer) provides impedance matching
(1E217)Fig. 2.42.2(a) eliminates loading problem. This is possible onlywith
special properties of CC configuration, i.e. high R, and
Cascading (connecting output of one amplifier
to

other) of CE amplifier as shown above reduces the total gain low R

due to loading effect as explained below.
CE
CE CC
Ro Ro

V, AV V

Rhigh R, high Rlow Rlow

Matched Matched

(1E218 Fig. 2.42.2(b) : Impedance matching

2 . 4 3 AC ANALYSIS OF CC Step 1:Circuit diagram

AMPLIFIER OR EMITTER +VcC
FOLLOWER OR BUFFER

for voltage gain,

current gain, Rs
Ua. Derive the expression
output impedance of common www.T
input impedance,
collector amplifier. (MU -Q.3(a), May 15, 10Marks
------- **--°-*
Vs T
V
In CC amplifiers input
AC signal is given to base,
R R
Emitter and collector is common
is taken from
output signal
for MF AC. Cc
to input and output ports

Source Amplifier Load

(1E219)Fig. 2.43.1(a)
Vat
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 Analog Electronic (MU-Sem.3-Electrical) 2-105 Bipolar Junction Transistor

AC equivalent circuit
Step 2:
Draw AC equivalent circuit by shorting all capacitors
Rs
and DC sources.

wwT
Vcc VçC Rg
=R,I R2RE R
Rs Module
w Short
2
(1E221)Fig. 2.43.1(c)

RE

(1E220)Fig. 243.1(b) form.

transistor with small model. We may h-t model. It is convenient to use current gain
Now, replace signal use
C
Rs B C

Short

lE (1+B)B
Vs Rg

Zin Zp
(1E222)Fig. 2.43.1(d)

Step 3: Input impedances

To find Zp. transfer emitter resistance R (= RE I R)

from E to B. Refer Fig. 2.43.1(e).

resistance is transferred
from E ZRRE l RL
We know, when a
series
B , it is multiplied by (1 + ) and is connected in
with base resistance (r).
(1E223)Fig. 2.43.1(e)
Zp (1 +B) R; + Z =Rg l| Zg

Zy Rg+Z, (Refer Fig 2.43.1(0).

Tech Fublieations.. here Authors inspire innovaion ASACHIN SHAH Venture
 Analog Electronics (MU-Sem.3-Electrical)
2-106 Bipolar Junction Transistor
Refer Fig. 2.43.1(
The circuit will look like as shown in Fig. 2.43.1(.
Rs
Now total resistance in base is (R, |I R,) + r.)
Vs To find Ze, transfer base resistance
from base
emitter, divide it by (1 +B) and connect between F .

n Rs+Z GND.

(1E224)Fig. 2.43.1()
Step 4:Output resistance impedance 1+B
To find output z =Z, I R
resistance seen at emitter (Z) short Zo ZEIRE and
input (Vs =0), therefore v, 0, Ig 0, B Ig 0 and
= = =

current source will be

open.

Rs

Open

Ru

Short
ZE ZE Z

(1E225)Fig.2.43.1(g)
Step 5:Voltage gain Ay and Avs (wihoutandwith R)From Fig. 243.1 using voltage division rule,
B Z
V Z+ Rs Vs
L(1B
V Ze
R(1+B) V Avs Ay xZ

Step 6: Current gain A and Ass (Without and with Rs

(1E228)Fig. 2.43.1(h) (1E227)Fig. 2.43.1()
Ay V,/R,)
Referring circuits shown in Fig. 2.43.1 (h) and Fig. 2.43.1(i),
(V,/Z)
(1+B)KRL
Av ... Without Rs
(1+B) R Ays
/RL)
.. With Rs
(VsR)
Ays xAyx V Rs
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Analog Electronics (MU-Sem.3-Electrical) 2-107 Bipolar Junction Transistor

impedance at the base of an emitter

Input
GQ.
follower isS.

input AC signal is given to base,

In CC amplifiers
VcC
signal is
outputsignal is taken from emitter and collector is common R1
and output ports
for MF AC C
to input Rs Short

Step 1: Circuit diagram

+VcC Module
Vs RE RE 2
R
Rs
B
(1E229)Fig. 2.43.2(b)
Cc2
T
Vs RE RL V
RS
Cc
Source - Amplifier Load Rg
(1E228)Fig. 2.43.2(a) R, R2RE RL2
Step 2 : AC equivalent circuit
Draw AC equivalent circuit by shorting all capacitors
and DC sources. (Refer Fig. 2.43.2(c). (1E230)Fig. 2.43.2(c)

use current gain form.

model. We may use h-t model. It is convenient to
Now replace transistor with small signal
C C
Rs
W.
E

Rg E (1+p)lB
Vi
|v. N

ZE Zo
in

(1E231)Fig. 2.43.2(d)

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 Analog Electronics (MU-Sem.3-Electrica 2-108 Bipolar Junction Trans

Step 3: Input impedances We know, when a resistance is transferred

E to B, it is multiplied by (1 + B) and is conneet
from
To find
ZB, transfer emitter resistance R, from E to B. ed i
series with base resistance (r)

Z (1+B)R +r,
This is resistance seen at base of an emitter follower
' = RE ll RL

(1E232)Fig. 2.43.2(e)
2 . 4 4 cOMPARISON OF CB, CE AND CC cONFIGURATION OF BT

GQ. Compare CE and CC configuration.

Parameters CE CC

(Common Emitter) (Commoncollector)

Circuit diagram

B
Rc Vo

Re Vcc
Vcc
RE
(1E252) Fig. 2.44.1(b) VpB
(1E253) Fig. 2.44.1(c)

AC equivalent
Circuit
DC short) Rc o

Re
(1 E255)Fig. 2.44.1(e)
(1E256)Fig. 2.44.1(
Emitter is common to input and output for AC. Collector is
Common common to input and output for AC
termina
Moderate 1 k2 to 3k2 High , mega 2
AC input
resistance (R)
Moderate 40 to 80 k2 Very low in N
AC output
resistance (R)
moderate 20 to 300
Current gain (A,)| Poc, YDc large, 1+Ppc
Voltage gain (A,)| > 1. power gain high 1 (unity gain)

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. A SACHIN SHAH
Analog Electron U-Sem.3-Electrical) 2-109
Bipolar Junction Transistor

Parameters CE CC
(Common Emitter) (Common collector
Input and output out of phase
Phase Input and outputin phase
Impedance
Efficient cascading is possible with CC. Works as impedance matching amplifier
matching

Leakage currentVery large S00 LA for Ge 20 HA for Si Same as that of CE

Applications Voltage amplifier Buffer or impedance matching amplifier.

Module
Part (D): Study of Frequency Response of BJT Amplifier
2
2.45 FREQUENCY RESPONSE OF BJT AMPLIFIER (WORKING OF CE
AMPLIFIER WITH ITS FREQUENCY RESPONSE)

Explain the working of CE amplifier with its frequency response. (MU-O. 4(d), May 19, 10 Marks)
Ua. Marks)
ua. Write short note on frequency response of BJT amplifier. (MU Q.6, Dec. 15. Q. 6(a), Dec. 19, 10
- -

- - - -

1. Circuit diagram +Vcc

Cc2
Rs Cc1 F

Vs
uF

(1F121)Fig. 2.45.1 Circuit diagram of CE amplifier

A
Decreasein gain due.
to coupling and
bypass capacitor
Decrease in gain due
Avmid to internalcapacitors
vimid-
wwwi.aa.a
N2 20dB/decade
or 6 dB/octave.
-20 dB/decade
* *****
r
6 dB/octave
*****************
H-Bw

log
High
Low Mid frequency band frequeno
frequencY{ band
band
General frequency response

General frequency response

(IF122)Fig. 2.45.2:
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 Analog Electronics (MU-Sem.3-Electrical) 2-110 Bipolar Junction Transistor
2. ne response of any amplifier is highly influenced by frequency of applied signal. AT low frequencies, presence
of
coupling and bypass capacitors decreases gain while at high frequencies, internal and stray capacitors decreases gain.

3. In general, any frequency response curve can be splitted in three regions.

(a) LF region (b) MF region (c) HF region

. Mid frequency region: In this region all coupling and bypass capacitors works as short circuit, while stray capacitors
works as open because they are in pico farads. At MF, the AC equivalent circuit is as shown in Fig. 2.45.3.

Also at mid frequencies, the gain of amplifier is given as

Avmd 8nZ, where Z, =R |I R

ww
From AC cquivalent circuit and formula for gain we see
Rc
that there is no capacitance involved and there is no
SR, IR2
frequency term in formulae. Hence in this region gain
remain constant even if frequency varies.

(1F123)Fig. 2.45.3: AC equivalent circuit

5. LF range
Aymid 1
IAvFL 27t RC
From equivalent circuit we can see presence of capacitors.
As we enter in LF, and start decreasing frequency.
Rs
(a) Reactance of CcI (Xce) increases, drop across it
increases, V, decreases therefore gain decreases.
R RLV
(b) XC increase, drop across it increases, therefore V s
decreases; this decreases gain.
(c) XCE increases, therefore Z increases. Increased
voltage across Zg increases AC negative feedback.
This again decreases gain. (1F124Fig. 2.45.4: LF AC equivalent circuit
relation for voltage gain in LF,
Also if we see

AvL also decreases.

voltage gain lAyul depends upon frequency. As frequency decreas
The frequency at which the gain falls to is considered to be boundary frequency and is known as lower cu-o
or corner frequency (D. This is important frequency because at this, output power of amplifier becomes half.

6. HF Range
C Sum of stray capacitors on input side

C Sum stray capacitors on output side

Pvmid
AVHF 27T RC Z pF

(1F125)Fig. 2.45.5: HF AC equivalent circuit

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 Bipolar Junction Transistor
Analog Electronics (MU-Sem.3-Electricall 2-111
Refer HF ac equival circuit Fig. 2.45.5. As we enter in HF range and start increasing frequency.
ases
(a) Reactance of CiAa2rC decreases, current taken by it increases (known as shunting effect), lg ue

therefore Ie also decreases. Hence the gain I gZI decreases, Sinceg = V)

nce
On output side, Aco decreases, the current taken by it increases, this causes output current
to decrease, e
(b)
output voltage decreases. This finally decreases voltage gain of amplifier.
Module
Also if we see relation for lAvHr, as frequency increases, gain of amplifier decreases.
2
Thefrequency at which gain falls to in HF band is known a f (higher cutoff frequency).
C)
6 dB/octave.
Decrease ingain, either in LF or HF band, is with rate 20 dB/ decade or
7 is bandwidth.
which frequency response of any amplifier provide us
8. The important parameter
BW = f - f L
Chapter Ends...