ee |__“"___—_EF Date: 204 Deeemnber NN? RURLA INSTITUTE OF TRCHNOLOGY AND SCIENCI, PILANI ~ KK. BIRLA GOA CAMPUS First Semester 2022-23 [BBEYINSTR F213 ~ Analog and Digital VIST Design CLOSED BOOK Max Marks: 110 Time: 160 min 1. (12 marks) Answer the following questions a Assume a ring oscillator using 5 CMOS Inverters, 5 powvinles a signat with 4596 duty eyele and a period of Dae What is the rive and fall ime of the inverter tw this: ; wy Van) [Vn ) [V0 0 rchnolygy? f fe ee A Cateutate the noise manginsat node at and node bin the} oi circuit in figure 100) Sf ae In the ctrvuit shown in Agure 1 (€), caeulate the raat tel woltages at nodes BCD and B His given that Upp = mre AV Vy = 0.28 Vand Vp, = 0.35 7. = 100r0m, The capsare 0.1 pF. 2 (LO merks) Consider a pseudoNMOS inverter with the Vag Figure (6) following parameters Vy = —Vyp = OAV, Von = 3.30, by = 10 KAYE and y= 40 RA/V?, W/L), = AW / Dp = Assume that a load of 100!F is connected to this circuit. Neglecting the effect of self-loading of the transistor, calculate the L-H (S088) delay for this gate, You may need the following formula 1 versa } @FNC-9 wemles baa) 3 (10 mers) In onder to implement OR4 logic to drive a 10fF on-chip capactaney, we end up with two options, (A) NOR(1X)+INV(SX) or (B) NOR2(2X)+NAND2(X}. Assume the reference is a 2/1 sized inverter, and the gate and diffusion capacitance per unit width is C = 1.25 /F/ym. Calculate the size ratio of NAND2 in option (B) to make the two options achieve the same delay. Assume the minimum CMOS transistor width (1¥j, + W,) is 80am. The convention NOR2(BX) means that the transistors in the NOR2 gate are sized B times larger than the smallest NOR2 gate in the technology. 4. (10 marks) Consider the complex logic gate in figure 4. The widths of the transistors are given. Assume that the minimum width NMOS transistor has an on-resistance of R, a gate cap of Cand aS/D cap of. The smallest inverter is of size P/N=2/1. There is no sharing of diffusions. When calculating delays assume that the internal nodes are charged or discharged as appropriate a. Find the contamination delay for the rising and falling transition and identify the input transition for the same. 1b Find the Elmore delay for the following transitions (ABCD) i (1110)3(0010) : ii, (0000)>(1010) .5. (10 marks) Find the sizes of the transistors in the circuit in figure S, for least delay from input to output. G2 is an AOL gate. Draw the circuit and indicate the sizes clearly along with the input that is in the enitical path The input inverter is minimum — sired with & (9 marks) The sequential arcuit in figure 6, has 2 fip- ops and 2 combinatorial blocks CB1 and CB2. The design is made using a library that includes inverters with 2Sps rise and fall delay. The parameters for the Hops are: fey = 100 PS, foxy = 20 PS. teeeup = 50 PS, and taoug = 100 ps. The parameters for the CLBs are as follows CB1: tay = 250 ps. fog = 100 ps and CB2: tpg = 350 ps. tog = 50 PS. Will the circuit work correctly? Explain and; cL if not. suggest a fix to the flip-flop parameters igure 6 ae that will not affect the maximum frequency at ae" which the circuit can be operated. whe b. Ifthe circuit can be operated correctly, what is the maximum CLK frequency at which it will So work correctly? Suggest modification in the CLK circuitry to increase the frequency found in (b). Explain your solution. 7. (9 marks) Answer the following questions a. An amplifier with forward gain Ay has two coincident poles at w,. Calculate the maximum value of Ag for a 60° phase margin with closed loop gain of (i) unity and (ii) 4. b. Anamplifieghgs a forward gain of Ay = 1000and two poles at wp; and wpa. For pr = 1 MHz, calculate the, unity-gain feedback loop if (i) @p2 = 2wp and (ii) Wpz = 40p1- 8. (10 marks) Design a differential input single ended output amplifier; with input applied toa pMos>$; ( pair; for output voltage swing of 0.8 V. The total bias current is 100A. The size of all transistors | Fhould be equal Keep minimum length as 1}. pnGax = 300 HA/V?,tgCge = 65 pA/V2, Veq = NMOS, 0.36 V, Vzp = —0.5 V. Use Ay = 0.11 V-? and Ay = 0.09 V™, Voy = 1.8V (ra a. Draw the circuit diagram b. Find the overdrive voltages of all transistors c. Find the W/L of all transistors Find Vinemmax 294 Viner min e. Calculate the gain of the amplifier sseeeese All the best tet?