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Experiment 3

The document describes an experiment to demonstrate the functioning of NOR and NAND latches using integrated circuits. The experiment involves setting up NOR and NAND latch ICs on a breadboard with power supply and input/output connections. The procedure tests different input combinations to observe the latch behavior and output states.

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Abdullah Zubair
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39 views3 pages

Experiment 3

The document describes an experiment to demonstrate the functioning of NOR and NAND latches using integrated circuits. The experiment involves setting up NOR and NAND latch ICs on a breadboard with power supply and input/output connections. The procedure tests different input combinations to observe the latch behavior and output states.

Uploaded by

Abdullah Zubair
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Experiment 3

NOR LATCH and NAND LATCH

Aim:
To demonstrate the functioning of NOR and NAND latches using integrated circuits (ICs) in a digital
electronics lab experiment.

Apparatus:

1. NOR latch IC (e.g., 74LS02)


2. NAND latch IC (e.g., 74LS00)
3. Power supply
4. Breadboard
5. Connecting wires

Theory:

1. NOR Latch:
 A NOR latch is a basic memory element that can store one bit of information.
 It consists of two cross-coupled NOR gates.
 The latch has two stable states: SET and RESET.
 The SET state is achieved when Q (output of the first NOR gate) is HIGH and Q' (output
of the second NOR gate) is LOW.
 The RESET state is achieved when Q is LOW and Q' is HIGH.
 The latch can be SET or RESET by applying appropriate input signals.
2. NAND Latch:
 A NAND latch is another type of memory element that can store one bit of information.
 It consists of two cross-coupled NAND gates.
 The latch also has two stable states: SET and RESET.
 The SET state is achieved when Q is LOW and Q' is HIGH.
 The RESET state is achieved when Q is HIGH and Q' is LOW.
 The latch can be SET or RESET by applying appropriate input signals.

Circuit Diagram:
Figure 1 NOR LATCH Figure 2 NAND LATCH

Procedure:
1. Set up the power supply and connect it to the breadboard.
2. Insert the NOR latch IC into the breadboard and connect the power supply pins (Vcc and GND)
of the IC to the appropriate power rails on the breadboard.
3. Connect the input pins (S and R) of the NOR latch IC to the desired input switches or buttons.
4. Connect the output pins (Q and Q') of the NOR latch IC to LED indicators.
5. Repeat steps 2-4 for the NAND latch IC.

Performing the Experiment:


1. Initially, apply logic 0 to both the SET and RESET inputs of the NOR latch.
2. Observe the outputs (Q and Q') on the LEDs. The latch should be in the RESET state.
3. Toggle the input switches/buttons to apply logic 0 to the SET input and logic 1 to the RESET
input of the NOR latch.
4. Observe the changes in the outputs (Q and Q') on the LEDs. The latch should be in the SET state.
5. Repeat steps 3-4 with different input combinations to further explore the latch's behavior.
6. Repeat steps 1-5 for the NAND latch IC to observe its functioning.

Truth Table:
The truth table for both NOR and NAND latches is as follows:

S R Q Q'
0 0 Q Q'
0 1 0 1
1 0 1 0
1 1 X X

In the truth table, S represents the SET input, R represents the RESET input, Q represents the output state
(SET or RESET), and Q' represents the complement of the output state.
Note: X indicates the "don't care" condition, which means the outputs are unpredictable when both S and
R are HIGH simultaneously.

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