CPSS Power Electronics Series

Huafeng Xiao
Xiaobiao Wang

Transformerless
Photovoltaic
Grid-Connected
Inverters
CPSS Power Electronics Series

Series Editors
Wei Chen, Fuzhou University, Fuzhou, Fujian, China
Yongzheng Chen, Liaoning University of Technology, Jinzhou, Liaoning, China
Xiangning He, Zhejiang University, Hangzhou, Zhejiang, China
Yongdong Li, Tsinghua University, Beijing, China
Jingjun Liu, Xi’an Jiaotong University, Xi’an, Shaanxi, China
An Luo, Hunan University, Changsha, Hunan, China
Xikui Ma, Xi’an Jiaotong University, Xi’an, Shaanxi, China
Xinbo Ruan, Nanjing University of Aeronautics and Astronautics, Nanjing Shi,
Jiangsu, China
Kuang Shen, Zhejiang University, Hangzhou, Zhejiang, China
Dianguo Xu, Harbin Institute of Technology, Haerbin Shi, Heilongjiang, China
Jianping Xu, Xinan Jiaotong University, Chengdu, Sichuan, China
Mark Dehong Xu, Zhejiang University, Hangzhou, Zhejiang, China
Xiaoming Zha, Wuhan University, Wuhan, Hubei, China
Bo Zhang, South China University of Technology, Guangzhou Shi, Guangdong,
China
Lei Zhang, China Power Supply Society, Tianjin, China
Xin Zhang, Hefei University of Technology, Heifei Shi, Anhui, China
Zhengming Zhao, Tsinghua University, Haidian Qu, Beijing, China
Qionglin Zheng, Beijing Jiaotong University, Haidian, Beijing, China
Luowei Zhou, Chongqing University, Chongqing, Sichuan, China
This series comprises advanced textbooks, research monographs, professional books,
and reference works covering different aspects of power electronics, such as Vari-
able Frequency Power Supply, DC Power Supply, Magnetic Technology, New
Energy Power Conversion, Electromagnetic Compatibility as well as Wireless Power
Transfer Technology and Equipment. The series features leading Chinese scholars
and researchers and publishes authored books as well as edited compilations. It aims
to provide critical reviews of important subjects in the field, publish new discoveries
and significant progress that has been made in development of applications and the
advancement of principles, theories and designs, and report cutting-edge research
and relevant technologies. The CPSS Power Electronics series has an editorial board
with members from the China Power Supply Society and a consulting editor from
Springer.

Readership: Research scientists in universities, research institutions and the industry,

graduate students, and senior undergraduates.

More information about this series at http://www.springer.com/series/15422

Huafeng Xiao · Xiaobiao Wang

Transformerless Photovoltaic
Grid-Connected Inverters
Huafeng Xiao Xiaobiao Wang
College of Electrical Engineering College of Electrical Engineering
Southeast University Southeast University
Nanjing, China Nanjing, China

ISSN 2520-8853 ISSN 2520-8861 (electronic)

CPSS Power Electronics Series
ISBN 978-981-15-8524-1 ISBN 978-981-15-8525-8 (eBook)
https://doi.org/10.1007/978-981-15-8525-8

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Pte Ltd. 2021
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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Energy Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Utilizing Styles of Solar Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Photothermal Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.2 Photochemical Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.3 Fuel Using . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.4 Photovoltaic Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Solar Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 Monocrystalline Silicon Photovoltaic Cell . . . . . . . . . . . . . . 5
1.3.2 Polycrystalline Silicon Photovoltaic Cells . . . . . . . . . . . . . . 5
1.3.3 Amorphous Silicon Photovoltaic Cells . . . . . . . . . . . . . . . . . 6
1.3.4 GaAs Photovoltaic Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Photovoltaic Power-Generation System . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4.1 Off-Grid PVPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4.2 On-Grid PVPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5 Maximum Power Point Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5.1 Perturbation and Observation Method . . . . . . . . . . . . . . . . . . 9
1.5.2 Incremental Conductance Method . . . . . . . . . . . . . . . . . . . . . 10
1.5.3 Intelligent Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Islanding Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.6.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Transformerless Photovoltaic Grid-Connected Inverters
and Leakage Current Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 Isolated PV Grid-Connected Inverters . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.1 Line-Frequency Isolated Structure . . . . . . . . . . . . . . . . . . . . . 17
2.1.2 High-Frequency Isolated Structures . . . . . . . . . . . . . . . . . . . . 18
2.2 Transformerless PV Grid-Connected Inverters . . . . . . . . . . . . . . . . . . 18
2.2.1 Leakage Current Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.2 Elimination Rules of LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 LC Suppression Techniques for Full-Bridge TLIs . . . . . . . . . . . . . . . 27

v
vi Contents

2.3.1 Combinations of Topology Structures and SPWM

Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.2 Matching Circuit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.4 LC Suppression Techniques for Half-Bridge TLIs . . . . . . . . . . . . . . . 29
2.4.1 Combinations of Topology Structures and SPWM
Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4.2 Matching Circuit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.4.3 LC Suppression Techniques for Common-Ground
TLIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4.4 Combinations of Topology Structures and SPWM
Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.4.5 Matching Circuit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3 Full-Bridge Transformerless PV Grid-Connected Inverters . . . . . . . . . 35
3.1 Conventional Full-Bridge TLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.1 Bipolar SPWM Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.2 Unipolar SPWM Modulation . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 Full-Bridge TLIs with Decoupling Branches . . . . . . . . . . . . . . . . . . . 40
3.2.1 HERIC Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.2 H5 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.3 H6-I Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2.4 H6-II Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2.5 H6-III Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2.6 H6-IV Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.2.7 H6-V Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.2.8 Double Inductors Dual Buck Inverter . . . . . . . . . . . . . . . . . . 69
3.2.9 High Efficiency and Reliability Transformerless
Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.3 Full-Bridge TLIs with Clamping Branches . . . . . . . . . . . . . . . . . . . . . 80
3.3.1 Clamping Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.3.2 Optimized H5 Transformerless Inverter . . . . . . . . . . . . . . . . 82
3.3.3 Diode Clamping H5 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.3.4 Full-Bridge DC Bypassed Inverter . . . . . . . . . . . . . . . . . . . . . 90
3.3.5 Active Clamping H6 Inverter I . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.6 Active Clamping H6 Inverter II . . . . . . . . . . . . . . . . . . . . . . . 101
3.3.7 Full-Bridge Zero-Voltage Rectifier Inverter . . . . . . . . . . . . . 105
3.3.8 Diode Clamping Full-Bridge Zero-Voltage Rectifier
Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.3.9 HERIC with Tri-direction Clamping Cell Inverter . . . . . . . . 113
3.3.10 Optimized HERIC Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.3.11 Full-Bridge with Constant Common-Mode Voltage
Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Contents vii

3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4 Half-Bridge Transformerless PV Grid-Connected Inverters . . . . . . . . 129
4.1 Conventional Half-Bridge TLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.2 I-Type Half-Bridge TLIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.2.1 NPC Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.2.2 Active NPC Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.2.3 Double Capacitors Legs NPC Inverter . . . . . . . . . . . . . . . . . . 143
4.2.4 Split-Inductor NPC Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 146
4.2.5 Diode Split-Inductor NPC Inverter . . . . . . . . . . . . . . . . . . . . 154
4.2.6 Six-Switch Five-Level Active Neutral Point
Clamped Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
4.3 T-Type Half-Bridge TLIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.3.1 Conventional T-NPC Inverter . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.3.2 Reduced Switches T-NPC Inverter . . . . . . . . . . . . . . . . . . . . . 163
4.3.3 Diode-Free T-NPC Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.4 Stacked Neutral Point Clamped TLIs . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.4.1 Conventional S-NPC Inverter . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.4.2 Active Stacked NPC Inverter . . . . . . . . . . . . . . . . . . . . . . . . . 179
4.4.3 High-Efficiency Stacked NPC Inverter . . . . . . . . . . . . . . . . . 182
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5 Common-Ground Transformerless Grid-Connected Inverters . . . . . . 189
5.1 Capacitor-Based Common-Ground TLIs . . . . . . . . . . . . . . . . . . . . . . . 189
5.1.1 Capacitor-Based Common-Ground Inverter I . . . . . . . . . . . . 189
5.1.2 Capacitor-Based Common-Ground Inverter II . . . . . . . . . . . 193
5.1.3 Capacitor-Based Common-Ground Inverter III . . . . . . . . . . 197
5.1.4 Capacitor-Based Common-Ground Inverter IV . . . . . . . . . . 201
5.2 Inductor-Based Common-Ground TLIs . . . . . . . . . . . . . . . . . . . . . . . . 206
5.2.1 Karschny Common-Ground Inverter . . . . . . . . . . . . . . . . . . . 207
5.2.2 Flying Inductor Transformerless Inverter . . . . . . . . . . . . . . . 209
5.2.3 Aalborg Transformerless Inverter . . . . . . . . . . . . . . . . . . . . . . 210
5.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6 DC Current Rejection for Transformerless Grid-Connected
Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.1 DC Component in Grid-In Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.1.1 Summarizing Analysis of DC Components . . . . . . . . . . . . . 217
6.1.2 Influence of DCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.1.3 Standards Limitations of DCC . . . . . . . . . . . . . . . . . . . . . . . . 219
6.1.4 Quantitative Analysis of DCC . . . . . . . . . . . . . . . . . . . . . . . . 220
6.2 Detection and Feedback Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.2.1 Coupled-Inductor Detection Method . . . . . . . . . . . . . . . . . . . 224
viii Contents

6.2.2 Sensor Auto-Calibration Method . . . . . . . . . . . . . . . . . . . . . . 225

6.2.3 DC-Link Current Sampling Method . . . . . . . . . . . . . . . . . . . 230
6.2.4 Double Integration Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
6.2.5 Resonant-Circuit Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
6.2.6 Bridge-Leg-Voltage Detection Method . . . . . . . . . . . . . . . . . 239
6.3 Capacitor Blocking Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.3.1 DC-Side Capacitor Blocking Method . . . . . . . . . . . . . . . . . . 240
6.3.2 AC-Side Capacitor Blocking Method . . . . . . . . . . . . . . . . . . 241
6.4 Intelligent Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.4.1 Fuzzy Iterative PI Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.4.2 BP Neural Network Method . . . . . . . . . . . . . . . . . . . . . . . . . . 245
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Chapter 1
Introduction

Abstract Photovoltaic power generation (PVPG) is an important part of renewable

energy and is considered as the most potential renewable energy around the world.
Major countries have invested huge amounts of money to compete in research and
industrialization activities. Until 2018, global-installed solar PV capacity had reached
505 GW [1]. PVPG started developing a bit late in China, but it is developing signif-
icantly fast. According to the statistics, between 2010 and 2015 years [1], a miracle
was created that worldwide cumulative installation capacity increased 100 times in
5 years. As a result, China has taken the first place in total PVPG accumulative
installed capacity since 2015, as well as the ratio of China’s PVPG installed capacity
to total capacity had reached 7% at the end of 2018. It produced 4% of the total power
generation amount during 2018. At the same time, China Electric Power Research
Institute reported that the average cost of PVPG plants had been reduced by 45% in
2017 compared with 2012.

Keywords Photovoltaic power generation · China · First place · Cost down

1.1 Energy Challenges

Human beings experienced energy utilization styles from the age of firewood to coal,
oil, gas, and electricity. While the total energy consumption is increasing constantly,
the proportions of different energy are also changing predicted by the Joint Research
Centre of European Commission in 2004 [2]. Every transition of the energy is accom-
panied by a huge leap in productivity, which has greatly promoted the development
of economy and society.
At the same time, with the increasing consumption of energy, especially for fossil
energy, the restriction of energy on economic and social development and the damage
to the environment are becoming significantly apparent, such as urban smoke caused
by soot pollution, automobile exhaust and industrial exhaust pollution, acid rain, the
ozone layer damaged, soil loss, mining earthquake, marine pollution, and nuclear
pollution, so far. Scientific observations show that the concentration of CO2 in atmo-
sphere has increased from 280 ppmv before the industrial revolution to the current

© The Editor(s) (if applicable) and The Author(s), under exclusive license 1
to Springer Nature Singapore Pte Ltd. 2021
H. Xiao and X. Wang, Transformerless Photovoltaic Grid-Connected Inverters,
CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-8525-8_1
2 1 Introduction

379 ppmv, and the global average temperature has also increased by 0.74 °C in the
past century.
A series of challenges in front of human beings force us to think about the solu-
tions, that is, how to find a way out for human energy? The answer is “drive the world
with sunlight!” The sun is the source of life on earth and also the source of energy,
which can be continuously regenerated. The development of renewable energy can
gradually meet the human energy needs, and is also an urgent need to protect the
environment.
As a kind of renewable energy, solar energy can be directly converted and used.
Calculations show that only 130,000 km2 of photovoltaic (PV) panels need to be
installed in China to meet the whole nation’s energy consumption. According to
China’s annual building construction area of 2 billion square meters, China’s urban
construction area can reach 32,000 km2 , rural construction area can reach 21,000
km2 , and the effective install area for PV panels can reach 10,000 km2 by adding
the southern wall areas at the end of 2020. Therefore, the development potential of
building-integrated PV (BIPV) is huge.

1.2 Utilizing Styles of Solar Energy

Since the birth of life on earth, it has been mainly survived by the thermal radiation
provided by the sunshine. Humans have also understood that objects can be dried
by the sunshine since ancient times, and treat that as a method of making food,
such as salt making and salted fish. With the decrease of fossil fuels, solar energy is
becoming an important part of human energy utilization, and develops quickly. In a
broad sense, wind energy, chemical energy, and water energy on the earth all belong
to solar energy. From a narrow sense, utilization of solar energy mainly includes
photothermal, photochemical, photovoltaic, and other conversion forms.

1.2.1 Photothermal Conversion

The principle of photothermal conversion is to collect solar radiation energy, and then
convert it into thermal energy by medium interaction [3]. There are four types of solar
collectors so far; they are flat-plate collector, vacuum tube collector, ceramic solar
collector, and focusing collector. According to medium temperatures, photothermal
utilizations can be classified into low-temperature utilization (<200 °C), medium-
temperature utilization (200–800°C), and high-temperature utilization (>800 °C),
respectively. For example, low-temperature utilization mainly includes solar water
heaters, solar dryers, solar air-conditioning refrigeration systems, and so on; solar
stoves belong to medium-temperature utilization; high-temperature solar furnace is
one example of high-temperature utilization.
1.2 Utilizing Styles of Solar Energy 3

Currently, the most successful commercialization form of photothermal conver-

sion is solar water heater. Its working principle is to convert sunshine energy into
thermal energy to heat water for needs in daily life and industrial applications.

1.2.2 Photochemical Conversion

Photochemical conversion is a process of absorbing sunshine energy for chemical

reactions to obtain chemical energy [3], such as photosynthesis of plants.
In recent years, a lot of PVPG plants were built in western China, but electricity
consumers are located in eastern China, so electricity transmission pressure is put
on the high-voltage transmission grid, and has caused severe abandonment of PV
electricity. In order to relieve this pressure, some cities have launched a plan named
as “ten cities one thousands of hydrogen fuel cell vehicles”. In this situation, use PV
electricity to produce hydrogen by electrolyzing water in the places of PVPG plants,
and then ship the produced hydrogen to different cities to fuel vehicles. Along with
the fast development and cost down of PV electricity and electrolyzing water, the
conversion between solar energy and hydrogen through photovoltaic process will
be a profitable way to guarantee China’s energy security and optimize the energy
structure.

1.2.3 Fuel Using

A new engine fuel named as “solar fuel” can be made of water and carbon dioxide
catalyzed by high-temperature energy from sunshine. The European Union has
successfully implemented the full-process production of laboratory-scale renewable
fuel around the world for the first time in June 2011, and the produced fuel fully
complies with the European Union standards in terms of aircraft and automotive
fuel. As a result, there is no need for any modification of aircraft and automobile
with engines.
The designed “solar fuel” prototype mainly has two parts: the first part uses high-
temperature energy generated by the concentrated solar light, supplemented by the
metal oxide material additives invented by the ETH Zürich’s intellectual property,
water and carbon dioxide to synthesize mixture gas. The second part works based on
the Fischer–Tropsch process, which converts the high-temperature mixture gas into
“solar fuel” product that can be commercially applied to the market.
4 1 Introduction

1.2.4 Photovoltaic Conversion

There are two ways to convert sunlight into electricity, that is, photovoltaic converting
directly, or indirectly converting from sunshine to electricity through thermal energy.
1. Light to heat to electricity conversion

The operation process is that the thermal energy generated from solar radiation is
used to generate electricity [4]. Commonly, a solar collector is used to convert the
absorbed thermal energy into working medium steam, and then the steam drives a
gas turbine to drive a generator to generate electricity. The first process is light to
heat conversion, and the second process is heat to electricity conversion.
At present, the most promising solar thermal power generation systems can be
roughly classified into three kinds: trough-shaped parabolic focusing system, central
receiver or solar tower focusing system, and disc-shaped parabolic focusing system.
The three forms that are technically and economically feasible are: 30–80 MW
focused parabolic trough solar thermal power-generation technology (parabolic
trough type); 30–200 MW point-focused central-receiving solar thermal power-
generation technology (central receiving type); 7.5–25 kW point-focused parabolic
disc solar thermal power-generation technology (parabolic disc type).
2. Light to electricity conversion

The basic operating principle is to directly convert solar radiant energy into elec-
trical energy using the photovoltaic effect [5]. Its basic device is solar cells.
The development history, technical characteristics, and application styles will be
discussed in detail in the next section. It is the main application form of renewable
energy technology and is the most successful form of solar energy utilization for
commercialization and large-scale application.

1.3 Solar Cell

Solar cell is a device that converts sunlight into electricity based on the photo-
voltaic effect. The photovoltaic effect was first discovered by French scientist A.E.
Becquerel in 1839. The first solar cell was manufactured by Charles Fritts in 1883.
At the very beginning, Charles overlaid a very thin metal layer on the selenium semi-
conductor to form a semiconductor metal junction, but its conversion efficiency was
only 1%, which was not practical. With the improvement of semiconductor physics
and manufacturing technology, researchers from Bell Labs in the United States found
that doping a certain amount of impurities in silicon would make it more sensitive
to light, and produced the first single-crystal silicon solar cell with an efficiency of
6% in practical application value in 1954 [3–5]. Nowadays, solar cell technology
has made great progress, and the efficiency of commercialized single-crystal silicon
1.3 Solar Cell 5

solar cells has reached 20%, as well as many types of commercialized batteries have
been designed, such as cadmium telluride batteries, copper indium gallium selenium
batteries, and amorphous silicon batteries. At the same time, novel solar cells with
high efficiency are being developed. Advances of photovoltaic cell technology drive
the cost of photovoltaic power generation down. The cost gradually approaches
the level that can compete with conventional power generation and promotes the
development of the photovoltaic industry.
There have been many types of solar cells so far [3–5]. According to structures:
homojunction solar cells, heterojunction solar cells, Schottky solar cells, and liquid
junction solar cells, and so on; while according to materials: silicon solar cells,
sensitized nanocrystalline solar cells, organic compounds and inorganic compounds,
semiconductor solar cells, thin-film solar cells, and so on. The following briefly
introduces the mainstream solar cells with the highest acceptance in the market.

1.3.1 Monocrystalline Silicon Photovoltaic Cell

Monocrystalline silicon photovoltaic cells are a type of photovoltaic cell that was
developed earlier and has the highest conversion efficiency. The conversion efficiency
of monocrystalline silicon photovoltaic cells has reached an average of 16.5% in
China, and the highest conversion efficiency recorded in the laboratory has exceeded
24.7% [3–5]. This photovoltaic cell generally uses high-purity monocrystalline
silicon rods as raw materials, and the purity requires 99.9999%.

1.3.2 Polycrystalline Silicon Photovoltaic Cells

Polycrystalline silicon photovoltaic cells are made of polycrystalline silicon mate-

rials [3]. Because polycrystalline silicon materials are mostly produced in casting
instead of the drawing process of the monocrystalline silicon, the production time
is shortened significantly, and the manufacturing cost is greatly reduced as well.
In addition, the monocrystalline silicon rod is cylindrical, and the produced wafers
are round shape too; as a consequence, the utilization rate of the panel is low after
forming the photovoltaic module. Compared with monocrystalline silicon photo-
voltaic cells, polycrystalline silicon photovoltaic cells appear to have a certain
competitive advantage in the market.
6 1 Introduction

1.3.3 Amorphous Silicon Photovoltaic Cells

Amorphous silicon photovoltaic cells are a new type of thin-film battery composed
of amorphous silicon as a raw material [4]. Amorphous silicon is a kind of semi-
conductor with amorphous crystal structure. The thickness of amorphous silicon
photovoltaic cells is only 1 µm, which is equivalent to 1/300 of monocrystalline
silicon photovoltaic cells. Most importantly, its manufacturing process is greatly
simplified, the silicon material consumption is low, and its unit power consumption
is also greatly reduced.

1.3.4 GaAs Photovoltaic Cells

GaAs photovoltaic cells are III–V compound semiconductor photovoltaic cells [4].
Compared with silicon photovoltaic cells, GaAs photovoltaic cells have high photo-
electric conversion efficiency. For instance, the theoretical efficiency of silicon photo-
voltaic cells is 23%. However, the conversion efficiency of single-junction GaAs
photovoltaic cells has already reached 27%. It can be made as thin film and ultra-
thin solar cells. For example, GaAs photovoltaic cells only need to be 5–10 µm in
thickness to absorb 95% of sunlight, but silicon photovoltaic cells need to be thicker
than 150 µm.

1.4 Photovoltaic Power-Generation System

PVPG usually consists of PV arrays, solar tracking equipment (optional), battery

pack (optional), battery controller (optional), and inverter, which can supply AC and
DC loads, as well as store excess energy in batteries or send it to the grid, as shown
in Fig. 1.1.

Controller Inverter Grid

PV
Battery DC load AC load

Fig. 1.1 Schematic diagram of PVPG

1.4 Photovoltaic Power-Generation System 7

1.4.1 Off-Grid PVPG

Off-grid PVPG is also named as independent PVPG, which means that this system
does not connect to the grid. It is mainly composed of solar arrays, controllers, and
batteries. In addition, an AC inverter is also required if there are AC loads in the
PVPG. Generally speaking, off-grid PVPGs include remote village power supply,
household solar power supply, communication power source, street lights source,
and so on.

1.4.2 On-Grid PVPG

On-grid PVPG is also called as grid-connected PVPG, and the DC power generated
by solar array is directly delivered into the public grid. On-grid PVPG may integrate
with batteries or not [5]. Obviously, the on-grid PVPG with batteries is dispatchable
according to the needs; in addition, it can be treated as a backup power source for
emergency loads when the grid fails.
On-grid PVPG without batteries is the most popular PVPG form. There are
different circuit structures according to power ratings, battery connection methods,
converter architectures, as shown in Fig. 1.2.
1. Centralized type

The centralized PVPG is the earliest structure in practice, as shown in Fig. 1.2a. Its
capacity is generally tens to hundreds of kilowatts. The system structure connects a
large number of photovoltaic arrays in series to a higher voltage level first, and then
collects them to a high current output through diodes in parallel. Finally, collected
DC electricity is fed into the grid through a centralized inverter. The main advantages
of centralized PVPG are high efficiency and low cost. But there are also issues, such
as low utilization of single photovoltaic arrays, poor ability to against local shadows,
and inconvenient maintenance. The centralized PVPG is generally used in ground
photovoltaic power farms with large capacity.
2. String and multi-string types

In order to avoid the mismatch loss of multiple strings in the centralized PVPG, string
and multi-string structures have emerged on the market, as shown in Fig. 1.2b and
c, respectively. Among them, each string has an independent maximum power point
tracking (MPPT) controller. Generally, the string-type PVPG is installed on the roof
of small power residential; the multi-string-type PVPG adopts a two-stage circuit,
and the front stage is scalable to fit different positions of PV arrays on the building.
However, these systems still have the following problems in practical applications:
(1) Although the MPPT controller solves the mismatch loss between the strings, the
battery modules in each string cannot be guaranteed to run at the maximum power
point; (2) the system maintenance is still difficult.
8 1 Introduction

a b c

PV PV PV PV PV PV PV

PV PV PV PV PV PV PV

DC DC
PV PV PV PV PV DC DC

DC BUS
DC DC DC DC
AC AC AC AC
AC grid AC grid AC grid

e
d
PV PV PV
PV PV PV
DC DC DC
DC DC DC
DC BUS
DC DC DC
AC AC AC
AC grid DC
AC
AC grid

Fig. 1.2 Structures of typical PVPG systems, a Centralized type, b String type, c Multi-string type,
d AC modular type, e DC modular type

3. AC module type

The AC module PVPG integrates a grid-connected inverter with MPPT function for
each PV module, as shown in Fig. 1.2d. The advantages of this structure are that each
PV module can be guaranteed to work at its maximum power point, and has strong
ability to stand local shadow. It is convenient to scale up and maintain. In addition,
the AC module PVPG supports plug and play. However, it still has the shortcomings
of low conversion efficiency, complex system circuit, and high cost.
4. DC module type

The DC module PVPG combines the characteristics of multi-string and AC module

structures, composed of multiple DC modules and a centralized inverter, as shown
in Fig. 1.2e. The MPPT function is implemented in different DC converters for each
PV module, and the centralized inverter connects DC bus and the AC grid.
With the development of PVPG technology, some new system structures have
also appeared in recent years, such as improved string structure based on bypass
1.4 Photovoltaic Power-Generation System 9

DC modules, improved string system based on power generation control circuits,

cascaded DC module system, and AC battery cell system [3].

1.5 Maximum Power Point Tracking

The efficiency of PVPG system is the product of PV panel conversion efficiency,

MPPT efficiency, and the inverter efficiency. Therefore, improving the MPPT effi-
ciency is of great significance for increasing the system efficiency and reducing the
cost. Under different radiation levels and PV cell temperatures, the maximum output
power points of photovoltaic cells are different, as shown in Fig. 1.3. Figure 1.3a
shows the current–voltage (I–U) curves of a PV module, and its power–voltage (P–
U) curves are shown in Fig. 1.3b, where S represents the radiation level, and I, U, and
P are the output current, voltage, and power of a PV module, respectively. In order to
track the maximum output power, some measures have to be taken to automatically
follow the changes in environmental conditions. The MPPT technology has been
proposed in response to this issue [3].
Conventional MPPT algorithms include open-circuit voltage method, short-circuit
current method, perturbation-observation method, incremental conductance method,
and so on [6, 7]. Recently, some intelligent tracking algorithms have appeared, such
as fuzzy control algorithms and neural network algorithms. Several widely used
MPPT algorithms are induced as follows.

1.5.1 Perturbation and Observation Method

The perturbation and observation method finds the maximum power point by
increasing and decreasing the output voltage of PV strings with a small step based

18 600
S=1000W/m2 S=1000W/m2
16
500 S=800W/m2
14 S=800W/m2 S=600W/m2
12 400 S=400W/m2
S=600W/m2
10
P /W
I /A

300
8 S=400W/m2
6 200
4
100
2
0 0
0 10 20 30 40 50 0 10 20 30 40 50
U /V U /V

Fig. 1.3 Output characteristic curves of a PV module, a I–U curve, b P–U curve
10 1 Introduction

on measuring and comparing power variations [8, 9]. Briefly speaking, the algorithm
keeps adjusting the output voltage with the same step if the output power variation
is positive; otherwise, change the step with opposite direction. Obviously, this algo-
rithm belongs to hill-climbing method, and depends on the P–U curves, as shown in
Fig. 1.3b. It is the most commonly used MPPT method in practice, but it results in
power loss due to small voltage oscillations.

1.5.2 Incremental Conductance Method

The increment conductance method essentially belongs to hill-climbing method too

[10]. It is proposed based on that the derivative of the PV cell output power to voltage
is zero at the maximum power point. Therefore,

dP d(U I ) dI
= = I +U =0 (1.1)
dU dU dU
Then the incremental conductance terms are obtained,

I dI
+ = G + G = 0 (1.2)
U dU
The change of the control signal is decided by detecting instantaneous conductance
G and conductance increment G of the PV string output, and comparing these
two values with zero. The outstanding advantage of the incremental conductance
method is that the amplitude of its voltage oscillation is relatively small. However,
the determination of the voltage increment step is much complicated. For instance,
the tracking error will be large if the step is too large; on the contrary, the tracking
speed will be slower. On the other hand, the incremental conductance method requires
high accuracy and response time of the sensors and detection circuits.

1.5.3 Intelligent Algorithms

In practical applications, complex environments such as local shadows often make

the P–U characteristic curves of PV arrays present multiple power pick points.
For conventional direct MPPT control methods based on sampled data, such as
above-mentioned perturbation and observation method, and incremental conduc-
tance method, they tend to be trapped in local peak points and cause serious power
mismatch. As a consequence, the local peak points not only lose energy but also
damage PV cells because of hot spot phenomenon. Therefore, how to track the
global maximum power point in the case of local shadows is a critical issue needed
to be solved.
1.5 Maximum Power Point Tracking 11

The main idea is to introduce intelligent algorithms into the conventional MPPT
methods to implement a global search task [10, 11]. There are several intelligent
MPPT methods listed as follows:
1. Particle swarm optimization algorithm

Particle swarm optimization algorithm is a global optimization method based on

multi-extremal function, which resulted from foraging behavior of birds. In the
continuous iterative process of particles, the update of positions and velocities is
under the influence of its own optimal solution and the group optimal solution, so
that the particles move to the position of the group optimal solution to achieve global
optimization [12]. Taking MPPT application as an example, the target is to find the
best particle (control parameter), so that the objective function (output power) has a
global optimal solution, that is, the global maximum power point of the array.
2. Fuzzy algorithm

The essence of fuzzy logic control is a logical reasoning system based on the expe-
rience and intuition of the equipment operator, which is suitable for some systems
whose mathematical models are difficult to build. For nonlinear output characteris-
tics of PVPG systems affected under factors of temperature and irradiance, a suitable
control fuzzy rule table can be formulated based on the PV output characteristics and
operating experience. The working voltage can be fast and accurately stabilized at
the maximum power point [13–17].
Because traditional fuzzy logic control is not suitable for the global MPPT problem
under local shadows, Hopfield neural network can be used to optimize the fuzzy logic
controller so that it has a dynamic fuzzy rule table [17]; or using immune algorithm
to optimize fuzzy logic control, for instance, combined with the double advantages
of fuzzy logic theory and artificial immune theory, the global maximum power point
can be achieved under local shadows [16].
3. Neural Network Algorithm

Neural network technology is a kind of control technology that mimics human

thinking. It does not depend on the mathematical model of the controlled process,
and features strong anti-interference ability and black box learning ability. Therefore,
it is quite suitable for the MPPT function of PVPG systems [18, 19]. However, the
learning mode of the neural network algorithm requires long-term training, and the
relationship between input and output data is difficult to be expressed.

1.6 Islanding Detection

Islanding refers to an electrical phenomenon that the distributed generator continues

to supply power for the local loads when the power grid is disconnected from an area
covering PVPG and loads [20–22]. The islanding phenomenon is shown in Fig. 1.4,
12 1 Introduction

Fig. 1.4 Schematic diagram P+jQ ∆P+j∆Q

of isolated islanding
ug
powered by PVPG system PVgrid-
connected system

PLoad+jQLoad

R L C

where P and Q represent active power and reactive power, respectively, ug represents
the power grid, and R, L, and C are resistor, inductor, and capacitor of local loads,
respectively. When the output power of the PVPG matches the load consumption, that
is, P = Q = 0, the voltage and frequency of the local power area will not change
basically after the grid-connected circuit breaker is disconnected. As a consequence,
the passive protection algorithm is not able to identify the absence of the grid.
When the islanding phenomenon occurs, it will cause serious consequences if the
PVPG fails to detect the islanding state timely and quickly, including but not limited:
(1) Users’ equipment might be damaged when the voltage and frequency of the
islanding area exceed a certain range because of the absence of the grid.
(2) May damage the bus or maintenance people.
(3) Reclosing of circuit breaker may cause rush current and damage the equipment
associated with the grid because of mismatch phase angle.
In order to avoid the above-mentioned damages, international standards, such as
IEEE Std 929-2000 [23] and UL1741 [24], put forward mandatory requirements for
islanding detection methods of distributed generators. The main technical terms are
shown in Table 1.1.
According to China’s technical standard GB/T 29319-2012 [25], the allowable
deviation of the phase voltage is −10% to +7% of the rated voltage, the frequency
at the point of common coupling is in the range of 49.5−50.2 Hz, the total harmonic
current should be less than 5% of the rated output current, and the DC current compo-
nent in the grid-connected current cannot exceed 0.5% of its rated output current
when the grid is working normally. The response time against the abnormal grid is
basically consistent with Table 1.1. In addition, there are some specific limitations
as listed in the following:
(1) The PVPG system should have the ability to quickly identify islanding and
immediately disconnect from the grid;
(2) The response time of the anti-islanding protection should be shorter than 2 s,
and the acting should be compatible with relay protection;
(3) The PVPG should not deliver power in 20–300 s after the grid return to normal.
1.6 Islanding Detection 13

Table 1.1 IEEE Std 929-2000/UL1741 requirements for maximum response time of islanding
detection
Status Voltage amplitude after Frequency after power Allowed maximum
power off off/Hz detection time
A u < 0.5unom f nom 6 power frequency
cycles
B 0.5unom ≤ u ≤ 0.88unom f nom 2s
C 0.88unom ≤ u ≤ 1.10unom f nom 2s
D 1.10unom ≤ u ≤ 1.37unom f nom 2s
E 1.37unom ≤ u f nom 2 power frequency
cycles
F unom f < f nom –0.7 6 power frequency
cycles
G unom f > f nom + 0.5 6 power frequency
cycles
unom refers to the nominal value of the grid voltage amplitude, f nom refers to the nominal value of
the grid voltage frequency, the quality factor Qf of RLC loads is not less than 2.5

In order to meet the above-mentioned detection requirements, a large number of

detection methods have been proposed and reported [26–30]. According to the imple-
mentation styles, they can be classified into two categories: remote islanding detec-
tion algorithms and local islanding detection algorithms. The remote islanding detec-
tion algorithm uses the communication medium to remotely collect grid-related state
data to identify potential islanding. The measures feature high reliability but high
cost. Therefore, it is not suitable for distributed PVPG with small and medium power
ratings.
The local islanding detection algorithm is used to determine the islanding state
by detecting the state of the grid, which is simple to implement and cost-effective.
The implementation methods can be classified into two categories, namely passive
islanding detection methods and active islanding detection methods. The passive
islanding detection method recognizes islanding by monitoring the voltage param-
eters and their variations, such as over/under voltage, phase abruption, over/under
frequency, or abrupt change of frequency. It is simple and cheap, but has a large
non-detection zone. The active islanding detection methods inject disturbances into
point of common coupling to identify the islanding state through monitoring param-
eter changes, such as active power disturbances, reactive power disturbances, load
injection, and frequency shifting and phase shifting. As a result, the non-detection
zone is significantly reduced. However, the injected disturbances would affect the
power quality and stability of the power grid.
14 1 Introduction

1.6.1 Summary

This chapter briefly describes the current state of energy around the world, and points
out that solar energy, as a renewable energy source, plays an important role in solving
energy shortages and environmental pollution. Then, several types of utilization of
solar energy are outlined, among which the photovoltaic power generation is the
most important one. Finally, a series of key technologies related to grid-connected
PVPG system are discussed, such as maximum power point tracking technology and
islanding detection technology.

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Chapter 2
Transformerless Photovoltaic
Grid-Connected Inverters and Leakage
Current Issue

Abstract As the interface between PV strings and the grid, grid-connected inverters
perform functions of converting power generated by PV modules into the grid. Gener-
ally, some indexes are used to evaluate its performance, such as conversion efficiency,
volume, cost, and grid-in current quality. This chapter mainly focuses on topologies
of distributed PV grid-connected inverters, including isolated type and non-isolated
type (also called as transformerless type). Especially, the leakage current issue of
transformerless grid-connected inverters is deeply discussed. Further, a common-
mode voltage model at switching frequency scale has been built, and restriction rules
of leakage current have been concluded. Finally, the proposed restriction rules are
discussed and used in full-bridge, half-bridge, and common-ground type topologies.

Keywords PV grid-connected inverte · Transformerless · Leakage current ·

Combination · Matching

2.1 Isolated PV Grid-Connected Inverters

The topology structure of grid-connected inverters is closely related to the efficiency,

cost, security, reliability, and grid-in current quality of PVPG system. Generally
speaking, grid-connected inverters have single-phase and three-phase structures.
According to whether transformer components are included or not, they can be classi-
fied into line-frequency isolated, high-frequency isolated, and non-isolated structures
[1–3].

2.1.1 Line-Frequency Isolated Structure

A line-frequency transformer is inserted at the AC output side of the inverter to

make galvanic isolation between PV modules and the grid, which is named as the
line-frequency isolated PVPG system, as shown in Fig. 2.1. This structure ensures
personal safety, and is beneficial to match the output voltage and suppress the DC

© The Editor(s) (if applicable) and The Author(s), under exclusive license 17
to Springer Nature Singapore Pte Ltd. 2021
H. Xiao and X. Wang, Transformerless Photovoltaic Grid-Connected Inverters,
CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-8525-8_2
18 2 Transformerless Photovoltaic Grid-Connected Inverters …

Fig. 2.1 Line-frequency

isolated structure

PV ug
Line-frequency
transformer

component going into the grid. However, the line-transformer increases the size,
weight, and cost of the PVPG system, and reduces the conversion efficiency of it
[4, 5]. Grid-connected inverters with line-frequency transformers are applied typi-
cally in high-power three-phase and few single-phase PVPG systems; commonly,
the conversion efficiency range of the line-frequency PVPG system is from 94 to
96%.

2.1.2 High-Frequency Isolated Structures

The line-frequency isolated structure is excluded in low-power and medium-power

PVPG applications because of big size, high weight, and cost. Inserting a high-
frequency transformer into the DC/AC conversion link is an alternative method to
realize the galvanic isolation and voltage matching. At the same time, the high-
frequency transformer significantly reduces the size, weight, and cost.
According to forms of the DC bus in the power conversion link, there are three
kinds of high-frequency isolated structures, that is, DC-link form [6–8], pseudo DC-
link form [9–16], and without DC-link form [17, 18], as shown in Fig. 2.2a, b, and
c, respectively.
The topology circuits of low-power PVPG are significantly enriched because of
inducing the high-frequency transformer, and are popularly installed in residential
applications at the very beginning. However, the inserted high-frequency transformer
makes the conversion circuits sophisticated, and results in low conversion efficiency
of 90–95%.

2.2 Transformerless PV Grid-Connected Inverters

An inverter structure with neither line-frequency nor high-frequency transformer is

named as transformerless grid-connected inverter (TLI), which brings the advantages
of higher efficiency, simple circuit, and reduced weight and cost. In general, TLIs
have single-stage and two-stage topologies [19], as shown in Fig. 2.3a, b, respectively.
Two-stage TLIs fit wide input voltage range and simple system design since
the pre-stage DC to DC converter and the post-stage inverter can be controlled and
optimized separately. Single-stage TLIs require higher input voltage from PV strings,
which should be higher than the peak voltage of the grid but offer higher efficiency
2.2 Transformerless PV Grid-Connected Inverters 19

(a)

PV ug
High-frequency
transformer
(b)

PV ug
High-frequency
transformer
(c)

PV ug
High-frequency
transformer

Fig. 2.2 High-frequency isolated structures, a structure with DC/DC stage, b structure with pseudo
DC/DC stage, c Structure without DC/DC stage

(a) (b)

PV ug PV ug

Fig. 2.3 Transformerless grid-connected inverters, a single-stage structure, b two-stage structure

than two-stage TLIs. With the trend that the output voltage of PV strings rises toward
1500 V (medium voltage), the single-stage TLIs will gain more market share in the
future.
Due to the advantages of TLIs, almost all photovoltaic inverter manufacturers have
launched their TLI product lines; the companies include Sunways, SMA, Sungrow
Power, Growatt, and so on.
20 2 Transformerless Photovoltaic Grid-Connected Inverters …

2.2.1 Leakage Current Issue

TLIs feature higher efficiency, smaller volume, and lower cost compared with isolated
counterparts. However, PVPG without transformer results in a galvanic connection
between the PV arrays and the grid [20–22]. Owing to the emergence of parasitic
capacitors between the PV arrays and the earth, as shown in Fig. 2.4, high-frequency
potential differences induced by switching actions may stimulate leakage current
(LC), also called as common-mode current or ground current. The high-frequency
LC results in severe conduction and radiation, electromagnetic interference, grid-
in current distortion, and energy loss, and it can even jeopardize equipment and
individual safety.
In order to guarantee the safety of individual and equipment, the LC of TLIs
has to comply with the mandatory standards. For example, the German standard
VDE0126-1-1 requires that leakage currents greater than 300 mA must trigger a
break within 0.3 s [23]. Besides, irrespective of the rated power of the inverter, any
sudden leakage currents should trigger the break at certain time. Table 2.1 shows
the sudden change amounts and related break times.
Chinese standard NB/T 32004-2013 also states that PVPG must be quit within
0.3 s and alarms if LC exceeds 300 mA for rated PVPG lower than 30 kVA, and
10 mA/kVA for rated PVPG higher than 30 kVA [24]. Meanwhile, the protection
procedure and limitations of LC changes are in accordance with Table 2.1.
Leakage current issue is of great importance because it is directly related to the
quality certification and marketing authorization of TLI products. That is the reason
why North American, Japan, and Australia forbade TLIs in PVPG system at the
beginning. In order to popularize the TLIs, the mechanism of LC must be figured
out, so a common-mode analytical model for TLIs is crucial.

Fig. 2.4 Parasitic capacitors Frame

between PV cells and the
frame Glass
PV cells

Substrate

Table 2.1 LC change

RMS value of LC change (mA) Break time (s)
amount and break time
30 0.3
60 0.15
150 0.04
2.2 Transformerless PV Grid-Connected Inverters 21

2.2.2 Elimination Rules of LC

Taking popular distributed PVPG system rated between 2 and 10 kW as an example,

a typical system structure is shown in Fig. 2.5, where iCM and iDM represent the
common-mode current and differential-mode current, respectively. From the perspec-
tive of spectral components, iCM includes a fundamental component at the grid
frequency, such as 50 or 60 Hz; a medium-frequency component band around the
switching frequency, whose scope is from 10–100 kHz roughly; and a high-frequency
component band from 150 kHz to 30 MHz.
Generally speaking, there are different measures for different LC frequency bands.
The fundamental frequency of common-mode current can be restricted and lower than
limitations of standards without any special design and hardware improvements in
distributed PVPG systems due to the large impedance in the common-mode loop and
the low grid voltage amplitude. High-frequency common-mode current components
belong to electromagnetic interference (EMI) noise, so the EMI filter is still the
main measure to suppress them. Medium-frequency common-mode current is the
most concerning component, and it may be much higher than the limitations of
standards when the switching modulation strategies are not suitable. This section
mainly discusses the inducing mechanism and suppression rules of the medium-
frequency common-mode current.
1. Common-mode equivalent models of TLIs

A generic TLI model is illustrated in Fig. 2.6, where C dc indicates that the TLI belongs
to voltage source inverter type. In Fig. 2.6, the generic TLI is composed of some basic
cells (BCs). In detail, BC may represent one or multiple power device combinations
with semiconductor switches and diodes while setting BC = 3; or BC = 2 when only
capacitors are covered in a BC; or BC = 1 while it is shorted; or BC = 0 when it is an
open circuit state. In addition, P and N are input terminals of DC source, respectively.
C pv1 and C pv2 are PV parasitic capacitors against ground; they depend on the material
and area of PV panels, soil properties, air humidity, and installation styles [20]. Points
1 and 2 are output terminals of differential-mode voltage; C 1 and C 2 are parasitic
capacitors of output terminals, respectively. L 1 and L 2 are two filter inductors; Y

Grid- ug
EMI
connected
filter
inverter

Fig. 2.5 Schematic diagram of a PVPG system without transformer

22 2 Transformerless Photovoltaic Grid-Connected Inverters …

P
BC1 BC7
BC3 BC6
ZLine1
2 1 L1
PV Cdc ug
BC4 BC9 EMI
N
BC2 BC5 BC8 ZLine2
L2

Cpv1 Cpv2 C2 C1 CY2 CY1 ZG

Fig. 2.6 Genetic TLI model with parasitic capacitors

capacitors C Y1 and C Y2 are part of EMI filter. Z Line1 and Z Line2 are impedance between
point of common coupling (PCC) and the grid; Z G represents the impedance between
grounding point of TLI and neutral line of the grid [21]; and ug is the AC grid voltage.
Taking terminal N as the reference, the common-mode voltage (CMV) vCM and
differential-mode voltage (DMV) vDM are defined as

u 1N + u 2N
u CM = (2.1)
2

u DM = u 1N − u 2N (2.2)

It can be seen that vCM and vDM are related to v1N and v2N . By combining (2.1)
and (2.2), v1N and v2N can be expressed as follows:
u DM
u 1N = u CM + (2.3)
2
u DM
u 2N = u CM − (2.4)
2
In order to obtain the CMV model at switching frequency, BCs of Fig. 2.6 can
be substituted with (2.3) and (2.4). Therefore, the DMV branches and elements can
be removed based on superposition principle; as a result, only the CMV branches
and elements are retained. Meanwhile, the grid voltage source can be shorted for
switching frequency CMV equivalent circuit. As an intermediate result, the first
CMV equivalent circuit is gained, as shown in Fig. 2.7, where L CM represents the
common-mode inductance of EMI filter.
Furthermore, Fig. 2.7 can be torn down to part A and part B, as shown in Fig. 2.8.
Then, two DMV branches can be simplified based on Thevenin’s theorem. It is worth
noting that the Delta–Wye transform needs to be used twice for simplifying branch
A, which is illustrated in Fig. 2.9. Finally, the simplified CMV equivalent circuit is
obtained, as shown in Fig. 2.10, where uA and uB represent the equivalent voltage
2.2 Transformerless PV Grid-Connected Inverters 23

L1 LCM ZLine1
uDM 1
2
2
uCM uDM L2 ZLine2
2 CY1 CY2
2Cpv C1 C2
ZG

Fig. 2.7 CMV equivalent model 1 for TLI system

A
B
L1 uDM
uDM CY1 2
C1
2
ZLine1 ZG LCM

uDM ZLine2 uDM

C2
uCM 2 2
CY2
L2
2Cpv

Fig. 2.8 CMV equivalent model 2 for TLI system

CY1
CY1
ZLine1 2Z
G
ZLine1 ZG Z1 Z3

ZLine2 2ZG Z2
ZLine2
CY2
CY2

Fig. 2.9 Delta–Wye transform for branch A

sources of branches A and B, respectively.

The impedances Z 1 , Z 2 , and Z 3 in Fig. 2.9 are expressed as follows:
24 2 Transformerless Photovoltaic Grid-Connected Inverters …

Fig. 2.10 CMV equivalent

model 3 for TLI system uA ZA LCM ZB uB
Z3
uCM

2Cpv

Z Line2 Z CY2
Z2 =
Z Line2 + 2Z G + Z CY2

2Z Linea Z G Z CY2 + 2Z Line2 Z G Z CY2 (Z Line1 + 2Z G + Z CY1 ) (Z Line2 + 2Z G Z CY2 )
+
(Z Line1 + Z CY1 )(Z Line2 + 2Z G + Z CY2 )(Z Line2 + Z CY2 )(Z Line1 + 2Z G + Z CY1 )
(2.5)
Z Line1 Z CY1
Z1 =
Z Line1 + 2Z G + Z CY1

2Z Line2 Z G Z CY1 + 2Z Line1 Z G Z CY1 (Z Line2 + 2Z G + Z CY2 ) (Z Line1 + 2Z G Z CY1 )
+
(Z Line1 + Z CY1 )(Z Line2 + 2Z G + Z CY2 )(Z Line2 + Z CY2 )(Z Line1 + 2Z G + Z CY1 )
(2.6)
2Z CY1 Z CY2 Z G
Z3 =
(Z Line1 + Z CY1 )(Z Line2 + 2Z G + Z CY2 ) + (Z Line2 + Z CY2 )(Z Line1 + 2Z G + Z CY1 )
(2.7)

In Fig. 2.10, the equivalent voltage sources and series impedances of branches A
and B are expressed as follows:

u DM (Z L2 + Z 2 ) − (Z L1 + Z 1 )
uA = (2.8)
2 Z L1 + Z L2 + Z 1 + Z 2
(Z L1 + Z 1 )(Z L2 + Z 2 )
ZA = (2.9)
Z L1 + Z L2 + Z 1 + Z 2
u DM Z C2 − Z C1
uB = (2.10)
2 Z C1 + Z C2
Z C1 Z C2
ZB = (2.11)
Z C1 + Z C2

2. Eliminating rules of switching frequency LC

The simplest CMV analysis model can be derived by using Thevenin’s theorem based
on Fig. 2.10, and the result is shown in Fig. 2.11, where uCM_tot and Z represent the
total equivalent CMV source and impedance of whole CMV path, respectively.

u A Z B + u B (Z A + Z 3 + Z LCM )
u CM−DM = (2.12)
Z A + Z 3 + Z LCM + Z B
2.2 Transformerless PV Grid-Connected Inverters 25

Fig. 2.11 The simplest

CMV equivalent model for uCM_tot
TLI system
Z
2CPV

Z B (Z A + Z 3 + Z LCM )
Z= (2.13)
Z A + Z 3 + Z LCM + Z B
u DM L 2 − L 1
u CM_ tot = u CM + u CM−DM = u CM + · (2.14)
2 L2 + L1

An important conclusion can be drawn from Fig. 2.11 that uCM_tot must be main-
tained constant in order to eliminate switching frequency LC in the CMV loop.
Furthermore, the generic LC elimination rules can be summarized from three kinds
of TLI topologies, respectively.
Rule 1 if BC5 = 1, BC6 = 0, BC1 = BC2 = BC3 = BC4 = 3, BC7 = BC8 = BC9 =
3 and L 1 = L 2 = 0, Fig. 2.6 can be redrawn as Fig. 2.12, which is a generic full-bridge
TLI topology. Since L 1 = L 2 , the second term of (2.14) equals zero, so uCM_tot can be
constant as long as uCM maintains constant in (2.1). Therefore, switching frequency
LC components can be eliminated if full-bridge TLIs can maintain CMV constant.
Rule 2 if BC1 = BC2 = BC5 = 1, BC7 = BC8 = BC9 = 3, BC3 = BC4 = 2, L 1 =
0 and L 2 = 0, Fig. 2.6 can be redrawn as Fig. 2.13, which is a generic half-bridge TLI
topology. Substituting L 2 = 0, (2.1), and (2.2) into (2.14), we can obtain that uCM_tot is

Fig. 2.12 Full-bridge TLI P BC1 BC7

structure
BC3
L1
2 1
PV Cdc ug
BC4
BC9
N BC2 BC8 L2

Fig. 2.13 Half-bridge TLI P BC7

structure
Cdc1
L1
2 1
PV ug
Cdc2 BC9
N BC8
26 2 Transformerless Photovoltaic Grid-Connected Inverters …

Fig. 2.14 Common-ground P BC1 BC7

TLI structure
BC3
L1
2 1
PV Cdc ug
N BC5 BC8

equal to u2N . Since u2N equals half of the DC voltage, thanks to the voltage-dividing
capacitors, half-bridge TLIs can naturally maintain total CMV uCM_tot constant.
Rule 3 if BC9 = 0, BC1 = BC3 = BC5 = BC7 = BC8 = 3, BC2 = BC4 =
BC6 = 1, L 1 = 0 and L 2 = 0, Fig. 2.6 can be redrawn as Fig. 2.14, which is a
generic common-ground TLI topology. Especially, the neutral line of AC grid is
directly connected to DC input terminal N, so u2N equals zero. Then, the expression
uDM = 2uCM can be obtained by combining (2.1) and (2.2). Therefore, the value of
the total equivalent CMV uCM_tot can be obtained according to (2.14) since L 2 = 0,
and naturally maintains zero.
Besides, grid voltage may cause line-frequency CMV across parasitic capacitors.
The CMV waveforms of full-bridge TLIs, half-bridge TLIs, and common-ground
TLIs are illustrated in Fig. 2.15, where uP and uN represent the voltages across C pv2
and C pv1 , respectively [25].
It can be seen that full-bridge TLIs have line-frequency CMV components, which
can induce line-frequency LC in the CMV loop. Fortunately, the impedance of para-
sitic capacitors is high for line-frequency CMV. Meanwhile, TLIs are commonly
installed in low-voltage distributed PVPG systems, so the grid voltage amplitude
is limited. Therefore, the line-frequency LC will be restricted and lower than the
limitations of standards without any special design and hardware.
It is also worth mentioning that the line-frequency CMV is constant in both of
half-bridge and common-ground TLIs. As a result, there is no line-frequency LC
according to the simplest CMV model in Fig. 2.11 due to the DC current blocking
property of capacitors.

Fig. 2.15 Line-frequency Full-bridge Half-bridge Common-ground

CMV waveforms on parasitic
uP
capacitors in three kinds of
uP uP
typical TLI topologies Upv
Upv/2

Upv/2 uN
uN uN
2.3 LC Suppression Techniques for Full-Bridge TLIs 27

2.3 LC Suppression Techniques for Full-Bridge TLIs

Full-bridge topologies feature high DC voltage utilization ratio, and they are the
preferred structures for residential roof PVPG systems. A classical full-bridge circuit
and product appearance are shown in Fig. 2.16. Full-bridge TLIs can work with
several kinds of modulation strategies, such as bipolar sinusoidal pulse width modu-
lation (SPWM), unipolar SPWM, and double-frequency unipolar SPWM. The CMV
characteristics of full-bridge structure will be discussed in this section based on the
derived CMV analysis model.

2.3.1 Combinations of Topology Structures and SPWM

Strategies

It can be deduced from Rule 1 and (2.1) that the sum of u1N and u2N must be constant
in order to maintain uCM at a constant value, which can be implemented by using
suitable modulation strategies. Table 2.2 lists the pulse amplitudes and frequencies

Fig. 2.16 Single-phase

full-bridge TLI
P
S1 S3
D1 D3
U pv
1 L1
C ug
C dc
PV
L2
2

S2 S4
N D2 D4

Table 2.2 Levels and frequencies of uCM and uDM under different SPWM styles in full-bridge
structures
SPWM style uCM ( u 1N +u
2
2N
) uDM (u 1N − u 2N )
Levels Frequency Levels Frequency
Bipolar SPWM U pv /2 0 U pv , −U pv f SW
Unipolar SPWM U pv /2, 0 f SW U pv , 0, −U pv f SW
Double-frequency unipolar U pv , U pv /2, 0 f SW U pv , 0, −U pv 2f SW
SPWM
Unipolar SPWM with AC bypass U pv /2, uncertain f SW U pv , 0, −U pv f SW
[26]
Unipolar SPWM with DC bypass U pv /2, uncertain f SW U pv , 0, −U pv f SW
[27, 28]
28 2 Transformerless Photovoltaic Grid-Connected Inverters …

of uCM and uDM of full-bridge TLIs working under several typical SPWM styles and
optimized topologies, where f SW represents the switching frequency of TLIs.
It can be seen from Table 2.2 that bipolar SPWM has excellent CMV characteristic,
but unipolar SPWM and double-frequency unipolar SPWM cannot be directly used
in full-bridge TLIs due to the poor CMV characteristics. A reverse conclusion can be
found from the perspective of DMV that unipolar SPWM strategies feature higher
conversion efficiency and grid-in current quality. Therefore, unipolar SPWM full-
bridge topologies with AC bypass and DC bypass have been proposed, under which
the PV array can be separated from grid in the freewheeling period by the new
freewheeling paths. However, the CMV of topologies proposed in the literatures
[26, 27] may still fluctuate at switching frequency scale for the non-negligible stray
capacitor of power devices. Based on Rule 1, the potential of the freewheeling path
must be clamped to half of the input voltage in the freewheeling period in order to
eliminate switching frequency LC.

2.3.2 Matching Circuit Parameters

A conclusion that maintaining the sum of uCM and uCM-DM at a constant value can
eliminate switching frequency LC is summarized in the aforementioned CMV model
and (2.14). The operation levels of full-bridge TLIs under unipolar and double-
frequency unipolar SPWM in one switching period are listed in Table 2.3, and the
expressions of a, b, c, d derived from (2.8), (2.10), and (2.12) are shown as follows:
⎧
⎪
⎪ (Z L2 + Z 2 ) − (Z L1 + Z 1 )
⎪
⎪ a=
⎪
⎪ Z L1 + Z L2 + Z 1 + Z 2
⎪
⎪
⎪
⎪ Z C2 − Z C1
⎪
⎨ b=
Z C1 + Z C2
(2.15)
⎪
⎪ ZB
⎪
⎪ c=
⎪
⎪ Z A + Z 3 + Z LCM + Z B
⎪
⎪
⎪
⎪ Z A + Z 3 + Z LCM
⎪
⎩ d=
Z A + Z 3 + Z LCM + Z B

Table 2.3 Operation levels of full-bridge TLIs under unipolar SPWM

u1N u2N uDM uCM uCM-DM
U pv U pv 0 U pv 0 + U pv
U pv 0 U pv U pv /2 (1 + ac + bd)U pv /2
0 U pv −U pv U pv /2 (1 − ac − bd)U pv /2
0 0 0 0 0+0
2.3 LC Suppression Techniques for Full-Bridge TLIs 29

It can be concluded from Table 2.3 that it is impossible to eliminate switching

frequency LC for full-bridge TLIs under unipolar SPWM by matching component
parameters, such as L 1 , L 2 and/or C 1 , C 2 . The reason is that the sum of uCM and
uCM-DM in rows 1 and 4 is unequal.

2.4 LC Suppression Techniques for Half-Bridge TLIs

Half-bridge structure has also been extensively applied in TLIs, including two-level
and multi-level topologies. For instance, the neutral point clamped (NPC) three-
level inverters have already been commercialized in single-phase and three-phase
TLI systems, which were developed by Danfoss of Denmark, as shown in Fig. 2.17
[29]. The NPC structure has advantages in dealing with LC and DC current injection
(DCCI) issues of TLIs [30], and also has merits of excellent DMV characteristic and
low-voltage stresses of power devices.

2.4.1 Combinations of Topology Structures and SPWM

Strategies

The feasibility of Rule 1 in half-bridge structure is chiefly analyzed by a case study of

NPC topology. When L 1 = L 2 = 0, uCM-DM maintains zero according to expression
(2.14), and it is possible that switching frequency LC may be eliminated by choosing
proper SPWM style to hold uCM constant. The conventional three-level NPC inverter
shown in Fig. 2.17 can output positive and zero levels in the positive half cycle of grid
voltage while negative and zero levels in the negative half cycle. This modulation
strategy is called unipolar SPWM. However, if it outputs both positive and negative
levels in whole cycle of the grid voltage, this modulation strategy is named as bipolar

Fig. 2.17 Neutral point

clamped three-level inverter Cdc1 S1 D1
and product appearance

Upv D5
S2 D2
1 2
PV L1
S3 D3
D6
Cdc2 ug
S4 D4
N

L2=0
30 2 Transformerless Photovoltaic Grid-Connected Inverters …

Table 2.4 Levels and frequencies of uCM and uDM under different SPWM styles with NPC
structures
SPWM style uCM ( u 1N +u
2
2N
) uDM (u 1N − u 2N )
Levels Frequency Levels Frequency
Unipolar SPWM 3U pv /4, U pv /2, U pv /4 f SW U pv /2, 0, −U pv /2 f SW
Bipolar SPWM 3U pv /4, U pv /4 f SW U pv /2, −U pv /2 f SW

SPWM. The levels and frequencies of uCM and uDM of NPC inverter under the
aforementioned two SPWM strategies are listed in Table 2.4.
It can be seen from Table 2.4 that the level of uCM changes at switching frequency
scale whether unipolar or bipolar SPWM is applied. The reason is that the potential of
point 2, that is, the midpoint of capacitor leg, is constant while the potential of output
point 1 varies in an SPWM style; as a consequence, the sum of u1N and u2N cannot
maintain constant. Therefore, Rule 1 is infeasible for half-bridge inverter structures.

2.4.2 Matching Circuit Parameters

According to Rule 2, properly matching component parameters of NPC topologies

may be an effective way to suppress LC, and will be discussed in detail in this
section. Although operation levels under two conventional SPWM styles are given
in Table 2.4, only unipolar SPWM is acceptable for three-level NPC grid-connected
inverters because bipolar SPWM leads to larger current ripple in the filter inductor
and lower conversion efficiency.
The operation levels of three-level NPC grid-connected inverter proposed in [29]
are listed in Table 2.5. It can be seen that the expression uCM + uCM-DM = U pv /2 is
true under the assumption that parasitic capacitors C 1 , C 2 and impedances Z Line1 ,
Z Line2 , Z G are zero. However, capacitors C 1 and C 2 are commonly different; usually
C 1 > C 2 in NPC structure due to different formation mechanisms. Therefore, uB is
not equal zero and turns out to be a positive value, which brings a negative impact
on the expectation that uCM-DM = −uCM . Moreover, the prerequisite of Z A + Z 3 +
Z LCM < <Z LB is no longer completely reliable as switching frequency increases even

Table 2.5 Operation levels of three-level NPC inverter with C 1 = C 2 = 0, L 1 = L, and L 2 = 0

u1N u2N uDM uCM uCM-DM uCM + uCM-DM
U pv /2 U pv U pv /2 3U pv /4 −U pv /4 U pv /2
U pv /2 U pv /2 0 U pv /2 0 U pv /2
U pv /2 0 −U pv /2 U pv /4 U pv /4 U pv /2
uCM-DM = −uDM/2 can also be derived by substituting Z CY1 = Z CY2 = ∞, Z Line1 = Z Line2 = 0,
Z L1 = Z L , Z L2 = 0, Z C1 = Z C2 = ∞ into (2.8)–(2.12)
2.4 LC Suppression Techniques for Half-Bridge TLIs 31

Table 2.6 Possible schemes for LC suppression in NPC topologies

Methods Theoretic expression Prerequisite Feasibility
Full-offset solution uA = −uDM /2, uB = L 1 = L, L 2 = 0, C 1 < Fine
−uDM /2 <C 2
Filter branch offset uA = −uDM /2, uB = 0 L 1 = L, L 2 = 0, C 1 = Difficulty of matching
solution Z B /(Z A + Z 3 + Z LCM C 2 C1 = C2;
+ Z B) = 1 Z A + Z 3 + Z LCM < Performance is
<Z B affected by switching
frequency
Parasitic branch offset uA = 0, uB = −uDM /2 L 1 = L 2 = L/2 Need for huge C 2 ;
solution (Z A + Z 3 + Z LCM )/ C 1 < <C 2 Performance is
(Z A + Z 3 + Z LCM + Z A + Z 3 + Z LCM affected by branch A
Z B) = 1 ZB

though C 1 and C 2 are exactly the same, so the uCM-DM = −uCM approximately makes
sense according to (2.12).
According to the analysis in [29], the equivalent voltage source uA shown in
Fig. 2.10 can counteract the high-frequency pulse of uCM . However, the compensation
effect is not perfect because the structure of three-level NPC inverter is asymmetric,
that is, capacitor leg and switch leg have different parasitic capacitors against the earth
[30]. Several possible schemes derived from the CMV analytical model are listed in
Table 2.6. However, only the full-offset solution can be realistically achieved. “Filter
branch offset solution” falls inferior because of its difficulty in determining the value
of C 1 , and this eliminating solution is an approximate method.
Although matching C 2 = C 1 can be approximately realized by adding some
extra capacitors, for instance, at least 10 times greater than the parasitic capacitor,
in doing so, high-frequency current across C 1 will be rapidly increased due to the
high-frequency pulse of point 1, and the realizability of expression Z A + Z 3 + Z LCM
< <Z LB is weakened as well. “Parasitic branch offset solution” is also difficult to
achieve since a huge C 2 is required to satisfy the prerequisite Z A + Z 3 + Z LCM
Z LB .

2.4.3 LC Suppression Techniques for Common-Ground TLIs

The neutral line of AC grid is directly connected to DC input terminal N in common-

ground TLIs, and the best CMV characteristic is achieved according to Rule 3
[31–33].
32 2 Transformerless Photovoltaic Grid-Connected Inverters …

2.4.4 Combinations of Topology Structures and SPWM

Strategies

It can be seen from Fig. 2.14 that the sum of u1N and u2N changes at switching
frequency scale in the common-ground structure since u2N maintains zero while u1N
varies in an SPWM style, which then leads to an inconstant CMV. Therefore, the
elimination methods applicable in full-bridge structure such as constructing DC or
AC bypass do not work in common-ground structure.

2.4.5 Matching Circuit Parameters

According to the aforementioned Rule 3, the constant total equivalent CMV uCM_tot
for switching frequency LC elimination can be achieved when L 2 = 0 and u2N =
0. Based on this conclusion, the virtual DC bus inverter (VDCBI) [31] shown in
Fig. 2.18 can work under unipolar SPWM and has a three-level output voltage. The
voltage of the capacitor C dc2 is supported by DC link voltage and charged in the
freewheeling period of negative half cycle through S1 and S3 .
The operation levels of VDCBI are listed in Table 2.7. It can be seen that the sum
of uCM and uCM-DM remains zero in the whole cycle. Considering the practical circuit
structure, it is still necessary to apply the full-offset solution presented in Table 2.6
to achieve the best performance of LC suppression.

Fig. 2.18 Single-phase

virtual DC bus Upv S1
common-ground TLI D1
Cdc1
PV
S2 S4
D2 D4
Cdc2 A
2 (N) Lf1 Lf2
S3 S5
D3 D5 ug
Cf

Table 2.7 Operation levels of VDCBI with C 1 = C 2 = 0, L 1 = L and L 2 = 0

u1N u2N uDM uCM uCM-DM uCM + uCM-DM
U pv 0 U pv U pv /2 −U pv /2 0
0 0 0 0 0 0
−U pv 0 −U pv −U pv /2 U pv /2 0
2.5 Summary 33

2.5 Summary

A switching-frequency CMV equivalent model for TLI system has been developed
in this chapter, and the parasitic parameters are taken into full consideration during
the derivation. Moreover, a total equivalent CMV source is calculated and then three
rules of LC elimination are summarized from the model. Finally, the applications of
these rules in full-bridge, half-bridge, and common-ground topologies are discussed
in detail, respectively.

References

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Chapter 3
Full-Bridge Transformerless PV
Grid-Connected Inverters

Abstract The CMV analysis model and three rules of LC elimination are discussed
in Chap. 2. One of the conclusions is that Rule 1 can be used in full-bridge TLIs.
This chapter discusses the application of Rule 1 in full-bridge TLIs, including LC
elimination by only decoupling the PV arrays with the grid and clamping the potential
of the freewheeling path, respectively. In general, decoupling circuits may disconnect
the PV arrays with the grid at AC side or DC side, while the clamping circuits may be
unidirectional or bidirectional. The number of added switches in clamping circuits
includes one, two, or more.

Keywords Transformerless PV grid-connected inverter · Full-bridge ·

Common-mode voltage · Decoupling · Clamping

3.1 Conventional Full-Bridge TLI

Conventional four-switch full-bridge TLI is the most mature and popular topology
in industrial applications, and the circuit is shown in Fig. 3.1a. C dc is the DC side
filter capacitor, S1 –S4 are power switches, L 1 , L 2 , and C are AC side filter inductors
and capacitor, respectively. It features simple and symmetrical circuit structure, high
DC voltage utilization, abundant modulation strategies, and so on.
Figure 3.1b, c shows two common modulation strategies, named as bipolar SPWM
and unipolar SPWM, respectively. vm is the reference, vtri is the carrier, and u12 is
the output voltage.

3.1.1 Bipolar SPWM Modulation

When the bipolar SPWM full-bridge TLI works with unity power factor, that is, the
grid-in current and the grid voltage are in phase all the time, four operating modes
can be gained, as shown in Fig. 3.2. Mode 1 and mode 3 are energy delivery stages,

© The Editor(s) (if applicable) and The Author(s), under exclusive license 35
to Springer Nature Singapore Pte Ltd. 2021
H. Xiao and X. Wang, Transformerless Photovoltaic Grid-Connected Inverters,
CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-8525-8_3
36 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a)

(b) (c)

Fig. 3.1 Conventional full-bridge TLI and its modulation strategies, a conventional full-bridge
TLI, b bipolar SPWM, c unipolar SPWM

so energy is fed forward into the grid from DC side. Mode 2 and mode 4 are energy
return stages, and the energy is fed back into DC side from AC filter.
According to the definitions of DMV and CMV, uDM and uCM were expressed as
(2.1) and (2.2) in Chap. 2. For convenience of reading, they are duplicated here as
(3.1) and (3.2), respectively.

u DM = u 1N − u 2N (3.1)

u 1N + u 2N
u CM = (3.2)
2
Based on the aforementioned operating modes, the potential of points 1 and 2
against N as well as uDM and uCM is shown in Table 3.1. It can be seen that DMV is
a two-level voltage, and CMV is a constant value.
Figures 3.3 and 3.4 are the simulation waveforms of DMV and CMV in time
domain and frequency domain, respectively. It can be seen that CMV is a constant
value, and the root mean square (RMS) of DMV is zero at switching frequency, that
3.1 Conventional Full-Bridge TLI 37

(a) (b)
S1 S3 S1 S3
D1 D3 ig D1 D3 ig
Upv Upv
iL1 L1 iL1 L1
C ug C ug
Cdc Cdc
PV L2 PV L2

S2 S4 S2 S4
N D2 D4 N D2 D4

(c) (d)

S1 S3 S1 S3
D1 D3 ig D1 D3 ig
Upv Upv
iL1 L1 iL1 L1
C ug C ug
Cdc Cdc
PV L2 PV L2

S2 S4 S2 S4
N D2 D4 N D2 D4

Fig. 3.2 Equivalent circuits of operating modes under bipolar SPWM modulation, a mode 1,
b mode 2, c mode 3, d mode 4

Table 3.1 DMV and CMV of different working stages with bipolar SPWM
Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) 0 U pv −U pv U pv /2
(3) 0 U pv −U pv U pv /2
(4) U pv 0 U pv U pv /2

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:[200V/div]

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.3 DMV waveforms of bipolar SPWM modulation, a time domain, b frequency domain
38 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.4 CMV waveforms of bipolar SPWM modulation, a time domain, b frequency domain

is, the high-frequency LC will be zero. However, DMV is a two-level waveform at

switching frequency scale. The RMS of DMV is about 100 V at switching frequency,
and DMV characteristic is poor.
In short, CMV can maintain constant during the whole line-frequency period by
using bipolar SPWM modulation. As a result, it features the best LC performance.
However, poor DMV characteristic results in too many harmonic components in the
output voltage, and energy return stages lead to too much reactive power swapping.
Obviously, bipolar SPWM modulation causes low conversion efficiency and big filter
volume.

3.1.2 Unipolar SPWM Modulation

It also has four operating modes when full-bridge TLI works with unity power factor
adopting unipolar SPWM, as shown in Fig. 3.5. Mode 1 and mode 3 are energy
delivery stages, and the energy is fed forward into the grid from DC side. Mode 2
and mode 4 are freewheeling stages, and the energy is also released into the grid
from AC filter.
Based on these modes, the potential of points 1 and 2 against N as well as uDM
and uCM is shown in Table 3.2. It can be seen that DMV is a three-level voltage, but
CMV contains switching frequency components.
Figures 3.6 and 3.7 are the simulation waveforms of DMV and CMV in time
domain and frequency domain, respectively. It is worth noting that the RMS of DMV
is about 75 V at switching frequency, which is reduced compared with Fig. 3.3b, so
the DMV characteristic is getting better. However, the RMS of CMV is about 50 V
at switching frequency, which is significantly enlarged compared to Fig. 3.4. Thus,
the CMV performance of unipolar SPWM modulation is not acceptable.
In summary, for bipolar SPWM modulation, the CMV performance is the best but
the DMV performance is worse. On the contrary, the DMV performance is better but
3.1 Conventional Full-Bridge TLI 39

(a) (b)

S1 S3 S1 S3
D1 D3 ig D1 D3 ig
Upv Upv
iL1 L1 iL1 L1
C ug C ug
Cdc Cdc
PV L2 PV L2

S2 S4 S2 S4
N D2 D4 N D2 D4
(c) (d)

S1 S3 S1 S3
D1 D3 ig D1 D3 ig
Upv Upv
iL1 L1 iL1 L1
C ug C ug
Cdc Cdc
PV L2 PV L2

S2 S4 S2 S4
N D2 D4 N D2 D4

Fig. 3.5 Equivalent circuits of operating modes under unipolar SPWM modulation, a mode 1,
b mode 2, c mode 3, d mode 4

Table 3.2 DMV and CMV of different working stages with unipolar SPWM
Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv U pv 0 U pv
(3) 0 U pv −U pv U pv /2
(4) 0 0 0 0

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.6 DMV waveforms of unipolar SPWM modulation, a time domain, b frequency domain
40 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[20V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:
[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.7 CMV waveforms of unipolar SPWM modulation, a time domain, b frequency domain

CMV is unacceptable when unipolar SPWM modulation is adopted in conventional

four-switch full-bridge TLI. In order to figure out this contradiction, a lot of improved
full-bridge TLIs are proposed by combining the advantages of the two modulation
strategies, including decoupling type and clamping type full-bridge TLIs.

3.2 Full-Bridge TLIs with Decoupling Branches

High efficiency and reliable inverter conception (HERIC) was first proposed by
Fraunhofer Institute of Solar Energy Systems (Fraunhofer ISE), which was presented
to use in distributed PVPG systems [1]. Later on, it was patented by Sunways Inc.
and commercially used in single-phase PVPG, including NT 3000, NT 4200, and
NT 5000, as well as three-phase PVPG, including PT 30k, PT 33k, and so on. For
detailed information refer to www.sunways.de.

3.2.1 HERIC Inverter

1. Operating principle

The main circuit of HERIC is illustrated in Fig. 3.8a, and it can be seen that a
decoupling branch made of S5 /D5 and S6 /D6 is added into conventional four-switch
full-bridge TLI at AC side. In this circuit, S5 /D5 and S6 /D6 are connected in anti-
series between points 1 and 2, also called as “AC decoupling type”. The modulation
strategy for six switches is shown in Fig. 3.8b. It is worth noting that S1 –S4 work
with high frequency, and the added S5 and S6 work with line-frequency. As a result, a
three-level output voltage is obtained, and high conversion efficiency is maintained.
3.2 Full-Bridge TLIs with Decoupling Branches 41

(a) (b)
vM vtri
S1 S3 ωt
D1 D3
Upv 1 L1
S5 D5 C ug S1, S4 ωt
Cdc S2, S3 ωt
PV S6
D6 S5 ωt
2 L2
S6 ωt
S2 S4 u12 ωt
N D2 D4

Fig. 3.8 High efficiency and reliable inverter conception, a main circuit, b modulation strategy

When HERIC works with unity power factor, there are four operating modes
based on the directions of grid-in current and grid voltage, as shown in Fig. 3.9.
Among them, Fig. 3.9a, b belongs to the positive half grid cycle, while Fig. 3.9c, d
belongs to the negative half grid cycle.
Mode 1: Refer to Fig. 3.9a; at this stage, the energy is delivering from the PV
side into the grid through S1 , S4 , and AC filter. The operation mode is the same as
conventional four-switch full-bridge TLI.
Mode 2: Refer to Fig. 3.9b; S1 –S4 are all off while S5 is on and S6 is off according
to Fig. 3.8b. At this stage, the freewheeling current flows through D6 , S5 , and the filter,
and keeps feeding the grid. The different thing from Fig. 3.5b is that the freewheeling
path is disconnected from PV side; as a result, the LC loop is cut off.
Mode 3: Refer to Fig. 3.9c; at this stage, the energy is delivering from the PV side
to the grid through S2 , S3 , and the filter. It is a symmetric mode with Fig. 3.9a.
Mode 4: Refer to Fig. 3.9d; S1 –S4 are all off while S6 is on and S5 is off according
to Fig. 3.8b. At this stage, the freewheeling current flows through D5 , S6 , and the
filter, and keeps feeding the grid. The same function of disconnecting from PV side
as Mode 2 does.
Based on the modes analyzed, the potential of points 1 and 2 against N as well
as uDM and uCM is shown in Table 3.3. It can be seen that DMV maintains unipolar
SPWM performance, and CMV has two uncertain states because the freewheeling
path is just disconnected from PV side in Mode 2 and Mode 4. In other words, the
CMV is not a perfect one in HERIC.
In summary, HERIC disconnects PV side and the grid side during freewheeling
periods by introducing a decoupling branch. LC will be significantly decreased due
to CMV source is weakened. According to the press reports, HERIC topology has
been commercialized by Sunways Inc., its European efficiency was 95%, and the
peak efficiency was up to 95.6%.
42 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
S1 S3 S1 S3

D1 D3 iL1 ig D1 D3 iL1 ig
Upv L1 Upv L1
S5 D5 C ug S5 D5 C ug
Cdc Cdc
PV D6 S6 PV D6 S6
L2 L2
S2 S4 S2 S4

N D2 D4 N D2 D4

(c) (d)
S1 S3 S1 S3

D1 D3 iL1 ig D1 D3 iL1 ig
Upv L1 Upv L1
S5 D5 C ug S5 D5 C ug
Cdc Cdc
PV D6 S6 PV D6 S6
L2 L2
S2 S4 S2 S4

N D2 D4 N D2 D4

Fig. 3.9 Equivalent circuits of operating modes of HERIC, a mode 1, b mode 2, c mode 3, d mode
4

Table 3.3 DMV and CMV of different operating modes for HERIC
Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 Uncertain
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 Uncertain

2. Simulation results

A simulation model is built by using Matlab/Simulink to verify the operating principle

and the performance analysis aforementioned, and the key parameters of HERIC
circuit are shown in Table 3.4.
The simulation waveforms of grid voltage ug , grid-in current reference iref , and
grid-in current ig are shown in Fig. 3.10. The simulation waveforms of DMV uDM in
time domain and frequency domain are shown in Fig. 3.11a, b, respectively. It can
3.2 Full-Bridge TLIs with Decoupling Branches 43

Table 3.4 Key parameters of HERIC circuit

Parameters Value Parameters Value
Input voltage U pv /V 360 Switching frequency f s /kHz 18
Grid voltage ug /V 220 Filter inductors L 1 , L 2 /mH 0.86
Grid frequency/Hz 50 Filter capacitor C/µF 4.7
Rated power P/W 3000 PV parasitic capacitor C pv /nF 300

ug:[100V/div]

ig:[10A/div] iref:[10A/div]

t[10ms/div]

Fig. 3.10 Simulation waveforms of ug , iref , and ig of HERIC

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.11 DMV waveforms of HERIC, a time domain, b frequency domain

be seen that the RMS of DMV is about 75 V at switching frequency, which is equal
to Fig. 3.6b with typical unipolar SPWM performance.
The simulation waveforms of CMV uCM in time domain and frequency domain
are shown in Fig. 3.12a, b, respectively. It can be seen that the RMS of CMV is about
2.5 V at switching frequency, which is quite close to Fig. 3.4b with typical bipolar
SPWM performance.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.13a, b, respectively. It can be seen that the RMS of LC is about
44 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]
uCM:
[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.12 CMV waveforms of HERIC, a time domain, b frequency domain

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[200mA/div]
0
0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.13 LC waveforms of HERIC, a time domain, b frequency domain

13 mA at switching frequency, which meets the limitation of DIN VDE 0126-1-1

[2] and NB/T 32004-2013 [3] of 30 mA. It is worth noting that the line-frequency
component of LC is obvious, which is induced by the fundamental component of the
grid voltage according to the analysis of Fig. 2.15 in Chap. 2.
3. Experimental results

In order to verify the theoretical analysis and simulation waveforms, a prototype of

HERIC having the same parameters with Table 3.4 is built in laboratory, as shown
in Fig. 3.14.
The experimental waveforms of DMV uDM in time domain and frequency domain
are shown in Fig. 3.15a, b, respectively. It can be seen that the RMS of DMV is about
70 V at switching frequency, which is in accordance with the simulation result of
Fig. 3.11b.
The experimental waveforms of CMV uCM in time domain and frequency domain
are shown in Fig. 3.16a, b, respectively. It can be seen that there exist some CMV
3.2 Full-Bridge TLIs with Decoupling Branches 45

Fig. 3.14 Experimental platform of 3 kW HERIC prototype

(a) (b)

ig:[20A/div] A[50V/div]

ug:[250V/div]
uDM:
[250V/div]

t[4ms/div]

Fig. 3.15 DMV waveforms of HERIC, a time domain, b frequency domain

(a) (b)

ig:[20A/div] A[2V/div]

ug:[250V/div]

uCM:[100V/div]

t[4ms/div]

Fig. 3.16 CMV waveforms of HERIC, a time domain, b frequency domain

46 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

ig:[20A/div] A[10mA/div]

ug:[250V/div]
iCM:[200mA/div]

t[4ms/div]

Fig. 3.17 LC waveforms of HERIC, a time domain, b frequency domain

components at switching frequency, and this is in accordance with Fig. 3.12b; the
reason is from the uncertain modes during the freewheeling periods as Table 3.3
lists. Furthermore, the LC iCM in time domain and frequency domain are shown in
Fig. 3.17a, b, respectively. It can be seen that the LC is about 22 mA at switching
frequency, and it is a little higher than the simulation result but still meets the standard
limitation.
With the popularization of distributed PVPG systems in Germany, patented
HERIC has been commercialized by Sunways Inc., and made a great success in
PVPG applications. The great market demand also attracted the attention of another
PV inverter manufacturer, named as SMA. In order to hold the key techniques of
TLIs, a patented topology named as H5 has been invented [4].

3.2.2 H5 Inverter

1. Operating principle

The main circuit of H5 is shown in Fig. 3.18a. A new power switch S5 is inserted at the
positive DC bus, which is called DC decoupling type TLI [4]. The modulation strategy
is shown in Fig. 3.18b. Apparently, S1 –S4 work in unipolar modulation strategy and
added S5 works in high frequency. The three-level output voltage remains.
When H5 works in unity power factor, there are four operating modes according
to the grid voltage and energy transmission direction, as shown in Fig. 3.19. Among
them, Fig. 3.19a, b belongs to the positive grid cycle, while Fig. 3.19c, d belongs to
the negative grid cycle.
Mode 1: Refer to Fig. 3.19a; in this stage, energy is delivering from PV side into
the grid through S1 , S4 , S5 , and the filter. The operating principle is the same as it is
in conventional four-switch full-bridge TLI.
3.2 Full-Bridge TLIs with Decoupling Branches 47

(a) (b) vM vtri

S5 ωt
D5
S1 S3
D1 D3 S1 ωt
Upv 1
L1 S2 ωt
C ug S3
Cdc ωt
PV L2 S4 ωt
2
S5 ωt
S2 S4 u12 ωt
N D2 D4

Fig. 3.18 H5 inverter, a main circuit, b modulation strategy

(a) (b)
S5 S5
D1 D3 D1 D3
D5 D5
S1 S3 ig S1 S3 ig
Upv Upv
iL1 L1 iL1 L1
Cdc C ug Cdc C ug
PV L2 PV L2
D2 D4 D2 D4
N S2 S4 N S2 S4
(c) (d)
S5 S5
D1 D3 D1 D3
D5 D5
S1 S3 ig S1 S3 ig
Upv Upv
iL1 L1 iL1 L1
Cdc C ug Cdc C ug
PV L2 PV L2
D2 D4 D2 D4
N S2 S4 N S2 S4

Fig. 3.19 Equivalent circuits of operating modes of H5, a mode 1, b mode 2, c mode 3, d mode 4

Mode 2: Refer to Fig. 3.19b; S2 –S5 are all closed while S1 is conducting from
Fig. 3.18b. At this stage, the freewheeling current flows through D3 , S1 , and the
filter, and keeps feeding grid. The freewheeling circuit is disconnected from PV
side completely and the LC loop is cut off compared to conventional four-switch
full-bridge TLI.
48 3 Full-Bridge Transformerless PV Grid-Connected Inverters

Table 3.5 DMV and CMV levels of different operating modes in H5

Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 Uncertain
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 Uncertain

Mode 3: Refer to Fig. 3.19c; in this stage, the energy is delivering from the PV side
to the grid through S2 , S3 , S5 , and the filter. It is a symmetric mode with Fig. 3.19a.
Mode 4: Refer to Fig. 3.19d; only S3 is conducting from Fig. 3.18b. At this stage,
the freewheeling current flows through D1 , S3 , and the filter and still feeding the grid.
The same purpose is realized as the Mode 2.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.5. From this table, it is clear that DMV maintains unipolar
SPWM performance, and CMV has two uncertain states because the freewheeling
path is just disconnected from PV side in Mode 2 and Mode 4. The CMV is not a
perfect one in H5.
In conclusion, a decoupling branch is introduced in the DC side to disconnect the
PV with grid during freewheeling stages in H5. LC will decrease due to CMV source
is weakened. The current flows through three power switches in power transmission
stages, and two power switches conduct current in freewheeling stages. The power
loss improved compared to HERIC. As the press reported, H5 topology has been
commercialized in SunnyBoy 4000/5000 series by SMA Inc. Its European efficiency
is 97.7% and the peak efficiency was up to 98%.
2. Simulation results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of H5 are shown in Table 3.4.
The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.20. The simulation waveforms of DMV uDM in time domain
and frequency domain are shown in Fig. 3.21a, b, respectively. It can be seen that
the RMS of DMV is about 75 V at switching frequency, which is equal to Fig. 3.6b
with typical unipolar SPWM performance.
The simulation waveforms of CMV uCM in time domain and frequency domain
are shown in Fig. 3.22a, b, respectively. It can be seen that the RMS of CMV is about
2 V at switching frequency, which is quite close to Fig. 3.4b with typical bipolar
SPWM performance.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.23a, b, respectively. It can be seen that the RMS of LC is about
13 mA at switching frequency, which meets the limitation of DIN VDE 0126-1-1
[2] and NB/T 32004-2013 [3] of 30 mA. It is worth noting that the line-frequency
component of LC is obvious, which is induced by the fundamental component of the
grid voltage according to the analysis of Fig. 2.15 in Chap. 2.
3.2 Full-Bridge TLIs with Decoupling Branches 49

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.20 Simulation waveforms of ug , iref , and ig of H5

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.21 DMV waveforms of H5, a time domain, b frequency domain

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]
uCM:
[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.22 CMV waveforms of H5, a time domain, b frequency domain

50 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[200mA/div]
0
0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.23 LC waveforms of H5, a time domain, b frequency domain

3. Experimental results
In order to verify the theoretical analysis and simulation waveforms, a prototype of
H5 is built using parameters in Table 3.6.
The experimental waveforms of ug , ig , uCM , iCM are shown in Fig. 3.24a, b,
respectively. uCM is still changed with switching frequency and the LC is about
2.8 mA at switching frequency and can meet the national standards.
Researchers have invented various improved full-bridge TLIs with the rapid devel-
opment of PVPG systems in the world, especially in North America and Asia.
Following the decoupling ideas, many AC coupling H6 as well as DC decoupling
H6 topologies are proposed.

Table 3.6 Key parameters of H5 prototype

Parameters Value Parameters Value
Input voltage U pv /V 340–700 Filter inductors L 1 , L 2 /mH 4
Grid voltage ug /V 240 Filter capacitor C/µF 6.6
Grid frequency/Hz 50 Common-mode inductor 2 × 2 W-43615-TC
L CM
Rated power P/W 1000 Wire/mm Wire: 2 mm
Switching frequency 20 Turns Turns: 10 + 10
f s /kHz
DC side capacitors C dc1 , 470 µF/400 V Common-mode capacitor 2.2
C dc2 /µF C Y1 , C Y2 /nF
MOSFET S1 –S6 IXFN36N100 PV parasitic capacitor 0.1
C pv1 , C pv2 /µF
3.2 Full-Bridge TLIs with Decoupling Branches 51

(a) (b)
ug:[200V/div] ug:[200V/div]
ig:[6.7A/div]
ig:[6.7A/div]
u1N:[200V/div]

2uCM:[200V/div] iCM:[80mA/div]
2.80mA
u2N:[200V/div]

Fig. 3.24 Common mode performances, a CMV waveforms, b LC waveforms

3.2.3 H6-I Inverter

H6-I was proposed by future energy electronics center (FEEC) of America [5].
1. Operating principle

The main structure of H6-I is shown in Fig. 3.25a, where two new switches S5 and
S6 are added to the inverter legs, respectively. This inverter is also classified in AC
decoupling type [6]. The modulation strategy is shown in Fig. 3.25b. Apparently,
S1 –S4 work in high frequency and S5 –S6 work in line-frequency. The output voltage
is also a three-level voltage and maintains high conversion efficiency.
There are four operating modes when H6-I works in unity power factor based
on the directions of grid voltage and grid-in current, as shown in Fig. 3.26. Among
them, Fig. 3.26a, b belongs to the positive grid cycle, while Fig. 3.26c, d belongs to
the negative grid cycle.

(a) (b)
vM vtri
S1 D1 S3 D3
ωt
Upv
1 L1 C ug
D7 D8 2
Cdc S1, S4 ωt
L2
PV S2, S3 ωt
S5 D5 S6 D6 S5 ωt
S6 ωt
S2 D2 S4 D4 u12 ωt
N

Fig. 3.25 H6-I inverter, a main circuit, b modulation strategy

52 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
ig ig
S1 D1 S3 D3 S1 D1 S3 D3

Upv iL1 L1 C ug Upv iL1 L1 C ug

D7 D8 D7 D8
Cdc Cdc
L2 L2
PV PV
S5 D5 S6 D6 S5 D5 S6 D6

S2 D2 S4 D4 S2 D2 S4 D4
N N

(c) (d)
ig ig
S1 D1 S3 D3 S1 D1 S3 D3

Upv iL1 L1 C ug Upv iL1 L1 C ug

D7 D8 D7 D8
Cdc Cdc
L2 L2
PV PV
S5 D5 S6 D6 S5 D5 S6 D6

S2 D2 S4 D4 S2 D2 S4 D4
N N

Fig. 3.26 Equivalent circuits of operating modes of H6-I, a mode 1, b mode 2, c mode 3, d mode
4

Mode 1: Refer to Fig. 3.26a; in this stage, the energy is delivering from PV side
to the grid through S1 , S4 , S6 , and the filter. The operating principle is the same as it
is in conventional four-switch full-bridge TLI.
Mode 2: Refer to Fig. 3.26b; only S6 is conducting from Fig. 3.25b. At this stage,
the freewheeling current flows through S6 , D7 , and the filter while keeping feeding
grid. Freewheeling circuit is disconnected with PV side completely and the LC loop
is cut off compared to conventional full-bridge TLI.
Mode 3: Refer to Fig. 3.26c; at this stage, the energy is delivering from the PV
side to the grid through S2 , S3 , S5 , and the filter.
Mode 4: Refer to Fig. 3.26d; only S5 is conducting from Fig. 3.25b. In this stage,
the freewheeling current flows through S5 , D8 , and the filter. The same function is
realized with Mode 2.
Based on these modes, the potential of points 1 and 2 against N as well as uDM
and uCM is shown in Table 3.7. It can be seen that DMV maintains unipolar SPWM
performance, while CMV has two uncertain states because the freewheeling path is
just disconnected from PV side in Mode 2 and Mode 4. In other words, the CMV is
not a perfect one in H6-I.
3.2 Full-Bridge TLIs with Decoupling Branches 53

Table 3.7 DMV and CMV of different operating modes in H6-I

Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 Uncertain
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 Uncertain

In conclusion, two power switches are introduced in H6-I compared to conven-

tional four-switch full-bridge TLI. The PV side and grid are disconnected during
freewheeling stages in H6-I. LC will decrease due to the weak CMV source. The
current flows through three power switches in power transmission stages, while
two power switches in freewheeling stages. The power loss improved compared to
HERIC.
2. Simulation results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of H6-I are shown in Table 3.4.
The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.27. The simulation waveforms of DMV uDM in time domain
and frequency domain are shown in Fig. 3.28a, b, respectively. It can be seen that
DMV is a three-level voltage and the RMS of it is about 75 V at switching frequency.
The simulation waveforms of CMV uCM in time domain and frequency domain
are shown in Fig. 3.29a, b, respectively. It can be seen that the RMS of CMV is about
2 V at switching frequency.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.30a, b, respectively. It can be seen that the RMS of LC is about
12 mA at switching frequency, which meets the limitation of national standards.

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.27 Simulation waveforms of ug , iref , and ig of H6-I

54 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.28 DMV waveforms of H6-I, a time domain, b frequency domain

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.29 CMV waveforms of H6-I, a time domain, b frequency domain

(a) (b)

A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[200mA/div]
0

0
50Hz 18kHz 36kHz
t[5ms/div]

Fig. 3.30 LC waveforms of H6-I, a time domain, b frequency domain

3.2 Full-Bridge TLIs with Decoupling Branches 55

3.2.4 H6-II Inverter

1. Operating principle

H6-II was proposed in [7], and its main circuit is shown in Fig. 3.31a. The structure
of H6-II is similar to H6-I. It reduces two diodes compared to H6-I. This inverter
is also AC side decoupling circuit. The modulation strategy is shown in Fig. 3.31b.
The output voltage is a three-level voltage.
There are four operating modes based on the directions of grid voltage and grid-in
current when H6-II works in unity power factor, as shown in Fig. 3.32. Among them,
Fig. 3.32a, b belongs to the positive grid cycle, while Fig. 3.32c, d belongs to the
negative grid cycle.
Mode 1: Refer to Fig. 3.32a; in this stage, the energy transfers from the PV side
to the grid through S1 , S4 , S6 , and the filter.
Mode 2: Refer to Fig. 3.32b; only S6 is conducting from Fig. 3.31b. In this stage,
the freewheeling current flows through S6 , D5 , and the filter. The freewheeling circuit
is disconnected with PV side completely and the LC loop is broken compared to
conventional full-bridge TLI.
Mode 3: Refer to Fig. 3.32c; in this stage, the energy transfers from PV side to
the grid through S2 , S3 , S5 , and the filter.
Mode 4: Refer to Fig. 3.32d; only S5 is conducting from Fig. 3.31b. In this stage,
the freewheeling current flows through S5 , D6 , and the filter. The freewheeling circuit
is disconnected with DC side completely. It has the same function as Mode 2.
Based on these modes, the potential of points 1 and 2 against N as well as uDM
and uCM is shown in Table 3.8. It can be seen that DMV maintains unipolar SPWM
performance, while CMV has two uncertain states because the freewheeling path is
just disconnected from PV side in Mode 2 and Mode 4. In other words, the CMV is
not a perfect one in H6-II.
In conclusion, two power switches are introduced in H6-II compared to conven-
tional four-switch full-bridge TLI. The PV side and grid side are disconnected during
freewheeling stages in H6-II. LC will decrease due to the weak CMV source. The

(a) (b)
vM vtri
S1 D1 S3 D3 ωt

Upv
1 L1 C ug
Cdc 2 S1, S4 ωt
L2 S2, S3 ωt
PV
S5 D5 S6 D6 S5 ωt
S6 ωt
S2 D2 S4 D4 u12 ωt
N

Fig. 3.31 H6-II inverter, a main circuit, b modulation strategy

56 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
ig ig
S1 D1 S3 D3 S1 D1 S3 D3

Upv iL1 L1 C ug Upv iL1 L1 C ug

Cdc Cdc
L2 L2
PV PV
S5 D5 S6 D6 S5 D5 S6 D6

S2 D2 S4 D4 S2 D2 S4 D4
N N

(c) (d)
ig ig
S1 D1 S3 D3 S1 D1 S3 D3

Upv iL1 L1 C ug Upv iL1 L1 C ug

Cdc Cdc
L2 L2
PV PV
S5 D5 S6 D6 S5 D5 S6 D6

S2 D2 S4 D4 S2 D2 S4 D4
N N

Fig. 3.32 Equivalent circuits of operating modes of H6-II, a mode 1, b mode 2, c mode 3, d mode
4

Table 3.8 DMV and CMV of different operating modes in H6-II

Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 Uncertain
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 Uncertain

current flows through three power switches in power transmission stages, and two
power switches conduct in freewheeling stages. Its working principles are similar to
H6-I.
2. Simulations results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of H6-II are shown in Table 3.4.
The simulation waveforms of ug , iref , and ig are shown in Fig. 3.33. The simula-
tion waveforms of DMV uDM in time domain and frequency domain are shown in
Fig. 3.34a, b. uDM is a three-level voltage and the RMS of it is about 75 V at switching
3.2 Full-Bridge TLIs with Decoupling Branches 57

ug:[100V/div]

ig:[10A/div]
iref:[10A/div]
0

t[10ms/div]

Fig. 3.33 Simulation waveforms of ug , iref , and ig of H6-II

(a) (b)

A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.34 DMV waveforms of H6-II, a time domain, b frequency domain

frequency.
The simulation waveforms of CMV uCM in time domain and frequency domain
are shown in Fig. 3.35a, b, respectively. It can be seen that the RMS of CMV is about
2 V at switching frequency.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.36a, b. From Fig. 3.36, the LC is about 14 mA at switching frequency.
Its common-mode performance is similar to H6-I.

3.2.5 H6-III Inverter

1. Operating principle

H6-III was proposed in [8], and its main circuit is shown in Fig. 3.37a. Two power
switches S5 and S6 as well as two independent diodes D6 and D7 are introduced in
H6-III compared to conventional four-switch full-bridge TLI. S5 and S6 are inserted
58 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.35 CMV waveforms of H6-II, a time domain, b frequency domain

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[200mA/div]
0

0
50Hz 18kHz 36kHz
t[5ms/div]

Fig. 3.36 LC waveforms of H6-II, a time domain, b frequency domain

(a) D5 (b)
vM vtri
S3
S1 S5 D3 ωt
Upv D1 D6
1 L1
Cdc C ug S1, S6 ωt
D7
PV S2, S5 ωt
L2
2 S3 ωt
D2
S2 S4 D4 S4 ωt
S6
N u12 ωt
D6

Fig. 3.37 H6-III inverter, a main circuit, b modulation strategy

3.2 Full-Bridge TLIs with Decoupling Branches 59

into positive and negative DC buses, respectively. Although the structure is different
from H6 topologies mentioned above, H6-III is still AC side decoupling circuit [9–
11]. The modulation strategy is shown in Fig. 3.37b. The output voltage is also a
three-level voltage.
There are four operating modes based on the directions of grid voltage and grid-in
current when H6-III works in unity power factor, as shown in Fig. 3.38. Figure 3.38a,
b belongs to the positive grid cycle, while Fig. 3.38c, d belongs to the negative grid
cycle.
Mode 1: Refer to Fig. 3.38a; in this stage, the energy transfers from the PV side
to the grid side through S1 , S4 , S6 , and the filter.
Mode 2: Refer to Fig. 3.38b; only S4 is conducting from Fig. 3.37b. In this stage,
the freewheeling current flows through S4 , D7 , and the filter. The freewheeling circuit
is disconnected with PV side completely and the LC loop is broken.
Mode 3: Refer to Fig. 3.38c; in this stage, the energy transfers from the PV side
to the grid through S2 , S3 , S5 , and the filter.

(a) (b)
D5 D5
S3 S3
S1 S5 D3 S1 S5 D3
D1 D6 ig D1 D6 ig
Upv Upv
Cdc iL1 L1 Cdc iL1 L1
C ug C ug
D7 D7
PV PV
L2 L2
D2 D2
S2 S4 D4 S2 S4 D4
S6 S6
N N
D6 D6
(c) (d)
D5 D5
S3 S3
S1 S5 D3 S1 S5 D3
D1 D6 ig D1 D6 ig
Upv Upv
Cdc iL1 L1 Cdc iL1 L1
C ug C ug
D7 D7
PV PV
L2 L2
D2 D2
S2 S4 D4 S2 S4 D4
S6 S6
N N
D6 D6

Fig. 3.38 Equivalent circuits of operating modes of H6-III, a mode 1, b mode 2, c mode 3, d mode
4
60 3 Full-Bridge Transformerless PV Grid-Connected Inverters

Table 3.9 DMV and CMV of different operating modes in H6-III

Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 Uncertain
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 Uncertain

Mode 4: Refer to Fig. 3.38d; only S3 is conducting from Fig. 3.37b. In this stage,
the freewheeling current flows through S3 , D6 , and the filter. The LC loop is also
broken compared to conventional full-bridge TLI.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.9. From this table, it can be seen that the DMV maintains
unipolar SPWM performance, while the CMV has two uncertain states because the
freewheeling path is just disconnected from PV side in Mode 2 and Mode 4. In other
words, the CMV is not a perfect one in H6-III.
In conclusion, two power switches are inserted into the DC bus to disconnect the
PV side and grid side during freewheeling stages in H6-III. LC will decrease due
to the disconnected CMV loop and CMV source. The current flows through three
power switches in power transmission stages, and two power switches conduct in
freewheeling stages. Its working principles and power loss are similar to H6-I or
H6-II.
2. Simulations results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of H6-III are shown in Table 3.4.
The simulation waveforms of ug , iref , and ig are shown in Fig. 3.39. The simu-
lation waveforms of DMV uDM in time domain and frequency domain are shown

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.39 Simulation waveforms of ug , iref , and ig of H6-III

3.2 Full-Bridge TLIs with Decoupling Branches 61

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.40 DMV waveforms of H6-III, a time domain, b frequency domain

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]
uCM:[50V/div]

0 t[5ms/div] 0
0Hz 18kHz 36kHz

Fig. 3.41 CMV waveforms of H6-III, a time domain, b frequency domain

in Fig. 3.40a, b, respectively. DMV is a three-level voltage and the RMS of it is

about 75 V at switching frequency. The simulation waveforms of CMV uCM in time
domain and frequency domain are shown in Fig. 3.41a, b, respectively. It can be seen
that the RMS of CMV is about 2 V at switching frequency and still contains certain
high-frequency components. The simulation waveforms of LC iCM in time domain
and frequency domain are shown in Fig. 3.42a, b, respectively. From Fig. 3.42, the
LC is about 20 mA at switching frequency, which is similar to H6-II.
62 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[200mA/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.42 LC waveforms of H6-III, a time domain, b frequency domain

3.2.6 H6-IV Inverter

1. Operating principle

H6-IV was proposed in [12], and its main circuit is shown in Fig. 3.43a. Two power
switches S5 and S6 are introduced into positive and negative DC buses in H6-IV
compared to conventional full-bridge inverter. Different from H6-III, this inverter is
DC side decoupling type TLI. The modulation strategy is shown in Fig. 3.43b. S3 –S6
work in high frequency. The output voltage is a three-level voltage.
There are four operating modes based on the directions of grid voltage and grid-in
current when H6-IV works in unity power factor, as shown in Fig. 3.44. Figure 3.44a,
b belongs to the positive grid cycle, while Fig. 3.44c, d belongs to the negative grid
cycle.
Mode 1: Refer to Fig. 3.44a; in this stage, the energy transfers from the PV side
to the grid through S1 , S4 , S5 , S6 , and the filter.

(a) (b)
vM vtri
S5
ωt
D5 S1 S3
D1 D3 S1
Upv ωt
1
L1 S2 ωt
C ug
Cdc S3 ωt
PV L2
2 S4 ωt
S5 ωt
S2 S4 S6 ωt
D6 D2 D4
N
u12 ωt
S6

Fig. 3.43 H6-IV inverter, a main circuit, b modulation strategy

3.2 Full-Bridge TLIs with Decoupling Branches 63

(a) (b)
S5 S5
D1 D3 D1 D3
D5 D5
S1 S3 ig S1 S3 ig
Upv Upv
iL1 L1 iL1 L1
Cdc C ug Cdc C ug
PV L2 PV L2
S2 D2 D4 S2 D2 D4
N D6 S4 N D6 S4
S6 S6
(c) (d)
S5 S5
D1 D3 D1 D3
D5 D5
S1 S3 ig S1 S3 ig
Upv Upv
iL1 L1 iL1 L1
Cdc C ug Cdc C ug
PV L2 PV L2
S2 D2 D4 S2 D2 D4
N D6 S4 N D6 S4
S6 S6

Fig. 3.44 Equivalent circuits of operating modes of H6-IV, a mode 1, b mode 2, c mode 3, d mode
4

Mode 2: Refer to Fig. 3.44b; S1 , S3 , and S6 are conducting from Fig. 3.43b. In this
stage, the freewheeling current flows through S1 , D3 , and the filter. The freewheeling
circuit is disconnected with PV side completely and the LC loop is cut off.
Mode 3: Refer to Fig. 3.44c; in this stage, the energy transfers from the PV side
to the grid through S2 , S3 , S5 , S6 , and the filter.
Mode 4: Refer to Fig. 3.44d; S2 , S4 , and S5 are conducting from Fig. 3.43b. In
this stage, the freewheeling current flows through S2 , D4 , and the filter. The LC loop
is also broken compared to conventional full-bridge TLI.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.10. From this table, it can be seen that the DMV maintains
unipolar SPWM performance, while the CMV has two uncertain states because the
freewheeling path is just disconnected from PV side in Mode 2 and Mode 4. In other
words, the CMV is not a perfect one in H6-IV.
64 3 Full-Bridge Transformerless PV Grid-Connected Inverters

Table 3.10 DMV and CMV of different operating modes in H6-IV

Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 Uncertain
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 Uncertain

In conclusion, the PV and grid are disconnected by the added two power switches
during freewheeling stages in H6-IV. LC will decrease due to weak CMV source.
The current flows through four power switches in power transmission stages, and two
power switches conduct in freewheeling stages. The power loss improved compared
to HERIC.
2. Simulations results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of H6-II are shown in Table 3.4.
The simulation waveforms of ug , iref , and ig are shown in Fig. 3.45. The simula-
tion waveforms of DMV uDM in time domain and frequency domain are shown in
Fig. 3.46a, b, respectively. uDM is a three-level voltage and the RMS of it is about
75 V at switching frequency.
The simulation waveforms of CMV uCM in time domain and frequency domain
are shown in Fig. 3.47a, b, respectively. It can be seen that the RMS of CMV is
about 2 V at switching frequency and contains little high-frequency components.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.48a, b, respectively. From Fig. 3.48, the LC is about 15 mA at
switching frequency. It still meets the standard.

ug:[100V/div]

ig:[10A/div]
iref:[10A/div]
0

t[10ms/div]

Fig. 3.45 Simulation waveforms of ug , iref , and ig of H6-IV

3.2 Full-Bridge TLIs with Decoupling Branches 65

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.46 DMV waveforms of H6-IV, a time domain, b frequency domain

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]
uCM:[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.47 CMV waveforms of H6-IV, a time domain, b frequency domain

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[200mA/div]
0

0
50Hz 18kHz 36kHz
t[5ms/div]

Fig. 3.48 LC waveforms of H6-IV, a time domain, b frequency domain

66 3 Full-Bridge Transformerless PV Grid-Connected Inverters

3.2.7 H6-V Inverter

1. Operating principle

H6-V was proposed in [13], and its main circuit is shown in Fig. 3.49a. The two power
switches S5 and S6 are introduced into H6-V. The power switch S5 is located on the
positive DC bus, while the switch S6 connects the positive DC bus and neutral point
2 of the inverter leg. This inverter is also DC side decoupling circuit. The modulation
strategy is shown in Fig. 3.49b. The output voltage is also a three-level voltage.
There are four operating modes based on the directions of grid voltage and grid-in
current when H6-V works in unity power factor, as shown in Fig. 3.50. Figure 3.50a,
b belongs to the positive grid cycle, while Fig. 3.50c, d belongs to the negative grid
cycle.
Mode 1: Refer to Fig. 3.50a; in this stage, the energy transfers from the PV side
to the grid through S1 , S4 , S5 , and the filter.
Mode 2: Refer to Fig. 3.50b; S1 is conducting from Fig. 3.49b. In this stage, the
freewheeling current flows through S1 , D3 , and the filter. The freewheeling circuit
is disconnected with PV side completely and the LC loop is cut off compared to
conventional full-bridge TLI.
Mode 3: Refer to Fig. 3.50c; in this stage, the energy transfers from the PV side
to the grid through S2 , S6 , and the filter.
Mode 4: Refer to Fig. 3.50d; S3 is conducting from Fig. 3.49b. In this stage, the
freewheeling current flows through S3 , D1 , and the filter. The LC loop is also open
as Mode 2.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.11. From this table, it can be seen that the DMV maintains
unipolar SPWM performance, and the CMV has two uncertain states because the
freewheeling path is just disconnected from PV side in Mode 2 and Mode 4. In other
words, the CMV is not a perfect one in H6-V.
In conclusion, two power switches are introduced at DC side in H6-V. The PV
and grid are disconnected during freewheeling stages in H6-V. LC will decrease due

(a) (b)
S5 vM vtri
D5 ωt
S1 S3
Upv D1 D3
1 S1 ωt
L1 C ug
S3 ωt
PV S6 2 L2 S4, S5 ωt
Cdc D6 S2, S6 ωt
S2 S4
D2 D4 u12 ωt
N

Fig. 3.49 H6-V inverter, a main circuit, b modulation strategy

3.2 Full-Bridge TLIs with Decoupling Branches 67

(a) (b)
S5 S5
D5 D5
S1 S3 S1 S3
Upv D1 D3 ig Upv D1 D3 ig
iL1 L1 C ug iL1 L1 C ug
S6 S6
PV L2 PV L2
Cdc D6 Cdc D6
S2 S4 S2 S4
N D2 D4 N D2 D4

(c) (d)

S5 S5

D5 D5
S1 S3 S1 S3
Upv D1 D3 ig Upv D1 D3 ig
iL1 L1 C ug iL1 L1 C ug
S6 S6
PV L2 PV L2
Cdc D6 Cdc
D6
S2 S4 S2 S4
N D2 D4 N D2 D4

Fig. 3.50 Equivalent circuits of operating modes of H6-V, a mode 1, b mode 2, c mode 3, d mode
4

Table 3.11 DMV and CMV of different operating modes in H6-V

Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 Uncertain
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 Uncertain

to the disconnected CMV loop. Its working principles and power loss are similar to
H5.
The current flows through three power switches in energy transmission stage
in grid positive cycle. However, the current flows through two power switches in
energy transmission stage in grid negative cycle during both power transmission and
freewheeling stages. The power loss is reduced compared to H6-I or H6-II.
2. Simulations results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of H6-II are shown in Table 3.4.
68 3 Full-Bridge Transformerless PV Grid-Connected Inverters

The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.51. The simulation waveforms of DMV uDM in time domain
and frequency domain are shown in Fig. 3.52a, b, respectively. uDM is a three-level
voltage. The simulation waveforms of CMV uCM in time domain and frequency
domain are shown in Fig. 3.53a, b, respectively. It can be seen that the RMS of CMV
is about 2 V at switching frequency.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.54a, b, respectively. From Fig. 3.54, the LC is about 12 mA at
switching frequency. It meets the standard and close to it in H6-IV.
Only active power switches are added to the inverter legs in traditional full-bridge
TLIs, and thus short-circuit risk exists. To improve the reliability of full-bridge
TLIs, researchers introduced the buck structure into full-bridge TLIs, such as double
inductors dual buck inverter (DIDBI) [14–16] and high efficiency and reliability
transformerless inverter (HERTLI) [17].

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.51 Simulation waveforms of ug , iref , and ig of H6-V

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.52 DMV waveforms of H6-V, a time domain, b frequency domain

3.2 Full-Bridge TLIs with Decoupling Branches 69

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.53 CMV waveforms of H6-V, a time domain, b frequency domain

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[200mA/div]
0

0
50Hz 18kHz 36kHz
t[5ms/div]

Fig. 3.54 LC waveforms of H6-V, a time domain, b frequency domain

3.2.8 Double Inductors Dual Buck Inverter

DIDBI was patented by Xantrex in 2005, and the main circuit is shown in Fig. 3.55a. It
is also called Xantrex inverter. Four inductors L 1 , L 2 , L 3 , and L 4 are used in DIDBI.
These inductors can be discrete components or coupled inductors. Its structure is
more complicated than conventional full-bridge TLI, but their operating principles
are the same.
1. Operating principle

Two modulation strategies can be used for DIDBI, which are shown in Fig. 3.55b and
3.55c, respectively. In modulation strategy I, as shown in Fig. 3.55b, S1 and S4 work
in high frequency in positive cycle of grid, and S2 and S3 work in high frequency in
negative cycle of grid. In this situation, the output voltage is a two-level voltage. In
modulation strategy II, S1 and S4 work complementary with S2 and S3 during the
70 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a)
S1 S3
D1 D5 D8
L1 D3
Upv L5
1
2 L2 C ug
L3
PV Cdc 3
4 L6
S2 S4 L4
D6 D2 D7 D4
N
(b) (c)
vM vtri vM vtri
ωt ωt

S1, S4 ωt S1, S4 ωt
v14 ωt v14 ωt

S2, S3 ωt S2, S3 ωt
u23 ωt u23 ωt

Fig. 3.55 Double inductors dual-buck inverter, a main circuit, b modulation strategy I, c modulation
strategy II

grid-in current crossing zero area, and the other modulation strategies are the same
with modulation strategy I, as shown in Fig. 3.55c. DIDBI can work in non-unity
power factor.
There are four operating modes based on the directions of grid voltage and grid-
in current when DIDBI works in unity power factor and using modulation strategy
I, as shown in Fig. 3.56. Figure 3.56a, b belongs to the positive grid cycle, while
Fig. 3.56c, d belongs to the negative grid cycle.
Mode 1: Refer to Fig. 3.56a; in this stage, the energy transfers from the PV side
to the grid through S1 , S4 , L 1 , and L 4 .
Mode 2: Refer to Fig. 3.56b; all the active power switches are closed from
Fig. 3.55b. In this stage, the current flows through D6 , D8 , L 1 , and L 4 . The energy is
transferred back to the DC side. It is the same as with conventional full-bridge TLI
using bipolar modulation strategy.
Mode 3: Refer to Fig. 3.56c. In this stage, the energy transfers from the PV side
to the grid through S2 , S3 , L 2 , and L 3 .
3.2 Full-Bridge TLIs with Decoupling Branches 71

(a) (b)
S1 S1
S3 D8 S3 D8
D1 D5 D3 D1 D5 D3
L1 L5 ig L1 L5 ig
Upv Upv
L2 C ug L2 C ug
L3 L3
PV Cdc PV Cdc
L6 S2 L6
S2 S4 L4 S4 L4
D6 D2 D7 D4 D6 D2 D7 D4
N N

(c) (d)
S1 S1
S3 D8 S3
D1 D5 D3 D1 D5 D3
D8
L1 L5 ig L1 L5 ig
Upv Upv
L2 C ug C ug
L2
L3 L3
PV Cdc PV Cdc
S2 L6 L6
S4 L4 S2 S4 L4
D6 D2 D7 D4 D6 D2 D7 D4
N N

Fig. 3.56 Equivalent circuits of operating modes of DIDBI using modulation strategy I, a mode 1,
b mode 2, c mode 3, d mode 4

Mode 4: Refer to Fig. 3.56d; all the active power switches are closed from
Fig. 3.55b. In this stage, the current flows through D5 , D7 , L 2 , and L 3 . The energy is
feeding back to the DC side as Mode 2.
Based on these modes, the potential of points 1 and 2 against N as well as uDM
and uCM is shown in Table 3.12. Because the current flows through different ways
in the positive and negative periods, the calculating methods are also different, as
shown in Table 3.12. From this table, it is clear that the CMV of DIDBI is constant
while DMV is two-level voltage. The CMV is perfect while DMV is poor in DIDBI.
From the operating modes in Fig. 3.56, the output voltage is a two-level voltage
and CMV is constant using modulation strategy I. Its operating modes are the same
as conventional full-bridge adopting bipolar modulation strategy. There are many
harmonics in the output voltage. Four inductors are used in DIDBI, which results in
low utilization of components. The inductors should work in DCM and lead to high
grid-in current distortion. Therefore, modulation strategy II is proposed to reduce the
current distortion. In modulation strategy II, switches S2 and S3 are triggered after S1

Table 3.12 DMV and CMV of different operating modes in DIDBI

Modes u1N u2N u3N u4N uDM uCM
(1) U pv – – 0 U pv U pv /2
(2) 0 – – U pv −U pv U pv /2
(3) – 0 U pv – −U pv U pv /2
(4) – U pv 0 – U pv U pv /2
72 3 Full-Bridge Transformerless PV Grid-Connected Inverters

and S4 are closed during the current crossing zero range. Then the inductors current
will decrease slowly and flows through S1 and S4 to S2 and S3 naturally. The current
distortion will be reduced in this situation. And another two modes will appear, as
shown in Fig. 3.57a, b, respectively. The current will flow through four inductors to
commutating smoothly.
2. Simulations results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of H6-II are shown in Table 3.13.
The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.58 when using modulation strategy I. The simulation waveforms
of DMV u14 and u23 are shown in Fig. 3.59a, b, respectively. From Fig. 3.59, u14 and
u23 are two-level voltages in the positive and negative grid cycle, respectively.
The simulation waveforms of inductors current iL1 and iL2 are shown in Fig. 3.60a,
b. It can be seen that L 1 and L 2 are working in the positive and negative grid cycle,
respectively. So do L 3 and L 4 . The simulation waveforms of LC iCM in time domain
and frequency domain are shown in Fig. 3.61a, b, respectively. From Fig. 3.61, the
switching frequency component is suppressed because of two-level output voltage.
The simulation waveforms of ig are shown in Fig. 3.62a and the simulation wave-
forms of ig , iL1 , and iL2 during the current crossing zero range using modulation

(a) (b)
S1 S1
S3 D8 S3
D1 D5 D3 D1 D5 D3
D8
L1 L5 ig L1 L5 ig
Upv Upv
iL1 ug iL1
L2 iL4 C L2 iL2 C ug
iL2 L3 L3
PV Cdc PV Cdc
iL3 L6 iL3 L6
S2 S4 L4 S2 S4 L4 iL4
D6 D2 D7 D4 D6 D2 D7 D4
N N

Fig. 3.57 Equivalent circuits of new operating modes of DIDBI using modulation strategy II,
a mode 1, b mode 2

Table 3.13 Simulation

Parameters Value Parameters Value
parameters of DIDBI
Input voltage U pv /V 200 Switching frequency 40
f s /kHz
Grid voltage ug /V 120 Inductors L 1 , L 2 , L 3 , 0.75
L 4 /mH
Grid frequency/Hz 50 Filter inductors L 5 , 0.25
L 6 /mH
Rated power P/W 2500 PV parasitic capacitor 300
C pv /nF
3.2 Full-Bridge TLIs with Decoupling Branches 73

ug:[100V/div]
0

ig:[5A/div]
iref:[5A/div]
0

Fig. 3.58 Simulation waveforms of ug , iref , and ig of DIDBI under unity power factor

(a) (b)

ig:[10A/div] ig:[10A/div]
0 0

ug:[50V/div] ug:[50V/div]
u14:[100V/div] u23 :[100V/div]

0 0 0
0
t[5ms/div] t[5ms/div]

Fig. 3.59 DMV waveforms of DIDBI, a u14 , b u23

(a) (b)

ig:[10A/div] ig:[10A/div]
0 0

ug:[50V/div] ug:[50V/div]

iL1:[2A/div] iL2 :[2A/div]

0 t[5ms/div] 0 t[5ms/div]

Fig. 3.60 Inductors current waveforms of DIDBI, a iL1 , b iL2

74 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

A[5mA/div]
ig:[10A/div]
0

ug:[50V/div]

iCM:[2mA/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.61 LC waveforms of DIDBI, a time domain, b frequency domain

(a) (b)

ig:[5A/div] iL1:[1A/div]
0 0
iL2:[1A/div]
ig:[1A/div]

t[2ms/div] t[5μs/div]

Fig. 3.62 Grid-in current and inductors current waveforms of DIDBI using modulation strategy I,
a ig , b ig , iL1 , and iL2 during current crossing zero range

strategy I are shown in Fig. 3.62b. From Fig. 3.62, it is clear that there is a long time
interval between iL1 decreasing to zero and iL2 increasing.
The simulation waveforms of ig are shown in Fig. 3.63a, and the simulation
waveforms of ig , iL1 , and iL2 during the current crossing zero range using modulation
strategy II is shown in Fig. 3.63b. As seen, iL1 and iL2 are not zero during this area.
The current distortion is reduced. The current is continuous in this situation and it can
work in non-unity power factor, as shown in Fig. 3.64. The simulation waveforms of
leading and lagging power factor are shown in Fig. 3.64a, b, respectively. So DIDBI
can work in non-unity power factor to support grid with reactive power.
The output voltage of DIDBI is a two-level voltage. The loss is high and needs
complicated filter. Then, researchers proposed unipolar high efficiency and reliability
transformerless inverter [17–19].
3.2 Full-Bridge TLIs with Decoupling Branches 75

(a) (b)

iL1 :[1A/div]
ig:[5A/div]

0 0
ig:[1A/div]
iL2 :[1A/div]

t[2ms/div] t [5μs/div]

Fig. 3.63 Grid-in current and inductors current waveforms of DIDBI using modulation strategy II,
a ig , b ig , iL1 , and iL2 during current crossing zero range

(a) (b)

ug:[50V/div]
ug:[50V/div]
ig:[5A/div]

0 0
ig:[5A/div]

t[5ms/div] t[5ms/div]

Fig. 3.64 Simulation waveforms of ug , iref , and ig of DIDBI under non-unity power factor, a leading
power factor, b lagging power factor

3.2.9 High Efficiency and Reliability Transformerless

Inverter

1. Operating principle

HERTLI [17] is shown in Fig. 3.65a. Two coupled inductors are used in this circuit
[18] which can also be replaced by discrete inductors. The modulation strategy is
shown in Fig. 3.65b. Apparently, S1 –S4 work in unipolar modulation strategy and
S5 –S6 work in fundamental frequency. The output voltage is also three-level voltage.
This inverter is AC side decoupling type TLI.
There are four operating modes according to the directions of grid voltage and
grid-in current when HERTLI works in unity power factor, as shown in Fig. 3.66.
76 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(b)
vM vtri
(a)
ωt
S1 D9 D10
S2 D2
D1 L1 S1, S 3 ωt
Upv 1
D5 S2, S 4 ωt
2 ug S5 ωt
PV Cdc S5 S6 ωt
3 S6 L2
D6 u13 ωt
4
S4 S3
D7 D8 u24 ωt
N D4 D3

Fig. 3.65 High efficiency and reliability transformerless inverter, a main circuit, b modulation
strategy

(a) (b)
S1 D9 D10 S1 D9 D10
S2 D2 S2 D2
D1 L1 ig D1 L1 ig
Upv D5 io1 Upv D5 io1
ug ug
PV Cdc S5 PV Cdc S5
S6 S6
L2 L2
D6 D6
S4 S3 S4 S3
D7 D3 D8 D7 D3 D8
N D4 N D4

(c) (d)
S1 D9 D10 S1 D9 D10
S2 D2 S2 D2
D1 L1 ig D1 L1 ig
Upv D5 Upv D5
ug ug
PV Cdc S5 PV Cdc S5
S6 S6
L2 L2
D6 io2 D6 io2
S4 S3 S4 S3
D7 D3 D8 D7 D3 D8
N D4 N D4

Fig. 3.66 Equivalent circuits of operating modes of HERTLI, a mode 1, b mode 2, c mode 3,
d mode 4

Figure 3.66a, b belongs to the positive grid cycle, while Fig. 3.66c, d belongs to the
negative grid cycle.
Mode 1: Refer to Fig. 3.66a; in this stage, the energy transfers from the PV side
to the grid through S1 , S3 , and L 1 . In this mode, current in primary winding of L 1 is
io1 .
Mode 2: Refer to Fig. 3.66b; only S5 is conducting from Fig. 3.65b. In this stage,
the freewheeling current flows through S5 , D5 , and L 1 . The freewheeling circuit
3.2 Full-Bridge TLIs with Decoupling Branches 77

Table 3.14 DMV and CMV levels of different operating modes in HERTLI
Modes u1N u2N u3N u4N uDM uCM
(1) U pv – 0 – U pv U pv /2
(2) U pv /2 – U pv /2 – 0 Uncertain
(3) – 0 – U pv −U pv U pv /2
(4) – U pv /2 – U pv /2 0 Uncertain

is disconnected with PV side completely and the LC loop is cut off compared to
conventional full-bridge TLI.
Mode 3: Refer to Fig. 3.66c; in this stage, the energy transfers from the PV side
to the grid through S2 , S4 , and L 2 . In this mode, current in primary winding of L 2 is
io2 .
Mode 4: Refer to Fig. 3.66d; only S6 is conducting and S2 and S4 are closed from
Fig. 3.65b. In this stage, the freewheeling current flows through S6 , D6 , and L 2 . The
LC loop is also cut off.
Based on these modes, the potential of points 1, 2, 3, and 4 against N as well as
uDM and uCM is shown in Table 3.14. Because the current flows through different
ways in positive and negative period, the calculating methods are also different, as
shown in Table 3.14. From this table, CMV of HERTLI is uncertain because the
freewheeling path is just disconnected from PV side in freewheeling modes. LC will
appear in this situation based on the first principle in Chap. 2.
Table 3.15 shows the number of components of H5, H6-I, and HERTLI in power
transmission and freewheeling stages. From this table, the number of conducting
components is the least in HERTLI. In [17], the authors give the total power loss of
H5, H6-I, and HERTLI at 5 kW and 20 kHz, as shown in Table 3.16. From this table,
the total power loss of HERTLI is the least in different output power.
In conclusion, shooting through is avoided by power switches S1 –S6 series with
power diodes in HERTLI. The operating reliability is improved. Two coupled induc-
tors are used in HERTLI. Reverse recovery problems of power diodes are alleviated.
The dead time for current crossing zero is avoided and distortion is reduced. But,
the design of coupled inductors is complicated and thus cost is improved. CMV of
HERTLI is still uncertain. Besides, the power loss is almost equal to it of HERIC,
but the utilization of the components of HERIC is higher. From this point, HERIC
is more popular in industry.

Table 3.15 Device numbers of conducting durations in different TLIs

Operating stages Switching components H5 H6-I HERTLI
Power transmission stage Power switches 3 3 2
Power diodes 0 0 0
Freewheeling stage Power switches 1 1 1
Power diodes 1 1 1
78 3 Full-Bridge Transformerless PV Grid-Connected Inverters

Table 3.16 Total power

Po (%) H5(W) H6-I(W) HERTLI(W)
losses in different TLIs
100 76.99 68.65 53.56
75 41.24 43.04 34.55
50 30.67 23.89 20.12
30 17.92 13.23 11.87
20 12.79 9.45 8.85
10 8.48 7.80 6.56

Table 3.17 Simulation

Parameters Value Parameters Value
parameters of HERTLI
Input voltage U pv /V 380 Switching frequency 20
f s /kHz
Grid voltage ug /V 240 Filter inductors L 1 , 0.95
L 2 /mH
Grid frequency/Hz 50 Filter capacitor C/µF 2.2
Rated power P/W 3500 PV parasitic capacitor 300
C pv /nF

2. Simulations results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of HERTLI are shown in Table 3.17.
The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.67. The simulation waveforms of DMV u13 and u24 are shown in
Fig. 3.68a, b, respectively. And u13 and u24 are three-level voltage in the positive and
negative grid cycle, respectively. The simulation waveforms of inductors current io1
and io2 are shown in Fig. 3.69a, b, respectively. It is clear that L 1 and L 2 are working

ug:[100V/div]
0

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.67 Simulation waveforms of ug , iref , and ig of HERTLI

3.2 Full-Bridge TLIs with Decoupling Branches 79

(a) (b)

ig:[10A/div] ig:[10A/div]
0 0

ug:[100V/div] ug:[100V/div]
u24 :[100V/div]

0 0

u13:[100V/div] t[5ms/div]
t[5ms/div]

Fig. 3.68 DMV waveforms of HERTLI, a u13 , b u24

(a) (b)

ig:[10A/div] ig:[10A/div]
0 0

ug:[100V/div] ug:[100V/div]

io1:[5A/div] io2 :[5A/div]

0 0
t[5ms/div] t[5ms/div]

Fig. 3.69 Inductors current waveforms of HERTLI, a primary current of L 1 io1 , b primary current
of L 2 io2

in the positive and negative grid cycle, respectively. The simulation waveforms of LC
iCM in time domain and frequency domain are shown in Fig. 3.70a, b, respectively.
From Fig. 3.70, the LC is about 11 mA at switching frequency. It meets the standard
and similar to HERIC.
Some of the TLIs above have been used in distributed PV generation. But, LC still
exists in decoupling type TLIs from the experimental result in the field. The reason
is that the potential of freewheeling circuit is oscillating because of PV parasitic
capacitors. CMV is uncertain during freewheeling stages. From the first principle of
Sect. 2.2.2, CMV should be clamped at half of the DC input to keep it constant [20,
21]. In [21], the CMV clamping conception is first proposed. New clamping cells are
presented. And novel TLI based on H5 is also presented with its modulation strategy.
From then on, researchers have done much research on clamping circuits and utilize
it in the TLIs introduced above [21–30].
80 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]
iCM:[100mA/div]
0

0
t[5ms/div] 50Hz 20kHz 40kHz

Fig. 3.70 LC waveforms of HERTLI, a time domain, b frequency domain

3.3 Full-Bridge TLIs with Clamping Branches

3.3.1 Clamping Circuits

The freewheeling circuit is the key structure in decoupling type full-bridge TLIs.
The AC decoupling structures are shown in Fig. 3.71 [20]. Two power switches can
be in series or parallel together for flowing current bidirectional in Fig. 3.71a–c. The
structure can also be replaced by one power switches combined with a rectifier bridge
in Fig. 3.71d.
Decoupling circuits should be combined with clamping structure to keep CMV
constant. The clamping structure can be classified into unidirectional and bidirec-
tional clamping with power switches or diodes. Unidirectional clamping can only
clamp CMV at constant when CMV is decreasing or increasing, while bidirectional
clamping can make CMV constant whenever the potential decreases or increases.
Only one diode is included in a unidirectional clamping structure because power
switches are always parallel with a diode. The clamping structure with only one
diode is shown in Fig. 3.72 based on Fig. 3.71.

(a) (b) (c) (d)

Fig. 3.71 Freewheeling circuits, a structure 1, b structure 2, c structure 3, d structure 4

3.3 Full-Bridge TLIs with Clamping Branches 81

Fig. 3.72 Single direction (a) (b)

clamping circuits with single
power switch, a structure 1,
b structure 2

Furthermore, bidirectional clamping with one power switch structure is got by

replacing the diode with a power switch in Fig. 3.72, as shown in Fig. 3.73c–e.
Bidirectional clamping with two power switches structure is shown in Fig. 3.74a.
The two power switches can also be connected back to back in Fig. 3.74b to form a
bidirectional clamping structure. Those components can be rearranged and replaced
by four power switches, as shown in Fig. 3.74c, d.
The clamping structures above can also be used in DC side decoupling type TLIs.
Clamping type full-bridge TLIs will be discussed in next section.

(a) (b)

(c) (d) (e)

Fig. 3.73 Bidirectional clamping circuits with single power switch, a structure 1, b structure 2,
c structure 3, d structure 4, e structure 5
82 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b) (c) (d)

Fig. 3.74 Bidirectional clamping circuits with two power switches, a structure 1, b structure 2,
c structure 3, d structure 4

3.3.2 Optimized H5 Transformerless Inverter

1. Operating principle

The optimized H5 transformerless inverter (oH5) was proposed in [21], the main
circuit of it is shown in Fig. 3.75a. A new power switch S6 is added to connect
the DC bus and the neutral point of DC input based on H5. The oH5 is clamping
type TLI but also a DC side decoupling circuit. The modulation strategy is shown
in Fig. 3.75b. S5 and S6 work in high frequency. S1 –S4 work in fundamental or high
frequency depending on the grid voltage. The output voltage is a three-level voltage
and maintains high efficiency as H5. In unity power factor, there are four operating
modes based on the directions of grid voltage and grid-in current. The modes are
similar to H5, as shown in Fig. 3.19. Dead time should be considered in the driving
logic between S5 and S6 for avoiding short circuit.
The operating principles of the clamping circuit are shown in Fig. 3.76. The
clamping mode when freewheeling circuit potential rises is shown in Fig. 3.76a,
while the clamping mode when freewheeling circuit potential decreases is shown
in Fig. 3.76b. In freewheeling stages, LC will flow into DC side through S6 if its
potential rises and it will flow from DC side through D6 if its potential decreases.
Thus, CMV is clamped at half of DC input voltage. It is pointed out that during dead

(a) (b)
vM vtri
S5
ωt
D5 D1 D3
Cdc1
S1 S3 S1 ωt
Upv S2 ωt
S6 1 L1
C ug S3 ωt
PV D6 L2 S4 ωt
2 S5 ωt
Cdc2 S2 D2 S6 ωt
N S4 D4 u12 ωt

Fig. 3.75 Optimized H5 transformerless inverter, a main circuit, b modulation strategy

3.3 Full-Bridge TLIs with Clamping Branches 83

(a) (b)
S5 S5

D1 D D1 D3
D D3 Cdc1 5
Cdc1 5
S3 LCM Zline1 S1 S3 LCM Zline1
S1
S6 CY1 S6 CY1
iCM ZG iCM ZG
iDM iDM
PV D6 PV D6
Cdc2 CY2 Zline2 Cdc2 CY2 Zline2
S2 S2
D2 D2
D5 D4 N D5 D4
N S4 S4

Fig. 3.76 Equivalent circuits when clamping circuit conducting in oH5, a potential rises, b potential
decreases

Table 3.18 DMV and CMV levels of different operating modes in oH5
Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 U pv /2 (uncertain during dead time)
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 U pv /2 (uncertain during dead time)

time between S5 and S6 , CMV can be clamped only when the potential decreases.
This is common in the active clamping CMV TLIs.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.18. From this table, it is clear that DMV maintains unipolar
SPWM performance. CMV of oH5 is constant except for it during dead time. CMV
performance is improved.
In conclusion, one power switch is introduced at DC side in oH5. The PV side
and grid side are disconnected during freewheeling stages in oH5. LC will decrease
due to the disconnected CMV loop. And CMV is clamped at constant during the
whole period except for dead time. The current flows through three power switches
in power transmission stages and through two power switches in freewheeling stages,
which is the same as H5.
2. Simulation results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters are shown in Table 3.4.
The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.77. The simulation waveforms of DMV uDM in time domain
and frequency domain are shown in Fig. 3.78a, b, respectively. uDM is a three-level
voltage and contains little harmonics. The simulation waveforms of CMV uCM in time
domain and frequency domain are shown in Fig. 3.79a, b, respectively. The amplitude
of high-frequency pulses is higher than U pv /2, while the amplitude of fundamental
84 3 Full-Bridge Transformerless PV Grid-Connected Inverters

ug:[100V/div]

ig:[10A/div]
iref:[10A/div]
0

t[10ms/div]

Fig. 3.77 Simulation waveforms of ug , iref , and ig of oH5

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.78 DMV waveforms of oH5, a time domain, b frequency domain

(a) (b)

A[2V/div]
ig:[10A/div]
0

ug:[100V/div]
uCM:[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.79 CMV waveforms of oH5, a time domain, b frequency domain

3.3 Full-Bridge TLIs with Clamping Branches 85

frequency pulses is lower than U pv /2. The former phenomenon is because CMV
is uncertain during dead time between power switches, and the latter phenomenon
is due to variable CMV during the time when current crossing zero, as shown in
Fig. 3.76.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.80a, b, respectively. From Fig. 3.80, the LC is about 4 mA at switching
frequency. LC is reduced by a wide margin because high-frequency components in
CMV are suppressed.
3. Experimental results

In order to verify the theoretical analysis and simulation waveforms, a prototype of

oH5 is built, and the key parameters are shown in Table 3.19.
The grid voltage ug , grid current ig , and inverter output voltage uDM (it is also
the differential-mode voltage) from top to bottom are shown in Fig. 3.81a. In this

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]
iCM:[50mA/div]

0
0 t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.80 LC waveforms of oH5, a time domain, b frequency domain

Table 3.19 Key parameters of oH5 prototype

Parameters Value Parameters Value
Input voltage U pv /V 340–700 Filter inductors L 1 , L 2 /mH 4
Grid voltage ug /V 240 Filter capacitor C/µF 6.6
Grid frequency/Hz 50 Common-mode inductor 2 × 2 W-43615-TC
L CM
Rated power P/W 1000 Wire/mm Wire: 2 mm
Switching frequency 20 Turns Turns: 10 + 10
f s /kHz
DC side capacitors C dc1 , 470 µF/400 V Common-mode capacitor 2.2
C dc2 /µF C Y1 , C Y2 /nF
MOSFET S1 –S6 IXFN36N100 PV parasitic capacitor 0.1
C pv1 , C pv2 /µF
86 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

Fig. 3.81 DMV and CMV waveforms of oH5, a DMV, b CMV

figure, the output voltage uDM has three levels as U pv , 0, and −U pv , so a good
differential-mode characteristic has been achieved like the unipolar SPWM full-
bridge grid-connected inverter with galvanic isolation. The grid voltage ug , grid
current ig , voltage u1N of midpoint 1 to terminal N, common-mode voltage uCM =
u1N + u2N , and voltage u2N of middle point 2 to terminal N are shown in Fig. 3.81b
from top to down, respectively.
Both of the detailed common-mode voltage waveforms at the peak and the value
of grid current are shown in Fig. 3.82a, b, respectively. It can be seen that the narrow
pulse width in the u1N turning to zero ring of Fig. 3.82a corresponds to the dead
time between the switches S5 and S6 . In this span, the freewheeling path potential
rises because the clamp switch S5 is still off. When S6 is on, the freewheeling path
potential will be quickly clamped to the midpoint potential of the capacitor divider.
The experimental results are in agreement with the theoretical analysis well.

(a) (b)

ug iD6 :[40mA/div]

iD6:[40mA/div] ug
v1N
v1N

2uCM 2u CM

v2N v2N

Fig. 3.82 Detailed CMV waveforms of oH5, a at the peak of grid current, b at the vale of grid
current
3.3 Full-Bridge TLIs with Clamping Branches 87

3.3.3 Diode Clamping H5 Inverter

1. Operating principle

Another active power switch is needed in oH5 inverter. And dead time should be
considered between the switch in positive DC bus and clamping switch. On the
contrary, diode clamping H5 (H5-D) was proposed in [22], the main circuit of which
is shown in Fig. 3.83a. A diode is needed instead of a power switch compared to
oH5. This diode connects to the DC side neural point to clamp the potential naturally
without dead time. H5-D is still DC side decoupling TLI. The modulation strategy is
shown in Fig. 3.83b. S1 –S4 work in fundamental or high frequency depending on the
grid voltage. S5 works in high frequency. The output voltage is a three-level voltage
and H5-D maintains high efficiency as H5.
There are four operating modes based on the directions of grid voltage and grid-in
current when H5-D works in unity power factor, as shown in Fig. 3.84. Figure 3.84a,
b belongs to the positive grid cycle, while Fig. 3.84c, d belongs to the negative grid
cycle.
Mode 1: Refer to Fig. 3.84a; in this stage, the energy transfers from the PV side
to the grid through S1 , S4 , S5 , and the filter.
Mode 2: Refer to Fig. 3.84b, S2 –S5 are all closed while S1 is conducting from
Fig. 3.83b. In this stage, the freewheeling current flows through S4 , D2 , and the filter.
The freewheeling circuit is disconnected with PV side completely and the LC loop
is cut off compared to conventional full-bridge TLI.
Mode 3: Refer to Fig. 3.84c; in this stage, the energy transfers from the PV side
to the grid through S2 , S3 , S5 , and the filter.
Mode 4: Refer to Fig. 3.84d; only S3 is conducting from Fig. 3.83b. In this stage,
the freewheeling current flows through S2 , D4 , and the filter. The freewheeling circuit
is disconnected with PV side and the LC loop is also cut off.
The working principles of clamping circuit are shown in Fig. 3.85. In freewheeling
stages, LC will flow into DC side through Dc if its potential rises. Thus, CMV is
clamped at half of DC input voltage. It is pointed out that CMV cannot be clamped

(a) (b)
vM vtri
D1 D3
Cdc1 S1 ωt
S3
Upv 1
Dc L1 S1 ωt
C ug
S2 ωt
PV Cdc2 L2 S3 ωt
S2 2
D2 S4 ωt
D5 S5 ωt
N S4 D4
u12 ωt
S5

Fig. 3.83 Diode clamping H5 inverter, a main circuit, b modulation strategy

88 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
D1 D1
Cdc1 D3 Cdc1 D3
S1 S3 ig S1 S3 ig
Upv Upv
Dc iL1 L1 Dc iL1 L1 u
C ug C g
PV Cdc2 L2 PV Cdc2 L2
S2 S2
D2 D2
D5 D4 D4
D5
N S4 N S4
S5 S5
(c) (d)
D1 D1
Cdc1 D3 Cdc1 S1 D3
S1 S3 ig S3 ig
Upv Upv
Dc iL1 L1 Dc iL1 L1
C ug C ug
PV Cdc2 L2 PV Cdc2 L2
S2 S2
D2 D2
D5 D4 D5 D4
N S4 N S4
S5 S5

Fig. 3.84 Equivalent circuits of H5-D, a mode 1, b mode 2, c mode 3, d mode 4

Fig. 3.85 Equivalent circuit

when clamping circuit
conducting in H5-D D1 D3
Cdc1
S1 S3 LCM Zline1
Upv iCM CY1
ZG
iDM
PV Dc
Cdc2 CY2 Zline2
S2
D2
N D5 D4
S4
S5

when freewheeling circuit potential decreases. Thus, H5-D is the unidirectional

clamping TLI.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.20. From this table, it is clear that DC side and AC side are
disconnected in freewheeling stages. DMV maintains unipolar SPWM performance.
3.3 Full-Bridge TLIs with Clamping Branches 89

Table 3.20 DMV and CMV levels of different operating modes in H5-D
Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 ≤U pv /2
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 ≤U pv /2

The uncertain state of CMV is suppressed partly. CMV of H5-D is smaller than
U pv /2.
In conclusion, one diode is introduced at DC side in H5-D. The PV side and grid
side are disconnected during freewheeling stages in oH5. CMV is clamped by the
diode. LC will decrease a lot. The current flows through three power switches in
power transmission stages and through two power switches in freewheeling stages,
which is the same as H5. But, it can only clamp the CMV at U pv /2 when the potential
of freewheeling circuit increases.
2. Simulations results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of H5-D are shown in Table 3.4. The simu-
lation waveforms of ug , grid-in current reference iref , and grid-in current ig are shown
in Fig. 3.86.
The simulation waveforms of DMV uDM in time domain and frequency domain
are shown in Fig. 3.87a, b, respectively. uDM is a three-level voltage and the RMS of
it is about 75 V at switching frequency.
The simulation waveforms of CMV uCM in time domain and frequency domain
are shown in Fig. 3.88a, b, respectively. uCM only contains the components whose
amplitude is smaller than U pv /2, as discussed in Fig. 3.85.

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.86 Simulation waveforms of ug , iref , and ig of H5-D

90 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.87 DMV waveforms of H5-D, a time domain, b frequency domain

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.88 CMV waveforms of H5-D, a time domain, b frequency domain

The simulation waveforms of LC iCM in time domain and frequency domain

are shown in Fig. 3.89a, b, respectively. From Fig. 3.89, the LC is about 8 mA
at switching frequency. It is greatly reduced compared to H5 because components
whose amplitude higher than U pv /2 are removed.

3.3.4 Full-Bridge DC Bypassed Inverter

1. Operating principle

Full-bridge DC bypassed inverter (FB-DCBP) was proposed in [23], the main circuit
of which is shown in Fig. 3.90a. It is the diode clamping TLI and can also be called
a H6-D. The H6-D is a DC side decoupling TLI and has been commercially used
in Inecon Sun TL series (2.5/3.3/6 kW) by Ingeteam Inc. Its European efficiency is
3.3 Full-Bridge TLIs with Clamping Branches 91

(a) (b)

A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[200mA/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.89 LC waveforms of H5-D, a time domain, b frequency domain

(a) (b)
D5 vM vtri
D1 D3 ωt
S5
Cdc1 S1 S3
Upv
D7 1 L1 S1, S4 ωt
C ug
S2, S3 ωt
PV D8 L2
2 S5, S6
Cdc2 S2 ωt
D2
S6
N u12 ωt
S4 D4
D6

Fig. 3.90 Full-bridge DC bypassed inverter, a main circuit, b modulation strategy

96.5% as Photon International reported in August, 2007. The modulation strategy is

shown in Fig. 3.90b. S5 –S6 work in high frequency and S1 –S4 work in fundamental
frequency. The output voltage is a three-level voltage.
There are four operating modes based on the directions of grid voltage and grid-in
current when H6-D works in unity power factor, as shown in Fig. 3.91. Figure 3.91a,
b belongs to the positive grid cycle, while Fig. 3.91c, d belongs to the negative grid
cycle.
Mode 1: Refer to Fig. 3.91a; in this stage, the energy transfers from the PV side
to the grid through S1 , S4 , S5 , S6 , and the filter.
Mode 2: Refer to Fig. 3.91b; S1 and S4 are conducting from Fig. 3.90b. When S5
and S6 are turned off, the current splits into two paths: S1 and the freewheeling diode
D3 , and S4 and the freewheeling diode D2 . Freewheeling circuit is disconnected with
PV side and the LC loop is broken.
Mode 3: Refer to Fig. 3.91c; in this stage, the energy transfers from the PV side
to the grid through S2 , S3 , S5 , S6 , and the filter.
Mode 4: Refer to Fig. 3.91d; S2 and S3 are conducting from Fig. 3.90b. When S5
and S6 are turned off, the current splits into two paths: S3 and the freewheeling diode
92 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
D5 D5
D1 D3 D1 D3
S5 S5
Cdc1 S1 S3 ig Cdc1 S1 S3 ig
Upv Upv
D7 iL1 L1 D7 iL1 L1
C ug C ug
PV D8 L2 PV D8 L2
Cdc2 S2 Cdc2 S2
D2 D2
S6 S6
N S4 D4 N S4 D4
D6 D6
(c) (d)
D5 D5
D1 D3 D1 D3
S5 S5
Cdc1 S1 S3 ig Cdc1 S1 S3 ig
Upv Upv
D7 iL1 L1 D7 iL1 L1
C ug C ug
PV D8 L2 PV D8 L2
Cdc2 S2 Cdc2 S2
D2 D2
S6 S6
N S4 D4 N S4 D4
D6 D6

Fig. 3.91 Equivalent circuits of operating modes of H6-D, a mode 1, b mode 2, c mode 3, d mode
4

D1 , and S2 and the freewheeling diode D4 . Freewheeling circuit is disconnected with

PV side and the same effect is gained just like Mode 2.
The working principles of clamping circuit during the positive grid cycle are shown
in Fig. 3.92. The clamping mode when freewheeling circuit potential rises is shown

(a) (b)
S5 S5

D D1 D3 D D1 D3
Cdc1 5 Cdc1 5
S1 S3 LCM Zline1 S1 S3 LCM Zline1

D7 CY1 D7 CY1
iCM ZG ZG
iDM iCM iDM
PV PV
D8 D8
Cdc2 CY2 Zline2 Cdc2 CY2 Zline2
S2 S2
D2 D2
S6 S6
N S4 D4 N S4 D4
D6 D6

Fig. 3.92 Equivalent circuits when clamping circuit conducting in H6-D, a potential rises,
b potential decreases
3.3 Full-Bridge TLIs with Clamping Branches 93

Table 3.21 DMV and CMV levels of different operating modes in H6-D
Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 U pv /2
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 U pv /2

in Fig. 3.92a. The clamping mode when freewheeling circuit potential decreases is
shown in Fig. 3.92b. In freewheeling stages, LC will flow into DC side through D8 if
its potential rises and it will flow from DC side through D7 if its potential decreases.
Thus, CMV is clamped at half of DC input voltage.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.21. From this table, it is clear that DC side and AC side are
disconnected in freewheeling stages. DMV maintains unipolar SPWM performance.
CMV of H6-D is constant. Its common-mode performance is well.
In conclusion, two power switches S5 and S6 are introduced at positive and nega-
tive DC buses in H6-D, respectively. The PV and grid are disconnected during
freewheeling stages in H6-D. LC is greatly decreased because CMV is clamped
at U pv /2 by D7 and D8 . The current flows through four power switches during energy
transmission stage, which has negative influence on efficiency.
2. Simulation results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of H6-D are shown in Table 3.4.
The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.93.

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.93 Simulation waveforms of ug , iref , and ig of H6-D

94 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.94 DMV waveforms of H6-D, a time domain, b frequency domain

The simulation waveforms of DMV uDM in time domain and frequency domain
are shown in Fig. 3.94a, b, respectively. uDM is a three-level voltage and the RMS of
it is about 75 V at switching frequency.
The simulation waveforms of CMV uCM in time domain and frequency domain are
shown in Fig. 3.95a, b, respectively. No high-frequency components are contained
in uCM like the discussion in Fig. 3.92.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.96a, b, respectively. From Fig. 3.96, the LC is about 0.6 mA at
switching frequency. It is largely reduced compared to H6-V.
3. Experimental results

In order to verify the theoretical analysis and simulation waveforms, a prototype of

H6-D is built, and the key parameters are shown in Table 3.22.

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.95 CMV waveforms of H6-D, a time domain, b frequency domain

3.3 Full-Bridge TLIs with Clamping Branches 95

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[50mA/div]
0

0
50Hz 18kHz 36kHz
t[5ms/div]

Fig. 3.96 LC waveforms of H6-D, a time domain, b frequency domain

Table 3.22 Key parameters of H6-D prototype

Parameters Value Parameters Value
Input voltage U pv /V 340–700 Filter inductors L 1 , L 2 /mH 4
Grid voltage ug /V 240 Filter capacitor C/µF 6.6
Grid frequency/Hz 50 Common-mode inductor 2 × 2 W-43615-TC
L CM
Rated power P/W 1000 Wire/mm Wire: 2 mm
Switching frequency 20 Turns Turns: 10 + 10
f s /kHz
DC side capacitors C dc1 , 470 µF/400 V Common-mode capacitor 2.2
C dc2 /µF C Y1 , C Y2 /nF
MOSFET S1 –S6 IXFN36N100 PV parasitic capacitor 0.1
C pv1 , C pv2 /µF

ug ug
ig:
[6.7A/div]
ig:
[6.7A/div]
u1N
iCM:[80mA/div]
2uCM

0.7mA
u2N

Fig. 3.97 DMV and CMV waveforms of H6-D in grid scale, a CMV, b LC
96 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
ug
ug
iD7:[40mA/div]
iD7 :[40mA/div]
u1N
u1N
2uCM
2u CM

u2N
u2N

Fig. 3.98 Detailed CMV waveforms of H6-D, a at the peak of grid current, b at the vale of grid
current

The experimental waveforms of ug , ig , uCM , and iCM are shown in Fig. 3.97a, b.
The grid voltage ug , grid current ig , voltage u1N of midpoint 1 to terminal N, common-
mode voltage uCM = u1N + u2N , and voltage u2N of middle point 2 to terminal N
are shown in Fig. 3.98a, b, from top to down, respectively. Both of the detailed
common-mode voltage waveforms are also shown in Fig. 3.98a, b, respectively. It
can be seen that uCM is constant and LC is about 0.7 mA. The experimental results
are in agreement with the theoretical analysis as well.

3.3.5 Active Clamping H6 Inverter I

1. Operating principle

The active clamping H6 inverter I (AH6-I) was proposed in [24], whose main circuit
is shown in Fig. 3.99a. AH6-I is the clamping TLI based on TLI proposed in [10].
A new power switch S7 is added to connect the DC bus and the neutral point of
DC input based on TLI proposed in [10]. The AH6-I is an AC side decoupling TLI.
The modulation strategy is shown in Fig. 3.99b. S7 works in high frequency. S1 –S6
work in fundamental or high frequency depending on the grid voltage. The output
voltage is a three-level voltage.
There are six operating modes based on the directions of grid voltage and
grid-in current when AH6-I works in unity power factor, as shown in Fig. 3.100.
Figure 3.100a–c belongs to the positive grid cycle, while Fig. 3.100d–f belongs to
the negative grid cycle.
Mode 1: Refer to Fig. 3.100a; in this stage, the energy transfers from the PV side
to the grid through S2 , S3 , and the filter.
3.3 Full-Bridge TLIs with Clamping Branches 97

(a) (b)
vM vtri
ωt
Cdc1 S1 D1 S3 D3
D7 D6
Upv S 1, S 4 ωt
S7 1 L1
S6 C ug S2, S 3 ωt
PV S5 S5 ωt
D5 L2 S6 ωt
Cdc2 2
S7 ωt
S2 D2 S4 D4 u12 ωt
N

Fig. 3.99 Active clamping H6 inverter I, a main circuit, b modulation strategy

Mode 2: Refer to Fig. 3.100b; S5 –S6 are conducting, while S7 is still closed. In
this stage, the freewheeling current flows through S6 , D5 , and the filter. In this mode,
the potential of freewheeling circuit is not clamped by power switches or diodes, and
narrow pulses may appear in CMV.
Mode 3: Refer to Fig. 3.100c; S5 –S7 are conducting from Fig. 3.99b. In this stage,
the freewheeling current flows through S6 , D5 , and the filter. The freewheeling circuit
is disconnected with PV side and the LC loop is open compared to conventional
full-bridge TLI.
Mode 4: Refer to Fig. 3.100d; in this stage, the energy transfers from the PV side
to the grid through S1 , S4 , S5 , and the filter.
Mode 5: Refer to Fig. 3.100e; S5 is conducting while S7 is still closed. In this
stage, the freewheeling current flows through S5 , D6 , and the filter. In this mode, the
potential of freewheeling circuit is not clamped by power switches or diodes, and
narrow pulses may appear in CMV.
Mode 6: Refer to Fig. 3.100f; S5 –S7 are conducting from Fig. 3.99b. In this stage,
the freewheeling current flows through S5 , D6 , and the filter. The freewheeling circuit
is disconnected with PV side and the LC loop is cut off.
The working principles of clamping circuit are shown in Fig. 3.101. The clamping
mode when freewheeling circuit potential rises is shown in Fig. 3.101a. The clamping
mode when freewheeling circuit potential decreases is shown in Fig. 3.101b. In
freewheeling stages, LC will flow into DC side through S7 if its potential rises and it
will flow from DC side through D7 if its potential decreases. Thus, CMV is clamped
at half of DC input voltage. It is pointed out that during dead time between S7 and
other switches, CMV can be clamped only when the potential decreases.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.23. From this table, it is clear that DMV maintains unipolar
SPWM performance. CMV of AH6-I is constant except for it during dead time.
In conclusion, two power switches are introduced at inverter leg in AH6-I. A new
power switch S7 is connected to the neutral point of DC input. Dead time is also
needed. The PV side and grid side are disconnected during freewheeling stages. LC
will decrease as a result of almost constant CMV. The current flows through two
98 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

Cdc1 S1 D1 S3 D3 Cdc1 S1 D1 S3 D3
D7 D6 ig D7 D6 ig
Upv Upv
S7 iL1 L1 S7 iL1 L1
S6 C ug S6 C ug
PV S5 PV S5
D5 L2 D5 L2
Cdc2 Cdc2
S2 D2 S4 D4 S2 D2 S4 D4
N N

(c) (d)

Cdc1 S1 D1 S3 D3 Cdc1 S1 D1 S3 D3
D7 D6 ig D7 D6 ig
Upv Upv
S7 iL1 L1 S7 iL1 L1
S6 C ug S6 C ug
PV S5 PV S5
D5 L2 D5 L2
Cdc2 Cdc2
S2 D2 S4 D4 S2 D2 S4 D4
N N

(e) (f)

Cdc1 S1 D1 S3 D3 Cdc1 S1 D1 S3 D3
D7 D6 ig D7 D6 ig
Upv Upv
S7 iL1 L1 S7 iL1 L1
S6 C ug S6 C ug
PV S5 PV S5
D5 L2 D5 L2
Cdc2 Cdc2
S2 D2 S4 D4 S2 D2 S4 D4
N N

Fig. 3.100 Equivalent circuits of operating modes of AH6-I, a mode 1, b mode 2, c mode 3, d mode
4, e mode 5, f mode 6

power switches in power transmission stages in positive grid cycle. It flows through
three power switches in power transmission stages in negative grid cycle. The power
loss may be saved compared to H6-D.
2. Simulation results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of AH6-I are shown in Table 3.4.
3.3 Full-Bridge TLIs with Clamping Branches 99

(a) (b)

Cdc1 S1 D1 S3 Cdc1 S1 D1 S3
D3 D3
D7 D6 LCM Zline1 D7 D6 LCM Zline1
Upv Upv
S7 CY1 S7 CY1
iCM S6 ZG iCM S6 ZG
PV S5 iDM PV S5 iDM
D5 CY2 Zline2 D5 CY2 Zline2
Cdc2 Cdc2
S2 D2 S4 D4 S2 D2 S4 D4
N N

Fig. 3.101 Equivalent circuits when clamping circuit conducting in AH6-I, a potential rises,
b potential decreases

Table 3.23 DMV and CMV levels of different operating modes in AH6-I
Modes u1N u2N uDM uCM
(1), (3) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 U pv /2 (uncertain during dead time)
(4), (6) 0 U pv −U pv U pv /2
(5) U pv /2 U pv /2 0 U pv /2 (uncertain during dead time)

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.102 Simulation waveforms of ug , iref , and ig of AH6-I

The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.102.
The simulation waveforms of DMV uDM in time domain and frequency domain
are shown in Fig. 3.103a, b, respectively. uDM is a three-level voltage and contains
little harmonics.
100 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.103 DMV waveforms of AH6-I, a time domain, b frequency domain

(a) (b)

A[2V/div]
ig:[10A/div]
0

t[5ms/div]
ug:[100V/div]
uCM:[50V/div]

0 0
0Hz 18kHz 36kHz

Fig. 3.104 CMV waveforms of AH6-I, a time domain, b frequency domain

The simulation waveforms of CMV uCM in time domain and frequency domain are
shown in Fig. 3.104a, b, respectively. It contains the components whose amplitude
is higher than U pv /2. This is because CMV is uncertain during dead time between
power switches. While the amplitude of fundamental frequency pulses lower than
U pv /2 also exists, this phenomenon is due to variable CMV when current crossing
zero, as discussed in Fig. 3.101.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.105a, b, respectively. From Fig. 3.105, the LC is about 7 mA at
switching frequency. LC is greatly reduced compared to the TLI in [10].
3.3 Full-Bridge TLIs with Clamping Branches 101

(a) (b)
A[5mA/div]
ig:[10A/div]
0

t[5ms/div]
ug:[100V/div]
iCM:[50mA/div]

0 0
50Hz 18kHz 36kHz

Fig. 3.105 LC waveforms of AH6-I, a time domain, b frequency domain

3.3.6 Active Clamping H6 Inverter II

1. Operating principle

The active clamping H6 inverter II (AH6-II) was proposed in [25], the main circuit
of which is shown in Fig. 3.106a. The main circuit of AH6-II is similar to H6-II. Two
power switches S7 and S8 are added as the clamping circuit. The AH6-II is also AC
side decoupling TLI. The modulation strategy is shown in Fig. 3.106b. S2 , S5 , S7 ,
and S8 work in fundamental frequency, while others work in fundamental or high
frequency depending on the grid voltage. The output voltage is a three-level voltage.
There are four operating modes based on the directions of grid voltage and
grid-in current when AH6-II works in unity power factor, as shown in Fig. 3.107.
Figure 3.107a, b belongs to the positive grid cycle, while Fig. 3.19c, d belongs to the
negative grid cycle.

(a) (b)
vM vtri

Cdc1 S1 S4 D4 ωt
D1
D7
Upv L1 C
D2 2 ug S1, S6 ωt
S7 S2 L2 S2, S5 ωt
S5
PV D8
1 D5 S3, S4 ωt
S7, S8 ωt
S8 S6 D6 u12
Cdc2 ωt
N S3 D3

Fig. 3.106 Active clamping H6 inverter II, a main circuit, b modulation strategy
102 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

S1 S4 iL1 ig S4 iL1 ig
Cdc1 D4 Cdc1 S1 D4
D1 D7 D1
D7
Upv L1 C Upv L1 C
D2 ug D2 ug
S7 S2 L2 S7 S2 L2
S5 S5
PV D8 PV D8
D5 D5

S8 S6 D6 S8 S6 D6
Cdc2 Cdc2
N S3 D3 N S3 D3
(c) (d)

S1 S4 iL1 ig S1 S4 iL1 ig
Cdc1 D4 Cdc1 D4
D1 D1
D7 D7
Upv L1 C Upv L1 C
D2 ug D2 ug
S7 S2 L2 S7 S2 L2
S5 S5
PV D8 PV D8
D5 D5

S8 S6 D6 S8 S6 D6
Cdc2 Cdc2
N S3 D3 N S3 D3

Fig. 3.107 Equivalent circuits of operating modes of AH6-II, a mode 1, b mode 2, c mode 3,
d mode 4

Mode 1: Refer to Fig. 3.107a; in this stage, the energy transfers from the PV side
to the grid through S1 , S2 , S5 , S6 , and the filter. The operating principle is the same
as in conventional full-bridge TLI using unipolar SPWM modulation.
Mode 2: Refer to Fig. 3.107b; S2 and S5 are all conducting from Fig. 3.106b. In
this stage, the freewheeling current flows through S2 , S5 , D7 , D8 , and the filter. The
freewheeling circuit is disconnected with PV side and the LC loop is broken.
Mode 3: Refer to Fig. 3.107c; in this stage, the energy transfers from the PV side
to the grid through S3 , S4 , and the filter.
Mode 4: Refer to Fig. 3.107d; only S3 is conducting from Fig. 3.106b. In this
stage, the freewheeling current flows through S7 , S8 , D2 , D5 , and the filter. The
freewheeling circuit is disconnected with PV side and the LC loop is also cut off.
The working principles of clamping circuit are shown in Fig. 3.108. Clamping
mode when freewheeling circuit potential rises is shown in Fig. 3.108a. Clamping
mode when freewheeling circuit potential decreases is shown in Fig. 3.108b. In
freewheeling stages, LC will flow into DC side through D8 if its potential rises and it
will flow from DC side through D7 if its potential decreases. Thus, CMV is clamped
at half of DC input voltage. Besides, the working principles of clamping circuits
are different from clamping type TLIs discussed above according to Fig. 3.108.
The clamping circuit in TLIs above only used to clamp the freewheeling potential.
However, not only common mode current but also differential mode current flows
3.3 Full-Bridge TLIs with Clamping Branches 103

(a) (b)

Cdc1 S1 S4 D4 Cdc1 S1 S4 D4
D7 D1 LCM Zline1 iCM D1 LCM Zline1
Upv CY1 Upv D7 CY1
D2 D2
S7 ZG S7 ZG
S2 S5 iDM S2 S5 iDM
PV iCM PV
D8
D8 D5 CY2 Zline2 D5 CY2 Zline2

S8 S6 D6 S8 S6 D6
Cdc2 Cdc2
N S3 D3 N S3 D3

Fig. 3.108 Equivalent circuits when clamping circuit conducting in AH6-II, a potential rises,
b potential decreases

Table 3.24 DMV and CMV levels of different operating modes in AH6-II
Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 U pv /2
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 U pv /2

through clamping circuit in AH6-II. Thus, clamping circuit is part of differential mode
loop in AH6-II, and the current flows through four power switching components.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.24. From this table, it is clear that DMV maintains unipolar
performance. CMV of AH6-II is constant and has the perfect CMV performance.
In conclusion, two power switches S7 , S8 are introduced in AH6-II. The PV
and grid are disconnected during freewheeling stages in AH6-II. LC will decrease
due to the constant CMV. The current flows through four power switches in energy
transmission stage during positive grid cycle and two in negative cycle. It flows
through two power switches and two diodes in freewheeling stages during whole
grid period. The power loss may be higher compared to H6-D.
2. Simulation results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of AH6-II are shown in Table 3.4.
The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.109.
The simulation waveforms of DMV uDM in time domain and frequency domain
are shown in Fig. 3.110a, b, respectively. uDM is a three-level voltage and contains
little harmonics.
The simulation waveforms of CMV uCM in time domain and frequency domain are
shown in Fig. 3.111a, b, respectively. uCM contains no high-frequency components
and keeps constant.
104 3 Full-Bridge Transformerless PV Grid-Connected Inverters

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.109 Simulation waveforms of ug , iref , and ig of AH6-II

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.110 DMV waveforms of AH6-II, a time domain, b frequency domain

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:[50V/div]

0 t[5ms/div] 0
0Hz 18kHz 36kHz

Fig. 3.111 CMV waveforms of AH6-II, a time domain, b frequency domain

3.3 Full-Bridge TLIs with Clamping Branches 105

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[50mA/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.112 LC waveforms of AH6-II, a time domain, b frequency domain

The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.112a, b, respectively. From Fig. 3.112, the LC is about 0.3 mA at
switching frequency. It meets the standard and greatly reduced compared to H6-II.
Although CMV is constant in the DC side clamping TLIs and two active clamping
H6 TLIs, current flows through three or four power switches in energy transmission
stages. Power loss is increased obviously. On the contrary, current flows through
few power switches in AC side clamping TLIs based on HERIC. The high efficiency
characteristic is maintained. Thus, researchers have proposed many AC side clamping
TLIs [26–30].

3.3.7 Full-Bridge Zero-Voltage Rectifier Inverter

1. Operating principle

Full-bridge zero-voltage rectifier (FB-ZVR) [26] was proposed by T. Kerekes and

R. Teodorescu from Aalborg University in Denmark. Its main circuit is shown in
Fig. 3.113a. Power switch S5 /D5 and a rectifier Drect are added to AC side in FB-ZVR.
Besides, switch S5 is connected to the neutral point of DC side through D6 . Thus,
the clamping structure is composed of those components. The modulation strategy
is shown in Fig. 3.113b. S1 –S4 work in fundamental or high frequency depending on
the grid voltage. S5 works in high frequency. Dead time is needed between S5 and
S1 –S4 to avoid short circuit. Thus, the output voltage is the quasi-unipolar voltage.
There are six operating modes according to the directions of grid voltage and
grid-in current when FB-ZVR works in unity power factor, as shown in Fig. 3.114.
Figure 3.114a–c belongs to the positive grid cycle, while Fig. 3.114d–f belongs to
the negative grid cycle.
106 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
S1 S3 vM vtri

D1 D3 ωt
Upv Cdc1
1 L1
D6 S5 C ug S1, S4 ωt
Drect
PV S2, S3 ωt
D5 L2
Cdc2 S5 ωt
2
S4
S2 u12 ωt
N D2 D4

Fig. 3.113 Full-bridge zero voltage rectifier, a main circuit, b modulation strategy

Mode 1: Refer to Fig. 3.114a; in this stage, the energy transfers from the PV side
to the grid through S1 , S4 , and the filter. The operating principle is the same as in
conventional full-bridge TLI using unipolar SPWM modulation.
Mode 2: Refer to Fig. 3.114b; in this stage, the mode gets into the dead time.
Power switch S1 and S4 are closed, but switch S5 is not triggered. The current flows
through D2 , D3 , and the filter to DC side. Thus, the narrow reverse pulse will appear
in the output voltage.
Mode 3: Refer to Fig. 3.114c; S1 –S4 are all closed while S5 is conducting from
Fig. 3.113b. In this stage, the freewheeling current flows through S5 , Drect , and the
filter. The freewheeling circuit is disconnected with PV side completely and the LC
loop is broken. The potential of freewheeling circuit is clamped at constant because
it is connected to the neutral point of DC side by D6 . Besides, short circuit will not
happen because current can only flow through diode D6 .
Mode 4: Refer to Fig. 3.114d; in this stage, the energy transfers from the PV side
to the grid through S2 , S3 , and the filter. The operating principle is the same as in
conventional full-bridge TLI using unipolar SPWM modulation.
Mode 5: Refer to Fig. 3.114e; in this stage, the mode gets into the dead time. Power
S1 and S4 are closed, and switch S5 is not triggered. The current flows through D1 ,
D4 , and the filter to DC side. Thus, narrow reverse pulse will appear in the output
voltage.
Mode 6: Refer to Fig. 3.114f, S1 –S4 are all closed while S5 is conducting from
Fig. 3.113b. In this stage, the freewheeling current flows through S5 , Drect , and
the filter. The freewheeling circuit is disconnected with PV side. The potential of
freewheeling circuit is clamped at constant by D6 .
The working principles of clamping circuit are shown in Fig. 3.115. In free-
wheeling stages, LC will flow into DC side through S5 , Drect , and D6 if its potential
rises. Thus, CMV is clamped at half of DC input voltage. It is pointed out that CMV
is uncertain and cannot be clamped when freewheeling circuit potential decreases.
Thus, FB-ZVR is the unidirectional clamping TLI.
3.3 Full-Bridge TLIs with Clamping Branches 107

(a) (b)
S1 S3 S1 S3

D1 D3 iL1 ig D1 D3 iL1 ig
Upv Cdc1 L1 Upv Cdc1 L1
D6 S5 C ug D6 S5 C ug
Drect Drect
PV PV
D5 D5
Cdc2 L2 Cdc2 L2
S4 S4
S2 S2
N D2 D4 N D2 D4

(c) (d)
S1 S3 S1 S3

D1 D3 iL1 ig D1 D3 iL1 ig
Upv Cdc1 L1 Upv Cdc1 L1
D6 S5 C ug D6 S5 C ug
Drect Drect
PV PV
D5 D5
Cdc2 L2 Cdc2 L2
S4 S4
S2 S2
N D2 D4 N D2 D4

(e) (f)

S1 S3 S1 S3

D1 D3 iL1 ig D1 D3 iL1 ig
Upv Cdc1 L1 Upv Cdc1 L1
D6 S5 C ug D6 S5 C ug
Drect Drect
PV PV
D5 D5
Cdc2 L2 Cdc2 L2
S4 S4
S2 S2
N D2 D4 N D2 D4

Fig. 3.114 Equivalent circuits of operating modes of FB-ZVR, a mode 1, b mode 2, c mode 3,
d mode 4, e mode 5, f mode 6

Based on these modes, the potential of points 1 and 2 against N as well as uDM
and uCM is shown in Table 3.25. From this table, it is clear that DMV is the quasi-
unipolar SPWM voltage. CMV of FB-ZVR is constant except for the freewheeling
circuit potential decreases.
In conclusion, many components are introduced in FB-ZVR. The PV and grid
are disconnected during freewheeling stages in this TLI. CMV is clamped by D6
and LC will be reduced. The current flows through two power switches in power
108 3 Full-Bridge Transformerless PV Grid-Connected Inverters

Fig. 3.115 Equivalent

circuit when clamping circuit S1 S3
conducting in FB-ZVR
D1 D3 LCM Zline1
Upv Cdc1
CY1
D6 S5 ZG
iDM
PV
iCM
D5 CY2 Zline2
Cdc2
S4
S2
N D2 D4

Table 3.25 DMV and CMV of different operating modes in FB-ZVR

Modes u1N u2N uDM uCM
(1), (5) U pv 0 U pv U pv /2
(3) U pv /2 U pv /2 0 ≤U pv /2
(2), (4) 0 U pv −U pv U pv /2
(6) U pv /2 U pv /2 0 ≤U pv /2

transmission stages and one power switch with two diodes in freewheeling stages.
But, it can only clamp the CMV at U pv /2 when the freewheeling circuit rises.
2. Simulation results

A simulation model is built by Matlab/Simulink to verify the performance analysis

aforementioned, and the key parameters of FB-ZVR are shown in Table 3.4.
The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.116.
The simulation waveforms of DMV uDM in time domain and frequency domain
are shown in Fig. 3.117a, b, respectively. From this figure, it is clear that the reverse
pulse exists in the output voltage. uDM is the quasi-unipolar three-level voltage and
contains little harmonics. The RMS of uDM is about 75 V at switching frequency.
The simulation waveforms of CMV uCM in time domain and frequency domain
are shown in Fig. 3.118a, b, respectively. uCM only contains the components whose
amplitude is smaller than U pv /2, as discussed in Fig. 3.115.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.119a, b, respectively. From Fig. 3.119, the LC is about 10 mA at
switching frequency. It is greatly reduced compared to HERIC because components
whose amplitude higher than U pv /2 are removed.
3.3 Full-Bridge TLIs with Clamping Branches 109

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.116 Simulation waveforms of ug , iref , and ig of FB-ZVR

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:[200V/div]

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.117 DMV waveforms of FB-ZVR, a time domain, b frequency domain

(a) (b)

A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:[50V/div]

0 0
0Hz 18kHz 36kHz

Fig. 3.118 CMV waveforms of FB-ZVR, a time domain, b frequency domain

110 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[200mA/div]
0
0
50Hz 18kHz 36kHz

Fig. 3.119 LC waveforms of FB-ZVR, a time domain, b frequency domain

3.3.8 Diode Clamping Full-Bridge Zero-Voltage Rectifier

Inverter

1. Operating principle

The diode clamping full-bridge zero-voltage rectifier (FB-ZVR-D) inverter was

proposed in [27], whose main circuit is shown in Fig. 3.120a. Another diode is
added in FB-ZVR-D compared to FB-ZVR. FB-ZVR-D has bidirectional clamping
ability. The modulation strategy is shown in Fig. 3.120b. S5 works in high frequency.
S1 –S4 work in fundamental or high frequency depending on the grid voltage. Dead
time is also needed between S5 and S1 –S4 to avoid short circuit. Thus, the output
voltage is the quasi-unipolar voltage.
The modulation strategy and differential mode performance are similar to FB-
ZVR. In unity power factor, there are also six operating modes which can refer to
Fig. 3.114. However, the common-mode performance is improved. The CMV is
clamped bidirectional.

(a) (b)
S1 S3 vM vtri

D1 D3 ωt
1
Upv Cdc1 L1
S5 C ug S1, S4 ωt
D7
PV D6 S2, S3 ωt
D5
Cdc2 L2 S5 ωt
2
S4
S2 u12 ωt
N D2 D4

Fig. 3.120 Diode clamping full-bridge zero-voltage rectifier, a main circuit, b modulation strategy
3.3 Full-Bridge TLIs with Clamping Branches 111

(a) (b)

S1 S3 S1 S3
D1 D3 LCM Zline1 LCM Zline1
Upv D1 D3
Cdc1 Upv
CY1 Cdc1 CY1
S5 ZG iCM ZG
D7 iDM D7
D6 iDM
PV PV D6
iCM S5
D5 CY2 Zline2 D5 CY2 Zline2
Cdc2 Cdc2
S4 S4
S2 S2
N D2 D4 N D2 D4

Fig. 3.121 Equivalent circuits when clamping circuit conducting in FB-ZVR-D, a potential rises,
b potential decreases

The working principles of clamping circuit are shown in Fig. 3.121. The clamping
mode when freewheeling circuit potential rises is shown in Fig. 3.121a. The clamping
mode when freewheeling circuit potential decreases is shown in Fig. 3.121b. In
freewheeling stages, LC will flow into DC side through D6 if its potential rises and it
will flow from DC side through D7 if its potential decreases. Thus, CMV is clamped
at half of DC input voltage. The clamping ability is dependent on the properties of
the diode and CMV can still be clamped at constant during dead time.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.26. From this table, it is clear that the DMV maintains quasi-
unipolar SPWM performance. The CMV of FB-ZVR-D is constant. The common-
mode performance is optimal.
In conclusion, freewheeling and clamping structures are introduced in FB-ZVR-
D. The PV side and grid side are disconnected during freewheeling stages. CMV
is clamped at constant in all modes. The current flows through two power switches
in power transmission stages and one power switch and two diodes in freewheeling
stages, like FB-ZVR. But, the CMV is clamped at U pv /2 whenever the potential
freewheeling circuit rises or decreases.
2. Simulation results
A simulation model is built by Matlab/Simulink to verify the performance analysis
aforementioned, and the key parameters of FB-ZVR-D are shown in Table 3.4.

Table 3.26 DMV and CMV levels of different operating modes in FB-ZVR-D
Modes u1N u2N uDM uCM
(1), (5) U pv 0 U pv U pv /2
(3) U pv /2 U pv /2 0 U pv /2
(2), (4) 0 U pv −U pv U pv /2
(6) U pv /2 U pv /2 0 U pv /2
112 3 Full-Bridge Transformerless PV Grid-Connected Inverters

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.122 Simulation waveforms of ug , iref , and ig of FB-ZVR-D

The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.122.
The simulation waveforms of DMV uDM in time domain and frequency domain
are shown in Fig. 3.123a, b, respectively. From this figure, it is clear that reverse
pulse exists in the output voltage. uDM is a quasi-unipolar three-level voltage and
contains little harmonics. The RMS of uDM is about 75 V at switching frequency.
The simulation waveforms of CMV uCM in time domain and frequency domain are
shown in Fig. 3.124a, b, respectively. uCM is constant and only contains fundamental
component.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.125a, b, respectively. From Fig. 3.125, the LC is decreased to 0.3 mA
compared to 10 mA in FB-ZVR at switching frequency.

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:[200V/div]

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.123 DMV waveforms of FB-ZVR-D, a time domain, b frequency domain

3.3 Full-Bridge TLIs with Clamping Branches 113

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]
uCM:
[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.124 CMV waveforms of FB-ZVR-D, a time domain, b frequency domain

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[50mA/div]
0
0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.125 LC waveforms of FB-ZVR-D, a time domain, b frequency domain

3.3.9 HERIC with Tri-direction Clamping Cell Inverter

1. Operating principle

HERIC with tri-direction clamping cell (HERIC-TDCC) was proposed in [28], whose
main circuit is shown in Fig. 3.126a. A new power switch S7 is added to connect the
neutral point of DC input and output compared to HERIC. HERIC-TDCC is also an
AC side decoupling TLI. The modulation strategy is shown in Fig. 3.126b. S7 works
in high frequency. S1 –S6 work in fundamental or high frequency depending on the
grid voltage. Dead time is needed between S7 and S1 –S4 to avoid short circuit. The
output voltage is still three-level voltage.
The modulation strategy and differential mode performance are similar to HERIC.
In unity power factor, there are also four operating modes which can refer to Fig. 3.9.
However, the common-mode performance is improved. The CMV is clamped.
114 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
vM vtri
S1 S3
ωt
D1 D3
1 L1
Upv C S1, S4 ωt
dc1 D7 S5 D5 C ug
S2, S3 ωt
PV S5 ωt
S7 D6 S6
Cdc2 L2 S6 ωt
2
S4 S7 ωt
S2 u12 ωt
N D2 D4

Fig. 3.126 HERIC with tri-direction clamping cell inverter, a main circuit, b modulation strategy

(a) (b)

S1 S3 S1 S3

D1 D3 LCM Zline1 LCM Zline1

D1 D3
Cdc1 Upv
CY1 Cdc1 CY1
iCM D7 S5 D5 iCM S5 D5
ZG D7 ZG
iDM iDM
PV PV
S7 D6 S6 S7 D6 S6
Cdc2 CY2 Zline2 CY2 Zline2
Cdc2
S4 S4
S2 S2
N D2 D4 N D2 D4

Fig. 3.127 Equivalent circuits when clamping circuit conducting in HERIC-TDCC, a potential
rises, b potential decreases

The working principles of the clamping circuit are shown in Fig. 3.127. The
clamping mode when freewheeling circuit potential rises is shown in Fig. 3.127a.
The clamping mode when freewheeling circuit potential decreases is shown in
Fig. 3.127b. In freewheeling stages, LC will flow into DC side through S7 if its poten-
tial rises. LC will flow from DC side through D7 if its potential decreases. CMV is
clamped naturally. Furthermore, CMV cannot be clamped when freewheeling circuit
potential rises during dead time.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.27. From this table, it is clear that DMV maintains unipolar

Table 3.27 DMV and CMV of different operating modes in HERIC-TDCC

Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 U pv /2 (uncertain during dead time)
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 U pv /2 (uncertain during dead time)
3.3 Full-Bridge TLIs with Clamping Branches 115

SPWM performance. CMV of HERIC-TDCC is constant except for it during dead

time.
In conclusion, freewheeling and clamping structures are introduced at AC side
in HERIC-TDCC. The PV side and grid side are disconnected during freewheeling
stages. The output voltage is also unipolar three-level voltage. CMV is clamped at
constant in all modes except for dead time. The current flows through two power
switches in power transmission or freewheeling stages, like HERIC. Power loss is
decreased compared to FB-ZVR or FB-ZVR-D.
2. Simulation results
A simulation model is built by Matlab/Simulink to verify the performance analysis
aforementioned, and the key parameters of HERIC-TDCC are shown in Table 3.4.
The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.128.
The simulation waveforms of DMV uDM in time domain and frequency domain
are shown in Fig. 3.129a, b, respectively. uDM is a three-level voltage and contains
little harmonics. The RMS of uDM is about 75 V at switching frequency.
The simulation waveforms of CMV uCM in time domain and frequency domain are
shown in Fig. 3.130a, b, respectively. It contains the components that its amplitude
higher than U pv /2; this is because CMV is uncertain during the dead time between
power switches. While the amplitude of fundamental frequency pulses is lower than
U pv /2 also exists, this phenomenon is due to variable CMV when current crossing
zero, as discussed in Fig. 3.127.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.131a, b, respectively. From Fig. 3.131, the LC is about 4 mA at
switching frequency. LC is greatly reduced compared to HERIC.

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.128 Simulation waveforms of ug , iref , and ig of HERIC-TDCC

116 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.129 DMV waveforms of HERIC-TDCC, a time domain, b frequency domain

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.130 CMV waveforms of HERIC-TDCC, a time domain, b frequency domain

(a) (b)
A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[50mA/div]

0
0 t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.131 LC waveforms of HERIC-TDCC, a time domain, b frequency domain

3.3 Full-Bridge TLIs with Clamping Branches 117

3.3.10 Optimized HERIC Inverter

1. Operating principle

The optimized HERIC transformerless inverter (oHERIC) was proposed in [29],

whose main circuit is shown in Fig. 3.132a. Two new power switches S7 and S8 are
added to connect the neutral point of DC input and output compared to HERIC. The
oHERIC is AC side decoupling TLI. The modulation strategy is shown in Fig. 3.132b.
S7 and S8 work in high frequency. S1 –S6 work in fundamental or high frequency
depending on the grid voltage. Dead time is needed between S7 , S8 and S1 –S4 to
avoid short circuit. The output voltage is still three-level voltage.
The modulation strategy and differential mode performance are similar to HERIC.
In unity power factor, there are also four operating modes which can refer to Fig. 3.9.
However, the common-mode performance improved. The CMV is clamped. Dead
time is also needed at the switching scale.
The working principles of the clamping circuit are shown in Fig. 3.133. The
clamping mode when freewheeling circuit potential rises is shown in Fig. 3.133a.
The clamping mode when freewheeling circuit potential decreases is shown in
Fig. 3.133b. In freewheeling stages, LC will flow into DC side through S7 and D8 if

(a) (b)
vM vtri
S1 S3 ωt
Cdc1 D1 D3
1
Upv L1
D8 S7 S1, S4 ωt
S5 D5 C ug
S2, S3 ωt
PV S5 ωt
S8 D7 D6 S6
L2 S6 ωt
Cdc2 2 S7, S8 ωt
S2 S4 u12 ωt
N D2 D4

Fig. 3.132 Optimized HERIC transformerless inverter, a main circuit, b modulation strategy

(a) (b)

S1 S3 S1 S3
Cdc1 D1 D3 LCM Zline1 Cdc1 D1 D3 LCM Zline1
iCM CY1 iCM
Upv S7 Upv S7 CY1
D8 S5 D5 ZG D8 S5 D5 ZG
iDM iDM
PV PV
S8 D7 D6 S6 S8 D7 D6 S6
CY2 Zline2 CY2 Zline2
Cdc2 Cdc2
S2 S4 S2 S4
N D2 D4 N D2 D4

Fig. 3.133 Equivalent circuits when clamping circuit conducting in oHERIC, a potential rises,
b potential decreases
118 3 Full-Bridge Transformerless PV Grid-Connected Inverters

Table 3.28 DMV and CMV levels of different operating modes in oHERIC
Modes u1N u2N uDM uCM
(1) U pv 0 U pv U pv /2
(2) U pv /2 U pv /2 0 U pv /2 (uncertain during dead time)
(3) 0 U pv −U pv U pv /2
(4) U pv /2 U pv /2 0 U pv /2 (uncertain during dead time)

potential rises. LC will flow from DC side through S8 and D7 if its potential decreases.
Furthermore, CMV cannot be clamped during dead time.
Based on these modes, the potential of points 1 and 2 against N as well as uDM
and uCM is shown in Table 3.28. From this table, it is clear that DMV is a three-level
voltage. CMV of oHERIC is constant except for it during dead time.
In conclusion, freewheeling and clamping structures are introduced at the AC side
in oHERIC. The PV and grid are disconnected during the freewheeling stages. The
output voltage is also unipolar three-level voltage. CMV is clamped at constant in
all modes except for short dead time. It is more flexible using two clamping power
switches. The current flows through two power switches in power transmission or
freewheeling stages, like HERIC.
2. Experimental results
The working principles of oHERIC are the same as HERIC-TDCC. Only experi-
mental results are given for avoiding duplication. Simulation waveforms can refer to
Figs. 3.128, 3.129, 3.130, and 3.131. To verify the theoretical analysis, a prototype
of oHERIC is built, and the key parameters are shown in Table 3.29.
The prototype is shown in Fig. 3.134a. The experimental waveforms of ug , ig , and
DMV uDM are shown in Fig. 3.134b. From Fig. 3.134b, uDM is a unipolar three-level
voltage.
The experimental waveforms of ug , ig , u1N , u2N , uCM in the grid frequency scale are
shown in Fig. 3.135a. The experimental waveforms of uCM in positive and negative
grid cycles at switching frequency scales are shown in Fig. 3.135b and c, respectively.
In Fig. 3.135a, CMV is oscillating in large amplitude. This is because clamping
switches S7 and S8 are not triggered during current crossing zero range to commuting
reliable. The CMV oscillating is owing to the dead time in Fig. 3.135b, c. In other
time intervals, CMV is constant as the theoretical analysis above.

3.3.11 Full-Bridge with Constant Common-Mode Voltage

Inverter

Although CMV can be clamped in FB-ZVR and its improved structure, power loss in
freewheeling is improved because conducting components are increasing from two to
three components. In HERIC-TDCC and oHERIC, the cost is also increased for using
3.3 Full-Bridge TLIs with Clamping Branches 119

Table 3.29 Key parameters of oHERIC prototype

Parameters Value Parameters Value
Input voltage 400 Diodes D5 , D6 IDD12SG60C
U pv /V
Grid voltage 220, 50 Filter inductors 0.5
ug /V, Hz L 1 , L 2 /mH
Rated power P/W 1000 Filter capacitor 2.2
C/µF
Switching 20 Common-mode 2 × B82726-S6223-N40
frequency f s /kHz inductor L CM
DC side 470µF/350 V Inductor L CM L: 2 × 1.6
capacitors C dc1 , value/mH
C dc2 /µF
IGBT S5 , S6 IRG4BC30S-S Turns Turns: 11 + 11
MOSFET S1 –S4 FZ06BIA070FS-P894E-14 Common-mode 22
capacitor C Y1 ,
C Y2 /nF
MOSFET S7 , S8 FQB5N50C PV parasitic 0.1
capacitor C pv1 ,
C pv2 /µF

(a) (b)
Capacitor Freewheeling Clamping
Balancing divider switches switches
circuit ig:[5A/div] ug:[200V/div]

uDM:[200V/div]

Fig. 3.134 oHERIC prototype and DMV waveforms, a oHERIC prototype, b DMV waveforms of
oHERIC

more active power switches. Besides, CMV cannot be clamped during dead time.
Thus, researchers proposed a TLI based on HERIC while CMV is clamped only using
diodes, which is called full-bridge inverter topology with constant common-mode
voltage (FB-CCV) [30].
1. Operating principle
The FB-CCV was proposed in [30], whose main circuit is shown in Fig. 3.136a.
Two diodes D7 and D8 are added based on Fig. 3.71c. D7 and D8 connect the neutral
point of DC side and S5 and S6 , respectively. The modulation strategy is shown
in Fig. 3.136b. S5 –S6 work in high frequency. The output voltage is a three-level
120 3 Full-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
ug:[200V/div]
ig:[5A/div] ug:[200V/div]
ig:[5A/div] u1N:[200V/div]
u1N:[200V/div]
2uCM:[200V/div] 2uCM:[200V/div]

u2N:[200V/div]
u2N:[200V/div]

(c)

ig:[5A/div]

ug:[200V/div]
u1N:[200V/div]
2uCM:[200V/div]

u2N:[200V/div]

Fig. 3.135 CMV waveforms of oHERIC, a grid frequency scale, b positive (switching frequency
scale), c negative (switching frequency scale)

(a) (b)
S1 S3 vM vtri
ωt
D1 D3
Upv L1
Cdc1 1
S5
D7 S6 C ug S1, S4 ωt
PV S2, S3 ωt
D8 D5 D6 S5, S6
Cdc2 L2
2 ωt
S4
S2 u12 ωt
N D2 D4

Fig. 3.136 Full-bridge with constant common-mode voltage inverter, a main circuit, b modulation
strategy

unipolar voltage. But actually, dead time is needed between S5 , S6 , and S1 –S4 . Thus,
the output voltage u12 is quasi-unipolar three-level voltage, as shown in Fig. 3.136b.
There are six operating modes based on the directions of grid voltage and grid-
in current when FB-CCV works in unity power factor, as shown in Fig. 3.137.
Figure 3.137a–c belongs to the positive grid cycle, while Fig. 3.137d–f belongs
to the negative grid cycle.
Mode 1: Refer to Fig. 3.137a; in this stage, the energy transfers from the PV
side to the grid through S1 , S4 , and the filter. The operating principle is the same as
HERIC.
Mode 2: Refer to Fig. 3.137b; in this stage, the mode gets into the dead time.
Power S1 and S4 are closed, and switches S5 and S6 are not triggered. The current
3.3 Full-Bridge TLIs with Clamping Branches 121

(a) (b)
S1 S3 S1 S3

D1 D3 iL1 ig D1 D3 iL1 ig
Upv L1 Upv L1
Cdc1 Cdc1
S5 S5
D7 S6 C ug D7 S6 C ug
PV PV
D8 D5 D6 D8 D5 D6
Cdc2 L2 Cdc2 L2
S4 S4
S2 S2
N D2 D4 N D2 D4

(c) (d)

S1 S3 S1 S3

D1 D3 iL1 ig D1 D3 iL1 ig
Upv L1 Upv L1
Cdc1 Cdc1
S5 S5
D7 S6 C ug D7 S6 C ug
PV PV
D8 D5 D6 D8 D5 D6
Cdc2 L2 Cdc2 L2
S4 S4
S2 S2
N D2 D4 N D2 D4

(e) (f)
S1 S3 S1 S3

D1 D3 iL1 ig D1 D3 iL1 ig
Upv L1 Upv L1
Cdc1 Cdc1
S5 S5
D7 S6 C ug D7 S6 C ug
PV PV
D8 D5 D6 D8 D5 D6
Cdc2 L2 Cdc2 L2
S4 S4
S2 S2
N D2 D4 N D2 D4

Fig. 3.137 Equivalent circuits of operating modes of FB-CCV, a mode 1, b mode 2, c mode 3,
d mode 4, e mode 5, f mode 6

flows through D2 , D3 , and the filter to DC side. Thus, the narrow reverse pulse will
appear in the output voltage.
Mode 3: Refer to Fig. 3.137c; S1 –S4 are all closed while S5 and S6 are conducting
from Fig. 3.136b. In this stage, the freewheeling current flows through S6 , D6 , and
the filter. The freewheeling circuit is disconnected with PV side completely and the
LC loop is cut off.
Mode 4: Refer to Fig. 3.137d; in this stage, the energy transfers from the PV side
to the grid through S2 , S3 , and the filter. The operating principle is the same as in
conventional full-bridge TLI.
122 3 Full-Bridge Transformerless PV Grid-Connected Inverters

Mode 5: Refer to Fig. 3.137e; in this stage, the mode gets into the dead time
stage. Power S1 and S4 are closed, and switches S5 and S6 are not triggered. The
current flows through D1 , D4 , and the filter to DC side. Thus, narrow reverse pulse
will appear in the output voltage.
Mode 6: Refer to Fig. 3.137f; S1 –S4 are all closed while S5 and S6 are conducting
from Fig. 3.136b. In this stage, the freewheeling current flows through S5 , D5 , and
the filter. The freewheeling circuit is disconnected with PV side and the LC loop
is broken compared to conventional full-bridge TLI. The potential of freewheeling
circuit is clamped at constant by diodes naturally.
The working principles of clamping circuit are shown in Fig. 3.138. The clamping
mode when freewheeling circuit potential rises is shown in Fig. 3.138a. The clamping
mode when freewheeling circuit potential decreases is shown in Fig. 3.138b. In
freewheeling stages, LC will flow into DC side through D7 if its potential rises and it
will flow from DC side through D8 if its potential decreases. Thus, CMV is clamped
at half of DC input voltage. The clamping ability is dependent on the properties of
the diode.
Based on these modes, the potential of points 1 and 2 against N as well as uDM and
uCM is shown in Table 3.30. From this table, it is clear that DC side and AC side are
disconnected in both Mode 3 and Mode 6. DMV is a quasi-unipolar voltage. CMV
of FB-CCV is constant. It has perfect CMV performance.
In conclusion, freewheeling and clamping structures are introduced at AC side in
FB-CCV. The PV side and grid side are disconnected during freewheeling stages.
CMV is clamped naturally at constant in all modes, avoiding uncertain state during

(a) (b)

S1 S3 S1 S3

D1 D3 LCM Zline1 D1 D3 LCM Zline1

Upv Cdc1 CY1 Upv Cdc1 CY1
iCM S5 iCM S5
D7 S6 ZG D7 S6 ZG
iDM iDM
PV PV
D8 D5 D6 CY2 Zline2 D8 D5 D6 CY2 Zline2
Cdc2 Cdc2
S4 S4
S2 S2
N D2 D4 N D2 D4

Fig. 3.138 Equivalent circuits when clamping circuit conducting in FB-CCV, a potential rises,
b potential decreases

Table 3.30 DMV and CMV of different operating modes in FB-CCV

Modes u1N u2N uDM uCM
(1), (5) U pv 0 U pv U pv /2
(3) U pv /2 U pv /2 0 U pv /2
(2), (4) 0 U pv −U pv U pv /2
(6) U pv /2 U pv /2 0 U pv /2
3.3 Full-Bridge TLIs with Clamping Branches 123

dead time in active clamping TLIs. The current flows through two power switches
in power transmission stages and one power switch with two diodes in freewheeling
stages. The CMV is clamped at U pv /2 whenever the potential freewheeling circuit
rises or decreases.
2. Simulation results
A simulation model is built by Matlab/Simulink to verify the performance analysis
aforementioned, and the key parameters of FB-CCV are shown in Table 3.4.
The simulation waveforms of ug , grid-in current reference iref , and grid-in current
ig are shown in Fig. 3.139.
The simulation waveforms of DMV uDM in time domain and frequency domain
are shown in Fig. 3.140a, b, respectively. From these figures, it is clear that reverse
pulse exists in the output voltage. uDM is the quasi-unipolar three-level voltage and
the switching frequency components are the same with unipolar three-level voltage.
Besides, dead time is not needed and eliminating CMV oscillation in active clamping
TLIs.

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 3.139 Simulation waveforms of ug , iref , and ig of FB-CCV

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:[200V/div]

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.140 DMV waveforms of FB-CCV, a time domain, b frequency domain

124 3 Full-Bridge Transformerless PV Grid-Connected Inverters

The simulation waveforms of CMV uCM in time domain and frequency domain are
shown in Fig. 3.141a, b, respectively. uCM is constant and only contains fundamental
component.
The simulation waveforms of LC iCM in time domain and frequency domain are
shown in Fig. 3.142a, b, respectively. From Fig. 3.142, it was observed that the
LC decreased to 0.2 mA at switching frequency. It decreased greatly compared to
HERIC.
3. Experimental results
In order to verify the theoretical analysis and simulation waveforms, a prototype of
FB-CCV is built, and the key parameters are shown in Table 3.31.
The experimental waveforms of ug , ig , and uCM in grid frequency and switching
frequency scale are shown in Fig. 3.143a, b, respectively. From Fig. 3.143, DMV is
quasi-unipolar three-level voltage due to dead time between S5 , S6 and S1 –S4 . The
grid voltage ug , grid current ig , voltage u1N of midpoint 1 to terminal N, common-
mode voltage uCM = u1N + u2N , and voltage u2N of middle point 2 to terminal N in grid

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM:[50V/div]

0
0 t[5ms/div] 0Hz 18kHz 36kHz

Fig. 3.141 CMV waveforms of FB-CCV, a time domain, b frequency domain

(a) (b)

A[5mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[50mA/div]
0
0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 3.142 LC waveforms of FB-CCV, a time domain, b frequency domain

3.3 Full-Bridge TLIs with Clamping Branches 125

Table 3.31 Key parameters of FB-CCV prototype

Parameters Value Parameters Value
Input voltage U pv /V 400 Freewheeling diodes APT60DQ60B
Grid voltage ug /V 220 Clamping diodes IDP08E65D1
Grid frequency/Hz 50 Filter inductors L 1 , 0.5
L 2 /mH
Rated power P/W 5000 Filter capacitor C/µF 2
Switching frequency 20 Common-mode 2 × B82726-S6223-N40
f s /kHz inductor L CM
DC side capacitors C dc1 , 470 µF/350 V Inductor value/mH L: 2 × 1.6 mH
C dc2 /µF
IGBT IKW75N60T Turns Turns: 11 + 11
MOSFET IPW65R019C7 Common-mode 22
capacitor C Y1 , C Y2 /nF
CoolMOSFET SPW47N60C3 PV parasitic capacitor 0.1
C pv1 , C pv2 /µF

(a) (b)
ig:[5A/div]
uGS1 :[10V/div]
uGS5 :[10V/div]
ug:[200V/div]
ig:[2.5A/div]
uDM :[400V/div]
uDM:[200V/div]

Fig. 3.143 Experimental waveforms of DMV in FB-CCV, a grid frequency scale, b switching
frequency scale

(a) (b)
ig:[5A/div] ug:[200V/div]
ug:[200V/div] iL:[2.5A/div] u1N :[200V/div]
u1N:[200V/div]
2uCM:[200V/div] 2u CM :[200V/div]

u2N :[200V/div]
u2N:[200V/div]

Fig. 3.144 Experimental waveforms of CMV in FB-CCV, a grid frequency scale, b switching
frequency scale

frequency and switching frequency scale are shown in Fig. 3.144a, b, respectively.
From Fig. 3.144, CMV is constant and in accordance to theoretical analysis.
126 3 Full-Bridge Transformerless PV Grid-Connected Inverters

3.4 Summary

Various full-bridge TLIs are analyzed in this chapter. It can be classified as decou-
pling and clamping categories. Besides, it can also be classified as AC side or DC
side decoupling type TLIs. Clamping conception is designed to improve the CMV
performance of full-bridge TLIs. Unidirectional and bidirectional clamping TLIs
are two types based on clamping conception. Moreover, it can also be classified
as active clamping or passive clamping TLIs based on the components used in the
clamping circuit. Table 3.32 is the comparison of DMV and CMV performance of
TLIs analyzed above and can also be used as the guidelines when choosing the proper
TLIs.

Table 3.32 DMV and CMV performance of full-bridge TLIs

Topologies DMV CMV
Decoupling AC side HERIC [1] Unipolar Uncertain when
freewheeling
H6-I [5] Unipolar Uncertain when
freewheeling
H6-II [7] Unipolar Uncertain when
freewheeling
H6-III [8] Unipolar Uncertain when
freewheeling
HERTLI [17] Unipolar Uncertain when
freewheeling
DC side H5 [4] Unipolar Uncertain when
freewheeling
H6-IV [12] Unipolar Uncertain when
freewheeling
H6-V [13] Unipolar Uncertain when
freewheeling
Clamping Unidirectional H5-D [22] Unipolar ≤U pv /2
FB-ZVR [26] Quasi-unipolar ≤U pv /2
Bidirectional oH5 [21] Unipolar Uncertain during
dead time
H6-D [23] Unipolar Constant
AH6-I [24] Unipolar Uncertain during
dead time
AH6-II [25] Unipolar Constant
FB-ZVR-D [27] Quasi-unipolar Constant
HERIC-TDCC [28] Unipolar Uncertain during
dead time
oHERIC [29] Unipolar Uncertain during
dead time
FB-CCV [30] Quasi-unipolar Constant
References 127

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29(6):3122–3132
Chapter 4
Half-Bridge Transformerless PV
Grid-Connected Inverters

Abstract Rule 1 for eliminating leakage current of full-bridge TLIs has been
discussed in Chap. 3. In this chapter, Rule 2 to eliminate leakage current of half-
bridge TLIs will be discussed in detail. Because the neutral line of the grid is
directly connected to the midpoint of DC side, the inductor of output AC filter is
asymmetrically placed. Therefore, the total CMV keeps constant.

Keywords Transformerless PV grid-connected inverter · Half-bridge ·

Three-level · Loss distribution

4.1 Conventional Half-Bridge TLI

A conventional single-phase two-level half-bridge inverter circuit is shown in

Fig. 4.1a, U pv is the output voltage of PV arrays, C dc1 and C dc2 are the DC voltage
dividing capacitors, S1 and S2 represent power switches, and ug is the grid voltage.
Different from the full-bridge inverter circuit, the filter inductor L is only placed in
live wire of the grid, so it is an asymmetric structure. L and C represent inductor and
capacitor of the AC filter, respectively. Modulation strategy is shown in Fig. 4.1b,
where u12 is the output voltage.
When half-bridge inverter works with unity power factor, four operating modes
are shown in Fig. 4.2 according to the polarities of the grid voltage and grid-in current.
According to the definitions of DMV uDM and CMV uCM (referring to (2.1), (2.2)),
and uCM_tot (referring to (2.14)) in Chap. 2, uCM-DM and uCM_tot are relisted in (4.1)
and (4.2) for convenience of reading.
u DM
u CM−DM = − (4.1)
2
u DM u PN
u CM_tot = u CM + u CM−DM = u CM − = (4.2)
2 2

© The Editor(s) (if applicable) and The Author(s), under exclusive license 129
to Springer Nature Singapore Pte Ltd. 2021
H. Xiao and X. Wang, Transformerless Photovoltaic Grid-Connected Inverters,
CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-8525-8_4
130 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
vM vtri

S1 ωt
Cdc1 D1
Upv
1 L ug
S1
C ωt
PV 2 S2
ωt
Cdc2 S2 u12
N D2 ωt

Fig. 4.1 Conventional two-level half-bridge TLI, a Main circuit, b Modulation strategy

(a) (b)

S1 S1
Cdc1 Cdc1
D1 ig D1 ig
Upv Upv
iL1 L iL1 L
C ug C ug
PV PV

Cdc2 S2 Cdc2 S2
N D2 N D2

(c) (d)

S1 S1
Cdc1 D1 Cdc1 D1
ig ig
Upv Upv
iL1 L iL1 L
C ug C ug
PV PV

Cdc2 S2 Cdc2 S2
N D2 N D2

Fig. 4.2 Equivalent circuits of operating modes of bipolar SPWM modulation, a Mode 1, b Mode
2, c Mode 3, d Mode 4

Based on the operating modes, the potentials of points 1 and 2 against N, as

well as DMV and CMV are shown in Table 4.1. It can be seen that DMV is a two-
level voltage, and CMV is a constant value. As discussed in Chap. 3, the constant
CMV characteristic is perfect for TLI applications, but two-level DMV characteristic
4.1 Conventional Half-Bridge TLI 131

Table 4.1 DMV and CMV levels at different working stages with bipolar SPWM
Modes u1N u2N uDM uCM uCM-DM uCM_tot
(1) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(3) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(4) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2

has the disadvantages of abundant output harmonics and low conversion efficiency.
Therefore, the combination of three-level DMV and constant CMV is developing
direction of half-bridge TLIs.

4.2 I-Type Half-Bridge TLIs

I-type half-bridge TLIs mainly include neutral point clamping inverter (NPC) and
its improved topologies. NPC was first proposed by Japanese scholars Akira Nabae,
Isao Takahashi, and Hirofumi Akagi in 1981 [1], which was used by Danfoss Solar
in TripleLynx series products (three-phase TLIs rated at about 10/12.5/15 kW).
According to the report of Photon Magazine in July 2010, the European efficiency
is 97%, and the peak efficiency is 98%.

4.2.1 NPC Inverter

1. Operating principle

The main circuit of NPC grid-connected inverter is shown in Fig. 4.3a [1]. Compared
with the conventional half-bridge circuit, two active switch combinations S2 /D2 and
S3 /D3 and two clamping diodes D5 and D6 are added. At the same time, the diodes
are connected to the midpoint of the capacitor bridge to guarantee that the voltage
stress of all power devices is reduced to half of the input voltage. In this circuit, a
positive voltage level is obtained when switches S1 and S2 are on; a zero voltage
is outputted while switches S2 and S3 are on; when switches S3 and S4 are on, the
inverter outputs a negative voltage level.
There are four operating modes according to the polarities of the grid voltage
and grid current when the power factor is 1, as shown in Fig. 4.4. Mode 1 and
Mode 2 in Fig. 4.4a, b, respectively, work in positive half period of the grid voltage;
symmetrically, Mode 3 and Mode 4 in Fig. 4.4c, d work in negative half period of
the grid voltage.
Mode 1: Refer to Fig. 4.4a; the energy is delivered from the PV side into the grid
through S1 , S2 , and the AC filter at this stage. The switches S3 and S4 are off, and
132 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
vM vtri
S1 D1
Cdc1 ωt

Upv D5
S2 D2
2 S1 ωt
1 ωt
PV L1 S2
S3 D3 ug S3 ωt
D6
S4 ωt
Cdc2 S4 D4 u12 ωt
N

Fig. 4.3 NPC grid-connected inverter, a Main circuit, b Modulation strategy

(a) (b)

S1 D1 S1 D1
Cdc1 Cdc1

Upv D5 Upv D5
S2 D2 S2 D2

PV iL1 L1 ig PV iL1 L1 ig
S3 D3 ug S3 D3 ug
D6 D6

Cdc1 S4 D4 Cdc1 S4 D4
N N

(c) (d)

S1 D1 S1 D1
Cdc1 Cdc1

Upv D5 Upv D5
S2 D2 S2 D2

PV iL1 L1 ig PV iL1 L1 ig
S3 D3 ug S3 D3 ug
D6 D6

Cdc1 S4 D4 Cdc1 S4 D4
N N

Fig. 4.4 Equivalent circuits of operating modes of NPC, a Mode 1, b Mode 2, c Mode 3, d Mode
4
4.2 I-Type Half-Bridge TLIs 133

share the input voltage U pv in series, so their turn-off voltage stress is half of the
input voltage due to the existence of clamping diode D6 .
Mode 2: Refer to Fig. 4.4b; only S2 is on and rest of the switches are off according
to Fig. 4.3b. At this stage, the freewheeling current flows through D5 , S2 , and the filter,
and keeps feeding the grid. It is worth noting that the potential of the freewheeling
path is clamped at the ground.
Mode 3: Refer to Fig. 4.4c; the energy is delivered from the PV side into the grid
through S3 , S4 , and the AC filter at this stage. The switches S1 and S2 are off, and
evenly share the input voltage U pv because of clamping diode D5 .
Mode 4: Refer to Fig. 4.4d; only S3 is on and rest of the switches are off according
to Fig. 4.3b. At this stage, the freewheeling current flows through D6 , S3 , and the
filter, and keeps feeding the grid. At the same time, the potential of the freewheeling
path is clamped at the ground.
According to the aforementioned analysis of operating modes, the potentials of
points 1 and 2 against N as well as related to DMV and CMV are shown in Table 4.2. It
can be seen that the output voltage uDM is a three-level voltage with unipolar SPWM,
and the total CMV uCM_tot remains constant. As a result, NPC inverter can be adopted
in distributed TLI-PVPG system with low LC and high efficiency. Besides, the circuit
structure of NPC can block the DC component in the grid-in current, and this issue
will be further discussed in Chap. 6.
2. Simulation results

In order to verify the aforementioned analysis, a simulation model of NPC grid-

connected inverter is established in Matlab/Simulink, and the key parameters are
listed in Table 4.3.

Table 4.2 DMV and CMV levels of different operating modes for NPC
Modes u1N u2N uDM uCM uCM-DM uCM_tot
(1) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(3) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(4) U pv /2 U pv /2 0 U pv /2 0 U pv /2

Table 4.3 Key parameters of NPC

Parameters Value Parameters Value
Input voltage U pv /V 720 Switching frequency f s /kHz 18
Grid voltage ug /V, frequency/Hz 220/50 Filter inductor L 1 /mH 1.72
Rated power P/W 3000 Parasitic capacitance of PV panel 300
C pv /nF
134 4 Half-Bridge Transformerless PV Grid-Connected Inverters

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 4.5 Simulation waveforms of ug , iref , and ig of NPC

When the NPC operates with unity power factor, the steady-state waveforms of
the grid voltage ug , reference signal of grid-in current iref , and actual grid-in current
ig are shown in Fig. 4.5.
The simulation waveforms of DMV uDM in time domain and frequency domain
are shown in Fig. 4.6a, b, respectively. It can be observed that the RMS of DMV is
about 75 V at switching frequency, which is equivalent to unipolar SPWM full-bridge
(referring to Fig. 3.5b in Chap 3).
The simulation waveforms of total CMV uCM_tot in time domain and frequency
domain are shown in Fig. 4.7a, b, respectively. It can be observed that the amplitude
of CMV is zero at switching frequency, but the DC component of CMV is signifi-
cant, and the simulation waveforms are in accordance with theoretical analysis. The
simulation waveforms of LC iCM in time domain and frequency domain are shown in
Fig. 4.8a, b, respectively. It is outstanding that no LC appears among whole frequency
span. It proves that the DC component of CMV does not induce LC.

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]

uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 4.6 DMV waveforms of NPC, a Time domain, b Frequency domain

4.2 I-Type Half-Bridge TLIs 135

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM_tot:[100V/div]

0 0
t[5ms/div] 0Hz 18kHz 36kHz

Fig. 4.7 CMV waveforms of NPC, a Time domain, b Frequency domain

(a) (b)
A[20mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[20mA/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 4.8 LC waveforms of NPC, a Time domain, b Frequency domain

3. Experimental results

In order to further verify the effectiveness of operating principle and simulation

waveforms, a grid-connected experimental platform with NPC is established in lab,
and the key component parameters are shown in Table 4.4.
The experimental waveforms of the grid voltage ug , grid-in current ig , bridge
voltages u1N and u2N are shown in Fig. 4.9. It can be seen that the middle point
voltage of input capacitors u2N has a line-frequency fluctuation because of output
power pulse, and it is consistent with the practice.
The waveforms of the LC iCM are shown in Fig. 4.10. It is necessary to point out
that the PV output was simulated by using a DC source with solar array simulation in
this experiment, and this is the reason that some LC components appear in Fig. 4.10a
when the circuit breaker is closed and the NPC inverter has not started yet. After the
NPC inverter starts working to deliver the energy into the grid, a new LC component
appears in Fig. 4.10b, and its frequency is the switching frequency of the NPC inverter
136 4 Half-Bridge Transformerless PV Grid-Connected Inverters

Table 4.4 Key parameters of NPC prototype

Parameters Value Parameters Value
Input voltage U pv /V 800 Filter inductor L 1 /mH 8
Grid voltage ug /V, 240, 50 Common-mode inductor L CM 2 × 2 W-43615-TC
frequency/Hz
Rated power P/W 1000 Wire diameter 2 mm
Switching frequency 20 Number of turns 10 + 10
f s /kHz
Capacitance of DC 235 μF/400 V Common-mode capacitor 2.2
side C Y1 , C Y2 /nF
C dc1 , C dc2 /μF
Switches S1 –S2 IXFN36N100 Parasitic capacitance of PV 0.1
panel C pv1 , C pv2 /μF

Fig. 4.9 Output voltage

waveforms of NPC
ig:[16.7A/div]

ug:[200V/div]

u2N:[400V/div]

u1N:[400V/div]

(i.e., 20 kHz). By equivalent calculation, the value of LC is about 1 mA, which meets
the limitation of DIN VDE 0126-1-1 and NB/T 32004-2013 of 30 mA.

4.2.2 Active NPC Inverter

The aforementioned NPC inverter features high efficiency as well as low LC and DC
current in the grid-in current, but the active switches in the bridge arm have uneven
loss distribution, and this will jeopardize the reliability of distributed PVPG system.
In order to solve this issue, active neutral point clamped three-level inverter (A-NPC)
is proposed.
4.2 I-Type Half-Bridge TLIs 137

(a) (b)

ig:[16.7A/div] ig:[16.7A/div]

ug:[200V/div] ug:[200V/div]

i50Hz iCM:[80mA/div] i50Hz iCM:[80mA/div]

i18kHz i18kHz i20kHz

Fig. 4.10 LC waveforms of NPC, a NPC inverter not working, b NPC inverter working

1. Operating principle

Compared with NPC, the diodes of A-NPC are replaced by active switches S5 /D5
and S6 /D6 to realize active clamping, as shown in Fig. 4.11a. The voltage of neutral
point is clamped when upper switches S2 and S5 are on, as well as the case that lower
switches S3 and S6 are on. And thus the freewheeling current flows through the upper
clamp branch or the lower clamp branch. A variety of modulation strategies can be
adopted in A-NPC [3–6], among which two conventional modulation strategies are
discussed in this book, as shown in Fig. 4.11b, c.
There are four operating modes according to the polarities of the grid voltage and
grid current when A-NPC works in unity power factor case with modulation strategy
I, as shown in Fig. 4.12. Mode 1 and Mode 2 in Fig. 4.12a, b, respectively, work in
positive half period of the grid voltage; symmetrically, Mode 3 and Mode 4 work in
negative half period of the grid voltage.
Mode 1: Refer to Fig. 4.12a; the energy is delivered from the PV side into the
grid through S1 , S2 , and the AC filter. The output voltage of the bridge is U pv /2 at
this stage.
Mode 2: Refer to Fig. 4.12b; S1 , S6 are on and rest of the switches are off according
to Fig. 4.11b. The freewheeling current flows through S6 , D3 , and the filter, and keeps
feeding the grid at this stage. It is worth noting that the potential of the freewheeling
path is clamped at the ground.
Mode 3: Refer to Fig. 4.12c; the energy is delivered from the PV side into the grid
through S3 , S4 , and the AC filter. The output voltage of the bridge is −U pv /2 at this
stage.
Mode 4: Refer to Fig. 4.12d; S2 , S5 are on and rest of the switches are off according
to Fig. 4.11b. Consequently, the freewheeling current flows through S5 , D2 , and the
filter at this stage. It is worth noting that the potential of the freewheeling path is
clamped at the ground.
138 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a)
S1
Cdc1
D1

Upv S5 S2
2 D5 D2
1
PV L
S6 S3
D3 ug
D6

Cdc2 S4 D4
N
(b) (c)
vM vr1 vr2
vM vtri
ωt
ωt

S1 ωt S1 ωt
S2 ωt S2 ωt
S3 ωt S3 ωt
S4 ωt S4 ωt
S5 ωt S5 ωt
S6 ωt S6 ωt
u12 ωt u12 ωt

Fig. 4.11 Acitve neutral point clamping inverter, a Main circuit, b Modulation strategy I,
c Modulation strategy II

Based on the operating modes, the potentials of points 1 and 2 against N, as well
as DMV and CMV are shown in Table 4.5. Different from operating characteristics
of NPC, it can be noticed that opposite clamping branch in the freewheeling stage
will optimize the distribution of switching loss. Subsequently, the operating modes
of A-NPC with modulation strategy II will be discussed.
There are six operating modes according to the polarities of the grid voltage and
grid current when A-NPC works in unity power factor case with modulation strategy
II, as shown in Fig. 4.13. Mode 1, Mode 2, and Mode 3 in Fig. 4.13a–c, respectively,
work in positive half period of the grid voltage; symmetrically, Mode 3, Mode 4,
4.2 I-Type Half-Bridge TLIs 139

(a) (b)

S1 S1
Cdc1 Cdc1
D1 D1

Upv S5 S2 Upv S5 S2
D5 D2 D5 D2
PV iL L ig PV iL L ig
S6 S3 S6 S3
D3 ug D3 ug
D6 D6

Cdc2 S4 D4 Cdc2 S4 D4
N N

(c) (d)

S1 S1
Cdc1 Cdc1
D1 D1

Upv S5 S2 Upv S5 S2
D5 D2 D5 D2
PV iL L ig PV iL L ig
S6 S3 S6 S3
D3 ug D3 ug
D6 D6

Cdc2 S4 D4 Cdc2 S4 D4
N N

Fig. 4.12 Equivalent circuits of operating modes of A-NPC with modulation strategy I, a Mode 1,
b Mode 2, c Mode 3, d Mode 4

Table 4.5 DMV and CMV levels of different operating modes for A-NPC with modulation strategy
I
Modes u1N u2N uDM uCM uCM-DM uCM_tot
(1) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(3) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(4) U pv /2 U pv /2 0 U pv /2 0 U pv /2

and Mode 5 in Fig. 4.13d–f, respectively, work in negative half period of the grid
voltage.
Mode 1: Refer to Fig. 4.13a; S2 , S5 are on and rest of the switches are off according
to Fig. 4.11c. At this stage, the freewheeling current flows through D5 , S2 , and the
filter, and keeps feeding the grid. At the same time, the potential of the freewheeling
path is clamped at the ground.
140 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

S1 S1
Cdc1 Cdc1
D1 D1

Upv S5 S2 Upv S5 S2
D5 D2 D5 D2
PV iL L ig PV iL L ig
S6 S3 S6 S3
D3 ug D3 ug
D6 D6

Cdc2 S4 D4 Cdc2 S4 D4
N N

(c) (d)

S1 S1
Cdc1 Cdc1
D1 D1

Upv S5 S2 Upv S5 S2
D5 D2 D5 D2
PV iL L ig PV iL L ig
S6 S3 S6 S3
D3 ug D3 ug
D6 D6

Cdc2 S4 D4 Cdc2 S4 D4
N N

(e) (f)

S1 S1
Cdc1 Cdc1
D1 D1

Upv S5 S2 Upv S5 S2
D5 D2 D5 D2
PV iL L ig PV iL L ig
S6 S3 S6 S3
D3 ug D3 ug
D6 D6

Cdc2 S4 D4 Cdc2 S4 D4
N N

Fig. 4.13 Equivalent circuits of operating modes of A-NPC with modulation strategy II, a Mode
1, b Mode 2, c Mode 3, d Mode 4, e Mode 5, f Mode 6
4.2 I-Type Half-Bridge TLIs 141

Mode 2: Refer to Fig. 4.13b; the energy is delivered from the PV side into the
grid through S1 , S2 , and the AC filter at this stage. The switches S3 and S4 are off
according to Fig. 4.11c, and share the input voltage U pv in series, so their turn-off
voltage stress is half of the input voltage.
Mode 3: Refer to Fig. 4.13c; S1 , S3 , S6 are on and rest of the switches are off
according to Fig. 4.11c. At this stage, the freewheeling current flows through S6 ,
D3 , and the filter, and keeps feeding the grid. At the same time, the potential of the
freewheeling path is also clamped at the ground.
Mode 4: Refer to Fig. 4.13d; S3 , S6 are on and rest of the switches are off according
to Fig. 4.11c. The freewheeling current flows through D6 , S3 , and the filter at this
stage. Meanwhile, the potential of the freewheeling path is clamped at the ground.
Mode 5: Refer to Fig. 4.13e; the energy is delivered from the PV side into the
grid through S4 , S3 , and the AC filter at this stage. The switches S1 and S2 are off
according to Fig. 4.11c, and share the input voltage U pv in series, so their turn-off
voltage stress is half of the input voltage.
Mode 6: Refer to Fig. 4.13f; S2 , S4 , S5 are on and rest of the switches are off
according to Fig. 4.11c. The freewheeling current flows through S5 , D2 , and the filter
at this stage. Meanwhile, the potential of the freewheeling path is clamped at the
ground.
Based on the operating modes, the potentials of points 1 and 2 against N, as well
as DMV and CMV are shown in Table 4.6.
Furthermore, the loss distribution of NPC and A-NPC in unity power factor case
is shown in Figs. 4.14 and 4.15 [4]. Loss of the outermost switch S1 and the innermost
switch S2 varies significantly when modulation strategy I is used for A-NPC, as shown
in Fig. 4.15a. Consequently, the life and output power of the inverter will be limited
by individual switch. Meanwhile, the total loss of NPC is highly in accordance with
that of A-NPC with modulation strategy I, because they have a consistent model in
the energy-delivering stage and an equivalent model in the freewheeling stage.
The loss distribution of A-NPC with modulation strategy II is shown in Fig. 4.15b.
It is worth mentioning that the difference between power loss of the outermost switch
S1 and the innermost switch S2 is significantly reduced, which will bring advantage
for heat dissipation and improvement of inverter life.

Table 4.6 DMV and CMV levels of different operating modes for A-NPC with modulation strategy
II
Modes u1N u2N uDM uCM uCM-DM uCM_tot
(1) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(2) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(3) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(4) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(5) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(6) U pv /2 U pv /2 0 U pv /2 0 U pv /2
142 4 Half-Bridge Transformerless PV Grid-Connected Inverters

Fig. 4.14 Loss distribution 700

700
of NPC Pcon
600
600
Psw

Power loss [w]

5500
00

4400
00

3300
00

2200
00

1100
00

00
S1 D1 S5 D5 S2 D2

(a) (b)
600
700
700 600
Pcon Pcon
Power loss [w]

600
Power loss [w]
600
500
500
Psw Psw
500
500
400
400

400
400
300
300
300
300
200
200
200
200

100
100
100
100

00 0 0
S1 D1 S5 D5 S2 D2 S1 D1 S5 D5 S2 D2

Fig. 4.15 Loss distributions of A-NPC with different modulation strategies, a Loss distribution
with modulation strategy I, b Loss distribution with modulation strategy II

As indicated by aforementioned discussion, the existence of two freewheeling

stages in each switching cycle yields more promising loss distribution. Besides,
there are two voltage pulses in every switching cycle when modulation strategy II is
used, which breeds an equivalent effect of double frequency in A-NPC.
2. Simulation results

In order to verify the aforementioned operating principle and property anal-

ysis, a simulation model of A-NPC grid-connected inverter is established in
Matlab/Simulink, and the key parameters are listed in Table 4.3.
When modulation strategy I is used in A-NPC, the simulation waveforms of DMV
uDM in time domain and frequency domain are shown in Fig. 4.16a, b, respectively.
In addition to the case that modulation strategy II is used in A-NPC, the associated
simulation waveforms are shown in Fig. 4.17. It can be seen that the amplitude of
DMV is zero at switching frequency, but there exists double frequency component.
An equivalent effect of double frequency appears due to the adoption of modulation
strategy II, which is consistent with the theoretical analysis. Besides, the CMV char-
acteristics of A-NPC are in accordance with that of NPC, as shown in the simulation
waveforms (Figs. 4.5, 4.6, 4.7, and 4.8).
4.2 I-Type Half-Bridge TLIs 143

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]

uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 4.16 DMV waveforms of A-NPC with modulation strategy I, a Time domain, b Frequency
domain

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]

uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 4.17 DMV waveforms of A-NPC with modulation strategy II, a Time domain, b Frequency
domain

4.2.3 Double Capacitors Legs NPC Inverter

1. Operating principle

The DC component of the grid-in current can be reduced by the shunt capacitor of
DC side in NPC, but the grid-in current does not flow through the capacitor during
freewheeling stages, which will introduce DC component to a certain extent. As
shown in Fig. 4.18a, double capacitors legs neutral point clamped three-level inverter
was proposed to further reduce DC component of grid-in current [7]. Compared with
NPC, a shunt capacitor bridge composed of capacitors C dc3 and C dc4 is added to the
circuit while the midpoint is connected to the neutral point of the grid, as main
circuit shown in Fig. 4.18a. In accordance with the modulation strategy of NPC, the
modulation strategy of NPC-C is shown in Fig. 4.18b.
144 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
vM vtri
P
S1 D1
Cdc1 Cdc3 ωt

Upv D5
S2 D2
S1 ωt
3 1 2
PV L S2 ωt
S3 ug
D3 S3 ωt
D6
S4 ωt
Cdc2 S4 D4 Cdc4 u12 ωt
N

Fig. 4.18 NPC-C grid-connected inverter, a Main circuit, b Modulation strategy

There are four operating modes according to the polarities of the grid voltage and
grid current when NPC-C works in unity power factor case, as shown in Fig. 4.19.
Mode 1 and Mode 2 in Fig. 4.19a, b, respectively, work in positive half period of the

(a) (b)

S1 D1 S1 D1
Cdc1 Cdc3 Cdc1 Cdc3

Upv D5 Upv D5
S2 D2 S2 D2
iL1 ig iL1 ig
PV L ug PV L ug
S3 D3 S3 D3
D6 D6

Cdc2 S4 D4 Cdc4 Cdc2 S4 D4 Cdc4

N N
(c) (d)

S1 D1 S1 D1
Cdc1 Cdc3 Cdc1 Cdc3

Upv D5 Upv D5
S2 D2 S2 D2
iL1 ig iL1 ig
PV L ug PV L ug
S3 D3 S3 D3
D6 D6

Cdc2 S4 D4 Cdc4 Cdc2 S4 D4 Cdc4

N N

Fig. 4.19 Equivalent circuits of operating modes of NPC-C, a Mode 1, b Mode 2, c Mode 3,
d Mode 4
4.2 I-Type Half-Bridge TLIs 145

grid voltage; symmetrically, Mode 3 and Mode 4 in Fig. 4.19c, d, respectively, work
in negative half period of the grid voltage.
Mode 1: Refer to Fig. 4.19a; the energy is delivered from the PV side into the
grid through S1 , S2 , and the AC filter at this stage. The switches S3 and S4 are off
according to Fig. 4.18b, and share the input voltage U pv in series, so their turn-off
voltage stress is half of the input voltage.
Mode 2: Refer to Fig. 4.19b; only S2 is on and rest of the switches are off according
to Fig. 4.18b. At this stage, the freewheeling current flows through D5 , S2 , and
the filter, and keeps feeding the grid. It is worth noting that the potential of the
freewheeling path is clamped at the ground.
Mode 3: Refer to Fig. 4.19c; the energy is delivered from the PV side into the
grid through S4 , S3 , and the AC filter at this stage. The switches S1 and S2 are off
according to Fig. 4.18b, and share the input voltage U pv in series, so their turn-off
voltage stress is half of the input voltage.
Mode 4: Refer to Fig. 4.19d; only S3 is on and rest of the switches are off according
to Fig. 4.18b. At this stage, the freewheeling current flows through D6 , S3 , and
the filter, and keeps feeding the grid. It is worth noting that the potential of the
freewheeling path is clamped at the ground.
As indicated by aforementioned operating principle, the switches S1 and S2 are
simultaneously conducted at the energy-delivering stage with positive grid voltage,
and then the value of u12 can be derived as U pv −uCdc4 . In addition to the freewheeling
stage with positive grid voltage, u12 can be expressed as uCdc2 −uCdc4 . At the energy-
delivering stage and the freewheeling stage with negative grid voltage, the value
of u12 can be obtained by uCdc2 −U pv and uCdc2 −uCdc4 , respectively. If uCdc2 and
uCdc4 have an equivalent value, the DMV of NPC-C is shaped as unipolar and three-
level waveform, which is basically consistent with NPC. Therefore, the voltage of
capacitor C dc4 should be controlled as a constant value to effectively balance the
input voltage and reduce DC component of the grid-in current.
Based on the operating modes, the potentials of points 1 and 2 against N, as well
as DMV and CMV are shown in Table 4.7. It can be noticed that the total CMV
uCM_tot of NPC-C is kept in a constant value. The voltage balance of the input-side
capacitor, as well as that of the output-side capacitor is crucial in the controlling of
NPC-C.

Table 4.7 DMV and CMV levels of different operating modes for NPC-C
Modes u1N u2N uDM uCM uCM-DM uCM_tot
(1) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(3) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(4) U pv /2 U pv /2 0 U pv /2 0 U pv /2
146 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

Cdc1 Cdc3
iL1 L1 ig iCdc1 iL1 ig iCdc3
D5
S2 D L ug iCdc4
ug iCdc2 5
S2
Cdc2 Cdc4

Fig. 4.20 Equivalent freewheeling circuits of NPC and NPC-C, a NPC, b NPC-C

2. Simulation results

In order to verify the aforementioned operating principle and property analysis, a

simulation model of NPC-C inverter is established in Matlab/Simulink, and the key
parameters in this circuit are listed in Table 4.3. Subsequently, the CMV and DMV
characteristics are consistent with that of NPC, as simulation waveforms are shown
in Figs. 4.5, 4.6, 4.7, and 4.8.
In positive half period of the grid voltage, equivalent circuits of the freewheeling
stage of NPC and NPC-C are shown in Fig. 4.20. It can be noticed that the grid current
flows through D5 , S2 , and the filter in Fig. 4.20a, while the grid current flows through
D5 , S2 , the filter, and the capacitors in Fig. 4.20b. As a result, the DC component of
grid-in current is significantly reduced with the isolation of capacitors.
When the reference of grid-in current iref is configured as 20sinωt + 1, the simu-
lation waveforms of grid-in current of HERIC, NPC, and NPC-C in time domain
and frequency domain are shown in Fig. 4.21. Furthermore, the spectrum of grid-in
current is listed in Table 4.8, in which 0 Hz represents the DC component and 50 Hz
is the fundamental current. In accordance with the theoretical analysis, NPC and
NPC-C have better DC-suppression effect than HERIC, while the DC component
NPC-C is eliminated the most significantly.
NPCs aforementioned are generally used in occasions with high-input DC voltage.
However, there still exists the shoot through risk of bridge, as indicated by analysis
of operating modes in NPC, A-NPC, and NPC-C. Therefore, the NPC with split-
inductor was proposed to improve operational reliability.

4.2.4 Split-Inductor NPC Inverter

1. Operating principle

The main circuit of split-inductor neutral point camped three-level inverter (SI-NPC)
is shown in Fig. 4.22a [8], where output point of NPC circuit is separated by two
inductors connected to the grid voltage. The switches S1 and S2 are on in positive
half period of the grid voltage, as shown in Fig. 4.22b. Symmetrically, the switches
4.2 I-Type Half-Bridge TLIs 147

(a) (b)
ig(5A/div) A[0.2A/div]

0
t[10µs/div] 0Hz 50Hz 100Hz 150Hz 200Hz
(c) (d)
ig(5A/div) A[50mA/div]

0
t[10µs/div] 0Hz 50Hz 100Hz 150Hz 200Hz
(e) (f)
ig(5A/div) A[50mA/div]

0
t[10µs/div] 0Hz 50Hz 100Hz 150Hz 200Hz

Fig. 4.21 Grid-in current waveforms of different TLIs, a HERIC in time domain, b HERIC in
frequency domain, c NPC in time domain, d NPC in frequency domain, e NPC-C in time domain,
f NPC-C in frequency domain
148 4 Half-Bridge Transformerless PV Grid-Connected Inverters

Table 4.8 Components of

Frequency (Hz) HERIC (A) NPC (A) NPC-C (A)
grid-in current at different
frequencies with different 0 0.976 0.023 0.006
TLIs 50 20.07 21.33 21.34
100 0.02 0.08 0.01
150 0.08 0.23 0.23
200 0.01 0.01 0.01

(a) (b)
vM vtri
ωt
S1 D1
Cdc1

S1 ωt
Upv D5 S2 D2
L1 S2 ωt
3 1 u13 ωt
PV 2
D6 L2
S3 D3 ωt
ug S3
S4 ωt
Cdc2 S4 D4 u23 ωt
N

Fig. 4.22 SI-NPC grid-connected inverter, a Main circuit, b Modulation strategy

S3 and S4 are on in negative half period of the grid voltage. It is worth noting that S1
and S4 operate with fundamental or high frequency depending on the grid voltage,
while S2 and S3 operate with line-frequency in SI-NPC.
There are four operating modes according to the polarities of the grid voltage and
grid current when SI-NPC works in unity power factor case, as shown in Fig. 4.23.
Mode 1 and Mode 2 in Fig. 4.23a, b, respectively, work in positive half period of the
grid voltage; symmetrically, Mode 3 and Mode 4 in Fig. 4.23c, d, respectively work
in negative half period of the grid voltage.
Mode 1: Refer to Fig. 4.23a; the energy is delivered from the PV side into the grid
through S1 , S2 , and the filter L 1 at this stage. According to Fig. 4.22b, the switches
S3 and S4 are off, and share the input voltage U pv in series, so their turn-off voltage
stress is half of the input voltage.
Mode 2: Refer to Fig. 4.23b; only S2 is on and rest of the switches are off according
to Fig. 4.22b. At this stage, the freewheeling current flows through D5 , S2 , and the
filter L 1 , and keeps feeding the grid. It is worth noting that the potential of the
freewheeling path is clamped at the ground.
Mode 3: Refer to Fig. 4.23c; the energy is delivered from the PV side into the grid
through S4 , S3 , and the filter L 2 at this stage. According to Fig. 4.22b, the switches
4.2 I-Type Half-Bridge TLIs 149

(a) (b)

S1 D1 S1 D1
Cdc1 Cdc1

Upv D5 S2 D2 Upv D5 S2 D2
iL1 L1 iL1 L1

PV PV
D6 L2 ig D6 L2 ig
S3 D3 ug S3 D3 ug

Cdc2 S4 D4 Cdc2 S4 D4
N N

(c) (d)

S1 D1 S1 D1
Cdc1 Cdc1

Upv D5 S2 D2 Upv D5 S2 D2
L1 L1

PV iL2 L PV iL2 L
D6 2 ig D6 2 ig
S3 D3 ug S3 D3 ug

Cdc2 S4 D4 Cdc2 S4 D4
N N

Fig. 4.23 Equivalent circuits of operating modes of SI-NPC, a Mode 1, b Mode 2, c Mode 3,
d Mode 4

S1 and S2 are off, and share the input voltage U pv in series, so their turn-off voltage
stress is half of the input voltage.
Mode 4: Refer to Fig. 4.23d; only S3 is on and rest of the switches are off according
to Fig. 4.22b. At this stage, the freewheeling current flows through D6 , S3 , and the
filter L 2 , and keeps feeding the grid. It is worth noting that the potential of the
freewheeling path is clamped at the ground.
Based on the operating modes, the potentials of points 1 and 2 against N, as
well as DMV and CMV are shown in Table 4.9. Note that circuit paths of the grid
current vary in positive and negative half period of the grid voltage, so the calculation
methods of DMV and CMV of Modes 1 and 2 differ from that of Modes 3 and 4.
It can be observed that the total CMV of SI-NPC is also kept in a constant value
without switching frequency LC. In addition, the risk of shoot through in bridge is
eliminated after the modified structure with two output inductors is adopted.
150 4 Half-Bridge Transformerless PV Grid-Connected Inverters

Table 4.9 DMV and CMV levels of different operating modes of SI-NPC
Modes u1N u2N u3N uDM uCM uCM-DM uCM_tot
(1) U pv ug + U pv /2 U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2) U pv /2 ug + U pv /2 U pv /2 0 U pv /2 0 U pv /2
(3) ug + U pv /2 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(4) ug + U pv /2 U pv /2 U pv /2 0 U pv /2 0 U pv /2

2. Simulation results

In order to verify the aforementioned operating principle and property anal-

ysis, a simulation model of SI-NPC grid-connected inverter is established in
Matlab/Simulink, and the key parameters are listed in Table 4.3.
When the SI-NPC operates with unity power factor, the steady-state waveforms of
the grid voltage ug , reference signal of grid-in current iref , and actual grid-in current
ig are shown in Fig. 4.24. Furthermore, the simulation waveforms of DMV, CMV, as
well as LC are shown in Figs. 4.25, 4.26, and 4.27, respectively. It can be seen that
the total CMV is kept in a constant value, and then LC is mitigated in the SI-NPC.
In case of shoot through in the SI-NPC and NPC, the modulation strategy of
switches is shown in Fig. 4.28. When shoot through occurs at peak of the grid
voltage, the modulation strategy at line-frequency scale and switching frequency
scale is shown in Fig. 4.28a, b, respectively. Furthermore, the current waveforms of
each switch in NPC and SI-NPC during shoot through stage are shown in Fig. 4.29. It
can be noticed that switches of NPC will be damaged due to the sharp rising current.
However, the switch currents of SI-NPC are limited by inductances with small rising
speed and low amplitude during shoot through stage, which effectively avoids the
short circuit of DC side.

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t[10ms/div]

Fig. 4.24 Simulation waveforms of ug , iref , and ig of SI-NPC under unity power factor
4.2 I-Type Half-Bridge TLIs 151

(a) (b)

ig:[10A/div] ig:[10A/div]
0 0

ug:[100V/div] ug:[100V/div]

u1N: u2N:
[100V/div] [100V/div]

0 t[5ms/div] 0 t[5ms/div]

Fig. 4.25 DMV waveforms of SI-NPC, a Output voltage 1, b Output voltage 2

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM_tot:[100V/div]

0 0
t [5ms/div] 0Hz 18kHz 36kHz

Fig. 4.26 CMV waveforms of SI-NPC, a Time domain, b Frequency domain

(a) (b)
A[20mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[20mA/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 4.27 LC waveforms of SI-NPC, a Time domain, b Frequency domain

152 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
1 1
uGS(S1)

uGS(S1)
0 0
1 1
uGS(S3) uGS(S2)

uGS(S3) uGS(S2)
0 0
1 1

0 0
1 1
uGS(S4)

uGS(S4)
t[2ms/div] t[10µs/div]
0 0

Fig. 4.28 Modulation strategy with shoot through scenario, a At line-frequency scale, b At
switching frequency scale

(a) (b)
iS1(5A/div)
iS1(5kA/div)

0 0
iS2(5kA/div)

iS2(5A/div)

0 0
iS3(5kA/div)

iS3(5A/div)

0 0
iS4(5kA/div)

iS4(5A/div)

0 t [10μs/div] 0
t [10μs/div]

Fig. 4.29 Shoot through currents waveforms from different topologies, a NPC, b SI-NPC
4.2 I-Type Half-Bridge TLIs 153

3. Experimental results

In order to further verify the effectiveness of operating principle and simulation wave-
forms, a grid-connected experimental platform with SI-NPC circuit is established in
lab. The key component parameters are shown in Table 4.4, where values of the filter
inductances L 1 and L 2 in the circuit are both 4 mH.
The experimental waveforms of the grid voltage ug , grid-in current ig , bridge
voltage u1N , u2N , and u3N are shown in Fig. 4.30a, while the experimental current
waveforms of the filter inductors L 1 and L 2 are shown in Fig. 4.30b.
The waveforms of the LC iCM are shown in Fig. 4.31. It is necessary to point out
that the PV output was simulated by using a DC source with solar array simulation
in this experiment. This is the reason that some LC components appear in Fig. 4.31a

(a) (b)

ig:[16.7A/div] ug:[400V/div]

ug:[400V/div]
iL1:
u3N:[400V/div] [3.3A/div]
u2N:[400V/div]
iL2:
[3.3A/div]

u1N:[400V/div]

Fig. 4.30 Differential-mode waveforms of SI-NPC, a Bridge output voltages, b Filter inductor
currents

(a) (b)

ig:[16.7A/div] ig:[6.7A/div]

ug:[200V/div] ug:[200V/div]

i50Hz iCM:[80mA/div] iCM:[80mA/div]

i50Hz
i18kHz i18kHz i20kHz

Fig. 4.31 LC waveforms of SI-NPC, a Inverter not working, b Inverter working

154 4 Half-Bridge Transformerless PV Grid-Connected Inverters

when the circuit breaker is closed and the SI-NPC inverter has not started yet. After
the SI-NPC inverter starts working to deliver the energy into the grid, a new LC
component appears in Fig. 4.31b, and its frequency is the switching frequency of the
SI-NPC inverter (i.e., 20 kHz). By equivalent calculation, the value of LC is about
1 mA, which is equivalent to the common-mode performance of the NPC circuit.

4.2.5 Diode Split-Inductor NPC Inverter

1. Operating principle

The main circuit of diode split-inductor neutral point clamped three-level inverter
(D-SI-NPC) is proposed by Michael Frisch and Ernö Ternesi in a US patent, as shown
in Fig. 4.32a [9, 10]. Compared with SI-NPC, two diodes are introduced in the D-SI-
NPC circuit, and point 1 is connected to the negative pole of the DC bus through D8 .
Symmetrically, point 2 is connected to the positive pole of the DC bus through D7 .
As a result, the reactive power capacity of SI-NPC is greatly improved. Furthermore,
the modulation strategy of different switches is consistent with NPC and SI-NPC in
unity power factor case, as shown in Fig. 4.32b. Therefore, the operating modes of
D-SI-NPC under unity power factor can also refer to equivalent circuits of Fig. 4.23.
When D-SI-NPC works in non-unity power factor case, the modulation strategy
is shown in Fig. 4.32c. It can be noticed that two new operating modes are introduced
by the high-frequency operation of S2 and S3 , as shown in Fig. 4.33.
Mode 1 in Fig. 4.33a is characterized by positive grid current and negative grid
voltage while the reactive power is delivered from the PV side into the grid through
D8 . Symmetrically, Mode 2 in Fig. 4.33b is characterized by negative grid current
and positive grid voltage, and the reactive power is delivering through D7 .
Based on the operating modes, the potentials of points 1 and 2 against N, as well
as DMV and CMV are shown in Table 4.10. The calculation methods of DMV and
CMV of Modes 1 and 2 differ from that of Modes 3 and 4 due to different circuit
paths of grid current in positive and negative half periods of the grid voltage. The
operating principle, DMV and CMV characteristics are consistent in unity power
factor case of D-SI-NPC and SI-NPC. At the same time, it is worth mentioning that
D-SI-NPC has reactive capability compared with SI-NPC.
2. Simulation results

According to the NPC-TLI parameters listed in Table 4.3, the D-SI-NPC simulation
model was established in Matlab/Simulink to verify the validity of the theoretical
analysis above. When D-SI-NPC operates under unity power factor, the simulation
waveforms can refer to Figs. 4.24, 4.26, and 4.27. Figure 4.34 shows the steady-state
waveforms of grid voltage ug , grid-in current reference iref , and actual grid-in current
ig when D-SI-NPC operates under non-unity power factor. Figure 4.35 shows the
4.2 I-Type Half-Bridge TLIs 155

(a)

S1 D1
Cdc1
D7
Upv D5 S2 D2
L1
3 1
PV 2
D6 L2
S3 D3 ug
D8
Cdc2 S4 D4
N
(b) (c)
vM vtri vM vtri iref
ωt ωt

S1 ωt S1 ωt
S2 ωt S2 ωt
S3 ωt S3 ωt
S4 ωt S4 ωt
u13 ωt u13 ωt

u23 ωt u23 ωt

Fig. 4.32 Diode split-inductor neutral point clamping inverter, a Main circuit, b Modulation
strategy I, c Modulation strategy II

(a) (b)

S1 D1 S1 D1
Cdc1 Cdc1
D7 D7
Upv D5 S2 D2 Upv D5 S2 D2
iL1 L1 L1
iL1
PV PV
D6 L2 ig D6 L2 ig
S3 D3 ug S3 D3 ug
D8 D8
Cdc2 S4 D4 Cdc2 S4 D4
N N

Fig. 4.33 Equivalent circuits of new operating modes of D-SI-NPC with non-unity power factor,
a Mode 1, b Mode 2
156 4 Half-Bridge Transformerless PV Grid-Connected Inverters

Table 4.10 DMV and CMV of different operating modes for D-SI-NPC
Modes u1N u2N uDM uCM uCM-DM uCM_tot
Unity power factor (1) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(3) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(4) U pv /2 U pv /2 0 U pv /2 0 U pv /2
Non-unity power factor (1) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(2) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t [10ms/div]

Fig. 4.34 Simulation waveforms of ug , iref , and ig of D-SI-NPC under non-unity power factor

(a) (b)

ig:[10A/div] ig:[10A/div]
0 0

ug:[100V/div] ug:[100V/div]

u1N: u2N:
[100V/div] [100V/div]
0 0

t [5ms/div] t [5ms/div]

Fig. 4.35 DMV waveforms of D-SI-NPC, a Output voltage 1, b Output voltage 2

waveforms of D-SI-NPC bridge voltage u1N and u2N . As conclusion, compared with
SI-NPC, two diodes added to provide a reactive power channel, so D-SI-NPC can
operate under non-unity power factor.
4.2 I-Type Half-Bridge TLIs 157

4.2.6 Six-Switch Five-Level Active Neutral Point Clamped

Inverter

Different from traditional two-level and three-level inverters, the number of output
levels in multi-level TLIs is increased [11–13], including five-level, seven-level, and
so on [14]. Furthermore, waveforms of multi-level inverters are more sinusoidal
and shaped with less harmonic components; then, smaller filters can be used in the
circuit. In this section, the six-switch five-level midpoint clamp TLI will be discussed
in detail [15].
1. Operating principle

The main circuit of a six-switch five-level active neutral point clamped inverter (6S-
5L-ANPC) is shown in Fig. 4.36a [15, 16], where the midpoint of the input voltage
is connected to the neutral point of the grid. Furthermore, refer to the driving logic
shown in Fig. 4.36b, and it can be noticed that the waveform of DMV is shaped as
five-level, and the voltage levels of different switching stages are listed in Table 4.11.

(a) (b)

Cdc1 S5 S1 D1

Upv D5 ωt
S2 D2
2
C 1
PV L
S3 D3 ug
D6 u12 ωt

Cdc2 S6 S4 D4
N

Fig. 4.36 6S-5L-ANPC grid-connected inverter, a Main circuit, b Modulation strategy

Table 4.11 DMV levels of 6S-5L-ANPC under different switching states

S1 S2 S3 S4 S5 S6 Output voltage
1 1 0 0 0 1 U pv /2
1 0 1 0 0 1 U pv /4
0 1 0 0 0 1 U pv /4
0 0 1 0 0 1 0+
0 1 0 0 1 0 0−
0 0 1 0 1 0 −U pv /4
0 1 0 1 1 0 −U pv /4
0 0 1 1 1 0 −U pv /2
158 4 Half-Bridge Transformerless PV Grid-Connected Inverters

There are eight operating modes according to the polarities of the grid voltage
and grid current when 6S-5L-ANPC works in unity power factor case, as shown in
Fig. 4.37. In positive half period of the grid voltage, the associated modes 1–4 are
illustrated in Fig. 4.37a, b, c, and d; symmetrically, the rest of the modes 5–8 work
in negative half period of the grid voltage.
Mode 1: Refer to Fig. 4.37a; the energy is delivered from the PV side into the
grid through S1 , S2 , and the AC filter at this stage. The switches S3 and S4 are off,
and their turn-off voltage stress is half of the input voltage.
Mode 2: Refer to Fig. 4.37b; the energy is delivered from the PV side into the
grid by charging the capacitor C. Besides, the grid current flows through S1 , D3 , and
the AC filter with 1/4 of U pv output in midpoint of the bridge.
Mode 3: Refer to Fig. 4.37c; the energy is delivered from the PV side into the
grid by discharging the capacitor C. Besides, the grid current flows through D6 , S6 ,
S2 , and the AC filter with 1/4 of U pv output in midpoint of the bridge.
Mode 4: Refer to Fig. 4.37d; only S6 is on and rest of the switches are off. The
freewheeling current flows through D6 , S6 , D3 , and the AC filter at this stage. It is
worth noting that the potential of the freewheeling path is still clamped at the ground.
Mode 5: Refer to Fig. 4.37e; the energy is delivered from the PV side into the
grid through S4 , S3 , and the AC filter at this stage. The switches S1 and S2 are off,
and their turn-off voltage stress is half of the input voltage.
Mode 6: Refer to Fig. 4.37f; the energy is delivered from the PV side into the grid
by the charging capacitor C. Besides, the grid-in current flows through S4 , D2 , and
the AC filter with 1/4 of −U pv output in midpoint of the bridge.
Mode 7: Refer to Fig. 4.37g; the energy is delivered from the PV side into the
grid by discharging the capacitor C. Besides, the grid current flows through D5 , S5 ,
S3 , and the AC filter with 1/4 of −U pv output in midpoint of the bridge.
Mode 8: Refer to Fig. 4.37h; only S4 is on and rest of the switches are off. The
freewheeling current flows through D5 , S5 , D2 , and the AC filter at this stage. It is
worth noting that the potential of the freewheeling path is still clamped at the ground.
2. Simulation results

In order to verify the aforementioned operating principle and property analysis,

a simulation model of 6S-5L-ANPC grid-connected inverter is established in
Matlab/Simulink, and the key parameters are listed in Table 4.12.
Figure 4.38 shows the waveforms of the grid voltage ug , the reference of grid-in
current iref , and the actual grid-in current ig when the 6S-5L-ANPC operates with
unity power factor. The simulation waveforms of DMV uDM in time domain and
frequency domain are shown in Fig. 4.39a, b, respectively. Besides the line-frequency
component, the amplitude of DMV is prominent around the switching frequency and
double switching frequency.
As shown in Fig. 4.40, it can be seen that the capacitor voltage is 1/4 of the
input voltage U pv during operation. Since the capacitor is charged and discharged at
the switching frequency scale, the balance between charge and discharge stages is
4.2 I-Type Half-Bridge TLIs 159

(a) (b)

Cdc1 S5 S1 D1 Cdc1 S5 S1 D1

Upv D5 Upv D5
S2 D2 S2 D2
ig ig
C C
PV iL L PV iL L
S3 D3 ug S3 D3 ug
D6 D6

Cdc2 S6 S4 D4 Cdc2 S6 S4 D4
N N
(c) (d)

Cdc1 S5 S1 D1 Cdc1 S5 S1 D1

Upv D5 Upv D5
S2 D2 S2 D2
ig ig
C C
PV iL L PV iL L
S3 D3 ug S3 D3 ug
D6 D6

Cdc2 S6 S4 D4 Cdc2 S6 S4 D4
N N
(e) (f)

Cdc1 S5 S1 D1 Cdc1 S5 S1 D1

Upv D5 Upv D5
S2 D2 S2 D2
ig ig
C C
PV iL L PV iL L
S3 D3 ug S3 D3 ug
D6 D6

Cdc2 S6 S4 D4 Cdc2 S6 S4 D4
N N
(g) (h)

Cdc1 S5 S1 D1 Cdc1 S5 S1 D1

Upv D5 Upv D5
S2 D2 S2 D2
ig ig
C C
PV iL L PV iL L
S3 D3 ug S3 D3 ug
D6 D6

Cdc2 S6 S4 D4 Cdc2 S6 S4 D4
N N

Fig. 4.37 Equivalent circuits of operating modes of 6S-5L-ANPC, a Mode 1, b Mode 2, c Mode
3, d Mode 4, e Mode 5, f Mode 6, g Mode 7, h Mode 8
160 4 Half-Bridge Transformerless PV Grid-Connected Inverters

Table 4.12 Key parameters of 1 kW 6S-5L-ANPC

Parameters Value Parameters Value
Input voltage U pv /V 400 Switching frequency f s /kHz 15
Grid voltage ug /V 110 Capacitance C/μF 310
Line frequency/Hz 50 Filter inductor L f /mH 1.6
Rated power P/W 1000 Parasitic capacitance of PV panel C pv /nF 50

ug:[100V/div]
0

ig:[10A/div] iref:[10A/div]
0

t [10ms/div]

Fig. 4.38 Simulation waveforms of ug , iref , and ig of 6S-5L-ANP under unity power factor

(a) (b)
A[20V/div]
ig:[10A/div]
0
ug:[50V/div]

u12:
[100V/div]
0

0
t[5ms/div] 50Hz 15kHz 30kHz

Fig. 4.39 DMV waveforms of 6S-5L-ANPC, a Time domain, b Frequency domain

effectively realized. As a result, the stability of the voltage can be controlled with a
smaller capacitor in the 6S-5L-ANPC circuit.
In the I-type half-bridge circuit with a voltage clamping structure, the operating
voltages of switches can be reduced to half of the input voltage, which is suitable
for high-voltage applications. When TLIs are used in lower voltage occasions, the
conduction loss is larger if the grid-in current flows through two switches during the
4.2 I-Type Half-Bridge TLIs 161

Fig. 4.40 Capacitor voltage

waveform in 6S-5L-ANPC
ig:[10A/div]
0
ug:[50V/div]

uC:[0.2V/div]
100

t [5ms/div]

energy-delivering stage. Furthermore, the T-type half-bridge TLI was proposed to

reduce the conduction loss of switches.

4.3 T-Type Half-Bridge TLIs

T-type half-bridge TLIs mainly include the T neutral point clamped grid-connected
inverter (T-NPC) and its improved topologies. Specifically, the T-NPC was invented
by Knaup Peter with an applied international patent [17]. T-NPC, also known as
Conergy NPC, has been applied to the IPG series products (2–5 kW) of Conergy
Company. According to report of Photo International in July 2007, the European
efficiency of T-NPC is 95.1% and the peak efficiency is 96.1%.

4.3.1 Conventional T-NPC Inverter

1. Operating principle

Compared with NPC, only two switches are configured in the bridge of T-NPC, as
shown in Fig. 4.41a [17, 18]. Furthermore, the capacitor bridge and switch bridge
are connected by two series switches to realize voltage clamping. As the modulation
strategy in Fig. 4.41b shows, switches S1 and S3 conduct complementarily in positive
half period of the grid voltage. Symmetrically, switches S2 and S4 conduct comple-
mentarily during negative half period of the grid voltage. It is worth mentioning that
the waveform of DMV is shaped as three-level voltage by unipolar modulation.
There are four operating modes according to the polarities of the grid voltage and
grid current when T-NPC works in unity power factor case, as shown in Fig. 4.42.
Mode 1 and Mode 2 in Fig. 4.42a, b, respectively, work in positive half period of the
grid voltage; symmetrically, Mode 3 and Mode 4 in Fig. 4.42c, d, respectively, work
in negative half period of the grid voltage.
162 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
vM vtri
ωt
Cdc1 S1 D1
Upv
D4 D3 ωt
2 1 S1
PV L S2 ωt
S4 S3 S3 ωt
S2 D2 ug
Cdc2 S4 ωt
N u12 ωt

Fig. 4.41 T-NPC grid-connected inverter, a Main circuit, b Modulation strategy

(a) (b)

Cdc1 S1 Cdc1 S1
D1 D1
Upv Upv
D4 D3 iL ig D4 D3 iL ig
PV L PV L
S4 S3 S4 S3
S2 D2 ug S2 D2 ug
Cdc2 Cdc2
N N
(c) (d)

Cdc1 S1 Cdc1 S1
D1 D1
Upv Upv
D4 D3 iL ig D4 D3 iL ig
PV L PV L
S4 S3 S4 S3
S2 D2 ug S2 D2 ug
Cdc2 Cdc2
N N

Fig. 4.42 Equivalent circuits of T-NPC in different modes, a Mode 1, b Mode 2, c Mode 3, d Mode
4

Mode 1: Refer to Fig. 4.42a; only S1 is on and rest of the switches are off according
to Fig. 4.41b. Similar to the operation mode of conventional half-bridge converters,
the energy is delivered from the PV side into the grid through S1 and AC filter at this
stage.
Mode 2: Refer to Fig. 4.42b; only S3 is on and rest of the switches are off according
to Fig. 4.41b. At this stage, the freewheeling current flows through D4 , S3 , and
the filter, and keeps feeding the grid. It is worth noting that the potential of the
freewheeling path is clamped at the ground.
4.3 T-Type Half-Bridge TLIs 163

Table 4.13 DMV and CMV levels of different operating modes for T-NPC
Modes u1N u2N uDM uCM uCM-DM uCM_tot
(1) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(3) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(4) U pv /2 U pv /2 0 U pv /2 0 U pv /2

Mode 3: Refer to Fig. 4.42c; the energy is delivered from the PV side into the grid
through S2 and the AC filter at this stage.
Mode 4: Refer to Fig. 4.42d; only S4 is on and rest of the switches are off according
to Fig. 4.41b. At this stage, the freewheeling current flows through D3 , S4 , and
the filter, and keeps feeding the grid. It is worth noting that the potential of the
freewheeling path is clamped at the ground.
Based on the operating modes, the potentials of points 1 and 2 against N, as well
as DMV and CMV are shown in Table 4.13. Compared with NPC, two diodes are
removed in the circuit of T-NPC. The grid current only flows through one switch in
the energy-delivering stage, so the switching loss and its distribution are optimized,
and bring advantages for design of heat dissipation and improvement of inverter life.
However, the voltage stress of switches S1 and S2 in T-NPC is U pv , which is twice
of that in NPC circuit in the same case. Meanwhile, it is worth noting that the total
CMV of T-NPC remains in a constant value in all operating modes.
2. Simulation results

In order to verify the aforementioned operating principle and property anal-

ysis, a simulation model of T-NPC grid-connected inverter is established in
Matlab/Simulink, and the key parameters are listed in Table 4.3.
When the T-NPC operates with unity power factor, the steady-state waveforms of
the grid voltage ug , reference signal of grid-in current iref , and actual grid-in current
ig are shown in Fig. 4.43. The simulation waveforms of DMV and CMV in time
domain and frequency domain are shown in Figs. 4.44 and 4.45. It can be noticed
that the DMV is shaped as quasi-unipolar three-level waveform, while no harmonic
appears in the CMV. Furthermore, the simulation waveforms of LC in time domain
and frequency domain are shown in Fig. 4.46a, b, respectively. As a conclusion, the
LC is effectively eliminated in T-NPC with a constant CMV.

4.3.2 Reduced Switches T-NPC Inverter

1. Operating principle

The reduced switches T neutral point clamped three-level inverter (RS-T-NPC) was
proposed, as shown in Fig. 4.47a [19]. Compared with conventional T-NPC, a circuit
164 4 Half-Bridge Transformerless PV Grid-Connected Inverters

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t [10ms/div]

Fig. 4.43 Simulation waveforms of ug , iref , and ig of T-NPC

(a) (b)

A[50V/div]
ig:[10A/div]
0

ug:[100V/div]

uDM:
[100V/div]
0

t[5ms/div] 0
50Hz 18kHz 36kHz

Fig. 4.44 DMV waveforms of T-NPC, a Time domain, b Frequency domain

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM_tot:[100V/div]

0 0
t [5ms/div] 0Hz 18kHz 36kHz

Fig. 4.45 CMV waveforms of T-NPC, a Time domain, b Frequency domain

4.3 T-Type Half-Bridge TLIs 165

(a) (b)

A[20mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[20mA/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 4.46 LC waveforms of T-NPC, a Time domain, b Frequency domain

(a) (b) vM vtri

ωt
Cdc1 S1 D1
Upv
S1 ωt
2 D5 D3 1
S3 S2 ωt
PV L
D6 D4 S3 ωt
S2 D2 ug
Cdc2 u12 ωt
N

Fig. 4.47 RS-T-NPC grid-connected inverter, a Main circuit, b Modulation strategy

composed of one switch and four diodes replaces the circuit composed of two
switches to realize freewheeling and voltage clamping. It can be noticed that S3
operates with high frequency throughout whole cycle of the grid voltage, as shown
in Fig. 4.47b. In order to prevent short-circuit at DC side, dead time in switching
frequency scale is needed between S3 and the combination of S1 and S2 . As a result,
the waveform of DMV is shaped as three-level voltage by unipolar modulation.
There are six operating modes according to the polarities of the grid voltage
and grid current when RS-T-NPC works in unity power factor case, as shown in
Fig. 4.48. Mode 1, Mode 2, and Mode 3 in Fig. 4.48a–c, respectively, work in
positive half period of the grid voltage; symmetrically, Mode 3, Mode 4, and Mode
5 in Fig. 4.48d–f, respectively, work in negative half period of the grid voltage.
Mode 1: Refer to Fig. 4.48a; only S1 is on and rest of the switches are off according
to Fig. 4.47b. And thus the energy is delivered from the PV side into the grid through
S1 and AC filter at this stage.
Mode 2: Refer to Fig. 4.48b; all of the switches are off according to Fig. 4.47b at
this stage. Thus the dead time current flows through D2 and AC filter with −U pv /2
output in midpoint of the bridge.
166 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

Cdc1 S1 Cdc1 S1
D1 D1
Upv Upv
D5 D3 iL ig D5 D3 iL ig
S3 S3
PV L PV L
D6 D4 D6 D4
S2 D2 ug S2 D2 ug
Cdc2 Cdc2
N N
(c) (d)

Cdc1 S1 Cdc1 S1
D1 D1
Upv Upv
D5 D3 iL ig D5 D3 iL ig
S3 S3
PV L PV L
D6 D4 D6 D4
S2 D2 ug S2 D2 ug
Cdc2 Cdc2
N N
(e) (f)

Cdc1 S1 Cdc1 S1
D1 D1
Upv Upv
D5 D3 iL ig D5 D3 iL ig
S3 S3
PV L PV L
D6 D4 D6 D4
S2 D2 ug S2 D2 ug
Cdc2 Cdc2
N N

Fig. 4.48 Equivalent circuits of operating modes of RS-T-NPC, a Mode 1, b Mode 2, c Mode 3,
d Mode 4, e Mode 5, f Mode 6

Mode 3: Refer to Fig. 4.48c; only S3 is on and rest of the switches are off according
to Fig. 4.47b. Thus the freewheeling current flows through D5 , S3 , D4 , and the AC
filter at this stage. It is worth noting that the potential of the freewheeling path is
clamped at the ground.
Mode 4: Refer to Fig. 4.48d; only S2 is on and rest of the switches are off according
to Fig. 4.47b. Thus the energy is delivered from the PV side into the grid through S2
and the AC filter at this stage.
Mode 5: Refer to Fig. 4.48e; all switches are off according to Fig. 4.47b at this
stage. Thus the dead time current flows through D1 and AC filter with U pv /2 output
in midpoint of the bridge.
Mode 6: Refer to Fig. 4.48f; only S3 is on and rest of the switches are off according
to Fig. 4.47b. Thus the freewheeling current flows through D6 , S3 , D3 , and the AC
filter at this stage. Meanwhile, the potential of the freewheeling path is clamped at
the ground.
4.3 T-Type Half-Bridge TLIs 167

Table 4.14 DMV and CMV of different operating modes for HE-S-NPC
Modes u1N u2N uDM uCM uCM-DM uCM_tot
(1), (5) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(3) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(2), (4) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(6) U pv /2 U pv /2 0 U pv /2 0 U pv /2

Based on the operating modes, the potentials of points 1 and 2 against N, as well
as DMV and CMV are shown in Table 4.14. It can be noticed that the principle
of RS-T-NPC is highly consistent with that of T-NPC. Specifically, the voltage is
clamped by one switch and one diode in T-NPC, while the voltage is clamped by
one switch and two diodes in RS-T-NPC during freewheeling stage. Considering the
rectification function of D3 –D6 , the grid current will flow through S3 in a certain
direction, so an active power device can be saved in RS-T-NPC compared with T-
NPC. In the dead-time stage, it is worth mentioning that there are narrow pulses with
a reverse polarity in DMV while total CMV remains constant.
2. Simulation results

In order to verify the aforementioned operating principle and property anal-

ysis, a simulation model of RS-T-NPC grid-connected inverter is established in
Matlab/Simulink, and the key parameters are listed in Table 4.3.
When the RS-T-NPC operates with unity power factor, the steady-state waveforms
of the grid voltage ug , reference signal of grid-in current iref , and actual grid-in current
ig are shown in Fig. 4.49. The simulation waveforms of DMV uDM in time domain and
frequency domain are shown in Fig. 4.50a, b, respectively. It can be seen that the DMV
is shaped as a quasi-unipolar three-level waveform. In addition to the characteristics
of CMV, RS-T-NPC is consistent with that T-NPC as shown in Figs. 4.45 and 4.46.

ug:[100V/div]

ig:[10A/div] iref:[10A/div]
0

t [10ms/div]

Fig. 4.49 Simulation waveforms of ug , iref , and ig of RS-T-NPC

168 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
uDM:[200V/div]

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 4.50 DMV waveforms of RS-T-NPC, a Mode 1, b Mode 2

4.3.3 Diode-Free T-NPC Inverter

1. Operating principle

To further improve the efficiency, the conduction loss of switches and reverse-
recovery loss of diodes in the freewheeling stage need to be reduced, and thus
the diode-free T neutral point clamped three-level inverter (DF-T-NPC) was
proposed in [20]. Compared with T-NPC, the combination of two IGBT in the free-
wheeling and clamping branch are replaced by four CoolMosfet S3 -S6 , as shown in
Fig. 4.51a. Furthermore, the modulation strategy of unipolar modulation is shown
in Fig. 4.51b. In order to avoid short-circuit of DC side, dead time in switching
frequency scale is configured between switches S3 -S6 and S1 , S2 . It can be noticed
that the waveform of DMV is finally shaped as three levels.

(a) (b)
vM vtri
ωt
Cdc1 S1 D1
S3 S5
Upv S1 ωt
2 1 S2 ωt
PV L S3, S6 ωt
S4 S6 ug S4, S5 ωt
S2 D2 u12
Cdc2 ωt
N

Fig. 4.51 DF-T-NPC grid-connected inverter, a Main circuit, b Modulation strategy

4.3 T-Type Half-Bridge TLIs 169

There are six operating modes according to the polarities of the grid voltage and
grid current when DF-T-NPC works in unity power factor case, as shown in Fig. 4.52.
Mode 1, Mode 2, and Mode 3 in Fig. 4.52a–c, respectively, work in positive half
period of the grid voltage; symmetrically, Mode 3, Mode 4, and Mode 5 (Fig. 4.52d–
f), respectively, work in negative half period of the grid voltage. Switches S3 –S6 are
MOSFETs with bidirectionally conductive channels, so the dead time is independent
with DMV. In the freewheeling stage, two switches among switches S3 –S6 are on in
the forward direction while the other switches are on in the reverse direction.
Mode 1: Refer to Fig. 4.52a; the energy is delivered from the PV side into the
grid through S1 and AC filter at this stage. Meanwhile, switches S4 and S5 are also
on according to Fig. 4.51b.

(a) (b)

Cdc1 S1 Cdc1 S1
D1 D1
S3 S5 S3 S5
Upv Upv
iL ig iL ig
PV L PV L
S4 S6 ug S4 S6 ug
S2 D2 S2 D2
Cdc2 Cdc2
N N
(c) (d)

Cdc1 S1 Cdc1 S1
D1 D1
S3 S5 S3 S5
Upv Upv
iL ig iL ig
PV L PV L
S4 S6 ug S4 S6 ug
S2 D2 S2 D2
Cdc2 Cdc2
N N
(e) (f)

Cdc1 S1 Cdc1 S1
D1 D1
S3 S5 S3 S5
Upv Upv
iL ig iL ig
PV L PV L
S4 S6 ug S4 S6 ug
S2 D2 S2 D2
Cdc2 Cdc2
N N

Fig. 4.52 Equivalent circuits of operating modes of DF-T-NPC, a Mode 1, b Mode 2, c Mode 3,
d Mode 4, e Mode 5, f Mode 6
170 4 Half-Bridge Transformerless PV Grid-Connected Inverters

Table 4.15 DMV and CMV of different operating modes in DF-T-NPC

Modes u1N u2N uDM uCM uCM-DM uCM_tot
(1) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2), (3) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(4) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(5), (6) U pv /2 U pv /2 0 U pv /2 0 U pv /2

Mode 2: Refer to Fig. 4.52b; only S4 and S5 are on at this stage according to
Fig. 4.51b, so the dead time current flows through switches S4 , S5 , parallel diodes
of S3 and S6 , and the filter inductors. It is worth noting that the potential of the dead
time path is clamped at the ground.
Mode 3: Refer to Fig. 4.52c; only S1 and S2 are off and rest of the switches
are on at this stage. The freewheeling current flows through switches S3 –S6 and
filter, where switches S4 and S5 are forward conducted while switches S3 and S6 are
reversely conducted. Meanwhile, the potential of the freewheeling path is clamped
at the ground.
Mode 4: Refer to Fig. 4.52d; the energy is delivered from the PV side into the
grid through S2 and AC filter at this stage. Meanwhile, switches S3 and S6 are also
on according to Fig. 4.51b.
Mode 5: Refer to Fig. 4.52e; only S3 and S6 are on at this stage according to
Fig. 4.51b, so the dead time current flows through switches S3 , S6 , parallel diodes
of S4 and S5 , and the filter inductors. It is worth noting that the potential of the dead
time path is clamped at the ground.
Mode 6: Refer to Fig. 4.52f; only S1 and S2 are off and rest of the switches are
on at this stage. The freewheeling current flows through switches S3 -S6 and filter,
where switches S4 and S5 are reversely conducted while switches S3 and S6 are
forward conducted. Meanwhile, the potential of the freewheeling path is clamped at
the ground.
Based on the operating modes, the potentials of points 1 and 2 against N, as well
as DMV and CMV are shown in Table 4.15. It can be seen that the grid current of
DF-T-NPC at the freewheeling stage is divided into two branches and flows through
S3 –S6 , respectively. Furthermore, the conduction loss of switches is optimized due
to the reduced equivalent resistor of clamping branch. Additionally, the DMV of
DF-T-NPC is clamped at the ground while the total CMV remained constant during
the dead time stage.
2. Simulation results

The DMV and CMV characteristics of DF-T-NPC are consistent with that of T-NPC,
as illustrated in Figs. 4.43, 4.44, 4.45, and 4.46.
4.4 Stacked Neutral Point Clamped TLIs 171

4.4 Stacked Neutral Point Clamped TLIs

Stacked neutral point clamped three-level inverter (S-NPC) was proposed to realize
even distribution of the power loss, combining bridge structure and midpoint
clamping circuit of NPC and T-NPC, respectively. Meanwhile, the operating prin-
ciple of S-NPC is similar to that of NPC and T-NPC, and thus the waveform of DMV
in S-NPC is also shaped as three-level [21–23].

4.4.1 Conventional S-NPC Inverter

1. Operating principle

The main circuit of S-NPC is shown in Fig. 4.53a [24] with modulation strategies I
and II shown in Fig. 4.53b, c.
There are four operating modes according to the polarities of the grid voltage and
grid current when S-NPC works in unity power factor case with modulation strategy
I, as shown in Fig. 4.54. Mode 1 and Mode 2 in Fig. 4.54a, b, respectively, work
in positive half period of the grid voltage; symmetrically, Mode 3 and Mode 4 in
Fig. 4.54c, d, respectively, work in negative half period of the grid voltage.
Mode 1: Refer to Fig. 4.54a; the energy is delivered from the PV side into the
grid through S1 , S2 , and the AC filter at this stage. The switches S3 and S4 are off,
and share the input voltage U pv in series, so their turn-off voltage stress is half of the
input voltage.
Mode 2: Refer to Fig. 4.54b; only S2 and S6 are on at this stage according to
Fig. 4.53b. The freewheeling current is divided into two branches, in which branch
one consists of S2 and D7 , while branch two consists of S6 and D5 . Finally, the currents
converge in the AC filter with the potential of the freewheeling path clamped at the
ground.
Mode 3: Refer to Fig. 4.54c; the energy is delivered from the PV side into the
grid through S4 , S3 , and AC filter at this stage. The switches S1 and S2 are off, and
evenly share the input voltage.
Mode 4: Refer to Fig. 4.54d; S3 , S5 , and S6 are on at this stage according to
Fig. 4.53b. The freewheeling current is divided into two branches, in which branch
one consists of S3 and D8 , while branch two consists of S5 and D6 . Finally, the currents
converge in the AC filter with the potential of the freewheeling path clamped at the
ground.
When S-NPC operates under non-unity power factor with modulation strategy
I, there are two new modes as shown in Fig. 4.55. The positive grid current flows
through D3 , D4 , and the filter in negative half period of the grid voltage, as shown in
Fig. 4.55a. Symmetrically, the negative grid current flows through D1 , D2 , and the
filter in positive half period of the grid voltage, as shown in Fig. 4.55b.
172 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a)
S1 D1
Cdc1 D7

Upv
D5 D6 S2 D2
2
PV 1 L
S5 S6 S3 D3 ug

Cdc2 D8
S4 D4
N
(c)
(b)
vM vr1 vr2
vM vtri ωt
ωt

S1 ωt S1 ωt
ωt S2 ωt
S2
S3 ωt S3 ωt
S4 ωt S4 ωt
S5 ωt S5 ωt
S6 ωt S6 ωt
u12 ωt u12 ωt

Fig. 4.53 S-NPC, a Main circuit, b Modulation strategy I, c Modulation strategy II

Based on the operating modes, the potentials of points 1 and 2 against N, as well
as DMV and CMV are shown in Table 4.16. It can be noticed that the grid current
flows through two parallel freewheeling branches, which include not only the diodes
but also the switches S5 and S6. As a result, the total CMV remains at constant, so
the common-mode characteristic is optimized in S-NPC.
The switching loss distribution of S-NPC under unity power factor is shown in
Fig. 4.56 [18]. It is worth noting that the switching frequency was configured as 1 kHz,
while the value of load-current is configured as 130 A. Since the switch combination
S1 and S4 , S2 and S3 , S5 and S6 , the diode combination D7 and D8 operate alternately
throughout whole cycle of the grid voltage, the switching losses of each combination
are an equivalent value, and thus Fig. 4.56 only shows the power loss of S1 , S2 ,
S5 , and D7 . It can be noticed that switching loss distribution is significantly uneven
while the disparity between S1 and S2 is the most outstanding. Therefore, modulation
strategy II was proposed to address the issue of switching loss distribution.
4.4 Stacked Neutral Point Clamped TLIs 173

(a) (b)

S1 D1 S1 D1
Cdc1 D7 Cdc1 D7

Upv Upv
D5 D6 S2 D2
ig D5 D6 S2 D2
ig
iL iL
PV L PV L
S5 S6 S3 D3 ug S5 S6 S3 D3 ug

Cdc2 D8 Cdc2 D8
S4 D4 S4 D4
N N

(c) (d)

S1 D1 S1 D1
Cdc1 D7 Cdc1 D7

Upv Upv
D5 D6 S2 D2
ig D5 D6 S2 D2
ig
iL iL
PV L PV L
S5 S6 S3 D3 ug S5 S6 S3 D3 ug

Cdc2 D8 Cdc2 D8
S4 D4 S4 D4
N N

Fig. 4.54 Equivalent circuits of operating modes of S-NPC with modulation strategy I, a Mode 1,
b Mode 2, c Mode 3, d Mode 4

(a) (b)

S1 D1 S1 D1
Cdc1 D7 Cdc1 D7

Upv Upv
D5 D6 S2 D2
ig D5 D6 S2 D2
ig
iL iL
PV L PV L
S5 S6 S3 D3 ug S5 S6 S3 D3 ug

Cdc2 D8 Cdc2 D8
S4 D4 S4 D4
N N

Fig. 4.55 Equivalent circuits of new operating modes of S-NPC with modulation strategy I under
non-unity power factor, a Mode 1, b Mode 2
174 4 Half-Bridge Transformerless PV Grid-Connected Inverters

Table 4.16 DMV and CMV levels of different working stages with modulation strategy I
Modes u1N u2N uDM uCM uCM-DM uCM_tot
Unity power factor (1) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(3) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(4) U pv /2 U pv /2 0 U pv /2 0 U pv /2
Non-unity power factor (1) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(2) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2

Fig. 4.56 Loss distribution 400

among power devices with 350

Power loss [W]

modulation strategy I 300
250
200
150
100
50
0
S1 S2 S5 D7

There are six operating modes according to the polarities of the grid voltage and
grid current when S-NPC works in unity power factor with modulation strategy II,
as shown in Fig. 4.57. Modes 1, 2, and 3 belong to positive half period of the grid
voltage in Fig. 4.57a–c, respectively; symmetrically, Modes 3, 4, and 5 belong to
negative half period of the grid voltage in Fig. 4.57d, f.
Mode 1: Refer to Fig. 4.57a; the energy is delivered from the PV side into the grid
through S1 , S2 , and the AC filter at this stage. The switches S3 , S4 , and S5 are off,
and S3 and S4 share the input voltage U pv in series, so their turn-off voltage stress is
half of the input voltage.
Mode 2: Refer to Fig. 4.57b; S2 and S5 are on and rest of the switches are off
according to Fig. 4.53c. At the first freewheeling stage, the current flows through D7 ,
S2 , and the filter, and keeps feeding the grid. It is worth noting that the potential of
the freewheeling path is clamped at the ground.
Mode 3: Refer to Fig. 4.57c; S1 , S3 , and S6 are on at the second freewheeling
stage according to Fig. 4.53c. The freewheeling current flows through D5 , S6 , and
the filter, and keeps feeding the grid. Meanwhile, the potential of the freewheeling
path is also clamped at the ground.
Mode 4: Refer to Fig. 4.57d, the energy is delivered from the PV side into the
grid through S4 , S3 , and the AC filter at this stage. The switches S1 and S2 are off
and evenly share the input voltage U pv .
Mode 5: Refer to Fig. 4.57e, only S3 is on and rest of the switches are off according
to Fig. 4.53c. At the third freewheeling stage, the current flows through D8 , S3 , and
the filter, and keeps feeding the grid. It can be noticed that the potential of the
freewheeling path is clamped at the ground.
4.4 Stacked Neutral Point Clamped TLIs 175

(a) (b)

S1 D1 S1 D1
Cdc1 D7 Cdc1 D7

Upv Upv
D5 D6 S2 D2
ig D5 D6 S2 D2
ig
iL iL
PV L PV L
S5 S6 S3 D3 ug S5 S6 S3 D3 ug

Cdc2 D8 Cdc2 D8
S4 D4 S4 D4
N N

(c) (d)

S1 D1 S1 D1
Cdc1 D7 Cdc1 D7

Upv Upv
D5 D6 S2 D2
ig D5 D6 S2 D2
ig
iL iL
PV L PV L
S5 S6 S3 D3 ug S5 S6 S3 D3 ug

Cdc2 D8 Cdc2 D8
S4 D4 S4 D4
N N

(e) (f)

S1 D1 S1 D1
Cdc1 D7 Cdc1 D7

Upv Upv
D5 D6 S2 D2
ig D5 D6 S2 D2
ig
iL iL
PV L PV L
S5 S6 S3 D3 ug S5 S6 S3 D3 ug

Cdc2 D8 Cdc2 D8
S4 D4 S4 D4
N N

Fig. 4.57 Equivalent circuits of operating modes of S-NPC with modulation strategy II, a Mode
1, b Mode 2, c Mode 3, d Mode 4, e Mode 5, f Mode 6

Mode 6: Refer to Fig. 4.57f; S2 , S4 , and S5 are on at the fourth freewheeling stage
according to Fig. 4.53c. The freewheeling current flows through S5 , D6 , and the filter,
and keeps feeding the grid. Meanwhile, the potential of the freewheeling path is still
clamped at the ground.
Based on the operating modes, the potentials of points 1 and 2 against N, as well
as DMV and CMV are shown in Table 4.17, and the losses of S1 , S2 , S5 , and D7
176 4 Half-Bridge Transformerless PV Grid-Connected Inverters

Table 4.17 DMV and CMV levels of different working stages with modulation strategy II
Modes u1N u2N uDM uCM uCM-DM uCM_tot
(1) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(3) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(4) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(5) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(6) U pv /2 U pv /2 0 U pv /2 0 U pv /2

Fig. 4.58 Loss distribution 300

among different devices with 250
Power loss [W]
modulation strategy II
200
150
100
50
0
S1 S2 S5 D7

in S-NPC with modulation strategy II [18] is shown in Fig. 4.58. Compared with
modulation strategy I, it can be noticed that the loss distribution of S1 and S2 is more
balanced due to the existence of two freewheeling stages in every switching cycle.
Additionally, there are two voltage pulses in each switching cycle, which can yield
an equivalent effect of twice switching frequency.
2. Simulation results

In order to verify the aforementioned operating principle and property anal-

ysis, a simulation model of S-NPC grid-connected inverter is established in
Matlab/Simulink, and the key parameters are listed in Table 4.3. When the S-NPC
operates with unity power factor and modulation strategy I, the steady-state wave-
forms of the grid voltage ug , reference signal of grid-in current iref , and actual grid-in
current ig are shown in Fig. 4.59.
The simulation waveforms of DMV uDM and CMV uCM_tat in time domain and
frequency domain are shown in Figs. 4.60 and 4.61. It can be noticed that the ampli-
tude of DMV is prominent around the switching frequency while no harmonic appears
in the waveform of CMV. Furthermore, the simulation waveforms of the LC in time
domain and frequency domain are shown in Fig. 4.62a, b, respectively. It is worth
mentioning that the LC is eliminated in S-NPC due to the constant total CMV.
Figure 4.63 shows the steady-state waveforms of the grid voltage ug , the grid-in
current ig , and its reference iref when T-NPC operates with non-unity power factor
and modulation strategy I, which indicates that there is reactive power capacity in
T-NPC.
4.4 Stacked Neutral Point Clamped TLIs 177

ug:[100V/div]

ig:[10A/div]
iref:[10A/div]
0

t[10ms/div]

Fig. 4.59 Simulation waveforms of ug , iref , and ig of S-NPC under unity power factor

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]

uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 4.60 DMV waveforms of S-NPC with modulation strategy I, a Time domain, b Frequency
domain

(a) (b)
A[2V/div]
ig:[10A/div]
0

ug:[100V/div]

uCM_tot:[100V/div]

0 0
t [5ms/div] 0Hz 18kHz 36kHz

Fig. 4.61 CMV waveforms of S-NPC with modulation strategy I, a Time domain, b Frequency
domain
178 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[20mA/div]
ig:[10A/div]
0

ug:[100V/div]

iCM:[20mA/div]
0

0
t [5ms/div] 50Hz 18kHz 36kHz

Fig. 4.62 LC waveforms of S-NPC with modulation strategy I, a Time domain, b Frequency
domain

Fig. 4.63 Simulation

waveforms of ug , and ig in ug:[100V/div]
S-NPC with non-unity power
factor
ig:[10A/div]

When the S-NPC operates with non-unity power factor, the steady-state wave-
forms of the grid voltage ug and grid-in current ig are shown in Fig. 4.63, which
indicates that S-NPC can be equipped with reactive power capacity.
When the S-NPC operates with non-unity power factor and modulation strategy
II, the simulation waveforms of DMV uDM in time domain and frequency domain are
shown in Fig. 4.64a, b, respectively. It can be seen that the amplitude of DMV is zero
at switching frequency, but double switching frequency component is significant.
As a conclusion, modulation strategy II in S-NPC can breed an equivalent effect of
twice switching frequency, and bring advantages for the design of filter.
4.4 Stacked Neutral Point Clamped TLIs 179

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]

uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 4.64 DMV waveforms of S-NPC with modulation strategy II, a Time domain, b Frequency
domain

4.4.2 Active Stacked NPC Inverter

1. Operating principle

To further realize the even distribution of switching loss, the active stacked neutral
point clamped three-level inverter (AS-NPC) was proposed, as shown in Fig. 4.65a
[25]. It can be noticed that the active switch is configured to replace the clamping
diodes of S-NPC. Modulated by the unipolar double frequency strategy, the waveform
of DMV is shaped as unipolar and three-level voltage, as shown in Fig. 4.65b.
There are six operating modes according to the polarities of the grid voltage and
grid current when AS-NPC works in unity power factor case, as shown in Fig. 4.66.

(b)
vM vr1 vr2

(a) ωt

S7 S1 D1
Cdc1 S1 ωt
D7 S2 ωt
Upv
D5 D6 S2 D2 S3 ωt
2
1 L S4 ωt
PV
S5 S6 S3 D3 ug S5 ωt
D8 S6 ωt
Cdc2 S7 ωt
S8 S4 D4
N S8 ωt
u12 ωt

Fig. 4.65 AS-NPC grid-connected inverter, a Main circuit, b Modulation strategy

180 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)

S7 S1 D1 S7 S1 D1
Cdc1 Cdc1
D7 D7
Upv Upv
D5 D6 S2 D2
ig D5 D6 S2 D2
ig
iL iL
PV L PV L
S5 S6 S3 D3 ug S5 S6 S3 D3 ug
D8 D8
Cdc2 S8 S4 D4 Cdc2 S8 S4 D4
N N
(c) (d)

S7 S1 D1 S7 S1 D1
Cdc1 Cdc1
D7 D7
Upv Upv
D5 D6 S2 D2
ig D5 D6 S2 D2
ig
iL iL
PV L PV L
S5 S6 S3 D3 ug S5 S6 S3 D3 ug
D8 D8
Cdc2 S8 S4 D4 Cdc2 S8 S4 D4
N N
(e) (f)

S7 S1 D1 S7 S1 D1
Cdc1 Cdc1
D7 D7
Upv Upv
D5 D6 S2 D2
ig D5 D6 S2 D2
ig
iL iL
PV L PV L
S5 S6 S3 D3 ug S5 S6 S3 D3 ug
D8 D8

Cdc2 S8 S4 D4 Cdc2 S8 S4 D4
N N

Fig. 4.66 Equivalent circuits of operating modes of AS-NPC, a Mode 1, b Mode 2, c Mode 3,
d Mode 4, e Mode 5, f Mode 6

Modes 1, 2, and 3 in Fig. 4.66a–c, respectively, work in positive half period of the
grid voltage; symmetrically, Modes 3, 4, and 5 in Fig. 4.66d–f, respectively, work in
negative half period of the grid voltage.
Mode 1: Refer to Fig. 4.66a; the energy is delivered from the PV side into the
grid through S1 , S2 , and the AC filter at this stage. The switches S3 and S4 are off,
and share the input voltage U pv in series, so their turn-off voltage stress is half of the
input voltage.
4.4 Stacked Neutral Point Clamped TLIs 181

Mode 2: Refer to Fig. 4.66b; S1 and S6 are on at the first freewheeling stage
according to Fig. 4.65b. The freewheeling current flows through D5 , S6 , and the
filter, and keeps feeding the grid. Meanwhile, the potential of the freewheeling path
is clamped at the ground.
Mode 3: Refer to Fig. 4.66c; S2 and S7 are on and rest of the switches are off
according to Fig. 4.65b. At the second freewheeling stage, the current flows through
D7 , S2 , and the filter, and keeps feeding the grid. It is worth noting that the potential
of the freewheeling path is clamped at the ground.
Mode 4: Refer to Fig. 4.66d; the energy is delivered from the PV side into the
grid through S4 , S3 , and the AC filter at this stage. The switches S1 and S2 are off
and evenly share the input voltage U pv .
Mode 5: Refer to Fig. 4.66e; S4 and S5 are on at the third freewheeling stage
according to Fig. 4.65b. The freewheeling current flows through S5 , D6 , and the
filter, and keeps feeding the grid. Meanwhile, the potential of the freewheeling path
is still clamped at the ground.
Mode 6: Refer to Fig. 4.66f; S3 , S8 are on and rest of the switches are off according
to Fig. 4.65b. At the fourth freewheeling stage, the current flows through D8 , S3
and filter, and keeps feeding the grid. It can be noticed that the potential of the
freewheeling path is still clamped at the ground.
Based on the operating modes, the potentials of point 1 and 2 against N, as well as
DMV and CMV are shown in Table 4.18. At the freewheeling stage, two branches of
S-NPC work simultaneously while branches of AS-NPC conduct separately. Further-
more, the pulse frequency of the output voltage in AS-NPC is twice the switching
frequency.
2. Simulation results

In order to verify the aforementioned operating principle and property anal-

ysis, a simulation model of AS-NPC grid-connected inverter is established in
Matlab/Simulink, and the key parameters are listed in Table 4.3. The simulation wave-
forms of DMV uDM in time domain and frequency domain are shown in Fig. 4.67a, b,
respectively. It can be seen that the amplitude of DMV is zero at switching frequency,
but double switching frequency component is significant. In accordance with the
theoretical analysis, the AS-NPC can yield an equivalent effect of double switching

Table 4.18 DMV and CMV of different operating modes for AS-NPC
Modes u1N u2N uDM uCM uCM-DM uCM_tot
(1) U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
(2) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(3) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(4) 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
(5) U pv /2 U pv /2 0 U pv /2 0 U pv /2
(6) U pv /2 U pv /2 0 U pv /2 0 U pv /2
182 4 Half-Bridge Transformerless PV Grid-Connected Inverters

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]

uDM:
[100V/div]
0

0
t[5ms/div] 50Hz 18kHz 36kHz

Fig. 4.67 DMV waveforms of AS-NPC, a Time domain, b Frequency domain

frequency in DMV. Furthermore, the CMV characteristics of AS-NPC are consistent

with that of S-NPC, which can refer to Figs. 4.60, 4.61, and 4.62.

4.4.3 High-Efficiency Stacked NPC Inverter

1. Operating principle

To further reduce the switching loss of S-NPC, high-efficiency stacked neutral point
clamped three-level inverter (HE-S-NPC) was proposed, as shown in Fig. 4.68a [26].
It can be noticed that CoolMosfet is configured to replace switches in the middle and
outside of S-NPC, and the midpoint clamping branch is verified from series switches
to parallel switches. Furthermore, the modulation strategy of HE-S-NPC is shown in

(b)
(a) vM vtri
ωt
S1 D1
Cdc1 D7
S1 ωt
Upv S5
D5 S2 S2 ωt
2 ωt
S3
PV 1 L
D6 S3 S4 ωt
S6 ug
S5 ωt
S6 ωt
Cdc2 D8
S4 D2 u12 ωt
N

Fig. 4.68 HE-S-NPC grid-connected inverter, a Main circuit, b Modulation strategy

4.4 Stacked Neutral Point Clamped TLIs 183

Fig. 4.68b. It is worth noting that the waveform of DMV is shaped as unipolar and
three-level voltage.
There are four operating modes according to the polarities of the grid voltage
and grid current when HE-S-NPC works in unity power factor case, as shown in
Fig. 4.69. Modes 1 and 2 in Fig. 4.69a, b, respectively, work in positive half period
of the grid voltage; symmetrically, Modes 3 and 4 in Fig. 4.69c, d, respectively, work
in negative half period of the grid voltage.
Mode 1: Refer to Fig. 4.69a; the energy is delivered from the PV side into the
grid through S1 , S2 , and the AC filter at this stage. The switches S3 and S4 are off,
and share the input voltage U pv in series, so their turn-off voltage stress is half of the
input voltage.
Mode 2: Refer to Fig. 4.69b; S2 and S6 are on and rest of the switches are off
according to Fig. 4.68b. The freewheeling current is divided into two branches, in
which branch one consists of S2 and D7 while branch two consists of S6 and D6 .
Finally, the currents converge in the AC filter with the potential of the freewheeling
path clamped at the ground.
Mode 3: Refer to Fig. 4.69c; the energy is delivered from the PV side into the
grid through S4 , S3 , and the AC filter at this stage. Meanwhile, the switches S1 and
S2 are off and evenly share the input voltage U pv .

(a) (b)

S1 D1 S1 D1
Cdc1 D7 Cdc1 D7
Upv S5 Upv S5
D5 S2 D5 S2
iL ig iL ig
PV L PV L
D6 S3 ug D6 S3 ug
S6 S6

Cdc2 D8 Cdc2 D8
S4 D2 S4 D2
N N

(c) (d)

S1 D1 S1 D1
Cdc1 D7 Cdc1 D7
Upv S5 Upv S5
D5 S2 D5 S2
iL ig iL ig
PV L PV L
D6 S3 ug D6 S3 ug
S6 S6

Cdc2 D8 Cdc2 D8
S4 D2 S4 D2
N N

Fig. 4.69 Equivalent circuits of operating modes of HE-S-NPC with unity power factor, a Mode
1, b Mode 2, c Mode 3, d Mode 4
184 4 Half-Bridge Transformerless PV Grid-Connected Inverters

Mode 4: Refer to Fig. 4.69d; S3 and S5 are on and rest of the switches are off
according to Fig. 4.68b. The freewheeling current is divided into two branches, in
which branch one consists of S5 and D5 while branch two consists of S3 and D8 .
Finally, the currents converge in the AC filter with the potential of the freewheeling
path clamped at the ground.
When HE-S-NPC operates with non-unity power factor, there are two new modes
as shown in Fig. 4.70. As shown in Fig. 4.70a, the current flows to the DC side
through diode D2 during the mode with negative grid voltage and positive grid-in
current. As shown in Fig. 4.70b, the current flows to the DC side through diode D1
during the mode with positive grid voltage and negative grid-in current. It is revealed
that the current does not flow through the parallel diodes of the switches during the
whole cycle of the grid voltage.
Based on the operating modes, the potentials of points 1 and 2 against N, as well
as DMV and CMV are shown in Table 4.19. Considering that only two switches
(CoolMosfet) of HE-S-NPC operate at high frequency with better performance, the
switching loss of HE-S-NPC will be obviously less than S-NPC.

(a) (b)

S1 D1 S1 D1
Cdc1 D7 Cdc1 D7
Upv S5 Upv S5
D5 S2 D5 S2
iL ig iL ig
PV L PV L
D6 S3 ug D6 S3 ug
S6 S6

Cdc2 D8 Cdc2 D8
S4 D2 S4 D2
N N

Fig. 4.70 Equivalent circuits of new operating modes of HE-S-NPC with non-unity power factor,
a Mode 1, b Mode 2

Table 4.19 DMV and CMV levels of different operating modes for HE-S-NPC
Modes u1N u2N uDM uCM uCM-DM uCM_tot
Unity power factor 1 U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
2 U pv /2 U pv /2 0 U pv /2 0 U pv /2
3 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
4 U pv /2 U pv /2 0 U pv /2 0 U pv /2
Non-unity power factor 1 0 U pv /2 −U pv /2 U pv /4 U pv /4 U pv /2
2 U pv U pv /2 U pv /2 3U pv /4 −U pv /4 U pv /2
SW, D, L and C denote the number of switche, diode, inductor and capacitor, respectively. EDS is
the energy-delivering stage while FWS is the freewheeling stage
4.4 Stacked Neutral Point Clamped TLIs 185

Table 4.20 Switch numbers of S-NPC and HE-S-NPC in conduction loops

SW D Unity power factor Non-unity power factor
SW(EDS) SW(FWS) SW3(EDS) SW4(FWS)
S-NPC 6*IGBT 8 2*IGBT 2//2 2 2
HE-S-NPC 4*IGBT+ 6 1*IGBT+ 2//2 1 2
2*CoolMosfet 1*CoolMosfet

Specifically, the numbers of conducting components in S-NPC and HE-S-NPC

during different operating modes are listed in Table 4.20. It can be noticed that the
switching loss of HE-S-NPC is less than that of S-NPC during the energy-delivering
stage. In addition, the conduction loss in HE-S-NPC can be reduced by using the
diodes D5 /D6 , whose loss is less than IGBT’s reverse parallel diode of S-NPC. In
addition to the freewheeling stage, the switching loss of HE-S-NPC is less than S-
NPC even though the two circuits have equivalent current in both branches of S-NPC.
It is worth noting that the switching loss during positive and negative half period
is a consistent value. As a conclusion, HE-S-NPC has more promising efficiency
compared with S-NPC.
As indicated by aforementioned discussion, the grid current of HE-S-NPC flows
through two parallel branches in the freewheeling stage to reduce the conduction
resistor and improve operation efficiency. Compared with S-NPC, it is worth noting
that the internal parallel diodes of switches will not conduct in HE-S-NPC. As S5 and
S6 are separately connected with an external diode, the conduction loss of switches
is lower than that of switches’ internal parallel diodes in the freewheeling stage. In
addition, the switching frequency can be further increased with CoolMosfet used in
the main circuit, which brings advantages for the filter design of HE-S-NPC.
2. Simulation results

The operating principle and simulation waveforms of HE-S-NPC are highly consis-
tent with that of S-NPC, which can refer to Figs. 4.59, 4.60, 4.61, 4.62 and
4.63.

4.5 Summary

The half-bridge NPC-TLI is discussed in this chapter with I-type, and T-type and
stacked-type are also included. The total CMV of half-bridge NPC-TLIs can be kept
in a constant value at high-frequency range which is equal to or larger than the
switching frequency. In addition to low-frequency range, the CMV is maintained
as half of the input voltage, and thus there is no LC as expected. Besides, distribu-
tions of the switching loss, the ability to eliminate DC components, the reliability of
preventing short-circuit, and the reactive power are discussed. Comparison of char-
acteristics among different half-bridge NPC TLIs discussed in this chapter is shown
in Table 4.21, which can be a reference for engineers and technicians.
 186

Table 4.21 Comparison of DMV performance among different NPC-TLIs

Name Circuit structure Power losses Remark
SW D L C SW(HF) SW(EDS) SW(FWS) HF: high-frequency
I-type NPC [1] 4 4+2 1 2 2+1 2 2 –
A-NPC [2] 6 6 1 2 2 2 2 Uniform distribution of switching losses
NPC-C [7] 4 6 1 4 2 2 2 Less DC component
SI-NPC [8] 4 6 2 2 2 2 2 Prevention of short-circuit
D-SI-NPC [9] 4 8 2 2 2 2 2 Large reactive power capability
6S-5L-ANPC [15] 6 6 4 6 2 2 3 Five-level output voltage
T-type T-NPC [17] 4 4 1 2 4 1 2 –
RS-T-NPC [19] 3 6 1 2 2+1 1 3 –
DF-T-NPC [20] 6 6 1 2 6 1 2//2 –
Stacked -type S-NPC [24] 6 8 1 2 4 2 2//2 Uniform distribution of switching losses
AS-NPC [25] 8 8 1 2 6+2 2 2 Uniform distribution of switching losses
HE-S-NPC [26] 6 6 1 2 2 2 2//2 –
HF denotes high-frequency while other Abbreviations are consistent with those of Table 4.20
4 Half-Bridge Transformerless PV Grid-Connected Inverters
References 187

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Chapter 5
Common-Ground Transformerless
Grid-Connected Inverters

Abstract Rule 1 for eliminating leakage current of full-bridge TLIs and Rule 2 for
eliminating leakage current of half-bridge TLIs have been discussed in Chaps. 3
and 4, respectively. This chapter focuses on Rule 3 used in common-ground TLIs.
Common-ground TLIs mean that the neutral line of the grid is directly connected to
the negative terminal of the PV output terminal. According to Rule 3, the total CMV
uCM_tot of common-ground TLIs is zero, so common-ground TLIs have the potential
of the best CMV performance.

Keywords Transformerless PV grid-connected inverter · Common-ground ·

Capacitor-based · Inductor-based

5.1 Capacitor-Based Common-Ground TLIs

The challenge of the common ground TLI topology is how to provide negative
voltage or negative current during the grid negative half period. The implementation
measures of common-ground structure can be classified into two categories, that
is, capacitor-based [1–6] and inductor-based circuits [7–11]. This section discusses
the circuit structures, operating principle, and characteristics of capacitor-based
common-ground TLIs.

5.1.1 Capacitor-Based Common-Ground Inverter I

1. Operating principle

The circuit structure of the first common-ground transformerless grid-connected

inverter (CGT-I) is shown in Fig. 5.1a [1], the PV negative terminal is directly
connected to the neutral line of the grid. There are four power switches and a capac-
itor C in CGT-I, and the modulation strategy is illustrated in Fig. 5.1b. It is worth
mentioning that switches S1 and S2 are working complementarily with dead time,

© The Editor(s) (if applicable) and The Author(s), under exclusive license 189
to Springer Nature Singapore Pte Ltd. 2021
H. Xiao and X. Wang, Transformerless Photovoltaic Grid-Connected Inverters,
CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-8525-8_5
190 5 Common-Ground Transformerless Grid-Connected Inverters

(a) (b)
vM vtri
ωt

D3
Upv S1 S1 ωt
Cdc D1 Lg S2 ωt
S3 1
PV S4 S3 ωt
ug
S2 C S4 ωt
D2
N D4 u1N ωt

Fig. 5.1 CGT-I grid-connected inverter, a Main circuit, b Modulation strategy

and switches S3 and S4 are complementary with each other as well. As a result, the
output voltage u1N is a three-level voltage with unipolar SPWM characteristic.
There are four operating modes according to the polarities of the grid voltage and
grid-in current when the power factor of CGT-I is equal to 1, as shown in Fig. 5.2.
It is necessary to point out that the voltage on capacitor C is half of the input DC
voltage U pv . Mode 1 and Mode 2 in Fig. 5.2a, b are modes in positive half period of
the grid, respectively; symmetrically, Mode 3 and Mode 4 in Fig. 5.2c, d belong to
negative half period of the grid.

(a) (b)
D3 D3
Upv S1 Upv S1
Cdc D1 Lg ig Cdc D1 Lg ig
S3 S3
PV S4 ug PV S4 ug
S2 C S2 C
D2 D2
D4 D4

(c) (d)
D3 D3
Upv S1 Upv S1
Cdc D1 Lg ig Cdc D1 Lg ig
S3 S3
PV S4 ug PV S4 ug
S2 C S2 C
D2 D2
D4 D4

Fig. 5.2 Equivalent circuits of operating modes of CGT-I, a Mode 1, b Mode 2, c Mode 3, d Mode
4
5.1 Capacitor-Based Common-Ground TLIs 191

Mode 1: Refer to Fig. 5.2a; the energy is delivered from the PV side into the grid
through S1 , D4 , C, and the AC filter at this stage. Due to the amplitude and polarity
of the voltage across capacitor C, the amplitude of the output DMV is half the DC
input voltage.
Mode 2: Refer to Fig. 5.2b; at this stage, the freewheeling current flows through
D2 , S3 , and the AC filter, and keeps feeding the grid. It is worth noting that the
potential of the freewheeling path is clamped at the ground.
Mode 3: Refer to Fig. 5.2c; the energy is delivered from capacitor C into the grid
through S2 , S4 , and the AC filter at this stage.
Mode 4: Refer to Fig. 5.2d; the freewheeling current flows through D3 , S2 , and
the AC filter, and keeps feeding the grid. Obviously, it is the freewheeling mode in
the negative half grid period.
According to the analysis of operating modes, capacitor C is charged during
the positive half grid period and discharged during the negative half cycle, so the
capacitance of C should be large enough to keep its voltage constant during the whole
grid cycle. In addition, the voltage across capacitor C has to be maintained at half
the input DC voltage.
2. Simulation Research

In order to further verify the presented theoretical analysis of CGT-I, a 1 kW CGT-I

simulation model has been built in Matlab/Simulink. The simulation parameters are
listed in Table 5.1.
The simulation waveforms of CGT-I with unity power factor are presented in
Figs. 5.3 and 5.4. While Fig. 5.3 shows the simulation waveforms of the grid voltage
ug , grid-in current reference iref , and the grid-in current ig when the power factor is
1, the simulation waveforms of the output voltage u1N with unipolar SPWM charac-
teristic is illustrated in Fig. 5.4a, verifying the amplitude of u1N is indeed maintained
at half the input DC voltage. Obviously, the amplitude of u1N decreases with the
capacitor C charged and discharged during each half grid period, but it only drops a
little because of the large capacitance of C. The switches operate at 15 kHz, so the
harmonic component of u1N concentrates at 15 kHz and its multiples, as is shown in
Fig. 5.4b. The simulation waveforms of the current through S1 , S4 , and D4 are shown
in Fig. 5.5a, b, respectively. It is clear that only the output current flows through S1 ,
S4 , and D4 , proving that the current stress on the switches is small. The operating
period of C is the same as the grid period, but the phase is delayed as shown in
Fig. 5.6. Additionally, CGT-I can operate perfectly when the power factor is not 1 as
shown in Fig. 5.7.

Table 5.1 Simulation parameters of 1 kW CGT-I

Parameter Value Parameter Value
Input voltage U pv /V 680 Switching frequency f s /kHz 15
Grid voltage ug /V 220 Capacitor C/µF 1100
Grid frequency/Hz 50 Filter inductor L f /mH 8
Rated power P/W 1000 PV panel parasitic capacitor C pv /nF 50
192 5 Common-Ground Transformerless Grid-Connected Inverters

ug:[100V/div]

ig:[4A/div]
iref:[4A/div]
0

t[10ms/div]

Fig. 5.3 Simulation waveforms of grid voltage and grid-in current of CGT-I with unity power factor

(a) (b)
A[50V/div]
ig:[4A/div]
0

ug:[100V/div]

u1N:
[100V/div]
0

0
t[5ms/div] 50Hz 15kHz 30kHz

Fig. 5.4 Simulation waveforms of output voltage U1N , a Time domain, b Frequency domain

(a) (b)

ig:[4A/div] ig:[4A/div]
0 0

ug:[100V/div] ug:[100V/div]

iS1:[2A/div] iS4:[2A/div]

0 0

iD4:[2A/div]
t[5ms/div] t[5ms/div]

Fig. 5.5 Simulation waveforms of switches current, a Current waveform of S1 , b Current

waveforms of S4 and D4
5.1 Capacitor-Based Common-Ground TLIs 193

Fig. 5.6 Simulation

waveforms of voltage across
C ig:[4A/div]
0

ug:[100V/div]

uC:[10V/div]

310 t[5ms/div]

Fig. 5.7 Simulation

waveforms of grid voltage
and grid-in current of CGT-I
with non-unity power factor

ig:[4A/div]
0

ug:[100V/div]
t[5ms/div]

5.1.2 Capacitor-Based Common-Ground Inverter II

As analyzed in Sect. 5.1, the capacitor C in CGT-I can only be charged during
the positive half grid period and discharged during the negative half grid period.
Therefore, it needs the large capacitor C and long time to be charged, which leads to
bigger capacitor volume and shorter lifetime. In order to reduce capacitor volume,
the virtual DC bus inverter (VDCBI) which capacitor can be charged and discharged
at high frequency was proposed in [2].
1. Operating principle

The circuit structure of the second common-ground transformerless grid-connected

inverter (CGT-II) is shown in Fig. 5.8a, which is also called VDCBI [2]. Different
from CGT-I, except for the capacitor C 1 connected to the PV panels forming the real
positive DC bus, another capacitor C 2 connected to the PV panels through S1 and
S3 forming the virtual negative DC bus is added into CGT-II. It is worth mentioning
that while switches S1 and S3 are working simultaneously, switches S1 /S3 and S2 are
working complementarily with dead time and switches S4 and S5 are complementary
194 5 Common-Ground Transformerless Grid-Connected Inverters

(a) (b)
vM vtri
ωt
Upv S1
D1
S 1, S3 ωt
PV C1
S2 S4 S2 ωt
D2 D4
S4 ωt
C2 1
N Lf1 Lf2 S5 ωt
S3 S5
D3 D5 C ug u1N ωt

Fig. 5.8 VDCBI grid-connected inverter, a Main circuit, b Modulation strategy

with each other as well. As a result, the output voltage u1N is a three-level voltage
with unipolar SPWM characteristic.
There are four operating modes according to the polarities of the grid voltage
and grid-in current when the power factor of VDCBI is 1, as shown in Fig. 5.9.
Mode 1 and Mode 2 in Fig. 5.9a, b belong to positive half period of the grid voltage,

(a) (b)

Upv S1 Upv S1
D1 D1

PV C1 PV Cdc
S2 S4 S2 S4
D2 D4 ig D2 D4 ig
C2 iLf1 Lf1 Lf2 C2 iLf1 Lf1 Lf2
N N
S3 S5 S3 S5
D3 D5 ug D3 D5 ug
C C

(c) (d)

Upv S1 Upv S1
D1 D1

PV Cdc PV Cdc
S2 S4 S2 S4
D2 D4 ig D2 D4 ig
N C2 iLf1 Lf1 Lf2 N C2 iLf1 Lf1 Lf2
S3 S5 S3 S5
D3 D5 ug D3 D5 ug
C C

Fig. 5.9 Equivalent circuits of operating modes of VDCBI, a Mode 1, b Mode 2, c Mode 3, d Mode
4
5.1 Capacitor-Based Common-Ground TLIs 195

respectively; symmetrically, Mode 3 and Mode 4 in Fig. 5.9c, d work in negative

half period of the grid voltage.
Mode 1: Refer to Fig. 5.9a; the energy is delivered from the PV side into the grid
through S1 , S4 , and the AC filter at this stage. Simultaneously, C 2 is charged by the
input DC voltage U pv through S1 and D3 .
Mode 2: Refer to Fig. 5.9b; at this stage, the freewheeling current flows through
S3 , D5 , and the AC filter, and keeps feeding the grid. C 2 continues to be charged by
the input DC voltage U pv through S1 and S3 .
Mode 3: Refer to Fig. 5.9c; the energy is delivered from capacitor C 2 into the grid
through S2 , S5 , and the AC filter at this stage.
Mode 4: Refer to Fig. 5.9d; the freewheeling current flows through S5 , D3 , and the
filter, and keeps feeding the grid. C 2 restarts to be charged by the input DC voltage
U pv through S1 and D3 .
According to the analysis of operating modes, the DMV and CMV in each mode
of VDCBI are listed in Table 5.2. Note that the voltage u2N is clamped at the ground.
It is revealed from the analysis of operating modes that a small capacitor C 2 has
the capability to keep the grid voltage constant because C 2 operates at switching
frequency. In Mode 4, the charging current and the freewheeling current both flow
through D3, which leads to large current stress on it. More specifically, the pre-charge
of C 2 can be accomplished by keeping S1 ON in the standby mode, so the voltage
of C 1 and C 2 are synchronized with U pv , limiting the inrush current.
2. Simulation Research

In order to further verify the presented theoretical analysis of VDCBI, a 500 W

VDCBI simulation model has been built in Matlab/Simulink. The simulation
parameters are listed in Table 5.3.

Table 5.2 DMV and CMV in each mode of VDCBI

Modes u1N u2N uDM uCM uCM_DM uCM_tot
(1) U pv 0 U pv U pv /2 −U pv /2 0
(2) 0 0 0 0 0 0
(3) −U pv 0 −U pv −U pv /2 U pv /2 0
(4) 0 0 0 0 0 0

Table 5.3 Simulation parameters of 500 W VDCBI

Parameter Value Parameter Value
Input voltage U pv /V 400 Capacitor C 2 /µF 940
Grid voltage ug /V, Frequency/Hz 220, 50 Filter inductance L f1 /mH 8
Rated power P/W 500 Filter capacitor C/µF 0.34
Switching frequency f s /kHz 20 Filter inductance L f2 /mH 0.8
Capacitor C 1 /µF 470 PV panel parasitic Capacitor C pv /nF 75
196 5 Common-Ground Transformerless Grid-Connected Inverters

The simulation waveforms of VDCBI with unity power factor are presented in
Figs. 5.10 and 5.11. While Fig. 5.10 shows the simulation waveforms of the grid
voltage ug , grid-in current reference iref , and the grid-in current ig when the power
factor is 1, the simulation waveforms of the output voltage u1N with unipolar SPWM
characteristic is illustrated in Fig. 5.11a. The simulation waveforms of the current
through the S1 and S3 are shown in Fig. 5.12a, b, respectively. It is clear that the
current stress on S1 and S3 is bigger during the negative half grid period.

ug:[100V/div]

ig:[2A/div] iref:[2A/div]
0

t[10ms/div]

Fig. 5.10 Simulation waveforms of grid voltage, grid-in current reference, and grid-in current of
VDCBI with unity power factor

(a) (b)
A[50V/div]
ig:[2A/div]
0

ug:[100V/div]

u1N:
[100V/div]
0

0
t[5ms/div] 50Hz 20kHz 40kHz

Fig. 5.11 Simulation waveforms of output voltage u1N, a Time domain, b Frequency domain
5.1 Capacitor-Based Common-Ground TLIs 197

(a) (b)

ig:[2A/div] ig:[2A/div]
0 0

ug:[100V/div] ug:[100V/div]

iS1:[5A/div] iS3/D3:[5A/div]

0
t[5ms/div] t[5ms/div]

Fig. 5.12 Simulation waveforms of switches current, a Current waveform of S1 , b Current

waveforms of S4 /D4

5.1.3 Capacitor-Based Common-Ground Inverter III

1. Operating principle

The circuit structure of the third common-ground transformerless grid-connected

inverter (CGT-III) is shown in Fig. 5.13a [3, 4], and the PV negative terminal is
directly connected to the neutral line of the grid. There are four power switches, two
diodes, and two capacitors C 1 and C 2 in CGT-III, and the modulation strategy is
illustrated in Fig. 5.13b. It is worth mentioning that switches S1 and S3 are working
complementarily with dead time, and switches S2 and S4 are complementary with
each other as well. As a result, the output voltage u1N is a three-level voltage with
unipolar SPWM characteristic. Compared with CGT-I and VDCBI, CGT-III has the
operation capability when the power factor is not 1.

(a) (b)
vM vtri
ωt
D1 D2
1 Lf Lg S1 ωt
Upv S1 S2 S
4
ug S2 ωt
Cdc C1 D4
S3 ωt
PV D5 Cf
S4 ωt
S3
D3 D6 C2 u1N ωt

Fig. 5.13 CGT-III grid-connected inverter, a Main circuit, b Modulation strategy

198 5 Common-Ground Transformerless Grid-Connected Inverters

(a) (b)
D1 D2 iLf ig D1 D2 iLf ig
Lf Lg Lf Lg
Upv S1 S2 S4 Upv S1 S2 S
4
Cdc C1 D4 ug Cdc C1 D4 ug

PV D5 Cf PV D5 Cf
S3 S3
D3 D6 D3 D6 C2
C2

(c) (d)
D1 D2 iLf ig D1 D2 iLf ig
Lf Lg Lf Lg
Upv S1 S2 S4 Upv S1 S2 S
4
Cdc C1 D4 ug Cdc C1 D4 ug
PV D5 Cf PV D5 Cf
S3 S3
D3 D6 C2 D3 D6 C2

Fig. 5.14 Equivalent circuits of operating modes of CGT-III with unity power factor, a Mode 1,
b Mode 2, c Mode 3, d Mode 4

There are four operating modes according to the polarities of the grid voltage and
grid-in current when the power factor of CGT-III is 1, as shown in Fig. 5.14. Mode 1
and Mode 2 shown in Fig. 5.14a, b belong to positive half period of the grid voltage,
respectively; symmetrically, Mode 3 and Mode 4 shown in Fig. 5.14c, d belong to
negative half period of the grid voltage.
Mode 1: Refer to Fig. 5.14a; the energy is delivered from the PV side into the grid
through S1 , S2 , and the AC filter at this stage. Simultaneously, C 1 is charged by the
input DC voltage U PV through S1 and D6 .
Mode 2: Refer to Fig. 5.14b; at this stage, the freewheeling current flows through
S2 , D3 , and the filter, and keeps feeding the grid. With S1 OFF, C 1 begins to charge
C 2 through D3 and D5 .
Mode 3: Refer to Fig. 5.14c; the energy is delivered from capacitor C 2 into the
grid through S4 and AC filter at this stage. Same as Mode 1, C 1 is re-charged by U PV
through S1 and D6 .
Mode 4: Refer to Fig. 5.14d; the freewheeling current flows through S3 , D2 , and
filter, and keeps feeding the grid. With S1 OFF and S3 ON, C 1 begins to charge C 2
through S3 and D5 .
There are four new operating modes when the power factor of CGT-III is not 1,
as shown in Fig. 5.15. Compared with Fig. 5.14, Mode 2 and Mode 4 with non-unity
power factor is the same as that with unity power factor. Differences mainly reflected
in Mode 1and Mode 3, and the reactive energy is exchanged between the grid and
C 2 with negative grid voltage and positive grid-in current, as is shown in Fig. 5.15a;
5.1 Capacitor-Based Common-Ground TLIs 199

(a) (b)
D1 D2 iLf ig D1 D2 iLf ig
Lf Lg Lf Lg
Upv S1 S2 S4 Upv S1 S2 S4
Cdc C1 D4 ug Cdc C1 D4 ug
PV D5 Cf PV D5 Cf
S3 S3
D3 D6 C2 D3 D6 C2

(c) (d)
D1 D2 iLf ig D1 D2 iLf ig
Lf Lg Lf Lg
Upv S1 S2 S 4 Upv S1 S2 S
4
Cdc C1 D4 ug Cdc C1 D4 ug
PV D5 Cf PV D5 Cf
S3 S3
D3 D6 C2 D3 D6 C2

Fig. 5.15 Equivalent circuits of new operating modes of CGT-III with non-unity power factor,
a Mode 1, b Mode 2, c Mode 3, d Mode 4

conversely, the reactive energy is exchanged between the grid, C 2 , and C dc , as is

shown in Fig. 5.15c.
According to the analysis of operating modes with unity power factor, C 1 is
charged by U pv in Mode 3, and then charges C 2 to keep the output voltage constant
in Mode 4. The two transmissions of energy incur a certain amount of loss, and the
charging and freewheeling current also results in large current stress on S1 and S3
during the negative grid period.
2. Simulation Research

In order to further verify the presented theoretical analysis of CGT-III, a 500 W CGT-
III simulation model has been built in Matlab/Simulink. The simulation parameters
are listed in Table 5.4.
The simulation waveforms of CGT-III with unity power factor are presented in
Figs. 5.16 and 5.17. While Fig. 5.16 shows the simulation waveforms of the grid
voltage ug and the grid-in current ig when the power factor is 1, the simulation

Table 5.4 Circuit parameters of the 500 W CGT-III topology

Parameter Value Parameter Value
Input voltage U pv /V 400 Capacitor C 2 /µF 330
Grid voltage ug /V, Frequency/Hz 220, 50 Filter inductance L f /mH 4
Rated power P/W 500 Filter inductance L g /mH 2
Switching frequency f s /kHz 24 Filter capacitor C f /µF 4.7
Capacitor C 1 /µF 220 PV panel parasitic capacitor C pv /nF 75
200 5 Common-Ground Transformerless Grid-Connected Inverters

ug:[100V/div]

ig:[2A/div]
0

t[10ms/div]

Fig. 5.16 Simulation waveforms of grid voltage and grid-in current of CGT-III with unity power
factor

(a) (b)
A[50V/div]
ig:[2A/div]
0

ug:[100V/div]

u1N:
[100V/div]
0

0
t[5ms/div] 50Hz 24kHz 48kHz

Fig. 5.17 Simulation waveforms of output voltage u1N, a Time domain, b Frequency domain

waveforms of the output voltage u1N with unipolar SPWM characteristic is illustrated
in Fig. 5.17a. The switches operate at 24 kHz, so the harmonic component of u1N
concentrates at 24 kHz and its multiples, as is shown in Fig. 5.17b. The simulation
waveforms of the current through S1 and S3 are shown in Fig. 5.18a, b, respectively.
The charging current into C 1 flows through S1 , and both the freewheeling current
and the charging current into C 2 flows through S3 . As a result, the current stress on
S1 and S3 is relatively high.
The simulation waveforms of the grid voltage and grid-in current waveforms of
CGT-III with non-unity power factor are presented in Fig. 5.19, which proves that
CGT-III can operate with good output characteristics when the power factor is not 1.
5.1 Capacitor-Based Common-Ground TLIs 201

(a) (b)

ig:[2A/div] ig:[2A/div]
0 0

ug:[100V/div] ug:[100V/div]

iS3:[5A/div]
iS1:[5A/div]
iD3:[5A/div]
0 0
t[5ms/div] t[5ms/div]

Fig. 5.18 Simulation waveforms of switches current, a Current waveform of S1 , b Current

waveforms of S3 /D3

Fig. 5.19 Simulation

waveforms of grid voltage
and grid-in current of
CGT-III with non-unity
power factor
ig:[2A/div]
0

ug:[100V/div]

5.1.4 Capacitor-Based Common-Ground Inverter IV

1. Operating principle

The circuit structure of the fourth common-ground transformerless grid-connected

inverter (CGT-IV) is shown in Fig. 5.20a [5], and the PV negative terminal is directly
connected to the neutral line of the grid. There are four power switches, a diode, and
a capacitor C 1 in CGT-IV, and the modulation strategy is illustrated in Fig. 5.20b.
It is worth mentioning that switches S1 and S2 are working complementarily with
dead time, and switches S3 and S4 are complementary working as well. As a result,
the output voltage u1N is a three-level voltage with unipolar SPWM characteristic.
Same as CGT-III, CGT-IV has the operation capability when the power factor is not
1 as well.
There are four operating modes according to the polarities of the grid voltage and
grid-in current when the power factor of CGT-IV is 1, as shown in Fig. 5.21. Mode 1
202 5 Common-Ground Transformerless Grid-Connected Inverters

(a) (b)
vM vtri
ωt
D1 D3
1 Lf S1 ωt
Upv S1 S3 S4
ug S2 ωt
Cdc D4
C1 S3 ωt
PV Cf
S4 ωt
S2
D2 D5 u1N ωt
N

Fig. 5.20 CGT-IV grid-connected inverter, a Main circuit, b Modulation strategy

(a) (b)
D1 D3 iLf ig D1 D3 iLf ig
Lf Lf
Upv S1 S3 S4 Upv S1 S3 S4
Cdc D4 ug Cdc D4 ug
C1 C1
PV Cf PV Cf
S2 S2
D2 D5 D2 D5

(c) (d)
D1 D3 iLf ig D1 D3 iLf ig
Lf Lf
Upv S1 S 3 S4 Upv S1 S 3 S4
Cdc D4 ug Cdc D4 ug
C1 C1
PV Cf PV Cf
S2 S2
D2 D5 D2 D5

Fig. 5.21 Equivalent circuits of operating modes of CGT-IV with unity power factor, a Mode 1,
b Mode 2, c Mode 3, d Mode 4

and Mode 2 in Fig. 5.21a, b are the modes in positive half period of the grid voltage;
symmetrically, Mode 3 and Mode 4 in Fig. 5.21c, d belong to negative half period
of the grid voltage.
Mode 1: Refer to Fig. 5.21a; the energy is delivered from the PV side into the grid
through S1 , S3 , and the AC filter at this stage. Simultaneously, C 1 is charged by the
input DC voltage U PV through S1 and D5 .
Mode 2: Refer to Fig. 5.21b; at this stage, the freewheeling current flows through
C dc , S1 , C 1 , D4 , and AC filter, and keeps feeding the grid with the output voltage u1N
clamped to zero. Different from other topologies, except for switches and diodes, the
capacitors are included in the freewheeling loop.
5.1 Capacitor-Based Common-Ground TLIs 203

(a) (b)
D1 D3 iLf ig D1 D3 iLf ig
Lf Lf
Upv S1 S 3 S4 Upv S1 S 3 S4
Cdc D4 ug Cdc D4 ug
C1 C1
PV Cf PV Cf
S2 S2
D2 D5 D2 D5

(c) (d)
D1 D3 iLf ig D1 D3 iLf ig
Lf Lf
Upv S1 S 3 S4 Upv S1 S 3 S4
Cdc D4 ug Cdc D4 ug
C1 C1
PV Cf PV Cf
S2 S2
D2 D5 D2 D5

Fig. 5.22 Equivalent circuits of operating modes of CGT-IV with non-unity power factor, a Mode
1, b Mode 2, c Mode 3, d Mode 4

Mode 3: Refer to Fig. 5.21c; the energy is delivered from capacitor C 1 into the
grid through S2 , S4 , and the AC filter at this stage.
Mode 4: Refer to Fig. 5.21d; the freewheeling current flows through S4 , D5 , and
the AC filter, and keeps feeding the grid. Same as Mode 1, C 1 is re-charged by U PV
through S1 and D5 .
There are four new operating modes when the power factor of CGT-IV is not 1,
as shown in Fig. 5.22. Compared with Fig. 5.21, Mode 2 and Mode 4 with non-
unity power factor are the same as that with unity power factor. Differences mainly
reflected in Mode 1 and Mode 3, and the reactive energy is exchanged between the
grid and C 1 with negative grid voltage and positive grid-in current, as is shown in
Fig. 5.22a; conversely, the reactive energy is exchanged between the grid, C 1 , and
C dc , as is shown in Fig. 5.22c.
According to the analysis of operating modes with unity power factor, the free-
wheeling current flows through C 1 in Mode 2. Therefore, C 1 is charged during the
positive half grid period, leading to the voltage across C 1 higher than the input voltage
U pv . Consequently, in this situation, the modes in the negative half grid period are
no more consistent with that shown in Fig. 5.21c, d, and two new modes will appear
between Mode 2 and Mode 3 in Fig. 5.21, as is shown in Fig. 5.23a, b. The energy is
delivered from capacitor C 1 into the grid and the DC side, as is shown in Fig. 5.23a.
With S2 OFF, the freewheeling current flows through S4 , C 1 , and D1 , and keeps
feeding the DC side, as is shown in Fig. 5.23b. Once the voltage across C 1 is equal to
U pv , the circuit continues to operate in Mode 3 and Mode 4, as is shown in Fig. 5.21c,
d.
It is also revealed from the analysis of operating modes that the energy is delivered
from capacitor C 1 into the grid in Mode 3, and then C 1 is charged by U pv in Mode
204 5 Common-Ground Transformerless Grid-Connected Inverters

(a) (b)
D1 D3 iLf ig D1 D3 iLf ig
Lf Lf
Upv S1 S3 S4 Upv S1 S3 S4
Cdc D4 ug Cdc D4 ug
C1 C1
PV Cf PV Cf
S2 S2
D2 D5 D2 D5

Fig. 5.23 Additional equivalent circuits of operating modes of CGT-IV with unity power factor,
a Mode 1, b Mode 2

4 during the negative grid period. As the charging current flows through S1 and D5 ,
the current stress of them is large.
2. Simulation Research

In order to further verify the presented theoretical analysis of CGT-IV, a 1 kW CGT-

IV simulation model has been built in Matlab/Simulink. The simulation parameters
are listed in Table 5.5.
The simulation waveforms of CGT-IV with unity power factor are presented in
Figs. 5.24 and 5.25. While Fig. 5.24 shows the simulation waveforms of the grid
voltage ug and the grid-in current ig , the simulation waveforms of the output voltage
u1N with unipolar SPWM characteristic are illustrated in Fig. 5.25a. For the switches
to operate at 50 kHz, the harmonic component of u1N concentrates at 50 kHz and its
multiples, as is shown in Fig. 5.25b.
As can be observed in Fig. 5.26, the voltage across C 1 is higher than the DC bus
voltage with the energy delivering into it during the positive grid period; once the
grid voltage ug is negative, C 1 discharged until the input voltage. With the voltage
across C 1 continuing to decrease, C 1 is conversely charged by U pv , which also
accounts for the asymmetry of the output voltage u1N . The simulation waveforms of
the current through S1 /D1 and D5 are shown in Fig. 5.27a, b, respectively. It is clear
that the charging current flows through S1 , and both the charging current and the
freewheeling current flow through D5 , which result in large current stress on them.
Additionally, CGT-IV has the operation capability when the power factor is not 1 as
well, and the simulation waveforms of the grid voltage ug and the grid-in current ig
under non-unity power factor are shown in Fig. 5.28.

Table 5.5 Simulation parameters of 1 kW CGT-IV

Parameters Value Parameters Value
Input voltage U pv /V 400 Capacitor C 1 /µF 470
Grid voltage ug /V, Frequency/Hz 230, 50 Filter inductance L f /mH 0.35
Rated power P/W 1000 Filter capacitor C f /µF 4.7
Switching frequency f s /kHz 50 PV panel parasitic capacitor C pv /nF 75
5.1 Capacitor-Based Common-Ground TLIs 205

ug:[100V/div]

ig:[4A/div]
0

t[10ms/div]

Fig. 5.24 Simulation waveforms of grid voltage and grid-in current of CGT-IV with unity power
factor

(a) (b)

A[50V/div]
ig:[4A/div]
0

ug:[100V/div]

u1N:
[100V/div]
0

0
t[5ms/div] 50Hz 50kHz 100kHz

Fig. 5.25 Simulation waveforms of output voltage u1N, a Time domain, b Frequency domain

Fig. 5.26 Simulation

waveform of the voltage
across C 1 ig:[4A/div]
0

ug:[100V/div]

uC1:[5V/div]

400
t[5ms/div]
206 5 Common-Ground Transformerless Grid-Connected Inverters

(a) (b)

ig:[4A/div] ig:[4A/div]
0 0

ug:[100V/div] ug:[100V/div]

iS1:[10A/div] iD5:[10A/div]
0
iD1:[10A/div] 0
t[5ms/div] t[5ms/div]

Fig. 5.27 Simulation waveforms of switches current, a Current waveform of S1 /D1 , b Current
waveforms of D5

Fig. 5.28 Simulation

waveforms of grid voltage
and grid-in current of
CGT-IV with non-unity
power factor ig:[4A/div]

ug:[100V/div]

The intermediate capacitors of the above common-ground TLIs have the capability
of operating at switching frequency during the negative grid period, which brings the
high reduction of the capacitor volume. Despite that, the high current stress on some
switches is a crucial challenge required to be studied and solved in capacitor-based
common-ground TLIs.

5.2 Inductor-Based Common-Ground TLIs

Capacitor-based common-ground TLIs with capacitors delivering energy have been

discussed in Sect. 5.1. The above topologies overcome the difficulty of providing
negative voltage or negative current during the grid negative half period. Neverthe-
less, they can only work in buck mode with high input DC voltage. This is the major
limitation in low-power distributed generation applications. Inductors are used as the
5.2 Inductor-Based Common-Ground TLIs 207

middle stage and own the ability of buck/boost in inductive-based common-ground

TLIs. Early inductive-based common-ground TLIs are mostly two-stage inverters
[7–9], which have negative influence on the improvement of inverter efficiency. In
order to solve this problem, single-stage inductive-based common-ground TLIs that
integrate buck/boost structures have been proposed [10–13].

5.2.1 Karschny Common-Ground Inverter

Karschny common-ground inverter was first patented by Karschny Dietrich in 1998

[11]. It is worth mentioning that Karschny common-ground inverter can work in
buck/boost mode with only an inductor storing the energy.
The circuit structure of the conventional Karschny common-ground transformer-
less grid-connected inverter, which is also called the flying inductor-based common-
ground TLI, is shown in Fig. 5.29a. There are five power switches, two diodes, and
one inductor in Karschny inverter. The modulation strategy is illustrated in Fig. 5.29b.
It is worth noting that the switches S3 –S5 operate at grid frequency. During the posi-
tive grid period, the Karschny inverter works in two-switch forward buck/boost mode
with S3 OFF, S4 and S5 ON, and S1 and S2 operating at high frequency; symmetri-
cally, the inverter works in two-switch reverse buck/boost mode with S2 and S3 ON,
S4 and S5 OFF, and only S1 operating at high frequency.
There are four operating modes when the power factor of Karschny inverter is 1,
as shown in Fig. 5.30. Mode 1 and Mode 2 in Fig. 5.30a, b are the modes of positive
half period of the grid voltage; symmetrically, Mode 3 and Mode 4 in Fig. 5.30c, d
are the modes of negative half period of the grid voltage.

(a) (b)
vM vtri
ωt
S1 D1
D3
1 S1 ωt
Upv
D6 Lf S2 ωt
L1 S3 ωt
S3
PV Cdc D7 D4 ug
S4 ωt
S5 ωt
S4 Cf
S2 S5
N D5 u12 ωt
D2 2

Fig. 5.29 Karschny common-ground inverter, a Main circuit, b Modulation strategy

208 5 Common-Ground Transformerless Grid-Connected Inverters

(a) (b)

S1 D1 S1 D1
D3 ig D3 ig
Upv Upv
D6 Lf D6 Lf
L1 S3 L1 S3
PV Cdc D7 D4 ug PV Cdc D7 D4 ug

S4 Cf S4 Cf
S2 S5 S2 S5
N D2 D5 N D2 D5

(c) (d)

S1 D1 S1 D1
D3 ig D3 ig
Upv Upv
D6 Lf D6 Lf
L1 S3 L1 S3
PV Cdc D7 D4 ug PV Cdc D7 D4 ug

S4 Cf S4 Cf
S2 S5 S2 S5
N D2 D5 N D2 D5

Fig. 5.30 Equivalent circuits of operating modes of Karschny common-ground inverter, a Mode
1, b Mode 2, c Mode 3, d Mode 4

Mode 1: Refer to Fig. 5.30a; at this stage, the charging current flows through S1
and S2 into the inductor L 1 . The energy stored in L f and C f keeps feeding the grid.
Mode 2: Refer to Fig. 5.30b; the energy is delivered from inductor L 1 into the grid
through S4 , S5 , D6 , and D7 at this stage. Simultaneously, Karschny inverter works in
two-switch forward buck/boost mode with L f and C f charged.
Mode 3: Refer to Fig. 5.30c; same as in Mode 1, the charging current flows through
S1 and S2 into the inductor L 1 . The energy stored in L f and C f keeps feeding the grid.
Mode 4: Refer to Fig. 5.30d; the energy is delivered from inductor L 1 into the
grid through S2 , S3 , and D6 at this stage. Simultaneously, Karschny inverter works
in two-switch backward buck/boost mode with L f and C f charged.
According to the analysis of operating modes, the input voltage of Karschny
inverter is lower than the peak grid voltage in buck/boost mode; however, the full-
power processing has an influence in improving efficiency.
5.2 Inductor-Based Common-Ground TLIs 209

5.2.2 Flying Inductor Transformerless Inverter

Based on one inductor, same as Karschny inverter, the second flying inductor
transformerless inverter (FITLI) was proposed in [12].
The structure of the flying inductor transformerless inverter (FITLI) is shown
in Fig. 5.31a. There are five power switches and one inductor in FITLI, and the
modulation strategy is illustrated in Fig. 5.31b. Note that the switches S2 , S4 , and S5
operate at grid frequency. During the positive grid period, FITLI works in two-switch
forward buck/boost mode with S2 and S5 ON, S4 OFF, while S1 and S3 operating
at high frequency. Symmetrically, FITLI works in two-switch backward buck/boost
mode with S3 and S4 ON, S2 and S5 OFF, and only S1 operating at high frequency.
There are four operating modes according to the polarities of the grid voltage and
grid-in current of FITLI, as shown in Fig. 5.32. Mode 1 and Mode 2 in Fig. 5.32a, b
are the modes of positive half period of the grid voltage; symmetrically, Mode 3 and
Mode 4 in Fig. 5.32c, d are the modes of negative half period of the grid voltage.
Mode 1: Refer to Fig. 5.32a; at this stage, the charging current flows through S1
and S3 into the inductor L 1 . The energy stored in L f and C f keeps feeding the grid.
Mode 2: Refer to Fig. 5.32b; the energy is delivered from inductor L 1 into the grid
through S2 and S5 at this stage. Simultaneously, FITLI works in two-switch forward
buck/boost mode with L f and C f charged.
Mode 3: Refer to Fig. 5.32c; same as in mode 1, the charging current flows through
S1 and S3 into the inductor L 1 . The energy stored in L f and C f keeps feeding the grid.
Mode 4: Refer to Fig. 5.32d; the energy is delivered from inductor L 1 into the
grid through S3 and S4 at this stage. Simultaneously, FITLI works in two-switch
backward buck/boost mode with L f and C f charged.
According to the analysis of operating modes, FITLI works in buck/boost mode,
and thus the full-power processing has an influence in improving efficiency as well.

(a) (b)
vM vtri
ωt
S4

S1 ωt
L1 1 Lf S2 ωt
Upv S1 S5 ωt
S3 S3
ug ωt
S4
PV Cdc S5 ωt
S2 Cf
v12 ωt
N 2

Fig. 5.31 FITLI grid-connected inverter, a Main circuit, b Modulation strategy

210 5 Common-Ground Transformerless Grid-Connected Inverters

(a) S4 (b) S4
ig ig
L1 Lf L1 Lf
Upv S1 S5 Upv S1 S5
S3 ug S3 ug
PV Cdc S2 PV Cdc S2
Cf Cf
N N

(c) (d)
S4 S4
ig ig
L1 Lf L1 Lf
Upv S1 S5 Upv S1 S5
S3 ug S3 ug
PV Cdc S2 PV Cdc S2
Cf Cf
N N

Fig. 5.32 Equivalent circuits of operating modes of FITLI, a Mode 1, b Mode 2, c Mode 3, d Mode
4

As is analyzed in Sects. 5.2.1 and 5.2.2, Karschny common-ground inverter

and FITLI both have the capability of working in buck/boost mode, but the full-
power processing becomes the main limitation in efficiency improvement. In order to
achieve high frequency, the Aalborg transformerless inverter (ATLI) with part-power
processing in buck/boost mode has been proposed in [13].

5.2.3 Aalborg Transformerless Inverter

The Aalborg transformerless inverter (ATLI) was first proposed by the researchers at
the University of Aalborg in Denmark. This section discusses the circuit structures,
operation characteristics, and simulation verification.
1. Operating principle

The symmetrical circuit structure of the Aalborg transformerless inverter (ATLI) is

shown in Fig. 5.33a [13]. The PV neutral terminal is directly connected to the neutral
line of the grid. There are six power switches, four diodes, and two inductors L p
and L n in ATLI. The modulation strategies operating in buck and boost mode are
illustrated in Fig. 5.33b, c, respectively. When the DC capacitor voltage is larger than
5.2 Inductor-Based Common-Ground TLIs 211

(a)
D1 D9 D3
1
Lp L
S1 S3
S2 D2
D7
Cdc1 C ug
Upv
2
PV Cdc2 S5 D5
D8
S4 S6

Ln D10 D
D4 6
(b) (c)
vM vtri vM vtri
ωt ωt

S1 ωt S1 ωt
S2 ωt S2 ωt
S3 ωt S3 ωt
S4 ωt S4 ωt
S5 ωt S5 ωt
S6 ωt S6 ωt
u12 ωt u12 ωt

Fig. 5.33 ATLI grid-connected inverter, a Main circuit, b Buck mode, c Boost mode

the amplitude of grid voltage, ATLI works in buck mode; symmetrically, when the
DC capacitor voltage is smaller than the amplitude of grid voltage, ATLI works in
boost mode.
There are four operating modes according to the polarities of the grid voltage
and grid-in current when ATLI works in buck mode, as shown in Fig. 5.34. Mode
1 and Mode 2 in Fig. 5.34a, b belong to positive half period of the grid voltage;
symmetrically, Mode 3 and Mode 4 in Fig. 5.34c, d belong to negative half period
of the grid voltage.
Mode 1: Refer to Fig. 5.34a; the energy is delivered from the PV side into the
grid through S1 , S3 , and the AC filter at this stage. Simultaneously, L p is charged by
C dc1 .
Mode 2: Refer to Fig. 5.34b; at this stage, the freewheeling current flows through
S3 , D7 , and the AC filter, and keeps feeding the grid.
212 5 Common-Ground Transformerless Grid-Connected Inverters

(a) (b)
D1 D9 D3 ig D1 D9 D3 ig
Lp L Lp L
S1 S3 S1 S3
S2 D2 S2 D2
Cdc1 D7 C ug Cdc1 D7 C ug
Upv Upv

PV Cdc2 D8 S5 D5 PV Cdc2 D8 S5 D5
S4 S6 S4 S6

Ln D10 D Ln D10 D
D4 6 D4 6

(c) (d)
D1 D9 D3 ig D1 D9 D3 ig
Lp L Lp L
S1 S3 S1 S3
D7 S2 D2 D7 S2 D2
Cdc1 C ug Cdc1 C ug
Upv Upv

PV Cdc2 S5 D5 PV Cdc2 S5 D5
D8 D8
S4 S6 S4 S6

Ln D10 D Ln D10 D
D4 6 D4 6

Fig. 5.34 Equivalent circuits of ATLI working in buck mode, a Mode 1, b Mode 2, c Mode 3,
d Mode 4

Mode 3: Refer to Fig. 5.34c; symmetrical to Mode 1, the energy is delivered from
the PV side into the grid through S4 , S6 , and the AC filter at this stage. Simultaneously,
L n is charged by C dc2 .
Mode 4: Refer to Fig. 5.34d; symmetrical to Mode 2, the freewheeling current
flows through S6 , D8 , and the AC filter, and keeps feeding the grid. Obviously, it is
the freewheeling mode in the negative half grid period.
There are four operating modes according to the polarities of the grid voltage
and grid-in current when ATLI works in boost mode, as shown in Fig. 5.35. Mode
1 and Mode 2 in Fig. 5.35a, b belong to positive half period of the grid voltage,
respectively; symmetrically, Mode 3 and Mode 4 in Fig. 5.35c, d are the modes of
negative half period of the grid.
Mode 1: As shown in Fig. 5.35a, it is the positive half grid cycle inductance energy
storage mode. Switches S1 and S2 are turned ON and the inductor L p is charged. The
filter capacitor C is discharged to maintain the current injected into the grid.
Mode 2: As shown in Fig. 5.35b, it is the positive half grid cycle energy transfer
mode. Switch S2 is turned OFF and switches S1 and S3 are turned ON. The inductor
L p is discharged and the current flows through S1 , S3 , and the filter to the power grid.
5.2 Inductor-Based Common-Ground TLIs 213

(a) (b)
D1 D9 D3 ig D1 D9 D3 ig
Lp L Lp L
S1 S3 S1 S3
S2 D2 S2 D2
Cdc1 D7 C ug Cdc1 D7 C ug
Upv Upv

PV Cdc2 D8 S5 D5 PV Cdc2 D8 S5 D5
S4 S6 S4 S6

Ln D10 D Ln D10 D
D4 6 D4 6

(c) (d)
D1 D9 D3 ig D1 D9 D3 ig
Lp L Lp L
S1 S3 S1 S3
D7 S2 D2 D7 S2 D2
Cdc1 C ug Cdc1 C ug
Upv Upv

PV Cdc2 S5 D5 PV Cdc2 S5 D5
D8 D8
S4 S6 S4 S6

Ln D10 D Ln D10 D
D4 6 D4 6

Fig. 5.35 Equivalent circuits of ATLI working in boost mode, a Mode 1, b Mode 2, c Mode 3,
d Mode 4

Mode 3: As shown in Fig. 5.35c, it is the negative half grid cycle inductance energy
storage mode. Switches S4 and S5 are turned ON and the inductor L n is charged. The
filter capacitor C is discharged to maintain the current injected into the grid.
Mode 4: As shown in Fig. 5.35d, it is the negative half grid cycle energy transfer
mode. Switch S5 is turned OFF and switches S4 and S6 are turned ON. The inductor
L n is discharged and the current flows through S4 , S6 , and the filter to the power grid.
According to the analysis of operating modes, ATLI works in buck/boost mode
with only processing a fraction of the total power during the grid period. As a result,
the improvement of efficiency of ATLI can be achieved.
2. Simulation Research
In order to further verify the presented theoretical analysis of ATLI, a 2 kW ATLI
simulation model has been built in Matlab/Simulink. The simulation parameters are
listed in Table 5.6.
The simulation waveforms of ATLI with unity power factor are presented in
Figs. 5.36 and 5.37. ATLI works in buck mode in this simulation. While Fig. 5.36
shows the simulation waveforms of the grid voltage ug and the grid-in current ig
214 5 Common-Ground Transformerless Grid-Connected Inverters

Table 5.6 Simulation parameters of 2 kW ATLI

Parameter Value Parameter Value
Input voltage U pv /V 700 Inductance L p , L n /mH 0.6
Grid voltage ug /V, Frequency/Hz 220, 50 Filter capacitor C 1 /µF 4.7
Rated power P/W 2000 Filter inductance L f /mH 0.6
Switching frequency f s /kHz 40 PV panel parasitic capacitor C pv /nF 75

ug:[100V/div]

ig:[10A/div]
0

t[10ms/div]

Fig. 5.36 Simulation waveforms of grid voltage ug and grid-in current ig of ATLI

(a) (b)
A[50V/div]
ig:[10A/div]
0

ug:[100V/div]
u12:[100V/div]

0 0
t[5ms/div] 50Hz 40kHz 80kHz

Fig. 5.37 Simulation waveforms of output voltage U12 , a Time domain, b Frequency domain

when the power factor is 1, the simulation waveforms of the output voltage u12 is
illustrated in Fig. 5.37. The simulation waveforms of the current through L p and L n
are shown in Fig. 5.38a, b, respectively. The energy is delivered from inductor L p into
the grid during the positive grid period, and the energy is delivered from inductor L n
into the grid during the negative grid period.
5.3 Summary 215

(a) (b)

ig:[10A/div] ig:[10A/div]
0 0

ug:[100V/div] ug:[100V/div]

iLp:[5A/div] iLn:[5A/div]

0 0
t[5ms/div] t[5ms/div]

Fig. 5.38 Simulation waveforms of inductors current, a Current waveform of Lp, b Current
waveforms of Ln

5.3 Summary

This chapter discusses the capacitor-based and the inductor-based common-ground

TLIs based on Rule 3, revealing that the common-ground TLIs has the optimal LC
characteristics. Specifically, the inductor-based common-ground TLIs, which can
work in buck/boost mode, are more appropriate for low-power distributed genera-
tion applications. The comparison results of the capacitor-based and the inductor-
based common-ground TLIs are concluded in Tables 5.7 and 5.8, which may provide
reference for other designs.

Table 5.7 Comparison results of capacitor-based common-ground TLIs

Topologies SW/D SW (High frequency) Negative bus capacitance
CGT-I [1] 4/0 4/2 1100 µF@1 kW
CGT-II [2] 5/0 2/3 940 µF@500 W
CGT-III [3, 4] 4/2 2/4 220 µF, 330 µF@500 W
CGT-IV [5] 4/1 2/2 470 µF@1 kW

Table 5.8 Comparison results of inductor-based common-ground TLIs

Topologies Operating mode SW/D SW (High frequency) Negative bus inductance
Karschny [11] Buck/Boost 5/2 2 Not listed [11]
FITLI [12] Buck/Boost 5/0 2 0.3mH@200 W
ATLI [13] Buck/Boost 6/4 1/2 0.6mH@2 kW
216 5 Common-Ground Transformerless Grid-Connected Inverters

References

1. Kadam A, Shukla A (2017) A multilevel transformerless inverter employing ground connection

between pv negative terminal and grid neutral point. IEEE Trans Industr Electron 64(11):8897–
8907
2. Gu YJ, Li WH, Zhao Y et al (2013) Transformerless inverter with virtual DC bus Concept for
cost-effective grid-connected PV power systems. IEEE Trans Power Electron 28(2):793–805
3. Ardashir JF, Sabahi M, Hosseini SH et al (2016) Transformerless inverter with charge pump
circuit concept for PV application. IEEE J Emerg Sel Topics Power Electron, Early Access
4. Ardashir JF, Sabahi M, Hosseini SH et al (2017) A single-phase transformerless inverter
with charge pump circuit concept for grid-tied PV applications. IEEE Trans Industr Electron
64(7):5403–5415
5. Siwakoti YP, Blaabjerg F (2018) Common-ground-type transformerless inverters for single-
phase solar photovoltaic systems. IEEE Trans Industr Electron 65(3):2100–2111
6. Liao ZL, Cao C, Qiu D et al (2019) Single-phase common-ground-type transformerless PV
grid-connected inverters 7:63277–63287
7. Saha S, Sundarsingh VP (1996) Novel grid-connected photovoltaic inverter. IEEE Proc Gener
Trans Distrib 143(2):219–224
8. Funabiki S, Tanaka T, Nishi T, A new buck-boost-operation-based sinusoidal inverter circuit.
In: 2002 power electronics specialists conference, Cairns, pp 1624–1629
9. Prasad BS, Jain S, Agarwal V (2008) Universal single-stage grid-connected inverter. IEEE
Trans Energy Convers 23(1):128–137
10. Araujo SV, Zacharias P, Mallwitz R (2010) Highly efficient single-phase transformerless
inverters for grid-connected photovoltaic systems. IEEE Trans Industr Electron 57(9):3118–
3128
11. Dietrich K. Wechselrichter. DE 19 642 522 C1.2010
12. Azary MT, Sabahi M, Babaei E et al (2018) Modified single-phase single-stage grid-tied flying
inductor inverter with MPPT and suppressed leakage current. IEEE Trans Industr Electron
65(1):221–231
13. Wu W, Ji J, Blaabjerg F (2013) Aalborg Inverter—A new type of “buck in buck, boost in boost”
grid-tied inverter. IEEE Trans Power Electron 30(9):4784–4793
Chapter 6
DC Current Rejection
for Transformerless Grid-Connected
Inverters

Abstract Leakage current eliminating techniques for TLIs have been discussed
from Chaps. 2, 3, 4 and 5 of this book. In distributed TLI-PVPG systems, DC current
in grid-in current is another issue due to the absence of line-frequency transformers at
AC side, which could result in safety risks, such as transformer saturation of upstream
distribution wires, accelerating degradation of insulation layer of electric cables, and
misaction of protection measures. Suppressing methods of DC current injection are
discussed in this chapter in detail.

Keywords Transformerless grid-connected inverter · DC current · Detection and

feedback · Capacitor blocking · Intelligent algorithm

6.1 DC Component in Grid-In Current

6.1.1 Summarizing Analysis of DC Components

Taking a typical single-phase full-bridge grid-connected TLI system as an example in

this section, there are six aspects of causing DC current (DCC), as shown in Fig. 6.1.
It is worth noting that the DC voltage component in the grid belongs to the external
factor of causing DCC, and the rest five aspects can be classified as internal factors.
1. Different properties among power devices

The reasons of resulting in DCC from power devices can be divided into two groups.
(1) Differences in gate driving circuits, for instance, the asymmetric widths of PWM
signals, unequal rising time and falling time of amplifier circuits, different dead
time of bridge switches, and so on.
(2) Various characteristics in power devices, such as conduction voltage drop,
leakage current, junction capacitors, parasitic parameters, etc.

© The Editor(s) (if applicable) and The Author(s), under exclusive license 217
to Springer Nature Singapore Pte Ltd. 2021
H. Xiao and X. Wang, Transformerless Photovoltaic Grid-Connected Inverters,
CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-8525-8_6
218 6 DC Current Rejection for Transformerless …

Power circuit Differences among

power device
characteristics
S1 S3
Sensor drift errors
Upv ig
L1 DC component of
grid voltage
PV Cdc C ug
L2

S2 S4
N

Sampling control
ig_ref

Driving Current ig Signal Signal

KPWM ADC conditioning
signals control conditioning errors

ADC errors

Asymmetric
driving circuit

Fig. 6.1 Factors of DC components

2. Sensing errors

Commonly, Hall Effect based current sensors are used in current detection. It has
errors in practical use. The sensing errors are from two factors, one is the residual
magnetism caused by magnetic hysteresis effect; another one is from potential drift
of Hall elements. It can be seen that the sensing errors are unavoidable, it can be
reduced by using high precision sensor but expensive.
3. Errors of signal conditioning circuits

The purpose of signal conditioning circuits is to match the output signal of sensors
with the input signal of analog-to-digital converters (ADC) in amplitudes. Therefore,
the operational amplifier is popularly used to amplify or minify the detection signals.
However, some technical limitations of the operational amplifier may cause addi-
tional detection errors, such as non-linear region, offset voltage and offset current,
etc.
6.1 DC Component in Grid-In Current 219

4. Resolution errors of ADCs

The reasons resulting in ADC errors can be classified into two categories, i.e. external
factors, and internal factors. For instance, the quality of power supply and ground
noise belong to external factors; internal errors result from nonlinearity of differential
and integral parts, offset and gain errors, and so on. The digit number of resolutions
is usually used to represent the error introduced by the ADC, whose unit is LSB.
5. DC voltage component of the grid

When the grid voltage contains a certain amount of DC voltage component, DCC
will be generated in grid-in current through the filter and line impedance by the DC
voltage component.

6.1.2 Influence of DCC

Once the amplitude of DCC reaches a limitation value, some damages may be
occurred, including but not limited as,
(1) DC magnetic offset in line-frequency transformers, which further causes
magnetic saturation of magnetic core in transformer unsymmetrically. As a
consequence, the distortion of excitation current will be distorted and harmonic
current components increased a lot. It may also generate vibration and noise
of transformers. Finally, the transformer may be damaged and loss will be
increased.
(2) Power wire loss and accelerating the corrosion of the ground cable and ground
electrode.
(3) Eddy current and torque ripples in motor loads, then the motor noise, vibration
and overheating will be unacceptable.

6.1.3 Standards Limitations of DCC

In order to avoid aforementioned damages in power system, some relevant technical

standards and limitations have been filed as the design criteria and testing guidelines.
Several typical Standards are listed in Table 6.1, including the standards and allowed
DCC values.
It can be seen that China, the United States, etc., set the limitation at certain ratio
of rated current. The United Kingdom, Germany, etc. directly set the limitation at
absolute magnitude of DCC. These standards are mandatory complied in associated
areas, inverter manufactures have to follow.
220 6 DC Current Rejection for Transformerless …

Table 6.1 Standards in terms

Countries Standards Maximum DCC
of DCC from different
countries China GB/T 33,593–2017 0.5% of rated output
current
United States IEEE 929–2000 0.5% of rated output
current
Japan IEC 61,727–2004 1% of rated output
current
Germany DIN VDE 0126 1000 mA
England ER G83/1 5 mA
Australia AS 4777.2 5 mA

6.1.4 Quantitative Analysis of DCC

1. Power circuits of TLIs

There are many factors in power circuits discussed in Sect. 6.1.1 that cause the DCC,
but all of them can be represented by the output voltage of the bridge leg. Taking
a bipolar modulation single-phase TLI as example, the effective on-state time of
the switch action during a grid period is accumulated to T (generally less than grid
period), as shown in Fig. 6.2. Where the on-time of positive output voltage is equal
to αT, if the turn-on times of positive and negative output voltage are different, i.e.,
α is not equal to 0.5, DDC will appear in the grid-in current.
Furthermore, the amplitude of DDC can be calculated by FFT (fast Fourier
transform),

Ig0 = 2 · Ir e f · (0.5 − α) (6.1)

where I ref is the reference current amplitude, and α is the ratio of the accumulated
time of positive output levels and total time of effective output levels. For example,
assuming that the inverter power is 3 kW, the grid voltage is 220 V, and α = 0.4995,
as a result, I ref = 3000/220 × 1.414 A = 19.281 A, and I g0 = 2 × I ref × (0.5−α) =

Fig. 6.2 Effective output U

voltage with accumulation T
Udc

-Udc
T
6.1 DC Component in Grid-In Current 221

19 mA, based on (6.1). According to Table 6.1, the asymmetry of power circuits will
fail TLIs on markets of the United Kingdom and Australia; some special measures
have to be adopted to deal with this problem.
2. Sampling circuits of TLIs

Measuring error of grid-in current is decided by the resolution of ADCs, the accuracy
of the current sensor, and the signal conditioning circuit. By summing up, the current
error can be expressed as (6.2),
     
Ig_ max = Ig1  + Ig2  + Ig3  (6.2)

Here, I g represents the total maximum current detection error, and I g1 , I g2 ,

and I g3 represent the detection errors from the ADC resolution, the current sensor,
and the signal conditioning circuit, respectively.
(1) ADC error

Assuming that the sampling error of the ADC is I gs , the inverter overcurrent coef-
ficient is β, the peak-to-peak value of grid-in current is I p−p , and the bit number of
ADC is N, respectively, the detection error I g1 from the ADC is

(1 + β) · I p− p · Igs
Ig1 = (6.3)
2N
Taking a popular DSP TMS320F28335 from TI as example, I gs = ± 1.5LSB
is generally acceptable, i.e., the sampling value error is approximately equal to 1.5
ADC resolution bits. For a 3 kW TLI connected with the grid of 220 V and 50 Hz,
the grid-in current amplitude is calculated as 3000/220 × 1.414 A = 19.281A, then
the calculated detection error I g1 is 18 mA if β = 0.3, and N = 12.
Obviously, the higher the resolution of the ADC is, the smaller the DCC caused
by the ADC. But, the cost will be high.
(2) Sensor error

The DCC is introduced by the detection accuracy of the current sensor, generally,
the allowable error can be expressed as the accuracy level times the capacity range,

Ig2 = FS · X (6.4)

Here, X represents the accuracy level of the current sensor, and FS represents
the maximum capacity range. Taking above 3 kW TLI as example, a Hall current
sensor CSM025NPT5 produced by Nanjing Chahua-Electric is adopted in the TLI,
the accuracy X is 0.1%, and the full-scale FS is 25 × 2 A = 50 A by referring
datasheet. Therefore, the sensor error I g2 is 50 × 0.1% mA = 50 mA.
222 6 DC Current Rejection for Transformerless …

Fig. 6.3 Signal conditioning Vdc

circuit R2 R5

R4 R7
R1 C
R3 R6

(3) Conditioning error

The error of the signal conditioning circuit is mainly dominated by offset voltage
U io and offset current I io of operational amplifiers. Taking an inverse proportional
amplifier circuit as example, the resulted error [1] is represented as,
   
K cs RF
Ig3 = Uio 1 + + Iio R F (6.5)
Au f R1

Here, I g3 represents the current error, R1 is the resistor of negative terminal of

operational amplifiers, RF is the negative feedback resistor, Auf is the amplification
coefficient of the inverse proportional operation circuit, and K cs is the conversion
coefficient from the primary side to the secondary side of the current sensor.
Figure 6.3 illustrates a two-stage conditioning circuit, TL074C with low input
drift and offset current from TI is selected as the operational amplifier. In this figure,
R1 = R4 = R5 = R6 = 10 k, R2 = R3 = 8.2 k, R7 = 300 , C = 0.1 μF, V dc
= 3.3 V, the input offset voltage U io = 3 mV, and offset current I io = 5 pA can be
obtained from the technical datasheet.
Therefore, the conditioning error can be calculated from two steps as bellow,
   
40 8.2 × 103
err1 = 3 × 10−3 × 1 + + 5 × 10 −12
× 8.2 × 10 3
−0.82 10 × 103
= −266 mA (6.6)

40
err2 = [3 × 10−3 × (1 + 1) + 5 × 10−12 × 10 × 103 ] = 293 mA
−1 × (−0.82)
(6.7)

Ig3 = err1 + err2 = 27 mA (6.8)

1. DC components of grid voltage

When the grid voltage contains a certain DC voltage component U g_dc , DCC will be
generated through the filter and line impedance. As shown in Fig. 6.4, the inverter
output voltage is equivalent to an ideal AC voltage source U bridge , which is equal to
the frequency components U g without DC component in the grid voltage; the lumped
impedance of the AC filter, power line and other components among the power lines
is Rs ; and I g is the grid-in current.
Therefore, DCC produced by the DC voltage component in grid-in current can be
expressed as
6.1 DC Component in Grid-In Current 223

Fig. 6.4 Equivalent circuit

Ig Rs
of DC voltage component in
Ug _dc
the grid voltage
Ubridge
Ug

Ug_dc
Ig1 = (6.9)
Rs

Still taking the 3 kW TLI connected with the grid voltage of 220 V and frequency
of 50 Hz as example, if U g_dc = 0.1 V and RS = 10 , then I g1 = 0.1/10 A = 10 mA.
In summary, the maximum DCC can be expressed as
     
Idc_ max =  Ig0  + Ig_ max  +  Ig1  (6.10)

Here, I g_max can be obtained based on (6.2), I g_max = I g1 + I g2 + I g3

= 18 + 50 + 27 mA = 95 mA, finally, I dc_max can be obtained: I dc_max = |I g0 | +
|I g | + |I g1 | = 19 + 95 + 10 mA = 124 mA.
For a 3 kW/220 V grid-connected inverter, the allowed DCC is 3000/220 ×
0.5% mA = 68 mA according to China standard GB/T 33,593–2017 in Table 6.1.
The accumulated DCC from aforementioned parts is 124 mA, it is almost two times
of standard limitation. Therefore, solutions are needed to eliminate DCC injected
into the grid.
Based on operating principles, DCC rejection methods can be classified into three
major categories, detection & feedback methods, capacitor blocking methods, and
intelligent algorithms, as shown in Fig. 6.5. Rest of this chapter will discuss these
methods one by one.

DCCI Suppression

Detection & feedback Capacitors blocking Intelligent methods

direct detection indirect detection DC side AC side

Conventional
Coupled-inductors [2] Parallel Transformer [6] half bridge [12]
Series capacitor [14] Fuzzy control [19-20]

Auto calibrating [3] Resonant circuit [7] Three level half Virtual capacitor [15-18] Neural network [21]
bridge [13]
DC-link Current [4] Output voltage [8-11]

Double integration [5]

Fig. 6.5 Classification of DCC rejection methods

224 6 DC Current Rejection for Transformerless …

6.2 Detection and Feedback Methods

Detection and feedback methods refer to precisely detect the DC component in grid-
in current by using various technical measures first, and then feeding this component
back into the control loop, and finally a bias voltage is generated in the output voltage
of TLIs to suppress DCC. The detection measures of DCC can be classified into two
kinds, i.e., direct detection and indirect detection methods.

6.2.1 Coupled-Inductor Detection Method

1. Operating principle

The operating principle sketch of coupled-inductor detection method is shown in

Fig. 6.6 [2]. A coupled-inductor and a hall sensor are adopted in the sketch. It
is worth noting that the turn numbers of primary and secondary windings in the
coupled-inductor are equal, and the secondary winding is short-circuited, as well
as the primary and secondary windings go through the hall sensor with opposite
directions.
Assuming that the primary side current ip is equal to the grid-in current ig = iac
+ I dc , here, iac and I dc are the AC component, and DC component of the grid-in
current, respectively. Due to the same turn numbers in the current transformer, is is
only equal to the AC component iac . Therefore, the output signal of the Hall sensor
exactly represents the DC component I dc of the grid-in current. Therefore, it is a
good way to use a Hall sensor with small capacity range to detect the DC component
with low cost and high accuracy.
2. Simulation results

In order to verify the effectiveness of the coupled current transformer detection, a

simulation model was built, and the key parameters are as follows: input DC voltage
U pv is 360 V, filter inductance L is 2mH, the grid voltage is 220 V/50 Hz, switching
frequency f s is 20 kHz, and rated power is 3 kW. By setting the grid-in current
reference as iref = 20sinωt + 1 (contains a DC bias current of 1 A), the grid-in current

Fig. 6.6 Coupled-inductor is=iac

detection method iac
Hall
sensor
ig=iac+Idc ip
0
DC
controller IDC
ig
current iref
SPWM controller
6.2 Detection and Feedback Methods 225

(a) (b)
ig:[10A/div] ip:[10A/div] is:[10A/div]

0 0

t[5ms/div] t[5ms/div]

Fig. 6.7 Current waveforms without DCC rejection compensation, a Grid-in current, b Primary
and secondary currents in coupled current transformer

waveform without DCC rejection compensation is shown in Fig. 6.7a, the current
waveforms in the primary and secondary windings of the coupled current transform
are shown in Fig. 6.7b. It can be seen that the grid-in current contains DCC because
of reference set, but the secondary winding current only contains AC component iac
included in grid-in current ig , it is in agreement with operating principle analysis.
After the DCC rejection strategy is enabled, the grid-in current waveform is shown
in Fig. 6.8a, it can be seen that the DCC is mostly disappeared even rough the current
reference contains 1A DCC setting. Again, the current waveforms in the primary and
secondary windings of the coupled current transform are shown in Fig. 6.8b, they
look same because the DC component I dc is restricted. The DCC waveform detected
by the Hall sensor is shown in Fig. 6.8c, it can be seen that only about 50 mA of
DCC is residual. Therefore, the detection & feedback method is able to make sure
the DC components complying with standard for a 3 kW PVPG system.
From the aforementioned analysis, it can be seen that using a small capacity range
Hall sensor in the coupled-inductor method can achieve higher detection accuracy
and acceptable rejection effect. However, the coupled-inductor needs to be carefully
designed to achieve tight coupling between primary and secondary windings. In order
to reduce sensor errors and avoid complex design caused by magnetic components,
sensor auto-calibrating method and DC-link current sampling method have been
proposed in [3, 4], respectively.

6.2.2 Sensor Auto-Calibration Method

1. Operating principle

The operating principle sketch of the sensor auto-calibration method is shown in

Fig. 6.9a [3], two current sensors are adopted in the sketch, which is used to measure
226 6 DC Current Rejection for Transformerless …

(a) (b)
ig:[10A/div] ip:[10A/div] is:[10A/div]

0 0

t[5ms/div] t[5ms/div]

(c)

iDC:[20mA/div]

0
t[5ms/div]

Fig. 6.8 Current waveforms with DCC rejection compensation, a Grid-in current, b Primary and
secondary currents in coupled current transformer, c DCC

(a) (b)
Sampling
ig icond
i'DC L1
i''g Sampling
PV ug ifwh
L2
icond-ifwh
PI controller
ig_ref Positive
Kp 1/Upv PWM No Reversing
i'g PWM? ifwh
Ki
1-z-1 Yes
Reconstruction i'DC Applying
unit result

Fig. 6.9 The detection and control structure of the sensor auto-calibration method, a Sensor auto-
calibration method, b Reconstruction process
6.2 Detection and Feedback Methods 227


the DC-link current i DC and the grid-in current ig , respectively. Assuming that the
full-bridge inverter operates under the unipolar SPWM modulation strategy, the DC-

link current i DC is equal to the absolute value of the grid-in current |ig | in the energy

transfer period, and the DC-link current i DC is equal to zero in the freewheeling

period, ideally. However, the measurement value of i DC in the freewheeling period
is not zero because of the non-linearity and inherent bias of the sensor. Therefore,
in order to achieve the auto-calibration of the sensor, the method can be taken that
 
subtracting the i DC in the freewheeling period from the i DC in the energy transfer
period. The detailed the reconstruction process in Fig. 6.9a is shown in Fig. 6.9b,
where icond is the sampling result of the DC-link current during the energy transfer
period, and ifwh is the sampling result of the DC-link current during the freewheeling
period. From the aforementioned analysis, ifwh is subtracted from icond to obtain the
corrected result. It is obvious that the corrected result can be directly applied as the
grid current reconstruction value if the output PWM command is positive, because
the grid voltage is in the positive half cycle at this time. By contrast, if the output
PWM instruction is negative, it can be known that it is in the negative half cycle of the
grid voltage at this time. Then, the corrected result is reversed to obtain the grid-in
current i’g after eliminating the sensor error. After that, the i’g is fed back to the grid-
in current controller as an accurate measurement result of the grid-in current, and
compared with the grid current reference ig_ref . The subtracted current error passes
through the grid current regulator and then outputs a PWM wave with dc bias. In the
end, this method achieves accurate tracking of the grid current to eliminate the DC
component of the grid.
2. Simulation results

In order to verify the effectiveness of the sensor auto-calibration method, a simulation

model was built in Matlab/Simulink, and the key parameters are as follows: input
DC voltage U pv is 360 V, filter inductance L is 2mH, the grid voltage is 220 V/50 Hz,
switching frequency f s is 20 kHz, and rated power is 3 kW. What is important is that
the sampling result is set to contain an offset of 0.1 A which causes that ifwh in the
freewheeling period is 0.1 A.
The actual DC-link current is shown in Fig. 6.10a, which is absolutely the high-
frequency current pulse. Figure 6.10b shows the icond waveform obtained after
sampling the DC-link current during the energy transfer period. What’s more,
Fig. 6.10c shows the sampling result of the DC-link current ifwh during the free-
wheeling period. It can be seen that there is a slight distortion at the zero-crossing
time of icond in Fig. 6.10b, and ifwh in Fig. 6.10c contains not only a DC component
of 0.1 A but also a pulsating component with lower amplitude. The main reason why
there are distortions in these waveforms is that there are some sampling points at the
time when the DC-link current has not completely returned to zero during the short
freewheeling period in the peak region of grid-in current. What’s similar is that there
are some sampling points at the time when the DC-link current is zero during the
short energy transfer period in the zero-cross region of grid-in current.
228 6 DC Current Rejection for Transformerless …

(a) (b)
i'DC:[5A/div] icond:[5A/div]

0 0
t[2ms/div] t[5ms/div]
(c)

ifwh:[50mA/div]

0
t[5ms/div]

Fig. 6.10 Waveforms of DC-link current, a Sampling waveform of DC-link current, b Sampling
waveform during the energy transfer period, c Sampling waveform in the freewheeling period

The i g shown in Fig. 6.11a is the grid-in current waveform reconstructed by the
process shown in Fig. 6.9b. It can be seen that the i g waveform is symmetrical and
contains all the information of the grid current. The grid-in current waveform directly
measured by the sensor is shown in Fig. 6.11b, which presents that the component
caused by the sensor bias error is included.
After the DCC rejection strategy is enabled, it is easy to find that there is almost
no DCC in the grid-in current shown in the waveform diagrams of Fig. 6.12a and b.
Concretely, it can be seen that the DC component of grid-in current is about 10 mA,
which follows the standards to connect the grid. Moreover, Fig. 6.12b and c show the
waveform of the grid-in current and the DCC by using the direct current detection
method. It can be seen that the DCC in the grid-in current is about 100 mA, which
is out of the grid-connection standard range as mentioned above.
From the aforementioned analysis, when applying the auto-calibration method,
the sensor has a good effect of eliminating sensor measurement errors. However, if
the PWM pulse width is narrow or wide, there is a certain error in the DC-link current
sampling. In order to improve the performance and reduce the cost, it is obvious that
6.2 Detection and Feedback Methods 229

(a) (b)
ig_recons:[5A/div] ig_recons:[5A/div]

0 0

t[5ms/div] t[5ms/div]

Fig. 6.11 Comparison between reconstructed grid-in current and original grid-in current, a Recon-
structed grid-in current, b Original grid-in current

(a) (b)

ig:[10A/div]
0

iDC:[20mA/div]
ug:[100V/div]
0
t[5ms/div] t[5ms/div]

(c) (d)

iDC:[20mA/div]

ig:[10A/div]
0

ug:[100V/div]
0
t[5ms/div] t[5ms/div]

Fig. 6.12 Simulation waveforms of sensor self-calibration method, a Grid-in current, b DCC of
grid-in current using sensor self-calibration method, c Grid current (direct measurement), d DCC
of grid-in current (direct measurement)
230 6 DC Current Rejection for Transformerless …

the current feedback is the reconstructed grid-in current using this method, so the
grid-side current sensor can be omitted. In this way, only the DC-link current sensor
is used for sampling, that is, the DC-link current sampling method [4].

6.2.3 DC-Link Current Sampling Method

1. Operating principle

The detection circuit of the DC-link current sampling method is shown in Fig. 6.13a

[4], where i DC is the DC-link sampling current. Assuming that iCond is the DC-link
conduction current, and the grid-in current is ig , the equation iCond = |ig | is satisfied.
Considering the DCC of the grid-in current, iCond divided into two components is
shown in (6.13), where I AC represents the output AC amplitude, and I DC represents
the injected DCC. The FFT of iCond is shown in (6.14) in which it can be seen that
the even harmonics component of iCond is related to the fundamental component of
the grid-in current, and the DCC of iCond is determined by odd harmonics of grid-in
current. Because of the lower high-harmonic content, ‘n’ can be replaced by ‘1’ in
(6.14) to get (6.15). What’s remarkable is that the third term of (6.14) is the line
frequency component, whose amplitude is related to I DC . Therefore, in this way,
the DCC of the grid-in current can be detected by calculating the power frequency
component of iCond .
The detection process of the DCC is shown in Fig. 6.13b, where the DC-link

current i DC is sampled and fed into the microprocessor through the current sensor and
the ADC. What’s more, the phase-locked loop is used to obtain the phase information

(a) (b)

L1 Low-
i'DC i'DC
CS ADC pass Averaging IDE
PV algorithm
L2 ug ug
filter
PLL sin
(c)

iref Current uin ig

controller
Gf(s)
icom i'g ug
Current iCond
reconstruction
Gsw(s)

IDE
Gdc(s) Gavg(s) Glf(s) Gsin(s)
0 Gex(s)
DC component suppression loop

Fig. 6.13 Detection and control structure of DC-link current sampling method, a DCC detection
circuit, b DCC detection structure, c Current control structure
6.2 Detection and Feedback Methods 231

(a) (b)

iDE:[5mA/div]
ig:[10A/div]
0

ug:[100V/div]
0
t[5ms/div] t[5ms/div]

(c)

iDC:[5mA/div]

0
t[5ms/div]

Fig. 6.14 Current and voltage waveforms with DC-link current sampling method, a DCC of DC-
link detection, b Grid-in current, c DCC of grid-in current (direct measurement)

of the grid. Based on the FFT result of (6.13), iCond is multiplied by sinωt to extract
its power frequency component, and further obtain I DC , which is shown in (6.14).
Substituting (6.13) into (6.14) to obtain (6.15), the DCC detected is the last term of
(6.15). Last, in order to eliminate the AC component to get the final DCC I DE , the
iEx is passed the through the low-pass filter and averaging algorithm, as shown in
(6.16).
On the whole, the control structure of this rejection strategy is shown in Fig. 6.13c,
where Gf (s) is the gain of the output filter, Gsw (s) is the switching transfer function,
Gsin (s) is the transfer function of the sine function, and Glf (s) is The transfer function
of the low-pass filter in Fig. 6.13b, Gavg (s) is the transfer function of the averaging
algorithm, and icom is the output compensation of the DC suppression loop. With the
output of DCC regulator Gdc (s) fed into the main control loop, the controller finally
outputs the switching signal with suppression bias to offset the DCC in the grid-in
current.
 
i Cond (t) = i g (t) = |I AC sin ωt + I DC | (6.11)
232 6 DC Current Rejection for Transformerless …

(a) (b)

ig:[10A/div]
iDC:[0.2A/div]

0
t[20ms/div] t[20ms/div]

(c) (d)

iDC:[0.5A/div]

iDC:[0.5A/div]

0 0

t[20ms/div] t[20ms/div]

Fig. 6.15 Integration results of the double integration method, a Grid-in current, b Integration
result when using grid period, c Single integration, d Double integration

Fig. 6.16 Resonance-circuit

detection L
ug
PV Cdc ig Ra

Lb
Cr Lr

Vm

Rm Lm
6.2 Detection and Feedback Methods 233

 ∞
4I AC 1  1
i Cond (t) = − cos 2nωt
π 2 n=1 4n 2 − 1
∞
 4I DC
+ sin[(2n − 1)ωt)], (n = 1, 2, 3...) (6.12)
n=1
(2n − 1)

2I AC 4I AC 4I DC
i Cond (t) = − cos 2nωt + sin ωt (6.13)
π 3π π

i E x (t) = i Cond (t) sin ωt (6.14)

2I AC
i E x (t) = i Cond (t) sin ωt = sin ωt
π
4I AC 2I DC 2I DC
− cos 2ωt sin ωt − cos 2ωt + (6.15)
3π π π
2I DC
IDE = (6.16)
π
2. Simulation results

In order to verify the effectiveness of the DC-link current sampling method, here
comes the simulation using Matlab/Simulink, and the key parameters are as follows:
input DC voltage U pv is 360 V, filter inductance L is 2mH, the grid voltage is
220 V/50 Hz, switching frequency f s is 20 kHz, and rated power is 3 kW. It is
worth noticing that the reference of grid-in current here is iref = 20sinωt + 1, which
contains a DC bias of 1A.
After the DCC rejection strategy is enabled, the steady-state simulation waveforms
of the DC-link current sampling method are shown in Fig. 6.14. It can be seen that the
sampling of DC-link current and the reconstruction results of grid-in current in this
method are consistent with the sensor self-calibration method. The DC-link current

i DC and the reconstructed grid-in current i g can be referred to Figs. 6.10a and 6.11a.
Figure 6.14a presents the waveforms iDE which is the DCC of grid-in current, and
Fig. 6.14b and c show the grid-in current and the DCC by directly measured. It can
be seen that the lower DCC of grid-in current is π/2 times of iDE in Fig. 6.14c, which
is consistent with the previous analysis.
It can be seen from the aforementioned analysis that this method only needs
to use one current sensor to detect the DC-link current, and the calculation of
DCC is completed in the microprocessor. However, the DCC extraction process
is complicated and is still based on one current sensor. In order to make better use
of the resources of the microprocessor, something else methods should be proposed.
Considering that the incoming current is a sine form term, the DCC of grid-in current
can be obtained by an integration method, that is, double integration method.
234 6 DC Current Rejection for Transformerless …

6.2.4 Double Integration Method

1. Operating principle

By detecting the grid-in current and integrating it, the double integration method
obtains the DCC of grid-in current injected into the grid [5]. This method can be
divided into two steps. Firstly, after decomposed using the FFT method, the AC
component of grid-in current is integrated. It is obvious that the integration result
is nearly zero when the integration period is equal to the grid period. Secondly, the
overall grid-in current is integrated during the grid period. Theoretically, the integra-
tion result is the DCC of grid-in current, but its actual value can be reduced because
of errors. Included the DCC in grid-in current, the result of the FFT can be shown in
(6.17). By integrating the first term of the (6.17) which is the DCC of grid-in current
and dividing by the integration period, the (6.18) can be obtained. Homoplastically,
by integrating the second term of the (6.17) which is the AC component, the (6.19)
can be obtained. As seen, if f g = 1/T, then (6.21) is equal to zero, that is, the DCC

(a) (b)

uRm_DC:[2mV/div]

0 0

uRm:[0.5V/div]
t[5ms/div] t[5ms/div]

(c) (d)

ig:[10A/div] iDC:[20mA/div]
0

ug:[100V/div]
0
t[5ms/div] t[5ms/div]

Fig. 6.17 Detection results of resonance-circuit method, a Voltage across detection resistor Rm ,
b DCC of voltage across detection resistor Rm , c Grid-in current, d DCC of grid-in current
6.2 Detection and Feedback Methods 235

Fig. 6.18 Detection and

control structure of S1 S3
bridge-leg-voltage method
L1 r
Upv
1
C ug
PV Cdc 2 L2
S2 S4

N
0
Differential
DC
MPPT detection LPF controller
circuit
ΔUDC
ug1 ug2 ug3 ug4 ig
Current ug
SPWM controller
cos PLL

of grid-in current can be obtained by integrating the grid current, directly. However,
when there is disturbance outside the system such that f g = 1/T, the (6.22) can be
obtained by integrating the (6.19). It can be seen that if the integration result of grid-
in current is directly sampled at this time, a larger detection error will be caused. In
order to reduce the error, double integration can be applied on (6.19). The double
integration results are shown in (6.23). Comparing (6.22) and (6.23), it is found that
the amplitude of AC component in (6.23) is lower and the error is smaller. That is
means, the more times integrations are applied, the smaller errors can be got. But too
many times integrations will slow down the system response, which is undesired.
Taking the right of (6.23) as the detection result of the DCC of grid-in current, the
DCC can be eliminated after discretizing and feeding it into the DC rejection loop.

i g (t) = Idc + i ac = Idc + i n sin(2π n f g t + ϕn ) (6.17)
n=1,2,3,...

t0 +T
1
i 0 (t) = Idc dt = Idc (6.18)
T t0

t0 +T 
i 1 (t) = In sin(2π n f i t + ϕn )dt
t0 n=1,2,3,...
 −In
= cos(2π n f g t + ϕn )|tt00 +T
n=1,2,3,...
2π n f g
 In
= · sin(2π n f g t0 + ϕn + π n f g T ) · sin(π n f g T ) (6.19)
n=1,2,3,...
π n fg
236 6 DC Current Rejection for Transformerless …

(a) (b)

u12_DC:[50mV/div]

u12_DC:[50mV/div]
0 0
t[5ms/div] t[5ms/div]
(c)

u12_DC:[50mV/div]
0
t[5ms/div]
(d) (e)

iDC:[10mA/div]
ig:[10A/div]
0

ug:[100V/div]
0
t[5ms/div] t[5ms/div]

Fig. 6.19 Current and voltage waveforms with Bridge-leg-voltage method enabled, a DCC of
bridge leg output without bias injected, b DCC of bridge leg output with 1 A bias injected, c DCC
of bridge leg output after compensation, d Grid-in current, e DCC of grid-in current
6.2 Detection and Feedback Methods 237

t0 +T
1
i 2 (t) = i g (t)dt
T t0

1 t0 +T t0 +T 
= Idc + In sin(2π n f g t + ϕn ) dt
T t0 t0 n=1,2,3,...
    
fi π n fg π n fg
= Idc + sin · In sin 2π n f g t0 + ϕn + (6.20)
n=1,2,3,...
π n fg fi fi
t0 +T t0 +T
1
i 3 (t) = i 2 (t)dt
T2 t0 t0
  2  
fi π n fg π n fg
= Idc + sin( ) · In sin 2π n f g t0 + ϕn +
n=1,2,3,...
π n fg fi fi
(6.21)

It can be seen from the aforementioned analysis that the double integration method
has higher detection accuracy. What is impressive is that only one current should
be sampled, but it is higher digital computing requirements that put pressure on
microprocessor resources.
2. Simulation results

Assuming that the fundamental component of grid-in current is i1 = 20sin(2πf g t),

where f g is the grid frequency equaling to 50 Hz. If the grid current contains low-
order harmonics and DCC, it can be expressed as ig = 20sin(2πf g t) + 4sin(3 ×
2πf g t) + 2sin(5 × 2πf g t) + 1. When f g is equal to 50 Hz, the waveform of ig is
shown in Fig. 6.15a (lower harmonic and DC components are added after two grid
cycles). When the grid period is equal to the integration period, single integration
of ig can obtain the result shown in Fig. 6.15b. In the case of disturbance, if the
grid period is not equal to the integration period, single and double integrations are
applied on ig , respectively. And the results are shown in Fig. 6.15c and d. It can
be seen from Fig. 6.15 that when the integration period is equal to the grid period,
the DCC of grid-in current can be effectively obtained by using a single integration.
However, when the integration period is different from the grid period, the result
of single integration will fluctuate greatly. At this time, double integration can be
applied to get more accurate detection results of DCC.
The method of obtaining the DCC of grid-in current by direct sampling is
described above. In order to minimize sampling errors, especially sensor errors,
an indirect sampling method is proposed. Namely, the indirect sampling mainly
reflects the DCC of grid-in current by sampling the DCC of voltage, including the
resonant-circuit method and the bridge-leg-voltage method [7–11].
238 6 DC Current Rejection for Transformerless …

6.2.5 Resonant-Circuit Method

1. Operating principle

The operating principle sketch of the resonant-circuit detection is shown in Fig. 6.16,
in which the resistor Ra is the sampling resistor of grid-in current. In order to
reduce the AC component entering the detection branch, a multi-level AC compo-
nent suppression branch is been applied in the circuit, where the inductor L b acts
as a first stage to block the AC component of the grid-in current from flowing into
the detection branch. It is worth noting that the inductor L r and the capacitor C r
are connected in series to form a resonance circuit as a second stage to bypass the
AC component that enters the detection branch. Therefore, this method is called a
resonance-circuit detection method. What’s more, the inductor L m is a third-stage to
block AC component from flowing into the detection resistor Rm . Finally, the voltage
across Rm can reflect the magnitude of the DCC of grid-in current.
It can be seen from the above-mentioned analysis that this method uses a multi-
stage circuit for detection. Moreover, there are discrete components used in the circuit
and no coupling inductor or transformer, which makes the circuit structure simple.
However, in order to minimize the AC component flowing into the detection branch,
the parameter design of these components is complicated, because the test results of
DCC are highly dependent on the parameters.
From Fig. 6.16, the transfer function of the grid-in current ig (s) to the detection
voltage vm (s) is shown as

vm (s) Rm Ra
G m (s) = = 
i g (s) s L b Rm +s(L m +L r )+ sC1r
s L r + sC1r
+ Rm + s L m
Rm Ra sCr (s 2 L r Cr + 1)
=
s 2 L b Cr [Rm sCr + s 2 Cr (L m + L r ) + 1] + sCr (Rm + s L m )(s 2 L r Cr + 1)
(6.22)

2. Simulation results

In order to verify the effectiveness of the resonance-circuit detection, a simulation

model was built in Matlab/Simulink, and the key parameters are as follows: input DC
voltage U pv is 360 V, filter inductance L is 2 mH, the grid voltage is 220 V/50 Hz,
switching frequency f s is 20 kHz, rated power is 3 kW, inductance L b is 0.8 mH, and
resistance Rm is 3 s. It is important that the reference of the grid-in current iref is
equal to 20sinωt + 0.5, which contains a DC bias of 0.5 A. As shown in Fig. 6.17,
the effectiveness of the resonance-circuit detection method can be verified.
Figure 6.17a shows the voltage across the sense resistor Rm , which contains AC
component, while Fig. 6.17b shows the DCC in the voltage of sense resistor Rm .
What’s more, Fig. 6.17c shows the grid current, and the DCC of grid-in current is
shown in Fig. 6.17d. From these waveforms in Fig. 6.17, it can be seen that the
6.2 Detection and Feedback Methods 239

voltage across the resistor Rm contains only the fundamental frequency component
and no high-frequency components. Therefore, this method can indirectly reflect the
DCC through the voltage across the resistor Rm . From the grid-in current and its
DCC waveform diagram, it is found that the DCC of grid-in current is about 60 mA
when the grid-in current reference contains 0.5A DC suppression, which follows the
standards to connect the grid.

6.2.6 Bridge-Leg-Voltage Detection Method

1. Operating principle

Bridge-leg-voltage method [9–11] is another indirect detection method that reflects

the DCC of grid-in current by detecting the DC voltage in the bridge leg voltage of
the inverter. Reference [9] uses a differential amplifier and a second-order low-pass
filter to filter out AC components, and the complete control loop is shown in Fig. 6.18
[9–10]. In Fig. 6.18, a differential amplifier circuit is used to detect the TLI output
differential mode voltage. By adopting a low-pass filter (LPF) to further eliminate
higher harmonic components, a DC voltage component related to the DCC of grid-
in current can be obtained. This DCC is fed into the DCC regulator to generate a
compensation bias, and this compensation bias is fed into the grid-in current regulator
to reject the DCC of grid-in current.
This method has a strong effect on the DCC of grid-in current caused by differences
from power devices. However, it has a weak effect on the errors of signal conditioning
circuits and the DC voltage component of the grid.
2. Simulation results

In order to verify the effectiveness of the bridge-leg-voltage method, a simulation

model was built in Matlab/Simulink, and the key parameters are as follows: input
DC voltage U pv is 360 V, filter inductance L is 2mH, the grid voltage is 220 V/50 Hz,
switching frequency f s is 20 kHz, rated power is 3 kW. In addition, the grid-in current
reference iref is equal to 20sinωt + 1, that is, it contains a DC bias of 1 A.
As shown in Fig. 6.19a, the output DC voltage of the bridge leg is nearly zero
when there is no DC bias in grid-in current reference. And Fig. 6.19b shows the
DC voltage of the bridge leg when a 1 A DC bias is injected and not fed into DC
regulator. What is important is that Fig. 6.19c shows the DC voltage of output from
the bridge leg after the 1 A DC bias is injected and the DC regulator is enabled.
Grid-in current waveforms and its DCC in steady-state of the bridge leg voltage
method are shown in Fig. 6.19d and e, respectively. It is worth noting that when the
grid-in current reference is not injected into the DC bias, the DC voltage of bridge
leg output is almost equal to zero from these figures. After the DC bias is injected,
the DC voltage of bridge leg output increases significantly. Therefore, this method
240 6 DC Current Rejection for Transformerless …

can indirectly detect the DCC of grid-in current. Noticing that the DCC of grid-in
current is about 40 mA shown in Fig. 6.19e, it is apparent that the DCC of grid-in
current is effectively rejected.

6.3 Capacitor Blocking Methods

Generally speaking, the detection-feedback method feeds the detected DCC of grid-
in current into the controller for rejection, so the result of the detection loop and
the control parameters of the system will have a greater impact on the suppression
effect. Adding a “blocking capacitor” to the loop of the grid-in current is a method
for rejecting DCC that does not rely on detection accuracy and has a good rejection
effect. According to the position of blocking capacitor placed, it can be divided into
DC side and AC side capacitor blocking methods.

6.3.1 DC-Side Capacitor Blocking Method

It is obvious that a half-bridge topology is a typical structure with a blocking capacitor

on the DC side, as shown in Fig. 6.20a which is a traditional two-level half-bridge
TLI circuit. In this circuit, the grid-in current flows through the capacitor during
the energy transfer period and the freewheeling period, when the blocking capacitor
can effectively eliminate the DCC of grid-in current. But its output is a two-level
voltage which means higher harmonic components contained in output. Introduced
in Sect. 4.2.1 of this book, the NPC half-bridge grid-connected inverter [12] also
has a half-bridge structure. The output of this structure is a three-level voltage with

(a) (b)
P
S1 D1
Cd c 1 Cd c 3

Cdc1 Up D5
S1 v S2 D2
Upv D1 2
3 1
L1 PV L ug
S3 D3
PV ug D6

S2 Cd c 2 S4 D4 Cd c 4

N Cdc1 D2 N

Fig. 6.20 DC-side blocking capacitor method, a Two-level half-bridge TLI topology, b Three-level
half-bridge TLI topology
6.3 Capacitor Blocking Methods 241

(a) (b)

1
Cs
Lf1
C
Io* D 1 Io
PV ug G(s) Kpwm
Cdc Lf2 Upv sL+R
Ug

Fig. 6.21 Sketch of actual series capacitor method, a Circuit sketch with actual capacitors,
b Transfer function model

better differential mode characteristics. However, during the freewheeling period, the
grid-in current cannot flow through the capacitor, which weakens the blocking effect.
The structure of the double-capacitor NPC grid-connected inverter [13] introduced
in Sect. 4.2.3 of this book is shown in Fig. 6.20b. This structure allows the grid
current to flow through the blocking capacitor during the energy transfer period and
the freewheeling period. In this way, the DC blocking effect in the energy transfer
period and the freewheeling period can be guaranteed and the three-level differential
mode voltage output can be maintained.
As shown in Table 4.8, Sect. 4.2.3 of this book analyzes the DCC of grid-in current
for HERIC, NPC, and the circuit shown in Fig. 6.20b.
The DC-side blocking capacitor method generally requires a larger volume to
place electrolytic capacitors and higher requirements for the voltage equalization
circuit. In other words, the imbalance of the capacitor voltage will affect the DC
blocking effect. For this reason, researchers have proposed the AC-side blocking
capacitor method [14–18]. The AC side blocking capacitor method places the capac-
itor on the AC output side in which capacitor can be an actual physical capacitor [14]
or a “virtual capacitor” [15–18] method.

6.3.2 AC-Side Capacitor Blocking Method

1. Actual series capacitor method

The circuit sketch of the AC-side blocking capacitor method using actual physical
capacitors [14] is shown in Fig. 6.21a, where the equivalent transfer function model
is shown in Fig. 6.21b, that is, a blocking capacitor is placed on the grid side. The
meanings of the symbols are as follows: U pv is the bridge leg voltage, R is the
equivalent series resistor of the inductor, I o * is the reference of grid-in current, C is
the actual physical capacitor, G(s) is the grid-in current controller, and D is the duty
ratio, Kpwm is the pulse width modulation gain. With clear principles and simple
implementation, the method still has many disadvantages. Firstly, the capacitance
value is difficult to determine, which means that larger capacitors will slow down
242 6 DC Current Rejection for Transformerless …

(a)

Drop Point ug

ig
Soft-start Dc component
Stage injection Point

(b)

Drop Point ug

iref ig

(c)

Dc component
ug
injection Point
iref

ig

Fig. 6.22 Key waveforms of actual series capacitor method in experiment test, a Grid-in
current respance waveforms with soft-start, sudden amplitude change and dc component injec-
tion, b Dynamic details of sudden current amplitude change, c Respance details of dc component
suppression
6.3 Capacitor Blocking Methods 243

(a) (b)
C 1
Lf1 KpwmCs
Virtual
capacitor Io* D 1 Io
PV ug G(s) Kpwm sL+R
Cdc Lf2 Upv
ug

Fig. 6.23 Sketch of virtual capacitor method, a Circuit sketch with virtual capacitor, b Transfer
function model

the dynamic performance of the system, and smaller capacitors will easily cause
oscillation. Secondly, the series resistor of capacitor will also reduce the efficiency
of the TLI.
2. Experimental results of the actual series capacitor method

In order to verify the effectiveness of the actual physical capacitor method, a hardware
platform was built and the key parameters are as follows: input DC voltage U pv is
360 V, grid voltage is 220 V/50 Hz, inductance L is 2.2 mH, and capacitance C is
600 μF. The effectiveness of this method can be evaluated, as shown in Fig. 6.22. In
addition, the grid-in current reference iref is changing according to certain rules [14].
Figure 6.22a shows the different working stages for a grid-connected inverter, and
Fig. 6.22b shows the dynamic process waveform of the system with actual capacitor.
In addition, the dc component suppression process is shown in Fig. 6.22c. It can be
seen from Fig. 6.22a that the grid-connected inverter experiences a soft-start process
firstly, and then it keeps running with 10 A current amplitude, next the reference
current amplitude suddenly changes to 5 A at the positive peak point of current
reference, and finally a 1 A dc component is superimposed on the reference current
at the zero crossing point, i.e. the reference current is 5sinωt + 1. The gray dotted
line represents the reference current iref , and the change points are aligned in the
center of the oscilloscope window, as shown in Fig. 6.22b and c. It is worth noting
that the dynamic performance of the system is good under this method, and the dc
component can be quickly suppressed within one line cycle.
In addition, after the reference current is superimposed with a positive DC bias,
the grid-in current will have a larger ripple in the negative half cycle than the posi-
tive half cycle, which will increase the harmonic components of the grid-in current.
In summary, actual capacitor method can achieve the function of DC component
suppression, but considering factors such as volume and cost, virtual capacitor
method should be used instead in actual applications.
244 6 DC Current Rejection for Transformerless …

3. Virtual capacitor method

The circuit sketch of the AC-side blocking capacitor method using the virtual capac-
itor method [15–18] is shown in Fig. 6.23a and b shows the equivalent transfer func-
tion model of this circuit, where the grid-in current is fed forward to the duty cycle.
In Fig. 6.23b, 1/(Kpwm Cs) is the equivalent virtual capacitor which can be realized
using a software algorithm. In this way, this method not only realizes the function of
suppressing the DCC of grid-in current, but also avoids a series of disadvantages of
the actual capacitor.
4. Experimental results of virtual capacitor

The experimental of blocking capacitor method using virtual capacitors and all
the key parameters are consistent with the capacitor blocking method using actual
physical capacitor.
By observing the key waveforms of virtual capacitor method in experimenting
shown in Fig. 6.24, it is found that when using virtual capacitors, the grid-connected
inverter has no significant difference in dynamic performance and dc component
suppression effect from the actual physical capacitors, and the current positive and
negative half-cycle ripples are symmetrical, and there is no overmodulation problem.
Therefore, experiment waveforms have confirmed that virtual capacitors can replace
actual physical capacitors in practice with low cost.
Suitable control parameters should be decided in the detection & feedback
methods, and the capacitor blocking method also needs to adjust its capacitance. The
control parameters cannot be adjusted in time when the system reference changes,
which may make the system unstable or increase tracking error, because of the
fixed parameters used in controller in traditional control methods. It is obvious
that the controller parameters have a great influence on both the tracking effect
on grid-in current and the suppressing effect on the DCC. However, the precise
design of controller parameters is very complicated. With the rapid development of
computer hardware resources, suppressing methods using intelligent control algo-
rithms have been gradually adopted, such as iterative PI control algorithms [19],
fuzzy control algorithms [20], and neural network ABP (adaptive back propagation)
control algorithms [21] and so on.

6.4 Intelligent Algorithms

6.4.1 Fuzzy Iterative PI Method

A control block diagram of the fuzzy iterative PI method proposed in [19] is shown
in Fig. 6.25 for a three-phase grid-connected inverter. Using a PI controller as the
main controller of the circuit, the improved sliding average filtering algorithm is used
to obtain the high-precision DCC of grid-in current in real-time. What’s more, an
6.4 Intelligent Algorithms 245

(a)

Drop Point ug

iref ig

(b)

Dc component
ug
injection Point
iref

ig

Fig. 6.24 Key waveforms of virtual capacitor method in experiment test, a Dynamic details of
sudden current amplitude change, b Respance details of dc component suppression

iterative PI controller is applied to the DCC suppression loop whose parameters are
generated in real-time by fuzzy computing. When combined with the parameter self-
adjusting strategy of fuzzy control, it is worth noticing that iterative PI control can
eliminate steady-state errors and improve the dynamic performance of the system.
With iterative PI control enable, the compensation bias is fed into the main controller
loop to eliminate the DCC of grid-in current.

6.4.2 BP Neural Network Method

As shown in Fig. 6.26, a BP neural network algorithm for three-phase grid-connected

inverters is proposed in [21], where the main controller of current loop is the QPR
controller. In order to accelerate the calculating speed in the microprocessor, an
adaptive learning speed regulator is used to select a suitable speed learning factor for
246 6 DC Current Rejection for Transformerless …

Parameter
pre-setting ug_a,b,c
Fuzzy Voltage control
reasoning
Current control
iga igb igc 0 de/dt
Filtering and Iterative PI control
coordinate SVPWM
transformation Iterative PI control
0 de/dt
Fuzzy
reasoning

Parameter
pre-setting

Fig. 6.25 Control strategy of fuzzy iterative PI method

igc igb iga

Pref igref_a
P/Q igref_b QPR
Qref igref_c controller PWM
controller

iga iga' idca

igb zero- drift igb' SWDIM idcb PID
igc suppression igc' sensing idcc controller
kd ki kp
iga'
igb' BP
Adaptive learning neural
igc' speed regulator
network
Fig. 6.26 Control strategy of BP neural network method

the subsequent operations of BP neural network. After compensated by the zero drift
suppression units, the sampled grid-in current is fed to the sliding window double
integration method (SWDIM) to extract the DCC of grid-in current, which is fed
into the PI controller of the DCC suppression loop next. Analogously, the control
parameters of PI controller are generated in real-time by the adaptive BP algorithm,
which can achieve accurate suppression of the DCC of grid-in current.
6.5 Summary 247

6.5 Summary

To summarize, the method of eliminating the DCC of grid-in current in a TLI system
are discussed in this chapter, which mainly includes detection-feedback method,
blocking capacitor method, and intelligent control algorithm. Detection results of
DCC fed back to the main controller to generate a modulation strategy with DC bias,
the detection-feedback method can eliminate the DCC of grid-in current. Meanwhile,
the blocking capacitor method does not need to detect the DCC of grid-in current,
because the DC blocking property of capacitor just coincides with the purpose of
eliminating the DCC. What’s more, unlike detection-feedback method which affected
by control parameters of the system easily, the intelligent control algorithm can
achieve the purpose of eliminating DCC of grid-in current by precise control with
real-time parameters.

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