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2nd Sessional VLSI Design

This document outlines the sections and questions for a VLSI design exam. Section A contains 8 brief questions about topics like propagation delay, linear delay model, power dissipation factors, parasitic delay, rise and fall time, lambda design rules, regularity, modularity, locality, and voltage bootstrapping. Section B contains 4 short answer questions about BIST techniques, the Y-chart design flow, wire interconnect geometry, and NMOS transistor fabrication. Section C contains 3 longer answer questions about implementing an XOR gate with different logic styles, implementing a Boolean function with CMOS logic and stick diagram, and proving the pull-up/pull-down ratio for an NMOS inverter. The exam tests knowledge

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Mr. Manoj Kr. Sharma Ece
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27 views1 page

2nd Sessional VLSI Design

This document outlines the sections and questions for a VLSI design exam. Section A contains 8 brief questions about topics like propagation delay, linear delay model, power dissipation factors, parasitic delay, rise and fall time, lambda design rules, regularity, modularity, locality, and voltage bootstrapping. Section B contains 4 short answer questions about BIST techniques, the Y-chart design flow, wire interconnect geometry, and NMOS transistor fabrication. Section C contains 3 longer answer questions about implementing an XOR gate with different logic styles, implementing a Boolean function with CMOS logic and stick diagram, and proving the pull-up/pull-down ratio for an NMOS inverter. The exam tests knowledge

Uploaded by

Mr. Manoj Kr. Sharma Ece
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Printed pages: 01 Sub Code: KEC 072

Paper Id: Roll No:


B TECH
(SEM VII) THEORY EXAMINATION 2023-24
VLSI DESIGN

Time:1.5Hrs Total Marks: 30


Notes: Attempt all Sections. Assume any missing data.

SECTION A
Q1. Attempt any seven parts in brief. (2*5=10)

a) Define Propagation delay and contamination time.


b) What is linear delay model?
c) What are the factors that reduce the power dissipation?
d) Define the parasitic delay.
e) Define the rise time and fall time.
f) Explain the lamda design rules in brief.
g) Define Regularity, Modularity and Locality.
h) What is voltage bootstrapping?

SECTION B

Q2. Attempt any three questions. All questions carry equal marks (5*2=10)
a) Explain the implementation of Built–in Self-Test (BIST) design techniques for VLSI
circuit testing.
b) Why Y-chart is essential in the implementation of the VLSI design flow? Explain the
three domains of VLSI design flow.
c) Write a short note on wire or interconnect geometry.
d) Explain the step-by-step fabrication of the NMOS transistor with suitable figures.

SECTION C
Q3. Attempt any two questions. All questions carry equal marks (10*1=10)

a) Explain 2 input XOR gates using CMOS logic circuits, TG gate, and pass transistor
logic.
b) Implement the Boolean function f (A, B, C) = A’BC+AB’C+ABC’ using CMOS logic
and also draw the stick diagram.
c) Prove that the pull-up and pull-down ratio for an NMOS inverter driven by another
NMOS is 4:1.

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