Fabrication of transistors and evolution of CMOS

Integrated Circuit die to package connections

10 cm diameter Si wafer with 100 dies

Apple M1 Pro ~250 mm2, 16 Billion Transistors

741 OP-amp, 20 Transistors

State-of-Art manufacturing
uses 300 mm wafers

Associate Professor Per-Erik Hellström, Division of Electronics and Embedded Systems

 Micro - nanoelectronic
manufacturing
Manufacturing in
Circuit / System Design
cleanroom factories Wafer level
Foundry

Electronic Device Automation

Fabless company, ASIC provider
Tool vendors

Packaged dies

Packaging
houses
Transistors
Chip / die

A company that do all of the above is called an Integrated Device Manufacturer

 Complementary Metal Oxide Semiconductor
(CMOS) technology NAND gate Optical
GDSII microscope
INVERTER gate

G S
PMOS
D
IN OUT
D
NMOS
G S
GND

• Two types of transistors: p-channel and n-channel Field Effect Transistors

• All logic gates are built with pFET network and nFET network between Vdd and GND.
 Fabrication in cleanrooms (fabs)

KTH Electrum Laboratory

 KTH CMOS process

Transistors and interconnections

Intel CMOS process

Semiconducting materials (e.g. Si, Ge…)

Insulating materials (e.g. SiO2, SiN, HfO2…..)
Many levels of metal interconnections,
Conductive materials (Al, Cu, TiN, TiW, NiSi…..) 12 levels in picture above
 The planar technology
1. Deposit Material
Chemical Vapour Deposition, Physical Vapour Deposition, Electropalting, ”Ion implantation”.
2. Perform Lithography
Optical (=365, 248, 193, and EUV at 13 nm)
3. Remove Material (often on selected places of the wafer)
Dry etching (a plasma in vacuum), wet etching (a liquid), chemical mechanical polishing…

Repeat 1-3 many times to build complex structures/devices

 Ion Implantation + high temperature annealing (~1000 °C)
to create p-type and n-typ Si.
Activation and diffusion of dopants occurs during annealing.

Energy range 200 eV up to several MeV

Ion current I Up to 30 mA
Dose range 1011 up to 2x1016 cm-2
Gaseous ion sources BF3 (for BF2 and B), Ar
Solid ion sources As, Sb, Ph, Ge, Si
 Deposit Material, Ex. Low Pressure CVD for Si3N4, SiO2 and poly-Si

poly- Si
SiH4 at T~550-650°C
Thermal LPCVD processes doping: B2H6, PH3
- Low Pressure ~100 – 300 mTorr to avoid SiO2
reactions in gas phase. SiH4+O2 at T~400-450°C
- Temperature to ensure reaction rate limits the TEOS at T~700°C
growth rate. (Need good temperature uniformity and control) Si3N4
SiH2Cl2 + NH3 at T~800°C

Si3N4 LPCVD

poly-Si LPCVD
 Plasma Enhanced CVD (PECVD)
• Non-thermal energy to enhance processes at lower temperatures.
- Low temperature might be needed due to materails already present on the
wafer (e.g. Al, Cu metallization, III-V epitaxial layers…..

• Plasma consists of electrons, ionized molecules, neutral molecules, neutral and ionized
fragments of broken-up molecules, excited molecules and free radicals.
• Free radicals are electrically neutral species that have incomplete bonding and are
extremely reactive. (e.g. SiO, SiH3, F)
• The net result from the fragmentation, the free radicals, and the ion bombardment is that
the surface processes and deposition occur at much lower temperatures than in non-
plasma systems.
Example deposition of SiO2 insulator

PECVD SiO2 (e.g. SiH4 + N2O)

T ≤ 400°C
Conformality, Pin holes,
HF Etch Rate ~ 5-10x thermally grown SiO2

Thermal LPCVD SiO2

T > 400°C
Improved conformality, No pin holes,
HF Etch Rate ~ 2-3x thermally grown SiO2

High Density Plasma CVD SiO2

T< 400°C
Etch + Dep, excellent filling, requires subsequent
Chemical Mechanical Planarization
HF Etch Rate ~ close to thermally grown SiO2
Deposit material: Example Aluminium

• Deposition of Aluminium is performed in low vacuum (10-11

atm) chambers at temperature of 175 °C at KTH.
 Lithography

Resist coating Light Exposure Resist develop

The stepper is capable of exposing 100 dies on a wafer at a speed of hundreds of wafers per hour
 Etching

Using plasma of gases we can create directional etching to define

fine features on the wafer
 • Iterate Deposition, Lithography and Etching many times with different
mask (resist patterns) and materials to build complex circuits

• The number of masks (that is iterations) is typically from 10 to 80

depending on the complexity of the circuit.
Micro-Electro-Mechanical-Systems
Optical devices
Electronics III-V materials
GaP Light Emitting Diodes (LED)
GaAsP
AlGaInP
InGaN

Solid State Lasers - ST Microelectronics three-axis

gyroscope that together with
accelerometer and electronic
devices gives full motion sensing
in smart phones.
Design Rules: Lithography Resolution & Alignment
δA,B : uncertainty in feature size for mask level A and B
Resolution: Δ : alignment (or overlay) error between A and B

R  k1
NA Placement error of level A to B = 2   A2   B2
Overlap > 3σ of minimum separation values usually given
KTH: =365 nm,
NA=0.4, k1=0.65
Resolution ~ 0.5 µm
Alignment < 50 nm

Total 3σ must consider overlay error, magnification error, lens

distortion, stepper-to-stepper error, and reticle error

Misaligned contact holes

 Yield:
# of working IC / # of IC that started fabrication

Functional Yield Parametric Yield

Identical IC has different performance (power consumption, possible
% IC that exhibits the intended clock speed, leakage current….)
function

Low functional yield can occur because (among

many, many things):

- Alignment errors
- Underexposed resists
- metal residuals after etching (shorts), etched
undercuts of metal lines (opens)
- not etched all contact holes complete (opens) 4 corners in timing analysis
- Metal shorts due to non-uniform deposition Fast PFET, Fast NFET
- Shorts due to pinholes in PECVDoxide Low VT: fast and high Ioff Slow PFET, Fast NFET
layers……. High VT: slow and low Ioff Fast PFET, Slow NFET
Slow PFET, Slow NFET
CMOS technology at KTH using =365 nm lithography

M1 pitch = 4000 nm
Contact Gate Pitch = 8000 nm

KTH 10 track standard cell library

VDD track

G S
D
IN OUT M1 pitch
Contact Gate Pitch
D
G S
GND VSS track
~ 6000 Tr/mm2
 Circle with diameter equal to an
average human hair

Chip NAND Ring Osc .

This circuit was made, in a M.Sc. thesis
project in 2022, to enable Si CMOS
PFET NFETs operating at high temperature.

PFET NFET NFET

TiW
Poly-Si
c-Si
BOX
Si

12 µm

Size of the circuit, if it would be scaled to state-of-the-art technology (3 nm node)

PEFE
 130 nm technology node (year 2000)
Cu metallization and low k dielectrics
Chemical Mechanical Planarization (CMP)

Cu

Design Rules includes density restrictions on all layers that will have CMP, i.e. all metal layers.
If density is too low then dummy metal lines is inserted to assure a high yield in the CMP process.
 Impact of the metal interconnections
𝑘𝜖0 𝐴
The metal interconnects give has capacitances (between wires as well as to substrate, C = ) and
𝑡𝑖𝑛𝑠
resistance R along the wires. These wires increase delay (=RC) and increase power consumtion 𝑃 = 𝑓𝐶𝑉 2 .

The exact power consumption and delay in a circuit depends on how the gates are laid out on the wafer and
therefore not known accurately when design is at the schematic or RTL level. Technology Ratio: Cwire/Cgate
350 nm ~30/70
The impact of interconnects increases with reduced transistor size.
90 nm ~50/50
16 nm ~80/20

1. Evaluate correct timing and power of circuit

(auto correct netlist if needed)
2. Place and route logic primitives
3. Extract parasitic R,C
4. Evaluate correct timing and power of circuit
(auto correct netlist if needed)
 Evolution of CMOS process technology
Historically (before 1995), all dimensions and voltages in the
transistor was scaled in order to keep electric field unchanged in a
transistor.

From around 1995 the gate length was scaled more to get higher
current to allow shorter delays, faster circuits.

Gate
length

𝑊 𝑉𝐷𝑆
𝐼𝐷 = µ𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆 − 𝑉𝐷𝑆 Manufacturing in 2003 Design rules on source/drain
𝐿 2
M1 pitch = 220 nm areas and pitch to assure
𝐶𝑉
delay of inverter ~ power of inverter ~𝑓𝐶𝑉 2 Contacted Gate Pitch = 260 nm strain in channel
𝐼𝑜𝑛
 High-k dielectric in CMOS
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained
Silicon,9 Cu Interconnect Layers, 193nm Dry Patterning.
NFET PFET

Manufacturing in 2006
M1 pitch = 160 nm
Contacted Gate Pitch = 180 nm

Design rules on gate density due to CMP on the gate

 FinFET technology at 22 nm node

Manufacturing in 2012 Design Rules inludes restrictions on how the fins and gates
M1 pitch = 80 nm are patterned (only straight lines that are cut at appropriate
Contacted Gate Pitch = 90 nm
places is allowed)

24
 Intel 10 nm technology node

Lithography: Immersion =193 nm with double patterning techniques

Standard cell reduction by self aligned contacts to source/drain and

contact to gate on active

Manufacturing in 2018
M1 pitch = 36 nm
Contacted Gate Pitch = 54 nm
State-of-the-Art Lithogaphy: Extreme Ultra Violet lithography (EUV)
• Light source with λ = 13.5 nm
• Purely reflecting system including mask
• Each mirror consists of multilayers of Mo and Si and can both be used for
reduction (usually 4x) and as mask
• Cost is about 150 MEuro/tool
• >100 tools has been shipped to manufacturer as of 2021.
27
TSMC 5 and 3 nm nodes, Intel 4 (EUV Lithography)
TSMC 5 nm node manufacturing in 2020 TSMC 3 nm node manufacturing in 2023
M1 pitch = 28 nm M1 pitch = 22 nm
Contacted Gate Pitch = 48 nm Contacted Gate Pitch = 45 nm
6 tracks 6 tracks

Apple M1 Chip
5 nm Node TSMC, Transistors 16
Billion
Area 119 mm2, ~ 134 MTr/mm2
 Technologies for next generation nodes
nanosheet FETs Backside power rails Stacking FETs to
increase #FETs/mm2

Intel 1.8 nm
Samsung 3 nm node 2023
node in Beyond 2025 ?
TSMC 2 nm node in 2024?
2025?
Intel 2 nm node in 2024?

- A key strategy is to find technologies that enable reduction of standard cells size.