i

Simon Boonants

TESTING AND ANALYSIS OF

UNIVERSAL HIGH VOLTAGE DIVIDER

Master of Science Thesis

Faculty of Information Technology
and Communication Sciences
Examiners: Adjunct professor Kari Lahti
and M.Sc. Minna Niittymäki
May 2022
ABSTRACT
Simon Boonants: Testing and analysis of universal high voltage divider
Master of Science Thesis
Tampere University
Master’s Degree Programme in Electrical Engineering
May 2022

A newly built universal high voltage divider designed by VTT MIKES technical research center
of Finland is developed to measure DC, AC, SI, LI, composite and combined waveforms.
In comparison with a RC divider, the RCR divider is also utilized to measure DC voltages. All
different kinds of waveshapes can be measured within prespecified voltage level limits and there-
fore the name “universal” divider is given to the RCR divider. Preliminary calibration tests have
been done by VTT to verify the short-term performance of this device. The assembly, dynamic
behaviour analysis, PD measurements and different types of voltage stressing of this non-com-
mercial RCR divider are done at the high voltage laboratory of Tampere University and are in
general the main content of this thesis. The ultimate goal is that the device can be used by national
metrology institutes to calibrate commercial universal HV dividers and therefore the device can
be called a reference HV divider.
Due to the large amount of different measurements executed in TAU's HV lab, only a few types
of measurements are explained and discussed in detail in this final work. The conclusion at the
end is based on all the measurements that are carried out at the HV lab. The thesis aims in
general to give a profoundly and well-illustrated explanation of the executed measurements and
their results. The unit step response and partial discharge measurements are done in accordance
with the IEC standards. This implies that the test results are valuable and thus can be used for
further test measurements or for comparison with other high voltage dividers. References to these
standards and interpretation of the norm will be done were needed to increase the fidelity of the
thesis.
High voltage dividers are one of the components of a high voltage measurement system.
The task of these HV dividers is to reduce the high voltage to voltage levels that are appropriate
for our measurement devices (low voltage) without causing any distortions on the waveshape.
The decrease in voltage level is described by a dividing ratio also known as the scale factor SF
of the HV divider. Mankind has developed a broad range of high voltage dividers. The most com-
mon classification is based on the kind of wave shapes and directly correlated with it, are the
voltage levels that these high voltage dividers are able to measure. There is noticeable evolution
in the development of high voltage dividers where designers try and succeed to improve these
measurement devices.
The literature study includes an overview of the different kinds of HV dividers and explains the
main differences between them according to the working principle, circuit and specifications. The
main problems that these high voltage dividers are facing will be discussed to indicate the flaws
of these devices. This background is needed to gain insight and to understand the main part of
the thesis better, the testing and evaluation of the RCR high voltage divider itself. At the end a
summary of the main outcomes of this thesis will be presented to the reader and further possible
research will be indicated.

Keywords: high voltage divider, high voltage measuring system, universal divider, RCR divider

The originality of this thesis has been checked using the Turnitin OriginalityCheck service.
PREFACE
This thesis is the final work for my Master's degree in electrical engineering and
was carried out at the high voltage laboratory of Tampere University. I would es-
pecially like to thank adjunct professor Kari Lahti for giving me the opportunity to
deepen my knowledge of high voltage engineering during my Erasmus exchange
period at TAU. This thesis was also made possible by VTT, who designed the
universal high voltage divider and provided additional information about the RCR
divider.

The universal HV divider is part of the HV-com² project with funding from the
EMPIR programme co-financed by the European Union’s Horizon 2020 research
and innovation programme and the EMPIR Participating States.

Tampere, 27 May 2022

Simon Boonants
CONTENTS
1. INTRODUCTION .................................................................................................. 1
2. FUNDAMENTALS OF HIGH VOLTAGE MEASUREMENT SYSTEMS ................. 5
2.1 General high voltage testing system .................................................... 5
2.2 High voltage dividers ............................................................................ 6
2.2.1 General electric circuit composition ............................................... 6
2.2.2 Shielding of HV dividers ................................................................ 8
2.2.3 General characterisation of the dynamic behaviour..................... 12
2.2.4 Resistive HV divider .................................................................... 19
2.2.5 Capacitive HV divider .................................................................. 24
2.2.6 Series-damped capacitive HV divider.......................................... 28
2.2.7 Universal HV divider ................................................................... 31
2.2.8 Summary of the suitability of the HV dividers .............................. 34
2.2.9 Low voltage arm and measuring cable ........................................ 35
2.2.10 High voltage lead....................................................................... 40
2.3 Partial discharges .............................................................................. 41
2.3.1 Origin of partial discharges ......................................................... 41
2.3.2 Loss factor tan(δ) measurement method..................................... 42
2.3.3 Electrical PD pulse measurement method .................................. 43
2.3.4 Acoustic detection method .......................................................... 46
3. HV DIVIDER SIMULATIONS .............................................................................. 47
3.1 Objectives and introduction ................................................................ 47
3.2 Simulated HV divider networks .......................................................... 48
3.2.1 Resistive HV divider .................................................................... 48
3.2.2 Capacitive HV divider .................................................................. 49
3.2.3 Series-damped capacitive HV divider.......................................... 50
3.2.4 Universal HV divider ................................................................... 51
3.3 Amplitude-frequency response simulation results .............................. 52
3.4 Step response simulation results........................................................ 55
4. EXPERIMENTAL INVESTIGATIONS.................................................................. 60
4.1 Evaluation of the initial PD performance............................................. 60
4.1.1 Loss factor tan⁡(𝛿)....................................................................... 60
4.1.2 Electrical PD pulse ...................................................................... 66
4.2 Optimization of the PD performance .................................................. 70
4.2.1 Electrical PD pulse ...................................................................... 70
4.3 Setting of the external damping resistor value .................................... 73
5. CONCLUSIONS.................................................................................................. 76
6. FUTURE WORK ................................................................................................. 78
REFERENCES....................................................................................................... 79
LIST OF SYMBOLS AND ABBREVIATIONS

* Complex conjugate
̅̅̅
𝑍𝑐 Characteristic impedance
Γ̅ Reflection coefficient
𝜀0 Vacuum permittivity
AC Alternating current
AE Acoustic emitted
C Capacitor
CC Connecting cable
CD Coupling device
CRO Cathode ray oscilloscope
DC Direct current
EMI Electromagnetic interference
G(f) Amplitude-frequency response function
g(t) Unit step response function
HV High voltage
HVDC High voltage DC
IEC International Electrotechnical Commission
𝐼 Current (RMS-value)
𝐼𝑓 Phase current (RMS-value)
k Coulomb’s constant
L Inductance
LI Lightning impulse
LV Low voltage
LVDC Low voltage DC
MI Measuring instrument
n Dividing ratio, amount of identical circuit elements
PCB Printed circuit board
PD Partial discharge
R Resistance
RMS Root mean square
s(t) Step function
SF Scale factor
SI Switching impulse
TAU Tampere University
TML Transmission line
USR Unit step response
VSC Voltage source converter
V𝑙𝑙 Line-line voltage (RMS-value)
𝑉 Voltage (RMS-value), volume
𝑉𝑓 Phase voltage (RMS-value)
 1

1. INTRODUCTION

High voltage (voltage level > 1 kV) is used to transport large amounts of active
power over large distances. The lines used for this transport are better known as
HV transmission lines. An example of a HV transmission line is the Nemo link.
The Nemo Link is a subsea HVDC TML (Figure 1.1) that connects the non-syn-
chronized grids of Great Britain and Belgium with a capacity of 1012 MW at
400 kV with a length of 140 km.

Figure 1.1. Nemo-link between Belgium and The United Kingdom [1].
One of the reasons why a HVDC TML is used instead of the classical HVAC TML
for subsea cables is to solve a well-known problem. In subsea HVAC TML
(Figure 1.2 (a)) the parasitic capacitance C between the conductors is larger than
in overhead HVAC TML (Figure 1.2 (b)) because the distance d between the
conductors in subsea HVAC TML is smaller. This results in a larger drop of the
active power transport capacity in function of the length of the cable which will be
explained gradually. The ground capacitances are not represented on Figure 1.2
(a) and (b).
 2

Figure 1.2. (a) Parasitic capacitance between phase conductors of a 3 phase

subsea line. (b) Parasitic capacitance between phase conductors
of a 3 phase overhead line.
In a 50 Hz 3 phase AC net these parasitic capacitances will load and unload 50
̅ which reduces the
times per second, this needs a capacitive load current 𝐼𝑓
amount of active power 𝑃 that can be transmitted. The used cables have a
maximum admitted line current value 𝐼𝑧 that cannot be exceeded continuous oth-
erwise an overload of the cable will occur. The line voltage 𝑉𝑙𝑙 of the TML is
considered to be fixed. The total apparent power 𝑆̅, active power 𝑃 and reactive
power Q of the AC TML is equal to:

𝑆̅ = ⁡ √3 ∙ ⁡𝐼𝑧 ∙ 𝑉𝑙𝑙, (1.1)

𝑃 = ⁡ √3 ∙ 𝐼𝑧 ∙ 𝑉𝑙𝑙 ∙ 𝑐𝑜𝑠(𝜑), (1.2)

𝑄 = ⁡ √3 ∙ ⁡𝐼𝑧 ∙ 𝑉𝑙𝑙 ∙ 𝑠𝑖𝑛(𝜑). (1.3)

̅ for these parasitic capacitors with

In AC circuits the loading current⁡⁡𝐼𝑓
capacitance C [F/km] in each phase is equal to:

̅ = 𝑉𝑓
𝐼𝑓 ̅̅̅̅ ∙ 𝑗 ∙ 2 ∙ 𝜋 ∙ 𝑓 ∙ 𝐶, (1.4)

of which the absolute value is equal to:

𝐼𝑓 = 𝑉𝑓 ∙ 2 ∙ 𝜋 ∙ 𝑓 ∙ 𝐶. (1.5)
 3

The following proportions can be found:

𝐼𝑓⁡~⁡𝐶 [𝐹/𝑘𝑚],⁡⁡ (1.6)

𝐼𝑓⁡~⁡𝑙 = ⁡𝑙𝑒𝑛𝑔𝑡ℎ⁡𝑜𝑓⁡𝑡ℎ𝑒⁡𝑠𝑢𝑏𝑠𝑒𝑎⁡𝑐𝑎𝑏𝑙𝑒⁡[𝑘𝑚], (1.7)

𝐼𝑓⁡~⁡𝑉𝑓 = 𝑉𝑙𝑙/√3. (1.8)

This capacitive current 𝐼𝑓 is reactive and thus doesn’t contribute to the transport
of the useful active power P. Due to this reactive current a smaller part of the
available current⁡𝐼𝑧 (cos⁡(φ)⁡value⁡ < ⁡1) of the cable can be used for the
transmission of active power. This problem can be solved by using HVDC TML
for the subsea cable. In steady state HVDC there are no problems with parasitic
capacitances since they can be seen as an open circuit (capacitor is fully loaded)
and thus don’t need a permanent load current which reduces the active power
capacity of the transmission line. The available current 𝐼𝑧 can thus be fully used
for active power transport.

This problem concerning subsea HVAC is numerical visualised in Figure 1.3, con-
sider the distance between the conductors fixed for each curve. The HVDC cable
has only a small reduction in transmission capacity in function of the length of the
cable in comparison with HVAC due to the voltage drop over the conductors
which leads to heat dissipation. The available active power at a cable length of
0⁡km at a voltage level of 30⁡kV(peak)/mm is taken as a reference (100 %).

Figure 1.3. The power P that is possible to transmit as a function of the

distance for HVAC subsea cable of various voltage stresses
compared to HVDC subsea cable [2].
 4

This first part of the introduction was used to explain the importance of HVDC as
a TML. In the future there will be a raise of HVDC TML for example due to the
construction of new offshore wind farms that are used to generate renewable
energy to achieve the climate targets. Wind farms are often connected with the
main land by using subsea HVDC cables. The crucial link of these HVDC TML
with the main topic of the thesis is that the universal RCR divider is the only type
of HV divider that is able to measure certain composite and combined waveforms,
e.g. rated DC voltage 𝑉0 with a positive switching impulse with same polarity from
the VSC superimposed on it as visualised in Figure 1.4. The voltage 𝑉𝑃2,𝑆 is 1.15
times the maximum absolute peak value of the switching impulse voltage that the
cable can experience when the impulse has the same polarity as the actual DC
voltage. [3]

Figure 1.4. Composite waveform, DC voltage with positive SI

with same polarity superimposed on it [3].
A RCR divider can be used in HVDC and in HVAC applications. By means of this
introduction there was made an attempt to convince the reader about present
situation about the need of an universal divider at HV testing sites. The following
part will be dealing with more technical aspects of the HV dividers.
 5

2. FUNDAMENTALS OF HIGH VOLTAGE

MEASUREMENT SYSTEMS

2.1 General high voltage testing system

HV dividers are one of the components of the high voltage testing system. To
have a better understanding of the use of a HV divider it is also important to
possess the knowledge of the other devices. The general scheme of the testing
system is visualised in Figure 2.1.

Figure 2.1. Basic high voltage testing system. 1. Voltage supply, 2. lead to
test object, 3. test object, 4. lead with damping resistor 𝑅𝑑 to voltage divider,
5. high voltage divider, 6. signal or measuring cable, 7. recording instrument,
8. ground return. Adapted from [4].
The voltage supply (1) depends on which kind of test you want to execute, e.g.
for a lightning impulse test you can use a Marx generator as voltage supply. Lead
to test object (2) will have any impedance or resistance to damp oscillations, if
necessary what will be discussed later on, or to limit the short-circuit current if the
test object fails. The test object (3) is the object that you want to run your test on,
e.g. a surge arrester where you want to do a lightning surge test on to character-
ise the properties of this protective device. These three first components are part
of the voltage generating system. Connected to this is the voltage measuring
system consisting of a lead to the voltage divider (4) with a damping resistor. The
damping resistor serves 2 purposes, prevention of HF travelling wave
 6

phenomena on the lead consequent to reflections, as well as the damping of os-

cillations that arise in the HV circuit due to resonance what will be discussed later
on [5]. The high voltage divider (5) is then connected by a signal measuring cable
(6) towards the recording instrument (7) which can be for example an oscillo-
scope. This cable makes also the connection between the laboratory and the
control room. The ground return (8) on ground potential is also visualised on the
figure. [4]

This figure is not sufficient as a representation of the real more specified meas-
uring setup to perform tests, but it gives insight to understand the more detailed
measuring setups. There are measurement setups for high voltage testing that
are bounded to the IEC 60270 standards e.g. partial discharge measurements,
and will be explained profoundly in the section that discusses the experimental
investigations.

2.2 High voltage dividers

2.2.1 General electric circuit composition

The most general composition of an individual HV divider is visualised in

Figure 2.2. High voltage dividers consist roughly of 2 parts, a high voltage arm
and a low voltage arm. The name corresponds with the voltage level across it.
The voltage V is the HV across the entire HV divider. The voltage V2 is the low
voltage across the LV arm. The HV arm consists of n-1 identical elements and
the LV arm consists of just one element, so in total the HV divider contains n
identical elements. The higher the voltage level to be measured, the more equal
elements there are needed to get a LV across the LV arm that is suitable for our
measurement device. The bigger the needed voltage reduction, the greater the
height of the HV divider. From our network theory there can be easily compre-
hended that the impedances 𝑍′𝑙(𝑜𝑛𝑔𝑖𝑡𝑢𝑑𝑖𝑛𝑎𝑙) in series ensures the voltage reduc-
tion due to a voltage drop across 𝑍′𝑙 . So the number n is equal to:
𝑉
𝑛 = 𝑉2 = 𝑣𝑜𝑙𝑡𝑎𝑔𝑒⁡𝑟𝑎𝑡𝑖𝑜 = 𝑠𝑐𝑎𝑙𝑒⁡𝑓𝑎𝑐𝑡𝑜𝑟⁡𝑆𝐹⁡𝑜𝑓⁡𝑡ℎ𝑒⁡𝐻𝑉⁡𝑑𝑖𝑣𝑖𝑑𝑒𝑟. (2.1)

The symbol 𝑍′𝑞(𝑎𝑢𝑑𝑟𝑎𝑡𝑖𝑐)⁡ is the impedance from the HV divider to the ground, this
is better known as the stray capacitance 𝐶′𝑒 = ⁡ 𝑍′𝑞⁡ . Other possible stray capaci-
tances will be discussed later on. These stray capacitances will be assumed
 7

equally distributed along the HV divider. This makes it possible to make test sim-
ulations who are thus not entirely correct, but these simulations are still meaning-
ful and can be compared with real measurements. These stray capacitances can
have an non-negligible influence on the dynamic behaviour of the HV dividers. [4]

Figure 2.2. Distributed parameter equivalent circuit of high voltage dividers.

Adapted from [4].
If the voltage divider is considered as a lean, vertical cylinder without shielding
with its bottom end at earth potential, its total capacitance to earth 𝐶𝑒 works out
to:
2∙𝜋∙𝜀0 ∙𝑙
𝐶𝑒 = 𝑛 ∙ 𝐶′𝑒 = 2 𝑙 , (2.2)
𝑙𝑛⁡( ∙ )
√3 𝑑

where:

𝑙 is the height of the HV divider,

𝑑 the diameter of the cylinder,

𝜀0 is the vacuum permittivity. [5]

The distribution of the earth capacitances 𝐶′𝑒 of the general HV divider is visual-
ised in Figure 2.3 (a). The longitudinal impedance 𝑍′𝑙 represents the real hard-
ware components of the general HV divider (resistance 𝑅′ and capacitance 𝐶′)
inclusive their parasitic elements, the inductance 𝐿′⁡and parallel capacitance 𝐶𝑝′
that are visualised in Figure 2.3 (b). [4]
 8

Figure 2.3. (a) Equivalent circuit of a high voltage divider with distributed
earth capacitances 𝐶′𝑒 . (b) Individual element 𝑍′𝑙 of the circuit diagram.
Adapted from [4].
The different high voltage dividers that will be discussed, will always be derived
from this general composition. The values of the components of the high voltage
divider (𝐶 ′ 𝑒 , 𝑅 ′ , 𝐶 ′ , 𝐿′ ⁡𝑎𝑛𝑑⁡𝐶𝑝′)⁡⁡can thus be found and enables it to make simula-
tions by using software, e.g. the step response of the HV divider can be simu-
lated. Simulations makes it possible to evaluate the device without carrying out
real test measurements and makes it possible to compare the theoretical calcu-
lation with the real measurement result. It is assumed for the circuit diagram of
HV dividers as visualised in Figure 2.2 that the LV arm is an integral part of the
divider and provides an impedance structure which is equivalent to the HV arm.
In reality, the structure, i.e. the composition of the circuit elements is quite differ-
ent. Many distortions in the signal can be related to this part of the system and
will be discussed in the paragraph about the low voltage arm and measuring ca-
ble. [4]

2.2.2 Shielding of HV dividers

Any two adjacent conductors with a distance d between each other can be con-
sidered as a capacitor. HV dividers consist of parasitic capacitances due to their
conductive parts and their conductive surrounding elements, e.g. consider a re-
sistive HV divider that is part of a HV measurement system. This divider consists
of three types of parasitic capacitances as visualised in Figure 2.4. The capaci-
tances 𝐶′𝑝 are the parallel capacitances inherent to the construction of the
 9

resistors 𝑅′, 𝐶′ℎ are the stray capacitances to the HV lead and 𝐶′𝑒 the stray ca-
pacitance to the earth potential. These capacitances influence the dynamic be-
haviour of the resistive HV divider and are thus called parasitic. They are in the
first instance not adjustable and designable compared to the actual elements of
the HV divider. The parasitic capacitances are not equally distributed over the full
length of the HV divider and their values are sensitive for the distance to the sur-
rounding objects, assigning a place to these parasitic capacitances is a deviation
from reality.

Figure 2.4. Equivalent network of an non-shielded resistive HV divider with

three different types of parasitic capacitance visualised 𝐶′𝑝 ⁡, 𝐶′ℎ and 𝐶′𝑒 .
Adapted from [4].
Several shielding designs are made to suppress the influence of parasitic capac-
itances and to gain more control over these parasitic capacitances. The common
design addition applied to HV dividers that will be discussed is the use of one or
more toroid-shaped grading rings visualised in Figure 2.6. For special measure-
ment tasks, smaller impulse voltage dividers up to a few 100 kV are accommo-
dated in a metallic housing for purposes of complete shielding. As a rule, bigger
voltage dividers (more than a few 100 kV) are not completely shielded, it is mostly
a high voltage divider with large toroid electrodes both at its top and base. [5]

The hardware elements (resistors, capacitors) can also be accommodated in an

insulating cylinder of hardboard Plexiglas or fibreglass-reinforced plastic, this is
important for the mechanical stability as well as electrical strength. For
 10

improvement of the flashover strength inside or for the heat transfer to the outside
during long-term loading, impulse voltage dividers are sometimes filled with insu-
lating gas under high pressure or with insulating oil. [5]

HV dividers with grading rings

In order to understand the principle and use of grading rings, the electrical field
distribution along the HV divider must be discussed. In Figure 2.5 the distribution
of equipotential electric field lines along the HV column of a resistive HV divider
without field grading is visualised. This figure makes it possible to see that the
electric field has a normal component (perpendicular to the axis of the HV divider
column) and a parallel component. Another conclusion that can be drawn is that
the field distribution between the HV electrode and the earth electrode is highly
not linear i.e. without considering the resistance column. The field strength 𝐸 in
the vicinity of a spherical electrode with charge Q decreases with the square of
the distance 𝑑 from the sphere:
𝑘∙𝑄 1
𝐸= ⁡~⁡ 𝑑2 , (2.3)
𝑑2

where:

k is the Coulomb’s constant. [5]

This means that the field strength in close proximity of the divider top electrode
is especially high compared to the field strength at lower region of the voltage
divider. In the extreme case, more than half of the field strength appears at the
upper 20 % of the divider height. In the upper region of the voltage divider, there
is therefore a marked difference between both fields, which leads to a strong nor-
mal component of the resulting field perpendicular to the divider column. This
normal component of the field is the driving force behind the frequency-depend-
ent leakage current that flows through the earth capacitances of the divider and
worsens its transfer behaviour at high frequencies. In Figure 2.6 (a) and (b) two
possible methods are described to nullify approximately the normal component
of the electric field and hence the capacitive leakage current to earth. [6]
 11

Figure 2.5. Distribution of equipotential electric field lines along the HV col-
umn of a resistive HV divider without field grading. Adapted from [6].
In Figure 2.6 (a) multiple grading rings equally distributed along the full length of
the HV divider and each with its own potential P are used. In Figure 2.6 (b) only
one grading top electrode is used. This grading ring(s) ensures that the distribu-
tion of the electric field is almost completely linear and parallel to the x-direction,
thus the voltage distribution will be linear as well. A reduction of the density of the
electric field at the top electrode is achieved, which reduces the voltage stress on
the insulator at the top of the HV divider. Another effect is that the stray capaci-
tances to ground 𝐶′𝑒 or to the HV lead 𝐶′ℎ are suppressed and only the negligible
parallel capacitances C′p remain. Both shielding requirements are fulfilled, sup-
press the stray capacitances and make the stray capacitances more controllable
by having an equally distribution of these parasitic elements 𝐶′𝑝 over the entire
length of the divider. [4]

If the current distribution and hence the resistance distribution of the voltage di-
vider is matched with the undisturbed field pattern of the HV electrode then the
normal component is also nullified. This type of divider is called a field-conformal
HV divider and will not be examined in detail.
 12

Figure 2.6. Suitable methods for the shielding of HV resistive dividers (a)
multiple grading rings (b) grading top electrode. Adapted from [4].
To avoid flashovers the high voltage divider including the top electrode, the con-
necting lead and the damping resistor should have sufficient clearance to the
walls and other neighbouring objects with the size of the distance depending on
the voltage level at the top electrode. The top toroid electrode can be so dimen-
sioned that it functions as an external overvoltage protection, it initiates a flasho-
ver when the rated voltage of the divider is exceeded. In such an event, the HV
divider is surely protected, but not the high voltage lead with damping resistor. [5]
Another benefit of linearising the electrical field alongside the HV divider is that
the PD behaviour of the HV divider can be improved. PD are typically caused by
local enhancements of the electrical field e.g. sharp edges. PD will be discussed
more thoroughly at the paragraph about the PD measurements of the RCR di-
vider.

2.2.3 General characterisation of the dynamic behaviour

The dynamic behaviour of the high voltage divider can be characterised by the
unit step response g(t) of the HV divider in the time domain, this method is used
for impulse voltages. In frequency domain the transfer behaviour is characterised
by the amplitude-frequency response H(jω) = G(jω) and will be applied for DC
and AC voltages. The meaning of g(t) and H(jω) is visualised in Figure 2.7.
 13

Both forms are mutually convertible by using the (inverse) Laplace transfor-
mation:
1
𝑔(𝑡) = ⁡ 𝐿−1 {𝑠 ∙ ⁡𝐻(𝑗𝜔)}. (2.4)

Based on the amplitude-frequency response the bandwidth of the HV divider can

be determined, the unit step response makes it possible to analyse the dynamic
behaviour of the HV divider with impulse voltages as input. This section deals
with the theoretical background of the unit step response g(t) and the amplitude-
frequency response G(f) with the aim of simulating them for each type of
HV divider and analysing the results.
Unit step response
The unit step response g(t) of the HV divider describes the relationship between
the input signal 𝑣(𝑡) and the output signal 𝑣2 (𝑡):
𝑣(𝑡) = 𝑉 ∙ 𝑠(𝑡), (2.5)
𝑣2 (𝑡) = 𝑉2 ∙ 𝑔(𝑡), (2.6)
where 𝑠(𝑡) is the unit step function with the time-dependent form:
𝑠(𝑡) = 0⁡𝑓𝑜𝑟⁡𝑡 < 0, (2.7)
𝑠(𝑡) = 1⁡𝑓𝑜𝑟⁡𝑡 > 0. (2.8)
Equitation (2.6) divided by equitation (2.5):
𝑔(𝑡) 𝑉2 𝑣2 (𝑡)
∙ = ,⁡ (2.9)
𝑠(𝑡) 𝑉 𝑣(𝑡)

V 𝑣2 (𝑡)
𝑔(𝑡) = 𝑠(𝑡) ∙ 𝑉 ∙ , (2.10)
2 𝑣(𝑡)

for 𝑡 > 0:
V 𝑣2 (𝑡) 𝑣2 (𝑡)
𝑔(𝑡) = 𝑉 ∙ = 𝑆𝐹 ∙ . (2.11)
2 𝑣(𝑡) 𝑣(𝑡)

Figure 2.7. Characterisation of a linear system by the step response g(t) or

the transfer function H(jω). Adapted from [5].
 14

The function g(t) can be calculated by using the equivalent network with imped-
ances or can be measured in accordance with the IEC 60060 standard. An ex-
ample of an arbitrary unit step response which has been obtained by running a
simulation to indicate the USR parameters is visualised in Figure 2.8.

Figure 2.8. Unit step response function [5].

The USR measurement of a HV divider need to satisfy requirements that are
listed in the IEC 60060 standard for which the measuring system is to be ap-
proved. More specifically, these requirements must be checked for each type of
impulse voltage that you want to measure with this HV divider separately, e.g. a
lightning impulse with 𝑇1 ⁡= 1.2 µs ± 30 % and 𝑇2 ⁡= 50 µs ± 20 %. If the require-
ments on the step response are met for a given waveform, the dynamic behaviour
of the voltage divider is recognised as adequate for the measurement of this
waveform [5]. This is not sufficient because there is no direct correlation between
the USR and correct measurement of impulse voltages, but the USR remains
important for characterising the dynamic behaviour of the HV divider for impulse
voltages. In order to check if the requirements are fulfilled, the response param-
eters of the USR that are defined in Figure 2.8 need to be known. As these criteria
 15

are not checked for the USR results in this thesis, only the parameters of Figure
2.8 that are used in this thesis to evaluate the unit step response are explained:

𝛽 is the overshoot of the USR,

𝑔̂ is the peak value of the step response g(t),

𝑡𝑠 ⁡is the settling time,

𝑡1 is the rise time.

The better numerical evaluation method to determine if the HV divider is suitable

for measuring the impulse voltage is to study the deformation of the standard
impulse by convolving the given impulse with the step response and look how the
impulse or its parameters change in the process. This is called the convolution
theorem. If the USR is known, the convolution integral also known as Duhamel’s
integral offers the possibility for calculating the output signal 𝑣2 (𝑡) for any arbitrary
input signal 𝑣(𝑡) without the need to do expensive experimental measurements
e.g. if the unit step response is known we can determine the output signal of the
HV divider when a lightning impulse is put at the input side. [5]

This convolution theorem will be discussed in the next paragraph. The IEC 60060
standard suggests a preferred arrangement for USR measurement as visualised
in Figure 2.9. The circuit arrangement used for determining the step response
should be described in the record of performance. The record of performance
contains the results of all tests and checks, including the conditions under which
the results were obtained. The step generator (1) is placed at a metallic wall or at
a metallic strip conductor (5) at least 1 m wide, which serves as the earth return.
The damping resistor (2) is connected to the HV lead towards the HV divider (3).
The measuring system (4) is connected to the LV arm of the HV divider. [7]
 16

Figure 2.9. Preferred arrangement for unit step response measurement.

1. Step generator, 2. damping resistor, 3. HV divider, 4. measuring instrument,
5. earth return conductor. Adapted from [5].
Convolution theorem
The content of this paragraph is almost entirely referenced to the IEC 60060
standard due to its theoretical nature, but knowledge of it is necessary to under-
stand the thesis. The convolution method is used for the determination and eval-
uation of the dynamic performance of an impulse HV divider from step response
measurements. This method uses the step response of the measuring system to
calculate its output impulse waveform from the input impulse waveform.
The errors of the impulse parameters of the output waveform relative to the input
waveform can be used to evaluate the performance of the measuring system for
a particular waveform to be measured. To use the convolution method correctly,
the step response of the measurement system has to be measured in accordance
with the IEC 60060 standard as described above and the input waveform used in
the calculation needs to be representative for the real impulse waveform that the
HV divider would measure, conditions for the input waveform are listed in the IEC
60060 standard. [7]
 17

The symbol 𝑣2 (𝑡) can be expressed by the following convolution integral:

𝑡 𝑑𝑣(𝜏)
𝑣2 (𝑡) = ∫0 ∙ 𝑔(𝑡 − 𝜏) ∙ 𝑑𝜏, (2.12)
𝑑𝑡

where:

𝑔(𝑡)⁡is the known unit step response of the system,

𝑣(𝑡) is the known arbitrary input signal,

𝑣2 (𝑡) is the output signal that we want to calculate.

If 𝑔(𝑡) and 𝑣(𝑡) are sampled with the same sampling interval and the number of
samples of 𝑔(𝑡) is the same as that of 𝑣(𝑡), the continuous convolution integral
reduces to the causal form of the discrete convolution sum:
𝑑𝑣(𝑘)
𝑣2 (𝑖) = ⁡ ∑𝑖𝑘=0 ∙ 𝑔(𝑖 − 𝑘) ∙ ∆𝑡, (2.13)
𝑑𝑡

where:

𝑣2 (𝑖) is the discrete output array,

𝑑𝑣(𝑖)
is the first derivative of input array,
𝑑𝑡

𝑔(𝑖) is the unit step-response array,

n is the number of samples of the input array,

∆𝑡 is the sampling interval of the input and output arrays, and the step-response
array.

The input signal v(t) is clearly considered as a superposition of many small time-
displaced individual steps as visualised in Figure 2.10. Each individual step ∆𝑣(𝑖)
generates the corresponding step response ∆𝑣2 (𝑖) at the output terminal. Super-
position of the individual step responses results in the time-discrete output signal
∆𝑣2 (𝑖), which, for infinitesimally small times, results in 𝑣2 (𝑡). [5]
 18

Figure 2.10. Representation of a voltage signal 𝑣(𝑡) by time displaced

voltage steps ∆𝑣(𝑖). Adapted from [5].
Amplitude-frequency response

The function 𝐺(𝑓) is the ratio of the output 𝑉2⁡ to the input 𝑉⁡of a measuring system
as a function of the frequency 𝑓 when the input is sinusoidal. An example of the
function 𝐺(𝑓) is visualised in Figure 2.11. The symbol 𝐺𝑚 is the constant value of
the amplitude-frequency response. The frequencies 𝑓1 and 𝑓2 are the lower and
upper limit of the range within which the amplitude-frequency response is nearly
constant. These limits are where the response deviates by a certain amount e.g.
plus/minus 15 % from the constant value. [7]

Figure 2.11. Amplitude-frequency response with examples for

limit frequencies (𝑓1 ,𝑓2 ) [7].
 19

RCR HV dividers are known to measure voltages in a wide frequency spectrum

from DC to lightning impulse voltages. The amplitude-frequency response 𝑮(𝒇)
is used to prove that the divider ratio remains constant within this broad frequency
range moreover we want to determine the bandwidth of the HV divider. These
scale factors are to be determined preferably by comparative measurements with
an accurate reference measuring system according to the IEC 60060 standards.
[5]

2.2.4 Resistive HV divider

The most general representation of resistive HV dividers is visualised in Figure

2.12. The circuit consists of the actual resistor elements R′ and their parasitic
inductances L′⁡ , who are inherent with every flow of current based on Ampere’s
law. The parallel parasitic capacitances C′ p are due to the construction of the
resistors. Also the stray capacitances to the ground C′e⁡ are visualised. Every ele-
ment with an index 1 refers to the high voltage arm and every element with index
2 refers to the low voltage arm, e.g. 𝑅1 is the equivalent resistance of the HV arm.
Please note that elements without an index refer to the entire HV divider, e.g. V
is the voltage across the complete HV divider. [4]

Figure 2.12. Equivalent circuit for resistor HV dividers. 𝑅 = 𝑛 ∙ 𝑅 ′ , 𝐿 = 𝑛 ∙ 𝐿′⁡ ,

𝐶′𝑝
𝐶𝑒 = ⁡𝑛 ∙ 𝐶 ′ 𝑒⁡ , 𝐶𝑝 = ⁡, 𝑅2 = ⁡ 𝑅 ′ , 𝐿2 = 𝐿′ , 𝑅1⁡ = (𝑛 − 1).
𝑛
Adapted from [4].
For DC voltages the frequency is equal to zero and the dividing ratio can be easily
found because all the capacitances can be considered as an open circuit and the
 20

inductances can be considered as a short circuit. In DC steady state the dividing

ratio of the resistive HV divider is equal to:
𝑅2 𝑉
𝑉2 = 𝑉 ∙ 𝑅 = 𝑛⁡, (2.14)
1 +𝑅2

𝑉 𝑅1 +𝑅2
𝑛 = ⁡ 𝑉2 = . (2.15)
𝑅2

It may happen that there is some not negligible ripple on the DC voltage e.g. after
rectifying AC voltage into DC voltage. So higher frequencies than zero will occur
in the signal that needs to be measured, which implies that the capacitances and
inductances of the circuit have to be taken in account. The equivalent circuit vis-
ualised in Figure 2.12 can be simplified, the transfer function of this circuit is equal
to [4]:
1 (𝑅+𝑠∙𝐿)∙𝑠∙C
e )⁡
sinh⁡( ∙√
𝑛 1+(𝑅+𝑠∙𝐿)∙𝑠∙C p
𝐻(𝑠) = 𝑛 ∙ (𝑅+𝑠∙𝐿)∙𝑠∙Ce
. (2.16)
𝑠𝑖𝑛ℎ(√ )
1+(𝑅+𝑠∙𝐿)∙𝑠∙Cp

If 𝑅 is put before the brackets in the numerators and denumerators, the following
equitation is obtained:
𝑠∙𝐿
1 𝑅∙(1+ 𝑅 )∙𝑠∙Ce
sinh⁡( ∙√ 𝑠∙𝐿 )⁡
𝑛 1+𝑅.(1+ 𝑅 )∙𝑠∙Cp
𝐻(𝑠) = 𝑛 ∙ . (2.17)
𝑠∙𝐿
𝑅∙(1+ 𝑅 )∙𝑠∙Ce
𝑠𝑖𝑛ℎ(√ 𝑠∙𝐿 )
1+𝑅∙(1+ 𝑅 )∙𝑠∙Cp

𝐿
For resistive HV dividers is 𝑅 << 1, 𝐻(𝑠) becomes approximately equal to:

1 𝑅∙𝑠∙C
e )⁡
sinh⁡( ∙√
𝑛 1+𝑅∙𝑠∙C p
𝐻(𝑠) ⁡ ≈ 𝑛 ∙ 𝑅∙𝑠∙Ce
, (2.18)
𝑠𝑖𝑛ℎ(√ )
1+𝑅∙𝑠∙Cp

and also Cp << Ce and Cp << 1 for resistive HV dividers then the final expression is
obtained:
1
sinh( ∙√𝑅∙𝑠∙Ce )
𝐻(𝑠) ≈ 𝑛 ∙ 𝑛
. (2.19)
𝑠𝑖𝑛ℎ(√𝑅∙𝑠∙Ce )

The dynamic behaviour only depends on the resistance value 𝑅 and the earth
capacitance value Ce , so every parasitic inductance L’ and capacitance C′p who
are related to the resistances in the circuit can be neglected. A RC circuit is ob-
tained, this causes that the response time will be proportional with R ∙ Ce . The
divider ratio will be time-dependent and frequency-dependent. The circuit
 21

diagram visualised in Figure 2.13 can be obtained from these simplifications. This
circuit diagram allows to carry out useful simulations to characterize the dynamic
behaviour of the divider. [4]

2
Figure 2.13. Common equivalent circuit, with 𝐿 = 𝐶𝑝 = 0 and 𝐶𝐸 = (3) ∙ 𝐶𝑒 .
Adapted from [5].
Consider 𝑪𝒆 to be fixed for a divider with a height h and a diameter d then the
bandwidth will only be inversely proportional with the only left degree of freedom,
the resistance value R. This resistance value R is the sum of individual re-
sistances R’ in series. Two types of categories are made to subdivide resistive
HV dividers. The first type are high ohmic HV dividers with 𝑅 value within the
range of MΩ to measure DC, AC and switching impulses. The second type are
low ohmic HV divider with 𝑅 value within the range of kΩ to measure only lightning
impulses appropriate.

High ohmic HV dividers are not used to measure lightning impulses because the
response time is too high. The high ohmic HV divider is best suited for DC voltage
measurements with limits depending on the frequency of the ripple on the DC
voltage part. Low ohmic HV dividers are only used for lightning impulses because
of their small response time and their heat dissipation that would be too large if
longer lasting measurements would be carried out. The resistances 𝑅′ will heat
 22

up when a current 𝐼 flows through it based on Joule’s law, the more time the
voltage measurement lasts the higher the heat dissipation 𝐸:

𝑃 = 𝑅 ′ ∙ 𝐼 2 ,⁡ (2.20)

𝐸 = 𝑃 ∙ 𝑡. (2.21)

An increase of the current 𝐼 has a greater effect than an equal decrease of the
resistance value 𝑅′ due to the quadratic dependence of heat losses on the current
𝐼 (𝑃~⁡𝐼 2 ). It takes time for the resistor to give of heat, e.g. by convection and thus
the time period between each measurement will have an influence as well on the
temperature of the resistances. The final temperature 𝑇2 of the resistances after
applying a SI or LI at ambient temperature 𝑇1 ⁡can be calculated by following this
reasoning. The timespan of a SI and LI is so small (ms range) that the energy of
the applied impulse 𝐸𝑖𝑚𝑝𝑢𝑙𝑠𝑒 can be assumed to be fully absorbed as heat 𝑄 by
the resistors of the HV divider:

𝐸𝑖𝑚𝑝𝑢𝑙𝑠𝑒 = 𝑄 = 𝑚 ∙ 𝐶 ∙ (𝑇2 − 𝑇1 ), (2.22)

𝐸𝑖𝑚𝑝𝑢𝑙𝑠𝑒
𝑇2 = + 𝑇1, ⁡ (2.23)
𝑚∙𝐶

𝑚 = 𝑉 ∙ 𝜌 = mass⁡of⁡the⁡resistive⁡wire, (2.25)

V = 𝑙 ∙ 𝐴 = volume⁡of⁡the⁡resistive⁡wire,⁡ (2.26)

𝜋∙𝑑2
A= ∙ 𝜌 = cross⁡section⁡of⁡the⁡resistive⁡wire, (2.27)
4

where:

𝜌 is the mass density of the wire,

𝑑 is the diameter of the wire,

𝑙 is the length of the wire,

𝐶 is the heat capacity of the wire.

The energy of an impulse voltage can be computed via a calculation tool if the
total resistance 𝑅 of the HV divider, the time parameters and peak voltage of the
impulse are known. Wirewound resistances are used for resistive HV dividers
due to their high power capability. If the calculated 𝑇2 exceeds the maximum
specified temperature of the resistance then the HV divider is not suited to
 23

measure such an impulse voltage. A numerical example is not elaborated in this

thesis, but can be carried out using this reasoning.

Another limitation for resistive HV dividers is the voltage level that needs to be
measured. The first approach, the larger the voltage level that needs to be meas-
ured by a HV divider, the higher the current, the higher the heat dissipation. The
second approach, if a low ohmic resistive HV divider needs to be designed, more-
over the 𝑅 ′ value of the HV divider needs to be determined to obtain a response
time of 50 ns to measure a full standard 1.2/50 µs lightning impulse. The higher
the voltage level 𝑉 of this lightning impulse the harder it will be to design the
device. Consider that a fixed voltage level 𝑉2 is needed across the low voltage
arm which is appropriate for the oscilloscope, if 𝑉 increases than the amount of
elements n need to increase as well:
𝑉↑
𝑉2 = 𝑛↑ = 𝑓𝑖𝑥𝑒𝑑. (2.28)

This implies that the total resistance value R of the entire HV divider increases:

⁡R ↑= n ↑∙ R′ , (2.29)

𝑟𝑒𝑠𝑝𝑜𝑛𝑠𝑒⁡𝑡𝑖𝑚𝑒⁡ ↑ ⁡ ~⁡𝑅 ↑.⁡ (2.30)

In case of a raise of V, a fixed response time is obtained if 𝑅 is kept constant.

R = n ↑∙ R′ ↓. (2.31)

It can be concluded that a constant response time and constant voltage 𝑉2 across
the LV arm that are suitable to measure lightning impulses in case of a raise of
the voltage level V can only be obtained if the value of the resistance element R’
decreases, which causes a higher current based on Ohm’s law and more heat
losses which are proportional to the current squared. There are restrictions on
the voltage level that this low ohmic HV divider can measure, due to the heat
losses that must fall within predefined limits. A summary can be made based on
the conclusions of the analysis above for the two types of resistive HV dividers,
listed in Table 2.1.
 24

Table 2.1. Application high ohmic and low ohmic HV divider. ++ works well,
+works, - problems or limitations, – cannot be used. Adapted from [8].
Divider Type DC AC SI LI

Resistive High Ohmic (𝑅~⁡𝑀Ω) ++ + + -

Low Ohmic (𝑅~⁡𝑘Ω) - - - ++

2.2.5 Capacitive HV divider

To overcome the main problem with pure resistive HV dividers i.e. the heat dissi-
pation, the use of pure capacitive dividers for AC and SI is a good alternative.
The HV divider will never heat up significantly based on Joule’s law (𝑃 = 𝑅. 𝐼 2 ),
even though voltages in the range of MV are used [6]. This statement can be
verified after analysis of the equivalent circuit. In Figure 2.14 the equivalent circuit
of a pure capacitive HV divider is visualised. The capacitors C′ are the stacked
capacitor elements, L′ takes the inductance due to the currentflow in account and
𝑅 ′ elements represents on the one hand the losses within the capacitor elements
C′ and on the other hand the resistance of the connecting conductors. Also the
stray capacitances 𝐶 ′ 𝑝 between each column are visualised and the ground stray
capacitance 𝐶′𝑒⁡ to complete the circuit. [4]

Figure 2.14. Equivalent circuit for capacitor HV dividers. 𝑅 = 𝑛 ∙ 𝑅 ′ , 𝐿 = 𝑛 ∙ 𝐿′⁡ ,

𝐶′𝑝 𝐶′
𝐶𝑒 = ⁡𝑛 ∙ 𝐶 ′ 𝑒⁡ , 𝐶𝑝 = ⁡, 𝐶 = , 𝑅2 = ⁡ 𝑅 ′ , 𝐿2 = 𝐿′ , 𝐶2 = 𝐶. Adapted from [4].
𝑛 𝑛

Pure capacitive dividers are used for the measurement of AC voltages and
switching impulse voltages up to the highest test voltage levels (MV range) and
 25

the scale factor is not frequency dependent in this frequency range, what will be
discussed later on. They are not suited for LI voltages, due to the fact that the
capacitor elements 𝐶′ form together with the inductances 𝐿′ a series-resonant LC-
circuit that oscillates at frequencies in the megahertz range. The output voltage
will oscillate with non-oscillating input voltages. These oscillations are only
weakly damped by the connection conductors’ resistances and losses in the ca-
pacitors. With an external damping resistor 𝑅𝑑 at the beginning of the HV lead or
at the divider top, these oscillations can be reduced to such an extent that the
capacitive HV divider can be employed for the measurement of LI voltages also.
Damping will be further discussed in the paragraph about series-damped capac-
itive HV dividers. [5]

The frequency independence of the HV divider for AC and SI can be verified by

introducing a fair simplification. The influence of the resistances 𝑅′ and induct-
ances 𝐿′ on the dynamic behaviour of the HV divider is negligible for AC and SI
voltages, no oscillations occur and the bandwidth of the HV divider will be not
exceeded in this frequency range. The equivalent circuit of Figure 2.14 can be
reduced for AC and SI voltages to the circuit of Figure 2.15 (a) by these simplifi-
cations. The equivalent circuit of Figure 2.15 (a) can then be further simplified in
1
a way that the HV capacitance C1 is reduced by an amount (6) ∙ 𝐶𝑒 to obtain the

circuit visualised in Figure 2.15 (b) consisting of two capacitances.

Figure 2.15. Simplified equivalent circuit of a HV capacitive divider for AC

and SI in which the earth capacitance 𝐶𝑒 is accounted for by a (a) parallel
2 1
capacitance 3 ∙ 𝐶𝑒 , (b) reduced HV arm capacitance 𝐶1 − (6) ∙ 𝐶𝑒 .
Adapted from [5].
 26

Unlike resistive HV dividers, the dynamic behaviour of the capacitive HV divider

for SI and AC voltages that can be determined via Figure 2.15 (b) does not de-
pend on the frequency 𝑓:
1 1
𝑉 𝑗 ∙2∙𝜋 ∙𝑓∙(𝐶1 − ∙𝐶𝑒 +C2 ) C1 −( )∙𝐶𝑒 +C2
𝑆𝐹 = 𝑉 = 6
1 =⁡ 6
1 ⁡, (2.32)
2 𝑗 ∙2∙𝜋∙𝑓∙(C1 −( )∙𝐶𝑒 ) (C1 −( )∙𝐶𝑒 )
6 6

1 1
when C2 ⁡(nF range) >> C1 − (6) ∙ 𝐶𝑒 (pF range) and C1 >> (6) ∙ 𝐶𝑒 :

𝑉 C2 C
𝑆𝐹 = 𝑉 = 1 = C2.⁡ (2.33)
2 (C1 −( )∙𝐶𝑒 ) 1
6

As a consequence of the effect of the earth capacitance 𝐶𝑒 ⁡in both equivalent

circuits, the current through the LV capacitor C2 is reduced, so that the output
voltage 𝑉2 across C2 is smaller. The divider ratio SF of the HV divider is accord-
ingly increased. The dividing ratio remains unchanged for low and high frequen-
cies. For these low and high frequencies the capacitances will function as a cur-
̅̅̅𝑐 = ⁡ 1 ). Together with the fact that the total resistor
rent-limiting impedance (𝑍 𝑗∙2∙𝜋∙𝑓∙𝐶

value 𝑅 is negligible, it has been demonstrated that capacitive HV dividers will

never heat up significantly based on Joule’s law: (𝑃 = 𝑅 ∙ 𝐼 2 ), even though volt-
ages in the range of MV are used. Pure capacitive HV dividers are therefore per-
fectly suited for AC and SI voltage measurements. [6]
1
The influence of the stray capacitance 𝐶𝑒 can be neglected (C1 >> (6) ∙ 𝐶𝑒 ) in the

analysis of the dynamic behaviour of the capacitive divider. In the further modifi-
cations of the capacitive divider e.g. series-damped capacitive divider and RCR
divider the stray capacitance will no longer be taken into account in order to main-
tain the simplicity of the circuit diagrams that gives insights. Capacitive HV divid-
ers are not usable for steady state HVDC measurements. Capacitors are repre-
sented in HVDC (frequency f = 0) steady state by an open chain:
1 1
̅̅̅
𝑍𝑐 = 𝑗∙2∙𝜋∙𝑓∙𝐶 = 𝑗∙2∙𝜋∙0∙𝐶 = ⁡∞, (2.34)

if this equitation is applied to Figure 2.15 (b) it means that the value of 𝑉2 will be
indeterminate and no correct HV measurement can be done.

A compressed gas capacitor device that is visualised in Figure 2.16 with single
capacitor units 𝐶1 and 𝐶2 is used to obtain a higher precision of the capacitance
 27

values by avoiding any stray capacitance to earth and to obtain a very low loss
factor 𝑡𝑎𝑛(𝛿) value in comparison with a capacitive HV divider with stacked ele-
ments. The loss factor 𝑡𝑎𝑛(𝛿) is in general about 10e-5 [4]. These devices are
frequently used as a standard capacitor within HV bridges for loss factor 𝑡𝑎𝑛(𝛿)
measurements that will be later on discussed. The capacitance 𝐶1 is the standard
capacitance used for loss factor 𝑡𝑎𝑛(𝛿) measurements and both capacitances 𝐶1
and 𝐶2 are used for voltage measurement purposes. The compressed insulating
gas, such as 𝑆𝐹6 , ensures an excellent stability of the capacitance at changing
temperatures and changing applied voltage level. The main disadvantage of
these capacitors is that they are more expensive than HV dividers with stacked
capacitor elements. Guard electrodes are used to prevent the influence of any
external distortion on the signal. A more detailed discussion of such devices is
not part of the content of this thesis. A summary can be made based on the con-
clusions of the analysis above for capacitive HV dividers, listed in Table 2.2.

Figure 2.16. SF6 filled compressed gas standard capacitor [6].

Table 2.2. Application capacitive HV divider. ++ works well, + works,
- problems or limitations, – cannot be used. Adapted from [8].
Divider Type DC AC SI LI
Capacitive -- ++ ++ -
 28

2.2.6 Series-damped capacitive HV divider

The improvement of pure capacitive voltage dividers with the aim to avoid the
oscillations when LI voltages are applied, can be made if real resistor units are
inserted in series with the capacitors 𝐶 ′ . If the value of these resistors is not too
high, but just sufficient to damp the oscillations, it is likely to achieve an excellent
transient performance. The series-damped capacitive divider is thus suited for
measuring AC, SI and LI high voltages. The equivalent circuit for a HV series-
damped capacitive divider visualised in Figure 2.17 is the same as Figure 2.15
(b) with only one notable difference, the resistance value 𝑅′ not only represents
the losses within the capacitor elements C′ and the resistance of the connecting
conductors, but also the real resistor units that are inserted in series with the
capacitors 𝐶. The damped capacitive impulse voltage divider is also known as
the Zaengl divider, referred to the name of the inventor of the series-damped
capacitive divider.

Figure 2.17. Equivalent circuit of a series-damped capacitive HV divider.

 29

The damped capacitive HV divider functions at high frequencies as a low ohmic

resistive HV divider then the ohmic divider ratio is effective owing to low capaci-
tive impedances (low capacitive impedances ̅̅̅
𝑍𝑐 are negligible compared to 𝑅):
1
𝑅 >> ̅̅̅
𝑍𝑐 ↓↓⁡= ⁡ 𝑗∙2∙𝜋∙𝑓↑↑∙𝐶. (2.35)

The capacitive ratio is effective at low frequencies owing to high capacitive im-
pedances (total resistance 𝑅 is negligible compared to the capacitive impedances
̅̅̅
𝑍𝑐 ):
1
𝑅 << ⁡ ̅̅̅
𝑍𝑐 ↑↑⁡= ⁡ . (2.36)
𝑗∙2∙𝜋∙𝑓↓↓∙𝐶

Therefore to achieve a frequency independent scale factor, the time constants 𝜏1

and 𝜏2 of the damped capacitive high- and low voltage part have to be equal:
𝑅 𝐶
𝜏1 = 𝜏2 → ⁡ 𝑅1 ∙ 𝐶1 = 𝑅2 ∙ 𝐶2 ↔ 𝑅1 = 𝐶2.⁡⁡ (2.37)
2 1

Otherwise if both time constants are not matched an inappropriate measurement

will be executed when measuring a signal that covers a certain frequency range.
Damped capacitive HV dividers are also not usable for HVDC steady state meas-
urements due to the same reason as discussed for capacitive HV dividers. The
HV arm design of impulse dividers usually consists of a helix-structure which is
visualised in Figure 2.18 (a). This design avoids sharp bends, which can lead to
partial discharges. A disadvantage of this concept is that inductance is inherent
to this design. To get a better dynamic behaviour, the damped capacitive branch
of the HV arm is divided into two helices. The first one (indices ‘1’) will be winded
clockwise, the second one (indices ‘2’) anticlockwise. In that arrangement, the
magnetic fields 𝐵 of the two helices will cancel each other in the common inner
area as shown in Figure 2.18 (b). [9]
 30

Figure 2.18. (a) Helix design of a resistive-capacitive HV divider. Adapted

from [10]. (b) Magnetic field situation by using double helix design.
Adapted from [9].
The magnetic field B between the two windings cannot be considered as zero,
the inductivity of the divider can be minimised, but not eliminated in this way. The
inductivity of the capacitors themselves get lower due to the two parallel
branches. This will result in a better step response with less overshoot and re-
spectively less oscillations. [9] Low ohmic resistive HV dividers and series-
damped capacitive HV dividers are both capable of measuring LI voltages, but
with one difference, series-damped capacitive HV dividers are capable of meas-
uring also an AC voltage with LI superimposed on it which is a huge benefit. A
summary can be made based on the conclusions of the analysis above for series-
damped capacitive HV dividers, listed in Table 2.3.

Table 2.3. Application series-damped capacitive HV divider. ++ works well. +

works. - problems or limitations. – cannot be used. Adapted from [8].
Divider Type DC AC SI LI
Series-damped capacitive -- + ++ ++
 31

2.2.7 Universal HV divider

The circuit diagram of an universal voltage visualised in Figure 2.19 (a) can be
formed with the only modification compared to the series-damped capacitive di-
vider, by adding in parallel with each capacitor 𝐶 a high ohmic resistance (range
of 𝑀Ω). This makes it possible to also measure DC voltages including superim-
posed voltage ripples covering a frequency spectrum up to several kHz. In order
to maintain an overview between the two types of resistors included in the net-
work, the resistor responsible for damping oscillations at impulse voltages is des-
ignated by the "d" index and the resistor responsible for measuring DC voltages
by the "DC" index.

Figure 2.19. (a) Equivalent symbolic circuit for universal HV dividers. (b)
RCR HV divider circuit diagram designed by VTT.
Similar to the series-damped capacitive divider, it is necessary that the time con-
stants 𝜏𝑑1 and 𝜏𝑑2 (ns range) of the damped capacitive branches of the low- and
high voltage arm are equal to:
𝑅 𝐶
𝜏𝑑1 = 𝜏𝑑2 → ⁡ 𝑅𝑑1 ∙ 𝐶1 = 𝑅𝑑2 ∙ 𝐶2 ↔ 𝑅𝑑1 = 𝐶2 .⁡ (2.38)
𝑑2 1

The value for the time constants 𝜏𝐷𝐶1 and 𝜏𝐷𝐶2 (ms range) of the DC branches of
the low- and high voltage arm will be higher than the time constants of the
damped capacitive branches due to the higher value of the resistances 𝑅𝐷𝐶1 and
𝑅𝐷𝐶2 in comparison with 𝑅𝑑1 and 𝑅𝑑2 , 𝜏𝐷𝐶1 and 𝜏𝐷𝐶2 can made equal if:
𝑅 𝐶 𝑅
𝜏𝐷𝐶1 = 𝜏𝐷𝐶2 → ⁡ 𝑅𝐷𝐶1 ∙ 𝐶1 = 𝑅𝐷𝐶2 ∙ 𝐶2 ↔ 𝑅𝐷𝐶1 = 𝐶2 = 𝑅𝑑1⁡. (2.39)
𝐷𝐶2 1 𝑑2
 32

Due this matching the scale factor of the DC branches and the series damped
capacitive branches are equal, which make it possible to make an accurate com-
bined waveshape measurement e.g. consisting of a DC voltage with a SI super-
imposed on it. If this is not the case then different SF will be obtained for the RCR
divider depending on the type of waveshape that is measured. The universal HV
divider is the type of HV divider that this thesis is dealing with. The circuit diagram
of the RCR divider designed by VTT consisting of a HV arm with only 1 PCB is
visualised in Figure 2.19 (b) and is slightly more detailed than the equivalent cir-
cuit diagram visualised in Figure 2.19 (a). If 1 PCB is used in the HV arm, for DC
and impulse voltages the nominal voltage level specification is equal to 100 kV
and for AC voltages the nominal voltage level specification is equal to 70 kV.

The total damping resistance 𝑅𝑑,1⁡ of the HV arm visualised in Figure 2.19 (b) con-
sists of an internal fixed value damping resistance 𝑅𝑑,1,𝑖𝑛𝑡⁡ and an adjustable ex-
ternal damping resistance 𝑅𝑑,1,𝑒𝑥𝑡⁡ to tune the step response, in total 𝑅𝑑,1⁡ is equal
to:

𝑅𝑑,1⁡ = 𝑅𝑑,1,𝑖𝑛𝑡⁡ + 𝑅𝑑,1,𝑒𝑥𝑡⁡ . (2.40)

The other hardware passive components elements of the HV arm are the re-
sistance 𝑅𝐷𝐶,1 of the resistive branch and the capacitance 𝐶1 of the resistive-ca-
pacitive branch. The HV arm with which the tests were carried out consists of 2
identical PCBs in series. The PCB, visualised in Figure 2.20 (a), has a modular
design, i.e. it consists of a basic network placed in series 120 times to obtain
enough voltage withstand capability, the design on component level will not be
further discussed in this thesis. The difference between using one PCB or using
multiple PCBs for the HV arm is that the scale factor will increase proportional
with the amount of PCBs in series used for the HV arm.
 33

Figure 2.20. (a) PCB of the HV arm. (b) LV arm of

the universal HV divider.
The LV arm that is visualised in Figure 2.20 (b) is built differently and is enclosed
in a metal casing. A deeper analysis of the LV arm and the measuring cable is
discussed in the next section. The LV arm consists of several components that
are visualised in Figure 2.19 (b). The resistance 𝑅𝐷𝐶,2 of the resistive branch con-
sists of a resistance 𝑅𝐷𝐶,2,𝑓 with a fixed value and an adjustable resistance 𝑅𝐷𝐶,2,𝑣
to obtain a matched scale factor for DC and AC voltages. The SF for impulse
voltages can deviate due to the reason that 𝑅𝑑,1 is adjusted to reach optimal
damping and not to obtain equal SF for all type of waveshapes. The terminating
resistance 𝑅𝑇𝑒𝑟 and the input resistance⁡𝑅𝐷𝑖𝑔 of the digitizer need also to be taken
in account when calculating the total resistance 𝑅𝐷𝐶,2. The resistive-capacitive
branch of the LV arm consist of the damping resistance 𝑅𝑑,2 ⁡and capacitance 𝐶2 .
With an universal divider, as discussed earlier in the introduction, both DC, AC,
SI and LI can be measured as listed in Table 2.4.

Table 2.4. Application universal HV divider. ++ works well, + works,

- problems or limitations, – cannot be used. Adapted from [8].
Divider Type DC AC SI LI
Universal divider ++ ++ ++ ++
 34

2.2.8 Summary of the suitability of the HV dividers

In Table 2.5 and Figure 2.21 a summary has been given of the various applica-
tions of the HV dividers seen in this literature study. These HV dividers needs to
be calibrated with a reference HV dividers, e.g. to determine the different scale
factors in function of the level of the applied type of high voltage of a new devel-
oped RCR divider. The calibration of a HV divider, that is described in the IEC
60060 standard, falls outside the scope of this thesis.

Table 2.5. Summary application of the different HV dividers. ++ works well, +

works, - problems or limitations, – cannot be used. Adapted from [8].

Divider Type DC AC SI LI

Resistive High Ohmic (𝑅~⁡𝑀Ω) ++ + + -

Low Ohmic (𝑅~⁡𝑘Ω) - - - ++

Capacitive -- ++ ++ -

Series-damped capacitive -- + ++ ++

Universal ++ ++ ++ ++

Figure 2.21. Different kinds and most commonly used applications of

the HV divider. Adapted from [6].
 35

2.2.9 Low voltage arm and measuring cable

The measuring cable is mostly a coaxial cable, that is used to transmit the signal
from the low voltage arm to the recording instrument as visualised in Figure 2.1.
It makes the connection between the laboratory and the control room. A coaxial
cable is used due to its large bandwidth (GHz range) and its shielding again EMI.
For DC and AC voltages, the design of the LV arm is not that critical and the
classic electric network theory can be used. If any fast transients like SI or LI have
to be transmitted from the voltage divider to the recording instrument, the LV arm
with the measuring cable may introduce large disturbances to the response. The
use of classic electric network theory is no longer accurate. The transition to the
use of transmission line theory must be made as the transmitted frequency's
wavelength is sufficiently short that the length of the cable becomes a significant
part of the wavelength. [4]
The coax cable can be considered as a TML. The design of the LV arm becomes
critical as was briefly mentioned earlier in the section on the general network
structure of HV dividers. The structure of the LV arm is different from that of the
HV arm and this will become more clear at the end of this section. The charac-
teristic impedance ̅̅̅
𝑍𝑐 of a TML is equal to:
(𝑅+𝑗∙2∙𝜋∙𝑓∙𝐿)
̅̅̅
𝑍𝑐 = ⁡ √(𝐺+𝑗∙2∙𝜋∙𝑓∙𝐶),⁡ (2.41)

where:
𝑅 is the resistance per unit length [Ohm/m],
𝐿 is the inductance per unit length [H/m],
𝐺 is the conductance per unit length [S/m,]
𝐶 is the capacitance per unit length [F/m],
j is the imaginary unit,
f is the frequency.
If the signal cable is approximately lossless (𝑅 ≈ 0 and 𝐺 ≈ 0), then the surge
impedance ̅̅̅
𝑍𝐶 = ̅̅̅
𝑍𝑘 becomes independent of frequency:

̅̅̅ ̅̅̅𝑘 = ⁡ √𝐿 ⁡.
𝑍𝐶 = 𝑍 (2.42)
𝐶
 36

A typical value for the characteristic impedance of a signal cable for measuring
voltages is 50⁡Ω. The travel time from the sender side to the receiver side for a
lossless TML with length D is equal to:
𝜏 = 𝐷 ∙ √𝐿 ∙ 𝐶. (2.43)
The aim is that the voltage wave presented at the beginning of the measuring
cable is transmitted undistorted to the measurement instrument. The way in which
this is achieved will be discussed for each type of HV divider.
Resistive HV divider
Reflection of the signal, that has to be measured, at the receiver side is undesir-
able and causes an incorrect measurement. Reflections at the receiver side can
be avoided if the reflection coefficient ̅̅̅𝑅̅⁡⁡of the TML is equal to zero:
̅̅̅̅ ̅̅̅
(𝑍 −𝑍 )
𝑅 = (𝑍̅̅̅̅𝑅+𝑍̅̅̅𝑐) = 0,
̅̅̅̅ (2.44)
𝑅 𝑐

where:
̅̅̅
𝑍𝑅 = 𝑅 is the impedance at the receiving end.
The signal cable is in this case terminated. So the cable matching for a resistive
HV divider is done by a putting a pure ohmic resistance 𝑅 = ⁡ ̅̅̅
𝑍𝑐 in parallel with
the LV arm at the end of the signal cable, as visualised in Figure 2.22 (a).

Figure 2.22. Circuits for signal cable matching. (a) Resistive divider, (b) capaci-
tive divider, simple matching, (c) capacitive divider, compensated matching, (d)
series-damped capacitor divider, simple matching. Adapted from [4].
 37

Capacitive HV divider

There are two possible methods to terminate the measuring cable of a capacitive
HV divider, simple matching and compensated matching. The compensated
matching is an improvement of the simple matching. Only the simple matching
will be discussed. The cable cannot be matched at the end as with the resistive
HV divider. A low ohmic resistor 𝑅 (≈ 50⁡Ohm)⁡in parallel with 𝐶2 would load the
LV arm of the divider too heavily and would decrease the output voltage with time,
this can be proved by simulations, but this falls outside the scope of this thesis.
To avoid travelling wave oscillations, the cable must be terminated at its input
end ̅̅̅̅̅̅̅̅̅̅̅
𝑍𝑆(𝑒𝑛𝑑𝑒𝑟) = ⁡ ̅̅̅
𝑍𝑐 = ̅̅̅
𝑍𝑘 as visualised in Figure 2.22 (b). The voltage 𝑉2 ⁡across 𝐶2
will be halved by 𝑅 = ⁡ ̅̅̅
𝑍𝑐 ⁡as 𝑅 and the surge impedance ̅̅̅
𝑍𝑐 of the TML form a
voltage divider consisting of two equal series-impedances, with the impedance of
the CRO:
̅̅̅̅̅̅
|𝑍 ̅̅̅
𝐶𝑅𝑂 | ≫ 𝑍𝑐 ⁡.

The transient voltages of this TML are discussed on the basis of Figure 2.23 (a),

where:

𝑣𝑠(𝑒𝑛𝑑𝑒𝑟) (𝑡) is the voltage across the capacitor 𝐶2 and can be for example a step
voltage 𝑠(𝑡) = 𝑢(𝑡),

D is the length of the measuring cable with distance 𝑧 = 0 at the input end and
𝑧 = 𝑧𝑗 at the output end,

𝑐 is the speed of propagation of the wave.

𝑣𝑠⁡
This halved voltage 𝑣(𝑧, 𝑡) = for 𝑡⁡𝜖⁡[0; 𝐷/𝑐] by 𝑅 as visualised in Figure 2.23
2
̅̅̅
(b) travels to the open end (𝑍 𝑅 = ⁡∞). The Thevenin equivalent voltage 𝑉𝑇ℎ (𝑡, 𝑧),

visualised in Figure 2.23 (c) and (d), of any linear system is simply it’s open circuit
voltage. The open-circuit voltage of a transmission line is twice the amplitude of
 38

𝑅̅ for an open

any incident voltage waveform because the reflection coefficient ̅̅̅
circuit is +1, which doubles the incident voltage at the position 𝑧𝑗 :

̅̅̅̅ ̅̅̅
(𝑍 −𝑍 ) ̅̅̅
(∞−𝑍 )
𝑅 = (𝑍̅̅̅̅𝑅 +𝑍̅̅̅𝑐) = ⁡ (∞+𝑍̅̅̅𝑐) = 1,
̅̅̅̅ (2.45)
𝑅 𝑐 𝑐

𝑉𝑇ℎ (𝑡, 𝑧𝑗 ) = 𝑣+ (𝑡, 𝑧𝑗 ) + 𝑣− (𝑡, 𝑧𝑗 ) = 𝑣+ (𝑡, 𝑧𝑗 ) + ̅̅̅𝑅̅ ∙ ⁡ 𝑣+ (𝑡, 𝑧𝑗 ) =

𝑣+ (𝑡, 𝑧𝑗 ) + 1 ∙ 𝑣+ (𝑡, 𝑧𝑗 ) = 2 ∙ 𝑣+ (𝑡, 𝑧𝑗 ) = 𝑣𝑠⁡ . [11] (2.46)

Thus the original amplitude of the voltage 𝑣𝑠⁡ across 𝐶2 appears at the input of the
recording instrument. The reflected wave at the receiver end 𝑣(𝑧, 𝑡) = ⁡ 𝑣𝑠⁡ for
𝐷
𝑡⁡𝜖⁡ [ 𝑐 ; 2. 𝐷/𝑐]⁡charges the cable to its final voltage amplitude and is absorbed as

the capacitor 𝐶2 , which is fully discharged (𝑣𝑠⁡ = 0), forms a short circuit. The
reflection coefficient at the sender equals zero:
̅̅̅̅ ̅̅̅
(𝑍 −𝑍 )
𝑆 = (𝑍̅̅̅̅𝑆 +𝑍̅̅̅𝑐) = 0,
̅̅̅ (2.47)
𝑆 𝑐

if:
̅̅̅
𝑍𝑆 = ⁡ ̅̅̅
𝑍𝑐 = 𝑅.

Figure 2.23. Transient voltages on an open-circuit terminated TML.

Adapted from [11].
The universal HV divider designed by VTT is simple matched, simple matching
is used for capacitive, series-damped capacitive and universal HV dividers. The
theoretical explanation of compensated matching that is visualised in Figure 2.22
(c) falls outside the scope of this thesis. For damped capacitive HV dividers the
cable matching can be executed as shown in Figure 2.22 (d). As 𝑅2 is very small
 39

in comparison to 𝑅1 ,⁡this value of the matching resistor 𝑅 must only be reduced

by the small value of 𝑅2 :

𝑅 = ̅̅̅
𝑍𝑐 − 𝑅2 ,

such that:

̅̅̅
𝑍𝑠 = ̅̅̅
𝑍𝑐 .

The matching resistors that are used in HV dividers are an integral part of the LV
arm also the input impedance of the recording instrument (typically 1⁡MΩ) must
be included in the value for the total resistance of the LV arm. The structure i.e.
the composition of the circuit elements of the LV arm is different from that of the
HV arm. The LV arm is often enclosed in a metal housing to avoid the impact of
electromagnetic fields, as visualised in Figure 2.24.

Figure 2.24. Sketched cross-section of a possible layout for the LV arm of an

impulse HV divider [4].
The hardware passive components of the LV arm are preferably equally distrib-
uted in a symmetric concentric way to achieve an evenly current distribution, the
fluxes of the branches will cancels each other out. In this way, the inductivity of
the low voltage part can theoretically be minimised, which is beneficial for the
dynamic behaviour of the HV divider. A too low inductance may easily be in-
creased by the addition of small wire loops in series with the elements [6].
 40

2.2.10 High voltage lead

The high voltage lead makes the connection between the test object and the HV
divider and may consist of a damping resistor (Figure 2.1). This damping resistor
serves 2 purposes, prevention of HF travelling wave phenomena on the lead con-
sequent to reflections and damping of the oscillations that arise in the HV circuit
due to the inductances and capacitances. An optimised value for reflection-free
termination of the lead, by a damping resistor R to equal the reflection coefficient
to zero, can be estimated from the surge impedance of the idealised HV lead. For
an infinitely long horizontal lead of diameter d at a height h above an earthed
surface, the surge impedance is equal to:
𝐿 1 µ 4∙ℎ 4∙ℎ
𝑍 = ⁡ √𝐶 = ⁡ 2∙𝜋 ∙ √𝜀0 ∙ ln ( 𝑑 ) ≈ 60 ∙ ln ( 𝑑 ) , (2.48)
0

whereby:

𝐿 is the inductance of the lead per unit length,

C is the capacitance of the lead per unit length. [5]

A horizontal HV lead cable has an inductance equal to:

𝜇 ∙𝑙 4∙ℎ
0
𝐿ℎ = ⁡ 2∙𝜋 ∙ ln ( 𝑑 ), (2.49)

where:

𝑙 = length of the lead,

𝑑 = diameter of the lead,

ℎ = height above the ground,

µ0 = vacuum permeability. [5]

The HV lead consists of stray capacitances to the ground and stray capacitances
𝐶ℎ ′ to the HV divider itself, as visualised in Figure 2.25. Also, the top electrode
consists of stray capacitances to the HV divider.
 41

Figure 2.25. Stray capacitances of a capacitive HV divider.

Adapted from [4].

2.3 Partial discharges

2.3.1 Origin of partial discharges

Partial discharges (PD) are electrical discharges that affects only a part of the
insulation distance and do not immediately lead to breakdown of the test object,
they take place in all types of insulation [12]. PD are often caused by imperfec-
tions in dielectric materials, such as gaseous inclusions in liquid and solid dielec-
trics (place for internal PD) which is a local reduction of the electrical strength. It
is also caused by sharp edges in gaseous media which are remote from liquid or
solid insulation (place for corona PD) which result in a local field enhancement,
so that the intrinsic field strength may be exceeded. The last main type of PD is
surface PD that appears at the surface of insulation due to contamination in case
of poor maintenance of the insulator surface or due to moisture in case of high
humidity. [6]

This electrical PD phenomenon is of particular importance in HV engineering

where non-uniform electrical fields are unavoidable. It is responsible for consid-
erable power losses from HV transmission lines. It often leads to deterioration of
insulation by the combined action of the discharge ions bombarding the surface
and the action of chemical compounds that are formed by the discharge. It causes
electromagnetic interference which affects and disturbs the accuracy of HV
measurements. [4] Ideally, one should aim to have a HV device PD free up to its
 42

nominal voltage level. Three common methods are used to evaluate the PD be-
haviour of the RCR divider: tan⁡(𝛿) measurement, electrical PD measurement
and acoustic detection method. Each of these methods will be discussed. Clearly,
the higher the voltage imposed on the test object, the stronger the electric field is
and the greater the chance that PD will occur. For this reason, the parameters
(loss factor 𝛿, apparent charge q) are plotted as a function of the imposed voltage
to visualise the PD behaviour of the test object.

2.3.2 Loss factor tan(δ) measurement method

The energy released by internal PD will increase the loss factor tan⁡(𝛿) of the test
object. The loss factor is a parameter of an insulation system that will increase in
case PD activity occurs within the insulation. The loss factor makes it possible to
analyse the PD behaviour of the test object as a function of the imposed voltage
𝑉𝐴𝐵 . In Figure 2.26 is the theoretical equivalent diagram visualised of the test ob-
ject considered as a lossy capacitance with values 𝑅 and 𝐶,
with:
𝑉𝐴𝐵 is the applied test voltage between nodes A and B,
𝑉𝐴′𝐵 is a partial voltage,
C is the ideal capacitance,
R is the ideal resistance,
𝐼𝑐 is the current through capacitance 𝐶,
𝐼𝑅 is the current through the resistance R.
The loss factor tan⁡(𝛿) is equal to:
𝐼𝑅 𝐼
tan(𝛿) = = 𝐼 𝑅𝑒𝑎𝑙 . (2.50)
𝐼𝑐 𝐼𝑚𝑎𝑔

Figure 2.26. Parallel equivalent diagram of a lossy capacitance with vector

diagram. Adapted from [13].
 43

2.3.3 Electrical PD pulse measurement method

Electrical measurement of impulsive (short duration) PD is a frequently used and

successful method to detect partial discharges. The IEC 60270 is devoted to this
measurement method. Some basic knowledge of these PD measurements is
needed to understand this paragraph. During a partial breakdown for example in
a cavity (Figure 2.27 (a)) changes in the field occur that are associated with a
charge transfer (discharge). [12] In a simplified capacitive equivalent circuit (Fig-
ure 2.27 (b)) an individual partial discharge impulse can be described as the dis-
charge of a cavity capacitance 𝐶𝐶𝑎𝑣 . The recharging is carried out for AC voltages
by the capacitive current that flows via the partial capacitance 𝐶𝑆 , that is assumed
in series with 𝐶𝐶𝑎𝑣 .[12]

The capacitance⁡𝐶0 approximately corresponds to the total capacitance 𝐶𝑇 of the

test object, furthermore 𝐶𝐶𝑎𝑣 ≫ 𝐶𝑆 ⁡. With no ignition of partial discharges, the cav-
ity voltage 𝑣𝐶𝑎𝑣 (𝑡) follows the external voltage 𝑣(𝑡) according to the capacitive
divider ratio of 𝐶𝑆 and 𝐶𝐶𝑎𝑣 with no phase shifts, as visualised in Figure 2.27 (c).
If the cavity voltage 𝑣𝐶𝑎𝑣 (𝑡) exceeds the PD ignition voltage 𝑉𝑃𝐷𝐼 of the gas gap
and if an initial free electron is available, the cavity voltage 𝑣𝐶𝑎𝑣 (𝑡) collapses
down to the value of a PD extinction voltage 𝑉𝑃𝐷𝐸 . The cavity capacitance 𝐶𝐶𝑎𝑣 is
then recharged capacitively via 𝐶𝑆 .[12]

Figure 2.27. (a) Insulating material with cavity. (b) Capacitive equivalent
circuit for an insulating material with cavity. (c) Waveshapes of the
voltages 𝑣(𝑡) and 𝑣𝐶𝑎𝑣 (𝑡). [12]
 44

The real charge turnover ∆𝑄 when exceeding the ignition voltage is equal to:
∆𝑄 = 𝐶𝑐𝑎𝑣 ∙ ∆𝑣𝑐𝑎𝑣 , (2.51)
where:
∆𝑣𝑐𝑎𝑣 is the voltage drop at the cavity 𝐶𝑐𝑎𝑣 .

The real internal charge turnover ∆𝑄 cannot be measured at the terminals of the
test object, so another parameter must be found to quantify the PD of the test
object. However, owing to the voltage division at 𝐶𝑆 and 𝐶0 and if you consider
𝐶𝑐𝑎𝑣 to be the voltage source of the voltage drop ∆𝑣𝑐𝑎𝑣 , ∆𝑄 only causes a negligi-
ble small voltage dip ∆𝑣 at the terminals of the entire test object:
𝐶𝑆 𝐶
∆𝑣 = ⁡ ∆𝑣𝑐𝑎𝑣 ∙ 𝐶 = ∆𝑣𝑐𝑎𝑣 ∙ 𝐶𝑆 , (2.52)
𝑆 +𝐶0 𝑇

with:
𝐶0 ∙𝐶𝑐𝑎𝑣
𝐶𝑇 = ⁡ 𝐶𝑆 + 𝐶 = ⁡𝑡ℎ𝑒⁡𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑦⁡𝑜𝑓⁡𝑡ℎ𝑒⁡𝑒𝑛𝑡𝑖𝑟𝑒⁡𝑡𝑒𝑠𝑡⁡𝑜𝑏𝑗𝑒𝑐𝑡, (2.53)
0 ⁡+𝐶𝑐𝑎𝑣 ⁡

in case 𝐶0 ≪ 𝐶𝑐𝑎𝑣 then:

𝐶0 ∙𝐶𝑐𝑎𝑣
𝐶𝑇 = ⁡ 𝐶𝑆 + = ⁡ 𝐶𝑆 + 𝐶0 . [12] (2.54)
𝐶𝑐𝑎𝑣 ⁡

This voltage dip ∆𝑣 is too small to measure directly. Instead of this the measure-
ment circuit visualised in Figure 2.28 is used. The charge q that flows out from
the coupling capacitor with capacitance 𝐶𝑘 and recharges the test object with ca-
pacitance 𝐶𝑎 ⁡ is measured. For this purpose, the coupling device CD is regarded
as the current i(t) measurement resistance 𝑅 and the signal is integrated in the
partial discharge measuring instrument MI as a voltage signal v(t) in order to cal-
culate the charge 𝑞 that is flowed through CD during the time period⁡𝑡1 → 𝑡2:
𝑡 1 𝑡
𝑞 = ∫𝑡 2⁡ 𝑖(𝑡) ∙ 𝑑𝑡 = 𝑅 ∙ ∫𝑡 2 𝑣(𝑡) ∙ 𝑑𝑡. (2.55)
1 1

This charge which can be measured, is described as the ”apparent charge q”

usually expressed in pC:
𝐶 ∆𝑄 𝐶𝑆
𝑞 = 𝐶𝑇 ∙ ∆𝑣 = 𝐶𝑇 ∙ ∆𝑣𝑐𝑎𝑣 ∙ 𝐶𝑆 = ∆𝑣𝑐𝑎𝑣 ∙ 𝐶𝑆 = 𝐶 ∙ 𝐶𝑆 = ∆𝑄 ∙ 𝐶 . [12] (2.56)
𝑇 𝑐𝑎𝑣 𝑐𝑎𝑣

For which is assumed that the voltage dip ∆𝑣 can be fully compensated by the
coupling capacitor 𝐶𝑘 . CC is the connecting cable between the coupling device
CD and the measuring instrument MI and Z is a necessary low-pass filter to
 45

decouple the entire partial discharge circuit from the supply side when PD occurs
or the high voltage supply needs to have negligible amount of background noise.
𝑉~ is the high voltage supply. [12]

Figure 2.28. Electrical PD pulse measurement setup [14].

The apparent charge 𝑞 is much smaller than the real charge turnover ∆𝑄 (due to
𝐶𝐶𝑎𝑣 ≫ 𝐶𝑆 ). Unfortunately, the relationship according to equation (2.56) is com-
pletely unknown, since the type, position and size of the defect are not known,
𝐶𝑆
thus there is no information about the ”transmission ratio ”. Despite this, the
𝐶𝑐𝑎𝑣

apparent charge 𝑞 has proven in practice its value as a valuable parameter for
the quantification of the partial discharge intensity. This is also comprehensible
since the apparent charge is related to the energy dissipation within the defect
(𝑊𝑃𝐷⁡⁡ ~⁡𝑞) and to the size of the internal cavities (𝑑𝑐𝑎𝑣⁡ ~⁡𝑞). The higher the value
for the apparent charge q, the higher the PD intensity of the test object. The latter
two relationships are assumed without mentioning their derivation in detail. [12]

The apparent charge q is thus an excellent parameter to analyse the PD

behaviour of test objects in function of the imposed voltage level. Also 𝑉𝑃𝐷𝐼 ⁡is a
parameter to quantify the PD behaviour of the test object. The main problem with
PD is to locate them due to the multitude of probable sources of PD and thus the
possible superimposition of PD from different defect sources. In the literature,
characteristic partial discharge patterns for different types of PD have been rec-
orded, in order to identify which type of PD is taking place by means of the oscil-
loscope, thus facilitating the localisation of the PD. This is not included in the
measurements, but acoustic detection method was used to localise the PD. Other
existing parameters, e.g. pulse repetition rate, related to this type of measure-
ment were not used and will therefore not be discussed.
 46

2.3.4 Acoustic detection method

PD events not only radiate electromagnetic waves but emit also acoustic pres-
sure waves, where the acoustic signal covers a frequency range between some
kHz and several hundreds of kHz. The main benefit of the detection of acoustic
emitted (AE) waves is their immunity against electromagnetic interferences. To
prevent an impact of other mechanical vibrations caused by pumps and fans as
well as acoustic noises emanated from iron core of transformers, commonly the
ultrasonic frequency range, preferably between 40kHz and 100kHz, is chosen to
capture and acquire AE signals. [6]

The ultrasonic PD detection that is visualised in Figure 2.29 has been used in the
laboratory of TAU to localise the place where PD events occur and to recognize
whether the measured PD is external or internal. This method can only be used
to detect external PD which is less harmful for the components than internal PD.
The only major problem is that if PDs occur inside the tube of the HV divider, the
AE signals can’t be heard due to the fact that there are no openings in the as-
sembly.

Figure 2.29. Equipment of the Ultrasonic detector SDT 170.

 47

3. HV DIVIDER SIMULATIONS
3.1 Objectives and introduction
Simulations are an approximation of reality, but can provide insight for optimali-
zation of the design and analysis of the circuit being simulated. In the previous
section, the areas of application were explained for each type of HV divider by
means of theoretical explanations and formulas and listed in Table 2.5. The in-
tention is to check these also by means of simulations applied to the simplified
circuit diagrams. So the standard network theory is used and not the transmission
line theory, which already shows that the simulation is not completely correct for
impulse voltages.

The simulations are only carried out for the HV dividers and not for the complete
measurement system. For the characterisation of the complete measurement
system, other more time consuming simulation methods are recommended to
increase the accuracy. An example is a finite element method to perfectly take
into account the influence of the electric field on the behaviour as well. As de-
scribed earlier, amplitude-frequency response will be used to characterise the
behaviour of HV divider for DC and AC voltages. The step response will be used
to describe the behaviour of the HV divider in impulse voltage applications.

The aim of this thesis is not to design HV dividers from scratch, but to analyse
existing typical realistic compositions for the different HV dividers. For the univer-
sal HV divider simulations are the real values of the RCR divider passive ele-
ments designed by VTT of course used. The components values of the simulated
series-capacitive HV divider and simulated capacitive HV divider are derived from
the RCR divider, just without the resistive branch and whether or not without
damping resistors. For the resistive HV dividers the values for the total resistance
𝑅 corresponds to the kΩ range respectively to the MΩ range. The values of the
elements of the HV divider will always be clearly visualised. For the simulations,
we consider the HV divider to be a lean, vertical cylinder with a height of 1000
mm and a diameter of 100 mm with the bottom-end at ground potential. Consider
that the parasitic capacitance of the hardware passive elements is neglectable in
comparison with the total stray capacitance 𝐶𝑒 . The HV lead is not considered in
 48

the simulations, thus also no parasitic capacitance from the HV lead to the HV
divider is considered. The total stray capacitance 𝐶𝑒 is equal to:
2∙𝜋∙𝜀0 ∙𝑙
𝐶𝑒 = 𝑛 ∙ 𝐶 ′ 𝑒 = 2 𝑙 , (3.1)
ln( ∙ )
√3 𝑑

2∙𝜋∙8.85∙10−12 ∙1
𝐶𝑒 = 2 1 = 22.72⁡𝑝𝐹. (3.2)
ln( ∙ )
√3 0,1

The geometry of the HV arm consists of a helix structure with a total of 30 wind-
ings N = 30. The helix structure avoids pointed turns, which could otherwise eas-
ily lead to partial discharges, but comes along with a non-negligible inductance
𝐿. From this we can determine the total inductance 𝐿 of the HV divider helix de-
sign, the HV divider is filled with air µ𝑟 = 1:

𝑑 2
𝑁 2 ∙µ𝑟 ∙µ0 ∙𝐴 𝑁 2 ∙µ𝑟 ∙µ0 ∙(𝜋∙( ) )
2
𝐿1 = = , (3.3)
𝑙 𝑙

2
100∙10−3
302 ∙1∙4∙𝜋∙10−7 ∙𝜋∙( )
2
𝐿1 ⁡ = = 8.88⁡𝜇𝐻. (3.4)
1

The parasitic inductance of the capacitors (nH range) themselves is neglected

compared to the inductance of the helix structure (μH range). The total inductance
of the LV arm is assumed to be in the nH range, a value of 𝐿2 = ⁡8.88⁡nH⁡is con-
sidered to make it possible to match the time constants of HV arm (index “1”) and
LV arm (index “2”) as good as possible:
𝐿1 𝐶 𝑅
= ⁡𝐶2 = ⁡𝑅1 = 𝑐𝑡𝑒. (3.5)
⁡𝐿2 1 2

As mentioned earlier, we will not discuss the design on single component level in
this section and thus the voltage specification is not dealt with in these simula-
tions.

3.2 Simulated HV divider networks

3.2.1 Resistive HV divider

The equivalent circuit shown in Figure 2.13 will be used for the simulation of both
types of resistive HV dividers. As demonstrated mathematically earlier, the total
inductance 𝐿 = 𝐿1 + 𝐿2 ⁡may be neglected. In Figure 3.1 the simulated circuit
 49

diagrams of the high ohmic HV divider (𝑅~𝑀Ω) are shown and in Figure 3.2 the
simulated circuit diagrams of the low ohmic HV divider (𝑅~𝑘Ω) are shown.

Figure 3.1. Simulated circuit diagram of a high ohmic HV divider

(a) amplitude-frequency response, (b) unit step response.

Figure 3.2. Simulated circuit diagram of a low ohmic HV divider

(a) amplitude-frequency response, (b) unit step response.

3.2.2 Capacitive HV divider

The equivalent circuit shown in Figure 2.15 (b) can be used for the simulation of
the capacitive divider for DC and AC voltages, the total inductance 𝐿 cannot be
neglected anymore for SI and LI voltages. The total inductance forms together
with the total capacitance 𝐶 a series-resonant circuit, that can be simulated by
adding the presumed equally distributed inductance 𝐿 to Figure 2.15 (b) so that
 50

the circuit diagram not only can be used for AC and DC voltages simulations. The
resonance frequency 𝑓𝑟𝑒𝑠 is equal to:
1 1
𝑓𝑟𝑒𝑠 = 2∙𝜋∙√𝐿∙𝐶 = = 1.86⁡MHz, (3.6)
2∙𝜋∙√8.89∙10−6 ∙820∙10−12

with:

𝐶 ′ ∙𝐶 821.21∙10−12 ∙825∙10−9
𝐶 = ⁡ 𝐶 ′ +𝐶2 = ⁡ 821.21∙10−12 ⁡+⁡825∙10−9 = 820⁡𝑝𝐹, (3.7)
2

𝐿 = ⁡ 𝐿1 + 𝐿2 = 8.88.10−6 + 8.88.10−9 = 8.89⁡𝜇𝐻. (3.8)

The influence of the stray capacitance 𝐶𝑒 to the ground on the dynamic behaviour
of the capacitive is negligible small (𝐶 ′ ≈ 𝐶1 ) and will no longer be taken into ac-
count when making adjustments to the capacitive divider (series-damped capac-
itive divider and RCR divider) so that the circuits remain simple and fundamental
statements can be made via short insights. In Figure 3.3 the simulated circuit
diagrams of the capacitive HV divider are visualised.

Figure 3.3. Simulated circuit diagram of a capacitive HV divider

(a) amplitude-frequency response, (b) unit step response.

3.2.3 Series-damped capacitive HV divider

The series-damped capacitive HV divider is formed by adding damping resistors
𝑅𝑑,1 and 𝑅𝑑,2 to the circuit diagram of the capacitive HV divider. In Figure 3.4 the
simulated circuit diagrams of the series-damped capacitive HV divider are
visualised.
 51

Figure 3.4. Simulated circuit diagram of a series-damped capacitive

HV divider (a) amplitude-frequency response, (b) unit step response.

3.2.4 Universal HV divider

The universal divider can be obtained by adding 2 resistive branches with values
𝑅𝐷𝐶,1 and 𝑅𝐷𝐶,2 to the circuit diagram of the series-damped capacitive HV divider.
The simulated universal divider corresponds to the RCR divider with a HV arm
consisting of one PCB designed by VTT. The simulated networks of the universal
HV divider are visualised in Figure 3.5.

Figure 3.5. Simulated circuit diagram of an universal HV divider

(a) amplitude-frequency response, (b) unit step response.
 52

3.3 Amplitude-frequency response simulation results

In Figure 3.6 the amplitude-frequency response 𝐺(𝑓) of the different HV divider
circuit diagrams are plotted. The aim is to evaluate these curves according to the
IEC 60060 standards. The frequency 𝑓1 is the lower frequency limit where the
value of G(f) = 0.85 intersects the rising G(f) of the respective HV divider and 𝑓2
is the upper frequency limit where the value of G(f) intersects the declining G(f)
of the respective HV divider. The range between 𝑓1 ⁡and 𝑓2 is considered as the
bandwidth of the HV divider, listed in Table 3.1.

Table 3.1. Summary of the amplitude-frequency parameter values of

the simulated networks.

Symbols High Ohmic Low Ohmic Capacitive Series- Universal

HV divider damped HV divider
resistive HV resistive HV
capacitive
divider (𝑹~𝑴Ω)
divider HV divider
(𝑹~𝒌Ω)

𝑓1 0⁡𝐻𝑧 0⁡𝐻𝑧 3⁡𝐻𝑧 3⁡𝐻𝑧 0⁡𝐻𝑧

𝑓2 260⁡𝐻𝑧 1.7⁡𝑀𝐻𝑧 > 100⁡𝑀𝐻𝑧 > ⁡100⁡𝑀𝐻𝑧 > 100⁡𝑀𝐻𝑧

Resistive HV dividers and the universal HV dividers are well suited for DC (f=0
Hz) measurements while the capacitive HV divider and series-damped capacitive
HV divider can’t be used for DC measurements based on the lower frequency
limit 𝑓1 which is greater than 0⁡𝐻𝑧. This conclusion corresponds to what was
demonstrated in the theoretical study. AC is evaluated for frequencies greater
than 𝑓 = 0⁡𝐻𝑧. A resistive HV divider functions as a low pass filter and their upper
1
frequency limit 𝑓2 is inverse proportional with 𝑅 ∙ 𝐶𝐸 (𝑓2 ~ 𝑅∙𝐶 ), this explains the
𝐸

difference of the 𝑓2 value of both types of resistive HV dividers, which had already
been theoretically demonstrated. The bandwidth of the resistive HV dividers can
be increased by suppressing the stray capacitances with shielding of the HV di-
vider. The capacitive and series-capacitive HV dividers are high pass filters, their
upper frequency limit 𝑓2 is greater than 100⁡𝑀𝐻𝑧. The universal HV divider has a
bandwidth spread over all values of frequencies listed on the x axis.

For the capacitive HV divider a transition phenomenon around the resonance

frequency 𝑓𝑟𝑒𝑠 = 1.86⁡𝑀𝐻𝑧 is visible, which causes oscillations and can be eval-
uated via the unit step response. The number of samples in the amplitude-
 53

frequency response is also too low to identify this correctly via Figure 3.6. In the
amplitude-frequency response of the capacitive HV divider is this not visible due
to the damping of the oscillations.

Figure 3.6. Amplitude-frequency response of the simulated

HV divider networks.
 54

Influence of unequal time constants

In the theoretical discussion of universal HV dividers, it was explained how a con-

stant scale factor SF can be obtained over the full bandwidth of the HV divider.
This rule is also applied to the universal HV divider designed by VTT no matter
how much PCBs in series are used for the HV arm. The SF may vary over the
bandwidth of the HV divider as the damping resistor value of the HV arm is ad-
justed to obtain critical damping and not to obtain equal SF over the entire band-
width, what is important to take into account in the design.
If the time constants are not equal, different SF are obtained depending on the
frequency. To demonstrate this, the circuit diagrams of the RCR divider with dif-
ferent time constants are also simulated and the results are shown in Figure 3.7.
The different scale factors are equal to:
𝑅 600⁡𝑀Ω
𝑆𝐹𝐷𝐶 = 𝑅𝐷𝐶1 = = 1000 and respectively 𝐺(𝑓) ⁡⁡ = ⁡1,
𝐷𝐶2 600⁡𝑘Ω

𝐶 825⁡𝑛𝐹
𝑆𝐹𝐶𝑎𝑝 = 𝐶2 = 1650⁡𝑝𝐹 = ⁡500 and respectively 𝐺(𝑓) ⁡⁡ = ⁡2,
1

𝑅 250⁡Ω
𝑆𝐹𝐷𝑎𝑚𝑝 = 𝑅𝑑1 = 250⁡𝑚Ω = 1000 and respectively 𝐺(𝑓) ⁡⁡ = ⁡1.
𝑑2

In the range between 0⁡𝐻𝑧 and 10⁡𝑚𝐻𝑧 is the DC scale factor (𝑆𝐹𝐷𝐶 )⁡dominant
because the voltage drop takes place almost entirely over the DC resistors. Then
there is a transition of the SF to the capacitive SF (𝑆𝐹𝐶𝑎𝑝 ) and remains constant
in the range between 1⁡𝐻𝑧 and 100⁡𝑘𝐻𝑧. Finally, the SF changes again with in-
creasing frequency to the damping SF (𝑆𝐹𝐷𝑎𝑚𝑝 ) and remains stable in the range
between 1⁡𝑀𝐻𝑧 and 100⁡𝑀𝐻𝑧. In practice a constant value over the entire fre-
quency range of the RCR HV divider is desired.
 55

Figure 3.7. Amplitude-frequency response of a RCR HV divider

with different scale factors.

3.4 Step response simulation results

The unit step response (USR) of each type of HV divider that is visualised in
Figure 3.8 is used to evaluate the behaviour of the HV dividers for impulse volt-
ages (LI and SI). The goal is to determine if the HV divider is suitable for the
measurement of LI and/or SI. The most simple way to prove this is to follow the
rule of thumb, the measurement device in this case the HV divider should have a
faster rise time 𝑡𝑟 at least by a factor of 5 than the fastest component of the signal
to be measured [15]. When this rule is applied for a standard LI (𝑇1 = 1.2⁡µ𝑠) then
1.2
if 𝑡𝑟 < ⁡µ𝑠 = 0.24⁡µ𝑠 = 240⁡𝑛𝑠 it can be concluded that the device is fast enough
5

to measure this LI. The rise time 𝑡𝑟 is the time required for a pulse to rise from
10 % to 90 % of its steady state value, in our case the steady state value is equal
to 1.

The time when the USR g(t) of the HV divider reaches a value of 𝑔(𝑡) ⁡ = ⁡0.1 is
named 𝑡1 . The time when the USR of the HV divider reaches a value of 𝑔(𝑡) ⁡ =
⁡0.9 is named 𝑡2 . The time parameters 𝑡1 and 𝑡2 are used to calculate the
 56

rise time (𝑡𝑟 = 𝑡2 − 𝑡1 ). In Table 3.2 the rise time for the different HV dividers is
calculated based on Figure 3.8, where the USR for the different HV dividers is
visualised.

Table 3.2. Summary of the unit step response parameter values of

the simulated HV divider networks.

Symbols High Ohmic Low Ohmic Capacitive Series- Universal

resistive HV resistive HV HV divider damped HV divider
divider divider capacitive
(𝑹~𝑴Ω) (𝑹~𝒌Ω) HV divider

𝑡𝑟 = 𝑡2 − 𝑡1 834⁡µ𝑠 125⁡𝑛𝑠 87⁡𝑛𝑠 58⁡𝑛𝑠 58⁡𝑛𝑠

𝑇1 No Yes Yes Yes Yes

𝑡𝑟 <
5
= 240⁡𝑛𝑠?

Only the high ohmic resistive HV divider has a rise time 𝑡𝑟 slower than 240⁡𝑛𝑠 and
is thus based on this criterium not suited for the measurement of LI voltages. This
method is not complete enough to make a final judgment, but it eliminates the
high ohmic resistive HV divider already. Also for SI, impulses with a front time 𝑇1
larger than 20 µ𝑠 is the high ohmic HV divider too slow.

A more accurate way of analysing if a HV divider is suited to measure LI or SI, is

to study the deformation of the standard impulse by convolving it with the unit
step response of the HV divider and look how the time parameters 𝑇1 and 𝑇2
change in the process. The software used is only capable of running convolution
with lightning impulses as input and not with switching pulses as input, which
means that the analysis of the unit step response cannot be done completely due
to the lack of available software. In Table 3.3 the results are listed of the convo-
lution method with a LI (1.2 μs/50 μs) as input, in the second and third column
the values of the time parameters 𝑇1 and 𝑇2 of the LI response of each divider are
listed and in the last two columns the deviation of these time parameters in com-
parison with the reference are listed. The high ohmic HV divider was not included
in the table because it was already shown with the previous analysis that this HV
divider is not suitable for the LI measurements. Also applying convolution with LI
as input for the pure capacitive HV divider that oscillates and is not damped is
unusable since it will never reach steady state. It can be concluded that the sim-
ulated capacitive HV divider is therefore only useful for AC measurements. The
series-damped capacitive and universal HV divider have a negative 𝑇1 error
 57

because there is still some overshoot, which means that the impulse will rise too
fast. This shows why it is so important to have an optimally damped HV divider
for impulse voltage measurements. The low ohmic HV divider has a perfect re-
sponse, so no time parameter errors occur.

Table 3.3. Convolution software time parameter results for LI (1.2/50).

HV divider 𝑻𝟏 [μs] 𝑻𝟐 [μs] 𝑻𝟏 error [%] 𝑻𝟐 error [%]

Series-damped 1.115 49.93 -7.1 -0.1

capacitive

Low ohmic 1.200 50 0.0 0.0

Universal 1.115 49.93 -7.1 -0.1

Reference 1.200 50.00 0.0 0.0

 58

Figure 3.8. Unit step response of the simulated HV divider networks.

 59

Influence of the damping resistor value 𝑹𝒅,𝟏

In Figure 3.9 multiple simulated unit step response of the series-damped capac-
itive HV divider with different values for 𝑅𝑑,1 are plotted to visualise the effect of
the value of the damping resistance of the HV arm 𝑅𝑑,1. The function s(t) is the
step that is applied at the input side. In case 𝑅𝑑,1 = 0⁡Ω no damping occurs and
actually a pure capacitive HV divider is obtained with a dynamic behaviour char-
acterised by oscillations. If 𝑅𝑑,1 = 100⁡Ω is applied then underdamping occurs
characterised by an overshoot of 30 % and finally if 𝑅𝑑,1 = 250⁡Ω is applied then
the overshoot is limited to 10 %. The USR is later on in the paragraph about the
measurements also experimental determined. The aim in these simulations was
not to calculate all the parameters for each curve on the graph, but rather to vis-
ualise what the effect is if the value for 𝑅𝑑,1 is changed.

Figure 3.9. Unit step response of a series-damped capacitive divider with dif-
ferent values for the damping resistor 𝑅𝑑,1 .
 60

4. EXPERIMENTAL INVESTIGATIONS

Several experimental investigations were carried out at the HV laboratory of Tam-

pere university. The first main topic is the evaluation of the initial partial discharge
performance of the HV divider by using the loss factor tan(𝛿) measurement
method and the electric PD pulse measurement method. To optimize the initial
PD performance of the HV divider, several adjustments to the design were made
and evaluated with the electric PD pulse measurement method. After succeeding
to get the HV divider PD free up to its nominal AC voltage level, the setting of the
external damping resistor value was executed and discussed.

The third and final part of the main measurements that were carried out in the lab
is the long-term stressing of the HV divider. First, a DC stressing of the PCBs was
performed. Then both an LI impulse voltage stressing and a tail chopped LI im-
pulse voltage stressing up to the nominal voltage level of the HV divider were
performed. These long-term stressing measurements are not explained in detail,
but the conclusion of these measurements is given at the end of the thesis.

4.1 Evaluation of the initial PD performance

4.1.1 Loss factor 𝐭𝐚𝐧⁡(𝜹)

Measurement setup

The energy released by internal partial discharges (PD) will increase the dissipa-
tion factor tan⁡(𝛿) of the test object. The test objects are the PCBs of the HV arm.
The HV arm consists of 2 PCBs. For practical reasons there are a limited amount
of attachment holes, it is only possible to take measurements per section of the
PCB as visualised in Figure 4.1. The two PCBs of the HV arm are labelled as
“PCB 5” and “PCB 6”.
 61

Figure 4.1. PCB as test object and voltage 𝑉𝑡𝑒𝑠𝑡 is applied in this figure over
the entire PCB.
The loss factor will be measured with a measuring bridge Type 2877, the internal
working principle of the measurement device made falls outside the scoop of this
thesis. The theoretical schematic diagram for the tan(δ) measurement with the
measuring bridge Type 2877 that is visualised in Figure 4.2 is included in the
manual of the device and explains how to connect everything,
with:
𝐶𝑥 , 𝑣𝑥 , 𝑣⁡𝑎𝑛𝑑⁡𝐶𝑁 are the terminal numbering of the measuring bridge Type 2877,
𝐶𝑛 is the standard capacitor (𝑡𝑎𝑛⁡(𝛿) ⁡ < ⁡ 1 ∙ 10−5 ),
𝑉𝑡𝑒𝑠𝑡 is the test high voltage supply,
𝑅⁡𝑎𝑛𝑑⁡𝐶 are the resistance and capacitance value of the test object.
 62

Figure 4.2. Schematic diagram of 𝑡𝑎𝑛(𝛿) measurement setup.

Adapted from [13].
In Figure 4.3 is the real setup made in the laboratory visualised with the used
devices and their specifications listed in Table 4.1. The standard capacitor 𝐶𝑛 is
the standard to which the whole measurement refers and with which the test ob-
ject is compared. Therefore the demands placed upon this test standard are high
e.g. tan(𝛿) less than 1 ∙ 10−5 and a good long term stability is required. The quality
of the standard capacitor 𝐶𝑛 is therefore an important integral part for the accu-
racy of the complete test system. The frequency 𝑓 that will be used is the fre-
quency specified on the HV supply rating plate (𝑓 = 50⁡𝐻𝑧).
 63

Figure 4.3. 𝒕𝒂𝒏(𝜹) measurement setup in the laboratory.

Table 4.1. Summary of the devices used in the 𝒕𝒂𝒏(𝜹) measurement

laboratory setup.

Part of the measurement circuit Specifications of the device

Measuring Bridge Type/model: Measuring bridge Type 2877,

Manufacturer: Tettex instruments

Test object Type/model: PCB

Manufacturer: VTT

Standard capacitor 𝐶𝑛 Type/model: MCP 300 Standard Capacitor

Manufacturer: HIGHVOLT Prüftechnik Dresden GmbH
Used capacitance: 101.426 pF
Rated voltage: 300 kV

Test high voltage 𝑉𝑡𝑒𝑠𝑡 supply Type/model: T750-300-760

Manufacturer: HIPOTRONICS
Rated input: 760 V, 329 A
Rated output: 50 kV, 300 kVA
Frequency: 50 Hz
 64

Before carrying out the measurements, an estimation can be made on the basis
of the circuit diagram visualised in Figure 4.4 to find out what the tan⁡(𝛿) value
will be if no PD’s occur:
𝐼𝑅 𝐼
tan(𝛿) = = 𝐼 𝑅𝑒𝑎𝑙 , (4.1)
𝐼𝑐 𝐼𝑚𝑎𝑔

with:
𝑉𝐴′ 𝐵
𝐼𝑅𝑒𝑎𝑙 = , (4.2)
𝑅

𝐼𝐼𝑚𝑎𝑔 = 𝑉𝐴′ 𝐵 ∙ 2.∙ 𝜋 ∙ 𝑓 ∙ 𝐶, (4.3)

then:
𝑉𝐴′ 𝐵 1 1
tan(𝛿) = ∙𝑉 = 2∙𝜋∙𝑓∙𝑅 , (4.4)
𝑅 𝐴′ 𝐵 ∙2∙⁡𝜋∙𝑓∙𝐶 𝐷𝐶,1 ∙𝐶1

1
tan(𝛿) = 2∙𝜋∙50∙600∙106∙825∙10−12 = 0.00643. (4.5)

So the loss factor tan(𝛿) is independent of the HV level 𝑉𝐴𝐵 if no PD occur. This
calculation will always give the same result for every combination of sections in
series that are measured, this can be easily understood on the basis of the rules
of network theory.

Figure 4.4. Circuit diagram of a single PCB as test object.

Results and conclusion

Six series of measurements are performed, each series consists of a different

number of sections over which the test voltage 𝑉𝑡𝑒𝑠𝑡 is applied, e.g. “Section 1,2”
means that 𝑉𝑡𝑒𝑠𝑡 is applied over section 1 and section 2. The reason why the
 65

number of sections is increased by 1 section each time is because if PD occurs,

the section where PD occurs can be found immediately. The first measurement
at the lowest imposed voltage for each setup is taken as the reference, then the
voltage is gradually increased. For each setup several 𝑉𝑡𝑒𝑠𝑡 are applied. In case
that there is a measurement that is not executed, due to the reason to limit the
amount measurements then this is represented by: “/”. The more sections there
are as a test object, the higher the max voltage 𝑉𝑡𝑒𝑠𝑡 that is applied. In case there
are PD’s a sudden increase of the loss factor will occur. In Table 4.2 the meas-
urement results of PCB 5 are listed. For each series there is no increase of the
loss factor in function of the applied test voltage. Also the value of the loss factor
is approximately equal to the calculated value in case no PD occurs, deviation of
this value can be due to the inaccuracy of the measurement device. No significant
rise of the loss factor occurs, PCB 5 is PD free up to 18 kV AC.

Table 4.2. Loss factor 𝑡𝑎𝑛(𝛿) measurement results of PCB 5.

PCB 5
Series Test voltage level 𝑉𝑡𝑒𝑠𝑡
2 kV 3 kV 4 kV 5 kV 6 kV 12 kV 18 kV
1. Section 1 0.00641 0.00641 / / / / /
2. Section 1,2 0.00641 0.00641 0.00643 / 0.00641 / /
3. Section 1,2,3 / 0.00642 0.00642 0.00642 0.00642 / /
4. Section 1,2,3,4 / / 0.00643 0.00642 0.00642 0.00642 /
5. Section 1,2,3,4,5 / / / 0.00639 0.0064 0.0064 /
6. Entire PCB: (1,2,3,4,5,6) / / / / 0.0064 0.0064 0.0064

In Table 4.3 the measurement results of PCB 5 are listed. Again no increase of
the loss factor is notable in function of the test voltage level for each series. In
series 4 there is a drop of the loss factor from 0.00653 at 5 kV to 0.00644 at 6 kV
and remains then stable for higher test voltage levels. The reason for this sudden
decline can be due to the fact that measuring bridge was not stabilized enough
and the measurement was carried out too fast. In general no significant rise of
the loss factor occurs, PCB 6 is PD free up to 18 kV AC.
 66

Table 4.3. Loss factor 𝑡𝑎𝑛(𝛿) measurement results of PCB 6.

PCB 6
Series Test voltage level 𝑉𝑡𝑒𝑠𝑡
2 kV 3 kV 4 kV 5 kV 6 kV 12 kV 18 kV
1. Section 1 0.00635 0.00635 / / / / /
2. Section 1,2 0.00636 0.00636 0.00637 / 0.00636 / /
3. Section 1,2,3 / 0.00637 0.00638 0.00637 0.00637 / /
4. Section 1,2,3,4 / / 0.00654 0.00652 0.00638 0.00648 /
5. Section 1,2,3,4,5 / / / 0.00653 0.00644 0.00644 /
6. Entire PCB: 1,2,3,4,5,6 / / / / 0.00639 0.00639 0.00639

Both PCBs, PCB 5 and PCB 6 are PD free up to 18 kV AC. Further PD measure-
ment test will be executed up to the nominal AC voltage level of the PCBs to
check whether the HV arm is PD free in its operating area. In this method the
PCBs were tested separately, in the following used methods it is recommended
to test the HV divider fully assembled to check if there are no PD problems in the
design of the HV divider.

4.1.2 Electrical PD pulse

Measurement setup

The theoretical measuring setup visualised in Figure 2.28 according to the IEC
60270 standard is used as a manual to build the test circuit for the electric PD
impulse measurements in the laboratory that is shown in Figure 4.5 with the de-
vice names marked on it. The connections to the coupling device are illustrated
more clearly in detail in Figure 4.6. An overview with the specifications of the
devices used is listed in Table 4.4. The aim in this thesis is rather to know the
specifications and understand the use of these devices than knowing in detail the
internal working principles of the devices.
 67

Figure 4.5. Electrical PD pulse measurement setup in the laboratory.

Figure 4.6. Connections to the coupling device CD.

 68

Table 4.4. Summary of the devices used in the electrical PD pulse

measurement setup.

Part of the measurement circuit Specifications of the device

High voltage supply 𝑉~ Model: T7300-300-760

Manufacturer: HIPOTRONICS
Rated input: 760 V, 396 A
Rated output: 300 kV, 300 kVA
Frequency: 50 Hz

Coupling capacitor 𝐶𝑘 Model: PSF300/1/DDX

Manufacturer: HIPOTRONICS

Test object⁡𝐶𝑎 Model: non-commercial Universal HV divider

Manufacturer: VTT MIKES

Coupling device CD Model: RPA1

Manufacturer: Power Diagnostix

Preamplifier Model: CIL5M/V3µ0

Manufacturer: Power Diagnostix

Measuring Instrument MI Model: ICMsystem

Manufacturer: Power Diagnostix

Oscilloscope connected to MI to visualise PD Model: LT264M

pattern
Manufacturer: LeCroy

The overall task of the coupling capacitor 𝐶𝑘 ⁡is when a partial discharge event
occurs, the coupling capacitor provides the test object 𝐶𝑎 ⁡with a charge current
which is measurable at the coupling device CD [16]. The preamplifier can be con-
sidered an integral part of the coupling device and measuring instrument. Pream-
plifiers serve to condition, filter, and amplify the partial discharge signal to be
measured. Because the frequency range in which PD signals are measured is
strongly dependent on the preamplifier used, proper selection of a preamplifier is
an important part of noise mitigation and can have a strong effect on the appear-
ance of the partial discharge pattern itself. The PD measurements are carried out
for the initial design of the HV divider designed by VTT that is visualised in Figure
4.7. [17]
 69

Figure 4.7. Initial design of the HV divider.

Results and conclusion

The results of the PD measurement are shown in Table 4.5. The values for the
apparent charge q are listed for different magnitudes of the applied AC voltage in
kVpeak. Also another PD intensity parameter, the PD inception voltage of the test
object 𝑉𝑃𝐷𝐼 is included. PD pulses are only detectable when the apparent charge
exceeds the background noise level, which should thus be kept as low as possi-
ble to prevent erroneous test results. If PD measurement results are discussed,
it is important to work with orders of magnitude for the apparent charge q. The
conditions under which the measurements were carried out in the laboratory:

calibration is done at 𝑞 = 20⁡𝑝𝐶,

the background noise of the measurement is 𝑞 = 1⁡𝑝𝐶

temperature 𝑇 = 18⁡°𝐶,

relative humidity of 18 %,

air pressure in the laboratory room 𝑝⁡ = ⁡1001⁡𝑚𝑏𝑎𝑟.

The apparent charge q begins to exceed the PD background noise level around
the PD inception voltage of 100 kVpeak with a value in the range of q = 160⁡pC.
From 100 kVpeak onwards, the HV divider is no longer PD free. The PD meas-
urement is only carried out up to a voltage of 120 kVpeak AC with an apparent
 70

charge in the range of 2 nC. It can be concluded that adjustments are needed to
the design in order to get the HV divider PD free up to its nominal voltage level.
This will be discussed in the next paragraph.

Table 4.5. PD measurement results of the HV divider before optimization.

RCR HV divider

Applied AC voltage [kVpeak]

PDI [kVpeak] 100 120 150 170 180 190 200
100 160 pC 2 nC / / / / /

4.2 Optimization of the PD performance

4.2.1 Electrical PD pulse

Measurement setup

The electrical PD pulse measurements are performed in total for 4 different con-
figurations of the HV divider in order to optimize the PD performance of the HV
divider. The evolution of the various configurations is such that one element is
added or removed each time compared to the previous best arrangement, so that
the effect of this modification on the PD performance can be analysed. The aim
is to compare the measurement results for the different configurations and to be
able to explain why the measurement results differ.
The first setup (Figure 4.8 (Left)) is the HV divider with the initial design as in the
previous paragraph. The second setup (Figure 4.8 (Right)) is the same as the
first setup but with one difference, an extra top electrode is added with the aim
that the electric field will be more uniform distributed along the length of the HV
divider. In the third setup (Figure 4.9 (Left)), the LV arm was removed and re-
placed by a short circuit to the ground. In such a way that it can be determined
whether the presence of the LV arm has any effect on the PD behaviour of the
HV divider. In the final setup (Figure 4.9 (Right)), the LV arm was again added,
but in comparison with the second setup extra grading rings were added at the
upper half of the HV arm in order to further improve the uniformity of the electrical
field along the HV-divider.
 71

Figure 4.8. Left, HV divider without external electrodes. Right, HV divider

with an added top electrode.

Figure 4.9. Left, HV divider with short-circuited LV arm. Right, HV divider

with grading rings.
 72

Results and conclusion

Table 4.6 shows the results of the electric pulse measurements for the different
configurations. The setups will be compared step by step.

Setup 1 ↔ Setup 2

The extra top toroid-shaped electrode used in setup 2 is necessary to improve

the PD behaviour of the HV divider. The 𝑉PDI increases with 45 kV and at an
applied AC voltage of 120 kVpeak the apparent charge is changed from the nC
range to the pC range. The reason for this difference was explained earlier in the
theoretical discussion of the influence of a top electrode on the electric field.

Setup 2 ↔ Setup 3

Between these two setups there is no noticeable difference between the results.
The LV arm has no influence on the PD behaviour of the HV divider. This is also
logical since there is a voltage in the range of 100 V over the LV arm at an applied
voltage of 200 kVpeak over the HV divider, which is therefore too low to initiate
notable PD events at the LV arm.

Setup 2 ↔ Setup 4

Extra grading rings on the PD behaviour assembled on the upper half of the HV
divider results in a PD free HV divider, in comparison with setup 2 only the back-
ground noise of 1 pC is noticeable. The reason for this was explained earlier in
the theoretical discussion of the influence of extra grading rings on the electric
field.

Table 4.6. Measurement results electrical PD pulse method

after optimization.

RCR HV divider

SETUP Applied AC voltage [kVpeak]

𝑉PDI [kVpeak] 100 120 150 170 180 190 200
1 100 160 pC 2 nC / / / / /
2 145 1 pC 1 pC 20 pC 60 pC 100 pC 150 pC 300 pC
3 145 1 pC 1 pC 20 pC 60 pC 100 pC 150 pC 280 pC
4 Not applicable 1 pC 1 pC 1 pC 1 pC 1 pC 1 pC 1 pC

After making several rational adjustments to the design, a PD free universal HV

divider up to 200 kVpeak AC with top electrode and grading rings is obtained.
The advantages of being PD free are that: no PD noise occurs, no deterioration
 73

of components due to PD occurs and the HV divider can be further analysed for
use in PD free setups.

4.3 Setting of the external damping resistor value

Introduction and objectives

The unit step response was discussed theoretically earlier, this was necessary in
combination with the amplitude-frequency response to characterise the different
types of HV dividers each with their own operating range. Simulations of the USR
of the RCR divider using the circuit diagram were also performed and provided
insights. This section is about the measurement in practice of the USR. The
measurement of the USR of the RCR divider is used to determine the value of
the external damping resistor that consist of separate ceramic disc resistor ele-
ments in series such that critical damping occurs. In TAU's lab the threshold be-
tween overdamping and underdamping was determined. In VTT’s lab the ideal
configuration of the damping resistor was then searched more precisely. The
USR was not used to apply the convolution theory, because VTT and TAU have
the necessary infrastructure to carry out impulse voltage tests to analyse the be-
haviour of the RCR HV divider for these impulse voltages.

Measurement setup

The measurement setup is made in accordance with the IEC 60060 standard
what was already discussed in the literature study. In Figure 4.10 is an overview
of the entire measurement setup in the laboratory given and in Figure 4.11 is a
more detailed representation of the connections to the step generator given. In
Table 4.7 are the specifications of the used devices listed.
 74

Figure 4.10. Unit step response measurement setup in the laboratory.

Figure 4.11. Close up of the damping resistors and step generator.

 75

Table 4.7. Summary of the devices used in the unit step response
measurement setup.

Part of the measurement circuit Specifications of the device

Step generator Model: non commercial

Manufacturer: VTT MIKES

Test object Model: non-commercial universal HV divider

Manufacturer: VTT MIKES

Oscilloscope Model: HDO4054a

Manufacturer: TELEDYNE LECROY

Results and conclusion

In Figure 4.12 are the three different curves of the measured unit step response
plotted on one graph. The first blue coloured curve visualises the underdamped
USR with overshoot when 2 external ceramic damping resistor elements of 100
Ohm are used in series. The second orange coloured curve displays the
overdamped USR when 3 external damping resistor elements of 100 Ohm are
used in series. The third red coloured curve is the critical damped USR, with a
value for the external damping resistor equal to 245 Ohm. A value of R d,1,ext =
245⁡Ohm is needed to obtain optimal behaviour of the RCR HV divider. There is
negligible overshoot with a rise time that is faster than when overdamping occurs.

Figure 4.12. Measured unit step response of the universal HV divider with
different damping resistor values.
 76

5. CONCLUSIONS

The design of the HV divider makes it very easy to assemble and disassemble
the device. It is possible to switch smoothly from measurements of the individual
PCBs or LV arm to measurements of the entire HV divider, as was experienced
during the measurements in TAU's HV lab. The DC scale factor and AC scale
factor matching measurements were done with the entire divider, but the meas-
urement of the resistance value⁡𝑅𝐷𝐶,2,𝑉 afterwards was done separately with the
LV arm. The variable resistance 𝑅𝐷𝐶,2,𝑉 of the LV arm was adjusted experimen-
tally at a value of 35.92 kΩ to match the DC scale factor and AC scale factor of
the HV divider.

The external damping resistor 𝑅𝑑,1,𝑒𝑥𝑡 is connected in series with the top electrode
of the HV divider and consists of ceramic disc resistors. The unit step response
measurements showed that the best dynamic behaviour at impulse voltages is
obtained if a value of 245 Ω is used for 𝑅𝑑,1,𝑒𝑥𝑡 . This top toroid-shaped electrode
is needed together with grading rings along the upper part of the HV divider to
obtain a PD free HV divider up to its nominal AC voltage level of 140 kV. So no
internal PD occurs inside the capacitors of the HV divider. One of the capacitors
failed during preliminary DC calibrations executed at VTT. A possible explanation
for this is that the failed capacitor’s specifications are outside its tolerances due
to a production error. From this it was decided that long-term DC stressing of the
PCBs is needed to find and replace out-of-tolerance capacitors. Both PCBs of the
HV divider withstood a 2 hour long DC-stressing test with an average voltage of
100 kV without failure of a component. The long term stability of the HV divider
was further analysed by carrying out LI stressing and tail chopped LI stressing.

The HV divider withstood a LI stressing of 200 consecutive positive LI and 200

consecutive negative LI (1.2⁡𝜇𝑠/⁡50⁡𝜇𝑠)⁡with an amplitude of 200⁡𝑘𝑉 without failure
of a component. After the LI stressing a tail chopped LI stressing was carried out.
The tail chopped LI stressing had the same values for the LI as in the previous
test. In total 100 consecutive positive tail chopped LI and 100 consecutive nega-
tive tail chopped LI were executed without failure of a component. These meas-
urements contributed to the further development of the universal HV divider. In
 77

addition to the practical part of the thesis, there was also a theoretical part that
encountered challenges.

The main challenge to prove the field of application of the different HV dividers is
that for the heating problem of the resistive HV dividers, specifications of the used
wire-wounded resistors are needed which is not open-sourced by the HV divider
manufacturers. In the section about the simulations of the different types of HV
dividers, the operating range of the HV dividers could not be fully justified be-
cause the software used does not have the capabilities to perform convolution
with SI as input. It can be concluded that both the theoretical and practical objec-
tives were achieved with the means that were available.
 78

6. FUTURE WORK

The assembly, testing and analysis of the universal HV divider at the HV lab of
TAU contributes to the HV-com² project in which one of the objectives is to de-
velop reference universal HV dividers. In the first instance, the calibration of the
universal HV divider should be performed once more in a national metrology in-
stitute. They need to compare whether the performance of the HV divider has
changed after the measurements, long-term stressing and adjustments per-
formed in the HV lab of Tampere University. Also the matching of the scale factor
for the different voltage waveforms needs further tuning, so that combined and
composite waveforms can be measured accurately. The universal HV divider was
designed to be modular, so that more dividers can be stacked on top of each
other to be able to measure higher voltages and thus to obtain higher rated volt-
age level specifications for the HV divider. In case the performance of the single
HV divider is promising, two single HV dividers could be assembled on top of
each other and then once more the performance of the HV divider can be deter-
mined.

From the PD behaviour perspective it is recommended to add grading rings along

the entire length of the upper single HV divider. Also a larger insulating tube may
be needed for the divider if it is used stacked. In any case some further testing
and modelling are needed to evaluate the size of the tube. If it is not possible to
get the modular constructed HV divider PD free by this design, the effect of PD
on the performance of the HV divider should be investigated or the HV divider
should be derated to a voltage level where no PD occurs. Another improvement
on the original design that can be made is to add guarding rails along the length
of the HV divider to stabilise and secure the position of the PCBs.
 79

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