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Description

About M32C/83 Group

The M32C/83 group of single-chip microcomputers are built using a high-performance silicon gate CMOS
process uses a M32C/80 Series CPU core and are packaged in a 144-pin and 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 16M bytes of address space, they are capable of executing instructions at high speed.
They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications,
industrial equipment, and other high-speed processing applications.

Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.

Index
About M32C/83 Group .......................................... 1 Three-phase motor control timers’ functions ..... 155
Central Processing Unit (CPU) ........................... 20 Serial I/O ........................................................... 168
Reset ................................................................... 24 CAN Module ...................................................... 198
SFR ..................................................................... 37 Intelligent I/O ..................................................... 235
Software Reset ................................................... 48 Base timer (group 0 to 3) .................................. 240
Processor Mode .................................................. 48 Time measurement (group 0 and 1) .................. 247
Bus Settings ........................................................ 52 WG function (group 0 to 3) ................................ 252
Bus Control ......................................................... 55 Serial I/O (group 0 to 2) .................................... 264
System Clock ...................................................... 65 A-D Converter ................................................... 281
Power Saving ...................................................... 76 D-A Converter ................................................... 296
Protection ............................................................ 81 CRC Calculation Circuit .................................... 298
Interrupt Outline .................................................. 83 X-Y Converter ................................................... 300
______
INT Interrupts ...................................................... 98 DRAM Controller ............................................... 303
______
NMI Interrupt ....................................................... 99 Programmable I/O Ports ................................... 310
Key Input Interrupt .............................................. 99 VDC .................................................................. 334
Address Match Interrupt .................................... 100 Usage Precaution ............................................. 335
Intelligent I/O and CAN Interrupt ....................... 101 Electrical characteristics ................................... 344
Precautions for Interrupts .................................. 104 Outline Performance ......................................... 381
Watchdog Timer ................................................ 106 Flash Memory ................................................... 383
DMAC ............................................................... 109 CPU Rewrite Mode ........................................... 384
DMAC II ............................................................ 121 Outline Performance of CPU Rewrite Mode ..... 384
Timer ................................................................. 129 Inhibit Rewriting Flash Memory Version ............ 397
Timer A .............................................................. 131 Parallel I/O Mode .............................................. 399
Timer B .............................................................. 147 Standard serial I/O mode .................................. 400

Specifications written in this manual are believed to be accurate, but are

not guaranteed to be entirely free of error.
Specifications in this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.

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Description

Performance Outline
Table 1.1.1 and 1.1.2 are performance outline of M32C/83 group.

Table 1.1.1. Performance outline of M32C/83 group (144-pin version) (1/2)

Item Performance
CPU Number of basic instructions 108 instructions
Shortest instruction execution time 33 ns(f(XIN)=30MHz)
Operation mode Single-chip, memory expansion and microprocessor modes
Memory space 16 M bytes
Memory capacity See ROM/RAM expansion figure.
Peripheral function
I/O port 123 pins (P0 to P15 except P85)
Input port 1 pin (P85)
Multifunction timer Output 16 bits x 5 (TA0, TA1, TA2, TA3, TA4)
Input 16 bits x 6 (TB0, TB1, TB2, TB3, TB4, TB5)
Intelligent I/O 4 groups
Time measurement 8 channels (group 0) + 4 channels (group 1)
Waveform generation 4 channels (group 0) + 8 channels X 3 (group 1, 2 and 3)
Bit-modulation PWM 8 channels X 2 (group 2 and 3)
Real time port 8 channels X 2 (group 2 and 3)
Communication function • Clock synchronous serial I/O, UART (group 0 and 1)
• HDLC data process (group 0 and 1)
• Clock synchronous variable length serial I/O (group 2)
• IE bus (Note 1) (group 2)
Serial I/O 5 channels (UART0 to UART4)
IE Bus (Note 1, 3), I2C Bus (Note 2, 3)
CAN module 1 channel, 2.0B specification
A-D converter 10-bit A-D x 2 circuits, standard 18 inputs, max 34 inputs
D-A converter 8-bit D-A x 2 circuits
DMAC 4 channels
DMAC II Start by all variable vector interrupt factor
Immediate transfer, operation transfer and chain transfer function
DRAM controller CAS before RAS refresh, self-refresh, EDO, FP
CRC calculation circuit CRC-CCITT
X-Y converter 16 bits X 16 bits
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt 42 internal and 8 external sources, 5 software sources, interrupt
priority level 7 levels
Clock generating circuit 3 built-in clock generation circuits
• Main/sub-clock generating circuit :built-in feedback resistance, and
external ceramic or quartz oscillator
• Ring oscillator for detecting main clock oscillation stop

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Description

Table 1.1.1. Performance outline of M32C/83 group (144-pin version) (2/2)

Electric characteristics
Supply voltage 4.2 to 5.5V (f(XIN)=30MHz without wait), 3.0 to 3.6V (f(X IN)=20MHz without wait)
Power consumption 26mA (f(XIN)=20MHz without software wait,Vcc=5V)
38mA (f(XIN)=30MHz without software wait,Vcc=5V)
I/O characteristics I/O withstand voltage :5V
I/O current :5mA
Operating ambient temperature –40 to 85oC
Device configuration CMOS high performance silicon gate
Package 144-pin plastic mold QFP
Note 1 :IE Bus is a trademark of NEC corporation.
Note 2 :I2C Bus is a registered trademark of Philips.
Note 3 :This function is executed by using software and hardware.

Table 1.1.2. Performance outline of M32C/83 group (100-pin version) (1/2)

Item Performance
CPU Number of basic instructions 108 instructions
Shortest instruction execution time 33 ns (f(XIN)=30MHz)
Operation mode Single-chip, memory expansion and microprocessor modes
Memory space 16 M bytes
Memory capacity See ROM/RAM expansion figure.
Peripheral function
I/O port 87 pins (P0 to P10 except P85)
Input port 1 pin (P85)
Multifunction timer Output 16 bits x 5 (TA0, TA1, TA2, TA3, TA4)
Input 16 bits x 6 (TB0, TB1, TB2, TB3, TB4, TB5)
Intelligent I/O 4 groups
Time measurement 3 channels (group 0) + 2 channels (group 1)
Waveform generation 2 channels X 2 (group 0 and 3) + 3 channels X 2 (group 1 and 2)
Bit-modulation PWM 3 channels (group 2) + 2 channels (group 3)
Real time port 3 channels (group 2) + 2 channels (group 3)
Communication function • Clock synchronous serial I/O, UART (group 0 and 1)
• HDLC data process (group 0 and 1)
• Clock synchronous variable length serial I/O (group 2)
• IE bus (Note 1) (group 2)
Serial I/O 5 channels (UART0 to UART4)
IE Bus (Note 1, 3), I2C Bus (Note 2, 3)
CAN module 1 channel, 2.0B specification
A-D converter 10 bits A-Dx 2 circuits, standard 10 inputs, max 26 inputs
D-A converter 8 bits D-A x 2 circuits
DMAC 4 channels
DMAC II Start by all variable vector interrupt factor
Immediate transfer, operation function and chain transfer function
DRAM controller CAS before RAS refresh, self-refresh, EDO, FP
CRC calculation circuit CRC-CCITT

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Description

Table 1.1.2. Performance outline of M32C/83 group (100-pin version) (2/2)

X-Y converter 16 bits X 16 bits
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt 42 internal and 8 external sources, 5 software sources, interrupt priority
level 7 levels
Clock generating circuit 3 built-in clock generation circuits
• Main/sub-clock generating circuit :built-in feedback resistance, and
external ceramic or quartz oscillator
• Ring oscillator for detecting main clock oscillation stop
Electric characteristics
Supply voltage 4.2 to 5.5V (f(XIN)=30MHz without wait), 3.0 to 3.6V (f(XIN)=20MHz without wait)
Power consumption 26mA (f(XIN)=20MHz without software wait,Vcc=5V)
38mA (f(XIN)=30MHz without software wait,Vcc=5V)
I/O characteristics I/O withstand voltage :5V
I/O current :5mA
Operating ambient temperature –40 to 85oC
Device configuration CMOS high performance silicon gate
Package 100-pin plastic mold QFP
Note 1 :IE Bus is a trademark of NEC corporation.
Note 2 :I2C Bus is a registered trademark of Philips.
Note 3 :This function is executed by using software and hardware.

Mitsubishi plans to release the following products in the M32C/83 group:

(1) Support for mask ROM version and flash memory version
(2) ROM capacity
(3) Package
100P6S-A : Plastic molded QFP (mask ROM version and flash memory version)
100P6Q-A : Plastic molded QFP (mask ROM version and flash memory version)
144P6Q-A : Plastic molded QFP (mask ROM version and flash memory version)

RAM size
(byte)
M30835FJGP
M30835MJGP
31K M30833FJGP
M30833MJGP
M30833FJFP
M30833MJFP
20K
10K
128K 192K 256K 512K ROM size
(byte)

Figure 1.1.1. ROM expansion

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Description

The M32C/83 group products currently supported are listed in Table 1.1.3.

Table 1.1.3. M32C/83 group As of Nov. 2001

Type No ROM capacity RAM capacity Package type Remarks
M30835MJGP *** 144P6Q-A
M30833MJGP *** 100P6Q-A Mask ROM version
M30833MJFP *** 100P6S-A
512K 31K
M30835FJGP ** 144P6Q-A
M30833FJGP ** 100P6Q-A Flash memory version
M30833FJFP ** 100P6S-A
** :Under development
*** :Under planning

Type No. M 3 0 8 3 5 F J – (X X X ) G P
Package type:
FP : Package 100P6S-A
GP : Package 100P6Q-A, 144P6Q-A
ROM capacity:
J : 512K bytes

Memory type:
M : Mask ROM version
F : Flash memory version

Shows RAM capacity, pin count, etc

(The value itself has no specific meaning)

M32C/83 Group

M16C Family

Figure 1.1.2. Type No., memory size, and package

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Description

Pin Configuration and Pin Description

Figure 1.1.3 to 1.1.5 show the pin configurations (top view), Table 1.1.3 list pin names, and Table 1.1.4 list
pin description.

P32 / A10 ( MA2 ) ( / D10 )

P34 / A12 ( MA4 ) ( / D12 )

P35 / A13 ( MA5 ) ( / D13 )
P36 / A14 ( MA6 ) ( / D14 )
P37 / A15 ( MA7 ) ( / D15 )
P33 / A11 ( MA3 ) ( / D11 )
P30 / A8 ( MA0 ) ( / D8 )

P31 / A9 ( MA1 ) ( / D9 )
P20 / A0 ( / D0 ) / AN20
P21 / A1 ( / D1 ) / AN21
P22 / A2 ( / D2 ) / AN22
P23 / A3 ( / D3 ) / AN23
P24 / A4 ( / D4 ) / AN24
P25 / A5 ( / D5 ) / AN25
P26 / A6 ( / D6 ) / AN26
P27 / A7 ( / D7 ) / AN27

P42 / A18 ( MA10 )

P43 / A19 ( MA11 )

P40 / A16 ( MA8 )
P41 / A17 ( MA9 )
P15 / D13 / INT3
P16 / D14 / INT4
P17 / D15 / INT5

P120 / OUTC30
P121 / OUTC31
P122 / OUTC32
P123 / OUTC33
P124 / OUTC34
P12 / D10

P14 / D12
P13 / D11
P11 / D9

Vss

Vcc

Vss

Vcc
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
D8 / P10 109 72 P44 / CS3 / A20 (MA12)
AN07 / D7 / P07 110 71 P45 / CS2 / A21
AN06 / D6 / P06 111 70 P46 / CS1 / A22
AN05 / D5 / P05 112 69 P47 / CS0 / A23
AN04 / D4 / P04 113 68 P125 / OUTC35
P114 114 67 P126 / OUTC36
OUTC13 / P113 115 66 P127 / OUTC37
BE1IN / ISRxD1 / OUTC12 / INPC12 / P112 116 65 P50 / WRL / WR / CASL
ISCLK1 / OUTC11 / INPC11 / P111 117 64 P51 / WRH / BHE / CASH
BE1OUT / ISTxD1 / OUTC10 / P110 118 63 P52 / RD / DW
AN03 / D3 / P03 119 62 P53 / CLKOUT / BCLK / ALE
AN02 / D2 / P02 120 61 P130 / OUTC24
AN01 / D1 / P01 121 60 P131 / OUTC25
AN00 / D0 / P00 122 59 Vcc
INPC07 / AN157 / P157 123 58 P132 / OUTC26
INPC06 / AN156 / P156 124 57 Vss
OUTC05 / INPC05 / AN155 / P155 125 56 P133 / OUTC23
OUTC04 / INPC04 / AN154 / P154
INPC03 / AN153 / P153
126
127
M32C/83 (144P6Q-A) 55
54
P54 / HLDA / ALE
P55 / HOLD
BE0IN / ISRxD0 / INPC02 / AN152 / P152 128 53 P56 / ALE / RAS
ISCLK0 / OUTC01 / INPC01 / AN151 / P151 129 52 P57 / RDY
Vss 130 51 P134 / OUTC20 / ISTxD2 / IEOUT
BE0OUT / ISTxD0 / OUTC00 / INPC00 / AN150 / P150 131 50 P135 / OUTC22 / ISRxD2 / IEIN
Vcc 132 49 P136 / OUTC21 / ISCLK2
KI3 / AN7 / P107 133 48 P137 / OUTC27
KI2 / AN6 / P106 134 47 P60 / CTS0 / RTS0 / SS0
KI1 / AN5 / P105 135 46 P61 / CLK0
KI0 / AN4 / P104 136 45 P62 / RxD0 / SCL0 / STxD0
AN3 / P103 137 44 P63 / TxD0 / SDA0 / SRxD0
AN2 / P102 138 43 P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2
AN1 / P101 139 42 P65 / CLK1
AVss 140 41 Vss
AN0 / P100 141 40 P66 / RxD1 / SCL1 / STxD1
VREF 142 39 Vcc
AVcc 143 38 P67 / TxD1 / SDA1 / SRxD1
STxD4 / SCL4 / RxD4 / ADTRG / P97 144 37 P70 / TA0OUT / TxD2 / SDA2 / SRxD2
/ OUTC20 / ISTxD2 / IEOUT
10

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11
1
2
3
4
5
6
7
8
9
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
CLK4 / ANEX0 / P95
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
IEOUT / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92
IEIN / STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
P146
P145
P144
OUTC17 / INPC17 / P143
OUTC16 / INPC16 / P142
OUTC15 / P141
OUTC14 / P140
BYTE
CNVss
VCONT / XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc
NMI / P85
INT2 / P84
CANIN / INT1 / P83
CANOUT / OUTC32 / INT0 / P82
OUTC30 / U / TA4IN / P81
BE0IN / ISRxD0 / INPC02 / U / TA4OUT / P80
CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77
CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74
BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
CLK2 / V / TA1OUT / P72
IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71

Note: P70 and P71 are N-channel open drain output.

Figure 1.1.3. 144-pin version pin configuration (top view)

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Description

Table 1.1.4. 144-pin version pin description (1/3)

Pin
No Control Port Interrupt Timer UART/CAN Intelligent I/O Analog Bus control

1 P96 TxD4/SDA4/SRxD4 ANEX1

2 P95 CLK4 ANEX0
3 P94 TB4IN CTS4/RTS4/SS4 DA1
4 P93 TB3IN CTS3/RTS3/SS3 DA0
5 P92 TB2IN TxD3/SDA3/SRxD3 OUTC20/IEOUT
6 P91 TB1IN RxD3/SCL3/STxD3 IEIN
7 P90 TB0IN CLK3
8 P146
9 P145
10 P144
11 P143 INPC17/OUTC17
12 P142 INPC16/OUTC16
13 P141 OUTC15
14 P140 OUTC14
15 BYTE
16 CNVSS
17 XCIN/VCONT P87
18 XCOUT P86
19 RESET
20 XOUT
21 VSS
22 XIN
23 VCC
24 P85 NMI
25 P84 INT2
26 P83 INT1 CANIN
27 P82 INT0 CANOUT OUTC32
28 P81 TA4IN/U OUTC30
29 P80 TA4OUT/U INPC02/ISRxD0/BE0IN
30 P77 TA3IN CANIN INPC01/OUTC01/ISCLK0
31 P76 TA3OUT CANOUT INPC00/OUTC00/ISTxD0/BE0OUT
32 P75 TA2IN/W INPC12/OUTC12/ISRxD1/BE1IN
33 P74 TA2OUT/W INPC11/OUTC11/ISCLK1
34 P73 TA1IN/V CTS2/RTS2/SS2 OUTC10/ISTxD1/BE1OUT
35 P72 TA1OUT/V CLK2
36 P71 TB5IN/TA0IN RxD2/SCL2/STxD2 OUTC22/ISRxD2/IEIN
37 P70 TA0OUT TxD2/SDA2/SRxD2 OUTC20/ISTxD2/IEOUT
38 P67 TxD1/SDA1/SRxD1
39 VCC
40 P66 RxD1/SCL1/STxD1
41 VSS
42 P65 CLK1
43 P64 CTS1/RTS1/SS1 OUTC21/ISCLK2
44 P63 TxD0/SDA0/SRxD0
45 P62 RxD0/SCL0/STxD0
46 P61 CLK0
47 P60 CTS0/RTS0/SS0
48 P137 OUTC27

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Description

Table 1.1.5. 144-pin version pin description (2/3)

Pin
No Control Port Interrupt Timer UART/CAN Intelligent I/O Analog Bus control

49 P136 OUTC21/ISCLK2
50 P135 OUTC22/ISRxD2/IEIN
51 P134 OUTC20/ISTxD2/IEOUT
52 P57 RDY
53 P56 ALE/RAS
54 P55 HOLD
55 P54 HLDA/ALE
56 P133 OUTC23
57 VSS
58 P132 OUTC26
59 VCC
60 P131 OUTC25
61 P130 OUTC24
62 P53 CLKOUT/BCLK/ALE
63 P52 RD/DW
64 P51 WRH/BHE/CASH
65 P50 WRL/WR/CASL
66 P127 OUTC37
67 P126 OUTC36
68 P125 OUTC35
69 P47 CS0/A23
70 P46 CS1/A22
71 P45 CS2/A21
72 P44 CS3/A20(MA12)
73 P43 A19(MA11)
74 VCC
75 P42 A18(MA10)
76 VSS
77 P41 A17(MA9)
78 P40 A16(MA8)
79 P37 A15(MA7)(/D15)
80 P36 A14(MA6)(/D14)
81 P35 A13(MA5)(/D13)
82 P34 A12(MA4)(/D12)
83 P33 A11(MA3)(/D11)
84 P32 A10(MA2)(/D10)
85 P31 A9(MA1)(/D9)
86 P124 OUTC34
87 P123 OUTC33
88 P122 OUTC32
89 P121 OUTC31
90 P120 OUTC30
91 VCC
92 P30 A8(MA0)(/D8)
93 VSS
94 P27 AN37 A7(/D7)
95 P26 AN36 A6(/D6)
96 P25 AN35 A5(/D5)

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Table 1.1.6. 144-pin version pin description (3/3)

Pin
Control Port Interrupt Timer UART/CAN Intelligent I/O Analog Bus control
No
97 P24 AN24 A4(/D4)
98 P23 AN23 A3(/D3)
99 P22 AN22 A2(/D2)
100 P21 AN21 A1(/D1)
101 P20 AN20 A0(/D0)
102 P17 INT5 D15
103 P16 INT4 D14
104 P15 INT3 D13
105 P14 D12
106 P13 D11
107 P12 D10
108 P11 D9
109 P10 D8
110 P07 AN07 D7
111 P06 AN06 D6
112 P05 AN05 D5
113 P04 AN04 D4
114 P114
115 P113 OUTC13
116 P112 INPC12/OUTC12/ISRxD1/BE1IN
117 P111 INPC11/OUTC11/ISCLK1
118 P110 OUTC10/ISTxD1/BE1OUT
119 P03 AN03 D3
120 P02 AN02 D2
121 P01 AN01 D1
122 P00 AN00 D0
123 P157 INPC07 AN157
124 P156 INPC06 AN156
125 P155 INPC05/OUTC05 AN155
126 P154 INPC04/OUTC04 AN154
127 P153 INPC03 AN153
128 P152 INPC02/ISRxD0/BE0IN AN152
129 P151 INPC01/OUTC01/ISCLK0 AN151
130 VSS
131 P150 INPC00/OUTC00/ISTxD0/BE0OUT AN150
132 VCC
133 P107 KI3 AN7
134 P106 KI2 AN6
135 P105 KI1 AN5
136 P104 KI0 AN4
137 P103 AN3
138 P102 AN2
139 P101 AN1
140 AVSS
141 P100 AN0
142 VREF
143 AVCC
144 P97 RxD4/SCL4/STxD4 ADTRG

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STxD4 / SCL4 /
RxD4 / ADTRG / P97
AVcc
VREF
AN0 / P100
AVss
AN1 / P101
AN2 / P102
AN3 / P103
KI0 / AN4 / P104
KI1 / AN5 / P105
KI2 / AN6 / P106
KI3 / AN7 / P107
D0 / AN00 / P00
D1 / AN01 / P01
D2 / AN02 / P02
D3 / AN03 / P03
D4 / AN04 / P04
D5 / AN05 / P05
D6 / AN06 / P06
D7 / AN07 / P07

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

100
SRxD4 / SDA4 / TxD4 / ANEX1 / P96 1 80 P10 / D8
CLK4 / ANEX0 / P95 2 79 P11 / D9
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 3 78 P12 / D10
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 4 77 P13 / D11
IEOUT / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 5 76 P14 / D12
IEIN / STxD3 / SCL3 / RxD3 / TB1IN / P91 6 75 P15 / D13 / INT3
CLK3 / TB0IN / P90 7 74 P16 / D14 / INT4
BYTE 8 73 P17 / D15 / INT5
CNVss 9 72 P20 / A0 ( / D0 ) / AN20
VCONT / XCIN / P87 10 71 P21 / A1 ( / D1 ) / AN21
XCOUT / P86 11 70 P22 / A2 ( / D2 ) / AN22
RESET 12 69 P23 / A3 ( / D3 ) / AN23
XOUT 13 68 P24 / A4 ( / D4 ) / AN24
Vss 14 67 P25 / A5 ( / D5 ) / AN25
XIN 15 66 P26 / A6 ( / D6 ) / AN26

Note: P70 and P71 are N-channel open drain output.

Vcc 16 65 P27 / A7 ( / D7 ) / AN27
NMI / P85 17 64 Vss
INT2 / P84 18 63 P30 / A8 ( MA0 ) ( / D8 )
Rev.B2 for proof reading

CANIN / INT1 / P83 19 62 Vcc

CANOUT / OUTC32 / INT0 / P82 20 61 P31 / A9 ( MA1 ) ( / D9 )

Figure 1.1.4. 100-pin version pin configuration (top view)

OUTC30 / U / TA4IN / P81 21 60 P32 / A10 ( MA2 ) ( / D10 )
BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80 22
M32C/83 (100P6S-A) 59 P33 / A11 ( MA3 ) ( / D11 )
CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 23 58 P34 / A12 ( MA4 ) ( / D12 )
CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 24 57 P35 / A13 ( MA5 ) ( / D13 )
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 25 56 P36 / A14 ( MA6 ) ( / D14 )
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 26 55 P37 / A15 ( MA7 ) ( / D15 )
BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 27 54 P40 / A16 ( MA8 )
CLK2 / V / TA1OUT / P72 28 53 P41 / A17 ( MA9 )
IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 29 52 P42 / A18 ( MA10 )
IEOUT / ISTxD2 / OUTC20 / SRxD2 / SDA2 / TxD2 / TA0OUT / P70 30 31 51 P43 / A19 ( MA11 )
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

P57 / RDY

P65 / CLK1
P61 / CLK0
P55 / HOLD
P52 / RD / DW
P47 / CS0 / A23
P46 / CS1 / A22
P45 / CS2 / A21

P56 / ALE / RAS

P54 / HLDA / ALE
P44 / CS3 / A20 (MA12)

P50 / WRL / WR / CASL

P60 / CTS0 / RTS0 / SS0

P51 / WRH / BHE / CASH

P66 / RxD1 / SCL1 / STxD1

P62 / RxD0 / SCL0 / STxD0

P67 / TxD1 / SDA1 / SRxD1

P63 / TxD0 / SDA0 / SRxD0
P53 / CLKOUT / BCLK / ALE

P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M32C/83 group
Mitsubishi Microcomputers
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Description

P32 / A10 ( MA2 ) ( / D10 )

P34 / A12 ( MA4 ) ( / D12 )

P35 / A13 ( MA5 ) ( / D13 )
P36 / A14 ( MA6 ) ( / D14 )
P37 / A15 ( MA7 ) ( / D15 )
P33 / A11 ( MA3 ) ( / D11 )
P20 / A0 ( / D0 ) / AN20
P21 / A1 ( / D1 ) / AN21
P22 / A2 ( / D2 ) / AN22
P23 / A3 ( / D3 ) / AN23
P24 / A4 ( / D4 ) / AN24
P25 / A5 ( / D5 ) / AN25
P26 / A6 ( / D6 ) / AN26
P27 / A7 ( / D7 ) / AN27

P30 / A8 ( MA0 ) ( / D8 )

P31 / A9 ( MA1 ) ( / D9 )

P40 / A16 ( MA8 )

P41 / A17 ( MA9 )
P15 / D13 / INT3
P16 / D14 / INT4
P17 / D15 / INT5
P14 / D12
P13 / D11

Vss

Vcc
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
D10 / P12 76 50 P42 / A18 ( MA10 )
D9 / P11 77 49 P43 / A19 ( MA11 )
D8 / P10 78 48 P44 / CS3 / A20 (MA12)
D7 / AN07 / P07 79 47 P45 / CS2 / A21
D6 / AN06 / P06 80 46 P46 / CS1 / A22
D5 / AN05 / P05 81 45 P47 / CS0 / A23
D4 / AN04 / P04 82 44 P50 / WRL / WR / CASL
D3 / AN03 / P03 83 43 P51 / WRH / BHE / CASH
D2 / AN02 / P02 84 42 P52 / RD / DW
D1 / AN01 / P01 85 41 P53 / CLKOUT / BCLK / ALE
D0 / AN00 / P00 86 40 P54 / HLDA / ALE
KI3 / AN37 / P107
KI2 / AN36 / P106
87
88
M32C/83 (100P6Q-A) 39
38
P55 / HOLD
P56 / ALE / RAS
KI1 / AN35 / P105 89 37 P57 / RDY
KI0 / AN34 / P104 90 36 P60 / CTS0 / RTS0 / SS0
AN33 / P103 91 35 P61 / CLK0
AN32 / P102 92 34 P62 / RxD0 / SCL0 / STxD0
AN31 / P101 93 33 P63 / TxD0 / SDA0 / SRxD0
AVss 94 32 P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2
AN30 / P100 95 31 P65 / CLK1
VREF 96 30 P66 / RxD1 / SCL1 / STxD1
AVcc 97 29 P67 / TxD1 / SDA1 / SRxD1
/ ISTxD2 / IEOUT
STxD4 / SCL4 / RxD4 / ADTRG / P97 98 28 P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20
SRxD4 / SDA4 / TxD4 / ANEX1 / P96 99 27 P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 / OUTC22
26 / ISRxD2 / IEIN
CLK4 / ANEX0 / P95 100 P72 / TA1OUT / V / CLK2
10

12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
1
2
3
4
5
6
7
8
9
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
IEOUT / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92
IEIN / STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
BYTE
CNVss
VCONT / XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc
NMI / P85
INT2 / P84
CANIN / INT1 / P83
CANOUT / OUTC32 / INT0 / P82
OUTC30 / U / TA4IN / P81
BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80
CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77
CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74
BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73

Note: P70 and P71 are N-channel open drain output.

Figure 1.1.5. 100-pin version pin configuration (top view)

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Description

Table 1.1.7. 100-pin version pin description (1/2)

Package
Pin No
Control Port Interrupt Timer UART/CAN Intelligent I/O Analog Bus control
FP GP
1 99 P96 TxD4/SDA4/SRxD4 ANEX1
2 100 P95 TB4IN CLK4 ANEX0
3 1 P94 TB3IN CTS4/RTS4/SS4 DA1
4 2 P93 TB2IN CTS3/RTS3/SS3 DA0
5 3 P92 TB1IN TxD3/SDA3/SRxD3 OUTC20/IEOUT
6 4 P91 TB0IN RxD3/SCL3/STxD3 IEIN
7 5 P90 CLK3
8 6 BYTE
9 7 CNVSS
10 8 XCIN/VCONT P87
11 9 XCOUT P86
12 10 RESET
13 11 XOUT
14 12 VSS
15 13 XIN
16 14 VCC
17 15 P85 NMI
18 16 P84 INT2
19 17 P83 INT1 CANIN
20 18 P82 INT0 TA4IN/U CANOUT OUTC32
21 19 P81 TA4OUT/U OUTC30
22 20 P80 TA3IN INPC02/ISRxD0/BE0IN
23 21 P77 TA3OUT CANIN INPC01/OUTC01/ISCLK0
24 22 P76 TA2IN/W CANOUT INPC00/OUTC00/ISTxD0/BE0OUT
25 23 P75 TA2OUT/W INPC12/OUTC12/ISRxD1/BE1IN
26 24 P74 TA1IN/V INPC11/OUTC11/ISCLK1
27 25 P73 TA1OUT/V CTS2/RTS2/SS2 OUTC10/ISTxD1/BE1OUT
28 26 P72 TB5IN/TA0IN CLK2
29 27 P71 TA0OUT RxD2/SCL2/STxD2 OUTC22/ISRxD2/IEIN
30 28 P70 TxD2/SDA2/SRxD2 OUTC20/ISTxD2/IEOUT
31 29 P67 TxD1/SDA1/SRxD1
32 30 P66 RxD1/SCL1/STxD1
33 31 P65 CLK1
34 32 P64 CTS1/RTS1/SS1 OUTC21/ISCLK2
35 33 P63 TxD0/SDA0/SRxD0
36 34 P62 RxD0/SCL0/STxD0
37 35 P61 CLK0
38 36 P60 CTS0/RTS0/SS0
39 37 P57 RDY
40 38 P56 ALE/RAS
41 39 P55 HOLD
42 40 P54 HLDA/ALE
43 41 P53 CLKOUT/BCLK/ALE
44 42 P52 RD/DW
45 43 P51 WRH/BHE/CASH
46 44 P50 WRL/WR/CASL
47 45 P47 CS0/A23
48 46 P46 CS1/A22
49 47 P45 CS2/A21
50 48 P44 CS3/A20(MA12)

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Description

Table 1.1.8. 100-pin version pin description (2/2)

Package
pin No Interrupt Timer UART/CAN Intelligent I/O Analog Bus control
Control Port
FP GP
51 49 P43 A19(MA11)
52 50 P42 A18(MA10)
53 51 P41 A17(MA9)
54 52 P40 A16(MA8)
55 53 P37 A15(MA7)(/D15)
56 54 P36 A14(MA6)(/D14)
57 55 P35 A13(MA5)(/D13)
58 56 P34 A12(MA4)(/D12)
59 57 P33 A11(MA3)(/D11)
60 58 P32 A10(MA2)(/D10)
61 59 P31 A9(MA1)(/D9)
62 60 VCC
63 61 P30 A8(MA0)(/D8)
64 62 VSS
65 63 P27 AN27 A7(/D7)
66 64 P26 AN26 A6(/D6)
67 65 P25 AN25 A5(/D5)
68 66 P24 AN24 A4(/D4)
69 67 P23 AN23 A3(/D3)
70 68 P22 AN22 A2(/D2)
71 69 P21 AN21 A1(/D1)
72 70 P20 AN20 A0(/D0)
73 71 P17 INT5 D15
74 72 P16 INT4 D14
75 73 P15 INT3 D13
76 74 P14 D12
77 75 P13 D11
78 76 P12 D10
79 77 P11 D9
80 78 P10 D8
81 79 P07 AN07 D7
82 80 P06 AN06 D6
83 81 P05 AN05 D5
84 82 P04 AN04 D4
85 83 P03 AN03 D3
86 84 P02 AN02 D2
87 85 P01 AN01 D1
88 86 P00 AN00 D0
89 87 P107 KI3 AN7
90 88 P106 KI2 AN6
91 89 P105 KI1 AN5
92 90 P104 KI0 AN4
93 91 P103 AN3
94 92 P102 AN2
95 93 P101 AN1
96 94 AVSS
97 95 P100 AN0
98 96 VREF
99 97 AVCC
100 98 P97 RxD4/SCL4/STxD4 ADTRG

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Description

Table 1.1.9. Pin description (1/4)

Port Function Pin name I/O type Description

Power supply VCC I 4.2 to 5.5 V or 3.0V to 3.6V.

input VSS I 0 V.
CPU mode switch CNVSS I Connect it to VSS : Single-chip or memory expansion mode
Connect it to VCC : Microprocessor mode
External data BYTE I Selects the width of the data bus for external memory.
bus width Connect it to VSS : A 16-bit width
select input Connect it to VCC : An 8-bit width
Reset input RESET I A “L” on this input resets the microcomputer.

Clock input XIN I These pins are provided for the main clock generating circuit.
Connect a ceramic resonator or crystal between the XIN and
Clock output XOUT O the XOUT pins. To use an externally derived clock, input it to
the XIN pin and leave the XOUT pin open.
Analog power AVCC I Connect this pin to VCC.
supply input AVSS I Connect this pin to VSS.
Reference VREF I This pin is a reference voltage input for the A-D converter.
voltage input
P0 I/O port P00 to P07 I/O An 8-bit CMOS I/O port.
It has an input/output port direction register that allows the
user to set each pin for input or output individually.
The user can specify in units of four bits via software whether
or not they are tied to a pull-up resistor.
Data bus D0 to D7 I/O When set as a separate bus, these pins input and output 8
low-order data bits.
Analog input port AN00 to AN07 I P00 to P07 are analog input ports for the A-D converter.
P1 I/O port P10 to P17 I/O This is an 8-bit I/O port equivalent to P0.
External interrupt input INT3 to INT5 I P15 to P17 function as external interrupt pins.
port
Data bus D8 to D15 I/O When set as a separate bus, these pins input and output 8
high-order data bits.
P2 I/O port P20 to P27 I/O This is an 8-bit I/O port equivalent to P0.

Address bus A0 to A7 O These pins output 8 low-order address bits.

Address bus/data bus A0/D0 to I/O If a multiplexed bus is set, these pins input and output data and
A7/D7 output 8 low-order address bits separated in time by
multiplexing.
Analog input port AN20 to AN27 I P20 to P27 are analog input ports for the A-D converter.

P3 I/O port P30 to P37 I/O This is an 8-bit I/O port equivalent to P0.

Address bus A8 to A15 O These pins output 8 middle-order address bits.

Address bus/data bus A8/D8 to I/O If the external bus is set as a 16-bit wide multiplexed bus,
A15/D15 these pins output 8 middle-order address bits, and input and
output 8 middle-order data separated in time by multiplexing.

Address bus MA0 to MA7 O If accessing to DRAM area, these pins output row address
and column address separated in time by multiplexing.
P4 I/O port P40 to P47 I/O This is an 8-bit I/O port equivalent to P0.

Address bus A16 to A22 O These pins output 8 high-order address bits.
A23 Highest address bit (A23) outputs inversely.
Chip select CS0 to CS3 O P40 to P47 are chip select output pins to specify access area.
Address bus MA8 to MA12 O If accessing to DRAM area, these pins output row address and
column address separated in time by multiplexing.

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Description

Table 1.1.10. Pin description (2/4)

Port Function Pin name I/O type Description

P5 I/O port P50 to P57 I/O This is an 8-bit I/O port equivalent to P0.
Clock output CLKOUT I/O P53 in this port outputs a divide-by-8 or divide-by-32 clock of
XIN or a clock of the same frequency as XCIN.
Bus control WRL / WR, O Output WRL, WRH and RD, or WR, BHE and RD bus control
WRH / BHE, O signals.
RD O WRL, WRH, and RD selected
In 16-bit data bus, data is written to even addresses when the
WRL signal is “L”.
Data is written to odd addresses when the WRH signal is “L”.
Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”.
Data is read when RD is “L”.
Odd addresses are accessed when BHE is “L”. Even
addresses are accessed when BHE is “H”.
Use WR, BHE, and RD when all external memory is an 8-bit
data bus.
BCLK, O Output operation clock for CPU.
HOLD, I While the input level at the HOLD pin is “L”, the microcomputer
is placed in the hold state.
HLDA O While in the hold state, HLDA outputs a “L” level.
ALE, O ALE is used to latch the address.
RDY I While the input level of the RDY pin is “L”, the microcomputer
is in the ready state.
Bus control for DRAM DW, O When DW signal is “L”, write to DRAM.
CASL, O Timing signal when latching to line address of even address.
CASH, O Timing signal when latching to line address of odd address.
RAS O Timing signal when latching to row address.
P6 I/O port P60 to P67 I/O This is an 8-bit I/O port equivalent to P0.
UART port CTS/RTS/SS I/O P60 to P63 are I/O ports for UART0.
CLK P64 to P67 are I/O ports for UART1.
RxD/SCL/STxD
TxD/SDA/SRxD
Intelligent I/O port OUTC/ISCLK I/O ISCLK is a clock I/O port for intelligent I/O communication.
OUTC is an output port for waveform generation function.
P7 I/O port P70 to P77 I/O This is an 8-bit I/O port equivalent to P0.
However, P70 and P71 are N-channel open drain outputs.
Timer A port TAOUT O P70 to P77 are I/O ports for timers A0–A3.
TAIN I
Timer B port TBIN I P71 is an input port for timer B5.
Three phase motor V, V O P72 and P73 are V phase outputs.
control output port W, W P74 and P75 are W phase outputs.
UART port CTS/RTS/SS I/O P70 to P73 are I/O ports for UART2.
CLK
RxD/SCL/STxD
TxD/SDA/SRxD
Intelligent I/O port INPC/OUTC I/O INPC is an input port for time measurement function.
ISCLK/ISTxD/ OUTC is an output port for waveform generation function.
ISRxD ISCLK is a clock I/O port for intelligent I/O communication.
IEOUT/IEIN ISTxD/IEOUT/BEOUT is transmit data output port for intelligent
BEOUT/BEIN I/O communication.
ISRxD/IEIN/BEIN is receive data input port for intelligent I/O
communication.
CANOUT CAN O P76 and P77 are I/O ports for CAN communication function.
CANIN I

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Description

Table 1.1.11. Pin description (3/4)

Port Function Pin name I/O type Description

P8 I/O port P80-P84, P86, P87 I/O This is a 7-bit I/O port equivalent to P0.
Sub clock input XCIN I P86 and P87 function as I/O ports for the sub clock
generating circuit by software. Connect a crystal between
Sub clock output XCOUT O the XCIN and the XCOUT pins.
Low-pass filter connect VCOUT O When using PLL frequency synthesizer, connect P87 to a
pin for PLL frequency low-pass filter. To stabilize PLL frequency, connect P86 to
synthesizer Vss.
Timer A port TA4OUT O P80 to P81 are I/O ports for timer A4.
TA4IN I
Three phase motor U, U O P80 and P81 are U phase output ports.
control output port
External interrupt input INT0 to INT2 I P82 to P84 are external interrupt input ports.
port
Intelligent I/O port INPC/ISRxD/BEIN I INPC is an input port for time measurement function.
ISRxD/BEIN is receive data input port for intelligent I/O
communication.
Input port P85/NMI I Input port and input ports for NMI interrupt.
P9 I/O port P90 to P97 I/O This is an 8-bit I/O port equivalent to P0.
Timer B port TB0IN to TB4IN I P90 to P94 are input port for timer B4.
UART port CTS/RTS/SS I/O P90 to P93 are I/O ports for UART3.
CLK I/O P94 to P97 are I/O ports for UART4.
RxD/SCL/STxD I/O
TxD/SDA/SRxD I/O
D-A output port DA0, DA1 O P93 and P94 are D-A output ports.

A-D related port ANEX1, ANEX2 I P95 to P96 are expanded input port for A-D converter.
ADTRG I P97 is A-D trigger input port.
Intelligent I/O port OUTC/IEOUT I/O OUTC is an output port for waveform generation function.
IEOUT is transmit data output port for intelligent I/O
communication.
IEIN I IEIN is receive data input port for intelligent I/O
communication.
The protect register prevents a false write to P9 direction register and function select register A3.

P10 I/O port P100 to P107 I/O This is an 8-bit I/O port equivalent to P0.
Key input interrupt port KI0 to KI3 I P104 to P107 are key input interrupt ports.
Analog input port AN0 to AN7 I P100 to P107 are analog input ports for A-D convertor.

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Description

Table 1.1.12. Pin description (4/4)

Port Function Pin name I/O type Description

P11 I/O port P110 to P114 I/O This is an 5-bit I/O port equivalent to P0.
(Note)
Intelligent I/O port INPC/OUTC I/O INPC is an input port for time measurement function.
ISCLK I/O OUTC is an output port for waveform generation function.
ISTxD/ISRxD ISCLK is a clock I/O port for intelligent I/O communication.
BEOUT/BEIN I/O ISTxD/BEOUT is transmit data output port for intelligent I/O
communication.
ISRxD/BEIN is receive data input port for intelligent I/O
communication.
P12 I/O port P120 to P127 I/O This is an 8-bit I/O port equivalent to P0.
(Note)
Intelligent I/O port OUTC O OUTC is an output port for waveform generation function.

P13 I/O port P130 to P137 I/O This is an 8-bit I/O port equivalent to P0.
(Note)
Intelligent I/O port OUTC I/O OUTC is an output port for waveform generation function.
ISCLK/ISTxD/ I/O ISCLK is a clock I/O port for intelligent I/O communication.
ISRxD I/O ISTxD/IEOUT is transmit data output port for intelligent I/O
IEOUT/IEIN I/O communication.
ISRxD/IEIN is receive data input port for intelligent I/O
communication.

P14 I/O port P140 to P146 I/O This is a 7-bit I/O port equivalent to P0.
(Note)
Intelligent I/O port INPC/OUTC I/O INPC is an input port for time measurement function.
OUTC is an output port for waveform generation function.

P15 I/O port P150 to P157 I/O This is an 8-bit I/O port equivalent to P0.
(Note)
Intelligent I/O port INPC/OUTC I/O INPC is an input port for time measurement function.
ISCLK/ISTxD/ I/O OUTC is an output port for waveform generation function.
ISRxD ISCLK is a clock I/O port for intelligent I/O communication.
BEOUT/BEIN I/O ISTxD/BEOUT is transmit data output port for intelligent I/O
communication.
ISRxD/BEIN is receive data input port for intelligent I/O
communication.
Analog input port AN150 to AN157 I P150 to P157 are analog input ports for A-D convertor.

Note :Port P11 to P15 exist in 144-pin version.

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Description

Block Diagram
The M32C/83 group includes the following devices in a single-chip. ROM and RAM for code instructions
and data, storage, CPU for executing operation and peripheral functions such as timer, serial I/O, D-A
converter, DMAC, CRC operation circuit, A-D converter, DRAM controller, intelligent I/O and I/O ports.
Figure 1.1.6 is a block diagram of the M32C/83 group (144-pin version).

8 8 8 8 8 8 8 8

Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7

I/O ports
Internal peripheral functions
Timer (16 bits) A-D converter
(10-bit X 2 circuits) System clock generator
Output (5) Input (6) XIN - XOUT
Timer A0 Timer B0 XCIN - XCOUT
Timer A1 Timer B1 UART/Clock synchronous Ring oscillator
Timer A2 Timer B2
SI/O (8-bit X 5 channels)
Timer A3 Timer B3
Timer A4 Timer B4
Timer B5 X-Y converter Memory (Note)
(16-bit X 16-bit)
Three-phase control ROM
circuit
CRC arithmetic circuit
(CCITT) RAM
Watchdog timer (15 bits)

Intelligent I/O M32C/80 series CPU core

Group 0
Group 1 R0H R0L FLG DMA
Group 2 R1H R1L INTB controller
Group 3 R2 ISP DMA II
R3 USP controller
D-A converter
A0 PC
(8-bit X 2 circuit) DRAM
A1 SVF controller
CAN communication FB SVP
function SB VCT Multiplier

Port P15 Port P14 Port P13 Port P12 Port P11 Port P10 Port P9 P85 Port P8

8 7 8 8 5 8 8 7

Figure 1.1.6. Block diagram of the M32C/83 group (144-pin version)

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Description

Memory
Figure 1.2.1 is a memory map of the M32C/83 group. The address space extends 16 Mbytes from address
00000016 to FFFFFF16. From FFFFFF16 down is ROM. For example, in the M30835FJGP, there are 512K
bytes of internal ROM from F8000016 to FFFFFF16. The vector table for fixed interrupts such as the reset
_______
and NMI are mapped to FFFFDC16 to FFFFFF16. The starting address of the interrupt routine is stored
here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal
register (INTB). See the section on interrupts for details.
From 00040016 up is RAM. For example, in the M30835FJGP, 31 Kbytes of internal RAM are mapped to
the space from 00040016 to 007FFF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped from 00000016 to 0003FF16. This area accommodates the control registers for
peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area
that is not occupied is reserved and cannot be used for any other purpose.
The special page vector table is mapped from FFFE0016 to FFFFDB16. If the starting addresses of subrou-
tines or the destination addresses of jumps are stored here, subroutine call instructions and jump instruc-
tions can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used.

00000016
SFR area
00040016
Internal RAM FFFE0016
area

AAAAA
XXXXXX16
Internal reserved

AAAAA
area (Note 1) Special page
00800016 vector table

AAAAA
External area

AAAAA FFFFDC16 Undefined instruction

F0000016 Overflow
Internal reserved BRK instruction
area (Note 2) Address match

YYYYYY16 Watchdog timer

Internal ROM
area NMI
Address Address
Type No. FFFFFF16 FFFFFF16 Reset
XXXXX16 YYYYY16
M30835F/MJ
007FFF16 F8000016 Note 1: During memory expansion and microprocessor modes, can not be used.
M30833F/MJ
Note 2: In memory expansion mode, can not be used.

Figure 1.2.1. Memory map

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Software Reset

Central Processing Unit (CPU)

The CPU has a total of 28 registers shown in Figure 1.3.1. Eight of these registers (R0, R1, R2, R3, A0, A1,
SB and FB) come in two sets; therefore, these have two register banks.

General register b15 b0

FLG Flag register
b31
R2 R0H R0L
R3 R1H R1L
Data register (Note)
R2

b23 R3
A0
Address register (Note)
A1
SB Static base register (Note)
FB Frame base register (Note)

USP User stack pointer

ISP Interrupt stack pointer

INTB Interrupt table register

PC Program counter

High-speed interrupt register b15 b0

SVF Flag save register
b23
SVP PC save register

VCT Vector register

DMAC related register b7 b0

DMD0
DMA mode register
b15 DMD1
DCT0
DMA transfer count register
DCT1

DRC0
DMA transfer count reload register
b23
DRC1
DMA0
DMA memory address register
DMA1

DSA0
DMA SFR address register
DSA1

DRA0
DMA memory address reload register
DRA1

Note: These registers have two register banks.

Figure 1.3.1. Central processing unit register

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Processor Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, R3, R2R0 and R3R1)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). Registers R2 and R0, as well as R3 and R1 can function as 32-bit data
registers (R2R0/R3R1).

(2) Address registers (A0 and A1)

Address registers (A0 and A1) are configured with 24 bits, and have functions equivalent to those of data
registers. These registers can also function as address register, indirect addressing and address register
relative addressing.

(3) Static base register (SB)

Static base register (SB) is configured with 24 bits, and is used for SB relative addressing.

(4) Frame base register (FB)

Frame base register (FB) is configured with 24 bits, and is used for FB relative addressing.

(5) Program counter (PC)

Program counter (PC) is configured with 24 bits, indicating the address of an instruction to be executed.

(6) Interrupt table register (INTB)

Interrupt table register (INTB) is configured with 24 bits, indicating the start address of an interrupt vector
table.

(7) User stack pointer (USP), interrupt stack pointer (ISP)

Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 24 bits.
The desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This
flag is located at bit 7 in the flag register (FLG).
To execute efficienly set USP and ISP to an even number.

(8) Save flag register (SVF)

This register consists of 16 bits and is used to save the flag register when a high-speed interrupt is
generated.

(9) Save PC register (SVP)

This register consists of 24 bits and is used to save the program counter when a high-speed interrupt is
generated.
This register consist of 24 bits and is used to indicate a jump address when a high-speed interrupt is
generated.

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Processor Mode

(10) Vector register (VCT)

This register consists of 24 bits and is used to indicate the jump address when a high-speed interrupt is
generated.

(11) DMA mode registers (DMD0/DMD1)

These registers consist of 8 bits and are used to set the transfer mode, etc. for DMA.

(12) DMA transfer count registers (DCT0/DCT1)

These registers consist of 16 bits and are used to set the number of DMA transfers performed.

(13) DMA transfer count reload registers (DRC0/DRC1)

These registers consist of 16 bits and are used to reload the DMA transfer count registers.

(14) DMA memory address registers (DMA0/DMA1)

These registers consist of 24 bits and are used to set a memory address at the source or destination of
DMA transfer.

(15) DMA SFR address registers (DSA0/DSA1)

These registers consist of 24 bits and are used to set a fixed address at the source or destination of DMA
transfer.

(16) DMA memory address reload registers (DRA0/DRA1)

These registers consist of 24 bits and are used to reload the DMA memory address registers.

(17) Flag register (FLG)

Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.3.2 shows the flag
register (FLG). The following explains the function of each flag:

• Bit 0: Carry flag (C)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

• Bit 1: Debug flag (D)

This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.

• Bit 2: Zero flag (Z)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.

• Bit 3: Sign flag (S)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”.

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Processor Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

• Bit 4: Register bank select flag (B)

This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.

• Bit 5: Overflow flag (O)

This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.

• Bit 6: Interrupt enable flag (I)

This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.

• Bit 7: Stack pointer select flag (U)

Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Numbers. 0 to 31 is executed.

• Bits 8 to 11: Reserved area

• Bits 12 to 14: Processor interrupt priority level (IPL)

Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.

• Bit 15: Reserved area

AAAAAAAAA
b15
AA
A
AAAAAAAAAAA
AA
A AAAAA
AA
AAAAAAAA
IPL AA
AAA U I O B S Z D C
b0
Flag register (FLG)

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

Figure 1.3.2. Flag register (FLG)

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Reset

Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is enabled by holding the
reset pin Low (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to High while
main clock is stable, the reset status is cancelled and program execution resumes from the address in the
reset vector table.
Since the value of RAM is indeterminate when power is applied, the initial values must be set. Also, if a
reset signal is input during write to RAM, the access to the RAM will be interrupted. Consequently, the value
of the RAM being written may change to an unintended value due to the interruption.
Figure 1.4.1 shows the example reset circuit. Figure 1.4.2 shows the reset sequence.
____________
Table 1.4.1 shows the status of other pins while the RESET pin level is Low. Figures 1.4.3 and 1.4.4 show
the internal status of the microcomputer immediately after the reset is cancelled.

5V
4.2V
VCC

0V
RESET VCC 5V

RESET
0.8V
0V

Example when VCC = 5V.

Figure 1.4.1. Example reset circuit

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Reset

XIN
More than 20 cycles are needed
Microprocessor
mode BYTE = “H”

RESET BCLK 24cycles

BCLK
Content of reset vector

Address FFFFC16 FFFFD16 FFFFE16

RD

WR

CS0

Microprocessor
mode BYTE = “L” Content of reset vector

Address FFFFC16 FFFFE16

RD

WR

CS0

Single chip
FFFFC16 Content of reset vector
mode

Address

FFFFE16

Figure 1.4.2. Reset sequence

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Reset

____________
Table 1.4.1. Pin status when RESET pin level is “L”

Status
Pin name CNVSS = VCC
CNVSS = VSS
BYTE = VSS BYTE = VCC

P0 Input port (floating) Data input (floating)

P1 Input port (floating) Data input (floating) Input port (floating)
P2, P3, P4 Input port (floating) Address output (undefined)
P50 Input port (floating) WR output (“H” level output)
P51 Input port (floating) BHE output (undefined)
P52 Input port (floating) RD output (“H” level output)
P53 Input port (floating) BCLK output

P54 Input port (floating) HLDA output (The output value depends on the input to the
HOLD pin)

P55 Input port (floating) HOLD input (floating)

P56 Input port (floating) RAS output
P57 Input port (floating) RDY input (floating)
P6 to P15 (Note) Input port (floating) Input port (floating)

Note :Port P11 to P15 exists in 144-pin version.

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Reset

(1) Processor mode register 0 (Note 1) (000416) 8016 (26) UART2 receive /ACK interrupt control register (006B16) X X X X ? 0 0 0

(2) Processor mode register 1 (000516) X 0 0 0 0 0 X X (27) Timer A0 interrupt control register (006C16) X X X X ? 0 0 0

(3) System clock control register 0 (000616) 0 0 0 0 X 0 0 0 (28) UART3 receive/ACK interrupt control register (006D16) X X X X ? 0 0 0

(4) System clock control register 1 (000716) 2016 (29) Timer A2 interrupt control register (006E16) X X X X ? 0 0 0

(5) Wait control register (000816) FF16 (30) UART4 receive/ACK interrupt control register (006F16) X X X X ? 0 0 0

(6) Address match interrupt control register (000916) X X X X 0 0 0 0 (31) Timer A4 interrupt control register (007016) X X X X ? 0 0 0

(7) Protect register (000A16) X X X X 0 0 0 0 (32) UART0/UART3 bus collision detection interrupt (007116) X X X X ? 0 0 0
control register

(8) External data bus width control register (Note 2) (000B16) XXXXX0 0 0 (33) UART0 receive/ACK interrupt control register (007216) X X X X ? 0 0 0

(9) Main clock divided register (000C16) X X X 0 1 0 0 0 (34) A-D0 interrupt control register (007316) X X X X ? 0 0 0

(10) Oscillation stop detect register (000D16) 0016 (35) UART1 receive/ACK interrupt control register (007416) X X X X ? 0 0 0

(11) Watchdog timer start register (000E16) ??16 (36) Intelligent I/O interrupt control register 0 (007516) X X X X ? 0 0 0

(12) Watchdog timer control register (000F16) 0 0 0 ? ? ? ? ? (37) Timer B1 interrupt control register (007616) X X X X ? 0 0 0

(13) Address match interrupt register 0 (001016) 0016 (38) Intelligent I/O interrupt control register 2 (007716) X X X X ? 0 0 0

(001116) 0016 (39) Timer B3 interrupt control register (007816) X X X X ? 0 0 0

(001216) 0016 (40) Intelligent I/O interrupt control register 4 (007916) X X X X ? 0 0 0

(14) Address match interrupt register 1 (001416) 0016 (41) INT5 interrupt control register (007A16) X X 0 0 ? 0 0 0

(001516) 0016 (42) Intelligent I/O interrupt control register 6 (007B16) X X X X ? 0 0 0

(001616) 0016 (43) INT3 interrupt control register (007C16) X X 0 0 ? 0 0 0

(15) VDC control register for PLL (001716) X X X X X X 0 1 (44) Intelligent I/O interrupt control register 8 (007D16) X X X X ? 0 0 0

(16) Address match interrupt register 2 (001816) 0016 (45) INT1 interrupt control register (007E16) X X 0 0 ? 0 0 0
Intelligent I/O interrupt control register 10/
(001916) 0016 (46) (007F16) X X X X ? 0 0 0
CAN interrupt 1 control register

(001A16) 0016 (47) Intelligent I/O interrupt control register 11/ (008116) X X X X ? 0 0 0
CAN interrupt 2 control register

(17) VDD control register 1 (001B16) 0016 (48) A -D1 interrupt control register (008616) X X X X ? 0 0 0

(18) Address match interrupt register 3 (001C16) 0016 (49) DMA1 interrupt control register (008816) X X X X ? 0 0 0

(001D16) 0016 (50) UART2 transmit /NACK interrupt control register (008916) X X X X ? 0 0 0

(001E16) 0016 (51) DMA3 interrupt control register (008A16) X X X X ? 0 0 0

(19) VDD control register 1 (001F16) 0016 (52) UART3 transmit /NACK interrupt control register (008B16) X X X X ? 0 0 0

(20) DRAM control register (004016) ? X X X ? ? ? ? (53) Timer A1 interrupt control register (008C16) X X X X ? 0 0 0

(21) DRAM refresh interval set register (004116) ??16 (54) UART4 transmit /NACK interrupt control register (008D16) X X X X ? 0 0 0

(22) Flash memory control register 0 (005716) X X 0 0 0 0 0 1 (55) Timer A3 interrupt control register (008E16) X X X X ? 0 0 0

(23) DMA0 interrupt control register (006816) X X X X ? 0 0 0 (56) UART2 bus collision detection interrupt (008F16) X X X X ? 0 0 0
control register
(24) Timer B5 interrupt control register (006916) X X X X ? 0 0 0 (57) UART0 transmit /NACK interrupt control register (009016) X X X X ? 0 0 0

(25) DMA2 interrupt control register (006A16) X X X X ? 0 0 0 (58) UART1/UART4 bus collision detection (009116) X X X X ? 0 0 0
interrupt control register

x : Nothing is mapped to this bit

? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note 1: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
Note 2: When the BYTE pin is "L", bit 3 is "1". When the BYTE pin is "H", bit 3 is "0".

Figure 1.4.3. Device's internal status after a reset is cleared (1/10)

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Reset

(59) UART1 transmit/NACK interrupt control register (009216) X X X X ? 0 0 0 (92) Interrupt enable register 7 (00B716) 0 X X 0 0 0 0 0

(60) Key input interrupt control register (009316) X X X X ? 0 0 0 (93) Interrupt enable register 8 (00B816) 0 0 X 0 0 0 0 0

(61) Timer B0 interrupt control register (009416) X X X X ? 0 0 0 (94) Interrupt enable register 9 (00B916) 0 X X X 0 0 0 0

(62) Intelligent I/O interrupt control register 1 (009516) X X X X ? 0 0 0 (95) Interrupt enable register 10 (00BA16) 0 X X X 0 0 0 0

(63) Timer B2 interrupt control register (009616) X X X X ? 0 0 0 (96) Interrupt enable register 11 (00BB16) 0 X X 0 0 0 0 0

(64) Intelligent I/O interrupt control register 3 (009716) X X X X ? 0 0 0 (97) Group 0 time measurement/waveform (00C016) ??16
generate register 0
(65) Timer B4 interrupt control register (009816) X X X X ? 0 0 0 (00C116) ??16

(66) Intelligent I/O interrupt control register 5 (009916) X X X X ? 0 0 0 (98) Group 0 time measurement/waveform (00C216) ??16
generate register 1
(67) INT4 interrupt control register (009A16) X X 0 0 ? 0 0 0 (00C316) ??16

(68) Intelligent I/O interrupt control register 7 (009B16) X X X X ? 0 0 0 (99) Group 0 time measurement/waveform (00C416) ??16
generate register 2
(69) INT2 interrupt control register (009C16) X X 0 0 ? 0 0 0 (00C516) ??16

(70) Intelligent I/O interrupt control register 9/ (009D16) X X X X ? 0 0 0 (100) Group 0 time measurement/waveform (00C616) ??16
CAN interrupt 0 control register
generate register 3
(71) INT0 interrupt control register (009E16) X X 0 0 ? 0 0 0 (00C716) ??16

(72) Exit priority register (009F16) X X 0 X 0 0 0 0 (101) Group 0 time measurement/waveform (00C816) ??16
generate register 4
(73) Interrupt request register 0 (00A016) X X 0 0 X 0 0 X (00C916) ??16

(74) Interrupt request register 1 (00A116) X X 0 0 X 0 0 X (102) Group 0 time measurement/waveform (00CA16) ??16
generate register 5
(75) Interrupt request register 2 (00A216) X X 0 0 X 0 X X (00CB16) ??16

(76) Interrupt request register 3 (00A316) X X 0 0 0 0 0 X (103) Group 0 time measurement/waveform (00CC16) ??16
generate register 6
(77) Interrupt request register 4 (00A416) 0 0 X 0 0 0 0 X (00CD16) ??16

(78) Interrupt request register 5 (00A516) X X X 0 0 0 0 X (104) Group 0 time measurement/waveform (00CE16) ??16
generate register 7
(79) Interrupt request register 6 (00A616) X X X 0 0 0 0 X (00CF16) ??16

(80) Interrupt request register 7 (00A716) 0 X X 0 0 0 0 X (105) Group 0 waveform generate control register 0 (00D016) 0 X 0 0 X 0 0 0

(81) Interrupt request register 8 (00A816) 0 0 X 0 0 0 0 X (106) Group 0 waveform generate control register 1 (00D116) 0 X 0 0 X 0 0 0

(82) Interrupt request register 9 (00A916) 0 X X 0 0 0 0 X (107) Group 0 waveform generate control register 4 (00D416) 0 X 0 0 X 0 0 0

(83) Interrupt request register 10 (00AA16) 0 X X 0 0 0 0 X (108) Group 0 waveform generate control register 5 (00D516) 0 X 0 0 X 0 0 0

(84) Interrupt request register 11 (00AB16) 0 X X 0 0 0 0 X (109) Group 0 time measurement control register 0 (00D816) 0016

(85) Interrupt enable register 0 (00B016) X X 0 0 X 0 0 0 (110) Group 0 time measurement control register 1 (00D916) 0016

(86) Interrupt enable register 1 (00B116) X X 0 0 X 0 0 0 (111) Group 0 time measurement control register 2 (00DA16) 0016

(87) Interrupt enable register 2 (00B216) X X 0 0 X 0 X 0 (112) Group 0 time measurement control register 3 (00DB16) 0016

(88) Interrupt enable register 3 (00B316) X X 0 0 0 0 0 0 (113) Group 0 time measurement control register 4 (00DC16) 0016

(89) Interrupt enable register 4 (00B416) 0 0 X 0 0 0 0 0 (114) Group 0 time measurement control register 5 (00DD16) 0016

(90) Interrupt enable register 5 (00B516) X X X 0 0 0 0 0 (115) Group 0 time measurement control register 6 (00DE16) 0016

(91) Interrupt enable register 6 (00B616) X X X 0 0 0 0 0 (116) Group 0 time measurement control register 7 (00DF16) 0016

x : Nothing is mapped to this bit

? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.

Figure 1.4.3. Device's internal status after a reset is cleared (2/10)

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Reset

(117) Group 0 base timer register (00E016) ??16 (144) Group 1 time measurement/waveform (010416) ??16
generate register 2
(00E116) ??16 (010516) ??16

(118) Group 0 base timer control register 0 (00E216) 0016 (145) Group 1 time measurement/waveform (010616) ??16
generate register 3
(119) Group 0 base timer control register 1 (00E316) 0016 (010716) ??16

(120) Group 0 time measurement prescaler register 6 (00E416) 0016 (146) Group 1 time measurement/waveform (010816) ??16
generate register 4
(121) Group 0 time measurement prescaler register 7 (00E516) 0016 (010916) ??16

(122) Group 0 function enable register (00E616) 0016 (147) Group 1 time measurement/waveform (010A16) ??16
generate register 5
(123) Group 0 function select register (00E716) 0016 (010B16) ??16

(124) Group 0 SI/O receive buffer register (00E816) ??16 (148) Group 1 time measurement/waveform (010C16) ??16
generate register 6
(00E916) X 0 0 0 X X X X (010D16) ??16

(125) Group 0 transmit buffer/receive data register (00EA16) ??16 (149) Group 1 time measurement/waveform (010E16) ??16
generate register 7
(126) Group 0 receive input register (00EC16) ??16 (010F16) ??16

(127) Group 0 SI/O communication mode register (00ED16) 0016 (150) Group 1 waveform generate control register 0 (011016) 0 X 0 0 X 0 0 0

(128) Group 0 transmit output register (00EE16) ??16 (151) Group 1 waveform generate control register 1 (011116) 0 X 0 0 X 0 0 0

(129) Group 0 SI/O communication control register (00EF16) 0 0 0 0 X 0 1 1 (152) Group 1 waveform generate control register 2 (011216) 0 X 0 0 X 0 0 0

(130) Group 0 data compare register 0 (00F016) ??16 (153) Group 1 waveform generate control register 3 (011316) 0 X 0 0 X 0 0 0

(131) Group 0 data compare register 1 (00F116) ??16 (154) Group 1 waveform generate control register 4 (011416) 0 X 0 0 X 0 0 0

(132) Group 0 data compare register 2 (00F216) ??16 (155) Group 1 waveform generate control register 5 (011516) 0 X 0 0 X 0 0 0

(133) Group 0 data compare register 3 (00F316) ??16 (156) Group 1 waveform generate control register 6 (011616) 0 X 0 0 X 0 0 0

(134) Group 0 data mask register 0 (00F416) ??16 (157) Group 1 waveform generate control register 7 (011716) 0 X 0 0 X 0 0 0

(135) Group 0 data mask register 1 (00F516) ??16 (158) Group 1 time measurement control register 1 (011916) 0016

(136) Group 0 receive CRC code register (00F816) ??16 (159) Group 1 time measurement control register 2 (011A16) 0016

(00F916) ??16 (160) Group 1 time measurement control register 6 (011E16) 0016

(137) Group 0 transmit CRC code register (00FA16) 0016 (161) Group 1 time measurement control register 7 (011F16) 0016

(00FB16) 0016 (162) Group 1 base timer register (012016) ??16

(138) Group 0 SI/O expansion mode register (00FC16) 0016 (012116) ??16

(139) Group 0 SI/O expansion receive control register (00FD16) 0016 (163) Group 1 base timer control register 0 (012216) 0016

(140) Group 0 SI/O special communication (00FE16) 0 0 0 0 0 0 X X (164) Group 1 base timer control register 1 (012316) 0016
interrupt detect register
(141) Group 0 SI/O expansion transmit (00FF16) 0 0 0 0 0 X X X
control register
(142) Group 1 time measurement/waveform (010016) ??16
generate register 0
(010116) ??16

(143) Group 1 time measurement/waveform (010216) ??16

generate register 1
(010316) ??16

x : Nothing is mapped to this bit

? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.

Figure 1.4.3. Device's internal status after a reset is cleared (3/10)

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Reset

(165) Group 1 time measurement prescaler register 6 (012416) 0016 (191) Group 2 waveform generate register 4 (014816) ??16

(166) Group 1 time measurement prescaler register 7 (012516) 0016 (014916) ??16

(167) Group 1 function enable register (012616) 0016 (192) Group 2 waveform generate register 5 (014A16) ??16

(168) Group 1 function select register (012716) 0016 (014B16) ??16

(169) Group 1 SI/O receive buffer register (012816) ??16 (193) Group 2 waveform generate register 6 (014C16) ??16

(012916) X 0 0 0 X X X X (014D16) ??16

(170) Group 1 transmit buffer/receive data register (012A16) ??16 (194) Group 2 waveform generate register 7 (014E16) ??16

(171) Group 1 receive input register (012C16) ??16 (014F16) ??16

(172) Group 1 SI/O communication mode register (012D16) 0016 (195) Group 2 waveform generate control register 0 (015016) 0016

(173) Group 1 transmit output register (012E16) ??16 (196) Group 2 waveform generate control register 1 (015116) 0016

(174) Group 1 SI/O communication control register (012F16) 0 0 0 0 X 0 1 1 (197) Group 2 waveform generate control register 2 (015216) 0016

(175) Group 1 data compare register 0 (013016) ??16 (198) Group 2 waveform generate control register 3 (015316) 0016

(176) Group 1 data compare register 1 (013116) ??16 (199) Group 2 waveform generate control register 4 (015416) 0016

(177) Group 1 data compare register 2 (013216) ??16 (200) Group 2 waveform generate control register 5 (015516) 0016

(178) Group 1 data compare register 3 (013316) ??16 (201) Group 2 waveform generate control register 6 (015616) 0016

(179) Group 1 data mask register 0 (013416) ??16 (202) Group 2 waveform generate control register 7 (015716) 0016

(180) Group 1 data mask register 1 (013516) ??16 (203) Group 2 base timer register (016016) ??16

(181) Group 1 receive CRC code register (013816) ??16 (016116) ??16

(013916) ??16 (204) Group 2 base timer control register 0 (016216) 0016

(182) Group 1 transmit CRC code register (013A16) 0016 (205) Group 2 base timer control register 1 (016316) 0016

(013B16) 0016 (206) Base timer start register (016416) X X X X 0 0 0 0

(183) Group 1 SI/O expansion mode register (013C16) 0016 (207) Group 2 function enable register (016616) 0016

(184) Group 1 SI/O expansion receive control register (013D16) 0016 (208) Group 2 RTP output buffer register (016716) 0016

(185) Group 1 SI/O special communication (013E16) 0 0 0 0 0 0 X X (209) Group 2 SI/O communication mode register (016A16) 0 0 XX X 0 0 0
interrupt detect register
(186) Group 1 SI/O expansion transmit control register (013F16) 0 0 0 0 0 X X X (210) Group 2 SI/O communication control register (016B16) 0 0 0 0 X 1 1 0

(187) Group 2 waveform generate register 0 (014016) ??16 (211) Group 2 SI/O transmit buffer register (016C16) ??16

(014116) ??16 (016D16) ? ? ? X X ? ? ?

(188) Group 2 waveform generate register 1 (014216) ??16 (212) Group 2 SI/O receive buffer register (016E16) ??16

(014316) ??16 (016F16) X XX ? X XX X

(189) Group 2 waveform generate register 2 (014416) ??16 (213) Group 2 IEBus address register (017016) ??16

(014516) ??16 (017116) X XXX ? ? ? ?

(190) Group 2 waveform generate register 3 (014616) ??16 (214) Group 2 IEBus control register (017216) 0 0 XX X 0 0 0

(014716) ??16

x : Nothing is mapped to this bit

? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.

Figure 1.4.3. Device's internal status after a reset is cleared (4/10)

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Reset

(215) Group 2 IEBus transmit interrupt (017316) X XX 0 0 0 0 0 (238) Group 3 waveform generate mask register 4 (019816) ??16
cause detect register
(216) Group 2 IEBus receive interrupt (017416) X XX 0 0 0 0 0 (019916) ??16
cause detect register
(217) Input function select register (017816) 0016 (239) Group 3 waveform generate mask register 5 (019A16) ??16

(218) Group 3 SI/O communication mode register (017A16) 0 0 XX 0 0 0 0 (019B16) ??16

(219) Group 3 SI/O communication control register (017B16) 0 0 ? 0 X ? ? 0 (240) Group 3 waveform generate mask register 6 (019C16) ??16

(220) Group 3 SI/O transmit buffer register (017C16) ??16 (019D16) ??16

(017D16) ??16 (241) Group 3 waveform generate mask register 7 (019E16) ??16

(221) Group 3 SI/O receive buffer register (017E16) ??16 (019F16) ??16

(017F16) ??16 (242) Group 3 base timer register (01A016) ??16

(222) Group 3 waveform generate register 0 (018016) ??16 (01A116) ??16

(018116) ??16 (243) Group 3 base timer control register 0 (01A216) 0016

(223) Group 3 waveform generate register 1 (018216) ??16 (244) Group 3 base timer control register 1 (01A316) 0 X X 0 X 0 0 0

(018316) ??16 (245) Group 3 function enable register (01A616) 0016

(224) Group 3 waveform generate register 2 (018416) ??16 (246) Group 3 RTP output buffer register (01A716) 0016

(018516) ??16 (247) Group 3 high-speed HDLC (01AB16) 0 0 X X X X X 0

communication control register 1
(225) Group 3 waveform generate register 3 (018616) ??16 (248) Group 3 high-speed HDLC (01AC16) 0016
communication control register
(018716) ??16 (249) Group 3 high-speed HDLC (01AD16) ??16
communication register
(226) Group 3 waveform generate register 4 (018816) ??16 (250) Group 3 high-speed HDLC transmit counter (01AE16) 0016

(018916) ??16 (01AF16) 0016

(227) Group 3 waveform generate register 5 (018A16) ??16 (251) Group 3 high-speed HDLC data (01B016) 0016
compare register 0
(018B16) ??16 (01B116) 0016

(228) Group 3 waveform generate register 6 (018C16) (252) Group 3 high-speed HDLC data (01B216) 0016
??16
mask register 0
(018D16) ??16 (01B316) 0016

(229) Group 3 waveform generate register 7 (018E16) ??16 (253) Group 3 high-speed HDLC data (01B416) 0016
compare register 1
(018F16) ??16 (01B516) 0016

(230) Group 3 waveform generate control register 0 (019016) 0016 (254) Group 3 high-speed HDLC data (01B616) 0016
mask register 1
(231) Group 3 waveform generate control register 1 (019116) 0016 (01B716) 0016

(232) Group 3 waveform generate control register 2 (019216) 0016 (255) Group 3 high-speed HDLC data (01B816) 0016
compare register 2
(233) Group 3 waveform generate control register 3 (019316) 0016 (01B916) 0016

(234) Group 3 waveform generate control register 4 (019416) 0016 (256) Group 3 high-speed HDLC data (01BA16) 0016
mask register 2
(235) Group 3 waveform generate control register 5 (019516) 0016 (01BB16) 0016

(236) Group 3 waveform generate control register 6 (019616) 0016 (257) Group 3 high-speed HDLC data (01BC16) 0016
compare register 3
(237) Group 3 waveform generate control register 7 (019716) 0016 (01BD16) 0016

x : Nothing is mapped to this bit

? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.

Figure 1.4.3. Device's internal status after a reset is cleared (5/10)

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Reset

(258) Group 3 high-speed HDLC data (01BE16) 0016 (282) CAN0 message slot buffer 0 data 6 (01EC16) ??16
mask register 3 (Note)
(01BF16) 0016 (283) CAN0 message slot buffer 0 data 7 (01ED16) ??16
(Note)
(259) A-D1 register 0 (01C016) ??16 (284) CAN0 message slot buffer 0 time stamp high (01EE16) ??16
(Note)
(01C116) ??16 (285) CAN0 message slot buffer 0 time stamp low (01EF16) ??16
(Note)
(260) A-D1 register 1 (01C216) ??16 (286) CAN1 message slot buffer 0 standard ID 0 (01F016) XX X ? ? ? ? ?
(Note)
(01C316) ??16 (287) CAN1 message slot buffer 0 standard ID 1 (01F116) XX ? ? ? ? ? ?
(Note)
(261) A-D1 register 2 (01C416) ??16 (288) CAN1 message slot buffer 0 extended ID 0 (01F216) XX X X ? ? ? ?
(Note)
(01C516) ??16 (289) CAN1 message slot buffer 0 extended ID 1 (01F316) ??16
(Note)
(262) A-D1 register 3 (01C616) ??16 (290) CAN1 message slot buffer 0 extended ID 2 (01F416) XX ? ? ? ? ? ?
(Note)
(01C716) ??16 (291) CAN1 message slot buffer 0 data length code (01F516) XX X X ? ? ? ?
(Note)
(263) A-D1 register 4 (01C816) ??16 (292) CAN1 message slot buffer 0 data 0 (01F616) ??16
(Note)
(01C916) ??16 (293) CAN1 message slot buffer 0 data 1 (01F716) ??16
(Note)
(264) A-D1 register 5 (01CA16) ??16 (294) CAN1 message slot buffer 0 data 2 (01F816) ??16
(Note)
(01CB16) ??16 (295) CAN1 message slot buffer 0 data 3 (01F916) ??16
(Note)
(265) A-D1 register 6 (01CC16) ??16 (296) CAN1 message slot buffer 0 data 4 (01FA16) ??16
(Note)
(01CD16) ??16 (297) CAN1 message slot buffer 0 data 5 (01FB16) ??16
(Note)
(266) A-D1 register 7 (01CE16) ??16 (298) CAN1 message slot buffer 0 data 6 (01FC16) ??16
(Note)
(01CF16) ??16 (299) CAN1 message slot buffer 0 data 7 (01FD16) ??16
(Note)
(267) A-D1 control register 2 (01D416) X 0 0 X X 0 0 0 (300) CAN1 message slot buffer 0 time stamp high (01FE16) ??16
(Note)
(268) A-D1 control register 0 (01D616) 0016 (301) CAN1 message slot buffer 0 time stamp low (01FF16) ??16
(Note)
(269) A-D1 control register 1 (01D716) XX 0 0 0 0 0 0 (302) CAN0 control register 0 (020016) X X 0 1 0 X 0 1
(Note)
(270) CAN0 message slot buffer 0 standard ID 0 (01E016) XX X ? ? ? ? ? (020116) XXXX 0 0 0 0
(Note)
(271) CAN0 message slot buffer 0 standard ID 1 (01E116) XX ? ? ? ? ? ? (303) CAN0 status register (020216) 0016
(Note) (Note)
(272) CAN0 message slot buffer 0 extended ID 0 (01E216) XX X X ? ? ? ? (020316) X 0 0 0 0 X 0 1
(Note)
(273) CAN0 message slot buffer 0 extended ID 1 (01E316) ??16 (304) CAN0 expansion ID register (020416) 0016
(Note) (Note)
(274) CAN0 message slot buffer 0 extended ID 2 (01E416) XX ? ? ? ? ? ? (020516) 0016
(Note)
(275) CAN0 message slot buffer 0 data length code (01E516) XX X X ? ? ? ? (305) CAN0 configuration register (020616) 0 0 0 0 X XXX
(Note) (Note)
(276) CAN0 message slot buffer 0 data 0 (01E616) ??16 (020716) 0016
(Note)
(277) CAN0 message slot buffer 0 data 1 (01E716) ??16 (306) CAN0 time stamp register (020816) 0016
(Note) (Note)
(278) CAN0 message slot buffer 0 data 2 (01E816) ??16 (020916) 0016
(Note)
(279) CAN0 message slot buffer 0 data 3 (01E916) ??16 (307) CAN0 transmit error count register (020A16) 0016
(Note) (Note)
(280) CAN0 message slot buffer 0 data 4 (01EA16) ??16 (308) CAN0 receive error count register (020B16) 0016
(Note) (Note)
(281) CAN0 message slot buffer 0 data 5 (01EB16) ??16
(Note)

x : Nothing is mapped to this bit

? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 024216) to 1 after reset.

Figure 1.4.3. Device's internal status after a reset is cleared (6/10)

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Reset

(309) CAN0 slot interrupt status register (020C16) 0016 (339) X0 register/Y0 register (02C016) ??16
(Note)
(020D16) 0016 (02C116) ??16

(310) CAN0 slot interrupt mask register (021016) 0016 (340) X1 register/Y1 register (02C216) ??16
(Note)
(021116) 0016 (02C316) ??16

(311) CAN0 error interrupt mask register (021416) XXX X X 0 0 0 (341) X2 register/Y2 register (02C416) ??16
(Note)
(312) CAN0 error interrupt status register (021516) XXX X X 0 0 0 (02C516) ??16
(Note)
(313) CAN0 baud rate prescaler (021716) 0116 (342) X3 register/Y3 register (02C616) ??16
(Note)
(314) CAN0 global mask register standard ID0 (022816) XXX 0 0 0 0 0 (02C716) ??16
(Note)
(315) CAN0 global mask register standard ID1 (022916) XX 0 0 0 0 0 0 (343) X4 register/Y4 register (02C816) ??16
(Note)
(316) CAN0 global mask register extended ID0 (022A16) ??16 (02C916) ??16
(Note)
(317) CAN0 global mask register extended ID1 (022B16) ??16 (344) X5 register/Y5 register (02CA16) ??16
(Note)
(318) CAN0 global mask register extended ID2 (022C16) ??16 (02CB16) ??16
(Note)
(319) CAN0 message slot 0 control register / (023016) XXX 0 0 0 0 0 (345) X6 register/Y6 register (02CC16) ??16
CAN0 local mask register A standard ID0 (Note)
(320) CAN0 message slot 1 control register / (023116) XX 0 0 0 0 0 0 (02CD16) ??16
CAN0 local mask register A standard ID1 (Note)
(321) CAN0 message slot 2 control register / (023216) 0016 (346) X7 register/Y7 register (02CE16) ??16
CAN0 local mask register A extended ID0 (Note)
(322) CAN0 message slot 3 control register / (023316) 0016 (02CF16) ??16
CAN0 local mask register A extended ID1 (Note)
(323) CAN0 message slot 4 control register / (023416) 0016 (347) X8 register/Y8 register (02D016) ??16
CAN0 local mask register A extended ID2 (Note)
(324) CAN0 message slot 5 control register (023516) 0016 (02D116) ??16
(Note)
(325) CAN0 message slot 6 control register (023616) 0016 (348) X9 register/Y9 register (02D216) ??16
(Note)
(326) CAN0 message slot 7 control register (023716) 0016 (02D316) ??16
(Note)
(327) CAN0 message slot 8 control register / (023816) XXX 0 0 0 0 0 (349) X10 register/Y10 register (02D416) ??16
CAN0 local mask register B standard ID0 (Note)
(328) CAN0 message slot 9 control register / (023916) XX 0 0 0 0 0 0 (02D516) ??16
CAN0 local mask register B standard ID1 (Note)
(329) CAN0 message slot 10 control register / (023A16) 0016 (350) X11 register/Y11 register (02D616) ??16
CAN0 local mask register B extended ID0 (Note)
(330) CAN0 message slot 11 control register / (023B16) 0016 (02D716) ??16
CAN0 local mask register B extended ID1 (Note)
(331) CAN0 message slot 12 control register / (023C16) 0016 (351) X12 register/Y12 register (02D816) ??16
CAN0 local mask register B extended ID2 (Note)
(332) CAN0 message slot 13 control register (023D16) 0016 (02D916) ??16
(Note)
(333) CAN0 message slot 14 control register (023E16) 0016 (352) X13 register/Y13 register (02DA16) ??16
(Note)
(334) CAN0 message slot 15 control register (023F16) 0016 (02DB16) ??16
(Note)
(335) CAN0 slot buffer select register (024016) 0016 (353) X14 register/Y14 register (02DC16) ??16
(Note)
(336) CAN0 control register 1 (024116) XX 0 0 0 0 X X (02DD16) ??16
(Note)
(337) CAN0 sleep control register (024216) XX X X XX X 0 (354) X15 register/Y15 register (02DE16) ??16
(Note)
(338) CAN0 acceptance filter support register (024416) 0016 (02DF16) ??16
(Note)
(024516) 0116 (355) XY control register (02E016) XX XX XX 0 0

x : Nothing is mapped to this bit

? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 024216) to 1 after reset.

Figure 1.4.3. Device's internal status after a reset is cleared (7/10)

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Reset

(356) UART1 special mode register 4 (02E416) 0016 (382) Three-phase output buffer register 0 (030A16) X X 0 0 0 0 0 0

(357) UART1 special mode register 3 (02E516) 0016 (383) Three-phase output buffer register 1 (030B16) X X 0 0 0 0 0 0

(358) UART1 special mode register 2 (02E616) 0016 (384) Dead time timer (030C16) ??16

(359) UART1 special mode register (02E716) 0016 (385) Timer B2 interrupt occurrence (030D16) XXX X ? ? ? ?
frequency set counter
(360) UART1 transmit-receive mode register (02E816) 0016 (386) Timer B3 register (031016) ??16

(361) UART1 bit rate generator (02E916) ??16 (031116) ??16

(362) UART1 transmit buffer register (02EA16) ??16 (387) Timer B4 register (031216) ??16

(02EB16) XXX X XX X ? (031316) ??16

(363) UART1 transmit-receive control register 0 (02EC16) 0816 (388) Timer B5 register (031416) ??16

(364) UART1 transmit-receive control register 1 (02ED16) 0216 (031516) ??16

(365) UART1 receive buffer register (02EE16) ??16 (389) Timer B3 mode register (031B16) 0 0 ? X 0 0 0 0

(02EF16) ? ? ? ? ? XX ? (390) Timer B4 mode register (031C16) 0 0 ? X 0 0 0 0

(366) UART4 special mode register 4 (02F416) 0016 (391) Timer B5 mode register (031D16) 0 0 ? 0 0 0 0 0

(367) UART4 special mode register 3 (02F516) 0016 (392) External interrupt cause select register (031F16) 0016

(368) UART4 special mode register 2 (02F616) 0016 (393) UART3 special mode register 4 (032416) 0016

(369) UART4 special mode register (02F716) 0016 (394) UART3 special mode register 3 (032516) 0016

(370) UART4 transmit-receive mode register (02F816) 0016 (395) UART3 special mode register 2 (032616) 0016

(371) UART4 bit rate generator (02F916) ??16 (396) UART3 special mode register (032716) 0016

(372) UART4 transmit buffer register (02FA16) ??16 (397) UART3 transmit-receive mode register (032816) 0016

(02FB16) XXX X XX X ? (398) UART3 bit rate generator (032916) ??16

(373) UART4 transmit-receive control register 0 (02FC16) 0816 (399) UART3 transmit buffer register (032A16) ??16

(374) UART4 transmit-receive control register 1 (02FD16) 0216 (032B16) XXX XX X X ?

(375) UART4 receive buffer register (02FE16) ??16 (400) UART3 transmit-receive control register 0 (032C16) 0816

(02FF16) ? ? ? ? ? XX ? (401) UART3 transmit-receive control register 1 (032D16) 0216

(376) Timer B3,B4,B5 count start flag (030016) 0 0 0 X XX XX (402) UART3 receive buffer register (032E16) ??16

(377) Timer A1-1 register (030216) ??16 (032F16) ? ? ? ? ? X X ?

(030316) ??16 (403) UART2 special mode register 4 (033416) 0016

(378) Timer A2-1 register (030416) ??16 (404) UART2 special mode register 3 (033516) 0016

(030516) ??16 (405) UART2 special mode register 2 (033616) 0016

(379) Timer A4-1 register (030616) ??16 (406) UART2 special mode register (033716) 0016

(030716) ??16 (407) UART2 transmit-receive mode register (033816) 0016

(380) Three-phase PWM control register 0 (030816) 0016 (408) UART2 bit rate generator (033916) ??16

(381) Three-phase PWM control register 1 (030916) 0016

x : Nothing is mapped to this bit

? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.

Figure 1.4.3. Device's internal status after a reset is cleared (8/10)

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Reset

(409) UART2 transmit buffer register (033A16) ??16 (432) Timer B1 mode register (035C16) 0 0 ? X 0 0 0 0

(033B16) XXX X XX X ? (433) Timer B2 mode register (035D16) 0 0 ? X 0 0 0 0

(410) UART2 transmit/receive control register 0 (033C16) 0816 (434) Timer B2 special mode register (035E16) XXX X X X X 0

(411) UART2 transmit/receive control register 1 (033D16) 0216 (435) Count source prescaler register (035F16) 0 XXX 0 0 0 0

(412) UART2 receive buffer register (033E16) ??16 (436) UART0 pecial mode register 4 (036416) 0016

(033F16) ? ? ? ? ? X X ? (437) UART0 special mode register 3 (036516) 0016

(413) Count start flag (034016) 0016 (438) UART0 special mode register 2 (036616) 0016

(414) Clock prescaler reset flag (034116) 0 X X XXX XX (439) UART0 special mode register (036716) 0016

(415) One-shot start flag (034216) 0016 (440) UART0 transmit/receive mode register (036816) 0016

(416) Trigger select register (034316) 0016 (441) UART0 bit rate generator (036916) ??16

(417) Up-down flag (034416) 0016 (442) UART0 transmit buffer register (036A16) ??16

(418) Timer A0 (034616) ??16 (036B16) X XXX XXX ?

(034716) ??16 (443) UART0 transmit/receive control register 0 (036C16) 0816

(419) Timer A1 (034816) ??16 (444) UART0 transmit/receive control register 1 (036D16) 0216

(034916) ??16 (445) UART0 receive buffer register (036E16) ??16

(420) Timer A2 (034A16) ??16 (036F16) ? ? ? ? ? X X ?

(034B16) ??16 (446) PLL control register 0 (037616) 0 0 1 1 0 1 0 0

(421) Timer A3 (034C16) ??16 (447) DMA0 cause select register (037816) 0 X 0 0 0 0 0 0

(034D16) ??16 (448) DMA1 cause select register (037916) 0 X 0 0 0 0 0 0

(422) Timer A4 (034E16) ??16 (449) DMA2 cause select register (037A16) 0 X 0 0 0 0 0 0

(034F16) ??16 (450) DMA3 cause select register (037B16) 0 X 0 0 0 0 0 0

(423) Timer B0 (035016) ??16 (451) CRC data register (037C16) ??16

(035116) ??16 (037D16) ??16

(424) Timer B1 (035216) ??16 (452) CRC input register (037E16) ??16

(035316) ??16 (453) A-D0 register 0 (038016) ??16

(425) Timer B2 (035416) ??16 (038116) ??16

(035516) ??16 (454) A-D0 register 1 (038216) ??16

(426) Timer A0 mode register (035616) 0 0 0 0 0 X 0 0 (038316) ??16

(427) Timer A1 mode register (035716) 0 0 0 0 0 X 0 0 (455) A-D0 register 2 (038416) ??16

(428) Timer A2 mode register (035816) 0 0 0 0 0 X 0 0 (038516) ??16

(429) Timer A3 mode register (035916) 0 0 0 0 0 X 0 0 (456) A-D0 register 3 (038616) ??16

(430) Timer A4 mode register (035A16) 0 0 0 0 0 X 0 0 (038716) ??16

(431) Timer B0 mode register (035B16) 0 0 ? 0 0 0 0 0

x : Nothing is mapped to this bit

? : Undefined

The content of other registers and RAM are undefined when the microcomputer is reset. The initial values must therefore be set.

Figure 1.4.3. Device's internal status after a reset is cleared (9/10)

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Reset

(457) A-D0 register 4 (038816) ??16 (486) Port P9 (03C516) ??16

(038916) ??16 (487) Port P8 direction register (03C616) 0 0 X 0 0 0 0 0

(458) A-D0 register 5 (038A16) ??16 (488) Port P9 direction register (03C716) 0016

(038B16) ??16 (489) Port P10 (03C816) ??16

(459) A-D0 register 6 (038C16) ??16 (490) Port P11 (Note) (03C916) XXX ? ? ? ? ?

(038D16) ??16 (491) Port P10 direction register (Note) (03CA16) 0016

(460) A-D0 register 7 (038E16) ??16 (492) Port P11 direction register (Note) (03CB16) XXX 0 0 0 0 0

(038F16) ??16 (493) Port P12 (Note) (03CC16) ??16

(461) A-D0 control register 2 (039416) X 0 0 0 0 0 0 0 (494) Port P13 (Note) (03CD16) ??16

(462) A-D0 control register 0 (039616) 0016 (495) Port P12 direction register (Note) (03CE16) 0016

(463) A-D0 control register 1 (039716) 0016 (496) Port P13 direction register (Note) (03CF16) 0016

(464) D-A register 0 (039816) ??16 (497) Port P14 (Note) (03D016) X ? ? ? ? ? ? ?

(465) D-A register 1 (039A16) ??16 (498) Port P15 (Note) (03D116) ??16

(466) D-A control register (039C16) XXXX XX 0 0 (499) Port P14 direction register (Note) (03D216) X 0 0 0 0 0 0 0

(467) Function select register A8 (Note) (03A016) XXXX 0 0 0 0 (500) Port P15 direction register (Note) (03D316) 0016

(468) Function select register A9 (Note) (03A116) 0016 (501) Pull-up control register 2 (03DA16) 0016

(469) Function select register C (03AF16) 0 0 X 0 0 0 0 0 (502) Pull-up control register 3 (03DB16) 0016

(470) Function select register A0 (03B016) 0016 (503) Pull-up control register 4 (Note) (03DC16) XX XX 0 0 0 0

(471) Function select register A1 (03B116) 0016 (504) Port P0 (03E016) ??16

(472) Function select register B0 (03B216) 0016 (505) Port P1 (03E116) ??16

(473) Function select register B1 (03B316) 0016 (506) Port P0 direction register (03E216) 0016

(474) Function select register A2 (03B416) XX XXX 0 0 0 (507) Port P1 direction register (03E316) 0016

(475) Function select register A3 (03B516) 0016 (508) Port P2 (03E416) ??16

(476) Function select register B2 (03B616) XX XXX 0 0 0 (509) Port P3 (03E516) ??16

(477) Function select register B3 (03B716) 0016 (510) Port P2 direction register (03E616) 0016

(478) Function select register A5 (Note) (03B916) XX XX 0 0 0 0 (511) Port P3 direction register (03E716) 0016

(479) Function select register A6 (Note) (03BC16) 0016 (512) Port P4 (03E816) ??16

(480) Function select register A7 (Note) (03BD16) 0016 (513) Port P5 (03E916) ??16

(481) Port P6 (03C016) ??16 (514) Port P4 direction register (03EA16) 0016

(482) Port P7 (03C116) ??16 (515) Port P5 direction register (03EB16) 0016

(483) Port P6 direction register (03C216) 0016 (516) Pull-up control register 0 (03F016) 0016

(484) Port P7 direction register (03C316) 0016 (517) Pull-up control register 1 (03F116) XX XX 0 0 0 0

(485) Port P8 (03C416) ??16 (518) Port control register (03FF16) XX XX X XX 0

x : Nothing is mapped to this bit

? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note :This register exists in 144-pin version.

Figure 1.4.3. Device's internal status after a reset is cleared (10/10)

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SFR

SFR
Address Register Address Register
000016 003016 ROM area set register ROA *
000116 003116 Debug moritor area set register DBA *
000216 003216 Expansion area set register 0 EXA0 *
000316 003316 Expansion area set register 1 EXA1 *
000416 Processor mode register 0 PM0 003416 Expansion area set register 2 EXA2 *
000516 Processor mode register 1 PM1 003516 Expansion area set register 3 EXA3 *
000616 System clock control register 0 CM0 003616
000716 System clock control register 1 CM1 003716
000816 Wait control register WCR 003816
000916 Address match interrupt control register AIER 003916
000A16 Protect register PRCR 003A16
000B16 External data bus width control register DS 003B16
000C16 Main clock divided register MCD 003C16
000D16 Oscillation stop detect register CM2 003D16
000E16 Watchdog timer start register WDTS 003E16
000F16 Watchdog timer control register WDC 003F16
001016 004016 DRAM control register DRAMCONT
001116 Address match interrupt register 0 RMAD0 004116 DRAM refresh interval set register REFCNT
001216 004216
001316 004316
001416 004416
001516 Address match interrupt register 1 RAMD1 004516
001616 004616
001716 VDC control register for PLL PLV 004716
001816 004816
001916 Address match interrupt register 2 RAMD2 004916
001A16 004A16
001B16 VDC control register 1 VDC1 * 004B16
001C16 004C16
001D16 Address match interrupt register 3 RAMD3 004D16
001E16 004E16
001F16 VDC control register 0 VDC0 * 004F16
002016 005016
002116 Emulator interrupt vector table register EIAD0 * 005116
002216 005216
002316 Emulator interrupt detect register EITD * 005316
002416 Emulator protect register EPRR * 005416
002516 005516 Flash memory control register 2 FMR2 *
002616 005616 Flash memory control register 1 FMR1 *
002716 005716 Flash memory control register 0 FMR0
002816 005816
002916 005916
002A16 005A16
002B16 005B16
002C16 005C16
002D16 005D16
002E16 005E16
002F16 005F16

The blank area is reserved and cannot be used by user.

*: User cannot use this. Do not access to the register.

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SFR

Address Register Address Register

006016 009016 UART0 transmit /NACK interrupt control register S0TIC
006116 009116 UART1/UART4 bus collision detection interrupt control register BCN1IC
006216 009216 UART1 transmit/NACK interruptcontrol register S1TIC
006316 009316 Key input interrupt control register KUPIC
006416 009416 Timer B0 interrupt control register TB0IC
006516 009516 Intelligent I/O interrupt control register 1 IIO1IC
006616 009616 Timer B2 interrupt control register TB2IC
006716 009716 Intelligent I/O interrupt control register 3 IIO3IC
006816 DMA0 interrupt control register DM0IC 009816 Timer B4 interrupt control register TB4IC
006916 Timer B5 interrupt control register TB5IC 009916 Intelligent I/O interrupt control register 5 IIO5IC
006A16 DMA2 interrupt control register DM2IC 009A16 INT4 interrupt control register INT4IC
006B16 UART2 receive /ACK interrupt control register S2RIC 009B16 Intelligent I/O interrupt control register 7 IIO7IC
006C16 Timer A0 interrupt control register TA0IC 009C16 INT2 interrupt control register INT2IC
006D16 UART3 receive /ACK interrupt control register S3RIC 009D16 Intelligent I/O interrupt control register 9/ IIO9IC
006E16 Timer A2 interrupt control register TA2IC CAN interrupt 0 control register CAN0ICI
006F16 UART4 receive /ACK interrupt control register S4RIC 009E16 INT0 interrupt control register INT0IC
007016 Timer A4 interrupt control register TA4IC 009F16 Exit priority register RLVL
007116 UART0/UART3 bus collision detection interrupt control register BCN0IC 00A016 Interrupt request register 0 IIO0IR
007216 UART0 receive/ACK interrupt control register S0RIC 00A116 Interrupt request register 1 IIO1IR
007316 A-D0 interrupt control register AD0IC 00A216 Interrupt request register 2 IIO2IR
007416 UART1 receive/ACK interrupt control register S1RIC 00A316 Interrupt request register 3 IIO3IR
007516 Intelligent I/O interrupt control register 0 IIO0IC 00A416 Interrupt request register 4 IIO4IR
007616 Timer B1 interrupt control register TB1IC 00A516 Interrupt request register 5 IIO5IR
007716 Intelligent I/O interrupt control register 2 IIO2IC 00A616 Interrupt request register 6 IIO6IR
007816 Timer B3 interrupt control register TB3IC 00A716 Interrupt request register 7 IIO7IR
007916 Intelligent I/O interrupt control register 4 IIO4IC 00A816 Interrupt request register 8 IIO8IR
007A16 INT5 interrupt control register INT5IC 00A916 Interrupt request register 9 IIO9IR
007B16 Intelligent I/O interrupt control register 6 IIO6IC 00AA16 Interrupt request register 10 IIO10IR
007C16 INT3 interrupt control register INT3IC 00AB16 Interrupt request register 11 IIO11IR
007D16 Intelligent I/O interrupt control register 8 IIO8IC 00AC16
007E16 INT1 interrupt control register INT1IC 00AD16
007F16 Intelligent I/O interrupt control register 10/ IIO10IC 00AE16
CAN interrupt 1 control register CAN1ICI 00AF16
008016 00B016 Interrupt enable register 0 IIO0IE
008116 Intelligent I/O interrupt control register 11/ IIO11IC 00B116 Interrupt enable register 1 IIO1IE
CAN interrupt 2 control register CAN2IC 00B216 Interrupt enable register 2 IIO2IE
008216 00B316 Interrupt enable register 3 IIO3IE
008316 00B416 Interrupt enable register 4 IIO4IE
008416 00B516 Interrupt enable register 5 IIO5IE
008516 00B616 Interrupt enable register 6 IIO6IE
008616 A-D1 interrupt control register AD1IC 00B716 Interrupt enable register 7 IIO7IE
008716 00B816 Interrupt enable register 8 IIO8IE
008816 DMA1 interrupt control register DM1IC 00B916 Interrupt enable register 9 IIO9IE
008916 UART2 transmit /NACK interrupt control register S2TIC 00BA16 Interrupt enable register 10 IIO10IE
008A16 DMA3 interrupt control register DM3IC 00BB16 Interrupt enable register 11 IIO11IE
008B16 UART3 transmit /NACK interrupt control register S3TIC 00BC16
008C16 Timer A1 interrupt control register TA1IC 00BD16
008D16 UART4 transmit /NACK interrupt control register S4TIC 00BE16
008E16 Timer A3 interrupt control register TA3IC 00BF16
008F16 UART2 bus collision detection interrupt control register BCN2IC

The blank area is reserved and cannot be used by user.

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SFR

Address Register Address Register

00C016 00F016 Group 0 data compare register 0 G0CMP0
Group 0 TM /WG register 0 G0TM0/G0PO0
00C116 00F116 Group 0 data compare register 1 G0CMP1
00C216 00F216 Group 0 data compare register 2 G0CMP2
Group 0 TM /WG register 1 G0TM1/G0PO1
00C316 00F316 Group 0 data compare register 3 G0CMP3
00C416 00F416 Group 0 data mask register 0 G0MSK0
Group 0 TM /WG register 2 G0TM2/G0PO2
00C516 00F516 Group 0 data mask register 1 G0MSK1
00C616 00F616
Group 0 TM /WG register 3 G0TM3/G0PO3
00C716 00F716
00C816 00F816
Group 0 TM /WG register 4 G0TM4/G0PO4 Group 0 receive CRC code register G0RCRC
00C916 00F916
00CA16 00FA16
Group 0 TM /WG register 5 G0TM5/G0PO5 Group 0 transmit CRC code register G0TCRC
00CB16 00FB16
00CC16 00FC16 Group 0 SI/O expansion mode register G0EMR
Group 0 TM /WG register 6 G0TM6/G0PO6
00CD16 00FD16 Group 0 SI/O expansion receive control register G0ERC
00CE16 00FE16 Group 0 SI/O special communication interrupt detect register G0IRF
Group 0 TM /WG register 7 G0TM7/G0PO7
00CF16 00FF16 Group 0 SI/O expansion transmit control register G0ETC
00D016 Group 0 waveform generate control register 0 G0POCR0 010016
00D116 Group 0 waveform generate control register 1 G0POCR1 Group 1 TM /WG register 0 G1TM0/G1PO0
010116
00D216 010216
00D316 Group 1 TM /WG register 1 G1TM1/G1PO1
010316
00D416 Group 0 waveform generate control register 4 G0POCR4 010416
00D516 Group 0 waveform generate control register 5 G0POCR5 Group 1 TM /WG register 2 G1TM2/G1PO2
010516
00D616 010616
00D716 Group 1 TM /WG register 3 G1TM3/G1PO3
010716
00D816 Group 0 time measurement control register 0 G0TMCR0 010816
00D916 Group 0 time measurement control register 1 G0TMCR1 Group 1 TM /WG register 4 G1TM4/G1PO4
010916
00DA16 Group 0 time measurement control register 2 G0TMCR2 010A16
00DB16 Group 0 time measurement control register 3 G0TMCR3 Group 1 TM /WG register 5 G1TM5/G1PO5
010B16
00DC16 Group 0 time measurement control register 4 G0TMCR4 010C16
00DD16 Group 0 time measurement control register 5 G0TMCR5 Group 1 TM /WG register 6 G1TM6/G1PO6
010D16
00DE16 Group 0 time measurement control register 6 G0TMCR6 010E16
00DF16 Group 0 time measurement control register 7 G0TMCR7 Group 1 TM /WG register 7 G1TM7/G1PO7
010F16
00E016 011016 Group 1 waveform generate control register 0 G1POCR0
Group 0 base timer register G0BT
00E116 011116 Group 1 waveform generate control register 1 G1POCR1
00E216 Group 0 base timer control register 0 G0BCR0 011216 Group 1 waveform generate control register 2 G1POCR2
00E316 Group 0 base timer control register 1 G0BCR1 011316 Group 1 waveform generate control register 3 G1POCR3
00E416 Group 0 time measurement prescaler register 6 G0TPR6 011416 Group 1 waveform generate control register 4 G1POCR4
00E516 Group 0 time measurement prescaler register 7 G0TPR7 011516 Group 1 waveform generate control register 5 G1POCR5
00E616 Group 0 function enable register G0FE 011616 Group 1 waveform generate control register 6 G1POCR6
00E716 Group 0 function select register G0FS 011716 Group 1 waveform generate control register 7 G1POCR7
00E816 011816
Group 0 SI/O receive buffer register G0BF
00E916 011916 Group 1 time measurement control register 1 G1TMCR1
00EA16 Group 0 transmit buffer/receive data register G0DR 011A16 Group 1 time measurement control register 2 G1TMCR2
00EB16 011B16
00EC16 Group 0 receive input register G0RI 011C16
00ED16 Group 0 SI/O communication mode register G0MR 011D16
00EE16 Group 0 transmit output register G0TO 011E16 Group 1 time measurement control register 6 G1TMCR6
00EF16 Group 0 SI/O communication control register G0CR 011F16 Group 1 time measurement control register 7 G1TMCR7

The blank area is reserved and cannot be used by user.

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M32C/83 group
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SFR

Address Register Address Register

012016 015016 Group 2 waveform generate control register 0 G2POCR0
Group 1 base timer register G1BT 015116 Group 2 waveform generate control register 1 G2POCR1
012116
012216 Group 1 base timer control register 0 G1BCR0 015216 Group 2 waveform generate control register 2 G2POCR2
012316 Group 1 base timer control register 1 G1BCR1 015316 Group 2 waveform generate control register 3 G2POCR3
012416 Group 1 time measurement prescaler register 6 G1TPR6 015416 Group 2 waveform generate control register 4 G2POCR4
012516 Group 1 time measurement prescaler register 7 G1TPR7 015516 Group 2 waveform generate control register 5 G2POCR5
012616 Group 1 function enable register G1FE 015616 Group 2 waveform generate control register 6 G2POCR6
012716 Group 1 function select register G1FS 015716 Group 2 waveform generate control register 7 G2POCR7
012816 015816
Group 1 SI/O receive buffer register G1BF 015916
012916
012A16 Group 1 transmit buffer/receive data register G1DR 015A16
012B16 015B16
012C16 Group 1 receive input register G1RI 015C16
012D16 Group 1 SI/O communication mode register G1MR 015D16
012E16 Group 1 transmit output register G1TO 015E16
012F16 Group 1 SI/O communication control register G1CR 015F16
013016 Group 1 data compare register 0 G1CMP0 016016
Group 2 base timer register G2BT
013116 Group 1 data compare register 1 G1CMP1 016116
013216 Group 1 data compare register 2 G1CMP2 016216 Group 2 base timer control register 0 G2BCR0
013316 Group 1 data compare register 3 G1CMP3 016316 Group 2 base timer control register 1 G2BCR1
013416 Group 1 data mask register 0 G1MSK0 016416 Base timer start register BTSR
013516 Group 1 data mask register 1 G1MSK1 016516
013616 016616 Group 2 function enable register G2FE
013716 016716 Group 2 RTP output buffer register G2RTP
013816 016816
Group 1 receive CRC code register G1RCRC 016916
013916
013A16 016A16 Group 2 SI/O communication mode register G2MR
Group 1 transmit CRC code register G1TCRC 016B16 Group 2 SI/O communication control register G2CR
013B16
013C16 Group 1 SI/O expansion mode register G1EMR 016C16
Group 2 SI/O transmit buffer register G2TB
013D16 Group 1 SI/O expansion receive control register G1ERC 016D16
013E16 Group 1 SI/O special communication interrupt detect register G1IRF 016E16
Group 2 SI/O receive buffer register G2RB
013F16 Group 1 SI/O expansion transmit control register G1ETC 016F16
014016 017016
Group 2 waveform generate register 0 G2PO0 Group 2 IEBus address register IEAR
014116 017116
014216 017216 Group 2 IEBus control register IECR
Group 2 waveform generate register 1 G2PO1 017316 Group 2 IEBus transmit interrupt cause detect register IETIF
014316
014416 017416 Group 2 IEBus receive interrupt cause detect register IERIF
Group 2 waveform generate register 2 G2PO2 017516
014516
014616 017616
Group 2 waveform generate register 3 G2PO3 017716
014716
014816 017816 Input function select register IPS
Group 2 waveform generate register 4 G2PO4 017916
014916
014A16 017A16 Group 3 SI/O communication mode register G3MR
Group 2 waveform generate register 5 G2PO5 017B16 Group 3 SI/O communication control register G3CR
014B16
014C16 017C16
Group 2 waveform generate register 6 G2PO6 Group 3 SI/O transmit buffer register G3TB
014D16 017D16
014E16 017E16
Group 2 waveform generate register 7 G2PO7 Group 3 SI/O receive buffer register G3RB
014F16 017F16

The blank area is reserved and cannot be used by user.

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M32C/83 group
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SFR

Address Register Address Register

018016 01B016
Group 3 waveform generate register 0 G3PO0 Group 3 high-speed HDLC data compare register 0 HDLCCP0
018116 01B116
018216 01B216
Group 3 waveform generate register 1 G3PO1 Group 3 high-speed HDLC data mask register 0 HDLCMK0
018316 01B316
018416 01B416
Group 3 waveform generate register 2 G3PO2 Group 3 high-speed HDLC data compare register1 HDLCCP1
018516 01B516
018616 01B616
Group 3 waveform generate register 3 G3PO3 Group 3 high-speed HDLC data mask register 1 HDLCMK1
018716 01B716
018816 01B816
Group 3 waveform generate register 4 G3PO4 Group 3 high-speed HDLC data compare register 2 HDLCCP2
018916 01B916
018A16 01BA16
Group 3 waveform generate register 5 G3PO5 Group 3 high-speed HDLC data mask register 2 HDLCMK2
018B16 01BB16
018C16 01BC16
Group 3 waveform generate register 6 G3PO6 Group 3 high-speed HDLC data compare register 3 HDLCCP3
018D16 01BD16
018E16 01BE16
Group 3 waveform generate register 7 G3PO7 Group 3 high-speed HDLC data mask register 3 HDLCMK3
018F16 01BF16
019016 Group 3 waveform generate control register 0 G3POCR0 01C016
A-D1 register 0 AD10
019116 Group 3 waveform generate control register 1 G3POCR1 01C116
019216 Group 3 waveform generate control register 2 G3POCR2 01C216
A-D1 register 1 AD11
019316 Group 3 waveform generate control register 3 G3POCR3 01C316
019416 Group 3 waveform generate control register 4 G3POCR4 01C416
A-D1 register 2 AD12
019516 Group 3 waveform generate control register 5 G3POCR5 01C516
019616 Group 3 waveform generate control register 6 G3POCR6 01C616
A-D1 register 3 AD13
019716 Group 3 waveform generate control register 7 G3POCR7 01C716
019816 01C816
Group 3 waveform generate mask register 4 G3MK4 A-D1 register 4 AD14
019916 01C916
019A16 01CA16
Group 3 waveform generate mask register 5 G3MK5 A-D1 register 5 AD15
019B16 01CB16
019C16 01CC16
Group 3 waveform generate mask register 6 G3MK6 A-D1 register 6 AD16
019D16 01CD16
019E16 01CE16
Group 3 waveform generate mask register 7 G3MK7 A-D1 register 7 AD17
019F16 01CF16
01A016 01D016
Group 3 base timer register G3BT
01A116 01D116
01A216 Group 3 base timer control register 0 G3BCR0 01D216
01A316 Group 3 base timer control register 1 G3BCR1 01D316
01A416 01D416 A-D1 control register 2 AD1CON2
01A516 01D516
01A616 Group 3 function enable register G3FE 01D616 A-D1 control register 0 AD1CON0
01A716 Group 3 RTP output buffer register G3RTP 01D716 A-D1 control register 1 AD1CON1
01A816 01D816
01A916 01D916
01AA16 01DA16
01AB16 Group 3 high-speed HDLC communication control register 1 HDLC1 01DB16
01AC16 Group 3 high-speed HDLC communication control register HDLC 01DC16
01AD16 Group 3 high-speed HDLC communication register HDLCF 01DD16
01AE16 01DE16
Group 3 high-speed HDLC transmit counter HDLCC
01AF16 01DF16

The blank area is reserved and cannot be used by user.

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SFR

Address Register Address Register

01E016 CAN0 message slot buffer 0 standard ID0 C0SLOT0_0 021016
CAN0 slot interrupt mask register C0SIMKR
01E116 CAN0 message slot buffer 0 standard ID1 C0SLOT0_1 021116
01E216 CAN0 message slot buffer 0 extend ID0 C0SLOT0_2 021216
01E316 CAN0 message slot buffer 0 extend ID1 C0SLOT0_3 021316
01E416 CAN0 message slot buffer 0 extend ID2 C0SLOT0_4 021416 CAN0 error interrupt mask register C0EIMKR
01E516 CAN0 message slot buffer 0 data length code C0SLOT0_5 021516 CAN0 error interrupt status register C0EISTR
01E616 CAN0 message slot buffer 0 data 0 C0SLOT0_6 021616
01E716 CAN0 message slot buffer 0 data 1 C0SLOT0_7 021716 CAN0 baud rate prescaler C0BPR
01E816 CAN0 message slot buffer 0 data 2 C0SLOT0_8 021816
01E916 CAN0 message slot buffer 0 data 3 C0SLOT0_9 021916
01EA16 CAN0 message slot buffer 0 data 4 C0SLOT0_10 021A16
01EB16 CAN0 message slot buffer 0 data 5 C0SLOT0_11 021B16
01EC16 CAN0 message slot buffer 0 data 6 C0SLOT0_12 021C16
01ED16 CAN0 message slot buffer 0 data 7 C0SLOT0_13 021D16
01EE16 CAN0 message slot buffer 0 time stamp highC0SLOT0_14 021E16
01EF16 CAN0 message slot buffer 0 time stamp low C0SLOT0_15 021F16
01F016 CAN0 message slot buffer 1 standard ID0 C0SLOT1_0 022016
01F116 CAN0 message slot buffer 1 standard ID1 C0SLOT1_1 022116
01F216 CAN0 message slot buffer 1 extend ID0 C0SLOT1_2 022216
01F316 CAN0 message slot buffer 1 extend ID1 C0SLOT1_3 022316
01F416 CAN0 message slot buffer 1 extend ID2 C0SLOT1_4 022416
01F516 CAN0 message slot buffer 1 data length code C0SLOT1_5 022516
01F616 CAN0 message slot buffer 1 data 0 C0SLOT1_6 022616
01F716 CAN0 message slot buffer 1 data 1 C0SLOT1_7 022716
01F816 CAN0 message slot buffer 1 data 2 C0SLOT1_8 022816 CAN0 global mask register standard ID0 C0GMR0
01F916 CAN0 message slot buffer 1 data 3 C0SLOT1_9 022916 CAN0 global mask register standard ID1 C0GMR1
01FA16 CAN0 message slot buffer 1 data 4 C0SLOT1_10 022A16 CAN0 global mask register extend ID0 C0GMR2
01FB16 CAN0 message slot buffer 1 data 5 C0SLOT1_11 022B16 CAN0 global mask register extend ID1 C0GMR3
01FC16 CAN0 message slot buffer 1 data 6 C0SLOT1_12 022C16 CAN0 global mask register extend ID2 C0GMR4
01FD16 CAN0 message slot buffer 1 data 7 C0SLOT1_13 022D16
01FE16 CAN0 message slot buffer 1 time stamp highC0SLOT1_14 022E16
01FF16 CAN0 message slot buffer 1 time stamp low C0SLOT1_15 022F16
020016 023016 CAN0 message slot 0 control register / C0MCTL0/
CAN0 control register 0 C0CTLR0
020116 CAN0 local mask register A standard ID0 C0LMAR0
020216 023116 CAN0 message slot 1 control register / C0MCTL1/
CAN0 status register C0STR
020316 CAN0 local mask register A standard ID1 C0LMAR1
020416 023216 CAN0 message slot 2 control register / C0MCTL2/
CAN0 expansion ID register C0IDR
020516 CAN0 local mask register A extend ID0 C0LMAR2
020616 023316 CAN0 message slot 3 control register / C0MCTL3/
CAN0 configuration register C0CONR
020716 CAN0 local mask register A extend ID1 C0LMAR3
020816 023416 CAN0 message slot 4 control register / C0MCTL4/
CAN0 time stamp register C0TSR
020916 CAN0 local mask register A extend ID2 C0LMAR4
020A16 CAN0 transmit error count register C0TEC 023516 CAN0 message slot 5 control register C0MCTL5
020B16 CAN0 receive error count register C0REC 023616 CAN0 message slot 6 control register C0MCTL6
020C16 023716 CAN0 message slot 7 control register C0MCTL7
CAN0 slot interrupt status register C0SISTR
020D16 023816 CAN0 message slot 8 control register / C0MCTL8/
020E16 CAN0 local mask register B standard ID0 C0LMBR0
020F16

The blank area is reserved and cannot be used by user.

Note 1: CAN0 message slot i control registers (i=0 to 15) are allocated to addresses 023016 to 023F16 by switching
banks.

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M32C/83 group
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SFR

Address Register Address Register

023916 CAN0 message slot 9 control register / C0MCTL9/ 02C016
X0 register/Y0 register X0R/Y0R
CAN0 local mask register B standard ID1 C0LMBR1 02C116
023A16 CAN0 message slot 10 control register / C0MCTL10/ 02C216
X1 register/Y1 register X1R/Y1R
CAN0 local mask register B extend ID0 C0LMBR2 02C316
023B16 CAN0 message slot 11 control register / C0MCTL11/ 02C416
X2 register/Y2 register X2R/Y2R
CAN0 local mask register B extend ID1 C0LMBR3 02C516
023C16 CAN0 message slot 12 control register / C0MCTL12/ 02C616
X3 register/Y3 register X3R/Y3R
CAN0 local mask register B extend ID2 C0LMBR4 02C716
023D16 CAN0 message slot 13 control register C0MCTL13 02C816
X4 register/Y4 register X4R/Y4R
023E16 CAN0 message slot 14 control register C0MCTL14 02C916
023F16 CAN0 message slot 15 control register C0MCTL15 02CA16
X5 register/Y5 register X5R/Y5R
024016 CAN0 slot buffer select register C0SBS 02CB16
024116 CAN0 control register 1 C0CTLR1 02CC16
X6 register/Y6 register X6R/Y6R
024216 CAN0 sleep control register C0SLPR 02CD16
024316 02CE16
X7 register/Y7 register X7R/Y7R
024416 02CF16
CAN0 acceptance filter support register C0AFS
024516 02D016
X8 register/Y8 register X8R/Y8R
02D116
02D216
X9 register/Y9 register X9R/Y9R
02D316
02D416
X10 register/Y10 register X10R/Y10R
02D516
02D616
X11 register/Y11 register X11R/Y11R
02D716
02D816
X12 register/Y12 register X12R/Y12R
02D916
02DA16
X13 register/Y13 register X13R/Y13R
02DB16
02DC16
X14 register/Y14 register X14R/Y14R
02DD16
02DE16
X15 register/Y15 register X15R/Y15R
02DF16
02E016 XY control register XYC
02E116
02E216
02E316
02E416 UART1 special mode register 4 U1SMR4
02E516 UART1 special mode register 3 U1SMR3
02E616 UART1 special mode register 2 U1SMR2
02E716 UART1 special mode register U1SMR
02E816 UART1 transmit-receive mode register U1MR
02E916 UART1 bit rate generator U1BRG
02EA16
UART1 transmit buffer register U1TB
02EB16
02EC16 UART1 transmit-receive control register 0 U1C0
02ED16 UART1 transmit-receive control register 1 U1C1
02EE16
UART1 receive buffer register U1RB
02EF16

The blank area is reserved and cannot be used by user.

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SFR

Address Register Address Register

02F016 032016
02F116 032116
02F216 032216
02F316 032316
02F416 UART4 special mode register 4 U4SMR4 032416 UART3 special mode register 4 U3SMR4
02F516 UART4 special mode register 3 U4SMR3 032516 UART3 special mode register 3 U3SMR3
02F616 UART4 special mode register 2 U4SMR2 032616 UART3 special mode register 2 U3SMR2
02F716 UART4 special mode register U4SMR 032716 UART3 special mode register U3SMR
02F816 UART4 transmit-receive mode register U4MR 032816 UART3 transmit-receive mode register U3MR
02F916 UART4 bit rate generator U4BRG 032916 UART3 bit rate generator U3BRG
02FA16 032A16
UART4 transmit buffer register U4TB UART3 transmit buffer register U3TB
02FB16 032B16
02FC16 UART4 transmit-receive control register 0 U4C0 032C16 UART3 transmit-receive control register 0 U3C0
02FD16 UART4 transmit-receive control register 1 U4C1 032D16 UART3 transmit-receive control register 1 U3C1
02FE16 032E16
UART4 receive buffer register U4RB UART3 receive buffer register U3RB
02FF16 032F16
030016 Timer B3,B4,B5 count start flag TBSR 033016
030116 033116
030216 033216
Timer A1-1 register TA11
030316 033316
030416 033416 UART2 special mode register 4 U2SMR4
Timer A2-1 register TA21
030516 033516 UART2 special mode register 3 U2SMR3
030616 033616 UART2 special mode register 2 U2SMR2
Timer A4-1 register TA41
030716 033716 UART2 special mode register U2SMR
030816 Three-phase PWM control register 0 INVC0 033816 UART2 transmit-receive mode register U2MR
030916 Three-phase PWM control register 1 INVC1 033916 UART2 bit rate generator U2BRG
030A16 Three-phase output buffer register 0 IDB0 033A16
UART2 transmit buffer register U2TB
030B16 Three-phase output buffer register 1 IDB1 033B16
030C16 Dead time timer DTT 033C16 UART2 transmit/receive control register 0 U2C0
030D16 Timer B2 interrupt occurrence frequency set counter ICTB2 033D16 UART2 transmit/receive control register 1 U2C1
030E16 033E16
UART2 receive buffer register U2RB
030F16 033F16
031016 034016 Count start flag TABSR
Timer B3 register TB3
031116 034116 Clock prescaler reset flag CPSRF
031216 034216 One-shot start flag ONSF
Timer B4 register TB4
031316 034316 Trigger select register TRGSR
031416 034416 Up-down flag UDF
Timer B5 register TB5
031516 034516
031616 034616
Timer A0 register TA0
031716 034716
031816 034816
Timer A1 register TA1
031916 034916
031A16 034A16
Timer A2 register TA2
031B16 Timer B3 mode register TB3MR 034B16
031C16 Timer B4 mode register TB4MR 034C16
Timer A3 register TA3
031D16 Timer B5 mode register TB5MR 034D16
031E16 034E16
Timer A4 register TA4
031F16 External interrupt cause select register IFSR 034F16

The blank area is reserved and cannot be used by user.

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SFR

Address Register Address Register

035016 038016
Timer B0 register TB0 A-D0 register 0 AD00
035116 038116
035216 038216
Timer B1 register TA1 A-D0 register 1 AD01
035316 038316
035416 038416
Timer B2 register TA2 A-D0 register 2 AD02
035516 038516
035616 Timer A0 mode register TA0MR 038616
A-D0 register 3 AD03
035716 Timer A1 mode register TA1MR 038716
035816 Timer A2 mode register TA2MR 038816
A-D0 register 4 AD04
035916 Timer A3 mode register TA3MR 038916
035A16 Timer A4 mode register TA4MR 038A16
A-D0 register 5 AD05
035B16 Timer B0 mode register TB0MR 038B16
035C16 Timer B1 mode register TB1MR 038C16
A-D0 register 6 AD06
035D16 Timer B2 mode register TB2MR 038D16
035E16 Timer B2 special mode register TB2SC 038E16
A-D0 register 7 AD07
035F16 Count source prescaler register TCSPR 038F16
036016 039016
036116 039116
036216 039216
036316 039316
036416 UART0 special mode register 4 U0SMR4 039416 A-D0 control register 2 AD0CON2
036516 UART0 special mode register 3 U0SMR3 039516
036616 UART0 special mode register 2 U0SMR2 039616 A-D0 control register 0 AD0CON0
036716 UART0 special mode register U0SMR 039716 A-D0 control register 1 AD0CON1
036816 UART0 transmit/receive mode register U0MR 039816 D-A register 0 DA0
036916 UART0 bit rate generator U0BRG 039916
036A16 039A16 D-A register 1 DA1
UART0 transmit buffer register U0TB
036B16 039B16
036C16 UART0 transmit/receive control register 0 U0C0 039C16 D-A control register DACON
036D16 UART0 transmit/receive control register 1 U0C1 039D16
036E16 039E16
UART0 receive buffer register U0RB
036F16 039F16
037016
037116
037216
037316
037416
037516
037616 PLL control register 0 PLC0
037716
037816 DMA0 cause select register DM0SL
037916 DMA1 cause select register DM1SL
037A16 DMA2 cause select register DM2SL
037B16 DMA3 cause select register DM3SL
037C16
CRC data register CRCD
037D16
037E16 CRC input register CRCIN
037F16

The blank area is reserved and cannot be used by user.

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SFR

<144-pin version>
Address Register Address Register
03A016 Function select register A8 PS8 03D016 Port P14 register P14
03A116 Function select register A9 PS9 03D116 Port P15 register P15
03A216 03D216 Port P14 direction register PD14
03A316 03D316 Port P15 direction register PD15
03A416 03D416
03A516 03D516
03A616 03D616
03A716 03D716
03A816 03D816
03A916 03D916
03AA16 03DA16 Pull-up control register 2 PUR2
03AB16 03DB16 Pull-up control register 3 PUR3
03AC16 03DC16 Pull-up control register 4 PUR4
03AD16 03DD16
03AE16 03DE16
03AF16 Function select register C PSC 03DF16
03B016 Function select register A0 PS0 03E016 Port P0 register P0
03B116 Function select register A1 PS1 03E116 Port P1 register P1
03B216 Function select register B0 PSL0 03E216 Port P0 direction register PD0
03B316 Function select register B1 PSL1 03E316 Port P1 direction register PD1
03B416 Function select register A2 PS2 03E416 Port P2 register P2
03B516 Function select register A3 PS2 03E516 Port P3 register P3
03B616 Function select register B2 PSL2 03E616 Port P2 direction register PD2
03B716 Function select register B3 PSL3 03E716 Port P3 direction register PD3
03B816 03E816 Port P4 register P4
03B916 Function select register A5 PS5 03E916 Port P5 register P5
03BA16 03EA16 Port P4 direction register PD4
03BB16 03EB16 Port P5 direction register PD5
03BC16 Function select register A6 PS6 03EC16
03BD16 Function select register A7 PS7 03ED16
03BE16 03EE16
03BF16 03EF16
03C016 Port P6 register P6 03F016 Pull-up control register 0 PUR0
03C116 Port P7 register P7 03F116 Pull-up control register 1 PUR1
03C216 Port P6 direction register PD6 03F216
03C316 Port P7 direction register PD7 03F316
03C416 Port P8 register P8 03F416
03C516 Port P9 register P9 03F516
03C616 Port P8 direction register PD8 03F616
03C716 Port P9 direction register PD9 03F716
03C816 Port P10 register P10 03F816
03C916 Port P11 register P11 03F916
03CA16 Port P10 direction register PD10 03FA16
03CB16 Port P11 direction register PD11 03FB16
03CC16 Port P12 register P12 03FC16
03CD16 Port P13 register P13 03FD16
03CE16 Port P12 direction register PD12 03FE16
03CF16 Port P13 direction register PD13 03FF16 Port control register PCR

The blank area is reserved and cannot be used by user.

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SFR

<100-pin version>
12345678901234567890123456789 12345678901234567890123456789
Address
12345678901234567890123456789
Register
12345678901234567890123456789
Address
03D016
12345678901234567890123456789
12345678901234567890123456789
Register

12345678901234567890123456789 12345678901234567890123456789
03A016
03A116 03D116 1234567890123456789012345678901212345678901234567890123456789012
1234567890123456789012345678901212345678901234567890123456789012
03A216 03D216 1234567890123456789012345678901212345678901234567890123456789012
1234567890123456789012345678901212345678901234567890123456789012
1234567890123456789012345678901212345678901234567890123456789012
1234567890123456789012345678901212345678901234567890123456789012
03A316 03D316 1234567890123456789012345678901212345678901234567890123456789012
1234567890123456789012345678901212345678901234567890123456789012
03A416 03D416
03A516 03D516
03A616 03D616
03A716 03D716
03A816 03D816
03A916 03D916
03AA16 03DA16 Pull-up control register 2 PUR2
03AB16 03DB1612345678901234567890123456789012123456789
Pull-up control register 3 PUR3
12345678901234567890123456789012123456789
03DC1612345678901234567890123456789012123456789
03AC16
03AD16 03DD16
03AE16 03DE16
03AF16 Function select register C PSC 03DF16
03B016 Function select register A0 PS0 03E016 Port P0 register P0
03B116 Function select register A1 PS1 03E116 Port P1 register P1
03B216 Function select register B0 PSL0 03E216 Port P0 direction register PD0
03B316 Function select register B1 PSL1 03E316 Port P1 direction register PD1
03B416 Function select register A2 PS2 03E416 Port P2 register P2
03B516 Function select register A3 PS3 03E516 Port P3 register P3
03B616 Function select register B2 PSL2 03E616 Port P2 direction register PD2
03B716 Function select register B3 PSL3 03E716 Port P3 direction register PD3
12345678901234567890123456789
03B816
12345678901234567890123456789 03E816 Port P4 register P4
03B916 12345678901234567890123456789 03E916 Port P5 register P5
03BA16 03EA16 Port P4 direction register PD4
12345678901234567890123456789
12345678901234567890123456789
03BB16 03EB16 Port P5 direction register PD5
03BC16 12345678901234567890123456789 03EC16
03BD16 12345678901234567890123456789 03ED16
03BE16 03EE16
03BF16 03EF16
03C016 Port P6 register P6 03F016 Pull-up control register 0 PUR0
03C116 Port P7 register P7 03F116 Pull-up control register 1 PUR1
03C216 Port P6 direction register PD6 03F216
03C316 Port P7 direction register PD7 03F316
03C416 Port P8 register P8 03F416
03C516 Port P9 register P9 03F516
03C616 Port P8 direction register PD8 03F616
03C716 Port P9 direction register PD9 03F716
12345678901234567890123456789
12345678901234567890123456789
03C816 Port P10 register P10 03F816
03C916 12345678901234567890123456789 03F916
03CA16 1234567890123456789012345678901212345678901234567890123456789012
Port P10 direction register PD10 03FA16
12345678901234567890123456789
1234567890123456789012345678901212345678901234567890123456789012
03CB16 1234567890123456789012345678901212345678901234567890123456789012
12345678901234567890123456789
1234567890123456789012345678901212345678901234567890123456789012 03FB16
1234567890123456789012345678901212345678901234567890123456789012
03CC16 12345678901234567890123456789 03FC16
12345678901234567890123456789
03CD16 1234567890123456789012345678901212345678901234567890123456789012 03FD16
1234567890123456789012345678901212345678901234567890123456789012
03CE16 1234567890123456789012345678901212345678901234567890123456789012
1234567890123456789012345678901212345678901234567890123456789012 03FE16
1234567890123456789012345678901212345678901234567890123456789012
1234567890123456789012345678901212345678901234567890123456789012
03CF16 1234567890123456789012345678901212345678901234567890123456789012
1234567890123456789012345678901212345678901234567890123456789012
03FF16 Port control register PCR
The blank area is reserved and cannot be used by user.
1234567
1234567
Note 1: 1234567
1234567 Addresses 03CB 16, 03CE 16 , 03CF16 , 03D216 , 03D316 does not exist in 100-pin version. Must set

12345
"FF16" to the addresses at initial setting.
12345
Note 2: 12345Addresses 03DC16 area does not exist in 100-pin version. Must set "0016" to addresses 03DC16 at initial setting.
1234
Note 3: 1234Addresses 03A016, 03A116, 03B916, 03BC16, 03BD16, 03C916, 03CC16, 03CD16, 03D3016, 03D116
does not exist in 100-pin version.

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Software Reset

Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM
are preserved.

Processor Mode
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-
processor mode. The functions of some pins, memory map, and access space differ according to the
selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P15 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as an address bus, a data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. There-
fore, never change the processor mode bits when changing the contents of other bits. Also do not
attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.6.1 and 1.6.2 show the processor mode register 0 and 1.
Figure 1.6.3 shows the memory maps applicable for each processor modes.

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Processor Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Processor mode register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
PM0 000416 8016 (CNVss = "L")
0
0316 (CNVss = "H")

Bit R W
symbol Bit name Function

b1 b0
PM00 0 0: Single-chip mode
Processor mode bit 0 1: Memory expansion mode
(Note 2) 1 0: Must not be set
PM01
1 1: Microprocessor mode

R/W mode select bit 0: RD / BHE / WR

PM02
(Note 3) 1: RD / WRH / WRL
The device is reset when this bit is
PM03 Software reset bit set to "1". The value of this bit is "0"
when read
b5 b4
PM04 0 0 : Multiplexed bus is not used
Multiplexed bus space 0 1 : Allocated to CS2 space
select bit 0 1 : Allocated to CS1 space
PM05 (Note 4) 1 1 : Allocated to entire CS space
(Note 5)

Reserved bit Must always be set to "0"

BCLK output disable bit 0 : BCLK is output (Note 7)

PM07 1 : Function set by bit 0,1 of system
(Note 6) clock control register 0
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Note 2: Do not set the processor mode bits and other bits simultaneously when setting the processor
mode bits to 012 or 112 . Set the other bits first,and then change the processor mode bits.
Note 3: When using 16-bit bus width in DRAM controler, must set this bit to "1".
Note 4: Valid in microprocessor and memory expansion modes 1, 2 and 3. Do not use multiplex bus
when mode 0 is selected. Do not set to allocated to CS2 space when mode 2 is selected.
Note 5: After the reset has been released, the M32C/83 group MCU operates using the separate bus. As
a result, in microprocessor mode, you cannot select the full CS space multiplex bus.
When you select the full CS space multiplex bus in memory expansion mode, the address bus
operates with 64 Kbytes boundaries, for each chip select.
Mode 0: Multiplexed bus cannot be used.
Mode 1: CS0 to CS2 when you select full CS space.
Mode 2: CS0 to CS1 when you select full CS space.
Mode 3: CS0 to CS3 when you select full CS space.
Note 6: No BCLK is output in single chip mode even when "0" is set in PM07. When stopping clock
output in microprocessor or memory expansion mode, make the following settings: PM07="1", bit 0
(CM00) and bit 1 (CM01) of system clock control register 0 (address 000616) = "0". "L" is now
output from P53.
Note 7: When selecting BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".

Figure 1.6.1. Processor mode register 0

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Processor Mode

Processor mode register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 PM1 000516 0X0000002

Bit
symbol Bit name Function R W
b1 b0
0 0 : Mode 0 (P44 to P47 : A20 to A23)
PM10 0 1 : Mode 1 (P44: A20,
External memory area P45 to P47: CS2 to CS0)
mode bit (Note 2) 1 0 : Mode 2 (P44, P45 : A20, A21,
P46, P47 : CS1, CS0)
PM11 1 1 : Mode 3 (Note 3)
(P44 to P47 : CS3 to CS0)

0 : No wait state
PM12 Internal memory wait bit
1 : Wait state inserted

0 : One wait state inserted

PM13 SFR area wait bit 0
1 : Two wait states inserted (Note 4)
b5 b4

PM14 0 0 : No ALE
ALE pin select bit 0 1 : P53/BCLK (Note 5)
(Note 2) 1 0 : P56/RAS
PM15 1 1 : P54/HLDA

Nothing is assigned.
When write, set "0". When read, its content is indeterminate.

PM17 Reserved bit Must set to "0"

Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: Valid in memory expansion mode or in microprocessor mode.
Note 3: When mode 3 is selected, DRAMC is not used.
Note 4: When accessing SFR area for CAN, PM13 must be set to "1".
Note 5: When selecting P53/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".

Figure 1.6.2. Processor mode register 1

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Single chip Memory expanded mode

t

Microprocessor mode
mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 0 Mode 1 Mode 2 Mode 3
00000016 SFR area
SFR area SFR area SFR area SFR area SFR area SFR area SFR area SFR area
00040016 Internal RAM area Internal RAM area Internal RAM area Internal RAM area Internal RAM area Internal RAM area Internal RAM area Internal RAM area Internal RAM area
Processor Mode

Internal reserved area Internal reserved area Internal reserved area Internal reserved area Internal reserved area Internal reserved area Internal reserved area Internal reserved area
00080016
CS1 No use CS1 No use
External area 0 2Mbytes External area 0 2Mbytes
(Note1) CS1 CS1, 1Mbytes (Note1) CS1, 1Mbytes
CS1
External area 0 External area 0 External area 0 External area 0
20000016 4Mbytes 4Mbytes
(Note2) CS2, 1Mbytes CS2, 1Mbytes
CS2 External area 1 CS2 (Note2)
External area 1 External area 1
2Mbytes External area 0 External area 1 2Mbytes External area 0
External area 1 No use External area 1 No use
40000016

Connect with Connect with Connect with

Connect with Connect with Connect with No use
DRAM No use DRAM DRAM
DRAM DRAM DRAM

Figure 1.6.3. Memory maps in each processor mode

0, 0.5 to 8MB 0, 0.5 to 8MB
Rev.B2 for proof reading

No use 0, 0.5 to 8MB 0, 0.5 to 8MB 0, 0.5 to 8MB

0, 0.5 to 8MB (When not (When open area (Cannot use as
(When not (Cannot use as
(When open area (When open area (When open area DRAM area or
connect with DRAM area or connect with is under 8MB,
is under 8MB, is under 8MB, is under 8MB, external area.)
DRAM, use as external area.) DRAM, use as cannot use the
cannot use the cannot use the cannot use the
external area.) external area.) rest of this area.)
rest of this area.) rest of this area.) rest of this area.)
(External area 2) (External area 2) (External area 2) (External area 2) (External area 2) (External area 2)

C0000016
CS0 CS3, 1Mbytes CS3, 1Mbytes
External area 2 External area 2
2Mbytes CS0 No use
External area 3 External area 3 3Mbytes No use CS0
E0000016 External area 3 External area 3 4Mbytes No use
No use CS0, 1Mbytes
External area 3 CS0 External area 3
F0000016 Internal reserved area Internal reserved area Internal reserved area Internal reserved area 2Mbytes
CS0, 1Mbytes
Internal ROM area Internal ROM area Internal ROM area Internal ROM area External area 3 External area 3
FFFFFF16 Internal ROM area

Each CS0 to CS3 can set 0 to 3 WAIT. Note 1: 20000016–00800016=2016 Kbytes. 32 K less than 2 MB.
Note 2: 40000016–00800016=4064 Kbytes. 32 K less than 4 MB.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M32C/83 group
Mitsubishi Microcomputers

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Bus Settings SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bus Settings
The BYTE pin, bit 0 to 3 of the external data bus width control register (address 000B16), bits 4 and 5 of the
processor mode register 0 (address 000416) and bit 0 and 1 of the processor mode register 1 (address
000516) are used to change the bus settings.
Table 1.7.1 shows the factors used to change the bus settings, figure 1.7.1 shows external data bus width
control register and table 1.7.2 shows external area 0 to 3 and external area mode.

Table 1.7.1. Factors for switching bus settings

Bus setting Switching factor
Switching external address bus width External data bus width control register
Switching external data bus width BYTE pin (external area 3 only)
Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0
Selecting external area Bits 0 and 1 of processor mode register 1

(1) Selecting external address bus width

You can select the width of the address bus output externally from the 16 Mbytes address space, the
number of chip select signals, and the address area of the chip select signals. (Note, however, that
____
when you select “Full CS space multiplex bus”, addresses A0 to A15 are output.) The combination of bits
0 and 1 of the processor mode register 1 allow you to set the external area mode.
When using DRAM controller, the DRAM area is output by multiplexing of the time splitting of the row
and column addresses.
(2) Selecting external data bus width
You can select 8-bit or 16-bit for the width of the external data bus for external areas 0, 1, 2, and 3. When
the data bus width bit of the external data bus width control register is “0”, the data bus width is 8 bits;
when “1”, it is 16 bits. The width can be set for each of the external areas. The default bus width for
external area 3 is 16 bits when the BYTE pin is “L” after a reset, or 8 bits when the BYTE pin is “H” after
a reset. The bus width selection is valid only for the external bus (the internal bus width is always 16
bits).
During operation, fix the level of the BYTE pin to “H” or “L”.

(3) Selecting separate/multiplex bus

The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this bus configuration, input and output is performed on separate data and address buses. The data
bus width can be set to 8 bits or 16 bits using the external data bus width control register. For all
programmable external areas, P0 is the data bus when the external data bus is set to 8 bits, and P1 is
a programmable IO port. When the external data bus width is set to 16 bits for any of the external
areas, P0 and P1 (although P1 is undefined for any 8-bit bus areas) are the data buses.
When accessing memory using the separate bus configuration, you can select a software wait using
the wait control register.
• Multiplex bus
In this bus configuration, data and addresses are input and output on a time-sharing basis. For areas
for which 8-bit has been selected using the external data bus width control register, the 8 bits D0 to D7
are multiplexed with the 8 bits A0 to A7. For areas for which 16-bit has been selected using the external
data bus width control register, the 16 bits D0 to D15 are multiplexed with the 16 bits A0 to A15. When

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Bus Settings

accessing memory using the multiplex bus configuration, two waits are inserted regardless of whether
you select “No wait” or “1 wait” in the appropriate bit of the wait control register.
____
The default after a reset is a separate bus configuration, and the full CS space multiplex bus configu-
____
ration cannot be selected in microprocessor mode. If you select “Full CS space multiplex bus”, the 16
bits from A0 to A15 are output for the address

External data bus width control register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
DS 000B16 XXXXX0002

Bit symbol Bit name Function

AA
A R W

AA
A
DS0 External area 0 data bus 0 : 8 bits data bus width
width bit 1 : 16 bits data bus width

AA
A
DS1 External area 1 data bus 0 : 8 bits data bus width
width bit 1 : 16 bits data bus width

AA
A
DS2 External area 2 data bus 0 : 8 bits data bus width
width bit 1 : 16 bits data bus width
DS3 External area 3 data bus 0 : 8 bits data bus width
width bit (Note) 1 : 16 bits data bus width

Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note: The value after a reset is determined by the input via the BYTE pin.
When BYTE pin is "L", DS3 is "1". When "H", it is "0".

Figure 1.7.1. External data bus width control register

Table 1.7.2. External area 0 to 3 and external area mode

External area mode
(Note 2) Mode 0 Mode 1 Mode 2 Mode 3
External External External
area 1 area 0

Memory expansion mode, <CS1 area> <CS1 area> <CS1 area>

00800016 to 00800016 to 10000016 to
Microprocessor mode 1FFFFF16 00800016 to
1FFFFF16 1FFFFF16 1FFFFF16

<CS2 area> <CS2 area>

Memory expansion mode, 20000016 to No area is
20000016 to 20000016 to
Microprocessor mode 3FFFFF16 selected.
3FFFFF16 2FFFFF16
area 2

Memory expansion mode, 40000016 to <DRAMC area> <DRAMC area> <CS3 area>
Microprocessor mode BFFFFF16 40000016 to 40000016 to C0000016 to
(Note 1) BFFFFF16 BFFFFF16 CFFFFF16

<CS0 area> <CS0 area> <CS0 area>

C0000016 to C0000016 to C0000016 to E0000016 to
Memory expansion mode
External

EFFFFF16 EFFFFF16 EFFFFF16

area 3

EFFFFF16
<CS0 area> <CS0 area> <CS0 area>
C0000016 to
Microprocessor mode E0000016 to C0000016 to F0000016 to
FFFFFF16
FFFFFF16 FFFFFF16 FFFFFF16

Note 1: DRAMC area when using DRAMC.

Note 2: Set the external area mode (modes 0, 1, 2, and 3) using bits 0 and 1 of the processor mode register
1 (address 000516).

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Table 1.7.3. Each processor mode and port function

Processor Single-chip Memory

Memory expansion mode/microprocessor modes
mode mode expansion mode

Multiplexed “01”, “10” “00” “11” (Note 1)

bus space
CS1 or CS2 : multiplexed Separate bus All space multiplexed
select bit
bus, and the other : bus
separate bus

Data bus width All external Some external All external Some external All external Some external
BYTE pin level area is 8 bits area is 16 bits area is 8 bits area is 16 bits area is 8 bits area is 16 bits

P00 to P07 I/O port Data bus Data bus Data bus Data bus I/O port I/O port

P10 to P17 I/O port I/O port I/O port Data bus I/O port I/O port I/O port

P20 to P27 I/O port Address bus Address bus Address bus Address bus Address bus Address bus
/data bus /data bus /data bus /data bus
(Note 2) (Note 2)
P30 to P37 I/O port Address bus Address bus Address bus Address bus Address bus Address bus
/data bus /data bus
(Note 2)

P40 to P43 I/O port Address bus Address bus Address bus Address bus I/O port I/O port

P44 to P46 I/O port CS (chip select) or address bus (A23)

(For details, refer to “Bus control”) (Note 5)

P47 I/O port CS (chip select) or address bus (A23)

(For details, refer to “Bus control”) (Note 5)
P50 to P53 I/O port Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”) (Note 3,4)

P54 I/O port HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3)

P55 I/O port HOLD HOLD HOLD HOLD HOLD HOLD

P56 I/O port RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3)

P57 I/O port RDY RDY RDY RDY RDY RDY

Note 1:The default after a reset is the separate bus configuration, and "Full CS space multiplex bus" cannot be selected in
microprocessor mode. When you select "Full CS space multiplex bus" in extended memory mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
Note 2: Address bus in separate bus configuration.
Note 3: The ALE output pin is selected using bits 4 and 5 of the processor mode register 1.
Note 4: When you have selected the DRAM controller and access the DRAM area, these are outputs CASL, CASH, DW, and
BCLK.
Note 5: The CS signal and address bus selection are set by the external area mode.

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Bus Control

Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expan-
sion mode and microprocessor mode.
(1) Address bus/data bus
_____
There are 24 pins, A0 to A22 and A23 for the address bus for accessing the 16 Mbytes address space.
_____
A23 is an inverted output of the MSB of the address.
The data bus consists of pins for data IO. The external data bus control register (address 000B16)
selects the 8-bit data bus, D0 to D7 for each external area, or the 16-bit data bus, D0 to D15. After a reset,
there is by default an 8-bit data bus for the external area 3 when the BYTE pin is High, or a 16-bit data
bus when the BYTE pin is Low.
When shifting from single-chip mode to extended memory mode, the value on the address bus is unde-
fined until an external area is accessed.
When accessing a DRAM area with DRAM control in use, a multiplexed signal consisting of row address
and column address is output to A8 to A20.
(2) Chip select signals
_____
The chip select signals share A0 to A22 and A23. You can use bits 0 and 1 of the processor mode register
1 (address 000516) to set the external area mode, then select the chip select area and number of
address outputs.
In microprocessor mode, external area mode 0 is selected after a reset. The external area can be split
into a maximum of four Blocks or Areas using the chip select signals. Table 1.7.4 shows the external
areas specified by the chip select signals.

Table 1.7.4. External areas specified by the chip select signals

Memory space Chip select signal
expansion Processor mode
mode CS0 CS1 CS2 CS3

Mode 0
(A23) (A22) (A21) (A20)
C0000016 to
Specified address range

Memory expansion mode DFFFFF16

(2 Mbytes) 00800016 to 20000016 to
Mode 1 1FFFFF16 3FFFFF16
E0000016 to (2016 Kbytes) (2 Mbytes) (A20)
Microprocessor mode FFFFFF16
(2 Mbytes)
C0000016 to
Memory expansion mode EFFFFF16
(3 Mbytes) 00800016 to
Mode 2 3FFFFF16
C0000016 to (4064 Kbytes) (A21) (A20)
Microprocessor mode FFFFFF16
(4 Mbytes)
E0000016 to
Memory expansion mode EFFFFF16
(1 Mbytes) 10000016 to 20000016 to C0000016 to
Mode 3 1FFFFF16 2FFFFF16 CFFFFF16
F0000016 to (1 Mbytes) (1 Mbytes)
Microprocessor mode (1 Mbytes)
FFFFFF16
(1 Mbytes)

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Bus Control

The chip select signal turns Low (active) in synchronize with the address bus. However, its turning High
depends on the area accessed in the next cycle. Figure 1.7.2 shows the output examples of the address
bus and chip select signals.

Example 1: After accessing the external area, the Example 2: After accessing the external area, only the
address bus and chip select signal both are chip select signal is changed in the next
changed in the next cycle. cycle. (The address bus does not change.)

The following example shows the other chip select The following example shows the CPU accesses the
signal accessing area (j) in the cycle after having internal ROM/RAM area in the cycle after having
accessed external area (i). In this case, the address accessed external area. In this case, the chip select
bus and chip select signal both change between the signal changes between the two cycles but the
two cycles. address bus does not.
Access to Access to Access to Access to
external external external internal
area (i) area (j) area ROM/RAM
area

Data bus
Data Data Data bus Data
Address bus
Address Address bus Address
Chip select
(CSi) Chip select
Chip select
(CSj)

Example 3: After accessing the external area, only the Example 4: After accessing the external area, the
address bus is changed in the next cycle. address bus and chip select signal both are
(The chip select signal does not change.) not changed in the next cycle.

The following example shows the same chip select The following example shows CPU does not access
signal accessing area (i) in the cycle after having any area in the cycle after having accessed external
accessed external area (i). In this case, the address area (no instruction pre-fetch is occurred). In this
bus changes between the two cycles, but the chip case, the address bus and the chip select signal do
select signal does not. not change between the two cycles.
Access to Access to Access to
external external external
area (i) area (i) area No access

Data bus Data Data

Data bus Data

Address bus Address Address bus Address

Chip select Chip select

(CSi)

Note: These examples show the address bus and chip select signal for two consecutive cycles.
By combining these examples, chip select signal can be extended beyond two cycles.

Figure 1.7.2. Example of address bus and chip select signal outputs (Separate bus)

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Bus Control

(3) Read/write signals

With a 16-bit data bus, bit 2 of the processor mode register 0 (address 000416) selects the combinations
_____ ________ ______ _____ ________ _________
of RD, BHE, and WR signals or RD, WRL, and WRH signals. With a 8-bit full space data bus, use the
_____ ______ ________
combination of RD, WR, and BHE signals as read/write signals. (Set "0" to bit 2 of the processor mode
register 0 (address 000416).) When using both 8-bit and 16-bit data bus widths to access a 8-bit data bus
_____ ______ ________
area, the RD, WR and BHE signals combination is selected regardless of the value of bit 2 of the
processor mode register 0 (address 000416).
Tables 1.7.5 and 1.7.6 show the operation of these signals.
_____ ______ ________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically se-
lected.
_____ _________ _________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of
the processor mode register 0 (address 000416) has been set (Note).
Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the
protect register (address 000A16) to “1”.
_____ ________ _________
Note 2: When using 16-bit data bus width for DRAM controller, select RD, WRL, and WRH signals.

_____ ________ _________

Table 1.7.5. Operation of RD, WRL, and WRH signals
Data bus width RD WRL WRH Status of external data bus
L H H Read data
16-bit H L H Write 1 byte of data to even address
H H L Write 1 byte of data to odd address
H L L Write data to both even and odd addresses
H L (Note) Not used Write 1 byte of data
8-bit
L H (Note) Not used Read 1 byte of data
______
Note: It becomes WR signal.
_____ ______ ________
Table 1.7.6. Operation of RD, WR, and BHE signals
Data bus width RD WR BHE A0 Status of external data bus
H L L H Write 1 byte of data to odd address
L H L H Read 1 byte of data from odd address
H L H L Write 1 byte of data to even address
16-bit
L H H L Read 1 byte of data from even address
H L L L Write data to both even and odd addresses
L H L L Read data from both even and odd addresses
H L Not used H/L Write 1 byte of data
8-bit
L H Not used H/L Read 1 byte of data

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Bus Control

(4) ALE signal

The ALE signal latches the address when accessing the multiplex bus space. Latch the address when
the ALE signal falls. The ALE output pin is selected using bits 4 and 5 of the processor mode register 1
(address 000516).
The ALE signal is occurred regardless of internal area and external area.

When BYTE pin = “H” When BYTE pin = “L”

ALE ALE

(Note 1) (Note 1)
D0/A0 to D7/A7 Address Data D0/A0 to D15/A15 Address Data

A8 to A15 Address

(Note 2)
A16 to A19 Address A16 to A19 Address (Note 2)

A20 to A22, A23 Address or CS A20 to A22, A23 Address or CS

Note 1: Floating when reading.

Note 2: When full space multiplexed bus is selected, these are I/O ports.

Figure 1.7.3. ALE signal and address/data bus

(5) Ready signal

The ready signal facilitates access of external devices that require a long time for access. As shown in
________
Figure 1.7.2, inputting “L” to the RDY pin at the falling edge of BCLK causes the microcomputer to enter
________
the ready state. Inputting “H” to the RDY pin at the falling edge of BCLK cancels the ready state. Table
_____
1.7.7 shows the microcomputer status in the ready state. Figure 1.7.4 shows the example of the RD
________
signal being extended using the RDY signal.
Ready is valid when accessing the external area during the bus cycle in which the software wait is
________
applied. When no software wait is operating, the RDY signal is ignored, but even in this case, unused
pins must be pulled up.

Table 1.7.7. Microcomputer status in ready state (Note)

Item Status
Oscillation On
_____ _____ _____
RD/WR signal, address bus, data bus, CS Maintain status when ready signal received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits On
Note: The ready signal cannot be received immediately prior to a software wait.

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Bus Control

Separate bus (2 wait)

1st cycle 2nd cycle 3rd cycle 4th cycle

BCLK

RD

CSi
AAAAAAAA
AAAAAAAA
(i=0 to 3)
(Note)

RDY
tsu(RDY - BCLK)

RDY received timing

Multiplexed bus (2 wait)

1st cycle 2nd cycle 3rd cycle 4th cycle

BCLK

AAAAAA
AAAAAA
RD

CSi
(i=0 to 3)
(Note)

RDY
tsu(RDY - BCLK)

AA
: Wait using RDY signal RDY received timing

: Wait using software

tsu(RDY-BCLK)=RDY input setup time

RDY signal received timing for i wait(s): i + 1 cycles (i = 1 to 3)

Note: Chip select (CSi) may get longer by a state of CPU such as an instruction queue buffer.

_____ ________
Figure 1.7.4. Example of RD signal extended by RDY signal

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(6) Hold signal

The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L”
__________
to the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This
__________ __________
status is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table
1.7.8 shows the microcomputer status in the hold state. The bus is used in the following descending
__________
order of priority: HOLD, DMAC, CPU.

__________
HOLD > DMAC > CPU
_____ ________
Figure 1.7.5. Example of RD signal extended by RDY signal

Table 1.7.8. Microcomputer status in hold state

Item Status
Oscillation ON
_____ _____ _____ _______
RD/WR signal, address bus, data bus, CS, BHE Floating
Programmable I/O ports: P0 to P15 Maintains status when hold signal is received
__________
HLDA Output “L”
Internal peripheral circuits ON (but watchdog timer stops)
ALE signal Output “L”

(7) External bus status when accessing to internal area

Table 1.7.9 shows external bus status when accessing to internal area

Table 1.7.9. External bus status when accessing to internal area

Item SFR accessing status Internal ROM/RAM accessing status
Address bus Remain address of external area accessed immediately before
Data bus When read Floating
When write Floating
_____ ______ ________ _________
RD, WR, WRL, WRH Output "H"
________
BHE Remain external area status accessed immediately before
____
CS Output "H"
ALE ALE output

(8) BCLK output

BCLK output can be selected by bit 7 of the processor mode register 0 (address 000416 :PM07) and bit
1 and bit 0 of the system clock select register 0 (address 000616 :CM01, CM00). Setting PM07 to “0”
and CM01 and CM00 to “00” outputs the BCLK signal from P53. However, in single chip mode, BCLK
signal is inactive. When setting PM07 to “1”, the function is set by CM01 and CM00.

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_______ __________ __________ _____

(9) DRAM controller signals (RAS, CASL, CASH, and DW)
Bits 1, 2, and 3 of the DRAM control register (address 000416) select the DRAM space and enable the
DRAM controller. The DRAM controller signals are output when the DRAM area is accessed. Table
1.7.10 shows the operation of the respective signals.

_______ __________ __________ _____

Table 1.7.10. Operation of RAS, CASL, CASH, and DW signals
Data bus width RAS CASL CASH DW Status of external data bus
L L L H Read data from both even and odd addresses
L L H H Read 1 byte of data from even address
L L H H Read 1 byte of data from odd address
16-bit
L L L L Write data to both even and odd addresses
L L H L Write 1 byte of data to even address
L H L L Write 1 byte of data to odd address
L L Not used H Read 1 byte of data
8-bit
L L Not used L Write 1 byte of data

(10) Software wait

A software wait can be inserted by setting the wait control register (address 000816). Figure 1.7.6 shows
wait control register.
You can use the external area i wait bits (where i = 0 to 3) of the wait control register to specify from “No
wait” to “3 waits” for the external memory area. When you select “No wait”, the read cycle is executed in
the BCLK1 cycle. The write cycle is executed in the BCLK2 cycle (which has 1 wait). When accessing
external memory using the multiplex bus, access has two waits regardless of whether you specify “No
wait” or “1 wait” in the appropriate external area i wait bits in the wait control register.
Software waits in the internal memory (internal RAM and internal ROM) can be set using the internal
memory wait bits of the processor mode register 1 (address 000516). Setting the internal memory wait
bit = “0” sets “No wait”. Setting the internal memory wait bit = “1” specifies a wait.
SFR area is accessed with either "1 wait" (BCLK 2-cycle) or "2 waits" (BCLK 3-cycle) by setting the SFR
wait bit (bit 3) of the processor mode register 1 (address 000516). SFR area of CAN must be accessed
with "2 waits".
Table 1.7.11 shows the software waits and bus cycles. Figures 1.7.7 and 1.7.8 show example bus timing
when using software waits.

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Bus Control

Wait control register (Note 1, 2)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
WCR 000816 FF16

Bit symbol
WCR0
Bit name
External area 0
wait bit
b1 b0
Function
0 0: Without wait AA
A
A
AA
R W

A
AA
0 1: With 1 wait
WCR1 1 0: With 2 waits
1 1: With 3 waits

A
AA
b3 b2
WCR2 External area 1
0 0: Without wait

AA
wait bit
0 1: With 1 wait
WCR3 1 0: With 2 waits

AA
1 1: With 3 waits
b5 b4
WCR4

A A
External area 2 0 0: Without wait
wait bit 0 1: With 1 wait
WCR5 1 0: With 2 waits

AA
1 1: With 3 waits
b7 b6

AA
WCR6 External area 3 0 0: Without wait
wait bit 0 1: With 1 wait
WCR7 1 0: With 2 waits
1 1: With 3 waits
Note 1: When using the multiplex bus configuration, there are two waits regardless of whether you have
specified "No wait" or "1 wait". However, you can specify "2 waits" or "3 waits".
Note 2: When using the separate bus configuration, the read bus cycle is executed in the BCLK1 cycle,
and the write cycle is executed in the BCLK2 cycle (with 1 wait).

Figure 1.7.6. Wait control register

Table 1.7.11. Software waits and bus cycles

SFR area Internal External memory

Area Bus status wait bit Bus cycle
memory wait bit area i wait bit

0 2 BCLK cycles
SFR
1 3 BCLK cycles
0 1 BCLK cycle
Internal
ROM/RAM 1 2 BCLK cycles
Read :1 BCLK cycle
002
Write : 2 BCLK cycles
012 2 BCLK cycles
Separate bus
102 3 BCLK cycles
External 112 4 BCLK cycles
memory
002 3 BCLK cycle
area
012 3 BCLK cycles
Multiplex bus
102 3 BCLK cycles
112 4 BCLK cycles

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Bus Control

< Separate bus (no wait) > Bus cycle (Note) Bus cycle (Note)

BCLK

Write signal

Read signal

Data bus Output Input

Address bus (Note 2) Address Address

Chip select (Note 2,3)

< Separate bus (with wait) >

Bus cycle (Note) Bus cycle (Note)

BCLK
Write signal

Read signal

Data bus Output Input

Address bus (Note 2) Address Address

Chip select (Note 2,3)

< Separate bus with 2 wait >

Bus cycle (Note 1) Bus cycle (Note 1)

BCLK

Write signal

Read signal

Data bus Data output Input

Address bus (Note 2) Address Address

Chip select (Note 2,3)

Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this
bus cycle.
Note 2: Address bus and chip select may get longer depending on the state of CPU such as an instruction
queue buffer.
Note 3: When accessing same external area (same CS area) continuously, chip select may output
continuously.

Figure 1.7.7. Typical bus timings using software wait

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Bus Control

< Separate bus (with 3 wait) >

Bus cycle (Note) Bus cycle (Note)

BCLK
Write signal

Read signal

Data bus Data output Input

Address Address Address

(Note 2)

Chip select
(Note 2,3)

< Multiplexed bus (with 2 wait) >

Bus cycle (Note) Bus cycle (Note)

BCLK

Write signal

Read signal

ALE

Address Address Address

Address bus/Data bus Address Data output Address Input

(Note 2)
Chip select
(Note 2,3)

< Multiplexed bus (with 3 wait) >

Bus cycle (Note) Bus cycle (Note)

BCLK

Write signal

Read signal

Address Address Address

Address bus
/Data bus ( Address Data output Address Input
Note 2)
ALE

Chip select
(Note 2,3)

Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this
bus cycle.
Note 2: Address bus and chip select may get longer depending on the state of CPU such as an instruction
queue buffer.
Note 3: When accessing same external area (same CS area) continuously, chip select may output
continuously.

Figure 1.7.8. Typical bus timings using software wait

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Clock Generating Circuit

System Clock
Clock Generating Circuit
The clock generating circuit contains three oscillator circuits as follows:
(1) Main clock generating circuit
(2) Sub clock generating circuit
(3) Ring oscillator (oscillation stop detect function)

Table 1.8.1 lists the clock generating circuit specifications and Table 1.8.2 lists registers controlling each
clock generating circuit. Figure 1.8.1 shows block diagram of the system clock generating circuit. Figure
1.8.2 to 1.8.5 show clock control related registers.

Table 1.8.1. The clock oscillation circuit specifications

Item Main clock Sub clock Ring oscillator

generating circuit generating circuit
Use of clock • CPU's operating • CPU's operating • CPU's operating
clock source clock source clock source when
• Internal peripheral • Timer A/B's count main clock
unit's operating clock source frequency stops
clock source
Clock frequency 0 to 30 MHz 32.768 kHz About 1 MHz
Usable oscillator • Ceramic oscillator • Crystal oscillator
• Crystal oscillator
Pins to connect XIN, XOUT XCIN, XCOUT
oscillator

Oscillation stop/ Presence Presence Presence

restart function

Oscillator status Oscillating Stopped Stopped

after reset

Other Externally derived clock can be input

Table 1.8.2. Control registers for each clock generating circuits

Clock generating circuit Control register
Main clock System clock control register 0 (address 000616) :CM0
System clock control register 1 (address 000716) :CM1
Main clock divide register (address 000C16) : MCD
Sub clock System clock control register 0 (address 000616) : CM0
System clock control register 1 (address 000716) :CM1
Oscillation stop detect function Oscillation stop detect register (address 000D16) : CM2

Note : CM0, CM1, CM2 and MCD registers are protected from a false write by program runaway. When you
want to rewrite these registers, set "1" to bit 0 of protect register (address 000A16) to release protect,
then rewrite the register.

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Clock Generating Circuit

Main clock
XIN XOUT
fAD
Ring oscillator
circuit f1
CM05
a b
Divider 1 f8
CM02 CM21
c d f2n
Divider 2
Sub clock
S Q XCIN XCOUT e
Divider 3
f
(Wait mode) WAIT instruction R
CM07

fC BCLK
Software reset
CM04
RESET
1/32 fC32
NMI
Interrupt request level
judgment output

(Stop mode) Write "1" to CM10 S Q

R

CM0i : Bit i at system clock control register 0 (address 000616)

CM1i : Bit i at system clock control register 1 (address 000716)
CM2i : Bit i at oscillation stop detect register (address 000D16)

Divider 1
a 1/2 1/2 1/2 b

Divider 2 Bit 7 at address 035F16

c 1/n 1/2 d
Divide rate 2n (n=0 to 15) is set by bit 0 to 3 at count source prescaler register (address 035F16)

Divider 3
1/m
e f
Divide rate m (m=1,2,3,4,6,8,10,12,14,16 ) is set by bit 0 to 4 at main clock divide register (address 000C16)

Ring
oscillator Clock edge detect
Clock /charge and Charge and Interrupt
from discharge discharge generating
XIN circuit control circuit circuit Interrupt
request signal
Watchdog timer
interrupt
Ring oscillator
Ring oscillator circuit
clock

CM21 switch
select signal

Figure 1.8.1. Clock generating circuit

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Clock Generating Circuit

System clock control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
CM0 000616 0000 X0002

A A
Bit symbol Bit Function RW
name

AA
b1 b0
CM00 Clock output function 0 0 : I/O port P53
select bit (Note 2) 0 1 : fC output

A
AA
CM01 1 0 : f8 output
1 1 : f32 output

A
AA
CM02 WAIT peripheral 0 : Do not stop peripheral clock
function clock stop bit in wait mode
1 : Stop peripheral clock in
wait mode (Note 3)
Nothing is assigned.

A A
When write, set "0". When read, their contents are indeterminate.
Port XC select bit 0 : I/O port

AA
CM04
1 : XCIN-XCOUT generation (Note 4)
Main clock (XIN-XOUT) 0 : Main clock On

A A
CM05
stop bit (Note 5) 1 : Main clock Off (Note 6)
Watchdog timer 0 : Watchdog timer interrupt

AA
CM06
function select bit 1 : Reset (Note 7)
System clock select bit 0 : XIN, XOUT
CM07 (Note 8) 1 : XCIN, XCOUT

Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: The port P53 dose not function as an I/O port in microprocessor or memory expansion
mode.
When outputting ALE to P53 (bits 5 and 4 of processor mode register 0 is "01"), set
these bits to "00".
The port P53 function is not selected, even when you set "00" in microprocessor or
memory expansion mode and bit 7 of the processor mode register 0 is "1".
Note 3: fc32 is not included. When this bit is set to "1", PLL cannot be used in WAIT.
Note 4: When XcIN-XcOUT is used, set port P86 and P87 to no pull-up resistance with the input
port.
Note 5: When entering the power saving mode, the main clock is stopped using this bit. To stop
the main clock, set system clock stop bit (CM07) to "1" while an oscillation of sub clock is
stable. Then set this bit to "1".
When XIN is used after returning from stop mode, set this bit to "0".
When this bit is "1", XOUT is "H". Also, the internal feedback resistance remains ON, so
XIN is pulled up to XOUT ("H" level) via the feedback resistance.
Note 6: When the main clock is stopped, the main clock division register (address 000C16) is set
to the division by 8 mode.
However, in ring oscillator mode, the main clock division register is not set to the division
by 8 mode when XIN-XOUT is stopped by this bit.
Note 7: When "1" has been set once, "0" cannot be written by software.
Note 8: Set this bit "0" to "1" when sub clock oscillation is stable by setting CM04 to "1".
Set this bit "1" to "0" when main clock oscillation is stable by setting CM05 to "0".
Do not set CM04 and CM05 simultaneously.

Figure 1.8.2. Clock control related register (1)

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Clock Generating Circuit

System clock control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol Address When reset
1 0 0 0 0
CM1 000716 001000002

Bit symbol
CM10
Bit
name
All clock stop control bit 0 : Clock on
Function

1 : All clocks off (stop mode) (Note 3)

AA
RW

AA
(Note 2)

Reserved bit Must set to “0”

Reserved bit Must set to “1” AA

Reserved bit Must set to “0”

Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
A
Note 2: When this bit is "1", XOUT is "H", and the internal feedback resistance is disabled. XCIN
and XCOUT are high-inpedance.
Note 3: When all clocks are stopped (stop mode), the main clock division register
(address 000C16) is set to the division by 8 mode.

Main clock division register (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset

AA
A
MCD 000C16 XXX010002

A
AA
Bit symbol Bit name Function RW
b4 b3 b2 b1 b0
MCD0 Main clock division select
10010 : No division mode

A
AA
bit (Note 2, 4)
00010 : Division by 2 mode
MCD1 00011 : Division by 3 mode

A
AA
00100 : Division by 4 mode
00110 : Division by 6 mode
MCD2 01000 : Division by 8 mode

A
AA
01010 : Division by 10 mode
MCD3 01100 : Division by 12 mode

A
AA
01110 : Division by 14 mode
00000 : Division by 16 mode
MCD4

Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.

Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: These bits are "010002" (8-division mode) when main clock is stopped or you shift to stop
mode. However, in ring oscillator mode, this register is not set to the division by 8 mode when
XIN-XOUT is stopped by main clock stop bit.
Note 3: Do not attempt to set combinations of values other than those shown in this figure.
Note 4: SFR area of CAN is accessed with no division mode.

Figure 1.8.3. Clock control related registers (2)

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Clock Generating Circuit

Oscillation stop detect register (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 0 0 0 CM2 000D16 0016

Bit
symbol Bit name Function R W

Oscillation stop detect 0: Oscillation stop detect function disabled

CM20
enable bit 1: Oscillation stop detect function enabled

Main clock switching bit 0: XIN selected

CM21
(Note 2,3) 1: Ring oscillator selected

Oscillation stop detect 0: Ignored

CM22
flag (Note 4) 1: Detect oscillation stop

XIN clock monitor flag 0: XIN oscillating

CM23
(Note 5) 1: XIN not oscillating

Reserved bit Must set to "0"

Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: When XIN oscillation stop is detected in CM20="1", this bit becomes "1".
After this, although XIN starts oscillating, this bit does not become "0". When you change to XIN as
system clock after XIN restarts oscillating, write "0" to this bit.
Note 3: When CM20="1" and CM22="1", this bit cannot be written.
Note 4: When detecting oscillation stop, this bit becomes "1". "0" can be written by software.
When "0" is written during XIN oscillation stop, this bit does not becomes "1" although XIN oscillating stops.
Note 5: XIN state is judged by reading this bit several times in oscillation stop interrupt process program.

Figure 1.8.4. Clock control related register (3)

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Clock Generating Circuit

Count source prescale register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
TCSPR 035F16 0XXX 00002

Bit
symbol Bit name Function R W
b3 b2 b1b0
CNT0 0 0 0 0: No-division
0 0 0 1: Division by 2
0 0 1 0: Division by 4
CNT1 0 0 1 1: Division by 6
Division rate select bit • (Note)
•
CNT2 •
1 1 0 1: Division by 26
1 1 1 0: Division by 28
CNT3 1 1 1 1: Division by 30

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

0: Divider stops
CST Operation enable bit
1: Divider starts
Note : Write to these bits during the count stop.

VDC control register for PLL (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
PLV 001716 XXXXXX012

Bit
symbol Bit name Function R W

PLL VDC enable bit 0 : Cut off power to PLL

PLV00
(Note 2) 1 : Power to PLL

Reserved bit Must set to "0"

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note 1: When rewriting this register, set bit 3 of protect regiser (address 000A16) to "1".
Note 2: Set this bit to "0" before shifting to stop mode.

Figure 1.8.5. Clock control related register (4)

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Clock Generating Circuit

(1) Main clock

The main clock is a clock source for CPU operation and peripheral I/O. Figure 1.8.6 shows example of a
main clock. When a reset, the clock oscillates and after a reset, the clock is divided by 8 to the BCLK
(CPU operating clock).

(a) Main clock On/Off function

• Main clock (XIN-XOUT) stop bit of system control register 0 (bit 5 at address 000616)
0: Main clock On
1: Main clock Off
Also, the clock is stopped by shifting to the stop mode.
• All clock stop control bit of system control register 1 (bit 0 at address 000716)
0: Clock on
1: All clocks off (stop mode)

Microcomputer Microcomputer
(Built-in feedback resistance) (Built-in feedback resistance)
XIN XOUT XIN XOUT
Open
(Note)
Rd
Externally derived clock

CIN Vcc
COUT
Vss

Note: Insert a damping resistance if required. The resistance will vary depending on
the oscillator setting. Use the value recommended by the maker of the oscillator.
Insert a feedback resistance between XIN and XOUT when an oscillation
manufacture required.

Figure 1.8.6. Examples of main clock

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Clock Generating Circuit

(2) Sub clock

The sub clock is a clock source for CPU operation and count source for timer A and B. Figure 1.8.7
shows example of sub clock. When the sub clock is used, set ports P86 and P87 to no pull-up resistance
with the input port. No sub clock is generated during and after a reset.

(a) Sub clock On/Off function

When you want to use sub clock, set the following bit and sub clock enabled.
• Port Xc select bit of system control register 0 (bit 4 at address 000616)
0: I/O port (sub clock off)
1: XIN-XOUT generation (sub-clock on)
Also, shifting to the stop mode stops the clock.
• All clock stop control bit of system control register 1 (bit 0 at address 000716)
0: Clock On
1: All clock stop (stop mode)

Microcomputer Microcomputer
(Built-in feedback resistance) (Built-in feedback resistance)
XCIN XCOUT XCIN XCOUT
Open
(Note)
RCd
Externally derived clock

CCIN CCOUT Vcc

Vss

Note: Insert a damping resistance if required. The resistance will vary depending on
the oscillator and the oscillation drive capacity setting. Use the value
recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Insert a feedback resistance between XCIN and XCOUT when an oscillation
manufacture required.

Figure 1.8.7. Examples of sub clock

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Clock Generating Circuit

(3) Oscillation stop detect function (OSD function)

This function monitor the main clock (XIN pin). When main clock is stopped, internal ring oscillator starts
ocsillation and replace the main clock. Then oscillation stop detect interrupt process is operated.
When frequency of main clock is less or equal than 2MHz, this function does not work.

(a) OSD function enable/disable

• OSD enable bit of oscillation stop detect register (bit 0 at address 000D16)
0: OSD function disabled
1: OSD function enabled
Set OSD enable bit (bit 0) of oscillation stop detect register to "0" to disable OSD function before
setting stop mode. Stop mode is canceled before setting this bit to "1".

(b) Operation when oscillation stop detects

1) When XIN oscillation stops, a built in ring oscillation starts as a main clock automatically.
2) OSD interrupt request is generated, jump to an address FFFFF016 to FFFFF316 allocated fixed
vector table (watchdog timer interrupt vector) and execute program of jump address.
3) OSD interrupt shares vector table with watchdog timer interrupt. When using both OSD and watch-
dog timer interrupts, read and judge OSD flag in interrupt process routine.
OSD flag of oscillation stop detect register (bit 2 at address 000D16)
1: Oscillation stop detects
4) XIN does not become main clock although XIN On after oscillation stop detects. When you want XIN
to be main clock, execute a process shown in Figure 1.8.8.

XIN switching

Oscillation stop detect register (address 000D16)

XIN is ON bit 3: XIN clock monitor flag
OFF
ON 0: XIN ON
1: XIN OFF

Confirm XIN is ON

Confirm XIN is ON several times

Write "0" to OSD flag bit2: Oscillation stop detect flag

bit 1: Main clock select bit

Write "0" to main clock
0: XIN selected
select bit
1: Ring oscillator selected

End

Figure 1.8.8. Main clock switching sequence

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Wait Mode

CPU clock (BCLK)

Main clock, sub clock or clock from ring oscillator can be selected as clock source for BCLK.
System clock select bit of system clock control register (bit 7 at address 000616)
0: Main clock is selected (XIN-XOUT)
1: Sub clock is selected (XCIN-XCOUT)
Main clock select bit of oscillation stop detect register (bit 1 at address 000D16)
0: Main clock is selected (XIN-XOUT)
1: Clock from ring oscillator is selected

Table 1.8.3. BCLK source and setting bit

BCLK source System clock select bit Main clock select bit
(Bit 7 of address 000616) (Bit 1 of address 000D16)
Main clock (XIN-XOUT) 0 0
Sub clock (XCIN-XCOUT) 1 0
Ring oscillator 0 1

When main clock or ring oscillator clock is selected as clock source for BCLK, the BCLK is the clock
derived by dividing the main clock or ring oscillator clock by 1, 2, 3, 4, 6, 8, 10, 12, 14 or 16.

Main clock divide rate select bit of main clock division register (bit 0 to 4 at address 000C16)

The BCLK is derived by dividing the main clock (XIN-XOUT) by 8 after a reset. (Main clock division register
= "XXX010002")
When main clock is stopped under changing to stop mode or selecting XIN-XOUT (main clock select bit =
"0"), the main clock division register is set to the division by 8 ("XXX010002").
When ring oscillator clock is selected as clock source for BCLK, although main clock is stoped, the
contents of main clock division register is maintained.

Peripheral function clock

Main clock, sub clock, PLL clock or ring oscillator clock can be selected as clock source for peripheral
function.
(1) f1, f8, f2n
The clock is derived from the main clock or by dividing it by 1, 8 or 2n (n=1 to 15). It is used for the
timer A and timer B counts and serial I/O and UART operation clock.
The f2n division rate is set by the count source prescaler register. Figure 1.8.5 shows the count source
prescaler register.
(2) fAD
This clock has the same frequency as the main clock or ring oscillator clock and is used for A-D
conversion.
(3) fC32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(4) fPLL
This clock is 80 MHz generated by PLL synthesizer. It is used for the intelligent I/O group 3.

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Clock Generating Circuit

Clock Output
You can output clock from the P53 pin.
• BCLK output function select bit of processor mode register 0 (bit 7 at address 000416)
• ALE select bits of processor mode register 1 (bit 4 and 5 at address 000516)
• Clock output function select bits of system clock select register (bits 1 and 0 at address 000616)

Table 1.8.4 shows clock output setting (single chip mode) and Table 1.8.5 shows clock output setting
(memory expansion/microprocessor mode).

Table 1.8.4. Clock output setting (single chip mode)

BCLK output function Clock output function
ALE pin select bit P53/BCLK/ALE/CLKOUT
select bit select bit
pin function
PM07 CM01 CM00 PM15 PM14
Ignored 0 0 Ignored Ignored P53 I/O port
1 0 1 Ignored Ignored fc output (Note)
1 1 0 Ignored Ignored f8 output (Note)
1 1 1 Ignored Ignored f32 output (Note)
Note :Must use P57 as input port.

Table 1.8.5. Clock output setting (memory expansion/microprocessor mode)

BCLK output function Clock output function
ALE pin select bit P53/BCLK/ALE/CLKOUT
select bit select bit
pin function
PM07 CM01 CM00 PM15 PM14
0 0 0 BCLK output
1 0 0 "L" output (not P53)
"0, 0"
1 0 1 "1, 0" fc output
"1, 1"
1 1 0 f8 output
1 1 1 f32 output
Ignored 0 0 0 1 ALE output

Note: The processor mode register 0 and 1 are protected from false write by program run away.
Set bit 1 to "1" at protect register (address 000A16) and release protect before rewriting processor
mode register 0 and 1.

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Power Saving

Power Saving
There are three power save modes. Figure 1.8.9 shows the clock transition between each of the three
modes, (1), (2), and (3).
• Normal operating mode
CPU and peripheral function operate when supplying clock. Power dissipation is reduced by making
BCLK slow.
• Wait mode
BCLK is stopped. Peripheral function clock is stopped as desired. Main clock and sub clock isn't
stopped. Power dissipation is reduced than normal operating mode.
• Stop mode (Note 1)
Main clock, sub clock and PLL synthesizer are stopped. CPU and peripheral function clock are
stopped. Power dissipation is the most few in this mode.
Note :When using stop mode, oscillation stop detect function must be canceled.

(1) Normal operating mode

High-speed mode
Main clock one cycle forms CPU operating clock.
Medium-speed mode
The main clock divided into 2, 3, 4, 6, 8, 10, 12, 14, or 16 forms CPU operating clock.
Low-speed mode
Subclock (fc) forms CPU operating clock.
Low power-dissipation mode
This mode is selected when the main clock is stopped from low-speed mode. Only the peripheral
functions for which the subclock was selected as the count source continue to run.
Ring oscillator mode
The ring oscillator clock divided into 2, 3, 4, 6, 8, 10, 12, 14, or 16 forms CPU operating clock.
Ring oscillator low power-dissipation mode
This mode is selected when the main clock is stopped from low-speed mode.

When switching BCLK from ring oscillator to main clock, switch clock after main clock oscillates fully
stable. After setting divided by 8 (main clock division register =0816) in ring oscilltor mode, switching
to the middle mode (divided by 8) is recommended.

(2) Wait mode

In wait mode, BCLK is stopped and CPU and watchdog timer operated by BCLK are halted. The main
clock, subclock and ring oscillator clock continue to run.

(a) Shifting to wait mode

Execute WAIT instruction.
(b) Peripheral function clock stop function
The f1, f8 and f2n being supplied to the internal peripheral functions stops. The internal peripheral
functions operated by the clock stop.

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Power Saving

WAIT peripheral function clock stop bit of system clock control register 0 (bit 2 at address 000616)
0: Do not stop f1, f8 and f2n in wait mode and do not stop supplying clock to PLL circuit
1: Stop f1, f8 and f2n in wait mode and stop supplying clock to PLL circuit

(c) The status of the ports in wait mode

Table 1.8.6 shows the status of the ports in wait mode.

(d) Exit from wait mode

Wait mode is cancelled by a hardware reset or interrupt. If a peripheral function interrupt is used to
cancel wait mode, set the following registers.

Interrupt priority set bits for exiting a stop/wait state of exit priority register (bits 0 to 2 at address
009F16) :RLVL0 to RLVL2
Set the same level as the flag register (FLG) processor interrupt level (IPL).
Interrupt priority set bits of interrupt control register (bits 0 to 2)
Set to a priority level above the level set by RLVL0 to RLVL2 bits
Interrupt enable flag of FLG register
I=1

When using an interrupt to exit Wait mode, the microcomputer resumes operating the clock that was oper-
ating when the WAIT command was executed as BCLK from the interrupt routine.

Table 1.8.6. Port status during wait mode

Pin Memory expansion mode Single-chip mode
Microprocessor mode
_______ _______
Address bus, data bus, CS0 to CS3, Retains status before wait mode
________
BHE
_____ ______ ________ _________ ______ _________ ________
RD, WR, WRL, WRH, DW, CASL, CASH “H” (Note)
________
RAS “H” (Note)
__________
HLDA,BCLK “H”

ALE “L”
Port Retains status before wait mode

CLKOUT When fC selected Does not stop

When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit is
“0”. When the WAIT peripheral function clock stop bit is “1”, the
status immediately prior to entering wait mode is maint ained.
________ ________
Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”.

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Power Saving

(3) Stop mode

All oscillation, main clock, subclock, and PLL synthesizer stop in this mode. Because the oscillation of
BCLK and peripheral clock stops in stop mode, peripheral functions such as the A-D converter, timer A
and B, serial I/O, intelligent I/O and watchdog timer do not function.
The content of the internal RAM is retained provided that VCC remains above 2.5V.
When changing to stop mode, the main clock division register (000C16) is set to “XXX010002” (division by
8 mode).

(a) Changing to stop mode

All clock stop control bit of system clock control register 1 (bit 0 at address 000716)
0: Clock ON
1: All clocks off (stop mode)
Before changing to stop mode, set bit 7 of PLL control register 0 (address 037616) to "0" to stop PLL.
Also, set bit 0 of VDC control register for PLL (address 001716) to "1" to turn PLL circuit power off.

(b) The status of the ports in stop mode

Table 1.8.7 shows the status of the ports in stop mode.

(c) Exit from stop mode

Stop mode is cancelled by a hardware reset or interrupt. If a peripheral function interrupt is used to
cancel stop mode, set the following registers.
• Interrupt priority set bits for exiting a stop/wait state of exit priority register (bits 0 to 2 at address 009F16) :RLVL0 to RLVL2
Set the same level as the flag register (FLG) processor interrupt level (IPL).
• Interrupt priority set bits of interrupt control register (bits 0 to 2)
Set to a priority level above the level set by RLVL0 to RLVL2 bits
• Interrupt enable flag of FLG register
I=1
When exiting from stop mode using peripheral interrupt request, CPU operates the following BCLK
and the relevant interrupt routine is executed.
• When subclock was set as BCLK before changing to stop mode, subclock is set to BCLK after
cancelled stop mode
• When main clock was set as BCLK before changing to stop mode, the main clock division by 8 is set
to BCLK after cancelled stop mode.

Table 1.8.7. Port status during stop mode

Pin Memory expansion mode Single-chip mode
Microprocessor mode
_______ _______ _______
Address bus, data bus, CS0 to CS3, BHE Retains status before stop mode
_____ ______ ________ _________ ______ _________ ________
RD, WR, WRL, WRH, DW, CASL, CASH “H” (Note)
________
RAS “H” (Note)
__________
HLDA, BCLK “H”

ALE “H”

Port Retains status before stop mode

CLKOUT When fc selected “H”

When f8, f32 selected Retains status before stop mode
________ ________
Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”.

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Power Saving

Reset

Interrupt Middle-speed mode

(divided by 8 mode)
Note 1
All oscillation is stopped
WAIT instruction
CM10="1" High-speed / Wait mode
Stop mode interrupt
middle-speed mode

CPU operation
Note 1, 5 Note 2, 4
All oscillation is stopped is stopped
CM10="1"
Low-speed/ low power WAIT instruction
Stop mode Note 3 Wait mode
dissipation mode interrupt
Interrupt
Note 1
XIN oscillation is stopped
Ring oscillator / ring oscillator Note 6
Detect Interrupt WAIT instruction
low power dissipation mode Wait mode
oscillation stop interrupt

Normal operation mode

Note 1 :Switch clocks after the main clock oscillation is fully stabled.
Note 2 :Switch clocks after oscillation of sub clock is fully stable.
Note 3 :The main clock division register is set to the division by 8 mode (MCD="0816").
Note 4 :When changing to low power dissipation mode, the main clock division register is set to
the division by 8 mode (MCD="0816").
Note 5 :Low power dissipation mode can not be changed to high-speed / middle-speed mode.
Note 6 :Other oscillation mode cannot be changed to low power dissipation mode.

Figure 1.8.9. Clock transition

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Power Saving

Main clock is oscillating

Transition of normal mode Sub clock is stopped
Please change according to a direction of an arrow. Middle-speed mode (divided-by-8 mode)

BCLK :f(XIN)/8
CM07=“0” MCD=“0816”
High-speed/middle-speed mode

MCD=“XX16” CM04=“1”
Main clock is oscillating Note 1, 3 Main clock is oscillating MCD=“XX16”
Sub clock is stopped Sub clock is oscillating Note 1, 3
High-speed mode High-speed mode
CM21=“0”
BCLK :f(XIN) BCLK :f(XIN) Note 1
CM07=“0” MCD=“1216” CM04=“0”
CM07=“0” MCD=“1216”

Middle-speed mode Middle-speed mode

(divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode) (divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode) CM21=“1”
BCLK :f(XIN)/division rate CM04=“1” Note 1
BCLK :f(XIN)/division rate
CM07=“0” MCD=“XX16” CM07=“0” MCD=“XX16”
Note 3 Note 3

CM07=“0” Note 1 CM07=“0” Note 1 CM07=“1”

MCD=“XX16” Note 3 MCD=“XX16” Note 3 Note 2
CM04=“0”

Low-speed/low power dissipation mode

Main clock is stopped CM07=“1” Note 2 Main clock is oscillating
Sub clock is oscillating CM05=“1” Sub clock is oscillating
Low power
dissipation mode Low-speed mode
CM05=“1”
BCLK :f(XCIN) BCLK :f(XCIN)
CM07=“1” CM07=“1”
CM05=“0” Note 4

Ring oscillator/ring oscillator low power dissipation mode

Ring oscillator is selected Ring oscillator is selected
Main clock is stopped Main clock is oscillating
Sub clock is stopped Sub clock is oscillating (stopped)
Ring oscillator low power Ring oscillator mode
dissipation mode
CM05=“1”
BCLK: Ring oscillator clock/division rate CM04="0" BCLK: Ring oscillator clock/division rate
CM21="1" CM21="1"
CM05="1" CM05="0"
CM05=“0”
(CM04="1")

Note 1: Switch clocks after oscillation of main clock is fully stable.

Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: Set the desired division to the main clock division register (MCD).
Note 4: Set to divided by 8 mode (MCD is set to "0816").

Figure 1.8.10. Clock transition

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Protection

Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.8.11 shows the protect register. The following registers are
protected by the protect register.
(1) Registers protected by PRC0 (bit 0)
• System clock control registers 0 and 1 (addresses 000616 and 000716)
• Main clock division register (address 000C16)
• Oscillation stop detect register (address 000D16)
• PLL control register 0 (address 037616)
(2) Registers protected by PRC1 (bit 1)
• Processor mode registers 0 and 1 (addresses 000416 and 000516)
• Three-phase PWM control registers 0 and 1 (addresses 030816 and 030916)
(3) Registers protected by PRC2 (bit 2)
• Port P9 direction register (address 03C716)
• Function select register A3 (address 03B516)
(4) Registers protected by PRC3 (bit 3)
• VDC control register for PLL (address 001716)
• VDC control register 0 (address 001F16)

If, after “1” (write-enabled) has been written to the PRC2, a value is written to any address, the bit automati-
cally reverts to “0” (write-inhibited). Change port P9 input/output and function select register A3 immedi-
ately after setting "1" to PRC2. Interrupt and DMA transfer should not be inserted between instructions.
However, the PRC0, PRC1 and PRC3 do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.

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Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
PRCR 000A16 XXXX00002

Bit Bit name Function R W

symbol

A
Enables writing to system clock control registers 0
and 1 (addresses 000616 and 000716), main clock
division register (address 000C16), oscillation stop
PRC0 Protect bit 0 detect register (address 000D16) and PLL control
register 0 (address 037616)
0 : Write-inhibited
1 : Write-enabled

A
Enables writing to processor mode registers 0 and
1 (addresses 000416 and 000516) and three-
PRC1 phase PWM control register 0 and 1 (addresses
Protect bit 1 030816 and 030916)
0 : Write-inhibited
1 : Write-enabled

PRC2 Protect bit 2

Enables writing to port P9 direction register (
address 03C716) and function select register A3
(address 03B516)
(Note 1) 0 : Write-inhibited A
A
1 : Write-enabled

Enables writing to VDC control register for PLL (

address 001716), VDC control register 0 and 1 (
PRC3 Protect bit 3 addresses 001F16 and 001B16)
0 : Write-inhibited
1 : Write-enabled (Note 2)

Nothing is assigned.
When write, set “0”. When read, their contents are indeterminate.

Note 1: Writing a value to an address after “1” is written to this bit returns the bit
to “0”. Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Note 2: User cannot use. Writing to VDC control registers 0 and 1 (addresses
001F16, 001B16) is enabled so that a careful handling is required.

Figure 1.8.11. Protect register

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Interrupts

Interrupt Outline
Types of Interrupts
• Maskable interrupt : An interrupt which can be disabled by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be disabled by the interrupt enable flag (I flag) or
whose interrupt priority cannot be changed by priority level.

Figure 1.9.1 lists the types of interrupts.

 Undefined instruction (UND instruction)

 Overflow (INTO instruction)
Software
 BRK instruction
 
 BRK2 instruction
 INT instruction


Interrupt
 
 Reset
_______
  NMI
  Special
 Watchdog timer
   Ocsillation stop detection
  Single step
Hardware 
 Address matched

Peripheral I/O*1

*1 Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer
system. High-speed interrupt can be used as highest priority in peripheral I/O interrupts.

Figure 1.9.1. Classification of interrupts

Software Interrupts
Software interrupts are generated by some instruction that generates an interrupt request when ex-
ecuted. Software interrupts are nonmaskable interrupts.
(1) Undefined-instruction interrupt
This interrupt occurs when the UND instruction is executed.
(2) Overflow interrupt
This interrupt occurs if the INTO instruction is executed when the O flag is 1.
The following lists the instructions that cause the O flag to change:
ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA,
SUB, SUBX
(3) BRK interrupt
This interrupt occurs when the BRK instruction is executed.
(4) BRK2 interrupt
This interrupt occurs when the BRK2 instruction is executed. This interrupt is used exclusively for
debugger purposes. You normally do not need to use this interrupt.

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Interrupts

(5) INT instruction interrupt

This interrupt occurs when the INT instruction is executed after specifying a software interrupt number
from 0 to 63. Note that software interrupt numbers 7 to 54 and 57 are assigned to peripheral I/O
interrupts. This means that by executing the INT instruction, you can execute the same interrupt
routine as used in peripheral I/O interrupts.
The stack pointer used in INT instruction interrupt varies depending on the software interrupt number.
For software interrupt numbers 0 to 31, the U flag is saved when an interrupt occurs and the U flag is
cleared to 0 to choose the interrupt stack pointer (ISP) before executing the interrupt sequence. The
previous U flag before the interrupt occurred is restored when control returns from the interrupt rou-
tine. For software interrupt numbers 32 to 63, such stack pointer switchover does not occur.
However, in peripheral I/O interrupts, the U flag is saved when an interrupt occurs and the U flag is
cleared to 0 to choose ISP.
Therefore movement of U flag is different by peripheral I/O interrupt or INT instruction in software
interrupt number 32 to 54 and 57.

Hardware Interrupts
There are Two types of hardware Interrupts; special interrupts and Peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are nonmaskable interrupts.
• Reset
____________
A reset occurs when the RESET pin is pulled low.
______
• NMI interrupt
______
This interrupt occurs when the NMI pin is pulled low.
• Watchdog timer interrupt
This interrupt is caused by the watchdog timer.
• Ocsillation stop detect interrupt
This interrupt is caused by the ocsillation stop detect function.
It occurs when detecting the XIN ocsillation is stopped.
• Single-step interrupt
This interrupt is used exclusively for debugger purposes. These interrupts normally do not need to use
this interrupt. A single-step interrupt occurs when the D flag is set (= 1); in this case, an interrupt is
generated each time an instruction is executed.
• Address-match interrupt
This interrupt occurs when the program's execution address matches the contents of the address
match register while the address match interrupt enable bit is set (= 1).
This interrupt does not occur if any address other than the start address of an instruction is set in the
address match register.

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Interrupts

(2) Peripheral I/O interrupts

A peripheral I/O interrupt is generated by one of the built-in peripheral functions. Built-in peripheral
functions are dependent on classes of products, so the interrupt factors too are dependent on classes
of products. The interrupt vector table is the same as the one for software interrupt numbers 7 through
54 and 57 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• UART related interrupt (UART0 to 4)
- UART transmission/NACK interrupt
- UART reception/ACK interrupt
- Bus collision detection, start/stop condition detection interrupts
This is an interrupt that the serial I/O bus collision detection generates. When I2C mode is selected,
start, stop condition interrupt is selected.
• DMA0 through DMA3 interrupts
• Key-input interrupt
___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt (AD0, 1)
• Timer A interrupt (TA0 to 4)
• Timer B interrupt (TB0 to 5)
_____ _______ ________
• INT interrupt (INT0 to INT5 )
_____ _____
An INT interrupt selects an edge sense or a level sense. In edge sense, an INT interrupt occurs if
_____ _____
either a rising edge or a falling edge is input to the INT pin. In level sense, an INT interrupt occurs if
_____
either a "H" level or a "L" level is input to the INT pin.
• Intelligent I/O interrupt
• CAN interrupt

High-speed interrupts
High-speed interrupts are interrupts in which the response is executed at 5 cycles and the return is 3
cycles.
When a high-speed interrupt is received, the flag register (FLG) and program counter (PC) are saved to
the save flag register (SVF) and save PC register (SVP) and the program is executed from the address
shown in the vector register (VCT).
Execute an FREIT instruction to return from the high-speed interrupt routine.
High-speed interrupts can be set by setting “1” in the high-speed interrupt specification bit allocated to bit
3 of the exit priority register. Setting “1” in the high-speed interrupt specification bit makes the interrupt set
to level 7 in the interrupt control register a high-speed interrupt.
You can only set one interrupt as a high-speed interrupt. When using a high-speed interrupt, do not set
multiple interrupts as level 7 interrupts. When using high speed interrupt, DMA II cannot be used.
The interrupt vector for a high-speed interrupt must be set in the vector register (VCT).
When using a high-speed interrupt, you can use a maximum of two DMAC channels.
The execution speed is improved when register bank 1 is used with high speed interrupt register selected
by not saving registers to the stack but to the switching register bank. In this case, switch register bank
mode for high-speed interrupt routine.

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Interrupts

Interrupts and Interrupt Vector Tables

If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.9.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table, in which addresses are fixed, and
relocatable vector table, in which addresses can be varied by the setting.

Vector address + 0
AAAAAAAA
AAAAAAAA
MSB
Low address
LSB

Vector address + 1
AAAAAAAA
AAAAAAAA
Mid address

AAAAAAAA
Vector address + 2 High address

0 0 16
Vector address + 3

Figure 1.9.2. Format for specifying interrupt vector addresses

• Fixed vector tables

The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFFDC16 to FFFFFF16. Each vector comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.9.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.

Table 1.9.1. Interrupt factors (fixed interrupt vector addresses)

Interrupt source Vector table addresses Remarks
Address (L) to address (H)
Undefined instruction FFFFDC16 to FFFFDF16 Interrupt on UND instruction
Overflow FFFFE016 to FFFFE316 Interrupt on INTO instruction
BRK instruction FFFFE416 to FFFFE716 If contents of FFFFE716 is filled with FF16, program
execution starts from the address shown by the vector in
the relocatable vector table
Address match FFFFE816 to FFFFEB16 There is an address-matching interrupt enable bit
Watchdog timer FFFFF016 to FFFFF316 Share it with watchdog timer and oscillation stop detect
interrupt
_______ _______
NMI FFFFF816 to FFFFFB16 External interrupt by input to NMI pin
Reset FFFFFC16 to FFFFFF16

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Interrupts

• Vector table dedicated for emulator

Table 1.9.2 shows interrupt vector address, which is vector table register dedicated for emulator (ad-
dress 00002016 to 00002216). These instructions are not effected with interrupt enable flag (I flag)
(non maskable interrupt).
This interrupt is used exclusively for debugger purposes. You normally do not need to use this inter-
rupt. Do not access the interrupt vector table register dedicated for emulator (address 00002016 to
00002216).

Table 1.9.2. Interrupt vector table register for emulator

Interrupt source Vector table addresses Remarks
Address (L) to address (H)
BRK2 instruction Interrupt vector table register for emulator Interrupt for debugger
Single step 00002016 to 00002216

• Relocatable vector tables

The addresses in the relocatable vector table can be modified, according to the user’s settings. Indi-
cate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the
address the INTB indicates becomes the area for the relocatable vector tables. One vector table
comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.9.3
shows the interrupts assigned to the relocatable vector tables and addresses of vector tables.
Set an even address to the start address of vector table setting in INTB so that operating efficiency is
increased.

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Interrupts

Table 1.9.3. Interrupt causes (variable interrupt vector addresses) (1/2)

Softwear interrupt number Vector table address Interrutp source
Address(L)to address(H) (Note 1)
Softwear interrupt number 0 (Note 2) +0 to +3 (000016 to 000316) BRK instruction

Softwear interrupt number 7 +28 to +31 (001C16 to 001F16) A-D channel 1

Softwear interrupt number 8 +32 to +35 (002016 to 002316) DMA0
Softwear interrupt number 9 +36 to +39 (002416 to 002716) DMA1
Softwear interrupt number 10 +40 to +43 (002816 to 002B16) DMA2
Softwear interrupt number 11 +44 to +47 (002C16 to 002F16) DMA3
Softwear interrupt number 12 +48 to +51 (003016 to 003316) Timer A0
Softwear interrupt number 13 +52 to +55 (003416 to 003716) Timer A1
Softwear interrupt number 14 +56 to +59 (003816 to 003B16) Timer A2
Softwear interrupt number 15 +60 to +63 (003C16 to 003F16) Timer A3
Softwear interrupt number 16 +64 to +67 (004016 to 004316) Timer A4
Softwear interrupt number 17 +68 to +71 (004416 to 004716) UART0 transmit/NACK (Note 3)
Softwear interrupt number 18 +72 to +75 (004816 to 004B16) UART0 receive/ACK (Note 3)
Softwear interrupt number 19 +76 to +79 (004C16 to 004F16) UART1 transmit/NACK (Note 3)
Softwear interrupt number 20 +80 to +83 (005016 to 005316) UART1 receive/ACK (Note 3)
Softwear interrupt number 21 +84 to +87 (005416 to 005716) Timer B0
Softwear interrupt number 22 +88 to +91 (005816 to 005B16) Timer B1
Softwear interrupt number 23 +92 to +95 (005C16 to 005F16) Timer B2
Softwear interrupt number 24 +96 to +99 (006016 to 006316) Timer B3
Softwear interrupt number 25 +100 to +103 (006416 to 006716) Timer B4
Softwear interrupt number 26 +104 to +107 (006816 to 006B16) INT5
Softwear interrupt number 27 +108 to +111 (006C16 to 006F16) INT4
Softwear interrupt number 28 +112 to +115 (007016 to 007316) INT3
Softwear interrupt number 29 +116 to +119 (007416 to 007716) INT2
Softwear interrupt number 30 +120 to +123 (007816 to 007B16) INT1
Softwear interrupt number 31 +124 to +127 (007C16 to 007F16) INT0
Softwear interrupt number 32 +128 to +131 (008016 to 008316) Timer B5
Softwear interrupt number 33 +132 to +135 (008416 to 008716) UART2 transmit/NACK (Note 3)
Softwear interrupt number 34 +136 to +139 (008816 to 008B16) UART2 receive/ACK (Note 3)
Softwear interrupt number 35 +140 to +143 (008C16 to 008F16) UART3 transmit/NACK (Note 3)
Softwear interrupt number 36 +144 to +147 (009016 to 009316) UART3 receive/ACK (Note 3)
Softwear interrupt number 37 +148 to +151 (009416 to 009716) UART4 transmit/NACK (Note 3)
Softwear interrupt number 38 +152 to +155 (009816 to 009B16) UART4 receive/ACK (Note 3)
Softwear interrupt number 39 +156 to +159 (009C16 to 009F16) Bus collision detection, start/stop condition
detection (UART2)(Note 3)
Softwear interrupt number 40 +160 to +163 (00A016 to 00A316) Bus collision detection, start/stop condition
detection (UART3/UART0)(Note 3)
Softwear interrupt number 41 +164 to +167 (00A416 to 00A716) Bus collision detection, start/stop condition
detection (UART4/UART1)(Note 3)
Softwear interrupt number 42 +168 to +171 (00A816 to 00AB16) A-D channel 0
Softwear interrupt number 43 +172 to +175 (00AC16 to 00AF16) Key input interrupt
Softwear interrupt number 44 +176 to +179 (00B016 to 00B316) Intelligent I/O interrupt 0
Softwear interrupt number 45 +180 to +183 (00B416 to 00B716) Intelligent I/O interrupt 1
Softwear interrupt number 46 +184 to +187 (00B816 to 00BB16) Intelligent I/O interrupt 2
Softwear interrupt number 47 +188 to +191 (00BC16 to 00BF16) Intelligent I/O interrupt 3
Softwear interrupt number 48 +192 to +195 (00C016 to 00C316) Intelligent I/O interrupt 4
Softwear interrupt number 49 +196 to +199 (00C416 to 00C716) Intelligent I/O interrupt 5
Softwear interrupt number 50 +200 to +203 (00C816 to 00CB16) Intelligent I/O interrupt 6
Softwear interrupt number 51 +204 to +207 (00CC16 to 00CF16) Intelligent I/O interrupt 7
Softwear interrupt number 52 +208 to +211 (00D016 to 00D316) Intelligent I/O interrupt 8
Softwear interrupt number 53 +212 to +215 (00D416 to 00D716) Intelligent I/O interrupt 9/CAN interrupt 0
Softwear interrupt number 54 +216 to +219 (00D816 to 00DB16) Intelligent I/O interrupt 10/CAN interrupt 1

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Interrupts

Table 1.9.3. Interrupt causes (variable interrupt vector addresses) (2/2)

Softwear interrupt number Vector table address Interrutp source
Address(L)to address(H) (Note 1)
Softwear interrupt number 55 +220 to +223 (00DC16 to 00DF16) Softwea interrupt
Softwear interrupt number 56 +224 to +227 (00E016 to 00E316) Softwea interrupt
Softwear interrupt number 57 +228 to +231 (00E416 to 00E716) Intelligent I/O interrupt 11/CAN interrupt 2
Softwear interrupt number 58 (Note 2) +232 to +235 (00E816 to 00EB16) Softwea interrupt
to to
Softwear interrupt number 63 +252 to +255 (00FC16 to 00FF16)
Note 1: Address relative to address in interrupt table register (INTB).
Note 2: Cannot be masked by I flag.
Note 3: When IIC mode is selected, NACK/ACK, start/stop condition detection interrupts are selected. The fault error
____
interrupt is selected when SS pin is selected.

Interrupt request reception

The following lists the conditions under which an interrupt request is acknowledged:
• Interrupt enable flag (I flag) =1
• Interrupt request bit =1
• Interrupt priority level > Processor interrupt priority level (IPL)

The interrupt enable flag (I flag), the processor interrupt priority level (IPL), interrupt request bit and
interrupt priority level select bit are all independent of each other, so they do not affect any other bit.
There are I flag and IPL in flag register (FLG). This flag and bit are described below.

Interrupt Enable Flag (I Flag) and processor Interrupt Priority Level (IPL)
I flag is used to disable/enable maskable interrupts. When this flag is set (= 1), all maskable interrupts
are enabled; when the flag is cleared to 0, they are disabled. This flag is automatically cleared to 0
after a reset.
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
Table 1.9.4 shows interrupt enable levels in relation to the processor interrupt priority level (IPL).

Table 1.9.4. IPL and Interrupt Enable Levels

Processor interrupt priority level (IPL) Enabled interrupt priority levels

IPL2 IPL1 IPL0

0 0 0 Interrupt levels 1 and above are enabled.

0 0 1 Interrupt levels 2 and above are enabled.

0 1 0 Interrupt levels 3 and above are enabled.

0 1 1 Interrupt levels 4 and above are enabled.

1 0 0 Interrupt levels 5 and above are enabled.

1 0 1 Interrupt levels 6 and above are enabled.

1 1 0 Interrupt levels 7 and above are enabled.

1 1 1 All maskable interrupts are disabled.

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Interrupts

Interrupt control registers and Exit priority register

Peripheral I/O interrupts have their own interrupt control registers. Figure 1.9.3 and 1.9.4 show the
interrupt control registers and figure 1.9.5 shows exit priority register.

Interrupt control register

Symbol Address When reset
TAiIC(i=0 to 4) 006C16, 008C16, 006E16, 008E16, 007016 XXXXX0002
TBiIC(i=0 to 5) 009416, 007616, 009616, 007816, 009816, 006916 XXXXX0002
SiTIC(i=0 to 4) 009016, 009216, 008916, 008B16, 008D16 XXXXX0002
SiRIC(i=0 to 4) 007216, 007416, 006B16, 006D16, 006F16 XXXXX0002

AAA
AAAA
BCNiIC(i=0 to 4) 007116, 009116, 008F16, 007116(Note 1), 009116(Note 2) XXXXX0002
DMiIC(i=0 to 3) 006816, 008816, 006A16, 008A16 XXXXX0002
ADiIC(i=0,1) 007316, 008616 XXXXX0002

AAAA
AAA
KUPIC (i=0) 009316 XXXXX0002
b7 b6 b5 b4 b3 b2 b1 b0
IIOiIC(i=0 to 5) 007516, 009516, 007716, 009716, 007916, 009916 XXXXX0002
IIOiIC(i=6 to 11) 007B16, 009B16, 007D16, 009D16, 007F16, 008116 XXXXX0002
CANiIC(i=0 to 2) 009D16, 007F16, 008116 XXXXX0002

AA
A A
Bit symbol Bit name Function R W
ILVL0 Interrupt priority level

AAAA
b2 b1 b0
select bit
000: Level 0 (interrupt disabled)
001: Level 1
ILVL1 010: Level 2
011: Level 3

AA
AA
A A
100: Level 4
ILVL2 101: Level 5
110: Level 6

AAAA
111: Level 7
IR Interrupt request bit 0 : Interrupt not requested
1 : Interrupt requested (Note 3)

Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.

Note 1: UART0 bus collision and start/stop condition detection interrupt control register is shared with UART3.
Note 2: UART1 bus collision and start/stop condition detection interrupt control register is shared with UART4.
Note 3: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).

Figure 1.9.3. Interrupt control register (1)

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Interrupts

AA
A
Interrupt control register

A
AA
b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
INTiIC(i=0 to 2) 009E16, 007E16, 009C16 XX00 X0002
INTiIC(i=3 to 5)(*1) 007C16, 009A16, 007A16 XX00 X0002

AA
Bit symbol Bit name Function R W
ILVL0 Interrupt priority level

AA
b2 b1 b0
select bit
0 0 0 : Level 0 (interrupt disabled)

AA
0 0 1 : Level 1
ILVL1 0 1 0 : Level 2
0 1 1 : Level 3

AA
1 0 0 : Level 4
ILVL2 1 0 1 : Level 5

AA
1 1 0 : Level 6
1 1 1 : Level 7
IR Interrupt request bit 0: Interrupt not requested
1: Interrupt requested (Note 1)

POL Polarity select bit 0 : Selects falling edge or L level

AA
AA
(Note 2) 1 : Selects rising edge or H level

LVS Level sense/edge 0 : Edge sense

sense select bit 1 : Level sense (Note 3)

Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.

Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: When related bit of external interrupt cause select register (address 031F16) are used for both edge,
select the falling edge (=0).
Note 3: When level sense is selected, set related bit of external interrupt cause select register (address 031F16) to
one edge.
*1 When using 16-bit data bus width in microprocessor mode or memory expansion mode, INT3 to INT5 are used
for data bus. In this case, set the interrupt disabled to INT3IC, INT4IC and INT5IC.

Figure 1.9.4. Interrupt control register (2)

Bit 0 to 2: Interrupt Priority Level Select Bits (ILVL0 to ILVL2)

Interrupt priority levels are set by ILVL0 to ILVL2 bits. When an interrupt request is generated, the
interrupt priority level of this interrupt is compared with IPL. This interrupt is enabled only when its
interrupt priority level is greater than IPL. This means that you can disable any particular interrupt by
setting its interrupt priority level to 0.

Bit 3: Interrupt Request Bit (IR)

This bit is set (= 1) by hardware when an interrupt request is generated. The bit is cleared (= 0) by
hardware when the interrupt request is acknowledged and jump to the interrupt vector.
This bit can be cleared (= 0) (but never be set to 1) in software.

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Interrupts

Exit priority register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
RLVL 009F16 XX0X00002

Bit
symbol Bit name Function R W

b2 b1 b0
RLVL0 0 0 0 : Level 0
Interrupt priority set bits 0 0 1 : Level 1
for exiting Stop/Wait 0 1 0 : Level 2
RLVL1 state 0 1 1 : Level 3
(Note 1) 1 0 0 : Level 4
1 0 1 : Level 5
RLVL2 1 1 0 : Level 6
1 1 1 : Level 7

0: Interrupt priority level 7 = normal

High-speed interrupt interrupt
FSIT
set bit (Note 2) 1: Interrupt priority level 7 =
high-speed interrupt

Nothing is assigned.
When write, set "0". When read, its content is indeterminate.

0: Interrupt priority level 7 = normal

DMA II select bit interrupt or high-speed interrupt
DMA II (Note 3) 1: Interrupt priority level 7 =
DMA II transfer

Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.

Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is higher than
that set in the exit priority register.
Set to the same value as the processor interrupt priority level (IPL) set in the flag
register (FLG).
Note 2: The high-speed interrupt can only be specified for interrupts with interrupt priority level
7. Specify interrupt priority level 7 for only one interrupt.
Note 3: Do not set this bit to 0 after once setting it to 1.
When this bit is 1, do not set the high-speed interrupt select bit to 0. (This cannot be
used simultaneously with the high-speed interrupt.)
Transfers by DMAC II are unaffected by the interrupt enable flag (I flag) and processor
interrupt priority level (IPL).

Figure 1.9.5. Exit priority register

Bit 0 to 2: Interrupt priority set bits for exiting Stop/Wait state (RLVL0 to RLVL2)
When using an interrupt to exit Stop mode or Wait mode, the relevant interrupt must be enabled and
set to a priority level above the level set by the RLVL0 to RLVL2 bits. Set the RLVL0 to RLVL2 bits to
the same level as the flag register (FLG) IPL.

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Interrupts

Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SCMPU, SIN, SMOVB, SMOVF, SMOVU,
SSTR, SOUT or RMPA instruction, the processor temporarily suspends the instruction being executed,
and transfers control to the interrupt sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
address 00000016 (address 00000216 when high-speed interrupt). After this, the related interrupt
request bit is "0".
(2) Saves the contents of the flag register (FLG) immediately before the start of interrupt sequence in the
temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag)
to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the contents of the temporary register (Note) within the CPU in the stack area. Saves in the
flag save register (SVF) in high-speed interrupt.
(5) Saves the content of the program counter (PC) in the stack area. Saves in the PC save register
(SVP) in high-speed interrupt.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.

Interrupt Response Time

'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the occur-
rence of an interrupt to the completion of the instruction under execution at that moment (a) and the time
required for executing the interrupt sequence (b). Figure 1.9.6 shows the interrupt response time.

Interrupt request generated Interrupt request acknowledged

Time

Instruction in interrupt
Instruction Interrupt sequence
routine
(a) (b)

Interrupt response time

(a) The period from the occurrence of an interrupt to the completion of the instruction under execution.
(b) The time required for executing the interrupt sequence.

Figure 1.9.6. Interrupt response time

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Interrupts

Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time of
29* cycles.
Time (b) is shown in table 1.9.5.

* It is when the divisor is immediate or register. When the divisor is memory, the following value is
added.
• Normal addressing :2+X
• Index addressing :3+X
• Indirect addressing : 5 + X + 2Y
• Indirect index addressing : 6 + X + 2Y

X is number of wait of the divisor area. Y is number of wait of the indirect address stored area.
When X and Y are in odd address or in 8 bit bus area, double the value of X and Y.

Table 1.9.5 Interrupt Sequence Execution Time

Interrupt Interrupt vector address 16 bits data bus 8 bits data bus
Peripheral I/O Even address 14 cycles 16 cycles
(Note 1) 16 cycles 16 cycles
Odd address
INT instruction Even address 12 cycles 14 cycles
(Note 1) 14 cycles 14 cycles
Odd address
_______
NMI Even address (Note 2) 13 cycles 15 cycles

Watchdog timer

Undefined instruction

Address match

Overflow Even address (Note 2) 14 cycles 16 cycles

BRK instruction (Relocatable vector table) Even address 17 cycles 19 cycles

(Note 1) 19 cycles 19 cycles
Odd address
Single step Even address (Note 2) 19 cycles 21 cycles

BRK2 instruction

BRK instruction (Fixed vector table)

High-speed interrupt (Note 3) Vector table is internal register 5 cycles

Note 1: Allocate interrupt vector addresses in even addresses as much as possible.

Note 2: The vector table is fixed to even address.
Note 3: The high-speed interrupt is independent of these conditions.

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Interrupts

Changes of IPL When Interrupt Request Acknowledged

When an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is
set to the processor interrupt priority level (IPL).
If an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in
Table 1.9.6 is set to the IPL.

Table 1.9.6 Relationship between Interrupts without Interrupt Priority Levels and IPL
Interrupt sources without interrupt priority levels Value that is set to IPL
_______
Watchdog timer, NMI 7
Reset 0
Other Not changed

Saving Registers
In an interrupt sequence, only the contents of the flag register (FLG) and program counter (PC) are
saved to the stack area.
The order in which these contents are saved are as follows: First, the FLG register is saved to the stack
area. Next, the 16 high-order bits and 16 low-order bits of the program counter expanded to 32-bit are
saved. Figure 1.9.7 shows the stack status before an interrupt request is acknowledged and the stack
status after an interrupt request is acknowledged.
In a high-speed interrupt sequence, the contents of the flag register (FLG) are saved to the flag save
register (SVF) and program counter (PC) are saved to PC save register (SVP).
If there are any other registers you want to be saved, save them in software at the beginning of the
interrupt routine. The PUSHM instruction allows you to save all registers except the stack pointer (SP)
by a single instruction.
In high speed interrupt, switch register bank, then register bank 1 is used as high speed interrupt register.
In this case, switch register bank mode for high-speed interrupt routine.

Address Stack area Stack area

Address
MSB LSB MSB LSB

Program counter
m-6 m-6 (PCL)
[SP]
Program counter New stack
m-5 m-5 (PC M) pointer value
Program counter
m–4 m–4 (PC H)

m–3 m–3 0 0
Flag register
m–2 m–2 (FLGL)
Flag register
m–1 m–1 (FLG H)
[SP]
Content of Stack pointer Content of
m previous stack m
value before previous stack
Content of interrupt occurs Content of
m+1 previous stack m+1 previous stack

Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged

Figure 1.9.7. Stack status before and after an interrupt request is acknowledged

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Interrupts

Return from Interrupt Routine

As you execute the REIT instruction at the end of the interrupt routine, the contents of the flag register
(FLG) and program counter (PC) that have been saved to the stack area immediately preceding the
interrupt sequence are automatically restored. In high-speed interrupt, as you execute the FREIT in-
struction at the end of the interrupt routine, the contents of the flag register (FLG) and program counter
(PC) that have been saved to the save registers immediately preceding the interrupt sequence are auto-
matically restored.
Then control returns to the routine that was under execution before the interrupt request was acknowl-
edged, and processing is resumed from where control left off.
If there are any registers you saved via software in the interrupt routine, be sure to restore them using an
instruction (e.g., POPM instruction) before executing the REIT or FREIT instruction.
When switching the register bank before executing REIT and FREIT instruction, switched to the register
bank immediately before the interrupt sequence.

Interrupt Priority
If two or more interrupt requests are sampled active at the same time, the interrupt with the highest
priority will be acknowledged.
Maskable interrupts (Peripheral I/O interrupts) can be assigned any desired priority by setting the inter-
rupt priority level select bit accordingly. If some maskable interrupts are assigned the same priority level,
the priority between these interrupts are resolved by the priority that is set in hardware.
Certain nonmaskable interrupts such as a reset (reset is given the highest priority) and watchdog timer
interrupt have their priority levels set in hardware. Figure 1.9.8 lists the hardware priority levels of these
interrupts.
Software interrupts are not subjected to interrupt priority. They always cause control to branch to an
interrupt routine whenever the relevant instruction is executed.

Interrupt Resolution Circuit

Interrupt resolution circuit selects the highest priority interrupt when two or more interrupt requests are
sampled active at the same time.
Figure 1.9.9 shows the interrupt resolution circuit.

_______
Reset > NMI > Watchdog > Peripheral I/O > Single step > Address match

Figure 1.9.8. Interrupt priority that is set in hardware

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Interrupts

High Priority level of each interrupt

Level 0 (initial value)
A-D1 conversion

DMA0

Bus collision/start, stop

DMA1 condition(UART2)

DMA2 Bus collision/start, stop

condition/fault error (UART0,3)

DMA3 Bus collision/start, stop

condition/fault error (UART1,4)

Timer A0 A-D0 conversion

Timer A1 Key input interrupt

Timer A2 Intelligent I/O interrupt 0

Timer A3 Intelligent I/O interrupt 1

Timer A4 Intelligent I/O interrupt 2

UART0 transmission/NACK Intelligent I/O interrupt 3

UART0 reception/ACK Intelligent I/O interrupt 4

UART1 transmission/NACK Intelligent I/O interrupt 5

UART1 reception/ACK Intelligent I/O interrupt 6

Timer B0 Intelligent I/O interrupt 7

Timer B1 Intelligent I/O interrupt 8

Timer B2 Intelligent I/O interrupt 9

/CAN interrupt 0

Timer B3 Intelligent I/O interrupt 10

/CAN interrupt 1
Timer B4 Intelligent I/O interrupt 11
/CAN interrupt 2
INT5
Stop/wait return interrupt level
INT4 (RLVL)
Interrupt
INT3 request
accepted.
INT2 To CLK
Processor interrupt priority level
(IPL)
INT1

INT0 Interrupt enable flag (I flag)

Interrupt
Instruction fetch request
Timer B5
accepted.
Address match To CPU
UART2 transmission/NACK
Watchdog timer

UART2 reception/ACK DBC

UART3 transmission/NACK NMI

Reset
UART3 reception/ACK

UART4 transmission/NACK

UART4 reception/ACK
Low
Priority of peripheral I/O interrupts
(if priority levels are same)

Figure 1.9.9. Interrupt resolution circuit

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Interrupts

______
INT Interrupts
________ ________
INT0 to INT5 are external input interrupts. The level sense/edge sense switching bits of the interrupt control
register select the input signal level and edge at which the interrupt can be set to occur on input signal level
and input signal edge. The polarity bit selects the polarity.
With the external interrupt input edge sense, the interrupt can be set to occur on both rising and falling
edges by setting the INTi interrupt polarity switch bit of the interrupt request select register (address
031F16) to “1”. When you select both edges, set the polarity switch bit of the corresponding interrupt control
register to the falling edge (“0”).
When you select level sense, set the INTi interrupt polarity switch bit of the interrupt request select register
(address 031F16) to “0”.
Figure 1.9.10 shows the interrupt request select register.

AAA
External interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset

IFSR 031F16 0016

Bit symbol Bit name Function

AA
A R W

AA
A
IFSR0 INT0 interrupt polarity 0 : One edge
select bit (Note) 1 : Both edges

AA
A
IFSR1 INT1 interrupt polarity 0 : One edge
select bit (Note) 1 : Both edges

IFSR2 INT2 interrupt polarity 0 : One edge

AA
A
AA
A
select bit (Note) 1 : Both edges
IFSR3 INT3 interrupt polarity 0 : One edge

AA
A
select bit (Note) 1 : Both edges

IFSR4 INT4 interrupt polarity 0 : One edge

AA
A
select bit (Note) 1 : Both edges

AA
A
IFSR5 INT5 interrupt polarity 0 : One edge
select bit (Note) 1 : Both edges

AA
A
IFSR6 UART0/3 interrupt 0 : UART3 bus collision /start,stop
cause select bit detect/false error detect
1 : UART0 bus collision /start,stop

AA
A
detect/false error detect

AA
A
IFSR7 UART1/4 interrupt 0 : UART4 bus collision /start,stop
cause select bit detect/false error detect
1 : UART1 bus collision /start,stop
detect/false error detect

Note :When level sense is selected, set this bit to "0".

When both edges are selected, set the corresponding polarity switching bit of INT interrupt control
register to "0" (falling edge).

Figure 1.9.10. External interrupt request cause select register

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Interrupts

______
NMI Interrupt
______ ______ ______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03C416).
This pin cannot be used as a normal port input.
Notes:
______ ______ ______
When not intending to use the NMI function, be sure to connect the NMI pin to VCC (pulled-up). The NMI
interrupt is non-maskable. Because it cannot be disabled, the pin must be pulled up.

Key Input Interrupt

If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.9.11 shows the block diagram of the key input interrupt. Note that if an “L”
level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Setting the key input interrupt disable bit (bit 7 at address 03AF16) to “1” disables key input interrupts from
occurring, regardless of the setting in the interrupt control register. When “1” is set in the key input interrupt
disable register, there is no input via the port pin even when the direction register is set to input.

Port P104-P107 pull-up

select bit
Pull-up Key input interrupt control
transistor Port P107 direction (address 009316)
register
register

Port P107 direction register

P107/KI3

Pull-up Port P106 direction

transistor register
Interrupt control Key input interrupt
P106/KI2 circuit request

Pull-up
transistor Port P105 direction
register

P105/KI1

Pull-up Port P104 direction

transistor register

P104/KI0

Figure 1.9.11. Block diagram of key input interrupt

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Interrupts

Address Match Interrupt

An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Four address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL).
Figure 1.9.12 shows the address match interrupt-related registers.
Set the start address of an instruction to the address match interrupt register.
Address match interrupt is not generated when address such as the middle of instruction or table data is
set.

Address match interrupt enable register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset

AAAAAAAAAAAAAA
AIER 000916 XXXX00002

AAAAAAAAAAAAAA
AA
A
Bit symbol Bit name Function RW

AIER0 Address match interrupt 0 0 : Interrupt disabled

AAAAAAAAAAAAAA
AA
A
enable bit 1 : Interrupt enabled

AAAAAAAAAAAAAA
AA
A
AIER1 Address match interrupt 1 0 : Interrupt disabled
enable bit 1 : Interrupt enabled

AAAAAAAAAAAAAA
AA
A
AIER2 Address match interrupt 2 0 : Interrupt disabled
enable bit 1 : Interrupt enabled

AAAAAAAAAAAAAA
AA
A
AIER3 Address match interrupt 3 0 : Interrupt disabled

AAAAAAAAAAAAAA
enable bit 1 : Interrupt enabled

Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.

Address match interrupt register i (i = 0, 1)

(b23) (b16)(b15) (b8)
Symbol Address When reset
b7 b0 b7 b0 b7 b0 RMAD0 001216 to 001016 00000016
RMAD1 001616 to 001416 00000016
RMAD2 001A16 to 001816 00000016
RMAD3 001E16 to 001C16 00000016

Function
Address setting register for address match
interrupt
00000016 to FFFFFF16
AAA
Values that can be set R W

Figure 1.9.12. Address match interrupt-related registers

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Interrupts

Intelligent I/O and CAN Interrupt

Group 0 to 3 intelligent I/O interrupts and CAN interrupt are assigned to software interrupt numbers 44 to 54
and 57.
As intelligent I/O interrupt request, there are base timer interrupt request signals, time measurement inter-
rupt request signals, waveform generation interrupt request signals and interrupt request signals from vari-
ous communication circuits.
Figure 1.9.13 shows the intelligent I/O interrupts and CAN interrupt block diagram, figure 1.9.14 shows the
interrupt request register and figure 1.9.15 shows interrupt enable register.

AAA
AAA
"0"

AAA
D Q "1" Interrupt
Interrupt request A R enable bit A

AAA
Write "0" to interrupt Interrupt
request flag A request bit
"0"

AAA
D Q
R
D Q "1" Interrupt
enable bit B

AAA
Interrupt request B R
Cleared when
Write "0" to interrupt an Interrupt
request flag B

AAA
request
received
"0"

Interrupt request n
Write "0" to interrupt
request flag n
AAA
AAA
D
R
Q

Interrupt request flag

"1" Interrupt
enable bit n

Interrupt request
latch bit
n=A to L

Figure 1.9.13. Intelligent I/O and CAN interrupt block diagram

When using the intelligent I/O or CAN interrupt as an starting factor for DMA II, the interrupt latch bit must be
set to "0" in order to enable only the interrupt request factor used by the interrupt enable register.

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Interrupts

Interrupt request register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
IIOiIR See below 0000 000X2

Bit
symbol Bit name Function R W

Nothing is assigned.
When write, set "0". When read, the content is indeterminate.

0 : Interrupt request not present

IRF1 Interrupt request flag 1
1 : Interrupt request present (Note)

0 : Interrupt request not present

IRF2 Interrupt request flag 2
1 : Interrupt request present (Note)

0 : Interrupt request not present

IRF3 Interrupt request flag 3
1 : Interrupt request presence (Note)

0 : Interrupt request not present

IRF4 Interrupt request flag 4
1 : Interrupt request present (Note)

0 : Interrupt request not present

IRF5 Interrupt request flag 5
1 : Interrupt request present (Note)

0 : Interrupt request not present

IRF6 Interrupt request flag 6
1 : Interrupt request present (Note)

0 : Interrupt request not present

IRF7 Interrupt request flag 7
1 : Interrupt request present (Note)

Note: "0" can be written.

Interrupt request register table

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Symbol Address (IRF7) (IRF6) (IRF5) (IRF4) (IRF3) (IRF2) (IRF1) -
IIO0IR 00A016 - - SIO0r G0RI - PO13 TM02 -
IIO1IR 00A116 - - SIO0t G0TO - PO14 TM00/PO00 -
IIO2IR 00A216 - - SIO1r G1RI - TM12/PO12 - -
IIO3IR 00A316 - - SIO1t G1TO PO27 PO10 TM03 -
IIO4IR 00A416 BEAN0 BEAN1 - BT1 PO32 TM17/PO17 TM04/PO04 -
IIO5IR 00A516 - - - SIO2r PO33 PO21 TM05/PO05 -
IIO6IR 00A616 - - - SIO2t PO34 PO20 TM06 -
IIO7IR 00A716 IE0 - - BT0 PO35 PO22 TM07 -
IIO8IR 00A816 IE1 IE2 - BT2 PO36 PO23 TM11/PO11 -
IIO9IR 00A916 CAN0 - - - PO31 PO24 PO15 -
IIO10IR 00AA16 CAN1 - - - PO30 PO25 TM16/PO16 -
IIO11IR 00AB16 CAN2 - - BT3 PO37 PO26 TM01/PO01 -
BTi : Interrupt request from base timer of intelligent I/O group i
TMij : Interrupt request from time measurement function ch j of intelligent I/O group i
POij : Interrupt request from waveform generator function ch j of intelligent I/O group i
SIOir/SIOit : Interrupt request from communication function of intelligent I/O group i (r:reception, t:transmission)
GiTO/GiRI : Interrupt request from HDLC data processing function of intelligent I/O group i
(RI:reception input, TO:transmission output)
BEANi : Interrupt request from special communication function of intelligent I/O group i (i=0,1)
IE : Interrupt request from IEBus communication function of intelligent I/O group 2
CANi : Interrupt request from AN communication function (i=0 to 2)
- : Nothing is assigned in this bit.

Figure 1.9.14. Interrupt request registers

Bit 1 to bit 7: Interrupt request flag (IRF1 to IRF7)

To retain respective interrupt requests and judge interrupt kind occurred in the interrupt process rou-
tine.

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Interrupts

Interrupt enable register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
IIOiIE See below 0016

Bit
symbol Bit name Function R W

0: Interrupt request is not latched(used by DMA II)

IRLT Interrupt request latch bit
1: Interrupt request is latched(used by interrupt)

0: Interrupt of corresponding interrupt

ITE1 Interrupt enable bit 1 request flag (IRF1) disabled
1: Interrupt of corresponding interrupt
request flag (IRF1) enabled
0: Interrupt of corresponding interrupt
ITE2 Interrupt enable bit 2 request flag (IRF2) disabled
1: Interrupt of corresponding interrupt
request flag (IRF2) enabled
0: Interrupt of corresponding interrupt
ITE3 Interrupt enable bit 3 request flag (IRF3) disabled
1: Interrupt of corresponding interrupt
request flag (IRF3) enabled
0: Interrupt of corresponding interrupt
ITE4 Interrupt enable bit 4 request flag (IRF4) disabled
1: Interrupt of corresponding interrupt
request flag (IRF4) enabled
0: Interrupt of corresponding interrupt
ITE5 Interrupt enable bit 5 request flag (IRF5) disabled
1: Interrupt of corresponding interrupt
request flag (IRF5) enabled
0: Interrupt of corresponding interrupt
ITE6 Interrupt enable bit 6 request flag (IRF6) disabled
1: Interrupt of corresponding interrupt
request flag (IRF6) enabled
0: Interrupt of corresponding interrupt
request flag (IRF7) disabled
ITE7 Interrupt enable bit 7
1: Interrupt of corresponding interrupt
request flag (IRF7) enabled

Interrupt request register table

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit1
Symbol Address (ITE7) (ITE6) (ITE5) (ITE4) (ITE3) (ITE2) (ITE1) (IRLT)
IIO0IE 00B016 - - SIO0r G0RI - PO13 TM02 IRLT
IIO1IE 00B116 - - SIO0t G0TO - PO14 TM00/PO00 IRLT
IIO2IE 00B216 - - SIO1r G1RI - TM12/PO12 - IRLT
IIO3IE 00B316 - - SIO1t G1TO PO27 PO10 TM03 IRLT
IIO4IE 00B416 BEAN0 BEAN1 - BT1 PO32 TM17/PO17 TM04/PO04 IRLT
IIO5IE 00B516 - - - SIO2r PO33 PO21 TM05/PO05 IRLT
IIO6IE 00B616 - - - SIO2t PO34 PO20 TM06 IRLT
IIO7IE 00B716 IE0 - - BT0 PO35 PO22 TM07 IRLT
IIO8IE 00B816 IE1 IE2 - BT2 PO36 PO23 TM11/PO11 IRLT
IIO9IE 00B916 CAN0 - - - PO31 PO24 PO15 IRLT
IIO10IE 00BA16 CAN1 - - - PO30 PO25 TM16/PO16 IRLT
IIO11IE 00BB16 CAN2 - - BT3 PO37 PO26 TM01/PO01 IRLT
BTi : Interrupt request from base timer of intelligent I/O group i is enabled
TMij : Interrupt request from time measurement function ch j of intelligent I/O group i is enabled
POij : Interrupt request from waveform generator function ch j of intelligent I/O group i is enabled
SIOir/SIOit : Interrupt request from communication function of intelligent I/O group i (r:reception, t:transmission) is enabled
GiTO/GiRI : Interrupt request from HDLC data processing function of intelligent I/O group i (RI:reception input,
TO:transmission output) is enabled
BEANi : Interrupt request from special communication function of intelligent I/O group i (i=0,1) is enabled
IE : Interrupt request from IEBus communication function of intelligent I/O group 2 is enabled
CANi : Interrupt request from CAN communication function (i=0 to 2) is enabled
- : Nothing is assigned in this bit. (Set "0" to these bits.)

Figure 1.9.15. Interrupt enable registers

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Interrupts

Bit 0: Interrupt request latch bit (IRLT)

An interrupt signal or latched signal of the interrupt signal is selected as an interrupt request signal.
When the latched signal of an interrupt signal is used, this flag must be set to "0" after interrupt request
flag is read in interrupt process routine, . If this flag is not set to "0" and interrupt process is completed,
although interrupt request occurs again, interrupt will not occur.

Bit 1 to bit 7: Interrupt enable bit (ITE 1 to ITE 7)

To enable/disable respective interrupts.

Precautions for Interrupts

(1) Reading addresses 00000016 and 00000216
• When maskable interrupt occurs, CPU reads the interrupt information (the interrupt number and inter-
rupt request level) in the interrupt sequence from address 00000016. When a high-speed interrupt
occurs, CPU reads from address 00000216.
The interrupt request bit of the certain interrupt will then be set to “0”.
However, reading addresses 00000016 and 00000216 by software does not set request bit to “0”.

(2) Setting the stack pointer

• The value of the stack pointer immediately after reset is initialized to 00000016. Accepting an interrupt
before setting a value in the stack pointer may cause runaway. Be sure to set a value in the stack
_______
pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the
_______
beginning of a program. Any interrupt including the NMI interrupt is generated immediately after ex-
ecuting the first instruction after reset. Set an even number to the stack pointer. Set an even address
to the stack pointer so that operating efficiency is increased.

_______
(3) The NMI interrupt
_______
• As for the NMI interrupt pin, this interrupt cannot be disabled. Connect it to the Vcc pin via a pull-up
resistor if unused.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input.
_______
• A low level signal with more than 1 clock cycle (BCLK) is necessary for NMI pin.

(4) External interrupt

• Edge sense
Either a low level or a high level for at least 250 ns is necessary for the signal input to pins INT0
to INT5 regardless of the CPU operation clock.
• Level sense
Either a low level or a high level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal
input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=20MHz and no division
mode, at least 250 ns width is necessary.)

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Interrupts

• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 1.9.12 shows the procedure for
______
changing the INT interrupt generate factor.

Set the interrupt priority level to level 0

(Disable INTi interrupt)

Set the polarity select bit

Clear the interrupt request bit to “0”

Set the interrupt priority level to level 1 to 7

(Enable the accepting of INTi interrupt request)

______
Figure 1.9.16. Switching condition of INT interrupt request

(5) Rewrite the interrupt control register

• When an instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET

(6) Rewrite interrupt request register

• When writing to "0" to this register, the following instructions must be used.
Instructions : AND, BCLR

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Watchdog Timer

Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a
watchdog timer interrupt is generated or reset is selected when an underflow occurs in the watchdog timer.
Watchdog timer interrupt is selected when bit 6 (CM06) of the system control register 0 (address 000816) is
"0" and reset is selected when CM06 is "1". No value other than "1" can be written in CM06. Once reset is
selected (CM06="1"), watchdog timer interrupt cannot be selected by software.
When XIN is selected for the BCLK, bit 7 (WDC7) of the watchdog timer control register (address 000F16)
selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is
set for division by 2 regardless of WDC7. Therefore, the watchdog timer cycle can be calculated as follows.
However, errors can arise in the watchdog timer cycle due to the prescaler.

When XIN is selected in BCLK

Prescaler division ratio (16 or 128) x watchdog timer count (32768)
Watchdog timer cycle =
BCLK
When XCIN is selected in BCLK
Prescaler division ratio (2) x watchdog timer count (32768)
Watchdog timer cycle =
BCLK

For example, when BCLK is 20MHz and the prescaler division ratio is set to 16, the monitor timer cycle is
approximately 26.2 ms, and approximately 17.5 ms when BCLK is 30MHz.

The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16). CM06 is initialized only at reset. After reset,
watchdog timer interrupt is selected.
The watchdog timer and the prescaler stop in stop mode, wait mode and hold status. After exiting these
modes and status, counting starts from the previous value.
In the stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released. Figure 1.10.1 shows the block diagram
of the watchdog timer. Figure 1.10.2 and 1.10.3 show the watchdog timer-related registers.

Prescaler
“CM07 = 0”
“WDC7 = 0” "CM06=0"
1/16 Watchdog timer
interrupt request
“CM07 = 0”
BCLK “WDC7 = 1”
1/128 Watchdog timer
HOLD

“CM07 = 1” "CM06=1"
1/2 Reset

Write to the watchdog timer

start register Set to
(address 000E16) “7FFF16”

RESET

Figure 1.10.1. Block diagram of watchdog timer

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Watchdog Timer

Watchdog timer control register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 0 WDC 000F16 000XXXXX2

Bit
symbol Bit name Function R W

High-order bit of watchdog timer

Reserved bit Must always be set to "0"

Prescaler select bit 0 : Divided by 16

WDC7
1 : Divided by 128

Watchdog timer start register

b7 b0 Symbol Address When reset
WDTS 000E16 Indeterminate

Function R W
The watchdog timer is initialized and starts counting after a write
instruction to this register. The watchdog timer value is always initialized
to "7FFF16" regardless of the value written.

Figure 1.10.2. Watchdog timer control and start registers

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Watchdog Timer

System clock control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
CM0 000616 0000 X0002

Bit symbol Bit Function

AA RW

AA
name b1 b0
CM00 Clock output function 0 0 : I/O port P53
select bit (Note 2) 0 1 : fC output
CM01 1 0 : f8 output
1 1 : f32 output

AA
CM02 WAIT peripheral 0 : Do not stop peripheral clock
function clock stop bit in wait mode
1 : Stop peripheral clock in
wait mode (Note 3)

A A
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.

A A
CM04 Port XC select bit 0 : I/O port
1 : XCIN-XCOUT generation (Note 4)

A A
CM05 Main clock (XIN-XOUT) 0 : Main clock On
stop bit (Note 5) 1 : Main clock Off (Note 6)

A
AA
Watchdog timer 0 : Watchdog timer interrupt
CM06
function select bit 1 : Reset (Note 7)

A
AA
System clock select bit 0 : XIN, XOUT
CM07 (Note 8) 1 : XCIN, XCOUT

Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: The port P53 dose not function as an I/O port in microprocessor or memory expansion
mode.
When outputting ALE to P53 (bits 5 and 4 of processor mode register 0 is "01"), set
these bits to "00".
The port P53 function is not selected, even when you set "00" in microprocessor or
memory expansion mode and bit 7 of the processor mode register 0 is "1".
Note 3: fc32 is not included. When this bit is set to "1", PLL cannot be used in WAIT.
Note 4: When XcIN-XcOUT is used, set port P86 and P87 to no pull-up resistance with the input
port.
Note 5: When entering the power saving mode, the main clock is stopped using this bit. To stop
the main clock, set system clock stop bit (CM07) to "1" while an oscillation of sub clock is
stable. Then set this bit to "1".
When XIN is used after returning from stop mode, set this bit to "0".
When this bit is "1", XOUT is "H". Also, the internal feedback resistance remains ON, so
XIN is pulled up to XOUT ("H" level) via the feedback resistance.
Note 6: When the main clock is stopped, the main clock division register (address 000C16) is set
to the division by 8 mode.
However, in ring oscillator mode, the main clock division register is not set to the division
by 8 mode when XIN-XOUT is stopped by this bit.
Note 7: When "1" has been set once, "0" cannot be written by software.
Note 8: Set this bit "0" to "1" when sub clock oscillation is stable by setting CM04 to "1".
Set this bit "1" to "0" when main clock oscillation is stable by setting CM05 to "0".
Do not set CM04 and CM05 simultaneously.

Figure 1.10.3. System clock control register 0

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DMAC

DMAC
This microcomputer has four DMAC (direct memory access controller) channels that allow data to be sent
to memory without using the CPU. DMAC is a function that transmit delete data of a source address (8 bits
/16 bits) to a destination address when transmission request occurs. When using three or more DMAC
channels, the register bank 1 and high-speed interrupt register are used as DMAC registers. If you are
using three or more DMAC channels, you cannot use high-speed interrupts. The CPU and DMAC use the
same data bus, but the DMAC has a higher bus access privilege than the CPU, and because of the use of
cycle-steeling, operations are performed at high-speed from the occurrence of a transfer request until one
word (16 bits) or 1 byte (8 bits) of data have been sent. Figure 1.11.1 shows the mapping of registers used
by the DMAC. Table 1.11.1 shows DMAC specifications. Figures 1.11.2 to 1.11.5 show the structures of the
registers used.
As the registers shown in Figure 1.11.1 are allocated in the CPU, use LDC instruction when writing. When
writing to DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3, set register bank select flag (B flag) to "1" and use
MOV instruction to set R0 to R3, A0 and A1 registers. When writing to DSA2 and DSA3, set register bank
select flag (B flag) to "1" and use LDC instruction to set SB and FB registers.

DMAC related registers

DMD0
DMA mode register 0, 1
DMD1
DCT0
DMA 0, 1 transfer count register
DCT1

DRC0
DMA 0, 1 transfer count reload register
DRC1
DMA0
DMA 0, 1 memory address register
DMA1
DSA0
DMA 0, 1 SFR address register
DSA1
DRA0
DMA 0, 1 memory address reload register
DRA1

When using three or more DMAC channels When using three or more DMAC channels
The register bank 1 is used as a DMAC register The high-speed interrupt register is used as a DMAC
register
DCT2 (R0) DMA2 transfer count register SVF Flag save register

DCT3 (R1) DMA3 transfer count register DRA2 (SVP) DMA2 memory address reload register

DRC2 (R2) DMA2 transfer count reload register DRA1 (VCT) DMA3 memory address reload register
DRC3 (R3) DMA3 transfer count reload register

DMA2 (A0) DMA2 memory address register

When using DMA2 and DMA3, use the CPU
DMA3 (A1) DMA3 memory address register registers shown in parentheses.
DSA2 (SB) DMA2 SFR address register
DSA3 (FB) DMA3 SFR address register

Figure 1.11.1. Register map using DMAC

In addition to writing to the software DMA request bit to start DMAC transfer, the interrupt request signals
output from the functions specified in the DMA request factor select bits are also used. However, in contrast
to the interrupt requests, repeated DMA requests can be received, regardless of the interrupt flag.
(Note, however, that the number of actual transfers may not match the number of transfer requests if the
DMA request cycle is shorter than the DMR transfer cycle. For details, see the description of the DMAC
request bit.)

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DMAC

Table 1.11.1. DMAC specifications

Item Specification
No. of channels 4 (cycle steal method)
Transfer memory space • From any address in the 16 Mbytes space to a fixed address (16
Mbytes space)
• From a fixed address (16 Mbytes space) to any address in the 16 M
bytes space
Maximum No. of bytes transferred 128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
________ ________
DMA request factors (Note) Falling edge of INT0 to INT3 or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 to UART4 transmission and reception interrupt requests
A-D conversion interrupt requests
Intelligent I/O interrupt
Software triggers
Channel priority DMA0 > DMA1 > DMA2 > DMA3 (DMA0 is the first priority)
Transfer unit 8 bits or 16 bits
Transfer address direction forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode • Single transfer
Transfer ends when the transfer count register is "000016".
• Repeat transfer
When the transfer counter is "000016", the value in the transfer
counter reload register is reloaded into the transfer counter and the
DMA transfer is continued
DMA interrupt request generation timing When the transfer counter register changes from "000116" to "000016".
DMA startup • Single transfer
Transfer starts when DMA transfer count register is more than
"000116" and the DMA is requested after “012” is written to the
channel i transfer mode select bits
• Repeat transfer
Transfer starts when the DMA is requested after “112” is written to the
channel i transfer mode select bits
DMA shutdown • Single transfer
When “002” is written to the channel i transfer mode select bits and
DMA transfer count register becomes "000016" by DMA transfer or
write
• Repeat transfer
When “002” is written to the channel i transfer mode select bits
Reload timing When the transfer counter register changes from "000116" to "000016" in
repeat transfer mode.
Reading / writing the register Registers are always read/write enabled.
Number of DMA transfer cycles Between SFR and internal RAM : 3 cycles
Between external I/O and external memory : minimum 3 cycles
Note: DMA transfer doed not affect any interrupt.

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DMAC

DMAi request cause select register (i=0 to 3)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
DMiSL(i=0 to 3) 037816, 037916, 037A16, 037B16 0X0000002

Bit
symbol Bit name Function R W

DSEL0

DSEL1

DSEL2 DMA request cause Refer to function table

select bit
(Note 1)
DSEL3

DSEL4

If software trigger is selected, a DMA request

Software DMA
DSR is generated by setting this bit to "1" (When
request bit (Note 2)
read, the value of this bit is always "0")
Nothing is assigned. When write, set "0".
When read, its content is indeterminate.

0 : Not requested
DRQ DMA request bit
(Note 2, 3) 1 : Requested
Note 1: Set DMA inhibit before changing the DMA request cause. Set DRQ bit to "1" simultaneously.
e.g.) MOV.B #083h, DMiSL ; Set timer A0
Note 2: When setting DSR to "1", set DRQ bit to "1" using OR instruction etc. simultaneously.
e.g.) OR.B #0A0h, DMiSL
Note 3: Do not write "0" to this bit. There is no need to clear the DMA request bit.

Figure 1.11.2. DMAC register (1)

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DMAC

Table 1.11.2. DMAi request cause select register function

Setting value DMA request cause
b4 b3 b2 b1 b0 DMA0 DMA1 DMA2 DMA3
0 0 0 0 0 Software trigger
0 0 0 0 1 Falling edge of INT0 pin Falling edge of INT1 pin Falling edge of INT2 pin Falling edge of INT3 pin (Note 1)
0 0 0 1 0 Both edges of INT0 Both edges of INT1 Both edges of INT2 Both edges of INT3 (Note 1)
0 0 0 1 1 Timer A0
0 0 1 0 0 Timer A1
0 0 1 0 1 Timer A2
0 0 1 1 0 Timer A3
0 0 1 1 1 Timer A4
0 1 0 0 0 Timer B0
0 1 0 0 1 Timer B1
0 1 0 1 0 Timer B2
0 1 0 1 1 Timer B3
0 1 1 0 0 Timer B4
0 1 1 0 1 Timer B5
0 1 1 1 0 UART0 transmit
0 1 1 1 1 UART0 receive /ACK (Note 2)
1 0 0 0 0 UART1 transmit
1 0 0 0 1 UART1 receive /ACK (Note 2)
1 0 0 1 0 UART2 transmit
1 0 0 1 1 UART2 receive /ACK (Note 2)
1 0 1 0 0 UART3 transmit
1 0 1 0 1 UART3 receive /ACK (Note 2)
1 0 1 1 0 UART4 transmit
1 0 1 1 1 UART4 receive /ACK (Note 2)
1 1 0 0 0 A-D0 A-D1 A-D0 A-D1
1 1 0 0 1 Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt
control register 0 control register 7 control register 2 control register 9

1 1 0 1 0 Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt
control register 1 control register 8 control register 3 control register 10

1 1 0 1 1 Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt
control register 2 control register 9 control register 4 control register 11

1 1 1 0 0 Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt
control register 3 control register 10 control register 5 control register 0

1 1 1 0 1 Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt
control register 4 control register 11 control register 6 control register 1

1 1 1 1 0 Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt
control register 5 control register 0 control register 7 control register 2

1 1 1 1 1 Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt Intelligent I/O interrupt
control register 6 control register 1 control register 8 control register 3

Note 1: When INT3 pin is data bus in microprocessor mode, INT3 edge cannot be used as DMA3 request cause.
Note 2: UARTi receive /ACK switched by setting of UARTi special mode register and UARTi special mode
register 2 (i=0 to 3)

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DMAC

DMA mode register 0

(CPU internal register)
b7 b6 b5 b4 b3 b2 b1 b0 Symbol When reset
DMD0 0016

AA
Bit symbol Bit name Function R W

A A
Channel 0 transfer b1 b0
MD00 0 0 : DMA inhibit
mode select bit
0 1 : Single transfer

AA
MD01 1 0 : Must not be set
1 1 : Repeat transfer

A
AA
BW0 Channel 0 transfer 0 : 8 bits
unit select bit 1 : 16 bits

A
AA
RW0 Channel 0 transfer 0 : Fixed address to memory (forward direction)
direction select bit 1 : Memory (forward direction) to fixed address

A
AA
b5 b4
MD10 Channel 1 transfer
0 0 : DMA inhibit

A A
mode select bit
0 1 : Single transfer
MD11 1 0 : Must not be set

A A
1 1 : Repeat transfer

BW1 Channel 1 transfer 0 : 8 bits

AA
unit select bit 1 : 16 bits
RW1 Channel 1 transfer 0 : Fixed address to memory (forward direction)
direction select bit 1 : Memory (forward direction) to fixed address

DMA mode register 1

(CPU internal register)
b7 b6 b5 b4 b3 b2 b1 b0 Symbol When reset
DMD1 0016

A A
Bit symbol Bit name Function R W
Channel 2 transfer b1 b0
MD20

AA
mode select bit 0 0 : DMA inhibit
0 1 : Single transfer
MD21 1 0 : Must not be set

A A
1 1 : Repeat transfer

Channel 2 transfer 0 : 8 bits

AA
BW2
unit select bit 1 : 16 bits

A A
RW2 Channel 2 transfer 0 : Fixed address to memory (forward direction)
direction select bit 1 : Memory (forward direction) to fixed address

A A
MD30 Channel 3 transfer b5 b4
mode select bit 0 0 : DMA inhibit
0 1 : Single transfer

A
AA
MD31 1 0 : Must not be set
1 1 : Repeat transfer

A
AA
BW3 Channel 3 transfer 0 : 8 bits
unit select bit 1 : 16 bits

A
AA
RW3 Channel 3 transfer 0 : Fixed address to memory (forward direction)
direction select bit 1 : Memory (forward direction) to fixed address

Figure 1.11.3. DMAC register (2)

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DMAC

DMAi transfer count register (i = 0 to 3)

(CPU internal register)
Symbol Address When reset
b15 b0 DCT0 (Note 2) (CPU internal register) XXXX16
DCT1 (Note 2) (CPU internal register) XXXX16
DCT2 (bank 1;R0) (Note 3) (CPU internal register) 000016
DCT3 (bank 1;R1) (Note 3) (CPU internal register) 000016

AA
Function Setting range R W

Set transfer number 000016 to FFFF16

Note 1: When "0" is set to this register, data transfer is not done even if DMA
is requested.
Note 2: Use LDC instruction to write to this register.
Note 3: When setting DCT2 and DCT3, set "1" to the register bank select flag
(B flag) of flag register (FLG), then set desired value to R0 and R1 of
register bank 1. Use MOV instruction to write to this register.

DMAi transfer count reload register (i = 0 to 3)

(CPU internal register)
Symbol Address When reset
b15 b0 DRC0 (Note 1) (CPU internal register) XXXX16
DRC1 (Note 1) (CPU internal register) XXXX16
DRC2 (bank 1;R2) (Note 2) (CPU internal register) 000016
DRC3 (bank 1;R3) (Note 2) (CPU internal register) 000016

AA
A
Function Setting range RW

Set transfer number

Note 1: Use LDC instruction to write to this register.

000016 to FFFF16

Note 2: When setting DRC2 and DRC3, set "1" to the register bank select
A
AA
flag (B flag) of flag register (FLG), then set desired value to R2 and
R3 of register bank 1. Use MOV instruction to write to this register.

Figure 1.11.4. DMAC register (3)

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DMAC

DMAi memory address register (i = 0 to 3)

(CPU internal register)
Symbol Address When reset
b23 b0 DMA0 (Note 2) (CPU internal register) XXXXXX16
DMA1 (Note 2) (CPU internal register) XXXXXX16
DMA2 (bank 1;A0) (Note 3) (CPU internal register) 00000016
DMA3 (bank 1;A1) (Note 3) (CPU internal register) 00000016

Function

Set source or destination memory address

(Note 1)
Setting range

00000016 to FFFFFF16
(16 Mbytes area)
AA
A
R W

A
AA
Note 1: When the transfer direction select bit is "0" (fixed address to memory), this register
is destination memory address.
When the transfer direction select bit is "1" (memory to fixed address), this register
is source memory address.
Note 2: Use LDC instruction to write to this register.
Note 3: When setting DMA2 and DMA3, set "1" to the register bank select flag (B flag) of
flag register (FLG), and set desired value to A0 and A1 of register bank 1. Use
MOV instruction to write to this register.

DMAi SFR address register (i = 0 to 3)

(CPU internal register)
Symbol Address When reset
b23 b0 DSA0 (Note 2) (CPU internal register) XXXXXX16
DSA1 (Note 2) (CPU internal register) XXXXXX16
DSA2 (bank 1;SB) (Note 3) (CPU internal register) 00000016
DSA3 (bank 1;FB) (Note 4) (CPU internal register) 00000016

AA
Function Setting range RW

00000016 to FFFFFF16
Set source or destination fixed address (16 Mbytes area)
(Note 1)

Note 1: When the transfer direction select bit is "0" (fixed address to memory), this register
is source fixed address.
When the transfer direction select bit is "1" (memory to fixed address), this register
is destination fixed address.
Note 2: Use LDC instruction to write to this register.
Note 3: When setting DSA2, set "1" to the register bank select flag (B flag) of flag register
(FLG), and set desired value to SB of register bank 1. Use LDC instruction to write
to this register.
Note 4: When setting DSA3, set "1" to the register bank select flag (B flag) of flag register
(FLG), and set desired value to FB of register bank 1. Use LDC instruction to write
to this register.

DMAi memory address reload register (i = 0 to 3) (Note 1)

(CPU internal register)
Symbol Address When reset
b23 b0
DRA0 (CPU internal register) XXXXXX16
DRA1 (CPU internal register) XXXXXX16
DRA2 (bank 1;SVP) (Note 2) (CPU internal register) XXXXXX16
DRA3 (bank 1;VCT) (Note 3) (CPU internal register) XXXXXX16

AA
Function Setting range R W

Set source or destination memory address 00000016 to FFFFFF16

(16 Mbytes area)

Note 1: Use LDC instruction to write to this register.

Note 2: When setting DRA2, set desired value to save PC register (SVP).
Note 3: When setting DRA3, set desired value to vector register (VCT).

Figure 1.11.5. DMAC register (4)

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DMAC

(1) Transfer cycle

The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle is longer when software waits are inserted.

(a) Effect of source and destination addresses

When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.

(b) Effect of external data bus width control register

When in memory expansion mode or microprocessor mode, the transfer cycle changes according to
the data bus width at the source and destination.
1. When transferring 16 bits of data and the data bus width at the source and at the destination is 8
bits (data bus width bit = “0”), there are two 8-bit data transfers. Therefore, two bus cycles are
required for reading and two cycles for writing.
2. When transferring 16 bits of data and the data bus width at the source is 8 bits (data bus width bit
= “0”) and the data bus width at the destination is 16 bits (data bus width bit = “1”), the data is read
in two 8-bit blocks and written as 16-bit data. Therefore, two bus cycles are required for reading
and one cycle for writing.
3. When transferring 16 bits of data and the data bus width at the source is 16 bits (data bus width bit
= “1”) and the data bus width at the destination is 8 bits (data bus width bit = “0”), 16 bits of data are
read and written as two 8-bit blocks. Therefore, one bus cycle is required for reading and two
cycles for writing.

(c) Effect of software wait

When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the soffware wait by 1 bus cycle. The length of the cycle is determined by BCLK.

Figure 1.11.6 shows the example of the transfer cycles for a source read. Figure 1.11.6 shows the desti-
nation is external area, the destination write cycle is shown as two cycle (one bus cycle) and the source
read cycles for the different conditions. In reality, the destination write cycle is subject to the same condi-
tions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer
cycle, remember to apply the respective conditions to both the destination write cycle and the source read
cycle. For example (2) in Figure 1.11.6, if data is being transferred in 16-bit units on an 8-bit bus, two bus
cycles are required for both the source read cycle and the destination write cycle.

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DMAC

(1) •When 8-bit data is transferred

•When 16-bit data is transferred on a 16-bit data bus and the source address is even

BCLK

Address
CPU use Source Destination CPU use
bus

RD signal

WR signal

Data
CPU use Source Destination CPU use
bus

(2) •When 16-bit data is transferred and the source address is odd
•When 16-bit data is transferred and the width of data bus at the source is 8-bit
(When the width of data bus at the destination is 8-bit, there are also two destination write cycles).

BCLK

Address
CPU use Source Source + 1 Destination CPU use
bus

RD signal

WR signal

Data CPU use Source CPU use

Source + 1 Destination
bus

(3) •When one wait is inserted into the source read under the conditions in (1)

BCLK

Address Source Destination

CPU use CPU use
bus

RD signal

WR signal

Data
CPU use Source Destination CPU use
bus

(4) •When one wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred and the width of data but at the destination is 8-bit, there are
two destination write cycles).

BCLK

Address
CPU use Source Source + 1 Destination CPU use
bus

RD signal

WR signal

Data
CPU use Source Source + 1 Destination CPU use
bus

Note: The same timing changes occur with the respective conditions at the destination as at the source.

Figure 1.11.6. Example of the transfer cycles for a source read

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DMAC

(2) DMAC transfer cycles

Any combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:

No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k

Table 1.11.2. No. of DMAC transfer cycles

Single-chip mode Memory expansion mode

Transfer unit Bus width Access address Microprocessor mode
No. of read No. of write No. of read No. of write
cycles cycles cycles cycles
16-bit Even 1 1 1 1
8-bit transfers (DSi = “1”) Odd 1 1 1 1
(BWi = “0”) 8-bit Even — — 1 1
(DSi = “0”) Odd — — 1 1
16-bit Even 1 1 1 1
16-bit transfers (DSi = “1”) Odd 2 2 2 2
(BWi = “1”) 8-bit Even — — 2 2
(DSi = “0”) Odd — — 2 2

Coefficient j, k
Coefficient j Coefficient k
Internal memory Internal ROM/RAM No wait 1 1
Internal ROM/RAM One wait 2 2
SFR area 2 2
External memory Separate bus No wait 1 2
Separate bus One wait 2 2
Separate bus Two waits 3 3
Separate bus Three waits 4 4
Multiplex bus 3 3

DMA Request Bit

The DMAC can issue DMA requests using preselected DMA request factors for each channel as triggers.
The DMA transfer request factors include the reception of DMA request signals from the internal periph-
eral functions, software DMA factors generated by the program, and external factors using input from
external interrupt signals.
See the description of the DMAi factor selection register for details of how to select DMA request factors.
DMA requests are received as DMA requests when the DMAi request bit is set to “1” and the channel i
transfer mode select bits are “01” or “11”. Therefore, even if the DMAi request bit is “1”, no DMA request
is received if the channel i transfer mode select bit is “00”. In this case, DMAi request bit is cleared.
Because the channel i transfer mode select bits default to “00” after a reset, remember to set the channel
i transfer mode select bit for the channel to be activated after setting the DMAC related registers. This
enables receipt of the DMA requests for that channel, and DMA transfers are then performed when the
DMAi request bit is set.
The following describes when the DMAi request bit is set and cleared.

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DMAC

(1) Internal factors

The DMAi request flag is set to “1” in response to internal factors at the same time as the interrupt
request bit of the interrupt control register for each factor is set. This is because, except for software
trigger DMA factors, they use the interrupt request signals output by each function.
The DMAi request bit is cleared to "0" when the DMA transfer starts or the DMA transfer is disabled
(channel i transfer mode select bits are "00" and the DMAi transfer count register is "0").

(2) External factors

______
These are DMA request factors that are generated by the input edge from the INTi pin (where i indi-
______
cates the DMAC channel). When the INTi pin is selected by the DMAi request factor select bit as an
external factor, the inputs from these pins become the DMA request signals.
When an external factor is selected, the DMAi request bit is set, according to the function specified in the
______
DMA request factor select bit, on either the falling edge of the signal input via the INTi pins, or both edges.
When an external factor is selected, the DMAi request bit is cleared, in the same way as the DMAi
request bit is cleared for internal factors, when the DMA transfer starts or the DMA transfer is in
disable state.

(3) Relationship between external factor request input and DMAi request bits, and DMA transfer timing
When the request inputs to DMAi occur in the same sampling cycle (between the falling edge of BCLK
and the next falling edge), the DMAi request bits are set simultaneously, but if the DMAi enable bits
are all set, DMA0 takes priority and the transfer starts. When one transfer unit is complete, the bus
privilege is returned to the CPU. When the CPU has completed one bus access, DMA1 transfer starts,
and, when one transfer unit is complete, the privilege is again returned to the CPU.
The priority is as follows: DMA0 > DMA1 > DMA2 > DMA3.
Figure 1.11.7. DMA transfer example by external factors shows what happens when DMA0 and DMA1
requests occur in the same sampling cycle.

In this example, DMA transfer request signals are input simultaneously from
external factors and the DMA transfers are executed in the minimum cycles.

BCLK

DMA0 AAA
AAA AAA
DMA1
A AAA AA Bus
CPU

INT0
AA
AAAAAAA
A
AA
A AAA AAAA priviledge
acquired

DMA0
request bit

INT1

DMA1
request bit

Figure 1.11.7. DMA transfer example by external factors

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DMAC

Precautions for DMAC

(1) Do not clear the DMA request bit of the DMAi request cause select register.
In M32C/83, when a DMA request is generated while the channel is disabled (Note), the DMA transfer is
not executed and the DMA request bit is cleared automatically.
Note :The DMA is disabled or the transfer count register is "0".

(2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause select
register to "1" simultaneously using the OR instruction.
e.g.) OR.B #0A0h, DMiSL ; DMiSL is DMAi request cause select register

(3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1" to
the DMA request bit, simultaneously. In this case, the corresponding DMA channel is set to disabled. At
least 8 + 6 x N (N: enabled channel number) clock cycles are needed from the instruction to write to the
DMAi request cause select bit to enable DMA.

e.g.) When DMA request cause is changed to timer A0 and using DMA0 in single transfer after
DMA initial setting
push.w R0 ; Store R0 register
stc DMD0, R0 ; Read DMA mode register 0
and.b #11111100b, R0L ; Clear DMA0 transfer mode select bit to "00"
ldc R0, DMD0 ; DMA0 disabled
mov.b #10000011b, DM0SL ; Select timer A0
; (Write "1" to DMA request bit simultaneously)
nop At least 8 + 6 x N cycles
: (N: enabled channel number)
ldc R0, DMD0 ; DMA0 enabled
pop.w R0 ; Restore R0 register

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DMAC II

DMAC II
When requested by an interrupt from any peripheral I/O, the DMAC performs a memory-to-memory trans-
fer, an immediate data transfer, or an arithmetic transfer (to transfer the sum of two data added).
Specifications of DMAC II are shown in Table 1.12.1.

Table 1.12.1 Specifications of DMAC II

Item Specification

Causes to activate DMAC II Interrupt request from any peripheral I/O whose interrupt priority is set to
"level 7" by the Interrupt Control Register

Transfer data (1) Memory -> memory (memory-to-memory transfer)

(2) Immediate data -> memory (immediate data transfer)
(3) Memory (or immediate data) + memory -> memory (arithmetic transfer)

Unit of transfer Transferred in 8 or 16 bits

Transfer space 64-Kbyte space at address up to 0FFFF16 (Note)

Direction of transfer Fixed or forward address

Can be selected individually for the source and the destination of transfer.

Transfer mode (1) Single transfer

(2) Burst transfer

Chained transfer function Parameters (transfer count, transfer address, and other information)
are switched over when the transfer counter reaches zero.
Interrupt at end of transfer Interrupt is generated when the transfer counter reaches zero.
Multiple transfer function Multiple data transfers can be performed by one DMA II transfer request generated.

Note : When transfer unit is 16 bits and destination address is 0FFFF16, data is transfered to addresses
0FFFF16 and 1000016. When source address is 0FFFF16, data is transfered as in the previous.

Settings of DMAC II
DMAC II can be enabled for use by setting up the following registers and tables.
• Exit Priority Register (address 009F16)
• DMAC II Index
• Interrupt Control Register for the peripheral I/O that requests a transfer by DMAC II
• Relocatable Vector Table for the peripheral I/O that requests a transfer by DMAC II
• When using an intelligent I/O or CAN interrupt, Interrupt Enable Register’s interrupt request latch bit
(bit 0)

(1) Exit priority register (address 009F16)

If this register’s DMAC II select bit (bit 5) and fast interrupt select bit (bit 3) respectively are set to 1 and
0, DMAC II is activated by an interrupt request from any peripheral I/O whose interrupt priority is set to
“level 7” by the interrupt priority level select bit.
The configuration of the exit priority register is shown in Figure 1.12.1.

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DMAC II

Exit priority register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
RLVL 009F16 XX0X00002

Bit
symbol Bit name Function R W

b2 b1 b0
RLVL0 0 0 0 : Level 0
Interrupt priority set bits 0 0 1 : Level 1
for exiting Stop/Wait 0 1 0 : Level 2
RLVL1 state 0 1 1 : Level 3
(Note 1) 1 0 0 : Level 4
1 0 1 : Level 5
RLVL2 1 1 0 : Level 6
1 1 1 : Level 7

0: Interrupt priority level 7 = normal

High-speed interrupt interrupt
FSIT
set bit (Note 2) 1: Interrupt priority level 7 =
high-speed interrupt

Nothing is assigned.
When write, set "0". When read, its content is indeterminate.

0: Interrupt priority level 7 = normal

DMA II select bit interrupt or high-speed interrupt
DMA II (Note 3) 1: Interrupt priority level 7 =
DMA II transfer

Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.

Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is higher than
that set in the exit priority register.
Set to the same value as the processor interrupt priority level (IPL) set in the flag
register (FLG).
Note 2: The high-speed interrupt can only be specified for interrupts with interrupt priority level
7. Specify interrupt priority level 7 for only one interrupt.
Note 3: Do not set this bit to 0 after once setting it to 1.
When this bit is 1, do not set the high-speed interrupt select bit to 0. (This cannot be
used simultaneously with the high-speed interrupt.)
Transfers by DMAC II are unaffected by the interrupt enable flag (I flag) and processor
interrupt priority level (IPL).

Figure 1.12.1. Exit priority register

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DMAC II

(2) DMAC II Index

The DMAC II Index is a data table, comprised of 8 to 18 bytes (max. 32 kbytes when multiple transfer
function is selected), which contains such parameters as transfer mode, transfer counter, transfer
source address (or immediate data), operation address, transfer destination address, chained trans-
fer address, and end-of-transfer interrupt address.
This DMAC II Index is located in the RAM area.
Configuration of the DMAC II Index is shown in Figure 1.12.2. The configuration of the DMAC II Index
by transfer mode is shown in Table 1.12.2.

Memory-to-memory transfer, Immediate transfer, Multiple transfer

Arithmetic transfer
16 bits 16 bits
DMAC II Index
start address (BASE) Transfer mode (MOD) BASE Transfer mode (MOD)
BASE + 2 Transfer counter (COUNT) BASE + 2 Transfer counter (COUNT)
BASE + 4 Transfer source address (or imm data)(SADR) BASE + 4 Transfer source address (SADR1)
BASE + 6 Operation address (OADR) (Note1) BASE + 6 Transfer destination address (DADR1)
BASE + 8 Transfer destination address (DADR) BASE + 8 Transfer source address (SADR2)
BASE + 10 Chained transfer address (CADR0) (Note2) BASE + 10 Transfer destination address (DADR2)
BASE + 12 Chained transfer address (CADR1) (Note2)

BASE + 14 End-of-transfer interrupt address (IADR0) (Note3) BASE + 28 Transfer source address (SADR7)
BASE + 16 End-of-transfer interrupt address (IADR1) (Note3) BASE + 30 Transfer destination address (DADR7)

Note 1: Delete this data when not using the arithmetic transfer function.
Note 2: Delete this data when not using the chained transfer function.
Note 3: Delete this data when not using an end-of-transfer interrupt.

Figure 1.12.2. DMAC II index

• Transfer mode (MOD)

This two-byte data sets DMAC II transfer mode. Configuration of transfer modes is shown in Figure
1.12.3.
• Transfer counter (COUNT)
This two-byte data sets the number of times transfer is performed.
• Transfer source address (SADR)
This two-byte data sets the memory address from which data is transferred or immediate data.
• Operation address (OADR)
This two-byte data sets the memory address to be operated on for calculation. This data is added to
the table only when using the arithmetic transfer function.
• Transfer destination address (DADR)
This two-byte data sets the memory address to which data is transferred.
• Chained transfer address (CADR)
This four-byte data sets the DMAC II Index start address for the next DMAC II transfer to be per-
formed. This data is added to the table only when using the chained transfer function.
• End-of-transfer interrupt address (IADR)
This four-byte data sets the jump address for end-of-transfer interrupt processing. This data is added
to the table only when using an end-of-transfer interrupt.

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DMAC II

Table 1.12.2. The configuration of the DMAC II Index by transfer mode

Memory-to-memory transfer
Transmit data Arithmetic transfer Multiple transfer
/immediate data transfer
Chained transfer Not use Use Not use Use Not use Use Not use Use Cannot use
Interrupt at Not use Not use Use Use Not use Not use Use Use Cannot use
end of transfer

MOD MOD MOD MOD MOD MOD MOD MOD MOD

COUNT COUNT COUNT COUNT COUNT COUNT COUNT COUNT COUNT
SADR SADR SADR SADR SADR SADR SADR SADR SADR1
DADR DADR DADR DADR OADR OADR OADR OADR DADR1
DMAC II CADR0 IADR0 CADR0 DADR DADR DADR DADR
8 bytes
index CADR1 IADR1 CADR1 CADR0 IADR0 CADR0
10 bytes
IADR0 CADR1 IADR1 CADR1 SADRi
12 bytes 12 bytes
IADR1 IADR0 DADRi
14 bytes 14 bytes
16 bytes IADR1 i=1 to 7
Max. 32 bytes
18 bytes (when i=7)

Transfer mode(MOD)
b15 b8
(b7) (b0)b7 b0

Bit Function Function

symbol Bit name (MULT=0) (MULT=1) R W

Transfer unit 0: 8 bits

SIZE
select bit 1: 16 bits

Transfer data 0: Immedeate data

IMM Must set to "1"
select bit 1: Memory

Transfer source 0: Fixed address

UPDS
direction select bit 1: Forward address

Transfer distination 0: Fixed address

UPDD
direction select bit 1: Forward address

OPER Alithmatic transfer 0: Not used b6 b5 b4

0 0 0: Do not
/CNT0 function select bit 1: Used set this
0 0 1: Once
BRST Burst transfer 0: Single transfer 0 1 0: Twice
/CNT1 select bit 1: Burst transfer :
:
INTE End of transfer 0: Interrupt not used 1 1 0: 6 times
/CNT2 interrupt select bit 1: Interrupt used 1 1 1: 7 times

Chained transfer 0: Chained transfer not used

CHAIN Must set to "0"
select bit 1: Chained transfer used

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.

Multiple transfer
MULT 0: Not multiple transfer 1: Multiple transfer
select bit

Figure 1.12.3. Transfer mode

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(3) Interrupt Control Register for Peripheral I/O

For peripheral I/O interrupts used to request a transfer by DMAC II, set the Interrupt Control Register
for each peripheral I/O to select “level 7” for their interrupt priority.

(4) Relocatable Vector Table for Peripheral I/O

In the relocatable vector table for each peripheral I/O that requests a transfer by DMAC II, set the
DMAC II Index start address. (When using chained transfers, the relocatable vector table must be
located in the RAM.)

(5) Interrupt Enable Register’s interrupt request latch bit (bit 0)

When using an intelligent I/O or CAN interrupt to activate DMAC II, set to 0 the Interrupt Enable
Register’s interrupt request latch bit (bit 0) for the intelligent I/O or CAN interrupt that requests a
transfer by DMAC II.

Operation of DMAC II
The DMAC II function is selected by setting the DMAC II select bit (bit 5 at address 009F16) to 1. All
peripheral I/O interrupt requests which have had their interrupt priorities set to “level 7” by the Interrupt
Control Register comprise DMAC II interrupt requests. These interrupt requests (priority level = 7) do not
generate an interrupt, however.
When an interrupt request is generated by any peripheral I/O whose interrupt priority is set to “level 7,”
DMAC II is activated no matter which state the I flag and processor interrupt priority level(IPL) is in. If an
_______
interrupt request with higher priority than that (e.g., NMI or watchdog timer) occurs, this higher priority
interrupt has precedence over and is accepted before DMAC II transfers. The pending DMAC II transfer
is started after the interrupt processing sequence for that interrupt finishes.

Transfer data
DMAC II transfers data in units of 8 or 16 bits as described below.
• Memory-to-memory transfer: Data is transferred from any memory location in the 64-Kbyte space to
any memory location in the same space.
• Immediate data transfer: Data is transferred as immediate data to any memory location in the 64-
Kbyte space.
• Arithmetic transfer: Two 8 or16 bits of data are added together and the result is transferred to any
memory location in the 64-Kbyte space.

When transfer unit is 16 bits and destination address is 0FFFF16, data is transfered to addresses
0FFFF16 and 1000016. When source address is 0FFFF16, data is transfered as in the previous.

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DMAC II

(1) Memory-to-memory transfer

Data can be transferred from any memory location in the 64-Kbyte space to any memory location in
the same space in one of the following four ways:
• Transfer from a fixed address to another fixed address
• Transfer from a fixed address to a variable address
• Transfer from a variable address to a fixed address
• Transfer from a variable address to another variable address
If variable address mode is selected, the transfer address is incremented for the next DMA II transfer
to be performed. When transferred in units of 8 bits, the transfer address is incremented by one; when
transferred in units of 16 bits, the transfer address is incremented by two. If the transfer source or
destination address exceeds 0FFFF16 as a result of address incrementation, the transfer source or
destination address recycles back to 0000016.

(2) Immediate data transfer

Data is transferred as immediate data to any memory location in the 64-Kbyte space. A fixed or
variable address can be selected for the transfer destination address. Store the immediate data in the
DMAC II Index’s transfer source address. When transferring 8-bit immediate data, set the data in the
lower byte position of the transfer source address. (The upper byte is ignored.)

(3) Arithmetic transfer

Data in two memory locations of the 64-Kbyte space or immediate data and data in any memory
location of the 64-Kbyte space are added together and the result is transferred to any memory location
in the 64-Kbyte space. Set the memory location to be operated on or immediate data in the DMAC II
Index’s transfer source address field and the other memory location to be operated on in the DMAC II
Index’s operation address field. When performing this mode of transfer on two memory locations, a
fixed or variable address can be selected for the transfer source and transfer destination addresses. If
the transfer source address is chosen to be variable, the operation address also becomes variable.
When performing this mode of transfer on immediate data and any memory location, a fixed or vari-
able address can be selected for the transfer destination address.

Transfer modes
DMAC II supports single and burst transfers. Use the burst transfer select bit (bit 5) for transfer mode
setup in the DMAC II index to choose single or burst transfer mode. Use the DMAC II index transfer
counter to set the number of times a transfer is performed. Neither single transfer nor burst transfer is
performed if the value “000016” is set in the transfer counter.

(1) Single transfer

For a DMAC II transfer request, 8 or 16 bits of data (one transfer unit) is transferred once. If the
transfer source or transfer destination address is chosen to be variable, the next DMA II transfer is
performed on an incremented memory address.
The transfer counter is decremented by each DMA II transfer performed. When using the end-of-transfer
interrupt facility, an end-of-transfer interrupt is generated at the time the transfer counter reaches zero.

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DMAC II

(2) Burst transfer

For a DMAC II transfer request, data transfers are performed in succession a number of times as set
by the DMAC II Index transfer counter. When using the end-of-transfer interrupt facility, an end-of-
transfer interrupt is generated at the time a burst transfer finishes (i.e., when the transfer counter
reaches zero after being decremented for each data transfer performed).

(3) Multiple transfers

For multiple transfers, use the multiple transfer select bit (bit 15) for transfer mode setup in the DMAC
II Index. Setting this bit to 1 selects the multiple transfer function. For the multiple transfer function,
memory to memory transfer can be performed.
Multiple transfers are performed for one DMAC II transfer request received. Use DMAC II Index trans-
fer mode bits 4–6 to set the number of transfers to be performed. (Setting these bits to 001 performs
one transfer; setting these bits to 111 performs 7 transfers. Setting these bits to 000 is inhibited.)
The transfer source and transfer destination addresses are alternately incremented beginning with the
DMAC II Index BASE address + 4 (as many times as the number of transfers performed).
When using multiple transfer function, arithmetic transfer, burst transfer, end-of-transfer interrupt and
chained transfer cannot be used.

(4) Chained transfer

For chained transfers, use the chained transfer select bit (bit 7) for transfer mode setup in the DMAC
II Index. Setting this bit to 1 selects the chained transfer function. The following describes how a
chained transfer is performed.
1) When a DMA II transfer request (interrupt request from any peripheral I/O) is received, a DMAC II
Index transfer is performed corresponding to the received request.
2) When the DMAC II Index transfer counter reaches zero, the chained transfer address in the DMAC
II Index (i.e., the start address of the DMAC II Index that contains a description of the next DMAC II
transfer to be performed) is written to the relocatable vector table for the peripheral I/O.
3) From the next DMA II transfer request on, transfers are performed based on the DMAC II Index
indicated by the rewritten relocatable vector table of the peripheral I/O.

Before the chained transfer function can be used, the relocatable vector table must be located in the
RAM area.

(5) End-of-transfer interrupt

For end-of-transfer interrupts, use the end-of-transfer interrupt select bit (bit 6) for transfer mode setup
in the DMAC II Index. Setting this bit to 1 selects the end-of-transfer interrupt function. Set the jump
address for end-of-transfer interrupt processing in the DMAC II Index’s end-of-transfer interrupt ad-
dress field. An end-of-transfer interrupt is generated when the DMAC II Index transfer counter reaches
zero.

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DMAC II

Execution time
The number of DMAC II execution cycles is calculated by the equation below.

For other than multiple transfers, t = 6 + (26 + A + B + C + D) X m + (4 + E) X n (cycles)

For multiple transfers, t = 21 + (11 + B + C) X k (cycles)
where
A: If the source of transfer is immediate data, A = 0; if it is memory, A = –1
B: If the source address of transfer is a variable address, B = 0; if it is a fixed address, B = 1
C: If the destination address of transfer is a variable address, C = 0; if it is a fixed address, C = 1
D: If the arithmetic function is not selected, D = 0; if the arithmetic function is selected and the source of
transfer is immediate data or fixed address memory, D = 7; if the arithmetic function is selected and the
source of transfer is variable address memory, D = 8
E: If the chained transfer function is not selected, E = 0; if the chained transfer function is selected, E = 4
m: For single transfer, m = 1; for burst transfer, m = the value set by the transfer counter
n: If the transfer count is one, n = 0; if the transfer count is two or greater, n = 1
k: Number of transfers set by transfer mode bits 4–7

The above equation applies only when all of the following conditions are met, however.
• No bus wait states are inserted.
• The DMAC II Index is set to an even address.
• During word transfer, the transfer source address, transfer destination address, and operation address
all are set to an even address.
Note that the first instruction in end-of-transfer interrupt processing is executed 7 cycles after DMAC II
transfers are completed.

When using an end-of-transfer interrupt (transfer counter = 2) after performing a memory to memory
single transfer twice from a variable source address to a fixed destination address, with the chained
transfer function unselected

A=0 B=1 C=0 D=0 E=0

First DMAC II transfer t=6+27X1+4X1=37 cycle

Second DMAC II transfer t=6+27X1+4X0=33 cycle

DMAC II transfer request DMAC II transfer request

Application DMAC II transfer Application DMAC II transfer

End of transfer interrupt program
program (First time) program (Second time)

37 cycles 33 cycles 8 cycles

Transfer counter = 2 Transfer counter = 1

Down count of transfer counter Down count of transfer counter
Transfer counter = 1 Transfer counter = 0

Figure 1.12.4. Transfer Time

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Timer

Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(six). All these timers function independently. Figures 1.13.1 and 1.13.2 show the block diagram of timers.

Clock prescaler
XIN f1 XCIN 1/32 fC32
1/8 f8 Reset
Clock prescaler reset flag (bit 7
at address 034116) set to “1”
1/2n f2n
(n = 0 to 15
Count source however, no division when n=0)
prescaler register
f1 f8 f2n fC32

• Timer mode
• One-shot mode
• PWM mode
Timer A0 interrupt
Timer A0
TA0IN Noise
filter • Event counter mode

• Timer mode
• One-shot mode
• PWM mode
Timer A1 interrupt
Noise
Timer A1
TA1IN filter
• Event counter mode

• Timer mode
• One-shot mode
• PWM mode
Timer A2 interrupt
Noise
Timer A2
TA2IN filter
• Event counter mode

• Timer mode
• One-shot mode
• PWM mode
Timer A3 interrupt
Noise
Timer A3
TA3IN filter
• Event counter mode

• Timer mode
• One-shot mode
• PWM mode
Timer A4 interrupt
Noise
Timer A4
TA4IN filter
• Event counter mode

Timer B2 overflow

Figure 1.13.1. Timer A block diagram

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Timer

Clock prescaler
XIN f1 XCIN 1/32 fC32
1/8 f8 Reset
Clock prescaler reset flag (bit 7
at address 034116) set to “1”
1/2n f2n
(n = 0 to 15
Count source however, no division when n=0)
prescaler register
f1 f8 f2n fC32
Timer B2 overflow (to timer A count source)

• Timer mode
• Pulse width measuring mode
Noise
Timer B0 interrupt
TB0IN filter Timer B0
• Event counter mode

• Timer mode
• Pulse width measuring mode Timer B1 interrupt
TB1IN Noise Timer B1
filter
• Event counter mode

• Timer mode
• Pulse width measuring mode Timer B2 interrupt
Noise
TB2IN filter Timer B2
• Event counter mode

• Timer mode
• Pulse width measuring mode
Noise
Timer B3 interrupt
TB3IN filter Timer B3
• Event counter mode

• Timer mode
• Pulse width measuring mode Timer B4 interrupt
TB4IN Noise Timer B4
filter
• Event counter mode

• Timer mode
• Pulse width measuring mode Timer B5 interrupt
Noise
TB5IN filter Timer B5
• Event counter mode

Figure 1.13.2. Timer B block diagram

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Timer A

Timer A
Figure 1.14.1 shows the block diagram of timer A. Figures 1.14.2 to 1.14.6 show the timer A-related registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer outputs one effective pulse until the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.

Data bus high-order bits

AAAA
Clock source
selection • Timer
Data bus low-order bits

AAAAA
f1 • One shot Low-order High-order
• PWM
f8 8 bits 8 bits

A
f32 • Timer Reload register (16)
(gate function)
fC32

A
• Event counter
Polarity Counter (16)
selection Up count/down count
TAiIN Clock selection
(i = 0 to 4) Always down count except
Count start flag in event counter mode
(Address 034016)
TAi Addresses TAj TAk
Down count Timer A0 034716 034616 Timer A4 Timer A1
TB2 overflow Timer A1 034916 034816 Timer A0 Timer A2
External Up/down flag Timer A2 034B16 034A16 Timer A1 Timer A3
TAj overflow trigger Timer A3 034D16 034C16 Timer A2 Timer A4
(j = i – 1. Note, however, that j = 4 when i = 0) (Address 034416) Timer A4 034F16 034E16 Timer A3 Timer A0

TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)

TAiOUT Pulse output

(i = 0 to 4)
Toggle flip-flop

Figure 1.14.1. Block diagram of timer A

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Timer A

Timer Ai register (i = 0 to 4) (Note 1)

(b15) (b8)
b7 b0 b7 b0
Symbol Address When reset
TAi (i = 0 to 2) 034716,034616, 034916,034816, 034B16,034A16 Indeterminate
TAi (i = 3, 4) 034D16,034C16, 034F16,034E16 Indeterminate

Function Values that can be set R W

Timer mode
16-bit counter (set to dividing ratio) 000016 to FFFF16

Event counter
mode 16-bit counter (set to dividing ratio) 000016 to FFFF16
(Note 2)

One-shot timer 16-bit counter (set to one shot width) 000016 to FFFF16
mode (Note 6) (Note 3)
Pulse width 16-bit pulse width modulator
modulation mode (set to PWM pulse “H” width) 000016 to FFFE16
(16-bit PWM) (Note 4, 7) (Note 3)

Low-order 8 bits : 8-bit prescaler (Note 5, 7) 0016 to FE16

Pulse width
(set to PWM period) (High-order address)
modulation mode
High-order 8 bits : 8-bit pulse width modulator 0016 to FF16
(8-bit PWM)
(set to PWM pulse “H” width) (Low-order address)
(Note 3)
Note 1: Read and write data in 16-bit units.
Note 2: Counts pulses from an external source or timer overflow.
Note 3: Use MOV instruction to write to this register.
Note 4: When setting value is n, PWM period and “H” width of PWM pulse are as follows:
PWM period : (216 - 1) / fi
PWM pulse “H” width : n / fi
Note 5: When setting value of high-order address is n and setting value of low-order address is m, PWM period and
“H” width of PWM pulse are as follows:
PWM period : (2 8 - 1) X (m + 1) / fi
PWM pulse “H” width : (m + 1)n / fi
Note 6: When the timer Ai register is set to "000016", the counter does not operate and the timer Ai interrupt request
is not generated. When the pulse is set to output, the pulse does not output from the TAiOUT pin.
Note 7: When the timer Ai register is set to "000016", the pulse width modulator does not operate and the output
level of the TAiOUT pin remains "L" level, therefore the timer Ai interrupt request is not generated. This also
occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register
are set to "0016".

Figure 1.14.2. Timer A-related registers (1)

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Timer A

Timer Ai mode register (i = 0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TAiMR(i=0 to 4) 035616, 035716, 035816, 035916, 035A16 00000X002

Bit symbol Bit name Function R W

b1 b0
TMOD0 Operation mode 0 0 : Timer mode
select bit 0 1 : Event counter mode
1 0 : One-shot timer mode
TMOD1 1 1 : Pulse width modulation
(PWM) mode
This bit is invalid in M32C/80 series.
MR0 Port output control is set by the function select
registers A, B and C.
MR1
Function varies with each
MR2 operation mode
MR3
TCK0 Count source Function varies with each
select bit operation mode
TCK1

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TABSR 034016 0016

Bit symbol Bit name Function R W

Timer A0 count 0 : Stops counting
TA0S start flag 1 : Starts counting

TA1S Timer A1 count 0 : Stops counting

start flag 1 : Starts counting
Timer A2 count 0 : Stops counting
TA2S
start flag 1 : Starts counting

TA3S Timer A3 count 0 : Stops counting

start flag 1 : Starts counting

TA4S Timer A4 count 0 : Stops counting

start flag 1 : Starts counting

TB0S Timer B0 count 0 : Stops counting

start flag 1 : Starts counting
Timer B1 count 0 : Stops counting
TB1S
start flag 1 : Starts counting

TB2S Timer B2 count 0 : Stops counting

start flag 1 : Starts counting

Figure 1.14.3. Timer A-related registers (2)

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Timer A

Up/down flag (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
UDF 034416 0016

AA
A
Bit symbol Bit name Function R W
Timer A0 up/down flag 0 : Down count

AA
A
TA0UD
1 : Up count (Note 2)

AA
A
TA1UD Timer A1 up/down flag 0 : Down count
1 : Up count (Note 2)

AA
A
TA2UD Timer A2 up/down flag 0 : Down count
1 : Up count (Note 2)

AA
A
TA3UD Timer A3 up/down flag 0 : Down count
1 : Up count

AA
A
(Note 2)

TA4UD Timer A4 up/down flag 0 : Down count

A
1 : Up count (Note 2)
Timer A2 two-phase pulse 0 : two-phase pulse signal
TA2P signal processing select bit processing disabled
1 : two-phase pulse signal

A
processing enabled (Note 3)
Timer A3 two-phase pulse 0 : two-phase pulse signal
TA3P signal processing select bit processing disabled
1 : two-phase pulse signal

A
processing enabled (Note 3)
Timer A4 two-phase pulse 0 : two-phase pulse signal
TA4P signal processing select bit processing disabled
1 : two-phase pulse signal
processing enabled (Note 3)
Note 1: Use MOV instruction to write to this register.
Note 2: This specification becomes valid when the up/down flag content is selected for up/down switching cause.
Note 3: When not using the two-phase pulse signal processing function, set the select bit to “0”.

One-shot start flag

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
ONSF 034216 0016

AA
A
Bit symbol Bit name Function RW
TA0OS Timer A0 one-shot start flag 0 : Invalid

AA
A
1 : Timer start (Note 1)
TA1OS Timer A1 one-shot start flag 0 : Invalid

AA
A
1 : Timer start (Note 1)
TA2OS Timer A2 one-shot start flag 0 : Invalid

AA
A
1 : Timer start (Note 1)

AA
A
TA3OS Timer A3 one-shot start flag 0 : Invalid
1 : Timer start (Note 1)

AA
A
TA4OS Timer A4 one-shot start flag 0 : Invalid
1 : Timer start (Note 1)

AA
A
TAZIE Z phase input enable bit 0 : Invalid
1 : Valid

AA
A
TA0TGL Timer A0 event/trigger b7 b6

select bit 0 0 : Input on TA0IN is selected (Note 2)

AA
A
0 1 : TB2 overflow is selected
TA0TGH 1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected

Note 1: When read, the value is “0”.

Note 2: Set the corresponding pin output function select register to I/O port, and port direction register to “0”.

Figure 1.14.4. Timer A-related registers (3)

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Timer A

Trigger select register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TRGSR 034316 0016

Bit symbol Bit name Function R W

A
b1 b0
TA1TGL Timer A1 event/trigger
0 0 : Input on TA1IN is selected (Note)

A
select bit
0 1 : TB2 overflow is selected
TA1TGH 1 0 : TA0 overflow is selected

A
1 1 : TA2 overflow is selected
Timer A2 event/trigger b3 b2

A
TA2TGL 0 0 : Input on TA2IN is selected (Note)
select bit
0 1 : TB2 overflow is selected

A
TA2TGH 1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected

A
Timer A3 event/trigger b5 b4
TA3TGL 0 0 : Input on TA3IN is selected (Note)
select bit

A
0 1 : TB2 overflow is selected
TA3TGH 1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected

TA4TGL

TA4TGH
Timer A4 event/trigger
select bit
b7 b6
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
A
A
Note: Set the corresponding port function select register A to I/O port, and port direction register to “0”.

Clock prescaler reset flag

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
CPSRF 034116 0XXXXXXX2

Bit symbol Bit name Function RW

Nothing is assigned.
When write, set “0”. When read, their contents are
indeterminate.

A
A
CPSR Clock prescaler reset flag 0 : Ignored
1 : Prescaler is reset
(When read, the value is “0”)

Figure 1.14.5. Timer A-related registers (4)

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Timer A

Count source prescaler register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TCSPR 035F16 0XXXXXXX2

Bit symbol Bit name Function

A
RW

AA
b3 b2 b1 b0
CNT0 Count value set bits 0 0 0 0 : No division
0 0 0 1 : Division by 2
CNT1 0 0 1 0 : Division by 4
0 0 1 1 : Division by 6

A
(Note 1)
CNT2
1 1 0 1 : Division by 26
CNT3 1 1 1 0 : Division by 28
1 1 1 1 : Division by 30

Nothing is assigned.
When write, set “0”. When read, their contents are
indeterminate.

CST Count start bit

Note 1: Set count start bit to “0” before writing to count value set bits.
0 : Stops counting
1 : Starts counting (Note 2) A
Note 2: When this bit is set to “0”, divider circuit is inactive.

Figure 1.14.6. Timer A-related registers (5)

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Timer A

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.14.1.) Figure 1.14.7
shows the timer Ai mode register in timer mode.
Table 1.14.1. Specifications of timer mode
Item Specification
Count source f1, f8, f2n, fC32
Count operation • Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio 1/(m+1) m : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing When the timer underflows
TAiIN pin function Programmable I/O port or gate input
TAiOUT pin function Programmable I/O port or pulse output (Setting by corresponding function select
registers A, B and C)
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and
counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Gate function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed

Timer Ai mode register (i = 0 to 4) (Timer mode)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TAiMR(i=0 to 4) 035616, 035716, 035816, 035916, 035A16 00000X002

Bit symbol Bit name Function R W

TMOD0 Operation mode
b1 b0

TMOD1 select bit 0 0 : Timer mode

This bit is invalid in M32C/80 series.

MR0 Port output control is set by the function select
registers A, B and C.
b4 b3
Gate function
MR1 select bit 0 X : Gate function not available (Note 1)
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN (Note 2)
pin is held “L”
MR2 1 1 : Timer counts only when TAiIN (Note 2)
pin is held “H”
MR3 0 (Set to “0” in timer mode)
Count source b7 b6
TCK0 0 0 : f1
select bit
0 1 : f8
TCK1 1 0 : f2n (Note 3)
1 1 : fC32
Note 1: X value can be “0” or “1”.
Note 2: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 3: n = 0 to 15. n is set by the count source prescaler register (address 035F16).

Figure 1.14.7. Timer Ai mode register in timer mode

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Timer A

(2) Event counter mode

In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 1.14.2 lists timer specifications when counting a single-phase external signal.
Table 1.14.3 lists timer specifications when counting a two-phase external signal. Figure 1.14.8 shows
the timer Ai mode register in event counter mode.

Table 1.14.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item Specification
Count source • External signals input to TAiIN pin (effective edge can be selected by software)
• TB2 overflows or underflows, TAj overflows or underflows
Count operation • Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register contents
before continuing counting (Note)
Divide ratio • 1/ (FFFF16 - n + 1) for up count
• 1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function Programmable I/O port or count source input
TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input (Setting by corre-
sponding function select registers A, B and C)
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and
counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Free-run count function
Even when the timer overflows or underflows, the reload register content is not
reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed

Note: This does not apply when the free-run function is selected.

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Timer A

Timer Ai mode register (i = 0 to 4) (Event counter mode)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset

TAiMR(i=0 to 4) 035616, 035716, 035816, 035916, 035A16 00000X002

Function Function
Bit (When not using two-phase
Bit name (When using two-phase R W
symbol pulse signal processing) pulse signal processing)

TMOD0 Operation mode b1 b0

select bit 0 1 : Event counter mode

TMOD1 (Note 1)
This bit is invalid in M32C/80 series.
MR0 Port output control is set by the function select registers A, B and C.

Count polarity 0 : Counts external 0 (Set to “0” when using

MR1 select bit signal's falling edges two-phase pulse signal
(Note 2) 1 : Counts external processing)
signal's rising edges

Up/down 0 : Up/down flag's content 1 (Set to “1” when using

MR2 switching cause 1 : TAiOUT pin's input signal two-phase pulse signal
select bit (Note 3) processing)

MR3 0 (Set to “0” in Event counter mode)

TCK0 Count operation 0 : Reload type

type select bit 1 : Free-run type

Two-phase pulse
0 (Set to “0” when not 0 : Normal processing
TCK1 signal processing operation
operation select using two-phase pulse
1 : Multiply-by-4
bit (Note 4,Note 5) signal processing) processing operation

Note 1: Count source is select by the event/trigger select bit (addresses 034216, 034316) in event counter mode.
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Signal of TAiOUT pin counts down at the time of “L” and counts up at the time of “H”.
Note 4: This bit is valid for timer A3 mode register.
Timer A0 and A1 can be “0” or “1”.
Timer A2 is fixed to normal processing operation and timer A4 is fixed to multiply-by-4
processing operation.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 034416) is set to “1”. Also, always be
sure to set the event/trigger select bit (address 034316) to “00”.

Figure 1.14.8. Timer Ai mode register in event counter mode

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Timer A

Table 1.14.3. Timer specifications in event counter mode

Item Specification
Count source Two-phase pulse signals input to TAiIN or TAiOUT pin
Count operation • Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note 1)
Divide ratio • 1/ (FFFF16 - n + 1) for up count
• 1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing Timer overflows or underflows
TAiIN pin function Two-phase pulse input
TAiOUT pin function Two-phase pulse input (Set corresponding function select register A for I/O port)
Read from timer Count value can be read out by reading timer A2, A3, or A4 register
Write to timer • When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only reload
register. (Transferred to counter at next reload time.)
Select function (Note 2) • Normal processing operation (TimerA2 and timer A3)
The timer counts up rising edges or counts down falling edges on the TAiIN pin when
input signal on the TAiOUT pin is “H”

TAiOUT

TAiIN
(i=2,3) Up Up Up Down Down Down
count count count count count count
• Multiply-by-4 processing operation (TimerA3 and timer A4)
If the phase relationship is such that the TAiIN pin goes “H” when the input signal on
the TAiOUT pin is “H”, the timer counts up rising and falling edges on the TAiOUT and
TAiIN pins. If the phase relationship is such that the TAiIN pin goes “L” when the input
signal on the TAiOUT pin is “H”, the timer counts down rising and falling edges on the
TAiOUT and TAiIN pins.
TAiOUT

Count up all edges Count down all edges

TAiIN
(i=3,4)

Count up all edges Count down all edges

(when processing two-phase pulse signal with timers A2, A3, and A4)
Note 1: This does not apply when the free-run function is selected.
Note 2: Timer A3 is selectable. Timer A2 is fixed to normal processing operation and timer A4 is fixed to
multiply-by-4 operation.

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Timer A

• Counter Resetting by Two-Phase Pulse Signal Processing

This function resets the timer counter to “0” when the Z-phase (counter reset) is input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode, two-phase pulse signal processing,
free-run type, and multiply-by-4 processing. The Z phase is input to the INT2 pin.
When the Z-phase input enable bit (bit 5 at address 034216) is set to “1”, the counter can be reset by
Z-phase input. For the counter to be reset to “0” by Z-phase input, you must first write “000016” to the
timer A3 register (addresses 034D16 and 034C16).
The Z-phase is input when the INT2 input edge is detected. The edge polarity is selected by the INT2
polarity switch bit (bit 4 at address 009C16). The Z-phase must have a pulse width greater than 1 cycle
of the timer A3 count source. Figure 1.14.9 shows the relationship between the two-phase pulse (A
phase and B phase) and the Z phase.
The counter is reset at the count source following Z-phase input. Figure 1.14.10 shows the timing at
which the counter is reset to “0”.
Note that timer A3 interrupt requests occur successively two times when timer A3 underflow and INT2
input reload occures at the same time.
Do not use timer A3 interrupt request when this function is used.

TA3OUT
(A phase)

TA3IN
(B phase)

Count source

INT2 (Note)
(Z phase)

The pulse must be wider than this width. Note: When the rising edge of INT2 is selected.

Figure 1.14.9. The relationship between the two-phase pulse (A phase and B phase) and the Z phase

TA3OUT
(A phase)

TA3IN
(B phase)

Count source

INT2 (Note)
(Z phase)

Count value m m+1 1 2 3 4 5

Becoming “0” at this timing. Note: When the rising edge of INT2 is selected.

Figure 1.14.10. The counter reset timing

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Timer A

(3) One-shot timer mode

In this mode, the timer operates only once. (See Table 1.14.4.) When a trigger occurs, the timer starts
up and continues operating for a given period. Figure 1.14.11 shows the timer Ai mode register in one-
shot timer mode.

Table 1.14.4. Timer specifications in one-shot timer mode

Item Specification
Count source f1, f8, f2n, fC32
Count operation • The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new
count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : Set value
Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Interrupt request generation timing The count reaches 000016
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Programmable I/O port or pulse output (Setting by corresponding function select regis-
ters A, B and C)
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and
counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)

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Timer A

Timer Ai mode register (i = 0 to 4) (One-shot timer mode)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset

AA
A
TAiMR(i=0 to 4) 035616, 035716, 035816, 035916, 035A16 00000X002

Bit symbol Bit name Function RW

AA
A
TMOD0 Operation mode select bit b1 b0

TMOD1 1 0 : One-shot timer mode

MR0 This bit is invalid in M32C/80 series.

AA
A
Port output control is set by the function select registers A, B and C. – –

AA
A
MR1 External trigger select bit 0 : Falling edge of TAiIN pin's input signal (Note 2)
(Note 1) 1 : Rising edge of TAiIN pin's input signal (Note 2)

AA
A
MR2 Trigger select bit 0 : One-shot start flag is valid
1 : Selected by event/trigger select register

MR3

TCK0
0 (Set to “0” in one-shot timer mode)

Count source select bit

b7 b6
0 0 : f1
AA
A
AA
A
AA
A
0 1 : f8
TCK1 1 0 : f2n (Note 3)
1 1 : fC32
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 034216 and 034316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 3: n = 0 to 15. n is set by the count source prescaler register (address 035F16).

Figure 1.14.11. Timer Ai mode register in one-shot timer mode

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Timer A

(4) Pulse width modulation (PWM) mode

In this mode, the timer outputs pulses of a given width in succession. (See Table 1.14.5.) In this mode, the
counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure
1.14.12 shows the timer Ai mode register in pulse width modulation mode. Figure 1.14.13 shows the
example of how a 16-bit pulse width modulator operates. Figure 1.14.14 shows the example of how an 8-
bit pulse width modulator operates.

Table 1.14.5. Timer specifications in pulse width modulation mode

Item Specification
Count source f1, f8, f2n, fC32
Count operation • The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
16-bit PWM • High level width n / fi n : Set value
• Cycle time (216-1) / fi fixed
8-bit PWM • High level width n (m+1) / fi n : values set to timer Ai register’s high-order address
• Cycle time (28-1) (m+1) / fi m:values set to timer Ai register’s low-order address
Count start condition • External trigger is input
• The timer overflows
• The count start flag is set (= 1)
Count stop condition • The count start flag is reset (= 0)
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Pulse output (TAiOUT is selected by corresponding function select registers A, B and C)
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and
counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)

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Timer A

Timer Ai mode register (i = 0 to 4) (Pulse width modulator mode)

b7 b6 b5 b4 b3 b2 b1 b0

AA
A
Symbol Address When reset
TAiMR(i=0 to 4) 035616, 035716, 035816, 035916, 035A16 00000X002

AA
A
Bit symbol Bit name Function R W
TMOD0 Operation mode b1 b0

TMOD1 select bit 1 1 : Pulse width modulator (PWM) mode

MR0 This bit is invalid in M32C/80 series.

AA
A
Port output control is set by the function select registers A, B and C. – –

MR1 External trigger select bit 0: Falling edge of TAiIN pin's input signal (Note 2)

AA
A
1: Rising edge of TAiIN pin's input signal (Note 2)
(Note 1)
MR2

AA
A
Trigger select bit 0: Count start flag is valid
1: Selected by event/trigger select register

AA
A
MR3 16/8-bit PWM mode 0: Functions as a 16-bit pulse width modulator
select bit 1: Functions as an 8-bit pulse width modulator

AA
A
b7 b6
TCK0 Count source select bit
0 0 : f1

AA
A
0 1 : f8
TCK1 1 0 : f2n (Note 3)
1 1 : fC32
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 034216 and 034316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 3: n = 0 to 15. n is set by the count source prescaler register (address 035F16).

Figure 1.14.12. Timer Ai mode register in pulse width modulation mode

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Timer A

Condition : Reload register = 000316, when external trigger

(rising edge of TAiIN pin input signal) is selected
1 / fi X (2 16 – 1)

Count source

“H”
TAiIN pin
input signal “L”
Trigger is not generated by this signal

1 / fi X n
PWM pulse output “H”
from TAiOUT pin “L”

Timer Ai interrupt “1”

request bit
“0”

fi : Frequency of count source

(f1, f8, f2n, fC32) Cleared to “0” when interrupt request is accepted, or cleared by software

Note: n = 000016 to FFFE16.

Figure 1.14.13. Example of how a 16-bit pulse width modulator operates

Condition : Reload register high-order 8 bits = 0216

Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected

1 / fi X (m + 1) X (2 8 – 1)

Count source (Note1)

TAiIN pin input signal “H”

AAAAAAAAAAAAAAA
“L”

1 / fi X (m + 1)

AAAAAAAAAAAAAAA
Underflow signal of “H”
8-bit prescaler (Note2) “L”

1 / fi X (m + 1) X n

PWM pulse output “H”

from TAiOUT pin “L”

Timer Ai interrupt “1”

request bit “0”

fi : Frequency of count source Cleared to “0” when interrupt request is accepted, or cleaerd by software
(f1, f8, f2n, fC32)

Note 1: The 8-bit prescaler counts the count source.

Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FE16.

Figure 1.14.14. Example of how an 8-bit pulse width modulator operates

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Timer B

Timer B
Figure 1.15.1 shows the block diagram of timer B. Figures 1.15.2 and 1.15.4 show the timer B-related
registers. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:

• Timer mode: The timer counts an internal count source.

• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.

Data bus high-order bits

Data bus low-order bits

Clock source selection
Low-order 8 bits High-order 8 bits
f1 • Timer
• Pulse period/pulse width measurement Reload register (16)
f8
f32
fC32 • Event counter Counter (16)

Polarity switching Count start flag

TBiIN
(i = 0 to 5) and edge pulse (address 034016)

Counter reset circuit

Can be selected in only
event counter mode
TBi Address TBj
TBj overflow Timer B0 035116 035016 Timer B2
(j = i – 1. Note, however, Timer B1 035316 035216 Timer B0
j = 2 when i = 0, Timer B2 035516 035416 Timer B1
j = 5 when i = 3) Timer B3 031116 031016 Timer B5
Timer B4 031316 031216 Timer B3
Timer B5 031516 031416 Timer B4

Figure 1.15.1. Block diagram of timer B

Timer Bi register (i = 0 to 6) (Note 1)

(b15) (b8)
b7 b0 b7 b0
Symbol Address When reset
TBi (i = 0 to 2) 035116,035016, 035316,035216, 035516,035416 Indeterminate
TBi (i = 3 to 5) 031116,031016, 031316,031216, 031516,031416 Indeterminate

Function Values that can be set RW

Timer mode 16-bit counter (set to dividing ratio) 000016 to FFFF16

Event counter mode 16-bit counter (set to dividing ratio) 000016 to FFFF16
(Note 2)

Pulse period / pulse width Measures a pulse period or width

measurement mode
Note 1: Read and write data in 16-bit units.
Note 2: Counts external pulses input or a timer overflow.

Figure 1.15.2. Timer B-related registers (1)

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Timer B

Timer Bi mode register (i = 0 to 5)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TBiMR(i=0 to 5) 035B16, 035C16, 035D16, 031B16, 031C16, 031DB16 00XX00002

Bit symbol Bit name Function R W

b1 b0
TMOD0 Operation mode 0 0 : Timer mode
select bit 0 1 : Event counter mode
1 0 : Pulse period/pulse width
TMOD1 measurement mode
1 1 : Don't set it up
MR0
MR1 Function varies with each (Note 1)
MR2 operation mode (Note 2)
MR3
TCK0 Count source Function varies with each
TCK1 select bit operation mode

Note 1: Bit 4 is valid only by timer B0 and timer B3.

Note 2: In timer B1, timer B2, timer B4 and timer B5, nothing is assigned by bit 4(There is not R/W).
When write, set “0”. When read, its content is indeterminate.

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TABSR 034016 0016

Bit symbol Bit name Function R W

Timer A0 count 0 : Stops counting
TA0S start flag 1 : Starts counting

TA1S Timer A1 count 0 : Stops counting

start flag 1 : Starts counting
Timer A2 count 0 : Stops counting
TA2S
start flag 1 : Starts counting

TA3S Timer A3 count 0 : Stops counting

start flag 1 : Starts counting

TA4S Timer A4 count 0 : Stops counting

start flag 1 : Starts counting

TB0S Timer B0 count 0 : Stops counting

start flag 1 : Starts counting
Timer B1 count 0 : Stops counting
TB1S
start flag 1 : Starts counting

TB2S Timer B2 count 0 : Stops counting

start flag 1 : Starts counting

Figure 1.15.3. Timer B-related registers (2)

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Timer B

Timer B3, B4,B5 count start flag

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TBSR 030016 000XXXXX2

Bit symbol Bit name Function R W

Nothing is assigned.
When write, set "0". When read, its content is indeterminate.

Timer B3 count 0 : Stops counting

TB3S
start flag 1 : Starts counting
Timer B4 count 0 : Stops counting
TB4S
start flag 1 : Starts counting

TB5S Timer B5 count 0 : Stops counting

start flag 1 : Starts counting

Clock prescaler reset flag

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
CPSRF 034116 0XXXXXXX2

Bit symbol Bit name Function RW

Nothing is assigned.
When write, set “0”. When read, their contents are
indeterminate.

A
A
CPSR Clock prescaler reset flag 0 : Ignored
1 : Prescaler is reset
(When read, the value is “0”)

Figure 1.15.4. Timer B-related registers (3)

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Timer B

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.15.1.) Figure 1.15.5
shows the timer Bi mode register in timer mode.

Table 1.15.1. Timer specifications in timer mode

Item Specification
Count source f1, f8, f2n, fC32
Count operation • Counts down
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio 1/(m+1)m : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function Programmable I/O port
Read from timer Count value is read out by reading timer Bi register
Write to timer • When counting stopped
When a value is written to timer Bi register, it is written to both reload register and
counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)

b7
AA
A
Timer Bi mode register (i = 0 to 5) (Timer mode)

AA
A
b6 b5 b4 b3 b2 b1 b0

A A
Symbol Address When reset
TBiMR(i=0 to 5) 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX00002

A
AAA
Bit symbol Bit name Function R W
TMOD0 Operation mode select bit
b1 b0

AA
AA
0 0 : Timer mode
TMOD1
MR0 Invalid in timer mode.

AA
MR1 Can be “0” or “1”.
0 (Set to “0” in timer mode) (Note 1)
MR2 (Note 2)
Nothing is assigned. (i = 1, 2, 4, 5)
When write, set "0". When read, its content is indeterminate.

AA
MR3 Invalid in timer mode. When write, set "0". When read in timer
mode, its content is indeterminate.

AA
b7 b6
Count source select bit
TCK0 0 0 : f1
0 1 : f8
TCK1 1 0 : f2n (Note 3)
1 1 : fC32
Note 1: R/W is valid only in timer B0 and timer B3.
Note 2: In timer B1, timer B2, timer B4 and timer B5, nothing is assigned by bit 4(There is not R/W).
When write, set “0”. When read, its content is indeterminate.
Note 3: n = 0 to 15. n is set by the count source prescaler register (address 035F16).

Figure 1.15.5. Timer Bi mode register in timer mode

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Timer B

(2) Event counter mode

In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.15.2.)
Figure 1.15.6 shows the timer Bi mode register in event counter mode.

Table 1.15.2. Timer specifications in event counter mode

Item Specification
Count source • External signals input to TBiIN pin
Effective edge of count source can be a rising edge, a falling edge, or falling and
rising edges as selected by software
• TBj overflows or underflows
Count operation • Counts down
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function Count source input (Set the corresponding function select register A to I/O port.)
Read from timer Count value can be read out by reading timer Bi register
Write to timer • When counting stopped
When a value is written to timer Bi register, it is written to both reload register and
counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)

b7 b6
AA
Timer Bi mode register (i = 0 to 5) (Event counter mode)

AA
b5 b4 b3 b2 b1 b0
Symbol Address When reset

AA
TBiMR(i=0 to 5) 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX00002

A
AA
A
Bit symbol Bit name Function R W
TMOD0 Operation mode b1 b0

AA
select bit 0 1 : Event counter mode
TMOD1
Count polarity select b3 b2

AA
MR0 0 0 : Counts external signal's falling edges
bit
0 1 : Counts external signal's rising edges
1 0 : Counts external signal's falling and

AA
MR1 rising edges
(Note 1) 1 1 : Inhibited
MR2 0 (Set to “0” in event counter mode) (Note 2)
Nothing is assigned. (i = 1, 2, 4, 5) (Note 3)
When write, set “0”. When read, its content is indeterminate.

AA
MR3 Invalid in event counter mode. When write, set "0". When
read in event counter mode, its content is indeterminate.
Invalid in event counter mode.

AA
TCK0
Can be “0” or “1”.
TCK1 Event clock select bit 0 : Input from TBiIN pin (Note 4)
1 : TBj overflow (Note 5)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: R/W is valid only in timer B0 and timer B3.
Note 3: In timer B1, timer B2, timer B4 and timer B5, nothing is assigned by bit 4(There is not R/W).
When write, set “0”. When read, its content is indeterminate.
Note 4: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 5: j = i – 1; however, j = 2 when i = 0, j = 5 when i = 3.

Figure 1.15.6. Timer Bi mode register in event counter mode

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Timer B

(3) Pulse period/pulse width measurement mode

In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.15.3.)
Figure 1.15.7 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.15.8 shows the operation timing when measuring a pulse period. Figure 1.15.9 shows the operation
timing when measuring a pulse width.

Table 1.15.3. Timer specifications in pulse period/pulse width measurement mode

Item Specification
Count source f1, f8, f2n, fC32
Count operation • Count up
• Counter value “000016” is transferred to reload register at measurement pulse's
effective edge and the timer continues counting
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to “1”.
The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value
is written to the timer Bi mode register.)
TBiIN pin function Measurement pulse input (Set the corresponding function select register A to I/O port.)
Read from timer When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer Cannot be written to

Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started
counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input
after the timer.

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Timer B

Timer Bi mode register (i = 0 to 5) (Pulse period / pulse width measurement mode)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset

A
AA
TBiMR(i=0 to 5) 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX00002

A
AA
Bit symbol Bit name Function R W
b1 b0
TMOD0 Operation mode

AA
A
select bit 1 0 : Pulse period / pulse width
TMOD1 measurement mode

AA
A
b3 b2
MR0 Measurement mode
select bit 0 0 : Pulse period measurement 1

A
AA
0 1 : Pulse period measurement 2
1 0 : Pulse width measurement

A
AA
MR1 1 1 : Must not be set (Note 1)

0 (Set to “0” in pulse period/pulse width measurement mode)

(Note 2)
MR2
Nothing is assigned (i = 1, 2, 4, 5). (Note 3)
When write, set "0". When read, its content is indeterminate.

A
AA
MR3 Timer Bi overflow 0 : Timer did not overflow
flag (Note 4) 1 : Timer has overflowed
b7 b6

A
AA
TCK0 Count source
0 0 : f1
select bit
0 1 : f8
TCK1 1 0 : f2n (Note 5)
1 1 : fC32
Note 1: Do the next measurement, In the measurement mode select bit.
Pulse period measurement 1 (bit 3, bit 2=“0 0”) : Interval between measurement pulse's falling edge to falling edge.
Pulse period measurement 2 (bit 3, bit 2=“0 1”) : Interval between measurement pulse's rising edge to rising edge.
Pulse width measurement (bit 3, bit 2=“1 0”) : Interval between measurement pulse's falling edge to rising edge,
and between rising edge to falling edge.
Note 2: R/W is valid only in timer B0 and timer B3.
Note 3: In timer B1, timer B2, timer B4 and timer B5, nothing is assigned by bit 4(There is not R/W).
When write, set “0”. When read, its content is indeterminate.
Note 4: It is indeterminate when reset.
The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 5: n = 0 to 15. n is set by the count source prescaler register (address 035F16).

Figure 1.15.7. Timer Bi mode register in pulse period/pulse width measurement mode

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Timer B

When measuring measurement pulse time interval from falling edge to falling edge

Count source

“H”
Measurement pulse
“L”
Transfer Transfer
(indeterminate value) (measured value)

Reload register counter

transfer timing
(Note 1) (Note 1) (Note 2)

Timing at which counter

reaches “000016”

“1”
Count start flag
“0”

Timer Bi interrupt “1”

request bit “0”

Cleared to “0” when interrupt request is accepted, or cleared by software.

Timer Bi overflow flag “1”
“0”

Note 1: Counter is initialized at completion of measurement.

Note 2: Timer has overflowed.

Figure 1.15.8. Operation timing when measuring a pulse period

Count source

“H”
Measurement pulse
“L”
Transfer Transfer Transfer Transfer
(indeterminate (measured value) (measured (measured value)
value) value)
Reload register counter
transfer timing
(Note 1) (Note 1) (Note 1) (Note 1) (Note 2)
Timing at which counter
reaches “000016”

“1”
Count start flag
“0”

Timer Bi interrupt “1”

request bit “0”

Cleared to “0” when interrupt request is accepted, or cleared by software.

“1”
Timer Bi overflow flag
“0”

Note 1: Counter is initialized at completion of measurement.

Note 2: Timer has overflowed.

Figure 1.15.9. Operation timing when measuring a pulse width

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Three-phase motor control timers’ functions

Three-phase motor control timers’ functions

Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor
driving waveforms.
Figures 1.16.1 through 1.16.5 show registers related to timers for three-phase motor control.

Three-phase PWM control register 0 (Note 4)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
INVC0 030816 0016

Bit symbol Bit name Description R W

Effective interrupt output 0: A timer B2 interrupt occurs when the
INV00 polarity select bit timer A1 reload control signal is “1”.
1: A timer B2 interrupt occurs when the
timer A1 reload control signal is “0”.
(Note 3)
Effective interrupt output 0: Not specified.
INV01 specification bit 1: Selected by the INV00 bit.
(Note 2) (Note 3)

INV02 Mode select bit 0: Normal mode

1: Three-phase PWM output mode
(Note 4)

INV03 Output control bit 0: Output disabled

1: Output enabled
Positive and negative 0: Feature disabled
INV04 phases concurrent L output 1: Feature enabled
disable function enable bit
Positive and negative 0: Not detected yet
INV05 phases concurrent L output 1: Already detected (Note 5)
detect flag
INV06 Modulation mode select 0: Triangular wave modulation mode (Note 6)
bit 1: Sawtooth wave modulation mode (Note 7)

INV07 Software trigger bit 0: Ignored

1: Trigger generated (Note 8)

Note 1: Set bit 1 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Set bit 1 of this register to “1” after setting timer B2 interrupt occurrences frequency set counter.
Note 3: Effective only in three-phase mode 1(Three-phase PWM control register's bit 1 = “1”).
Note 4: Selecting three-phase PWM output mode causes the dead time timer, the U, V, W phase output control circuits,
and the timer B2 interrupt frequency set circuit works.
For U, U, V, V, W and W output from P80, P81, and P72 through P75, setting of function select registers A, B and
C is required.
Note 5: No value other than “0” can be written.
Note 6: The dead time timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the
three-phase buffer register to the three-phase output shift register is made only once in synchronization with the
transfer trigger signal after writing to the three-phase output buffer register.
Note 7: The dead time timer starts in synchronization with the falling edge of timer A output and with the transfer trigger
signal. The data transfer from the three-phase output buffer register to the three-phase output shift register is
made with respect to every transfer trigger.
Note 8: The value, when read, is “0”.

Figure 1.16.1. Registers related to timers for three-phase motor control

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Three-phase motor control timers’ functions

Three-phase PWM control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
INVC1 030916 0016

Bit symbol Bit name Description R W

Timer Ai start trigger signal 0: Timer B2 overflow signal
INV10 select bit 1: Timer B2 overflow signal,
signal for writing to timer B2

Timer A1-1, A2-1, A4-1 0: Three-phase mode 0

INV11 control bit 1: Three-phase mode 1
(Note 2)

INV12 Dead time timer count 0 : f1

source select bit 1 : f1/2

INV13 Carrier wave detect flag 0: Rising edge of triangular waveform

1: Falling edge of triangular waveform

Output polarity control bit 0 : Low active

INV14 1 : High active

Dead time invalid bit 0: Dead time valid bit

INV15 1: Dead time invalid bit

Dead time timer trigger 0: Triggers from corresponding timer

INV16 select bit 1: Rising edge of corresponding phase
output (Note 3)

INV17 Waveform reflect timing 0: Synchronized with raising edge of

select bit triangular waveform
1: Synchronized with timer B2 overflow
(Note 4)
Note 1: Set bit 1 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: INV13 is valid only in triangular waveform mode (INV06=0) and three-phase mode (INV11=1).
Note 3:Usually set to “1”.
Note 4:INV17 is valid only in three-phase mode 1.

Three-phase output buffer register i (i=0, 1) (Note)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
IDBi (i=0,1) 030A16, 030B16 XX00 00002

Bit Symbol Bit name Function R W

DUi U phase output buffer i Setting in U phase output buffer i

DUBi U phase output buffer i Setting in U phase output buffer i

DVi V phase output buffer i Setting in V phase output buffer i

DVBi V phase output buffer i Setting in V phase output buffer i

DWi W phase output buffer i Setting in W phase output buffer i

DWBi W phase output buffer i Setting in W phase output buffer i

Nothing is assigned.
When write, set “0”. When read, their contents are “0”.

Note: When executing read instruction of this register, the contents of three-phase shift register is read out.

Figure 1.16.2. Registers related to timers for three-phase motor control

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Three-phase motor control timers’ functions

Dead time timer (Note)

b7 b0
Symbol Address When reset
DTT 030C16 Indeterminate

Function Values that can be set R W

8-bits counter (set dead time timer) 1 to 255

Note: Use MOV instruction to write to this register.

Timer B2 interrupt occurrences frequency set counter (Note 1 to 4)

b7 b0
Symbol Address When reset
ICTB2 030D16 Indeterminate

Function Values that can be set R W

Set occurrence frequency of timer B2
interrupt request 1 to 15

Nothing is assigned.
When write, set to “0”.

Note 1: Use MOV instruction to write to this register.

Note 2: When the effective interrupt output specification bit (INV01: bit 1 at 030816) is set to “1” and three-phase
motor control timer is operating, do not rewrite to this register.
Note 3: Do not write to this register at the timing of timer B2 overflow.
Note 4: Setting of this register is valid only when bit 2 (INV02) of three-phase PWM control register 0 is set to "1".

Timer Ai, Ai-1 register (Note 1 to 3)

(b15) (b8)
b7 b0 b7 b0 Symbol Address When reset
TAi (i 1, 2, 4) 034916,034816, 034B16,034A16, 034F16,034E16 Indeterminate
TAi1 (i 1, 2, 4) 030316,030216, 030516,030416, 030716,030616 Indeterminate

Function Values that can be set R W

Three-phase PWM pulse width modulator 000016 to FFFF16

(decide PWM output pulse width)

Note 1: Read and write data in 16-bit units.

Note 2: When set “000016” to the timer Ai register, counter doesn't move, and timer Ai interrupt isn't generated.
Note 3: Use MOV instruction to write to this register.

Timer B2 register (Note)

(b15) (b8)
b7 b0 b7 b0 Symbol Address When reset
TB2 035516,035416 Indeterminate

Function Values that can be set R W

Set the period of carrier wave 000016 to FFFF16

Note : Read and write data in 16-bit units.

Figure 1.16.3. Registers related to timers for three-phase motor control

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Timer B2 special mode register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TB2SC 035E16 XXXXXXX02

AA
Bit symbol Bit name Function R W
PWCOM Timer B2 reload timing 0 : Next underflow
switching bit 1 : Synchronized rising edge of
triangular wave
Nothing is assigned.
When write, set “0”. When read, its content is “0”.

Trigger select register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TRGSR 034316 0016

A A
Bit symbol Bit name Function R W
TA1TGL Timer A1 event/trigger

A
AAA
Set bit 1 and bit 0 to “0 1” before using
select bit to the V phase output control circuit.
TA1TGH

A
AA
(Note)

TA2TGL Timer A2 event/trigger Set bit 3 and bit 2 to “0 1” before using

A
AA
select bit to the W phase output control circuit.
TA2TGH (Note)

TA3TGL
Inhibited in Three-phase PWM mode.

A A
TA3TGH

AA
TA4TGL Timer A4 event/trigger
Set bit 7 and bit 6 to “0 1” before using
select bit
to the U phase output control circuit.
TA4TGH (Note)

Note: Set the corresponding port function select register A to I/O port, and port direction register to “0”.

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TABSR 034016 0016

Bit symbol Bit name Function R W

Timer A0 count 0 : Stops counting
TA0S start flag 1 : Starts counting

TA1S Timer A1 count 0 : Stops counting

start flag 1 : Starts counting
Timer A2 count 0 : Stops counting
TA2S
start flag 1 : Starts counting

TA3S Timer A3 count 0 : Stops counting

start flag 1 : Starts counting

TA4S Timer A4 count 0 : Stops counting

start flag 1 : Starts counting

TB0S Timer B0 count 0 : Stops counting

start flag 1 : Starts counting
Timer B1 count 0 : Stops counting
TB1S
start flag 1 : Starts counting

TB2S Timer B2 count 0 : Stops counting

start flag 1 : Starts counting

Figure 1.16.4. Registers related to timers for three-phase motor control

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Three-phase motor control timers’ functions

Three-phase motor driving waveform output mode (three-phase PWM output mode)
Setting “1” in the mode select bit (bit 2 at 030816) shown in Figure 1.16.1 causes three-phase PWM
output mode that uses four timers A1, A2, A4, and B2. As shown in Figure 1.16.4 and 1.16.5 set timers
A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode using
the respective timer mode registers.

Timer Ai mode register (i = 1, 2, 4)

b7 b6 b5 b4 b3 b2 b1 b0

0 1 1 0 Symbol Address When reset

AA
A
TAiMR(i=1, 2, 4) 035716, 035816, 035A16 00000X002

AA
A A
Bit symbol Bit name Function R W
TMOD0 Operation mode select bit b1 b0

TMOD1 1 0 : One-shot timer mode

A A
This bit is invalid in M32C/80 series.
MR0 Port output control is set by the function select registers A, B and C.

A
AA
MR1 External trigger select bit Invalid in Three-phase PWM output mode.

MR2

MR3
Trigger select bit 1 : Selected by event/trigger select register

0 (Set to “0” in one-shot timer mode)

A
AA
A
AA
A
AA
b7 b6
TCK0 Count source select bit 0 0 : f1

AA
0 1 : f8
TCK1 1 0 : f2n (Note)
1 1 : fC32
Note: n = 0 to 15. n is set by the count source prescaler register (address 035F16).

AAA
Timer B2 mode register

A
AA
b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 Symbol Address When reset

TB2MR 035D16 00XX00002

Bit symbol Bit name Function

AA
R W

A A
TMOD0 b1 b0
Operation mode select bit 0 0 : Timer mode

A
AAA
TMOD1
MR0

AA
A A
Invalid in timer mode
MR1 Can be “0” or “1”

MR2 0 (Set to “0” in timer mode)

Invalid in timer mode.
MR3 When write, set “0”. When read in timer mode, its content is
indeterminate.

A A
b7 b6
TCK0 Count source select bit
0 0 : f1

AA
0 1 : f8
1 0 : f2n (Note)
TCK1
1 1 : fC32
Note: n = 0 to 15. n is set by the count source prescaler register (address 035F16).

Figure 1.16.5. Timer mode registers in three-phase PWM output mode

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Figure 1.16.6 shows the block diagram for three-phase waveform mode. The Low active output polarity
in three-phase waveform mode, the positive-phase waveforms (U phase, V phase, and W phase) and
___ ___ ___
negative waveforms (U phase, V phase, and W phase), six waveforms in total, are output from P80, P81,
P72, P73, P74, and P75 as active on the “L” level. Of the timers used in this mode, timer A4 controls the
___ ___
U phase and U phase, timer A1 controls the V phase and V phase, and timer A2 controls the W phase
___
and W phase respectively; timer B2 controls the periods of one-shot pulse output from timers A4, A1,
and A2.
In outputting a waveform, dead time can be set so as to cause the “L” level of the positive waveform
___
output (U phase, V phase, and W phase) not to lap over the “L” level of the negative waveform output (U
___ ___
phase, V phase, and W phase).
To set short circuit time, use three 8-bit timers, sharing the reload register, for setting dead time. A value
from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead
time works as a one-shot timer. If a value is written to the dead timer (030C16), the value is written to the
reload register shared by the three timers for setting dead time.
Any of the timers for setting dead time takes the value of the reload register into its counter, if a start
trigger comes from its corresponding timer, and performs a down count in line with the clock source
selected by the dead time timer count source select bit (bit 2 at 030916). The timer can receive another
trigger again before the workings due to the previous trigger are completed. In this instance, the timer
performs a down count from the reload register’s content after its transfer, provoked by the trigger, to the
timer for setting dead time.
Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger
comes; it stops outputting pulses as soon as its content becomes 0016, and waits for the next trigger to
come.
___ ___
The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V
___
phase, and W phase) in three-phase waveform mode are output, from respective ports by means of
setting “1” in the output control bit (bit 3 at 030816). Setting “0” in this bit causes the ports to be the high-
impedance state. This bit can be set to “0” not only by use of the applicable instruction, but by entering
_______
a falling edge in the NMI terminal or by resetting. Also, if “1” is set in the positive and negative phases
concurrent L output disable function enable bit (bit 4 at 030816) causes one of the pairs of U phase and
___ ___ ___
U phase, V phase and V phase, and W phase and W phase concurrently go to “L”, as a result, the output
control bit becomes the high-impedance state.

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INV13

Circuit for interrupt occurrence

INV01 frequency set counter
INV11 INV03 D Q
INV00
Overflow 1 Interrupt occurrence R
frequency set counter RESET
Interrupt request bit
n = 1 to 15 NMI
0 INV05
Signal to be
written to B2
INV07 f1 0
A
INV10 Reload register INV04 INV14
Timer B2 1/2 1
Trigger
U(P80)
(Timer mode)
Dead time timer setting (8) D Q
Trigger signal for Trigger
timer Ai start n = 1 to 255 T
INV06
U phase output control circuit Bit 0 at 030B16
Bit 0 at 030A16

DU1 DU0

Timer A4 Reload Timer A4-1 Trigger U phase output signal

signal for D Q D Q
transfer T T
Trigger
Timer A4 counter Three-phase output
shift register
Three-phase motor control timers’ functions

(One-shot timer mode) (U phase)

DUB1 DUB0

INV11
T Q U phase output signal U(P81)
Rev.B2 for proof reading

D Q D Q D Q
T T
To be set to “0” when timer A4 stops T

Trigger D Q V(P72)
Trigger Dead time timer setting (8)
T

Figure 1.16.6. Block diagram for three-phase waveform mode

n = 1 to 255
Timer A1 Reload Timer A1-1
INV06
V phase output signal
Trigger V phase output
Timer A1 counter control circuit V phase output signal V(P73)
D Q
(One-shot timer mode)
T
INV11
T Q
To be set to “0” when timer A1 stops For short circuit
prevention
Trigger W(P74)
Trigger Dead time timer setting (8) D Q
T
n = 1 to 255
INV06
Timer A2 Reload Timer A2-1
W phase output W phase output signal
Trigger control circuit
Timer A2 counter W phase output signal W(P75)
D Q
(One-shot timer mode)
T
INV11
T Q
To be set to “0” when timer A2 stops Diagram for switching to P80, P81 and P72 - P75 is not shown.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M32C/83 group
Mitsubishi Microcomputers

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Three-phase motor control timers’ functions

Triangular wave modulation

To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit
(bit 6 at 030816). Also, set “1” in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 030916). In this mode,
each of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register’s con-
tent to the counter every time timer B2 counter’s content becomes 000016. If “0” is set to the effective
interrupt output specification bit (bit 1 at 030816), the frequency of interrupt requests that occur every
time the timer B2 counter’s value becomes 000016 can be set by use of the timer B2 counter (030D16)
for setting the frequency of interrupt occurrences. The frequency of occurrences is given by (setting;
setting ≠ 0).
Setting “1” in the effective interrupt output specification bit (bit 1 at 0308 16) provides the means to
choose which value of the timer A1 reload control signal to use, “0” or “1”, to cause timer B2’s interrupt
request to occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at
030816).
An example of U phase waveform is shown in Figure 1.16.7, and the description of waveform output
workings is given below. Set “1” in DU0 (bit 0 at 030A16). And set “0” in DUB0 (bit 1 at 030A16). In
addition, set “0” in DU1 (bit 0 at 030B16) and set “1” in DUB1 (bit 1 at 030B16). Also, set “0” in the
effective interrupt output specification bit (bit 1 at 030816) to set a value in the timer B2 interrupt occur-
rence frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter’s
content becomes 000016 as many as (setting) times. Furthermore, set “1” in the effective interrupt output
specification bit (bit 1 at 030816), set in the effective interrupt polarity select bit (bit 0 at 030816) and set
“1” in the interrupt occurrence frequency set counter (030D16). These settings cause a timer B2 interrupt
to occur every other interval when the U phase output goes to “H”.
When the timer B2 counter’s content becomes 000016, timer A4 starts outputting one-shot pulses. In this
instance, the content of DU1 (bit 0 at 030B16) and that of DU0 (bit 0 at 030A16) are set in the three-phase
output shift register (U phase), the content of DUB1 (bit 1 at 030B16) and that of DUB0 (bit 1 at 030A16)
___
are set in the three-phase shift register (U phase). After triangular wave modulation mode is selected,
however, no setting is made in the shift register even though the timer B2 counter’s content becomes
000016.
___
The value of DU0 and that of DUB0 are output to the U terminal (P8 0) and to the U terminal (P81)
respectively. When the timer A4 counter counts the value written to timer A4 (034F16, 034E16) and when
timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one posi-
___
tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase
output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time
used for setting the time over which the “L” level of the U phase waveform doesn’t overlap the Low level
___
of the U phase waveform, which has the opposite phase of the former. The U phase waveform output
that started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-
shot pulses even though the three-phase output shift register’s content changes from “1” to “0” by the
effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses,
“0” already shifted in the three-phase shift register goes active, and the U phase waveform changes to
the Low level. When the timer B2 counter’s content becomes 000016, the timer A4 counter starts count-
ing the value written to timer A4-1 (030716, 030616), and starts outputting one-shot pulses. When timer
A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one position,
but if the three-phase output shift register’s content changes from “0” to “1” as a result of the shift, the
output level changes from “L” to “H” without waiting for the timer for setting dead time to finish outputting
one-shot pulses. A U phase waveform is generated by these workings repeatedly. With the exception
that the three-phase output shift register on the U phase side is used, the workings in generating a U

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Three-phase motor control timers’ functions

phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating
a U phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner
in which the “L” level of the U phase waveform doesn’t lap over that of the U phase waveform, which has
the opposite phase of the U phase waveform. The width of the “L” level too can be adjusted by varying
___ ___
the values of timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W
phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to
___
dealing with the U and U phases to generate an intended waveform.

A carrier wave of triangular waveform

Carrier wave

Signal wave

Timer B2

Timber B2 interrupt occurres

Rewriting timer A4 and timer A4-1.
Possible to set the number of overflows to generate an
Trigger signal for interrupt by use of the interrupt occurrences frequency
timer Ai start set circuit
(timer B2 overflow
signal)
The three-phase
m n m n m p o shift register
Timer A4 output shifts in
synchronization
with the falling
Control signal for edge of the A4
timer A4 reload output.

U phase
output signal

U phase
output signal

U phase
(Note 1)

U phase

Dead time

U phase
(Note 2)
U phase

Dead time
INV13(Triangular wave
modulation detect flag)
(Note 3)

Note 1: When INV14="0" (output wave Low active)

Note 2: When INV14="1" (output wave High active)
Note 3: Set to triangular wave modulation mode and to three-phase mode 1.

Figure 1.16.7. Timing chart of operation (1)

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Three-phase motor control timers’ functions

Assigning certain values to DU0 (bit 0 at 030A16) and DUB0 (bit 1 at 030A16), and to DU1 (bit 0 at
030B16) and DUB1 (bit 1 at 030B16) allows you to output the waveforms as shown in Figure 1.16.8, that
___ ___
is, to output the U phase alone, to fix U phase to “H”, to fix the U phase to “H,” or to output the U phase
alone.

A carrier wave of triangular waveform

Carrier wave

Signal wave

Timer B2

Rewriting timer A4 every timer B2 interrupt occurres.

Timer B2 interrupt occurres.

Trigger signal for Rewriting three-phase buffer register.
timer Ai start
(timer B2 overflow
signal)

m n m n m p o
Timer A4 output

Control signal for

timer A4 reload

U phase
output signal
U phase
output signal

U phase

U phase

Dead time

Note: Set to triangular wave modulation mode and to three-phase mode 1.

Figure 1.16.8. Timing chart of operation (2)

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Three-phase motor control timers’ functions

Sawtooth modulation
To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit
(bit 6 at 030816). Also, set “0” in the timers A4, A1, and A2-1 control bit (bit 1 at 030916). In this mode, the
timer registers of timers A4, A1, and of A2 comprise conventional timers A4, A1, and A2 alone, and
reload the corresponding timer register’s content to the counter every time the timer B2 counter’s con-
tent becomes 000016. The effective interrupt output specification bit (bit 1 at 030816) and the effective
interrupt output polarity select bit (bit 0 at 030816) go nullified.
An example of U phase waveform is shown in Figure 1.16.9, and the description of waveform output
workings is given below. Set “1” in DU0 (bit 0 at 030A16), and set “0” in DUB0 (bit 1 at 030A16). In
addition, set “0” in DU1 (bit 0 at 030B16) and set “1” in DUB1 (bit 1 at 030B16).
When the timber B2 counter’s content becomes 000016, timer B2 generates an interrupt, and timer A4
starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase
buffer registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents
of DUB1 and DUB0 are set in the three-phase output register (U phase). After this, the three-phase
buffer register’s content is set in the three-phase shift register every time the timer B2 counter’s content
becomes 000016.
___
The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81)
respectively. When the timer A4 counter counts the value written to timer A4 (034F16, 034E16) and when
timer A4 finishes outputting one-shot pulses, the three-phase output shift register’s content is shifted
one position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the
___
U output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time
used for setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level
___
of the U phase waveform, which has the opposite phase of the former. The U phase waveform output
that started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-
shot pulses even though the three-phase output shift register’s content changes from “1” to “0 ”by the
effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses,
0 already shifted in the three-phase shift register goes effective, and the U phase waveform changes to
the “L” level. When the timer B2 counter’s content becomes 000016, the contents of the three-phase
buffer registers DU1 and DU0 are set in the three-phase shift register (U phase), and the contents of
___
DUB1 and DUB0 are set in the three-phase shift register (U phase) again.
A U phase waveform is generated by these workings repeatedly. With the exception that the three-
___ ___
phase output shift register on the U phase side is used, the workings in generating a U phase waveform,
which has the opposite phase of the U phase waveform, are the same as in generating a U phase
waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which
the “L” level of the U phase waveform doesn’t lap over that of the U phase waveform, which has the
opposite phase of the U phase waveform. The width of the “L” level can also be adjusted by varying the
___ ___
values of timer B2 and timer A4. In dealing with the V and W phases, and V and W phases, the latter are
of opposite phase of the former, have the corresponding timers work similarly to dealing with the U and
___
U phases to generate an intended waveform.

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Three-phase motor control timers’ functions

A carrier wave of sawtooth waveform

Carrier wave

Signal wave

Timer B2

Data transfer is made from the three-

phase buffer registers to the three-
Interrupt occurres.
phase shift registers in step with the
Trigger signal for Rewriting the value of timer A4.
timing of the timer B overflow.
timer Ai start
(timer B2 overflow
signal)

The three-phase
Timer A4 output m n o p shift registers
shifts in
synchronization
with the falling
U phase output edge of timer A4.
signal

U phase
output signal

U phase

U phase

Dead time

Note: Set to sawtooth modulation mode and to three-phase mode 0.

Figure 1.16.9. Timing chart of operation (3)

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Three-phase motor control timers’ functions

___
Setting “1” both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U
phase output to “H” as shown in Figure 1.16.10.

A carrier wave of sawtooth waveform

Carrier wave

Signal wave

Timer B2

Interrupt occurres. Interrupt occurres. Data transfer is made from the three-
Rewriting the value of timer A4. Rewriting the value of timer A4. phase buffer registers to the three-
Trigger signal for Rewriting three-phase phase shift registers in step with the
timer Ai start output buffer register timing of the timer B overflow.
(timer B2 overflow
signal)

The three-phase
shift registers shifts
Timer A4 output m n p in synchronization
with the falling
edge of timer A4.

U phase
output signal

U phase
output signal

U phase

U phase

Dead time

Note: Set to sawtooth modulation mode and to three-phase mode 0.

Figure 1.16.10. Timing chart of operation (4)

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Serial I/O

Serial I/O
Serial I/O is configured as five channels: UART0 to UART4.
UARTi (i=0 to 4) each have an exclusive timer to generate a transfer clock, so they operate independently
of each other.
Figure 1.17.1 shows the block diagram of UARTi.
UARTi has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O
mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 036816,
02E816, 033816, 032816 and 02F816) determine whether UARTi is used as a clock synchronous serial I/O
or as a UART.
It has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin
are different in level.
Figures 1.17.2 through 1.17.8 show the registers related to UARTi.

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Serial I/O

TxD
RxD polarity
RxDi reversing circuit
polarity TxDi
reversing
UART reception circuit
1/16 Receive
Clock source selection Reception clock Transmit/
control circuit (Note)
Bit rate Clock synchronous type receive
f1
Internal generator unit
f8 UART transmission Transmit
f2n 1 / (ni+1) 1/16 Transmission clock
Clock synchronous type control circuit
External
Clock synchronous type
(when internal clock is selected)
1/2

Clock synchronous type Clock synchronous type

(when internal clock is selected) (when external clock is
CLK selected)
polarity
CLKi reversing
circuit CTS/RTS CTS/RTS disabled
selected
RTS2
CTSi / RTSi

Vcc
CTS/RTS disabled
CTS2
ni : Values set to UARTi bit rate generator (UiBRG)
Note :UART 2 is not CMOS output but N channel open drain output.

No reverse
RxD data
RxDi reverse circuit
Reverse

Clock
synchronous type
UART
(7 bits)
Clock UART
PAR UART(7 bits) UARTi receive register
synchronous (8 bits)
1SP disabled type
SP SP PAR
2SP UART Clock
PAR UART
enabled synchronous type
(9 bits)
UART
(8 bits)
UART
(9 bits)

UARTi receive
0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 buffer register
Address 036E16
Logic reverse circuit + MSB/LSB conversion circuit Address 036F16
Address 02EE16
Address 02EF16
Address 033E16
Data bus high-order bits Address 033F16
Address 032E16
Address 032F16
Address 02FE16
Data bus low-order bits Address 02FF16

Logic reverse circuit + MSB/LSB conversion circuit

D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTI transmit buffer

register
Address 036A16
Address 036B16
UART Address 02EA16
(8 bits) Address 02EB16
UART Address 033A16
(9 bits) Address 033B16
Address 032A16
UART Clock
PAR Address 032B16
(9 bits) synchronous type
enabled Address 02FA16
2SP UART
Address 02FB16
SP SP PAR
1SP PAR Clock
synchronous
UART UART(7 bits) UARTi transmit register
disabled (7 bits)
type
UART
(8 bits)
“0”
Clock
synchronous type
Error signal output
disable No reverse

Error signal TxD data TxDi

SP : Stop bit output circuit reverse circuit
PAR : Parity bit Error signal output Reverse
i : 0 to 4 enable

Figure 1.17.1. Block diagram of UARTi

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Serial I/O

UARTi transmit buffer register (i=0 to 4) (Note)

b15 b8
(b7) (b0) b7 b0 Symbol Address When reset
UiTB(i=0,1,2) 036B16, 036A16, 02EB16, 02EA16, 033B16, 033A16 Indeterminate
UiTB(i=3,4) 032B16, 032A16, 02FB16, 02FA16 Indeterminate

Bit Function Function

symbol (Clock synchronous serial I/O mode) (UART mode) R W

Transmit data Transmit data

Transmit data (9th bit)

Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note: Use MOV instruction to write to this register.

UARTi receive buffer register (i = 0 to 4)

b15 b8
(b7) (b0)b7 b0 Symbol Address When reset
UiRB(i=0,1,2) 036F16,036E16, 02EF16,02EE16, 033F16,033E16 Indeterminate
UiRB(i=3,4) 032F16,032E16, 02FF16,02FE16 Indeterminate

Bit Function Function

symbol Bit name (Clock synchronous R W
serial I/O mode) (UART mode)

Receive data Receive data

Receive data(9th bit)

Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.

Arbitration lost 0: Not detectet

ABT Invalid
detecting flag (Note 1) 1: Detected
Overrun error flag 0: No overrun error 0: No overrun error
OER
(Note 2) 1: Overrun error found 1: Overrun error found
Framing error flag 0: No framing error
FER Invalid
(Note 2) 1: Framing error found
Parity error flag 0: No parity error
PER Invalid
(Note 2) 1: Parity error found
Error sum flag 0: No error
SUM Invalid
(Note 2) 1: Error found
Note 1: Arbitration lost detecting flag must always write "0".
Note 2: Bits 15 through 12 are set to 0002 when the serial I/O mode select bit (bits 2 to 0 at addresses 036816,
02E816, 033816, 032816, 02F816) are set to "0002" or the receive enable bit is set to "0".
(Bit 15 is set to "0" when bits 14 to 12 all are set to "0".)
Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses
036E16, 02EE16, 033E16, 032E16, 02FE16) is read.

Figure 1.17.2. Serial I/O-related registers (1)

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Serial I/O

UARTi bit rate generator (i=0 to 4) (Note 1, 2)

b7 b0 Symbol Address When reset
UiBRG(i=0 to 4) 036916, 02E916, 033916, 032916, 02F916 Indeterminate

Function Values that can be set R W

Assuming that set value = n, BRGi divides

the count source by n+1 0016 to FF16

Note 1: Use MOV instruction to write to this register.

Note 2: Write a value to this register while transmit/receive halts.

UARTi transmit/receive mode register (i=0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
UiMR(i=0 to 4) 036816, 02E816, 033816, 032816, 02F816 0016

Bit Function Function

symbol Bit name (Clock synchronous R W
serial I/O mode) (UART mode)
b2 b1 b0 b2 b1 b0
SMD0 0 0 0: Serial I/O invalid 0 0 0: Serial I/O invalid
0 0 1: Serial I/O mode 1 0 0: Transfer data 7 bits long
Serial I/O mode 0 1 0: I2C mode 1 0 1: Transfer data 8 bits long
SMD1 1 1 0: Transfer data 9 bits long
select bit Must not be set
except above Must not be set
except above
SMD2

Internal/external 0 : Internal clock

(Note 1)
0 : Internal clock
CKDIR 1 : External clock
clock select bit 1 : External clock (Note 2)
(Note 2)
Stop bit length 0 : One stop bit
STPS Invalid
select bit 1 : Two stop bits

Odd/even parity Valid when bit 6 = "1"

PRY Invalid 0 : Odd parity
select bit 1 : Even parity
0 : Parity disabled
PRYE Parity enable bit Invalid
1 : Parity enabled
TxD,RxD input/
0: No reversed
IOPOL output polarity
switch bit (Note 3) 1: Reversed
Note 1: Select CLK output by the corresponding function select registers A, B and C.
Note 2: Set the corresponding function select register A to the I/O port.
Note 3: Normally set "0".

Figure 1.17.3. Serial I/O-related registers (2)

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UARTi transmit/receive control register 0 (i=0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
UiC0(i=0 to 4) 036C16, 02EC16, 033C16, 032C16, 02FC16 0816

Bit Function Function

symbol Bit name (Clock synchronous R W
serial I/O mode) (UART mode)
b1 b0
CLK0 0 0: f1 is selected
BRG count source 0 1: f8 is selected
select bit
1 0: f2n is selected
CLK1
1 1: Must not be set

CST/RTS function Valid when bit 4 = “0”

CRS 0 : CTS function is selected (Note 1)
select bit 1 : RTS function is selected (Note 2)
0 : Data present in transmit register
Transmit register (during transmission)
TXEPT
empty flag 1 : No data present in transmit register
(transmission completed)

CTS/RTS disable 0 : CTS/RTS function enabled

CRD
bit 1 : CTS/RTS function disabled

NCH Data output select 0 : TXDi pin is CMOS output

(Note 3) bit 1 : TXDi pin is N-channel open drain output
0 : Transmit data is output
at falling edge of transfer
CLK polarity clock and receive data
CKPOL Set to “0”
select bit is input at rising edge
1 : Transmit data is output
at rising edge of transfer
clock and receive data
is input at falling edge

Transfer format 0 : LSB first

UFORM
select bit (Note 4) 1 : MSB first

Note 1: Set the corresponding function select register A to I/O port, and port direction register to “0”
Note 2: Select RTS output using the corresponding function select registers A, B and C.
Note 3: UART2 transfer pin (TxD2:P70) is N-channel open drain output. It is not set to CMOS output.
Note 4: Valid only in clock syncronous serial I/O mode and 8 bits UART mode.

Figure 1.17.4. Serial I/O-related registers (3)

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UARTi transmit/receive control register 1 (i=0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
UiC1(i=0 to 4) 036D16, 02ED16, 033D16, 032D16, 02FD16 0216

Bit Function Function

symbol
Bit name (Clock synchronous
(UART mode)
R W
serial I/O mode)
Transmit 0: Transmission disabled
TE
enable bit 1: Transmission enabled

Transmit buffer 0: Data present in transmit buffer register

TI
empty flag 0: No data present in transmit buffer register

Receive 0: Reception disabled

RE
enable bit 1: Reception enabled

Receive 0: Data present in receive buffer register

RI
complete flag 0: No data present in receive buffer register
UARTi transmit 0: Transmit buffer empty (TI = 1)
UiIRSinterrupt cause
select bit 1: Transmit is completed (TXEPT = 1)
UARTi 0: Continuous receive
UiRRM continuous mode disabled
receive mode 1: Continuous receive Set to “0”
enable bit mode enabled
Data logic 0: No reverse
UiLCH
select bit 1: Reverse

SCLKSTPB Clock divide Clock divide synchronizing stop bit

synchronizing stop bit 0: Synchronizing stop
/error signal output Set to “0”
/UiERE 1: Synchronous start (Note)
enable bit
Note :When this bit and bit 7 of UARTi special mode register 2 are set, clock synchronizing function is used.

UARTi special mode register (i=0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
UiSMR(i=0 to 4) 036716, 02E716, 033716, 032716, 02F716 0016

Bit Function Function

Bit name (Clock synchronous R W
symbol serial I/O mode) (UART mode)

IIC mode 0: Normal mode

IICM Set to "0"
select bit 1: IIC mode
Arbitration lost
0: Update per bit
ABC detecting flag Set to "0"
control bit 1: Update per byte
0: STOP condition
detected
BBS Bus busy flag 1: START condition Set to "0"
detected (Note 1)
SCLL sync
0: Disabled
LSYN output enable Set to "0"
bit 1: Enabled
Bus collision 0: Rising edge of transfer clock
ABSCS detect sampling Set to "0" 1: Underflow signal of timer Ai
clock select bit (Note 2)
Auto clear function 0: No auto clear function
ACSE select bit of transmit Set to "0" 1: Auto clear at
enable bit occurrence of bus
Transmit start 0: Ordinary
SSS condition Set to "0"
select bit 1: Falling edge of RxDi

Clock divide 0: Divided-by-2

SCLKDIV (Note 3) Set to "0"
set bit 1: No divided
Note 1: Nothing but "0" may be written.
Note 2: UART0: timer A3 underflow signal, UART1: timer A4 underflow signal, UART2: timer A0 underflow signal,
UART3: timer A3 underflow signal, UART4: timer A4 underflow signal.
Note 3: When this bit and bit 7 of UARTi transmit/receive control register 1 are set, clock synchronizing
function is used.

Figure 1.17.5. Serial I/O-related registers (4)

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Serial I/O

UARTi special mode register 2 (i=0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
UiSMR2(i=0 to 4) 036616, 02E616, 033616, 032616, 02F616 0016

Bit
symbol
Bit name Function R W
0: NACK/ACK interrupt (DMA source - ACK)
Transfer to receive buffer at the rising
edge of last bit of receive clock
Receive interrupt occurs at the rising edge
IIC mode select of last bit of receive clock
IICM2 1: UART transfer/receive interrupt (DMA
bit 2
source - UART receive)
Transfer to receive buffer at the falling
edge of last bit of receive clock
Receive interrupt occurs at the falling
edge of last bit of receive clock
Clock 0: Disabled
CSC
synchronous bit 1: Enabled

0: Disabled
SWC SCL wait output bit
1: Enabled

0: Disabled
ALS SDA output stop bit
1: Enabled

0: Disabled
STC UARTi initialize bit
1: Enabled

SCL wait output 0: UARTi clock

SWC2
bit 2 1: 0 output

SDA output inhibit 0: Disabled

SDHI
bit 1: Enabled (high impedance)
Clock divide 0: Synchronous disabled
SU1HIM synchronizing
enable bit 1: Synchronous enabled

Figure 1.17.6. Serial I/O-related registers (5)

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Serial I/O

UARTi special mode register 3 (i=0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
UiSMR3(i=0 to 4) 036516, 02E516, 033516, 032516, 02F516 0016

Bit Bit name Function

symbol R W

SS port function 0: SS function disabled

SSE
enable bit (Note 1) 1: SS function enabled

Clock phase 0: Without clock delay

CKPH
set bit 1: With clock delay

Serial input port 0: Select TxDi and RxDi (master mode)

DINC
set bit 0: Select STxDi and SRxDi (slave mode)

Clock output 0: CLKi is CMOS output (Note 2)

NODC
select bit 1: CLKi is N-channel open drain output (Note 3)

0: Without fault error

ERR Fault error flag
1: With fault error (Note 4)
b7 b6 b5
DL0 000 :Without delay
001 :2-cycle of BRG count source
010 :3-cycle of BRG count source
SDAi(TxDi) digital 011 :4-cycle of BRG count source
DL1
delay time set bit 100 :5-cycle of BRG count source
(Note 5,6) 101 :6-cycle of BRG count source
DL2 110 :7-cycle of BRG count source
111 :8-cycle of BRG count source

Note 1: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control
register 0) to "1".
Note 2: Set CLKi and TxDi both for output using the CLKi and TxDi function select register A. Set the
RxDi function select register A for input/output port and the port direction register to "0".
Note 3: Set STxDi for output using the STxDi function select registers A and B. Set the CLKi and
SRxDi function select register A for input/output port and the port direction register to "0".
Note 4: Nothing but "0" may be written.
Note 5: These bits are used for SDAi (TxDi) output digital delay when using UARTi for IIC interface.
Otherwise, must set to "000".
Note 6: When external clock is selected, delay is increased approximately 100ns.

Figure 1.17.7. Serial I/O-related registers (6)

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UARTi special mode register 4 (i=0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
UiSMR4(i=0 to 4) 036416, 02E416, 033416, 032416, 02F416 0016

Bit
Bit name Function R W
symbol

Start condition 0: Clear

STAREQ generate bit (Note) 1: Start

Restart condition 0: Clear

RSTAREQ generate bit (Note) 1: Start

Stop condition 0: Clear

STPREQ generate bit (Note) 1: Start

SCL, SDA output 0: Ordinal block

STSPSEL select bit 1: Start/stop condition generate block

0: ACK
ACKD ACK data bit
1: NACK

ACK data output 0: SI/O data output

ACKC enable bit 1: ACKD output

SCL output stop 0: Disabled

SCLHI
enable bit 1: Enabled

SCL wait output 0: SCL "L" hold disabled

SWC9 bit 3 1: SCL "L" hold enabled
Note :When start condition is generated, these bits automatically become "0".

AAA
AA
AExternal interrupt request cause select register

AAAA
AA
b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset

IFSR 031F16 0016

AA
Bit symbol Bit name Function R W

AA
IFSR0 INT0 interrupt polarity 0 : One edge
select bit (Note) 1 : Both edges

AA
IFSR1 INT1 interrupt polarity 0 : One edge
select bit (Note) 1 : Both edges

IFSR2

IFSR3
INT2 interrupt polarity
select bit (Note)
INT3 interrupt polarity
0 : One edge
1 : Both edges
0 : One edge
AA
AA
AA
select bit (Note) 1 : Both edges

AA
IFSR4 INT4 interrupt polarity 0 : One edge
select bit (Note) 1 : Both edges
IFSR5 INT5 interrupt polarity 0 : One edge
select bit (Note) 1 : Both edges

AA
IFSR6 UART0/3 interrupt 0 : UART3 bus collision /start,stop
cause select bit detect/false error detect
1 : UART0 bus collision /start,stop
detect/false error detect

AA
IFSR7 UART1/4 interrupt 0 : UART4 bus collision /start,stop
cause select bit detect/false error detect
1 : UART1 bus collision /start,stop
detect/false error detect

Note :When level sense is selected, set this bit to "0".

When both edges are selected, set the corresponding polarity switching bit of INT interrupt control
register to "0" (falling edge).

Figure 1.17.8. Serial I/O-related registers (7)

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Clock synchronous serial I/O mode

(1) Clock synchronous serial I/O mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.18.1
and 1.18.2 list the specifications of the clock synchronous serial I/O mode.

Table 1.18.1. Specifications of clock synchronous serial I/O mode (1/2)

Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • When internal clock is selected (bit 3 at addresses 036816, 02E816, 033816, 032816,
02F816 = “0”) : fi/ 2(m+1) (Note 1) fi = f1, f8, f2n(Note 2)
_ CLK is selected by the corresponding peripheral function select register A, B and C.
• When external clock is selected (bit 3 at addresses 036816, 02E816, 033816 , 032816,
02F816= “1”) : Input from CLKi pin
_ Set the corresponding function select register A to I/O port
_______ _______ _______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at addresses 036D16, 02ED16, 033D16, 032D16, 02FD16) = “1”

_ Transmit buffer empty flag (bit 1 at addresses 036D16, 02ED16, 033D16, 032D16, 02FD16) = “0”
_______ _______
_ When CTS function selected, CTS input level = “L”
_ TxD output is selected by the corresponding peripheral function select register A, B and C.
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “1”: CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at addresses 036D 16, 02ED16, 033D16, 032D16, 02FD16) = “1”
_ Transmit enable bit (bit 0 at addresses 036D 16, 02ED16, 033D16, 032D16, 02FD16) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 036D16, 02ED16, 033D16, 032D16, 02FD16) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “1”: CLKi input level = “L”
Interrupt request • When transmitting
generation timing _ Transmit interrupt cause select bit (bit 4 at address 036D16, 02ED16, 033D16,
032D16, 02FD16) = “0”: Interrupts requested when data transfer from UARTi trans-
fer buffer register to UARTi transmit register is completed
_ Transmit interrupt cause select bit (bit 4 at address 036D16, 02ED16, 033D16,
032D16, 02FD16) = “1”: Interrupts requested when data transmission from UARTi
transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to UARTi
receive buffer register is completed
Note 1: “m” denotes the value 0016 to FF16 that is set to the UART bit rate generator.

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Clock synchronous serial I/O mode

Table 1.18.2. Specifications of clock synchronous serial I/O mode (2/2)

Item Specification
Error detection • Overrun error (Note)
This error occurs when the next data is started to receive and 6.5 transfer clock is
elapsed before UARTi receive buffer register are read out.
Select function • CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the transfer
clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Reversing serial data logic
Whether to reverse data in writing to the transmission buffer register or reading the
reception buffer register can be selected.
• TxD, RxD I/O polarity reverse
This function is reversing TxD port output and RxD port input. All I/O data level is
reversed.
Note : If an overrun error occurs, the UARTi receive buffer will have the next data written in.

Table 1.18.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note
that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin
outputs a “H”. (If the N-channel open drain is selected, this pin is in floating state.)

Table 1.18.3. Input/output pin functions in clock synchronous serial I/O mode
Pin name Function Method of selection
TxDi Serial data output (Outputs dummy data when performing reception only)
(P63, P67, P70, (Note 1)
P92, P96)
RxDi Serial data input Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address
(P62, P66, P71, (Note 2) 03C216, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= “0”
P91, P97) (Can be used as an input port when performing transmission only)

CLKi Transfer clock output Internal/external clock select bit (bit 3 at addresses 036816, 02E816,
(P61, P65, P72, (Note 1) 033816, 032816, 02F816) = “0”
P90, P95)
Transfer clock input Internal/external clock select bit (bit 3 at addresses 036816, 02E816,
(Note 2) 033816, 032816, 02F816) = “1”
Port P61, P65, P72, P90 and P95 direction register (bits 1 and 5 at address
03C216, bit 2 at address 03C316, bit 0 and 5 at address 03C716) = “0”
CTSi/RTSi CTS input CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16, 032C16,
(P60, P64, P73, (Note 2) 02FC16) =“0”
P93, P94) CTS/RTS function select bit (bit 2 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “0”
Port P60, P64, P73, P93 and P94 direction register (bits 0 and 4 at address
03C216, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = “0”
RTS output (Note 1) CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “0”
CTS/RTS function select bit (bit 2 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “1”
Programmable I/O port CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16,
(Note 2) 032C16, 02FC16) = “1”
________
Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B and C.
Note 2: Select I/O port by the corresponding function select register A.

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Clock synchronous serial I/O mode

• Example of transmit timing (when internal clock is selected)

Tc

Transfer clock

“1”
Transmit enable
bit (TE) “0” Data is set in UARTi transmit buffer register

Transmit buffer “1”

empty flag (Tl) “0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi TCLK
“L”
Stopped pulsing because CTS = “H” Stopped pulsing because transfer enable bit = “0”

CLKi

TxDi D0 D 1 D2 D3 D4 D5 D6 D7 D0 D 1 D2 D3 D4 D5 D 6 D7 D 0 D1 D2 D 3 D 4 D 5 D6 D7

Transmit “1”
register empty
“0”
flag (TXEPT)
Transmit interrupt “1”
request bit (IR) “0”

Cleared to “0” when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

The above timing applies to the following settings: Tc = TCLK = 2(m + 1) / fi

• Internal clock is selected. fi: frequency of BRGi count source (f1, f8, f2n)
• CTS function is selected. m: value set to BRGi
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.

• Example of receive timing (when external clock is selected)

Receive enable “1”
bit (RE) “0”

Transmit enable “1”

bit (TE) Dummy data is set in UARTi transmit buffer register
“0”

Transmit buffer “1”

empty flag (Tl)
“0” Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
RTSi
“L”
1 / fEXT
CLKi
Receive data is taken in

RxDi D0 D 1 D2 D3 D4 D 5 D6 D7 D 0 D1 D2 D3 D 4 D5 D6 D7 D0 D1 D2 D 3 D4 D 5 D

Transferred from UARTi receive register Read out from UARTi receive buffer register
Receive complete “1” to UARTi receive buffer register
flag (Rl) “0”

Receive interrupt “1”

request bit (IR) “0”

Cleared to “0” when interrupt request is accepted, or cleared by software

Over run error “1”
flag(OER) “0”

Shown in ( ) are bit symbols.

The above timing applies to the following settings: The following conditions are met when the CLKi
• External clock is selected. input before data reception = “H”
• RTS function is selected. • Transmit enable bit “1”
• CLK polarity select bit = “0”. • Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
fEXT: frequency of external clock

Figure 1.18.1. Typical transmit/receive timings in clock synchronous serial I/O mode

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Clock synchronous serial I/O mode

(a) Polarity select function

As shown in Figure 1.18.2, the CLK polarity select bit (bit 6 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) allows selection of the polarity of the transfer clock.

• When CLK polarity select bit = “0”

CLKi

D0 D1 D2 D3 D4 D5 D6 D7
Note 1: The CLK pin level when not
TXDi
transferring data is “H”.

R XD i D0 D1 D2 D3 D4 D5 D6 D7

• When CLK polarity select bit = “1”

CLKi
Note 2: The CLK pin level when not
TXDi D0 D1 D2 D3 D4 D5 D6 D7 transferring data is “L”.

RXDi D0 D1 D2 D3 D4 D5 D6 D7

Figure 1.18.2. Polarity of transfer clock

(b) LSB first/MSB first select function

As shown in Figure 1.18.3, when the transfer format select bit (bit 7 at addresses 036C16, 02EC16,
033C16, 032C16, 02FC16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format
is “MSB first”.

• When transfer format select bit = “0”

CLKi

TXDi D0 D1 D2 D3 D4 D5 D6 D7
LSB first
R XD i D0 D1 D2 D3 D4 D5 D6 D7

• When transfer format select bit = “1”

CLKi

TXDi D7 D6 D5 D4 D3 D2 D1 D0
MSB first
RXDi D7 D6 D5 D4 D3 D2 D1 D0

Note: This applies when the CLK polarity select bit = “0”.

Figure 1.18.3. Transfer format

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Clock synchronous serial I/O mode

(c) Continuous receive mode

If the continuous receive mode enable bit (bit 5 at address 036D16, 02ED 16, 033D16, 032D16,
02FD16) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive
buffer register is read out, the unit simultaneously goes to a receive enable state without having to set
dummy data back to the transmit buffer register again.

(d) Serial data logic switch function

When the data logic select bit (bit6 at address 036D16, 02ED16, 033D16, 032D16, 02FD16) = “1”, and
writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure
1.18.4 shows the timing example of serial data logic switch.

•When LSB first

“H”
Transfer clock
“L”

TxDi “H”
D0 D1 D2 D3 D4 D5 D6 D7
(no reverse) “L”

TxDi “H”
D0 D1 D2 D3 D4 D5 D6 D7
(reverse) “L”

Figure 1.18.4. Timing for switching serial data logic

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Clock asynchronous serial I/O (UART) mode

(2) Clock asynchronous serial I/O (UART) mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.19.1 and 1.19.2 list the specifications of the UART mode. Figure 1.19.1 shows the
UARTi transmit/receive mode register.

Table 1.19.1. Specifications of UART Mode (1/2)

Item Specification
Transfer data format • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock • When internal clock is selected (bit 3 at addresses 036816, 02E816, 033816, 032816,
02F816 = “0”) : fi/16(m+1) (Note 1) fi = f1, f8, f2n
• When external clock is selected (bit 3 at addresses 036816, 02E816, 033816, 032816,
02F816 =“1”) : fEXT/16(m+1)(Note 1, 2)
_______ _______ _______ _______
Transmission/reception control • CTS function, RTS function, CTS/RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 036D 16, 02ED16, 033D16, 032D16, 02FD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 036D16, 02ED16, 033D16, 032D16,
02FD16) = “0”
_______ _______
- When CTS function selected, CTS input level = “L”
- TxD output is selected by the corresponding peripheral function select register A, B
and C.
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 036D16, 02ED16, 033D16, 032D16, 02FD16) = “1”
- Start bit detection
Interrupt request • When transmitting
generation timing - Transmit interrupt cause select bits (bit 4 at address 036D16, 02ED16, 033D16,
032D16, 02FD16) = “0”: Interrupts requested when data transfer from UARTi transfer
buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bit 4 at address 036D16, 02ED16, 033D16,
032D16, 02FD16) = “1”: Interrupts requested when data transmission from UARTi
transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to UARTi
receive buffer register is completed
Error detection • Overrun error (Note 3)
This error occurs when the next data is started to receive and 6.5 transfer
clock is elapsed before UARTi receive buffer register are read out.
Note 1: ‘m’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will be over written with the next data.

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Clock asynchronous serial I/O (UART) mode

Table 1.19.2. Specifications of UART Mode (2/2)

Item Specification
Error detection • Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
If parity is enabled this error occurs when, the number of 1’s in parity and character
bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is e n c o u n -
tered
Select function • Serial data logic switch
This function reveres the logic value of transferring data. Start bit, parity bit and stop
bit are not reversed.
• TxD, RxD I/O polarity switch
This function reveres the TxD port output and RxD port input. All I/O data level is
reversed.

Table 1.19.3 lists the functions of the input/output pins in UART mode. Note that for a period from when
the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-
channel open drain is selected, this pin is in floating state.)

Table 1.19.3. Input/output pin functions in UART mode

Pin name Function Method of selection
TxDi Serial data output
(P63, P67, P70, (Note 1)
P92, P96)
RxDi Serial data input Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address
(P62, P66, P71, (Note 2) 03C216, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= “0”
P91, P97) (Can be used as an input port when performing transmission only)

CLKi Programmable I/O port Internal/external clock select bit (bit 3 at addresses 036816, 02E816,
(P61, P65, P72, (Note 2) 033816, 032816, 02F816) = “0”
P90, P95) Transfer clock input Internal/external clock select bit (bit 3 at addresses 036816, 02E816,
(Note 2) 033816, 032816, 02F816) = “1”
Port P61, P65, P72, P90 and P95 direction register (bits 1 and 5 at address
03C216, bit 2 at address 03C316, bits 0 and 5 at address 03C716) = “0”
CTSi/RTSi CTS input CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16,
(P60, P64, P73, (Note 2) 032C16, 02FC16) =“0”
P93, P94) CTS/RTS function select bit (bit 2 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “0”
Port P60, P64, P73, P93 and P94 direction register (bits 0 and 4 at address
03C216, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = “0”
RTS output (Note 1) CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “0”
CTS/RTS function select bit (bit 2 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “1”
Programmable I/O port CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16, 032C16,
(Note 2) 02FC16) = “1”
________
Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B and C.
Note 2: Select I/O port by the corresponding function select register A.

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Clock asynchronous serial I/O (UART) mode

• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc

Transfer clock

Transmit enable “1”

bit(TE) “0” Data is set in UARTi transmit buffer register.
Transmit buffer “1”
empty flag(TI) “0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
“L”
Start Parity Stop Stopped pulsing because transmit enable bit = “0”
bit bit bit
TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1

Transmit register “1”

empty flag (TXEPT)
“0”

Transmit interrupt “1”

request bit (IR) “0”

Cleared to “0” when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

The above timing applies to the following settings : Tc = 16 (m + 1) / fi or 16 (m + 1) / fEXT

• Parity is enabled. fi : frequency of BRGi count source (f1, f8, f2n)
• One stop bit. fEXT : frequency of BRGi count source (external clock)
• CTS function is selected. m : value set to BRGi
• Transmit interrupt cause select bit = “1”.

• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

Tc

Transfer clock

Transmit enable “1”

bit(TE) “0” Data is set in UARTi transmit buffer register

Transmit buffer “1”

empty flag(TI) “0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start Stop Stop
bit bit bit
TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1

Transmit register “1”

empty flag (TXEPT)
“0”

Transmit interrupt “1”

request bit (IR) “0”

Cleared to “0” when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.
The above timing applies to the following settings : Tc = 16 (m + 1) / fi or 16 (m + 1) / fEXT
• Parity is disabled. fi : frequency of BRGi count source (f1, f8, f2n)
• Two stop bits. fEXT : frequency of BRGi count source (external clock)
• CTS function is disabled. m : value set to BRGi
• Transmit interrupt cause select bit = “0”.

Figure 1.19.1. Typical transmit timings in UART mode

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Clock asynchronous serial I/O (UART) mode

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

BRGi count
source
“1”
Receive enable bit
“0”
Stop bit
RxDi Start bit D0 D1 D7
Sampled “L”
Receive data taken in
Transfer clock
Reception triggered when transfer clock Transferred from UARTi receive register to
Receive “1” is generated by falling edge of start bit UARTi receive buffer register
complete flag “0”
“H”
RTSi
“L” Becomes “L” by reading the receive buffer
Receive interrupt “1”
request bit “0”

Cleared to “0” when interrupt request is accepted, or cleared by software

The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.

Figure 1.19.2. Typical receive timing in UART mode

(a) Function for switching serial data logic

When the data logic select bit (bit 6 of address 036D16, 02ED16, 033D16, 032D16, 02FD16) is assigned
1, data is inverted in writing to the transmission buffer register or reading the reception buffer register.
Figure 1.19.3 shows the example of timing for switching serial data logic.

• When LSB first, parity enabled, one stop bit

“H”
Transfer clock
“L”

TxDi “H”
(no reverse) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
“L”

TxDi “H”
(reverse) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
“L”

ST : Start bit
P : Even parity
SP : Stop bit

Figure 1.19.3. Timing for switching serial data logic

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Clock asynchronous serial I/O (UART) mode

(b) TxD, RxD I/O polarity reverse function

This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
normal use.

(c) Bus collision detection function

This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.19.4
shows the example of detection timing of a bus collision (in UART mode).
UART0 and UART3 are allocated to software interrupt number 40. UART1 and UART4 are allocated
to software interrupt number 41. When selecting UART 0, 3, 1 or 4 bus collision detect function, bit 6
or 7 of external interrupt cause select register (address 031F16) must be set.

“H”
Transfer clock
“L”

“H”
TxDi ST SP
“L”

“H”
RxDi ST SP
“L”

Bus collision detection “1”

interrupt request signal “0”

Bus collision detection “1”

interrupt request bit “0”
ST : Start bit
SP : Stop bit

Figure 1.19.4. Detection timing of a bus collision (in UART mode)

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UARTi Special Mode Register

UARTi Special Mode Register

UARTi (i=0 to 4) operate the IIC bus interface (simple IIC bus) using the UARTi special mode register
(addresses 036716, 02E716, 033716, 032716 and 02F716) and UARTi special mode register 2 (addresses
036616, 02E616, 033616, 032616 and 02F616). UARTi add special functions using UARTi special mode
resister 3 (addresses 036516, 02E516, 035516, 032516 and 02F516).

(1) IIC Bus Interface Mode

The I2C bus interface mode is provided with UARTi.
Table 1.21.1 shows the construction of the UARTi special mode register and UARTi special mode regis-
ter 2.
When the I2C mode select bit (bit 0 in addresses 036716, 02E716, 033716, 032716 and 02F716) is set to
“1”, the I2C bus (simple I2C bus) interface circuit is enabled.
To use the I2C bus, set the SCLi and the SDAi of both master and slave to output with the function select
register. Also, set the data output select bit (bit 5 in address 036C16, 02EC16, 033C16, 032C16 and
02FC16) to N-channel open drain output.
Table 1.21.1 shows the relationship of the IIC mode select bit to control. To use the chip in the clock
synchronized serial I/O mode or UART mode, always set this bit to “0”.

Table 1.21.1. Features in I2C mode

Function Normal mode (IICM=0) I2C mode (IICM=1) (Note 1)
(Note 2) Start condition detection or stop
1 Factor of interrupt number 39 to 41 Bus collision detection condition detection
(Note 2)
2 Factor of interrupt number 17, 19, 33, 35, 37 UARTi transmission No acknowledgment detection (NACK)
(Note 2)
3 Factor of interrupt number 18, 20, 34, 36, 38 UARTi reception Acknowledgment detection (ACK)

4 UARTi transmission output delay Not delayed Delayed

5 P63, P67, P70, P92, P96 at the time when UARTi

TxDi (output) SDAi (input/output)
is in use
6 P62, P66, P71, P91, P97 at the time when UARTi
RxDi (input) SCLi (input/output)
is in use
7 P61, P65, P72, P90, P95 at the time when UARTi CLKi P61, P65, P72, P90, P95 (Note 3)
is in use
8 DMA factor at the time UARTi reception Acknowledgment detection (ACK)

9 Noise filter width 15ns 50ns

Reading the terminal when 0 is Reading the terminal regardless of the
10 Reading P62, P66, P71, P91, P97 assigned to the direction register value of the direction register
The value set in latch P63, P67, P70,
H level (when 0 is assigned to P92, P96 when the port is selected
11 Initial value of UARTi output
the CLK polarity select bit) (Note 3)

Note 1: Make the settings given below when I2C mode is used.
Set 0 1 0 in bits 2, 1, 0 of the UARTi transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.
Note 2: Follow the steps given below to switch from one factor to another.
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when IIC mode (IIC mode select bit = "1") is valid and serial I/O is invalid.

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UARTi Special Mode Register

TXDi/SDA

Timer To DMAi
Selector
I/O
UARTi transmission/
UARTi IICM=1 IICM=0 or IICM2=1 NACK interrupt
delay Transmission register request

IICM=0 UARTi IICM=1 and

SDHI IICM2=0
ALS

D
To DMAi
Q
Arbitration
T
Noize IICM=0 or
Filter IICM=1 IICM2=1 UARTi reception/ACK
interrupt request
Reception register DMAi request
IICM=0 UARTi
IICM=1 and
Start condition detection IICM2=0

S Bus
Q busy
R
Stop condition detection

NACK
L-synchronous D Q
Falling edge output enabling bit T
detection
RxDi/SCL D Q
I/0 R T ACK
Data register
9th pulse
Selector Bus collision/start, stop
IICM=1 condition detection
UARTi Internal clock
interrupt request
IICM=1 SWC2 Bus collision
CLK
IICM=1 detection IICM=0
Noize control
Filter External clock UARTi
Noize
Filter Falling edge of 9th pulse
IICM=0 R
S SWC

Port reading
UARTi * With IICM set to 1, the port terminal is to be readable
CLKi IICM=0 even if 1 is assigned to P71 of the direction register.
Serector
I/0
Timer

Figure 1.21.1. Functional block diagram for I2C mode

Figure 1.21.1 is a block diagram of the IIC bus interface.

The control bits of the IIC bus interface is explained as follow:

UARTi Special Mode Register (UiSMR:Addresses 036716, 02E716, 033716, 032716, 02F716)
Bit 0 is the IIC mode select bit. When set to “1”, ports operate respectively as the SDAi data transmis-
sion-reception pin, SCLi clock I/O pin and port. A delay circuit is added to SDAi transmission output,
therefore after SCLi is sufficiently L level, SDAi output changes. Port (SCLi) is designed to read pin
level regardless of the content of the port direction register. SDAi transmission output is initially set to
port in this mode. Furthermore, interrupt factors for the bus collision detection interrupt, UARTi trans-
mission interrupt and UARTi reception interrupt change respectively to the start/stop condition detec-
tion interrupts, acknowledge non-detection interrupt and acknowledge detection interrupt.

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UARTi Special Mode Register

The start condition detection interrupt is generated when the falling edge at the SDAi pin is detected
while the SCLi pin is in the H state. The stop condition detection interrupt is generated when the rising
edge at the SDAi pin is detected while the SCLi pin is in the H state.
The acknowledge non-detection interrupt is generated when the H level at the SDAi pin is detected at
the 9th rise of the transmission clock.
The acknowledge detection interrupt is generated when the L level at the SDAi pin is detected at the
9th rise of the transmission clock. Also, DMA transfer can be started when the acknowledge is de-
tected and UARTi transmission is selected as the DMAi request factor.

Bit 1 is the arbitration lost detection flag control bit (ABC). Arbitration detects a conflict between data
transmitted at SCLi rise and data at the SDAi pin. This detection flag is allocated to bit 11 in UARTi
transmission buffer register (addresses 036F16, 02EF16, 033F16, 032F16, 02FF16). It is set to “1” when
a conflict is detected. With the arbitration lost detection flag control bit, it can be selected to update the
flag in units of bits or bytes. When this bit is set to “1”, update is set to units of byte. If a conflict is then
detected, the arbitration lost detection flag control bit will be set to “1” at the 9th rise of the clock. When
updating in units of byte, always clear (“0” interrupt) the arbitration lost detection flag control bit after
the 1st byte has been acknowledged but before the next byte starts transmitting.

Bit 2 is the bus busy flag (BBS). It is set to “1” when the start condition is detected, and reset to “0”
when the stop condition is detected.

Bit 3 is the SCLi L synchronization output enable bit (LSYN). When this bit is set to “1”, the port data
register is set to “0” in sync with the L level at the SCLi pin.

Bit 4 is the bus collision detection sampling clock select bit (ABSCS). The bus collision detection
interrupt is generated when RxDi and TxDi level do not conflict with one another. When this bit is “0”,
a conflict is detected in sync with the rise of the transfer clock. When this bit is “1”, detection is made
when timer Ai (timer A3 with UART0, timer A4 with UART1, timer A0 with UART2, timer A3 with
UART3 and timer A4 with UART4) underflows. Operation is shown in Figure 1.21.2.

Bit 5 is the transmission enable bit automatic clear select bit (ACSE). By setting this bit to “1”, the
transmission bit is automatically reset to “0” when the bus collision detection interrupt factor bit is “1”
(when a conflict is detected).

Bit 6 is the transmission start condition select bit (SSS). By setting this bit to “1”, TxDi transmission
starts in sync with the rise at the RxDi pin.

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UARTi Special Mode Register

1. Bus collision detect sampling clock select bit (Bit 4 of the UARTi special mode register)
0: Rising edges of the transfer clock

CLKi

TxDi/RxDi
1: Timer Ai underflow

Timer Ai

2. Auto clear function select bit of transmit enable bit (Bit 5 of the UARTi special mode
register)

CLKi

TxDi/RxDi

Bus collision
detect interrupt
request bit
Transmit
enable bit

3. Transmit start condition select bit (Bit 6 of the UARTi special mode register)
0: In normal state
CLKi

TxDi
Enabling transmission

With "1: falling edge of RxDi" selected

CLKi

TxDi

RxDi

Figure 1.21.2. Some other functions added

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UARTi Special Mode Register

UARTi Special Mode Register 2 (UiSMR2:Addresses 036616, 02E616, 033616, 032616, 02F616)
Bit 0 is the IIC mode select bit 2 (IICM2). Table 1.21.2 gives control changes by bit when the IIC mode
select bit is “1”. Start and stop condition detection timing characteristics are shown in Figure 1.21.4.
Always set bit 7 (start/stop condition control bit) to “1”.

Bit 1 is the clock synchronizing bit (CSC). When this bit is set to “1”, and the rising edge is detected at
pin SCLi while the internal SCL is High level, the internal SCL is changed to Low level, the baud rate
generator value is reloaded and the Low sector count starts. Also, while the SCLi pin is Low level, and
the internal SCL changes from Low level to High, baud rate generator stops counting. If the SCLi pin
is H level, counting restarts. Because of this function, the UARTi transmission-reception clock takes
the AND condition for the internal SCL and SCLi pin signals. This function operates from the clock half
period before the 1st rise of the UARTi clock to the 9th rise. To use this function, select the internal
clock as the transfer clock.

Bit 2 is the SCL wait output bit (SWC). When this bit is set to “1”, output from the SCLi pin is fixed to L
level at the clock’s 9th rise. When set to “0”, the Low output lock is released.

Bit 3 is the SDA output stop bit (ALS). When this bit is set to “1”, an arbitration lost is generated. If the
arbitration lost detection flag is “1”, then the SDAi pin simultaneously becomes high impedance.

Bit 4 is the UARTi initialize bit (STC). While this bit is set to “1”, the following operations are performed
when the start condition is detected.
1. The transmission shift register is initialized and the content of the transmission register is trans-
mitted to the transmission shift register. As such, transmission starts with the 1st bit of the next
input clock. However, the UARTi output value remains the same as when the start condition was
detected, without changing from when the clock is input to when the 1st bit of data is output.
2. The reception shift register is initialized and reception starts with the 1st bit of the next input
clock.
3. The SCL wait output bit is set to “1”. As such, the SCLi pin becomes Low level at the rise of the
9th bit of the clock.
When UART transmission-reception has started using this function, the content of the transmission
buffer available flag does not change. Also, to use this function, select an external clock as the transfer
clock.

Bit 5 is SCL wait output bit 2 (SWC2). When this bit is set to “1” and serial I/O is selected, an Low level
can be forcefully output from the SCLi pin even during UART operation. When this bit is set to “0', the
Low output from the SCLi pin is canceled and the UARTi clock is input and output.

Bit 6 is the SDA output disable bit (SDHI). When this bit is set to “1”, the SDAi pin is forced to high
impedance. To overwrite this bit, do so at the rise of the UARTi transfer clock. The arbitration lost
detection flag may be set.

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UARTi Special Mode Register

Table 1.21.2. Functions changed by I2C mode select bit 2

Function IICM2 = 0 IICM2 = 1
Interrupt no. 17, 19, 33, 35, 37 fac- Acknowledge not detect UARTi transfer (rising edge of the
tor (NACK) last bit)
Interrupt no. 18, 20, 34, 36, 38 fac- Acknowledge detect (ACK) UARTi receive (falling edge of the
tor last bit)
DMA factor Acknowledge detect (ACK) UARTi receive (falling edge of the
last bit)
Data transfer timing from UART re- Rising edge of the last bit of re- Rising edge of the last bit of re-
ceive shift register to receive buffer ceive clock ceive clock
UART receive / ACK interrupt re- Rising edge of the last bit of re- Rising edge of the last bit of re-
quest generation timing ceive clock ceive clock

3 to 6 cycles < set up time (Note)

3 to 6 cycles < hold time (Note)
Set up time Hold time

SCL
SDA
(Start condition)

SDA
(Stop condition)

Note : Cycle number shows main clock input oscillation frequency f(XIN) cycle number.

Figure 1.21.3. Start/stop condition detect timing characteristics

UARTi Special Mode Register 3 (UiSMR3:Addresses 036516, 02E516, 033516, 032516, 02F516)
Bit 1 is clock phase set bit (CKPH). When both the IIC mode select bit (bit 0 of UARTi special mode
select register) and the IIC mode select bit 2 (bit 0 of UiSMR2 register) are "1", functions changed by
these bits are shown in table 1.21.3 and figure 1.21.4.
Bits 5 to 7 are SDAi digital delay setting bits (DL0 to DL2). By setting these bits, it is possible to turn the
SDAi delay OFF or set the BRG count source delay to 2 to 8 cycles.

Table 1.21.3. Functions changed by clock phase set bits

Function CKPH = 0, IICM = 1, IICM2 = 1 CKPH = 1, IICM = 1, IICM2 = 1
SCL initial and last value Initial value = H, last value = L Initial value = L, last value = L
Transfer interrupt factor Rising edge of 9th bit Falling edge of 10th bit
Data transfer times from UART re- Falling edge of 9th bit Two times :falling edge of 9th bit
ceive shift register to receive buffer and rising edge of 9th bit
register

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UARTi Special Mode Register

• CKPH= "0" (IICM=1, IICM2=1)

SCL

SDA D7 D6 D5 D4 D3 D2 D1 D0 D8
(Internal clock, transfer data 9 bits long and MSB first selected.)
Receive interrupt Transmit interrupt

Transfer to receive buffer

• CKPH= "1" (IICM=1, IICM2=1)

SCL

SDA D7 D6 D5 D4 D3 D2 D1 D0 D8
(Internal clock, transfer data 9 bits long and MSB first selected.)
Receive interrupt Transmit interrupt

Transfer to receive buffer

Figure 1.21.4. Functions changed by clock phase set bits

UARTi Special Mode Register 4 (UiSMR4:Addresses 036416, 02E416, 033416, 032416, 02F416)
Bit 0 is the start condition generate bit (STAREQ). When the SCL, SDA output select bit (bit 3 of
UiSMR4 register) is "1" and this bit is "1", then the start condition is generated.

Bit 1 is the restart condition generate bit (RSTAREQ). When the SCL, SDA output select bit (bit 3 of
UiSMR4 register) is "1" and this bit is "1", then the restart condition is generated.

Bit 2 is the stop condition generate bit (STPREQ). When the SCL, SDA output select bit (bit 3 of
UiSMR4 register) is "1" and this bit is "1", then the stop condition is generated.

Bit 3 is SCL, SDA output select bit (STSPSEL). Functions changed by these bits are shown in table
1.21.4 and figure 1.21.5.

Table 1.21.4. Functions changed by SCL, SDA output select bit

Function STSPSEL = 0 STSPSEL = 1
SCL, SDA output Output of SI/O control circuit Output of start/stop condition
control circuit
Star/stop condition interrupt factor Start/stop condition detection Completion of start/stop condition
generation

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UARTi Special Mode Register

• When slave mode (CKDIR=0, STSPSEL=0)

SCL

SDA

Start condition detection Stop condition detection

interrupt interrupt

• When master mode (CKDIR=1, STSPSEL=1)

STSPSEL=0 STSPSEL=1 STSPSEL=0 STSPSEL=1 STSPSEL=0

SCL

SDA

STAREQ=1
STPREQ=1
Start condition detection Stop condition detection
interrupt interrupt

Figure 1.21.5 Functions changed by SCL, SDA output select bit

Bit 4 is ACK data bit (ACKD). When the SCL, SDA output select bit (bit 3 of UiSMR4 register) is "0"
and the ACK data output enable bit (bit 5 of UiSMR4 register) is "1", then the content of ACK data bit
is output to SDAi pin.

Bit 5 is ACK data output enable bit (ACKC). When the SCL, SDA output select bit (bit 3 of UiSMR4
register) is "0" and this bit is "1", then the content of ACK data bit is output to SDAi pin.

Bit 6 is SCL output stop bit (SCLHI). When this bit is "1", SCLi output is stopped at stop condition
detection. (Hi-impedance status).

Bit 7 is SCL wait output bit 3 (SWC9). When this bit is "1", SCLi output is fixed to "L" at falling edge of
10th bit of clock. When this bit is "0", SCLi output fixed to "L" is released.

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UARTi Special Mode Register

(2) Serial Interface Special Function

_____
UARTi can control communications on the serial bus using the SSi input pins (Figure 1.21.6). The master
outputting the transfer clock transfers data to the slave inputting the transfer clock. In this case, in order to
_____
prevent a data collision on the bus, the master floats the output pin of other slaves/masters using the SSi
input pins.
_____
SSi input pins function between the master and slave are as follows.

IC1 IC2
P13
P12

P93(SS3) P93(SS3)
P90(CLK3) P90(CLK3)
P91(RxD3) P91(STxD3)
P92(TxD3) P92(SRxD3)
M16C/80 (M) M16C/80 (S)

IC3

P93(SS3)
P90(CLK3)
P91(STxD3)
M :Master
S :Slave P92(SRxD3)
M16C/80 (S)

Figure 1.21.6. Serial bus communication control example using the SS input pins

< Slave Mode (STxDi and SRxDi are selected, DINC = 1) >
_____
When an H level signal is input to an SSi input pin, the STxDi and SRxDi pins both become high
_____
impedance, hence the clock input is ignored. When an "L" level signal is input to an SSi input pin, the
clock input becomes effective and serial communications are enabled.

< Master Mode (TxDi and RxDi are selected, DINC = 0) >
_____ _____
The SSi input pins are used with a multiple master system. When an SSi input pin is H level, transmis-
_____
sion has priority and serial communications are enabled. When an L signal is input to an SSi input pin,
another master exists, and the TxDi, RxDi and CLKi pins all become high impedance. Moreover, the
trouble error interrupt request bit becomes “1”. Communications do not stop even when a trouble error
is generated during communications. To stop communications, set bits 0, 1 and 2 of the UARTi trans-
mission-reception mode register (addresses 036816, 02E816, 033816, 032816 and 02F816) to “0”.

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UARTi Special Mode Register

Clock Phase Setting

With bit 1 of UARTi special mode register 3 (UiSMR3:addresses 036516, 02E516, 033516, 032516,
02F516) and bit 6 of UARTi transmission-reception control register 0 (addresses 036C16, 02EC16,
033C16, 032C16, 02FC16), four combinations of transfer clock phase and polarity can be selected.
Bit 6 of UARTi transmission-reception control register 0 sets transfer clock polarity, whereas bit 1 of
UiSMR3 register sets transfer clock phase.
Transfer clock phase and polarity must be the same between the master and slave involved in the
transfer.

< Master (Internal Clock) (DINC = 0) >

Figure 1.21.7 shows the transmission and reception timing.

< Slave (External Clock) (DINC = 1) >

_____
• With “0” for CKPH bit (bit 1 of UiSMR3 register), when an SSi input pin is H level, output data is high
_____
impedance. When an SSi input pin is L level, the serial transmission start condition is satisfied,
though output is indeterminate. After that, serial transmission is synchronized with the clock. Figure
1.21.8 shows the timing.
_____ _____
• With “1” for CKPH bit, when an SSi input pin is H level, output data is high impedance. When an SSi
input pin is L level, the first data is output. After that, serial transmission is synchronized with the
clock.Figure 1.21.9 shows the thing.

"H"
Master SS input
"L"

Clock output "H"

(CKPOL=0, CKPH=0) "L"

Clock output "H"

(CKPOL=1, CKPH=0) "L"

Clock output "H"

(CKPOL=0, CKPH=1) "L"

Clock output "H"

(CKPOL=1, CKPH=1) "L"

Data output timing "H"

D0 D1 D2 D3 D4 D5 D6 D7
"L"

Data input timing

Figure 1.21.7. The transmission and reception timing in master mode (internal clock)

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UARTi Special Mode Register

"H"
SS input
"L"

Clock input "H"

(CKPOL=0, CKPH=0) "L"

Clock input "H"

(CKPOL=1, CKPH=0) "L"

Data output timing "H"

D0 D1 D2 D3 D4 D5 D6 D7
(Note) "L" High- High-
inpedance inpedance

Data input timing Indeterminate

Note :UART2 output is an N-channel open drain and needs to be pulled-up externally.

Figure 1.21.8. The transmission and reception timing (CKPH=0) in slave mode (external clock)

"H"
SS input
"L"

Clock input "H"

(CKPOL=0, CKPH=0) "L"

Clock input "H"

(CKPOL=1, CKPH=0) "L"

Data output timing "H"

D0 D1 D2 D3 D4 D5 D6 D7
(Note) "L" High- High-
inpedance inpedance

Data input timing

Note :UART2 output is an N-channel open drain and needs to be pulled-up externally.

Figure 1.21.9. The transmission and reception timing (CKPH=1) in slave mode (external clock)

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CAN Module

CAN Module
The microcomputer incorporates Full-CAN modules compliant with CAN (Controller Area Network) 2.0B
specification.
These Full-CAN modules are outlined below.

Table 1.22.1 Outline of the CAN module

Item Description
Protocol Compliant with CAN 2.0B specification
Number of message slots 16 slots
Polarity 0: Dominant
1: Recessive
Acceptance filter Global mask: 1 mask (for message slots 0–13)
Local mask: 2 masks (for message slots 14 and 15 each)
Baud rate 1 time quantum (Tq) = (BRP + 1) / CPU clock (Note)
(BRP = baud rate prescaler set value)
Baud rate = 1 / (Tq period x number of Tq’s in one bit) ---Max. 1 Mbps
BRP: 1-255 (0: Inhibited)
Number of Tq’s in one bit = Synchronization Segment +
Propagation Time Segment +
Phase Buffer Segment 1 +
Phase Buffer Segment 2
Synchronization Segment : 1 Tq (fixed)
Propagation Time Segment : 1 to 8 Tq
Phase Buffer Segment 1 : 2 to 8 Tq
Phase Buffer Segment 2 : 2 to 8 Tq
Remote frame automatic The message slot that received a remote frame automatically transmits it.
answering function
Timestamp function This timestamp function is based on a 16-bit counter. A count period can
be derived from the CAN bus bit period (as the fundamental period) by
dividing it by 1, 2, 3, or 4.
BasicCAN mode The BasicCAN function is realized by using message slots 14 and 15.
Transmit abort function This function is used to cancel a transmit request.
Loopback function The data the CAN module itself transmitted is received.
Return from bus-off function Forcibly placed into an error active state from a bus-off state.
Note: Use a specification conforming resonator whose maximum permissible error of oscillation is not
greater than 1.58%

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CAN Module

Data bus

Sleep control Control register Global Error interrupt Error interrupt Acceptance
register mask register mask register Message status register
slot buffer 0 filter support
Slot interrupt register
Baud rate Configuration Local Slot interrupt status register
BCLK prescaler register mask register A mask register
Status
Expansion ID Local register
register mask register B
Slot buffer Transmit error
count register
Message slot 0 select register
control register Receive error
count register

Message
slot 0
Acceptance
Filter
CANOUT CAN protocol Message box
controller 16 bits timer (slot 0 to 15)
CANIN Time stamp
Ver 2.0B register
Interrupt
Interrupt request
control circuit

Figure 1.22.1 CAN module blobk diagram

CAN0 message slot buffer 0 and 1 can be selected by setting of slot buffer select register. Figure 1.22.2
shows the message slot buffer and 16 bytes of message slots. Figure 1.22.26 to 1.22.30 show related
registers.

CAN0 message slot buffer 0 (addresses 01E016 to 01EF16)

CAN0 message slot 0 to 15
CAN0 message slot buffer 1 (addresses 01F016 to 01FF16)

CAN0 message slot buffer 0 standard ID0 CAN0 message slot 0 standard ID0
CAN0 message slot buffer 0 standard ID1 CAN0 message slot 0 standard ID1
CAN0 message slot buffer 0 standard ID0
CAN0 message slot buffer 0 extend ID0 CAN0 CAN0
message slot 0 extend
message ID00 standard ID0
slot buffer
CAN0 message slot buffer 0 standard ID1
CAN0 message slot buffer 0 extend ID1 CAN0 CAN0
message slot 0 extend
message ID10 standard ID1
slot buffer
CAN0 message slot buffer 0 extended ID0
CAN0 message slot buffer 0 extend ID2 CAN0 CAN0
message slot 0 extend
message ID20 extended ID0
slot buffer
CAN0 message slot buffer 0 extended ID1
CAN0 message slot buffer 0 data length code CAN0 CAN0
message slot 0 data
message length0code
slot buffer extended ID1
CAN0 message slot buffer 0 extended ID2
CAN0 message slot buffer 0 data 0 CAN0 CAN0
message slot 0 data
message 0
slot buffer 0 extended ID2
CAN0 message slot buffer 0 data length code
CAN0 message slot buffer 0 data 1 CAN0 CAN0
message slot 0 data
message 1
slot buffer 0 data length code
CAN0 message slot buffer 0 data 0
CAN0 message slot buffer 0 data 2 CAN0 CAN0
message slot 0 data
message 2
slot buffer 0 data 0
CAN0 message slot buffer 0 data 1
CAN0 message slot buffer 0 data 3 CAN0 CAN0
message slot 0 data
message 3
slot buffer 0 data 1
CAN0 message slot buffer 0 data 2
CAN0 message slot buffer 0 data 4 CAN0 CAN0
message slot 0 data
message 4
slot buffer 0 data 2
CAN0 message slot buffer 0 data 3
CAN0 message slot buffer 0 data 5 CAN0 CAN0
message slot 0 data
message 5
slot buffer 0 data 3
CAN0 message slot buffer 0 data 4
CAN0 message slot buffer 0 data 6 CAN0 CAN0
message slot 0 data
message 6
slot buffer 0 data 4
CAN0 message slot buffer 0 data 5
CAN0 message slot buffer 0 data 7 CAN0 CAN0
message slot 0 data
message 7
slot buffer 0 data 5
CAN0 message slot buffer 0 data 6
CAN0 message slot buffer 0 time stamp high CAN0 CAN0
message slot 0 time
message stamp0high
slot buffer data 6
CAN0 message slot buffer 0 data 7
CAN0 message slot buffer 0 time stamp low CAN0 CAN0
message slot 0 time
message stamp0low
slot buffer data 7
CAN0 message slot buffer 0 time stamp high
CAN0 message slot buffer 1 time stamp low
CAN0 message slot 15 time stamp low

Figure 1.22.2. Message slot buffer and message slots

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CAN0 control register 0

b15 b8
(b7) (b0)b7 b0 Symbol Address When reset (Note 1)
0 C0CTLR0 020116, 020016 XXXX 0000 XX01 0X012

Bit
symbol Bit name Function R W
0: Reset released
Reset 0 CAN reset bit 0
1: Reset requested
Loop back mode 0: Loop back function disabled
Loopback
select bit 1: Loop back function enabled
Nothing is assigned. When write, set to "0".
When read, its contents is indeterminate.
Basic CAN mode 0 : Basic CAN mode function disabled
BasicCAN
select bit 1 : Basic CAN mode function enabled
0 : Reset released
Reset 1 CAN reset bit 1
1 : Reset requested

Reserved bit Must set to "0".

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

b9 b8
TSPre0 Time stamp 0 0: CAN bus bit clock is selected
prescaler select bit 0 1: Division by 2 of CAN bus bit clock is selected
1 0: Division by 3 of CAN bus bit clock is selected
TSPre1
1 1: Division by 4 of CAN bus bit clock is selected
Time stamp 0 : Count enabled
TSReset
counter reset bit 1 : Count reset (set 000016) (Note 2)
Error counter 0 : Normal operation mode
ECReset
reset bit 1 : Error counter reset (Note 2)

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note 1: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.
Note 2: Only writing 1 is accepted. The bit is automatically cleared to 0 in hardware.

Figure 1.22.3 CAN0 control register 0

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1. CAN0 control register 0

Bit 0: CAN reset bits 0 and 1 (Reset0 and Reset1)
If the Reset0 and Reset1 bits both are set from 1 to 0, CAN communication is enabled after detecting
11 consecutive recessive bits. The CAN Timestamp Register starts counting at the same time com-
munication is enabled.
In no case will the CAN be reset unless transmission of all messages are completed.
Note 1: Reset0 and Reset1 bits must both be cleared to "0" or set to "1" simutnously.
Note 2: Setting a new transmit request is inhibited before the CAN Status Register State_Reset bit is
set to 1 and the CAN module is reset after setting the Reset0 and Reset1 bits to 1.
Note 3: When the CAN module is reset by setting the Reset0 and Reset1 bits to 1, the CAN
Timestamp Register (C0TSR), CAN Transmit Error Counter (C0TEC), and CAN Receive
Error Counter (C0REC) are initialized to 0.
Note 4: If Reset0 and Reset1 bits sre set to "1" during communication, the CANOUT pin output goes
"H" immediately after that. Therefore, setting these bits to 1 while the CAN module is sending
a frame may cause a CAN bus error.
Note 5: To CAN communication, function select register A1 (PS1), function select register A2 (PS2),
function select register B1 (PSL1), function select register B2 (PSL2), function select register
C (PSC) and input function select register (IPS) must be set. These registers must be set
when CAN module is reset.

Bit 1: Loopback mode select bit (LoopBack)

Setting the LoopBack bit to 1 enables loopback mode, so that if any receive slot whose ID matches
that of a frame the CAN module itself transmitted exists, the frame is received.
Note 1: ACK is not returned for the transmit frame.
Note 2: Do not set or reset the LoopBack bit while the CAN module is operating (CAN Status Register
State_Reset bit = 0).

Bit 3: BasicCAN mode select bit (BasicCAN)

If this bit is set to 1, message slots 14 and 15 operate in BasicCAN mode.
• Operation during BasicCAN mode
In BasicCAN mode, message slots 14 and 15 are used with a dual-structured buffer. The received
frames whose IDs are found matching by acceptance filtering are stored in slots 14 and 15 alter-
nately. When slot 14 is active (i.e., the next received frame is to be stored in slot 14), this acceptance
filtering is accomplished using the ID that is set in slot 14 and local mask A; when slot 15 is active, it
is accomplished using the ID that is set in slot 15 and local mask B. Frame types of both data frame
and remote frame can be received.
When using BasicCAN mode, setting the IDs of two slots and the mask registers the same way helps
to reduce the possibility of causing an overrun error.
• Procedure for entering BasicCAN mode
Make the following settings during initialization.
(1) Set the BasicCAN bit to 1.
(2) Set the IDs of slots 14 and 15 and Local Mask Registers A and B. (We recommend setting the
same value)
(3) Set the frame format to be handled with slots 14 and 15 (standard or extended) in the CAN
Extended ID Register. (We recommend setting the same format)

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(4) Set the Message Slot Control Registers for slots 14 and 15 to receive data frames.
Note 1: Do not set or reset the BasicCAN bit while the CAN module is operating (CAN Status Regis-
ter State_Reset bit = 0).
Note 2: Slot 14 is the first slot to become active after clearing the Reset0 bit.
Note 3: Even during BasicCAN mode, slot 0 through slot 13 can be used in the same way as when
operating normally.

Bit 8, 9: Timestamp prescaler select bits (TSPre0, 1)

These bits select the count clock source for the timestamp counter.
Note 1: Do not set or reset these TSPre0, 1 bits while the CAN module is operating (CAN Status
Register State_Reset bit = 0).

Bit 10: Timestamp counter reset bit (TSReset)

Setting this bit to 1 clears the value of the CAN Timestamp Register (C0TSR) to 000016. This bit is
automatically cleared after the CAN Timestamp Register (C0TSR) has its value cleared to 000016.

Bit 11: Error counter reset bit (ECReset)

Setting this bit to 1 clears the Receive Error Counter Register (C0REC) and Transmit Error Counter
Register (C0TEC), with the CAN module forcibly placed in an error active state. This bit is automati-
cally cleared upon entering an error active state.
Note 1: When in an error active state, the CAN module becomes ready to communicate when it
detects 11 consecutive recessive bits on the CAN bus.

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CAN0 control register 1

b7 b0 Symbol Address When reset (Note)
0 0 0 C0CTLR1 024116 XX0000XX2

Bit
symbol Bit name Function R W

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Reserved bit Must set to "0".

0 : Message slot control register

BankSel CAN0 bank select bit selected
1 : Mask register selected

Reserved bit Must set to "0".

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.4. CAN0 control register 1

2. CAN0 control register 1

Bit 3: CAN0 bank select bit (BankSel)
This bit selects between registers allocated to the addresses 022016 through 023F16.
Setting the BankSel bit to 0 selects the CAN0 Message Slot Control Register. Setting the BankSel bit
to 1 selects the CAN0 Mask Register.

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CAN0 sleep control register

b7 b0 Symbol Address When reset
C0SLPR 024216 XXXXXXX02

Bit
symbol Bit name Function R W

0 : Sleep mode On
Sleep Sleep mode control bit (Note)
1 : Sleep mode Off

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: After CAN sleep mode is canceled, set up the CAN configuration. While the CAN module is in sleep
mode, no SFR registers for the CAN, except the sleep mode control register, can be accessed for
read or write.

Figure 1.22.5. CAN0 sleep control register

3. CAN0 sleep control register

Bit 0: Sleep mode control bit (Sleep)
The CAN module isn't supplied with a clock by setting the Sleep bit to 0, and is shifted to sleep mode.
The CAN module is supplied with a clock by setting the Sleep bit to 1, and is released from sleep
mode.
Note: Sleep mode can be shifted to only after CAN is reset (State_Reset bit = 1).

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CAN0 status register

b15 b8
(b7) (b0)b7 b0 Symbol Address When reset (Note)
C0STR 020316,020216 X000 0X01 0000 00002

Bit R W
symbol Bit name Function
b3 b2 b1 b0
MBox0
0 0
0 0 : Slot 0
0 0
1 0 : Slot 1
MBox1 0 0
1 1 : Slot 2
Active slot 0 1
0 0 : Slot 3
determination bit • •
MBox2 • •
1 1 0 1 : Slot 13
1 1 1 0 : Slot 14
MBox3 1 1 1 1 : Slot 15

Transmission-finished 0: Transmission not finished

TrmSucc
status 1: Transmission finished
Reception-finished 0: Reception not finished
RecSucc
status 1: Reception finished
0: Not transmitting
TrmState Transmission status
1: Transmitting
0: Not receiving
RecState Reception status
1: Receiving

0: Operating
State_Reset CAN reset status
1: Reset
0: Normal mode
State_LoopBack Loop back status
1: Loop back mode
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
0: Normal mode
State_BasicCAN Basic CAN status
1: Basic CAN mode
0: No error occurred
State_BusError CAN bus error
1: Error occurred
0: Not error passive state
State_ErrPas Error passive status
1: Error passive state
0: Not bus-off state
State_BusOff Bus-off status
1: Bus-off state
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.6. CAN0 status register

4. CAN0 status register

Bits 0–3: Active slot determination bits (MBox)
When the CAN module finished transmitting data or finished storing received data, the relevant slot
number is stored in these bits.
The MBox bits cannot be cleared to 0 in software.

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Bit 4: Transmission-finished status (TrmSucc)

[Set condition]
This bit is set to 1 when the CAN module finished transmitting data normally.
[Clear condition]
This bit is cleared when the CAN module finished receiving data normally.

Bit 5: Reception-finished status (RecSucc)

[Set condition]
This bit is set to 1 when the CAN module finished receiving data normally (regardless of whether the
received message has been stored in a message slot). However, this bit is not set if the received
message is one that was transmitted in loopback mode.
[Clear condition]
This bit is cleared when the CAN module finished transmitting data normally.

Bit 6: Transmission status (TrmState)

[Set condition]
This bit is set to 1 when the CAN module is operating as a transmit node.
[Clear condition]
This bit is cleared when the CAN module goes to a bus-idle state or starts operating as a receive
node.

Bit 7: Reception status (RecState)

[Set condition]
This bit is set to 1 when the CAN module is operating as a receive node.
[Clear condition]
This bit is cleared when the CAN module goes to a bus-idle state or starts operating as a transmit
node.

Bit 8: CAN reset status (State_Reset)

When the State_Reset bit = 1, it means that the CAN module is in a reset state.
[Set condition]
This bit is set to 1 when CAN module is in a reset state.
[Clear condition]
This bit is cleared by clearing the Reset0 or Reset1 bits to 0.

Bit 9: Loopback status (State_loopBack)

When the State_loopBack bit = 1, it means that the CAN module is operating in loopback mode.
[Set condition]
This bit is set to 1 by setting the CAN control register LoopBack bit to 1.
[Clear condition]
This bit is cleared by clearing the LoopBack bit to 0.

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Bit 11: BasicCAN status (State_BasicCAN)

When the State_BasicCAN bit = 1, it means that the CAN module is operating in BasicCAN mode.
[Set condition]
This bit is set to 1 when the CAN module is operating in BasicCAN mode.
Conditions for the CAN module to operate in BasicCAN mode are as follows:
• The CAN Control Register BasicCAN bit is set to 1.
• Slots 14 and 15 both are set for data frame reception.
[Clear condition]
This bit is cleared by clearing the BasicCAN bit to 0.

Bit 12: CAN bus error (State_BusError)

[Set condition]
This bit is set to 1 when an error on the CAN bus is detected.
[Clear condition]
This bit is cleared when the CAN module finished transmitting or receiving normally. Clearing of this
bit does not depend on whether the received message has been stored in a message slot.
Note :When this bit is 1, although CAN module is reset, this bit does not become to 0.

Bit 13: Error passive status (State_ErrPas)

When the State_ErrPas bit = 1, it means that the CAN module is in an error-passive state.
[Set condition]
This bit is set to 1 when the value of C0TEC register or C0REC register exceeds 127, with the CAN
module in an error-passive state.
[Clear condition]
This bit is cleared when the CAN module goes from the error-passive state to any other error state.
Note :When this bit is 1, then CAN module is reset, this bit becomes 0 automatically.

Bit 14: Bus-off status (State_BusOff)

When the State_BusOff bit = 1, it means that the CAN module is in a bus-off state.
[Set condition]
This bit is set to 1 when the value of the C0TEC register exceeds 255, with the CAN module in a bus-
off state.
[Clear condition]
This bit is cleared when the CAN module returns from the bus-off state.

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CAN0 extended ID register

b15 b8
(b7) (b0)b7 b0 Symbol Address When reset (Note)
C0IDR 020516,020416 000016

Bit R W
symbol Bit name Function
0: Standard ID format
IDE15 Expansion ID15 (slot 15)
1: Extended ID format
0: Standard ID format
IDE14 Expansion ID14 (slot 14)
1: Extended ID format
0: Standard ID format
IDE13 Expansion ID13 (slot 13)
1: Extended ID format
0: Standard ID format
IDE12 Expansion ID12 (slot 12)
1: Extended ID format
0: Standard ID format
IDE11 Expansion ID11 (slot 11)
1: Extended ID format
0: Standard ID format
IDE10 Expansion ID10 (slot 10)
1: Extended ID format
0: Standard ID format
IDE9 Expansion ID9 (slot 9)
1: Extended ID format
0: Standard ID format
IDE8 Expansion ID8 (slot 8)
1: Extended ID format
0: Standard ID format
IDE7 Expansion ID7 (slot 7)
1: Extended ID format
0: Standard ID format
IDE6 Expansion ID6 (slot 6)
1: Extended ID format
0: Standard ID format
IDE5 Expansion ID5 (slot 5)
1: Extended ID format
0: Standard ID format
IDE4 Expansion ID4 (slot 4)
1: Extended ID format
0: Standard ID format
IDE3 Expansion ID3 (slot 3)
1: Extended ID format
0: Standard ID format
IDE2 Expansion ID2 (slot 2)
1: Extended ID format
0: Standard ID format
IDE1 Expansion ID1 (slot 1)
1: Extended ID format
0: Standard ID format
IDE0 Expansion ID0 (slot 0)
1: Extended ID format

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.7. CAN0 extended ID register

5. CAN0 extended ID register

This register selects the format of a frame handled by the message slot that corresponds to each bit
in this register.
Setting any bit to 0 selects the standard (Standard ID) format.
Setting any bit to 1 selects the extended (Extended ID) format.
Note 1: When setting or resetting any bit in this register, make sure the corresponding slot has no
transmit or receive request.

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CAN0 configuration register

b15 b8
(b7) (b0)b7 b0 Symbol Address When reset (Note)
0 C0CONR 020716,020616 000X16

Bit
symbol Bit name Function R W

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

0: Sampled once
SAM Sampling number
1: Sampled three times
b7 b6 b5
PTS0 0 0 0: Propagation Time Segment = 1Tq
0 0 1: Propagation Time Segment = 2Tq
Propagation Time 0 1 0: Propagation Time Segment = 3Tq
PTS1 0 1 1: Propagation Time Segment = 4Tq
Segment 1 0 0: Propagation Time Segment = 5Tq
1 0 1: Propagation Time Segment = 6Tq
PTS2 1 1 0: Propagation Time Segment = 7Tq
1 1 1: Propagation Time Segment = 8Tq
b10 b9 b8
PBS10 0 0 0: Must not be set
0 0 1: Phase Buffer Segment 1 = 2Tq
Phase Buffer 0 1 0: Phase Buffer Segment 1 = 3Tq
PBS11 0 1 1: Phase Buffer Segment 1 = 4Tq
Segment 1 1 0 0: Phase Buffer Segment 1 = 5Tq
1 0 1: Phase Buffer Segment 1 = 6Tq
PBS12 1 1 0: Phase Buffer Segment 1 = 7Tq
1 1 1: Phase Buffer Segment 1 = 8Tq
b13 b12 b11
PBS20 0 0 0: Must not be set
0 0 1: Phase Buffer Segment 2 = 2Tq
Phase Buffer 0 1 0: Phase Buffer Segment 2 = 3Tq
PBS21 0 1 1: Phase Buffer Segment 2 = 4Tq
Segment 2 1 0 0: Phase Buffer Segment 2 = 5Tq
1 0 1: Phase Buffer Segment 2 = 6Tq
PBS22 1 1 0: Phase Buffer Segment 2 = 7Tq
1 1 1: Phase Buffer Segment 2 = 8Tq
b15 b14
SJW0
reSynchronization 0 0: SJW = 1Tq
0 1: SJW = 2Tq
Jump Width 1 0: SJW = 3Tq
SJW1 1 1: SJW = 4Tq

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.8. CAN0 configuration register

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6. CAN0 configuration register

Bit 4: SAM bit (SAM)
This bit sets the sampling number per one bit.
0: The value sampled at the last of the Phase Buffer Segment 1 becomes the bit value.
1: The bit value is determined by the majority operation circuit using values sampled at the following
three points: the last of the Phase Buffer Segment 1, before 1Tq, and before 2Tq.

Bits 5–7: PTS bits (RTS00-RTS02)

These bits set the width of Propagation Time Segment.

Bits 8–10: PBS1 bits (PBS10-PBS12)

These bits set the width of Phase Buffer Segment 1. The PBS1 bits must be set to 1 or greater.

Bits 11–13: PBS2 bits (PBS20-PBS22)

These bits set the width of Phase Buffer Segment 2. The PBS2 bits must be set to 1 or greater.

Bits 14, 15: SJW bits (SJW0, SJW1)

These bits set the width of reSynchronization Jump Width. The SJW bits must be set to a value equal
to or less than PBS2.

Table 1.22.2 Bit Timing Setup Example when the CPU Clock = 30 MHz
Baud rate BRP Tq period (ns) 1 bit's Tq number PTS+PBS1 PBS2 Sample point
1Mbps 1 66.7 15 12 2 87%
1 66.7 15 11 3 80%
1 66.7 15 10 4 73%
2 100 10 7 2 80%
2 100 10 6 3 70%
2 100 10 5 4 60%
500Kbps 2 100 20 16 3 85%
2 100 20 15 4 80%
2 100 20 14 5 75%
3 133.3 15 12 2 87%
3 133.3 15 11 3 80%
3 133.3 15 10 4 73%
4 166.7 12 9 2 83%
4 166.7 12 8 3 75%
4 166.7 12 7 4 67%
5 200 10 7 2 80%
5 200 10 6 3 70%
5 200 10 5 4 60%

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CAN0 time stamp register

b15 b8
(b7) (b0)b7 b0 Symbol Address When reset (Note)
(Upper 8-bit) (Lower 8-bit) C0TSR 020916,020816 000016

Function Setting range R W

16 bits count value 000016 to FFFF16

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.9. CAN0 time stamp register

7. CAN0 Timestamp register

The CAN module incorporates a 16-bit counter. The count period for this counter can be derived
from the CAN bus bit period by dividing it by 1, 2, 3, or 4 using the CAN0 control register0
(C0CTLR0)’s TSPre0, 1 bits.
When the CAN module finishes transmitting or receiving, the CAN0 Timestamp Register (C0TSR)
value is captured and the value is automatically stored in a message slot.
The C0TSR register starts counting upon clearing the C0CTLR register’s Reset and Reset1 bits to 0.
Note 1: Setting the C0CTLR0 register’s Reset0 and Reset1 bits to 1 resets CAN, and the C0TSR
register thereby initialized to 000016. Also, setting the TSReset (timestamp counter reset) bit
to 1 initializes the C0TSR register to 000016 on-the-fly (while the CAN remains operating;
CAN0 status register's State_Reset bit is "0").
Note 2: During loopback mode, if any receive slot exists in which a message can be stored, the
C0TSR register value is stored in the corresponding slot when the CAN module finished
receiving. (This storing of the C0TSR register value does not occur at completion of trans-
mission.)

CAN0 transmit error count register

b7 b0 Symbol Address When reset (Note)
8-bit C0TEC 020A16 0016

Function R W

Transmit error count value

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.10. CAN0 transmit error count register

8. CAN0 transmit error count register

When in an error active or an error passive state, the transmit error count value is stored in this
register. The count is decremented when the CAN module finished transmitting normally or
incremented when an error occurred while transmitting.
When in a bus-off state, an indeterminate value is stored in this register. The register is reset to 0016
upon returning to an error active state.

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CAN0 reception error count register

b7 b0 Symbol Address When reset (Note)
8-bit C0REC 020B16 0016

Function R W

Reception error count value

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.11. CAN0 reception error count register

9. CAN0 reception error count register

When in an error active or an error passive state, the receive error count value is stored in this
register. The count is decremented when the CAN module finished receiving normally or incremented
when an error occurred while receiving.
When C0REC > 128 (error passive state) at the time the CAN module finished receiving normally, the
C0REC register is set to 127.
When in a bus-off state, an indeterminate value is stored in this register. The register is reset to 0016
upon returning to an error active state.

CAN0 baud rate prescaler

b7 b0 Symbol Address When reset (Note 1)
8-bit C0BRP 021716 0116

Function Setting range R W

Baud rate prescaler value selected 0116 to FF16

(Note 2)
Note 1: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.
Note 2: Do not set to "0016" (division by 1).

Figure 1.22.12. CAN0 baud rate register

10. CAN0 baud rate prescaler

This register is used to set the Tq period, the CAN bit time. The CAN baud rate is determined by (Tq
period x number of Tq’s in one bit).

Tq period = (C0BRP+1)/CPU clock

CAN baud rate = 1 / (Tq period x number of Tq’s in one bit)
Number of Tq’s in one bit = Synchronization Segment +
Propagation Time Segment +
Phase Buffer Segment 1 +
Phase Buffer Segment 2

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CAN0 slot interrupt status register

b15 b8
(b7) (b0)b7 b0 Symbol Address When reset (Note 1)
C0SISTR 020D16,020C16 000016

Bit R W
symbol Bit name Function
Slot 15 interrupt 0: Interrupt not requested
SIS15 (Note 2)
request status bit 1: Interrupt requested
Slot 14 interrupt 0: Interrupt not requested
SIS14 (Note 2)
request status bit 1: Interrupt requested
Slot 13 interrupt 0: Interrupt not requested
SIS13 (Note 2)
request status bit 1: Interrupt requested
Slot 12 interrupt 0: Interrupt not requested
SIS12 (Note 2)
request status bit 1: Interrupt requested
Slot 11 interrupt 0: Interrupt not requested
SIS11 (Note 2)
request status bit 1: Interrupt requested
Slot 10 interrupt 0: Interrupt not requested
SIS10 (Note 2)
request status bit 1: Interrupt requested
Slot 9 interrupt 0: Interrupt not requested
SIS9 (Note 2)
request status bit 1: Interrupt requested
Slot 8 interrupt 0: Interrupt not requested
SIS8 (Note 2)
request status bit 1: Interrupt requested

Slot 7 interrupt 0: Interrupt not requested

SIS7 (Note 2)
request status bit 1: Interrupt requested
Slot 6 interrupt 0: Interrupt not requested
SIS6 (Note 2)
request status bit 1: Interrupt requested
Slot 5 interrupt 0: Interrupt not requested
SIS5 (Note 2)
request status bit 1: Interrupt requested
Slot 4 interrupt 0: Interrupt not requested
SIS4 (Note 2)
request status bit 1: Interrupt requested
Slot 3 interrupt 0: Interrupt not requested
SIS3 (Note 2)
request status bit 1: Interrupt requested
Slot 2 interrupt 0: Interrupt not requested
SIS2 (Note 2)
request status bit 1: Interrupt requested
Slot 1 interrupt 0: Interrupt not requested
SIS1 (Note 2)
request status bit 1: Interrupt requested
Slot 0 interrupt 0: Interrupt not requested
SIS0 (Note 2)
request status bit 1: Interrupt requested

Note 1: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.
Note 2: "0" can be set. When set to "1", the previous value is remained.

Figure 1.22.13. CAN slot interrupt status register

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9. CAN0 slot interrupt status register

When using CAN interrupts, the CAN0 Slot Interrupt Status Register helps to know which slot requested
an interrupt.
• For transmit slots
The status is set to 1 when the CAN module finished storing the CAN Timestamp Register value in
the message slot after completing transmission.
To clear this bit, write 0 in software (Note 1).

• For receive slots

The status is set to 1 when the CAN module finished storing the received message in the message
slot after completing reception.
To clear this bit, write 0 in software (Note 1).

Note 1: To clear any bit of the CAN Interrupt Status Register, write 0 to the bit to be cleared and 1 to
all other bits, without using bit clear instructions.
Example : Assembler language mov.w #07FFFh, C0SISTR
C language c0sister = 0x7FFF;
Note 2: For remote frame receive slots whose automatic answering function is enabled, the slot
interrupt status bit is set when the CAN module finished receiving a remote frame and when
it finished transmitting a data frame.
Note 3: For remote frame transmit slots, the slot interrupt status bit is set when the CAN module
finished transmitting a remote frame and when it finished receiving a data frame.
Note 4: If the slot interrupt status bit is set by an interrupt request at the same time it is cleared by
writing in software, the former has priority, i.e., the slot interrupt status bit is set.

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CAN0 slot interrupt mask register

b15 b8
(b7) (b0)b7 b0 Symbol Address When reset (Note)
C0SIMKR 021116,021016 000016

Bit R W
symbol Bit name Function
Slot 15 interrupt 0: Interrupt request masked (disabled)
SIM15
request mask bit 1: Interrupt request enabled
Slot 14 interrupt 0: Interrupt request masked (disabled)
SIM14
request mask bit 1: Interrupt request enabled
Slot 13 interrupt 0: Interrupt request masked (disabled)
SIM13
request mask bit 1: Interrupt request enabled
Slot 12 interrupt 0: Interrupt request masked (disabled)
SIM12
request mask bit 1: Interrupt request enabled
Slot 11 interrupt 0: Interrupt request masked (disabled)
SIM11
request mask bit 1: Interrupt request enabled
Slot 10 interrupt 0: Interrupt request masked (disabled)
SIM10
request mask bit 1: Interrupt request enabled
Slot 9 interrupt 0: Interrupt request masked (disabled)
SIM9
request mask bit 1: Interrupt request enabled
Slot 8 interrupt 0: Interrupt request masked (disabled)
SIM8
request mask bit 1: Interrupt request enabled

Slot 7 interrupt 0: Interrupt request masked (disabled)

SIM7
request mask bit 1: Interrupt request enabled
Slot 6 interrupt 0: Interrupt request masked (disabled)
SIM6
request mask bit 1: Interrupt request enabled
Slot 5 interrupt 0: Interrupt request masked (disabled)
SIM5
request mask bit 1: Interrupt request enabled
Slot 4 interrupt 0: Interrupt request masked (disabled)
SIM4
request mask bit 1: Interrupt request enabled
Slot 3 interrupt 0: Interrupt request masked (disabled)
SIM3
request mask bit 1: Interrupt request enabled
Slot 2 interrupt 0: Interrupt request masked (disabled)
SIM2
request mask bit 1: Interrupt request enabled
Slot 1 interrupt 0: Interrupt request masked (disabled)
SIM1
request mask bit 1: Interrupt request enabled
Slot 0 interrupt 0: Interrupt request masked (disabled)
SIM0
request mask bit 1: Interrupt request enabled

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.14. CAN0 slot interrupt mask register

12. CAN0 slot interrupt mask register

This register controls CAN interrupts by enabling or disabling interrupt requests generated by each
corresponding slot at completion of transmission or reception. Setting any bit of this register (SIMn
where n = 0–15) to 1 enables the interrupt request to be generated by the corresponding slot at
completion of transmission or reception.

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CAN0 error interrupt mask register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset (Note)
C0EIMKR 021416 XXXX X0002

Bit
symbol Bit name Function R W

Bus off interrupt 0: Interrupt request masked (disabled)

BOIM
mask bit 1: Interrupt request enabled

Error passive interrupt 0: Interrupt request masked (disabled)

EPIM
mask bit 1: Interrupt request enabled

CAN bus error interrupt 0: Interrupt request masked (disabled)

BEIM
mask bit 1: Interrupt request enabled

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.15. CAN0 error interrupt mask register

13. CAN0 error interrupt mask register

Bit 0: Bus-off interrupt mask bit (BOIM)
This bit controls CAN interrupts by enabling or disabling interrupt requests generated when the CAN
module goes to a bus-off state. Setting this bit to 1 enables a bus-off interrupt request.

Bit 1: Error passive interrupt mask bit (EPIM)

This bit controls CAN interrupts by enabling or disabling interrupt requests generated when the CAN
module goes to an error passive state. Setting this bit to 1 enables an error passive interrupt request.

Bit 2: CAN bus error interrupt mask bit (BEIM)

This bit controls CAN interrupts by enabling or disabling interrupt requests generated by occurrence
of a CAN bus error. Setting this bit to 1 enables a CAN bus error interrupt request.

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CAN0 error interrupt status register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset (Note 1)
C0EISTR 021516 XXXX X0002

Bit
symbol Bit name Function R W

Bus off interrupt 0: Interrupt not requested

BOIS (Note 2)
status bit 1: Interrupt requested

Error passive interrupt 0: Interrupt not requested

EPIS (Note 2)
status bit 1: Interrupt requested

CAN bus error interrupt 0: Interrupt not requested

BEIS (Note 2)
status bit 1: Interrupt requested

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note 1: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.
Note 2: "0" can be set. When set to "1", the previous value is remained.

Figure 1.22.16. CAN0 error interrupt status register

14. CAN0 error interrupt status register

When using CAN interrupts, the CAN Error Interrupt Status Register helps to verify the causes of
error-derived interrupts.
Bit 0: Bus-off interrupt status bit (BOIS)
This bit is set to 1 when the CAN module goes to a bus-off state.
To clear this bit, write 0 in software (Note 1).

Bit 1: Error passive interrupt status bit (EPIS)

This bit is set to 1 when the CAN module goes to an error passive state.
To clear this bit, write 0 in software (Note 1).

Bit 2: CAN bus error interrupt status bit (BEIS)

This bit is set to 1 when a CAN communication error is detected.
To clear this bit, write 0 in software (Note 1).

Note 1: To clear any bit of the CAN Error Interrupt Status Register, write 0 to the bit to be cleared and
1 to all other bits, without using bit clear instructions.
Example: Assembler language mov.B #006h, C0EISTR
C language c0eistr = 0x06;

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C0SISTR
C0SIMKR
Slot 15 transmit/receive finished
Data bus 19-source inputs
SIS15
b0 F/F
CAN0 transmit/ receive
SIM15 (Level) error interrupt
b0 F/F

Slot 14 transmit/receive finished

SIS14
b1 F/F
SIM14
b1 F/F

Slot 13 transmit/receive finished

SIS13
b2 F/F
SIM13
b2
F/F

Slot 12 transmit/receive finished

SIS12
b3 F/F
SIM12
b3 F/F

Slot 11 transmit/receive finished

SIS11
b4
F/F
SIM11
b4 F/F

Slot 10 transmit/receive finished

SIS10
b5 F/F
SIM10
b5 F/F

Slot 9 transmit/receive finished

SIS9
b6 F/F
SIM9
b6 F/F

Slot 8 transmit/receive finished

SIS8
b7 F/F
SIM8
b7
F/F

To 11 other input sources on the next page

Figure 1.22.17. CAN0 transmit, receive and error interrupt block diagram (1/3)

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C0SISTR
C0SIMKR
Slot 7 transmit/receive finished

Data bus SIS7 19-source inputs

b8 F/F
To previous page
SIM7 (Level)
b8 F/F

Slot 6 transmit/receive finished

SIS6
b9 F/F
SIM6
b9 F/F

Slot 5 transmit/receive finished

SIS5
b10 F/F
SIM5
b10
F/F

Slot 4 transmit/receive finished

SIS4
b11 F/F
SIM4
b11 F/F

Slot 3 transmit/receive finished

SIS3
b12
F/F
SIM3
b12 F/F

Slot 2 transmit/receive finished

SIS2
b13 F/F
SIM2
b13 F/F

Slot 1 transmit/receive finished

SIS1
b14 F/F
SIM1
b14 F/F

Slot 0 transmit/receive finished

SIS0
b15 F/F
SIM0
b15
F/F

To 3 other input sources on the next page

Figure 1.22.18. CAN0 transmit, receive and error interrupt block diagram (2/3)

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C0EISTR
C0EIMKR
CAN bus error occur
Data bus 19-source inputs
BEIS
b2 F/F
To the previous page
BEIM (Level)
b2 F/F

Shift to error passive state

EPIS
b1 F/F
EPIM
b1 F/F

Shift to bus off state

BOIS
b0 F/F
BOIM
b0
F/F

Figure 1.22.19. CAN0 transmit, receive and error interrupt block diagram (3/3)

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CAN0 global mask register standard ID0

CAN0 local mask register A, B standard ID0
b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset (Note)
C0GMR0 022816 XXX0 00002
C0LMAR0 023016 XXX0 00002
C0LMBR0 023816 XXX0 00002

Bit
symbol Bit name Function R W

0: ID not checked
SID6M Standard ID6
1: ID checked

0: ID not checked
SID7M Standard ID7
1: ID checked

0: ID not checked
SID8M Standard ID8
1: ID checked

0: ID not checked
SID9M Standard ID9
1: ID checked

0: ID not checked
SID10M Standard ID10
1: ID checked

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.20. CAN0 global mask register standard ID0 and CAN0 local mask register A, B standard ID0

15. CAN0 global mask register standard ID0

CAN0 local mask register A, B standard ID0
The mask registers used for acceptance filtering consist of the global mask register, local mask
register A, and local mask register B.
The global mask register takes care of message slots 0–13 whereas local mask registers A and B are
used for message slots 14 and 15, respectively.
• If any bit of this register is set to 0, its corresponding ID bit is masked during acceptance filtering.
(The masked bit is not checked for ID; the ID is assumed to be matching.)
• If any bit of this register is set to 1, its corresponding ID bit is compared with the received ID during
acceptance filtering. If it matches the ID that is set in any message slot, the received data is stored
in that slot.
Note 1: The global mask register can only be modified when none of the slots 0–13 has receive
requests set.
Note 2: The local mask register A can only be modified when slot 14 has no receive requests set.
Note 3: The local mask register B can only be modified when slot 15 has no receive requests set.

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CAN0 global mask register standard ID1

CAN0 local mask register A, B standard ID1
b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset (Note)
C0GMR1 022916 XX00 00002
C0LMAR1 023116 XX00 00002
C0LMBR1 023916 XX00 00002

Bit
symbol Bit name Function R W

0: ID not checked
SID0M Standard ID0
1: ID checked

0: ID not checked
SID1M Standard ID1
1: ID checked

0: ID not checked
SID2M Standard ID2
1: ID checked

0: ID not checked
SID3M Standard ID3
1: ID checked

0: ID not checked
SID4M Standard ID4
1: ID checked

0: ID not checked
SID5M Standard ID5
1: ID checked

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.21. CAN0 global mask register standard ID1 and CAN0 local mask register A, B standard ID1

16. CAN0 global mask register standard ID1

CAN0 local mask register A, B standard ID1
The mask registers used for acceptance filtering consist of the global mask register, local mask
register A, and local mask register B.
The global mask register takes care of message slots 0–13 whereas local mask registers A and B are
used for message slots 14 and 15, respectively.
• If any bit of this register is set to 0, its corresponding ID bit is masked during acceptance filtering.
(The masked bit is not checked for ID; the ID is assumed to be matching.)
• If any bit of this register is set to 1, its corresponding ID bit is compared with the received ID during
acceptance filtering. If it matches the ID that is set in any message slot, the received data is stored
in that slot.
Note 1: The global mask register can only be modified when none of the slots 0–13 has receive
requests set.
Note 2: The local mask register A can only be modified when slot 14 has no receive requests set.
Note 3: The local mask register B can only be modified when slot 15 has no receive requests set.

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CAN0 global mask register extend ID0

CAN0 local mask register A, B extend ID0
b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset (Note)
C0GMR2 022A16 XXXX 00002
C0LMAR2 023216 XXXX 00002
C0LMBR2 023A16 XXXX 00002

Bit R W
symbol Bit name Function

0: ID not checked
EID14M Extend ID14
1: ID checked

0: ID not checked
EID15M Extend ID15
1: ID checked

0: ID not checked
EID16M Extend ID16
1: ID checked

0: ID not checked
EID17M Extend ID17
1: ID checked

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.22. CAN0 global mask register extend ID0 and CAN0 local mask register A, B extend ID0

17. CAN0 global mask register extend ID0

CAN0 local mask register A, B extend ID0
The mask registers used for acceptance filtering consist of the global mask register, local mask
register A, and local mask register B.
The global mask register takes care of message slots 0–13 whereas local mask registers A and B are
used for message slots 14 and 15, respectively.
• If any bit of this register is set to 0, its corresponding ID bit is masked during acceptance filtering.
(The masked bit is not checked for ID; the ID is assumed to be matching.)
• If any bit of this register is set to 1, its corresponding ID bit is compared with the received ID during
acceptance filtering. If it matches the ID that is set in any message slot, the received data is stored
in that slot.
Note 1: The global mask register can only be modified when none of the slots 0–13 has receive
requests set.
Note 2: The local mask register A can only be modified when slot 14 has no receive requests set.
Note 3: The local mask register B can only be modified when slot 15 has no receive requests set.

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CAN0 global mask register extend ID1

CAN0 local mask register A, B extend ID1
b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset (Note)
C0GMR3 022B16 0016
C0LMAR3 023316 0016
C0LMBR3 023B16 0016

Bit
symbol Bit name Function R W

0: ID not checked
EID6M Extend ID6
1: ID checked

0: ID not checked
EID7M Extend ID7
1: ID checked

0: ID not checked
EID8M Extend ID8
1: ID checked

0: ID not checked
EID9M Extend ID9
1: ID checked

0: ID not checked
EID10M Extend ID10
1: ID checked

0: ID not checked
EID11M Extend ID11
1: ID checked

0: ID not checked
EID12M Extend ID12
1: ID checked

0: ID not checked
EID13M Extend ID13
1: ID checked

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.23. CAN0 global mask register extend ID1 and CAN0 local mask register A, B extend ID1

18. CAN0 global mask register extend ID1

CAN0 local mask register A, B extend ID1
The mask registers used for acceptance filtering consist of the global mask register, local mask
register A, and local mask register B.
The global mask register takes care of message slots 0–13, whereas local mask registers A and B
are used for message slots 14 and 15, respectively.
• If any bit of this register is set to 0, its corresponding ID bit is masked during acceptance filtering.
(The masked bit is not checked for ID; the ID is assumed to be matching.)
• If any bit of this register is set to 1, its corresponding ID bit is compared with the received ID during
acceptance filtering. If it matches the ID that is set in any message slot, the received data is stored
in that slot.
Note 1: The global mask register can only be modified when none of the slots 0–13 has receive
requests set.
Note 2: The local mask register A can only be modified when slot 14 has no receive requests set.
Note 3: The local mask register B can only be modified when slot 15 has no receive requests set.

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CAN0 global mask register extend ID2

CAN0 local mask register A, B extend ID2
b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset (Note)
C0GMR4 022C16 XX00 00002
C0LMAR4 023416 XX00 00002
C0LMBR4 023C16 XX00 00002

Bit
symbol Bit name Function R W

0: ID not checked
EID0M Extend ID0
1: ID checked

0: ID not checked
EID1M Extend ID1
1: ID checked

0: ID not checked
EID2M Extend ID2
1: ID checked

0: ID not checked
EID3M Extend ID3
1: ID checked

0: ID not checked
EID4M Extend ID4
1: ID checked

0: ID not checked
EID5M Extend ID5
1: ID checked

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.24. CAN0 global mask register extend ID2 and CAN0 local mask register A, B extend ID2

19. CAN0 global mask register extend ID2

CAN0 local mask register A, B extend ID2
The mask registers used for acceptance filtering consist of the global mask register, local mask
register A, and local mask register B.
The global mask register takes care of message slots 0–13, whereas local mask registers A and B
are used for message slots 14 and 15, respectively.
• If any bit of this register is set to 0, its corresponding ID bit is masked during acceptance filtering.
(The masked bit is not checked for ID; the ID is assumed to be matching.)
• If any bit of this register is set to 1, its corresponding ID bit is compared with the received ID during
acceptance filtering. If it matches the ID that is set in any message slot, the received data is stored
in that slot.
Note 1: The global mask register can only be modified when none of the slots 0–13 has receive
requests set.
Note 2: The local mask register A can only be modified when slot 14 has no receive requests set.
Note 3: The local mask register B can only be modified when slot 15 has no receive requests set.

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CAN0 message slot i control register (i=0 to 15)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset (Note 1)
C0MCTLi(i=0 to 5) 023016, 023116, 023216, 023316, 023416, 023516 0016
C0MCTLi(i=6 to 11) 023616, 023716, 023816, 023916, 023A16, 023B16 0016
C0MCTLi(i=12 to 15) 023C16, 023D16, 023E16, 023F16 0016

Bit
symbol Bit name Function R W
When receive, When transmitting When receiving (Note 2)
NewData Transmit/receive
0: Not transmitted yet 0: Not received yet
When transmit, finished flag
SentData 1: Finished transmitting 1: Finished receiving
When receive, When transmitting When receiving
InvalData Transmitting/
0: Stopped transmitting 0: Stopped receiving
When transmit, receiving flag 1: Accepted transmit request 1: Storing received data
TrmActive
0: Over run error not occurred
MsgLost Overwrite flag (Note 2)
1: Over run error occurred
Using BasicCan mode
Remote flame 0: Data flame received (status) (Note 2)
1: Remote flame received (status)
RemActive transmit/receive
Not using BasicCan mode
status flag 0: Data flame
1: Remote flame
Automatic answering 0: Automatic answering of remote flame enable
RspLock
disable bit 1: Automatic answering of remote flame disable

Remote frame 0: Transmit/receive data flame

Remote
set bit 1: Transmit/receive remote flame

Receive 0: Reception not requested

RecReq
request bit 1: Reception requested

Transmit 0: Transmission not requested

TrmReq
request bit 1: Transmission requested
Note 1: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.
Note 2: "0" can be set. When set to "1", the previous value is remained.

Figure 1.22.25. CAN0 message slot i control register

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20. CAN0 message slot i control register

Bit 0: Transmission finished flag /reception finished flag (SentData, NewData)
This bit indicates that the CAN module finished transmitting or receiving a message.
• For transmit slots
The bit is set to 1 when the CAN module finished transmitting from the message slot.
This bit is cleared by writing 0 in software. However, it cannot be cleared when the TrmActive
(transmit/receive status) bit = 1.
• For receive slots
The bit is set to 1 when the CAN module finished receiving a message normally that is to be stored
in the message slot.
This bit is cleared by writing 0 in software. However, it cannot be cleared when the InvalData (trans-
mit/receive status) bit = 1.

Note 1: Before reading received data from the message slot, be sure to clear the NewData (transmis-
sion/reception finished status) bit. Also, if the NewData bit is set to 1 after readout, it means
that new received data has been stored in the message slot while reading out from the slot,
and that the read data contains an indeterminate value. In this case, discard the read data
and clear the NewData bit before reading out from the slot again.
Note 2: The NewData bit is not set by a completion of remote frame transmission or reception.

Bit 1: Transmitting flag /receiving flag (TrmActive, InvalData)

This bit indicates that the CAN module is transmitting or receiving a message, with the message slot
being accessed. The bit is set to 1 when the CAN module is accessing the message slot and set to 0
when not accessing the message slot.
• For transmit slots
This bit is set to 1 when the message slot has its transmit request accepted. If the message slot
failed in arbitration, this bit is cleared to 0 by occurrence of a CAN bus error or completion of trans-
mission.
• For receive slots
This bit is set to 1 when the CAN module is receiving a message, with the received message being
stored in the message slot. Note that the value read out from the message slot while this bit remains
set is indeterminate.

Bit 2: Overwrite flag (MsgLost)

This bit is useful for the receive slots, those that are set for reception. This bit is set to 1 when while
the message slot contains an unread received message, it is overwritten by a new received mes-
sage.
This bit is cleared by writing 0 in software.

Bit 3: Remote frame transmit/receive status flag (RemActive)

This bit functions differently for slots 0–13 and slots 14, 15.
• For slots 0–13
If the slot is set for remote frame transmission (or reception), this bit is set to 1. Then, when the slot
finished transmitting (or receiving) a remote frame, this bit is cleared to 0.

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• For slots 14 and 15

The RemActive bit functions differently depending on how the CAN Control Register’s BasicCAN
(BasicCAN mode) bit is set.
When BasicCAN = 0 (operating normally), if the slot is set for remote frame transmission (or recep-
tion), the RemActive bit is set to 1.
When BasicCAN = 1 (operating in BasicCAN mode), the RemActive bit indicates which frame type
of message was received. During BasicCAN mode, slots 14 and 15 store the received data whether
it be a data frame or a remote frame.
If RemActive = 0, it means that the message stored in the slot is a data frame.
If RemActive = 1, it means that the message stored in the slot is a remote frame.

Bit 4: Automatic answering disable bit (RspLock)

This bit is useful for the slots set for remote frame reception, indicating the processing to be per-
formed after receiving a remote frame.
If this bit is set to 0, the slot automatically changes to a transmit slot after receiving a remote frame
and the message stored in the slot is transmitted as a data frame.
If this bit is set to 1, the slot stops operating after receiving a remote frame.
Note 1: This bit must always be set to 0 for any slots other than those set for remote frame reception.

Bit 5: Remote frame set bit (Remote)

Set this bit to 1 for the message slots that handle a remote frame.
Message slots can be set to handle a remote frame in the following two ways.
• Set to transmit a remote frame and receive a data frame
The message stored in the message slot is transmitted as a remote frame. The slot automatically
changes to a data frame receive slot after it finished transmitting.
However, if it receives a data frame before it finishes transmitting a remote frame, the data frame is
stored in the message slot and the remote frame is not transmitted.
• Set to receive a remote frame and transmit a data frame
The slot receives a remote frame. The processing to be performed after receiving a remote frame
depends on how the RspLock (automatic answering disable) bit is set.

Bit 6: Receive request bit (RecReq)

Set this bit to 1 when using any message slot as a receive slot.
Set this bit to 0 when using any message slot as a data frame transmit or remote frame transmit slot.
If the TrmReq (transmit request) bit and RecReq (receive request) bit both are set to 1, the operation
of the CAN module is indeterminate.

Bit 7: Transmit request bit (TrmReq)

Set this bit to 1 when using any message slot as a transmit slot.
Set this bit to 0 when using any message slot as a data frame receive or remote frame receive slot.

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CAN0 slot buffer select register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset (Note 2)
C0SBS 024016 0016

Bit
symbol Bit name Function R W
b3 b2 b1 b0
SBS00 0 0 0 0: slot 0
0 0 1 0: slot 1
0 0 1 1: slot 2
SBS01 CAN0 message 0 1 0 0: slot 3
slot buffer 0 • • (Note 1)
• •
number select bit • •
SBS02 1 1 0 0: slot 12
1 1 0 1: slot 13
1 1 1 0: slot 14
SBS03
1 1 1 1: slot 15
b3 b2 b1 b0
SBS10 0 0 0 0: slot 0
0 0 1 0: slot 1
0 0 1 1: slot 2
SBS11 CAN0 message 0 1 0 0: slot 3
slot buffer 1 • • (Note 1)
• •
number select bit • •
SBS12
1 1 0 0: slot 12
1 1 0 1: slot 13
SBS13 1 1 1 0: slot 14
1 1 1 1: slot 15
Note 1: There is a total of 16 CAN0 message slots for transmission and reception uses, respectively.
Each message slot can be selected for use as a transmit or a receive slot.
Note 2: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.

Figure 1.22.26. CAN0 slot buffer select register

21. CAN0 slot buffer select register

Bits 0-3: CAN0 message slot buffer 0 slot number select bits (SBS0)
The message slot whose number is selected with these bits appears in CAN0 message slot buffer 0.

Bits 4-7: CAN0 message slot buffer 1 slot number select bits (SBS1)
The message slot whose number is selected with these bits appears in CAN0 message slot buffer 1.

The selected message slot can be identified by reading the message slot buffer.
A message written to the message slot buffer is stored in the selected message slot.

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CAN0 message slot buffer i standard ID0 (i=0,1) (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
C0SLOTi_0(i=0,1) 01E016, 01F016 Indeterminate

Bit
symbol Bit name Function R W

SID6 Standard ID6 Message slot j (j=0 to 15)

SID7 Standard ID7 Message slot j (j=0 to 15)

SID8 Standard ID8 Message slot j (j=0 to 15)

SID9 Standard ID9 Message slot j (j=0 to 15)

SID10 Standard ID10 Message slot j (j=0 to 15)

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: CAN0 message slot j standard ID0 (j=0 to 15) is stored in this register. j is selected with the slot
buffer select register.

CAN0 message slot buffer i standard ID1(i=0,1) (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
C0SLOTi_1(i=0,1) 01E116, 01F116 Indeterminate

Bit
symbol Bit name Function R W

SID0 Standard ID0 Message slot j (j=0 to 15)

SID1 Standard ID1 Message slot j (j=0 to 15)

SID2 Standard ID2 Message slot j (j=0 to 15)

SID3 Standard ID3 Message slot j (j=0 to 15)

SID4 Standard ID4 Message slot j (j=0 to 15)

SID5 Standard ID5 Message slot j (j=0 to 15)

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: CAN0 message slot j standard ID1 (j=0 to 15) is stored in this register. j is selected with the slot
buffer select register.

Figure 1.22.27. CAN0 message slot buffer i standard ID0 and ID1

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CAN0 message slot buffer i extend ID0 (i=0,1) (Note 1, 2)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
C0SLOTi_2(i=0,1) 01E216, 01F216 Indeterminate

Bit
symbol Bit name Function R W

EID14 Extended ID14 Message slot j (j=0 to 15)

EID15 Extended ID15 Message slot j (j=0 to 15)

EID16 Extended ID16 Message slot j (j=0 to 15)

EID17 Extended ID17 Message slot j (j=0 to 15)

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note 1: When receive slot is standard ID format, EID bits are indeterminate when saving received data.
Note 2: CAN0 message slot j extend ID0 (j=0 to 15) is stored in this register. j is selected with the slot
buffer select register.

CAN0 message slot buffer i extend ID1 (i=0,1) (Note 1,2)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
C0SLOTi_3(i=0,1) 01E316, 01F316 Indeterminate

Bit
symbol Bit name Function R W

EID6 Extended ID6 Message slot j (j=0 to 15)

EID7 Extended ID7 Message slot j (j=0 to 15)

EID8 Extended ID8 Message slot j (j=0 to 15)

EID9 Extended ID9 Message slot j (j=0 to 15)

EID10 Extended ID10 Message slot j (j=0 to 15)

EID11 Extended ID11 Message slot j (j=0 to 15)

EID12 Extended ID12 Message slot j (j=0 to 15)

EID13 Extended ID13 Message slot j (j=0 to 15)

Note 1: When receive slot is standard ID format, EID bits are indeterminate when saving received data.
Note 2: CAN0 message slot j extend ID1 (j=0 to 15) is stored in this register. j is selected with the slot
buffer select register.

Figure 1.22.28. CAN0 message slot buffer i extended ID0 and ID1

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CAN0 message slot buffer i extend ID2 (i=0,1) (Note 1,2)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
C0SLOTi_4(i=0,1) 01E416, 01F416 Indeterminate

Bit
symbol Bit name Function R W

EID0 Extended ID0 Message slot j (j=0 to 15)

EID1 Extended ID1 Message slot j (j=0 to 15)

EID2 Extended ID2 Message slot j (j=0 to 15)

EID3 Extended ID3 Message slot j (j=0 to 15)

EID4 Extended ID4 Message slot j (j=0 to 15)

EID5 Extended ID5 Message slot j (j=0 to 15)

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note 1: When receive slot is standard ID format, EID bits are indeterminate when saving received data.
Note 2: CAN0 message slot j extend ID2 (j=0 to 15) is stored in this register. j is selected with the slot
buffer select register.

CAN0 message slot buffer i data length code (i=0,1)(Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
C0SLOTi_5(i=0,1) 01E516, 01F516 Indeterminate

Bit
symbol Bit name Function R W

DLC0

DLC1
Data length set bit Message slot j (j=0 to 15)
DLC2

DLC3

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note : CAN0 message slot j data length code (j=0 to 15) is stored in this register. j is selected with the
slot buffer select register.

Figure 1.22.29. CAN0 message slot buffer i extended ID2 and CAN0 message slot buffer i data lengthcode

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CAN0 message slot buffer i data m (i=0,1 m=0 to 7) (Note)

b7 b0 Symbol Address When reset

C0SLOT0_n(n=m+6,m=0 to 3) 01E616, 01E716, 01E816, 01E916 Indeterminate
C0SLOT0_n(n=m+6,m=4 to 7) 01EA16, 01EB16, 01EC16, 01ED16 Indeterminate
C0SLOT1_n(n=m+6,m=0 to 3) 01F616, 01F716, 01F816, 01F916 Indeterminate
C0SLOT1_n(n=m+6,m=4 to 7) 01FA16, 01FB16, 01FC16, 01FD16 Indeterminate

Function Setting range R W

Message slot j data m (j=0 to 15, m=0 to 7) 0016 to FF16

Note: j is selected with the slot buffer select register

CAN0 message slot buffer i time stamp high (i=0,1) (Note)

b7 b0 Symbol Address When reset
C0SLOTi_14(i=0,1) 01EE16, 01FE16 Indeterminate

Function Setting range R W

Message slot j time stamp high (j=0 to 15) 0016 to FF16

Note : CAN0 message slot j time stamp high (j=0 to 15) is stored in this register. j is selected with the
slot buffer select register.

CAN0 message slot buffer i time stamp low (i=0,1) (Note)

b7 b0 Symbol Address When reset
C0SLOTi_15(i=0,1) 01EF16, 01FF16 Indeterminate

Function Setting range R W

Message slot j time stamp low (j=0 to 15) 0016 to FF16

Note : CAN0 message slot j time stamp low (j=0 to 15) is stored in this register. j is selected with the
slot buffer select register.

Figure 1.22.30. CAN0 message slot buffer i data m and CAN0 message slot buffer i time stamp

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CAN0 acceptance filter support register

b15 b8 b7 b0 Symbol Address When reset (Note)
C0AFS 024516,024416 010016

Function Setting range R W

Produces receive ID determination data 000016 to FFFF16

Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.
b15 b0
Write SID5 SID4 SID3 SID2 SID1 SID0 SID10 SID9 SID8 SID7 SID6

3-8 decode
b15 b8 b7 b0
Read CSID7 CSID6 CSID5 CSID4 CSID3 CSID2 CSID1 CSID0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3

b7 b6 b5 b4 b3 b2 b1 b0
From the receive ID of the standard for- 00716 00616 00516 00416 00316 00216 00116 00016
Top+0016
"0" "0" "0" "0" "0" "0" "1" "0"
mat, this register produces data with 00F16 00E16 00D16 00C16 00B16 00A16 00916 00816
Top+0116
which to search the data table. After "1" "0" "0" "0" "0" "0" "0" "0"

searching the table using this data, the

CAN module determines whether the 6F716 6F616 6F516 6F416 6F316 6F216 6F116 6F016
Top+DE16
"0" "0" "0" "0" "1" "0" "0" "0"
receive ID is valid or not.

7F716 7F616 7F516 7F416 7F316 7F216 7F116 7F016

Top+FE16
"0" "0" "0" "0" "0" "0" "0" "1"
7FF16 7FE16 7FD16 7FC16 7FB16 7FA16 7F916 7F816
Top+FF16
"0" "0" "1" "0" "0" "0" "0" "0"

Address search information Bit search information

When receive ID is "6F316" b15 b8 b7 b0

SID5 SID4 SID3 SID2 SID1 SID0 SID10SID9 SID8 SID7 SID6

Write to C0AFS 0 0 1 1 0 0 1 1 0 0 0 1 1 0 1 1

SID10 SID0

Receive ID "6" "F" "3"

1 1 0 1 1 1 1 0 0 1 1
Divide to 8 bits and 3 bits "D" "E" "3"

8 bits 3 bits

b15 b8 b7 b0

0 0 0 0 1 0 0 0 1 1 0 1 1 1 1 0 Because the value of

these three bits is 3,
Read from C0AFS "0816" "D" "E" bit 3 in the table below
Bit search information Address search information is 1. (If the value of
these three bits is 4,
bit 4 in the table below
Bit search information b7 b3 b0 Low-order 3 bits of receive ID is 1.)
0116 0 0 0 0 0 0 0 1 016
0216 0 0 0 0 0 0 1 0 116
0416 0 0 0 0 0 1 0 0 216
0816 0 0 0 0 1 0 0 0 316
1016 0 0 0 1 0 0 0 0 416
2016 0 0 1 0 0 0 0 0 516
4016 0 1 0 0 0 0 0 0 616
8016 1 0 0 0 0 0 0 0 716

Figure 1.22.31. CAN0 acceptance filter support register

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Intelligent I/O

Intelligent I/O
Intelligent I/O uses multifunctional I/O ports for time measurement, waveform generation, clock-synchro-
nous/asynchronous (UART) serial I/O, IE bus (Note) communications, HDLC data processing and more. A
single Intelligent I/O group comes with one 16-bit base timer for free running, eight 16-bit registers for time
measurement and waveform generation, and two shift registers for 8-bit and 16-bit communications.
The M32C/83 has four internal Intelligent I/O groups. Table 1.23.1 lists functions by group.

Table 1.23.1. List of functions of intelligent I/O

Function Group 0 Group 1 Group 2 Group 3 Group 0,1
cascaded
Configuration
•Base timer 1 1 1 1 1
•TM 4ch(2ch) – – – –
•TM/WG register (shared) 4chs(1ch) 4chs(2chs) – – 8chs(3chs)
•WG register – 4chs(1ch) 8chs 8chs(3chs) 8chs(2chs)
•Communication shift register 8bits X 2chs 8bits X 2chs 8bits X 2chs – –
Time measurement functions Max. 8chs Max. 4chs – – Max. 8chs
(3chs) (2chs) (3chs)
•Digital filter function √ √ – – √
•Trigger input prescale function 2chs 2chs – – 2chs
•Gate function for trigger input 2chs 2chs – – 2chs
WG function Max. 4chs Max. 8chs Max. 8chs Max. 8chs Max. 8chs
(1ch) (3chs) (3chs) (2chs) (1ch)
•Single phase waveform output √ √ √ √ √
•Phase delayed waveform output √ √ √ √ √
•Set/reset waveform output √ √ √ √ √
•Bit modulation PWM output – – √ √ –
•Real-time port output – – √ √ –
•Parallel real-time port output – – √ √ –

Communication functions
•Bit length 8 bits fixed 8 bits fixed Variable length – –
•Communication mode
1. Clock synchronous serial I/O √ √ √ – –
2. UART √ √ – – –
3. HDLC data processing √ √ – – –
4. IE Bus sub set – – √ – –
Note 1: IE Bus is a trademark of NEC.
Note 2: 100-pin specification are in parentheses.
√ : Present
– : Not present
TM:Time Measurement
WG:Waveform Genaration

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Block diagrams for groups 0 to 3 are given in Figures 1.23.1 to 1.23.4.

Start bit Reset request from

BT0S communication block
BTS Reset
Gr1 base timer reset

2 x (n+1) 16-bit
f1 Divider Base timer
Base timer carry output

Digital Edge Ch0 TM/WG OUTC00/

INPC00 IST x D0
filter DF select register
PWM
output
INPC01 Digital Edge Ch1 TM/WG OUTC01/
/ISCLK0 filter DF select register ISCLK0

INPC02 Digital Edge

Ch2 TM register
/ISRxD0 filter DF select
PWM
output
Digital Edge
INPC03 filter select
Ch3 TM register
DF

Digital Edge Ch4 TM/WG

INPC04 filter select register OUTC04
DF
PWM
output (Note 1)
Digital Edge Ch5 TM/WG
INPC05 OUTC05
(Note 1) filter DF select register

Digital Edge Gate Prescale

INPC06 filter select function function Ch6 TM register
DF GT PR

Digital Edge Gate Prescale

INPC07 filter select function function Ch7 TM register
DF GT PR
8 Ch0 to ch7
/ interrupt request signal
TM input to Gr1
(When cascaded)
WG input to Gr1
(When cascaded)

Transmit interrupt
SI/O transmit Transmit data
buffer register SOF generation circuit Transmission
(8-bit) generation circuit

Transmit
buffer Bit insert circuit
Transmit
Transmit CRC
register
Transmit latch
Polarity
reversing
Start bit
Clock wait generation circuit
control Transmit output
Clock
circuit register
selector Parity bit (8-bit)
generation circuit
Transmit HDLC data
Stop bit shift register
transmit interrupt
generation circuit
Transmit
buffer

Clock
Arbitration Reception
selector
Receive Receive data
Receive input register CRC generation circuit
(8bit)
SI/O receive
Receive buffer register
buffer (8bit)
Bit insert
Polarity
check Receive Receive interrupt
Receive shit reversing buffer
register Start bit
Data register check Receive shift
(8-bit) register
Shift Parity bit
register check
Stop bit
Buffer check
register Special Special
HDLC data interrupt communication
process interrupt
4 check interrupt
/

Comparison Comparator
register
Comparison 4 Comparator
(8-bit) 4
(8-bit)
register
Comparison / Comparator
(8-bit) /
Comparison
(8-bit)
register (8-bit)
Comparator
register
(8-bit)
(8-bit) (8-bit) TM: Time Measurement
WG: Waveform Generation

Note 1: These pins aren't connected with external pins in 100-pin version.
Note 2: Each register becomes reset status after supplying a clock by setting of the base timer control register 0.

Figure 1. 23. 1. Block diagram of intelligent I/O group 0

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Start bit Reset request from

BT1S communication block
Reset
BTS Base timer carry input Gr0 base timer reset

2 x (n+1) 16bits
f1 Divider Base timer
WG input from Gr0
(When cascaded)
Ch0 TM/WG OUTC10
TM input from Gr0 register (Note) /IST x D1
(When cascaded) PWM /BE1OUT
output
Digital Edge Ch1 TM/WG OUTC11
INPC11 /ISCLK1
filter DF select register

INPC12 Digital Edge Ch2 TM/WG

OUTC12
filter DF select register
PWM
output
Ch3 TM/WG
OUTC13
register

Ch4 TM/WG
OUTC14
register
PWM
output
Ch5 TM/WG
OUTC15 (Note 2)
register

Digital Edge Gate Prescale Ch6 TM/WG OUTC16

INPC16 filter DF select function GT function PR register
(Note 2) PWM
output
Digital Edge Gate Prescale Ch7 TM/WG OUTC17
INPC17 select
filter DF function GT function PR register

8 Ch0 to ch7
/ interrupt request signal

Transmit interrupt

SI/O transmit Transmit data

SOF generation circuit Transmission
buffer register generation circuit
(8-bit)
Transmit
buffer Bit insert circuit
Transmit
CRC
Transmit
register
Transmit latch
Polarity
reversing
Start bit
Clock wait generation circuit
Clock control
Transmit output
selector circuit
register (8-bit)
Parity bit
generation circuit Transmit shift HDLC data
register transmit interrupt
Stop bit
generation circuit
Transmit
buffer

Arbitration Reception
Clock
selector Receive Receive data
Receive input register CRC
(8bit) generation circuit
SI/O receive
Receive buffer register
buffer (8bit)
Bit insert
Polarity check Receive
buffer Receive interrupt
Receive shit reversing
register Start bit
Data register check Receive shift
(8-bit) register
Shift Parity bit
register check
Stop bit
Buffer check
register Special Special
HDLC data interrupt communication
process interrupt check interrupt
4
/

Comparison
register
Comparison
Comparator
(8-bit)
register
Comparison 4 Comparator
(8-bit) 4
Comparison / Comparator
(8-bit) /
(8-bit)
register Comparator
register
(8-bit)
(8-bit)
(8-bit) (8-bit)

Note 1: Ch0 TM register can be used in 32-bit cascade connections. TM: Time Measurement
Note 2: These pins aren't connected with external pins in 100-pin version. WG: Waveform Generation
Note 3: Each register becomes reset status after supplying a clock by setting of the base timer control register 0.

Figure 1. 23. 2. Block diagram of intelligent I/O group 1

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Reset request from communication block

BT2S Reset Gr1 base timer reset
BTS

2 x (n+1) 16-bit ch0 interrupt request signal

f1 Divider Base timer
Real time port
output value

Bit modulation
ch0 WG register PWM
OUTC20
PWM /ISTxD2
IPS6 output
ISCLK20 0 0 control
Digital Bit modulation
ISCLK21
1 filter 1
ch1 WG register PWM
OUTC21
/ISCLK2
DF
ISRxD20 00 0
Digital Bit modulation
ISRxD21
01 filter 1
ch2 WG register PWM
OUTC22
PWM
ISRxD22 10 DF
output
IPS4,5 control
Bit modulation
ch3 WG register PWM
OUTC23

Bit modulation
ch4 WG register PWM
OUTC24
PWM
output
control
Bit modulation
ch5 WG register PWM
OUTC25
(Note 1)

Bit modulation
ch6 WG register PWM
OUTC26
PWM
output
control
Bit modulation
ch7 WG register PWM
OUTC27

8 Waveform
generation
interrupt
Transmit buffer
register(8-bit)
8

Clock Bit Transmit Output control

selector counter register (8-bit) function

Transmit parity Transmit Output

operation latch inverted

Byte counter
Arbitration
lost detect
ACK operation
Start bit
IE start bit interrupt
detect
IE transmit interrupt
Receive parity IE, serial I/O IE receive interrupt
interrupt control Serial I/O transmit interrupt
operation Serial I/O receive interrupt
Input
inverted

Receive shift Receive buffer

register (8-bit) register (8-bit)

Statement
ID detect
length detect

ALL "F" detect

Address detect WG: Waveform Generation

Note 1: These pins aren't connected with external pins in 100-pin version.
Note 2: Each register becomes reset status after supplying a clock by setting of the base timer control register 0.

Figure 1. 23. 3. Block diagram of intelligent I/O group 2

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BT3S Reset Gr2 base timer reset

BTS

2 x (n+1) 16-bit ch0 interrupt request signal

f1 Divider Base timer
Real time port
output value

Bit modulation
ch0 WG register PWM
OUTC30
PWM
output
control
Bit modulation
ch1 WG register PWM
OUTC31

Bit modulation
ch2 WG register PWM
OUTC32
PWM
output
control
Bit modulation
ch3 WG register PWM
OUTC33

Bit modulation
ch4 WG register PWM
OUTC34
PWM
ch4 mask register output
control
Bit modulation
ch5 WG register PWM
OUTC35
(Note 1)
ch5 mask register

Bit modulation
ch6 WG register PWM
OUTC36
PWM
ch6 mask register output
control
Bit modulation
ch7 WG register PWM
OUTC37

ch7 mask register 8

Waveform
generation
interrupt

Note 1: These pins aren’t connected with external pins in 100-pin version. WG: Waveform Generation
Note 2: Each register becomes reset status after supplying a clock by setting of the base timer control register 0.

Figure 1. 23 . 4. Block diagram of intelligent I/O group 3

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Base timer (group 0 to 3)

The internally generated count source is a free run source. Base timer specifications are given in Table
1.23.2, base timer registers in Figures 1.23.5 to 1.23.9 and a block diagram in Figure 1.23.10.

Group i base timer register (i=0 to 3)

b15 b8
(b7) (b0) b7 b0 Symbol Address When reset
GiBT (i=0,1) 00E116, 00E016, 012116, 012016 Indeterminate
GiBT (i=2,3) 016116, 016016, 01A116, 01A016 Indeterminate

Function Setting range R W

Count value of the 16-bit base timer (Note) 000016 to FFFF16

Note : When this register is read while the base timer is being reset, the value is indeterminate.
The counter value is read if the register is output while the timer is running.
Written value while the base timer is being reset is ignored. The count starts from "000016" after
starting the base timer. When writing value while the base timer is operating, the count starts from
the written value immediately after written.

Group i base timer control register 0 (i=0 to 3) (Note)

b7 b0 Symbol Address When reset
GiBCR0 (i=0 to 3) 00E216, 012216, 016216, 01A216 0016

Bit
symbol Bit name Function R W
b1 b0
BCK0 0 0 : Clock stop
Count source
0 1 : Must not be set
select bit
1 0 : Must not be set
BCK1 1 1 : f1

Divides the count source by 2x(n + 1)

DIV0 for a setting value n (n = 0 to 31).

b6 b5 b4 b3 b2
DIV1 (n=0) 0 0 0 0 0 : Division by 2
(n=1) 0 0 0 0 1 : Division by 4
(n=2) 0 0 0 1 0 : Division by 6
Count source
DIV2 :
division ratio (n=30) 1 1 1 1 0 : Division by 62
select bit (n=31) 1 1 1 1 1 : No division
DIV3

DIV4

Base timer 0 : Bit 15 overflow

IT interrupt select bit 1 : Bit 14 overflow

Note: In cascade connections, set the same value to the base timer control register 0 of groups 0 and 1.

Figure 1. 23. 5. Base timer-related register (1)

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Group i base timer control register 1 (i=0,1)

b7 b0 Symbol Address When reset
0 GiBCR1 (i=0,1) 00E316, 012316 0016

Bit
symbol Bit name Function R W
0: Synchronizes the base timer reset
Base timer reset without resetting the timer
RST0 1: Synchronizes the base timer reset
cause select bit 0
with resetting the timer (Note1)
0: Does not reset the base timer when
Base timer reset it matches WG register ch0
RST1 1: Reset the base timer when it matches
cause select bit 1
WG register ch0 (Note 2)
0: Does not reset the base timer when
Base timer reset input to the INT pin is "L" level
RST2 1: Reset the base timer when input to
cause select bit 2
the INT pin is "L" level (Note 3)

Reserved bit Must always set to "0".

Base timer 0: Base timer reset

BTS
start bit 1: Base timer count start
b6 b5
UD0 0 0 : Up mode
Up / down 0 1 : Up / down mode (triangle wave)
control bit 1 0 : Two-phase pulse signal processing
UD1 mode (Note 4)
1 1 : Must not be set
Groups 0 and 1 0: 16-bit TM / WG function
CAS cascaded function 1: 32-bit TM / WG function (Note 5)
select bit

Note 1: With group 0, reset synchronizing with group 1 base timer. With group 1, reset synchronizing with
group 0 base timer.
Note 2: The base timer is reset 2 clock cycles after it matches waveform generation register ch0.
Note 3: With group 0, the base timer is reset when "L" level is input to INT0. With group 1, it resets when
"L" level is input to INT1.
Note 4:Operation of this mode is equal to Timer A two-phase pulse signal processing except count value.
Note 5: In cascade connections, set to "8116" for group 0 base timer control register 1. Set to "1000 0XX02"
for group 1 base timer control register 1.

Figure 1. 23. 6. Base timer-related register (2)

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Group 2 base timer control register 1

b7 b0 Symbol Address When reset
0 0 0 G2BCR1 016316 0016

Bit
symbol Bit name Function R W
0 : Synchronizes the group 1 base timer reset
Base timer
reset cause without resetting the timer
RST0
select bit 0 1 : Synchronizes the group 1 base timer reset
with resetting the timer
Base timer 0 : Does not reset the base timer when it matches WG
RST1 reset cause register ch0
select bit 1 1 : Reset the base timer when it matches WG register ch0 (Note)

Base timer 0 : Does not reset the base timer when a reset is requested
reset cause from the communication additional circuit
RST2
select bit 2 1 : Reset the base timer when a reset is requested from
the communication additional circuit

RST3 Reserve bit Must always set to "0".

Base timer 0 : Base timer reset

BTS
start bit 1 : Base timer count start

UD0
Reserve bit Must always set to "0".
UD1

Parallel real-time 0 : Not use

PRP port function
select bit 1 : Use

Note : The base timer is reset 2 clock cycles after it matches waveform generation register ch0.

Figure 1. 23. 7. Base timer-related register (3)

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Group 3 base timer control register 1

b7 b0 Symbol Address When reset
0 G3BCR1 01A316 0XX0 X0002

Bit
symbol Bit name Function R W
0 : Synchronizes the base timer 2 reset
Base timer
reset cause without resetting the timer
RST0
select bit 0 1 : Synchronizes the base timer 2 reset
with resetting the timer
Base timer 0 : Does not reset the base timer when it matches WG
RST1 reset cause register ch0
select bit 1 1 : Reset the base timer when it matches WG register ch0 (Note)

Reserved bit Must always set to "0".

Nothing is assigned. When write, set to "0".

When read, the content is indeterminate.

Base timer 0 : Base timer reset

BTS
start bit 1 : Base timer count start

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Parallel real-time
port function 0 : Not use
PRP
select bit 1 : Use

WG: Waveform Generation

Note : The base timer is reset 2 clock cycles after it matches waveform generation register ch0.

Figure 1. 23. 8. Base timer-related register (4)

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Base timer start register (Note 1, 2)

b7 b0 Symbol Address When reset
BSTR 016416 XXXX 00002

Bit
symbol Bit name Function R W

Group 0 base timer 0 : Base timer reset

BT0S start bit 1 : Base timer count start

Group 1 base timer 0 : Base timer reset

BT1S start bit 1 : Base timer count start

Group 2 base timer 0 : Base timer reset

BT2S start bit (Note 2) 1 : Base timer count start

Group 3 base timer 0 : Base timer reset

BT3S start bit 1 : Base timer count start

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.

Note 1: When starting multiple base timer with this register at the same time (including group 0 and 1
cascaded connection), do the followings. Do not need when starting base timer individually.
* Set the same values to each group’s base timer clock division ratio ( bits 6 to 0 of base timer
control register).
* When changing base timer clock division ratio, start base timer twice with the following
procedure.
(1) Start each group base timer using the base timer start register.
(2) After one clock, stop base timer by setting "0016" to base timer start register.
(3) Further after one clock, restart each group base timer using the base timer start register.
Note 2: This register is enabled after when group 2 base timer control register 0 is set.

Figure 1. 23. 9. Base timer-related register (5)

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Table 1. 23.2. Base timer specifications

Item Specifications
Count source f1/2(n+1)
n: Set by count source division ratio select bit
(n=0 to 31, however, please note when n=31, the counter source is not divided.)

Count operation Up count / down count

Count start condition Writes "1" for the start bit in the base timer start register or base timer control
register 1. (After writing the bit, the base timer resets to "000016" and
counting starts.)

Count stop condition Writes "0" for both the start bit in the base timer start register and base timer
control register 1.
Count reset condition Group 0, 1 (1) Synchronizes and resets the base timer with that of another group.
Group 0: Synchronizes base timer reset with the group 1 base timer.
Group 1: Synchronizes base timer reset with the group 0 base timer.
(2) Matches the value of the base timer to the value of WG register 0.
(3) Input "L" to INT pin
Group 0 : INT 0 pin Group 1 : INT 1 pin
The above 3 factors can be used in conjunction with one another.
Group 2, 3 (1) Synchronizes and resets the base timer with that of another group.
Group 2: Synchronizes base timer reset with the group 1 base timer.
Group 3: Synchronizes base timer reset with the group 2 base timer.
(2) Matches the value of the base timer to the value of WG register 0.
(3) Reset request from communication additional circuit (group 2 only)

The above 3 factors can be used in conjunction with one another.

Interrupt request generation timing When bit 14 or bit 15 overflows

Read from timer •When the base timer is running
The count is output when the base timer is read.
•When the base timer not running
An undefined value is output when the base timer is read.
Write to timer Possible. Values that are written while the base timer is resetting are
ignored. If values are written while the base timer is running, counting
continues after the values are written.

Count source
switching select bit

f1 2(n+1) divider Base timer i b14 b15

Interrupt timing
select bit
BT0S Base timer i
Reset signal interrupt request
BTS
Overflow signal
RST0
Other base timer reset
RST1
Matched to waveform
generation register 0
RST2
Input "L" to INT pin
(Group 0,1)

Figure 1. 23.10. Base timer block diagram

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FFFF16

Contents of counter
800016

000016

b14 "1"
(Overflow signal)
"0"

"1"
b15 "0"

Figure 1. 23.11. Operation timing of base timer

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Time measurement (group 0 and 1)

Synchronizes external trigger input and stores the base timer value in the time measurement register j.
Specifications for the time measurement function are given in Table 1.23.3, the time measurement control
registers in Figures 1.23.12 to 1.23.13, and the operating timing of the time measurement function in Figure
1.23.14 and 15.

Group i time measurement control register j (i=0,1/j=0 to 7) (Note 1)

b7 b0 Symbol Address When reset
GiTMCRj(i=0/j=0 to 3) 00D816, 00D916, 00DA16, 00DB16 0016
GiTMCRj(i=0/j=4 to 7) 00DC16, 00DD16, 00DE16, 00DF16 0016
GiTMCRj(i=1/j=1, 2) 011916, 011A16 0016
GiTMCRj(i=1/j=6, 7) 011E16, 011F16 0016

Bit
symbol Bit name Function R W
b1 b0
CST0 0 0 : No time measurement
Time measurement
0 1 : Rising edge
trigger select bit
1 0 : Falling edge
CST1
1 1 : Both edges
b3 b2
DF0 0 0 : No digital filter
Digital filter function
0 1 : Must not be set
select bit
1 0 : Base timer clock
DF1
1 1 : f1

Gate function 0 : Gate function not used

GT
select bit (Note 2, 4) 1 : Gate function used

Gate function release 0 : No effect

GOC 1 : Release the gate when it
select bit (Note 2, 3) matches WG register
Gate function release 0 : No effect
GSC
bit (Note 2, 3)
1 : Gate released

Prescaler function 0 : Not used

PR
select bit (Note 2) 1 : Used

WG: Waveform Generation

Note 1: The 16-bit time measurement function is available for 8 channels (ch0 to 7) with group 0 and 4 channels
(ch1, 2, 6 and 7) with group 1. When using the 16-bit time measurement function, use the time
measurement register values for ch0, 3, 4 and 5 of group 1 as they are, or, if writing values, write "0016".
The 32-bit time measurement function can be used with 8 channels (ch0 to 7) by linking groups 0 and 1.
When using the 32-bit time measurement function, write the same value for time measurement registers
of similar channels in groups 0 and 1.
Note 2: These functions are available only for time measurement ch6 and 7 (time measurement registers 6
and 7). For ch0 to 5, set "0" for bits 4 to 7 of the time measurement register.
Note 3: These bits are valid only when "1" is set for the gate function select bit.
Note 4: The gate function cannot be used at the same time as the 32-bit time measurement function.

Figure 1. 23. 12. Time measurement-related register (1)

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Group i time measurement prescale register j (i=0,1/j=6,7)

b7 b0 Symbol Address When reset
GiTPRj(i=0/j=6, 7) 00E416, 00E516 0016
GiTPRj(i=1/j=6, 7) 012416, 012516 0016

Function Setting range R W

Prescales time measurement events.
(Generates the time measurement request after 0016 to FF16
an n + 1 count.) (Note)

Note : This function is only built into time measurement ch6 and 7 of Intelligent I/O groups 0 and 1.

Group i time measurement register j (i=0,1/j=0 to 7)

b15 b8
(b7) (b0) b7 b0 Symbol Address When reset
GiTMj(i=0/j=0 to 2) 00C116,00C016, 00C316,00C216, 00C516,00C416 000016
GiTMj(i=0/j=3 to 5) 00C716,00C616, 00C916,00C816, 00CB16,00CA16 000016
GiTMj(i=0/j=6,7) 00CD16,00CC16, 00CF16,00CE16 000016
GiTMj(i=1/j=0 to 2) 010116,010016, 010316,010216, 010516,010416 000016
GiTMj(i=1/j=3 to 5) 010716,010616, 010916,010816, 010B16,010A16 000016
GiTMj(i=1/j=6,7) 010D16,010C16, 010F16,010E16 000016

Function Setting range R W

When an event occures, the value of the base

timer is stored.

Group i function select register (i=0, 1)

b7 b0 Symbol Address When reset
GiFS (i=0,1) 00E716, 012716 0016

Bit
symbol Bit name Function R W

Ch0 TM/WG function Whether the corresponding port

FSC0
select bit functions as TM or WG is selected
0 : WG function is selected
Ch1 TM/WG function 1 : TM function is selected
FSC1
select bit

Ch2 TM/WG function

FSC2 select bit

Ch3 TM/WG function

FSC3
select bit

Ch4 TM/WG function

FSC4
select bit

Ch5 TM/WG function

FSC5 select bit

Ch6 TM/WG function

FSC6 select bit

Ch7 TM/WG function

FSC7 select bit

Note : In group 0, channles 2, 3, 6 and 7 cannot be selected in 16-bit mode. All channel can be selected
in 32-bit mode.
In group 1, channles 0 and 3 to 5 cannot be selected in 16-bit mode. All channel can be selected
in 32-bit mode.

Figure 1. 23. 13. Time measurement-related register (2)

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Table 1. 23.3. Specifications of time measurement function

Item Specifications
Time resolution t=1/(base timer count source)

Trigger input polarity select •Rising edge •Falling edge •Both edges

Measurement start condition (Note) Write "1" to the function enable bit

Measurement stop condition Write "0" to the function enable bit

Time measurement timing •Prescaler (only ch6 and ch7) : Every the (m+1) trigger input

•No prescaler : Every trigger input

Interrupt request generation timing Same timing as time measurement

INPC pin function Trigger input pin

(Set the corresponding pin to input with the function select register)
Select function •Digital filter function
Pulses will pass when they match either f1 or the base timerclock 3 times .
•Prescaler function (only for ch6 and ch7)
Counts trigger inputs and measures time by inputting a trigger of +1 the
value of the time measurement prescale register.
•Gate function (only for ch6 and ch7)
Prohibits the reception of trigger inputs after the time measurement starts
for the first trigger input. Trigger input is newly enabled when the below
conditions are satisfied.
(1) When the base timer i matches the value in WG register j
(2) When “1” is written for the gate function release bit
This bit automatically becomes “0” after the gate function is released.

Note: On channels where both the time measurement function and waveform output function can be used, select the
time measurement function for the function select register (addresses 00E716 and 012716).

Table 1. 23.4. List of time measurement channels with prescaler function and gate function
Group Channel TM register WG register matehes signal to release gate function

ch6 TM register 6 Base timer 0 matches to WG register 4

Group 0
ch7 TM register 7 Base timer 0 matches to WG register 5

ch6 TM register 6 Base timer 1 matches to WG register 4

Group 1
ch7 TM register 7 Base timer 1 matches to WG register 5

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(a) When the rising edge has been selected as the trigger input polarity
Base timer
count source

Base timer n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14
value

Trigger input

Time measurement
interrupts request
signal
Delay by 1 clock

Time measurement n n+5 n+8

register

(b) When both edges have been selected as the trigger input polarity

Base timer
count source

Base timer n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14
value

Trigger input

Time measurement
interrupts request
signal

Time measurement n n+2 n+5 n+8 n+12

register

(c) When digital filter is used (count of digital filter)

Digital filter
count source

Trigger input

Signals which do not match Max. 3.5 clock cycles

Triggers signal 3 times are stripped off
after passing
through digital filter Trigger signal delayed
by digital filter

Figure 1. 23. 14 Operation timing of time measurement function

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(a) When prescaler function is used (the value of time measurement prescaler register is "2".)

Base timer
counter source

Base timer n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14

Trigger input

Internal time
measurement trigger

Prescaler 2 1 0 2

Time measurement
interrupts request signal

Time measurement
n+1 n+13
register

(b) When gate function is used (gate function released by matching WG register)

Base timer
counter source

FFFF16
WG register value (XXXX16)
Base timer
000016

Function enabled
flag

Trigger input

This trigger input is invalid

Internal time because of gate function.
measurement trigger

Waveform generation
register match signal

Gate signal

Time measurement
interrupts request signal

Time measurement
register

Figure 1. 23. 15. Operation timing when gate function and prescaler function is used

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Waveform generation (WG) function (group 0 to 3)

Waveforms are generated when the base timer value matches the value of WG register j.
There are five mode in WG function: single phase waveform output mode (group 0 to 3), phase delayed
waveform output mode (group 0 to 3), SR (Set/Reset) waveform output mode (group 0 to 3), bit modulation
PWM output mode (group 2 and 3) and parallel real-time port output mode (group 2 and 3).
The WG function related registers are shown in Figures 1.23.16 to 1.23.19.

Group i waveform generation register j (i=0 to 3/j=0 to 7)

b15 b8
Symbol Address When reset
(b7) (b0) b7 b0
GiPOj(i=0/j=0 to 2) 00C116,00C016, 00C316,00C216, 00C516,00C416 XXXX16
GiPOj(i=0/j=3 to 5) 00C716,00C616, 00C916,00C816, 00CB16,00CA16 XXXX16
GiPOj(i=0/j=6,7) 00CD16,00CC16, 00CF16,00CE16 XXXX16
GiPOj(i=1/j=0 to 2) 010116,010016, 010316,010216, 010516,010416 XXXX16
GiPOj(i=1/j=3 to 5) 010716,010616, 010916,010816, 010B16,010A16 XXXX16
GiPOj(i=1/j=6,7) 010D16,010C16, 010F16,010E16 XXXX16
GiPOj(i=2/j=0 to 2) 014116,014016, 014316,014216, 014516,014416 XXXX16
GiPOj(i=2/j=3 to 5) 014716,014616, 014916,014816, 014B16,014A16 XXXX16
GiPOj(i=2/j=6,7) 014D16,014C16, 014F16,014E16 XXXX16
GiPOj(i=3/j=0 to 2) 018116,018016, 018316,018216, 018516,018416 XXXX16
GiPOj(i=3/j=3 to 5) 018716,018616, 018916,018816, 018B16,018A16 XXXX16
GiPOj(i=3/j=6,7) 018D16,018C16, 018F16,018E16 XXXX16

Function Setting range R W

A compared value for waveform generation

000016 to FFFF16
is stored. (Note)
WG: Waveform Generation
Note: When resetting the base timer on ch0, the timer is reset 2 clock cycles after it matches the waveform
generation register of ch0.

Group 3 waveform generation mask register j (j=4 to 7)

b15 b8
(b7) (b0) b7 b0 Symbol Address When reset
G3MKj (j=4,5) 019916,019816, 019B16,019A16 XXXX16
G3MKj (j=6,7) 019D16,019C16, 019F16,019E16 XXXX16

Function Setting range R W

(Note 1)
Masks base timer value 000016 to FFFF16
(Note 2)

Note 1: This function is provided only for the waveform generation functions on ch 4 to 7 of Intelligent I/O group 3.
Note 2: Comparison results are masked in bit positions where a "1" has been set for the register bits.

Figure 1. 23. 16. WG-related register (1)

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Group i waveform generation control register j (i=0 to 1/ j=0 to 7) (Note 1)

b7 b0 Symbol Address When reset
GiPOCRj (i=0/j=0,1) 00D016, 00D116 0X00X0002
GiPOCRj (i=0/j=4,5) 00D416, 00D516 0X00X0002
GiPOCRj (i=1/j=0 to 3) 011016, 011116, 011216, 011316 0X00X0002
GiPOCRj (i=1/j=4 to 7) 011416, 011516, 011616, 011716 0X00X0002

Bit
symbol Bit name Function R W
b2 b1b0
MOD0 0 0 0 : Single PWM mode
0 0 1 : S-R PWM mode (Note 2)
0 1 0 : Phase delayed PWM mode
Operation mode
0 1 1 : Must not be set
MOD1 select bit 1 0 0 : Must not be set
1 0 1 : Must not be set
1 1 0 : Must not be set (Note 3)
MOD2 1 1 1 : Assigns communication output
to a port (Note 4)

Must always set to "0"

When read, the value of this bit is indeterminate.

Output initial value 0: Outputs "0" as the initial value

IVL
select bit 1: Outputs "1" as the initial value
0: Reloads a new count when CPU
Reload timing writes the count
RLD 1: Reloads a new count when the
select bit
base timer i is reset

Must always set "0"

When read, the value of this bit is indeterminate.

Inverted output function 0: Output is not inverted

INV
select bit (Note 5) 1: Output is inverted

Note 1: Group 0 and 1 have 16-bit WG function and 32-bit WG function.

The 16-bit WG function is available for 4 channels (ch=0,1,4,5) with group 0 and 8 channels
(ch=0 to 7) with group 1. When using the 16-bit WG function, use the WG register values for ch2,
3, 6 and 7 of group 0 as they are, or, if writing values, write "0016".
The 32-bit WG function can be used with 8 channels (ch0 to 7) by linking groups 0 and 1.
When using the 32-bit WG function, write the same value for WG registers of similar channels in
groups 0 and 1.
Note 2: This setting is valid only on even-numbered channels. When this mode is selected, settings for
corresponding odd-numbered (even number + 1) channels are ignored. Waveforms are output for
even-numbered channels, not output for odd-numbered channels.
Note 3: When receiving in UART mode of group 0 and 1, group i WG control register 2 is set to be
"000001102".
Note 4: This setting is valid only for WG function ch0 and 1. Do not set this value for other channels.
Note 5: Inverted output function is allocated at the final stage of WG circuit. Therefore, when selecting

Figure 1. 23. 17. WG-related register (2)

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Group i waveform generation control register j (i=2 to 3/ j=0 to 7)

b7 b0 Symbol Address When reset
GiPOCRj (i=2/j=0 to 3) 015016, 015116, 015216, 015316 0X00 X0002
GiPOCRj (i=2/j=4 to 7) 015416, 015516, 015616, 015716 0X00 X0002
GiPOCRj (i=3/j=0 to 3) 019016, 019116, 019216, 019316 0X00 X0002
GiPOCRj (i=3/j=4 to 7) 019416, 019516, 019616, 019716 0X00 X0002

Bit
symbol Bit name Function R W
b2 b1b0
MOD0 0 0 0 : Single PWM mode
0 0 1 : S-R PWM mode (Note 1)
0 1 0 : Phase delayed PWM mode
Operation mode
0 1 1 : Must not be set
MOD1 select bit 1 0 0 : Bit modulation PWM mode
1 0 1 : Must not be set
1 1 0 : Must not be set
MOD2 1 1 1 : Assigns communication output
to a port (Note 2)

Parallel RTP output 0: Match of WG register j isn’t trigger

PRT
trigger select bit 1: Match of WG register j is trigger

Output initial value 0: Outputs "0" as the initial value

IVL
select bit 1: Outputs "1" as the initial value
0: Reloads a new count when CPU
Reload timing writes the count
RLD 1: Reloads a new count when the
select bit
base timer i is reset

RTP port function 0: Not use

RTP
select bit 1: Use

Inverted output function 0: Output is not inverted

INV
select bit (Note 3) 1: Output is inverted

Note 1: This setting is valid only on even-numbered channels. When this mode is selected, settings for
corresponding odd-numbered (even number + 1) channels are ignored. Waveforms are output for
even-numbered channels, not output for odd-numbered channels.
Note 2: This setting is valid only for group 2 WG function ch0 and 1. Do not set this value for other channels.
Note 3: Inverted output function is allocated at the final stage of WG circuit. Therefore, when selecting "0"
output by IVL bit and inverted output by INV bit, "1" is output.

Group i function enable register (i=0 to 3)

b7 b0 Symbol Address When reset
GiFE (i=0 to 3) 00E616, 012616, 016616, 01A616 0016

Bit
symbol Bit name Function R W

IFE0 Ch0 function enable bit Whether the corresponding port

IFE1 Ch1 function enable bit functions is selected
0 : Disables function on ch i
IFE2 Ch2 function enable bit
1 : Enables function on ch i
IFE3 Ch3 function enable bit
IFE4 Ch4 function enable bit
IFE5 Ch5 function enable bit
IFE6 Ch6 function enable bit
IFE7 Ch7 function enable bit

Figure 1. 23. 18. WG-related register (3)

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Group i function select register (i=0, 1)

b7 b0 Symbol Address When reset
GiFS (i=0,1) 00E716, 012716 0016

Bit
symbol Bit name Function R W

Ch0 TM/WG function Whether the corresponding port

FSC0
select bit functions as TM or WG is selected
0 : WG function is selected
Ch1 TM/WG function 1 : TM function is selected
FSC1
select bit

Ch2 TM/WG function

FSC2 select bit

Ch3 TM/WG function

FSC3
select bit

Ch4 TM/WG function

FSC4
select bit

Ch5 TM/WG function

FSC5 select bit

Ch6 TM/WG function

FSC6 select bit

Ch7 TM/WG function

FSC7 select bit

Note : In group 0, channles 2, 3, 6 and 7 cannot be selected in 16-bit mode. All channel can be selected
in 32-bit mode.
In group 1, channles 0 and 3 to 5 cannot be selected in 16-bit mode. All channel can be selected
in 32-bit mode.

Group i RTP output buffer register (i=2,3)

b7 b0 Symbol Address When reset
GiRTP (i=2,3) 016716, 01A716 0016

Bit
symbol Bit name Function R W
RTP0 Ch0 RTP output buffer The corresponding port's output
RTP1 value is set
Ch1 RTP output buffer
0 : Output "0"
RTP2 Ch2 RTP output buffer 1 : Output "1"
RTP3 Ch3 RTP output buffer
RTP4 Ch4 RTP output buffer
RTP5 Ch5 RTP output buffer
RTP6 Ch6 RTP output buffer
RTP7 Ch7 RTP output buffer

Figure 1. 23. 19. WG-related register (4)

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(1) Single phase waveform output mode (group 0 to 3)

This mode is set when the base timer value matches the value of WG register j, and reset when the base
timer overflows or the count is reset. Specifications for the single phase waveform output mode are given
in Table 1.23.5 and an operating chart for the single phase waveform output mode in Figure 1.23.20.

Table 1. 23.5. Specifications of single phase waveform output mode

Item Specifications

Output waveform •When free run operation

Period : Base timer count source x 1/65536
"H" level width : 1/base timer count source x (65536 - m)
•Resetting when the base timer matches WG register 0 (ch0)
Period : Base timer count source x 1/(k+2)
"H" level width : 1/base timer count source x (k+2-m)
m : values set to WG register j k: values set to WG register 0

Waveform output start condition Write "1" to the function enable bit(Note)
Waveform output stop condition Write "0" to the function enable bit

Interrupt generation timing When the base timer value matches the WG register j

OUTC pin Pulse output (Corresponding pins are set with the function select register.)

Read from the WG register 0 The set value is output

Write to the WG register 0 Can always write

Select function •Initial value setting function

Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the OUTC pin

Note: On channels where both the time measurement function and waveform output function can be used, select the
waveform output function for the function select register (addresses 00E716 and 012716).

When WG register is "xxxa16" Reset when channel 0 (xxxa16) is matched

Count source

Base timer xxxa xxxb xxxc xxxd xxxe ffff 0000 0001 xxxa xxxb 0000 0001 0002 0003

Output "H"
waveform "L"

Interrupt "1"
request flag "0"
Cleared by software.

Figure 1. 23. 20. Operation timing in single phase waveform output mode

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(2) Phase delayed waveform output mode (group 0 to 3)

This mode is repeatedly set and reset when the base timer value matches the value of WG register j.
Specifications for the phase delayed waveform output mode are given in Table 1.23.6 and an operation
timing in phase delayed waveform output mode in Figure 1.23.21.

Table 1. 23.6. Specifications of phase delayed waveform output mode

Item Specifications

Output waveform •When free run operation

Period : Base timer count source x 1/65536 x 1/2
"H" and "L" level width : 1/base timer count source x 65536
•Resetting when group i base timer matches WG register 0 (ch0)
Period : Base timer count source x 1/(k+2) x 1/2
"H" and "L" level width : 1/base timer count source x (k+2)
k : values set to WG register 0

Waveform output start condition Write "1" to the function enable bit (Note)
Waveform output stop condition Write "0" to the function enable bit

Interrupt generation timing When the base timer value matches the WG register j

OUTCij pin Pulse output (Corresponding pins are set with the function select register.)

Read from the WG register The set value is output

Write to the WG register Can always write

Select function •Initial value setting function

Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the OUTC pin

Note : On channels where both the time measurement function and waveform output function can be used, select the
waveform output function for the function select register (addresses 00E716 and 012716).

When WG register is "xxxb16"

Count source

Base timer xxxa xxxb xxxc ffff 0000 0001 xxxa xxxb xxxc xxxd

Output "H"
waveform "L"
Interrupt "1"
request flag "0"

Cleared by software. Cleared by software.

Figure 1. 23. 21. Operation timing in phase delayed waveform output mode

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(3) SR (Set/Reset) waveform output mode (group 0 to 3)

This mode is set when the base timer value matches the value of WG register j (j is an even-numbered
channel), and reset when the base timer matches the WG register (j + 1) or the base timer value is “0”.
Specifications for the SR waveform output mode are given in Table 1.23.7 and an operating chart for the
SR waveform output mode in Figure 1.23.22.

Table 1. 23.7. Specifications of SR waveform output mode

Item Specifications

Output waveform •When free run operation

Period : Base timer count source x 1/65536
"H" level width : 1/base timer count source x (m-p)
•Resetting when base timer matches WG register 0 (ch0)
Period : Base timer count source x 1/(k+2) (Note 1)
"H" level width : 1/base timer count source x (m-p)
m : values set to WG register j p : values set to WG register i(j+1)
k : values set to WG register 0 (j is an even-numbered channel) (Note 2)

Waveform output start condition Write "1" to the function enable bit (Note 3)

Waveform output stop condition Write "0" to the function enable bit

Interrupt generation timing When the base timer value matches the WG register j

OUTC pin (Note 4) Pulse output (Corresponding pins are set with the function select register.)

Read from the WG register The set value is output

Write to the WG register Can always write

Select function (Note 5) •Initial value setting function

Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the OUTC pin

Note 1: The SR waveform output function that sets and resets the mode on ch0 and 1 cannot be used when the base
timer is reset by WG register 0 (ch0).
Note 2: Set WG register values for odd-numbered channels that are lower than even-numbered channels.
Note 3: On channels where both the time measurement function and waveform output function can be used, select the
waveform output function for the function select register (addresses 00E716 and 012716).
Note 4: SR waveforms are output for even-numbered channels only.
Note 5: Settings for the WG control register on the odd-numbered channels are ignored.

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When WG register j is "xxxb16" and WG register j + 1 is "yyya16"

Count source

Base timer xxxa xxxb xxxc yyy9 yyya yyyb yyyc

Output "H"
waveform "L"

Channel j Interrupt "1"

request flag "0"

Cleared by software.
Channel j+1 Interrupt "1"
request flag "0"
Cleared by software.

Figure 1. 23. 22. Operation timing in SR waveform output mode

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(4) Bit modulation PWM output mode (group 2 and 3)

This mode performs PWM to improve output resolution. Specifications for the bit modulation PWM mode
are given in Table 1.23.8 and an operating chart for the bit modulation PWM mode in Figure 1.23.23.

Table 1. 23.8. Specifications of bit modulation PWM mode

Item Specifications
Output waveform Period : Base timer count source x 1/64
"H" level width (avelage) : 1/base timer count source x [k+(m/1024)]
k : values set to WG register j (six high-order bits)
m : values set to WG register j (ten lower-order bits)

Waveform output start condition Write "1" to the function enable bit

Waveform output stop condition Write "0" to the function enable bit

Interrupt generation timing When the base timer value matches the WG register j

OUTC pin Pulse output (Corresponding pins are set with the function select register.)

Read from the WG register j The set value is output

Write to the WG register j Can always write
Select function •Initial value setting function

Sets output level used at waveform output start

•Inverted output function

Inverts waveform output level and outputs the waveform from the OUTC pin

Sets PWM width Sets bit modulation frequency

k=0 to 63 (3F16) m=0 to 1023 (3FF16)
b15 b10 b9 b0

WG register j

1024 pulses
3F16 Set value k

A
Base timer 6
low-order bits
0016

AA
k
Output waveform

AA
Increases the "L" level width for
1 clock cycle for an m number of
pulses out of 1,024
3F16
Base timer
6 low-order bits Set value k
0016
Base timer

A
count source

Internal signal

k k+1
Output waveform

Figure 1. 23. 23. Operation timing in bit modulation PWM mode

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(5) Real-time port output mode (group 2 and 3)

This mode outputs the value set in the real-time port register from the OUTC pin when the base timer
value matches the value of WG register j. Specifications for the real-time port output mode are given in
Table 1.23.9 and a block diagram and timing chart of the real-time port output function in Figure 1.23.24.

Table 1. 23.9. Specifications of real-time port output mode

Item Specifications

Waveform output start condition Write "1" to the function enable bit

Waveform output stop condition Write "0" to the function enable bit

Interrupt generation timing When the base timer value matches the WG register j

OUTC pin RTP output (Corresponding pins are set with the function select register.)

Read from the WG register j The set value is output

Write to the WG register j Can always write

Read from the RTP output buffer register The set value is output
Write to the RTP output buffer register Can always write
Select function •Initial value setting function
Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the
OUTC pin

Base timer
AAA
AAA
RTP output buffer register
RTP output

AAA
bit0 DQ OUTCi0
WG register 0 T

WG register 6
AAA
AAA
bit6 DQ
T
OUTCi6

AAA
bit7 (i=2, 3)
DQ OUTCi7
WG register 7 T

When WG register j = "xxx816" and

bit j of RTP output buffer register = "1" (previous value is 0)

Count source

Base timer xxx5 xxx6 xxx7 xxx8 xxx9 xxxa xxxb xxxc xxxd xxxe xxxf

"H"
Output waveform "L"

Channel i "1"
interrupt request flag "0"
Cleared by software.

Figure 1. 23. 24. Block diagram and operation timing of real-time port output function

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(6) Parallel real-time port output mode (group 2 and 3)

This mode outputs the value set in the real-time port register from the OUTC pin when the base timer
value matches the value of WG register j. Specifications for the parallel real-time port output mode are
given in Table 1.23.10 and a block diagram and timing chart of the real-time port output function in Figure
1.23.25.

Table 1. 23.10. Specifications of parallel real-time port output mode

Item Specifications

Waveform output start condition Write "1" to the function enable bit

Waveform output stop condition Write "0" to the function enable bit

Interrupt generation timing When the base timer value matches the WG register

OUTC pin RTP output (Corresponding pins are set with the function select
register.)
Read from the WG register The set value is output
Write to the WG register Can always write

Read from the RTP output buffer register The set value is output

Write to the RTP output buffer register Can always write

Select function •Initial value setting function
Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the
OUTC pin

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AA
AA
Real-time port output
buffer register
Real-time port output

AA
Base timer bit0 DQ OUTCi0
T

AA
bit1 DQ OUTCi1
WG register 0 T

AA
WG register 1 bit2 DQ OUTCi2

AA
T
WG register 2
bit3 DQ OUTCi3
WG register 3

AA
T

WG register 4 bit4 DQ OUTCi4

AA
T
WG register 5
bit5 DQ OUTCi5

AA
WG register 6 T

WG register 7 OUTCi6

AA
bit6 DQ
T

AA
bit7 DQ OUTCi7
T

(i=2, 3)

When WG register j = "xxx116" RTP output buffer register = "0xxx xx012"

WG register j + 1 = "xxx516" RTP output buffer register = "1xxx xx102"
(this value is saved to RTP output buffer register as channel j interrupt request trigger)
WG register j + 2 = "xxxC16" RTP output buffer register = "1xxx xx112"
(this value is saved to RTP output buffer register as channel j+1 interrupt request trigger)

Count source

Base timer xxx1 xxx2 xxx3 xxx4 xxx5 xxx6 xxx7 xxxc xxxd xxxe xxxf

Output waveform "H"

OUTCi0 "L"

"H"
Output waveform
OUTCi1 "L"

Output waveform "H"

OUTCi7 "L"

Channel j "1"
interrupt request flag "0"

Cleared by software.
Channel j+1 "1"
interrupt request flag "0"

Cleared by software.
Channel j+2 "1"
interrupt request flag "0"
Cleared by software.

Figure 1. 23. 25. Block diagram and operation timing of parallel real-time port output function

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Serial I/O (group 0 to 2)

Intelligent I/O groups 0 to 2 each have two internal 8-bit shift registers. When used in conjunction with the
time measurement (TM) function or WG function, these shift registers enable clock synchronous/asyn-
chronous serial communications.

(1) Clock synchronous serial I/O mode (group 0, 1)

Intelligent I/O groups 0 and 1 each have communication block that have two internal 8-bit shift registers.
When used in conjunction with the communication block and WG function, these shift registers enable
8-bit clock synchronous and HDLC data process function. When used in conjunction with the communi-
cation block, TM function and WG function, these shift registers enable 8-bit clock asynchronous com-
munication.
Table 1.23.11 lists using registers in group 0 and 1, figure 1.23.26 to 1.23.29 shows the related regis-
ters.

Table 1.23.11. Using registers in group 0 and 1

Clock synchronous serial I/O UART HDLC
Base timer control register 0 √ √ √
Base timer control register 1 √ √ √
Time measument control register 2 – √ –
Waveform generate control register 0 √ √ √
Waveform generate control register 1 – – √
Waveform generate control register 2 √ √ –
Waveform generate control register 3 √ √ –
Waveform generate register 0 √ √ √
Waveform generate register 1 √ – √
Time measument /Waveform generate register 2 √ √ –
Waveform generate register 3 √ √ –
Function select register √ √ √
Function enable register √ √ √
SI/O communication mode register √ √ √
SI/O extended mode register – – √
SI/O communication control register √ √ √
SI/O extended transmit control register – – √
SI/O extended receive control register – – √
SI/O special communication interrupt detect register – – √
SI/O receive buffer register √ √ √
Transmit buffer √ √ √
(Receive data register ) – – √
Data compare register j (j=0 to 3) – – √
Data mask register j (j=0, 1) – – √
Transmit CRC code register – – √
Receive CRC code register – – √
Transmit output register – – √
Receive input register – – √
√ : Use – : Not use

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Group i receive input register (i=0,1)

b7 b0 Symbol Address When reset
GiRI (i=0, 1) 00EC16, 012C16 Indeterminate

Function Setting range R W

Data that is input to the receive data

0016 to FF16
process unit

Group i transmit output register (i=0,1)

b7 b0 Symbol Address When reset
GiTO (i=0, 1) 00EE16, 012E16 Indeterminate

Function Setting range R W

Data that is output from the transmit data

process unit

Group i SI/O communication control register (i=0,1)

b7 b0 Symbol Address When reset
GiCR (i=0,1) 00EF16, 012F16 0000 X0002

Bit
symbol Bit name Function R W

Transmit buffer 0 : Data present in transmit buffer register

TI
empty flag 1 : No data present in transmit buffer register

0 : Data present in transmit register

Transmit register (during transmission)
TXEPT
empty flag 1 : No data present in transmit register
(transmission completed)

Receive complete 0 : No data present in receive buffer register

RI
flag 1 : Data present in receive buffer register

Nothing is assigned. When write, set to "0".

When read, the contents is indeterminate.

0 : Transmission disabled
TE Transmit enable bit
1 : Transmission enabled

0 : Reception disabled
RE Receive enable bit
1 : Reception enabled

RxD input polarity 0 : No reverse (Usually set to "0")

IPOL
reverse select bit 1 : Reverse (Note)

TxD output polarity 0 : No reverse (Usually set to "0")

OPOL
reverse select bit 1 : Reverse (Note)
Note :This bit is set to "1" in UART mode.

Figure 1. 23. 26. Group 0 and 1 related register (1)

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Group i SI/O receive buffer register (i=0,1)

b15 b14 b13 b12 b11 b10 b9 b8
(b7)(b6)(b5)(b4)(b3)(b2)(b1)(b0) b7 b0 Symbol Address When reset
GiBF(i=0,1) 00E916,00E816, 012916,012816 Indeterminate

Bit
symbol Bit name Function R W

Receive buffer Receive data

Nothing is assigned.
When read, their value are indeterminate.
Overrun error flag 0 : No overrun error
OER
(Note) 1 : Overrun error found

Framing error flag 0 : No Framing error

FER
(Note) 1 : Framing error found
Parity error flag 0 : No parity error
PER
(Note) 1 : Parity error found
Nothing is assigned.
When read, its value is indeterminate.
Note: Only effective for receive data.

Group i SI/O communication mode register (i=0,1)

b7 b0 Symbol Address When reset
GiMR (i=0,1) 00ED16, 012D16 0016

Bit
symbol Bit name Function R W
b1 b0
GMD0 0 0 : UART mode
Communication mode
0 1 : Serial I/O mode
select bit
1 0 : Special communication mode
GMD1
1 1 : HDLC data process mode

Internal/external clock 0 : Internal clock (Note 2)

CKDIR
select bit 1 : External clock (Note 3)

Stop bit length 0 : 1 stop bit

STPS
select bit (Note 1) 1 : 2 stop bits

Odd/even parity 0 : Odd parity

PRY
select bit (Note 1) 1 : Even parity

Parity enable 0 : Parity disabled

PRYE
select bit (Note 1) 1 : Parity enabled

Transfer direction 0 : LSB first

UFORM
select bit 1 : MSB first

Transmit interrupt 0 : Transmit buffer is empty

IRS
cause select bit 1 : Transmit is completed

Note 1: Can be used only in the UART mode.

Note 2: Select a pin for clock output by setting the waveform generation control register, input function select
register, and function select registers A, B and C.
Data transmission pins are the same as clock output pins.
Note 3: Select which pins will input the clock with the input function select register and set those pins to the
input port using function select register A.
Data input pins are the same as with clock input pins.

Figure 1. 23. 27. Group 0 and 1 related register (2)

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Group i SI/O expansion mode register (i=0,1) (Note 1)

b7 b0 Symbol Address When reset
GiEMR (i=0,1) 00FC16, 013C16 0016

Bit
symbol Bit name Function R W

Synchronous mode 0 : Normal mode

SMODE
select bit 1 : Resynchronous mode

CRC initial value 0 : "000016" is set

CRCV
select bit 1 : "FFFF16" is set

CRC initialization 0 : Not initialize

ACRC
select bit 1 : Initialize (Note 2)

Bit stuffing error 0 : Not use

BSINT
interrupt select bit 1 : Use

Reception source 0 : RxD pin

RXSL
select bit 1 : Receive input register

Transmission source 0 : TxD pin

TXSL
select bit 1 : Transmit output register
b7 b6
CRC0 0 0 : X8+X4+X+1
CRC polynomial
0 1 : Must not be set
select bit
CRC1
1 0 : X16+X15+X2+1
1 1 : X16+X12+X5+1
Note 1: Other than when in the special communication mode or HDLC data process mode, either
use the reset state as is or write "0016".
Note 2: Initialized when the data compare register matches.

Group i SI/O expansion transmit control register (i=0,1) (Note)

b7 b0 Symbol Address When reset
GiETC (i=0,1) 00FF16, 013F16 00000XXX2

Bit
symbol Bit name Function R W

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.

SOF transmit 0 : No SOF transmit request

SOF
request bit 1 : SOF transmit request

Transmit CRC 0 : Not use

TCRCE
enable bit 1 : Use

0 : Not use
ABTE Arbitration enable bit
1 : Use

Transmit bit stuffing "1" 0 : "1" is not inserted

TBSF0
insert select bit 1 : "1" is inserted

Transmit bit stuffing "0" 0 : "0" is not inserted

TBSF1
insert select bit 1 : "0" is inserted

Note : Other than when in the special communication mode or HDLC data processing mode, either
use the reset state as is or write "0016".

Figure 1. 23. 28. Group 0 and 1 related register (3)

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Group i SI/O expansion receive control register (i=0,1) (Note 1)

b7 b0 Symbol Address When reset
GiERC (i=0,1) 00FD16, 013D16 0016

Bit
symbol Bit name Function R W
Data compare 0 : Does not compare the received data with
CMP0E function 0 data compare register 0
select bit 1 : Compare the received data with data compare register 0
Data compare 0 : Does not compare the received data with
CMP1E function 1 data compare register 1
select bit 1 : Compare the received data with data compare register 1
Data compare 0 : Does not compare the received data with
CMP2E function 2 data compare register 2
select bit 1 : Compare the received data with data compare register 2
Data compare 0 : Does not compare the received data with
CMP3E function 3 data compare register 3 (Note 2)
select bit 1 : Compare the received data with data compare register 3
Receive CRC 0 : Not enable
RCRCE
enable bit 1 : Enable
Receive shift 0 : Receive shift operation disabled
RSHTE operation
enable bit 1 : Receive shift operation enabled
Receive bit 0 : "1" is not deleted
RBSF0 stuffing "1" delete
select bit 1 : "1" is deleted
Receive bit 0 : "0" is not deleted
RBSF1 stuffing "1" delete
select bit 1 : "0" is deleted

Note 1: Other than when in the special communication mode or HDLC data processing mode, either
use the reset state as is or write "0016".
Note 2: To use the CRC initialization function (when bit 2 of SI/O expansion mode register is set to "1"),
set bit 3 to "1".

Group i special communication interrupt detect register (i=0,1) (Note)

b7 b0 Symbol Address When reset
GiIRF (i=0,1) 00FE16, 013E16 0000 00XX2

Bit
symbol Bit name Function R W

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.

Bit stuffing error 0 : Not detected

BSERR
detecting flag 1 : Detected

Arbitration lost 0 : Not detected

ABT
detecting flag 1 : Detected
Interrupt cause 0 : Received data does not match data
IRF0 determination compare register 0
flag 0 1 : Received data matches data compare register 0
Interrupt cause 0 : Received data does not match data
IRF1 determination compare register 1
flag 1 1 : Received data matches data compare register 1
Interrupt cause 0 : Received data does not match data
IRF2 determination compare register 2
flag 2 1 : Received data matches data compare register 2
Interrupt cause 0 : Received data does not match data
IRF3 determination compare register 3
flag 3 1 : Received data matches data compare register 3
Note : Other than when in the special communication mode or HDLC data processing mode, either
use the reset state as is or write "0016".

Figure 1. 23. 29. Group 0 and 1 related register (4)

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Group i transmit buffer/receive data register (i=0,1)

b7 b0 Symbol Address When reset
GiDR (i=0,1) 00EA16, 012A16 Indeterminate

Function Setting range R W

Transmit data for data compare is stored

Receive data for data compare is stored

Group i data compare register j (i=0,1/j=0 to 3)

b7 b0 Symbol Address When reset
GiCMPj (i=0/j=o to 3) 00F016, 00F116, 00F216, 00F316 Indeterminate
GiCMPj (i=1/j=o to 3) 013016, 013116, 013216, 013316 Indeterminate

Function Setting range R W

Compare data 0016 to FF16

Note : When using the data compare registers 0 and 1, the data mask registers 0 and 1 must be set.

Group i data mask register j (i=0,1/j=0,1)

b7 b0 Symbol Address When reset
GiMSKj (i=0/j=0, 1) 00F416, 00F516 Indeterminate
GiMSKj (i=1/j=0, 1) 013416, 013516 Indeterminate

Function Setting range R W

Mask data for receive data (masked by "1") 0016 to FF16

Group i transmit CRC code register (i=0,1)

b15 b8
(b7) (b0) b7 b0 Symbol Address When reset
GiTCRC (i=0, 1) 00FB16,00FA16, 013B16, 013A16 000016

Function Setting range R W

Transmit CRC calculation results

(Note)

Note : Computed results are initialized when the transmit CRC enable bit (bit 4 of group i expanded
transmit control register) is set to "0".

Group i receive CRC code register (i=0,1)

b15 b8
(b7) (b0) b7 b0 Symbol Address When reset
GiRCRC (i=0, 1) 00F916,00F816, 013916, 013816 000016

Function Setting range R W

Receive CRC calculation results

Note 1: Computed results are initialized when the receive CRC enable bit (bit 4 of group i expanded
reseive control register) is set to "0", or when the CRC initialization bit (bit 2 of group i SI/O
expansion mode register) is set to "1" and values match the data comparison register.
Note 2: Initialize to selected value when starting to receive.

Figure 1. 23. 30. Group 0 and 1 related register (5)

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• Clock synchronous serial I/O mode (group 0 and 1)

Table 1.23.12 gives specifications for the clock synchronous serial I/O mode.

Table 1.23.12. Specifications of clock synchronous serial I/O mode (group 0 and 1)
Item Specification
Transfer data format • Transfer data length: 8 bits fixed
Transfer clock • When internal clock is selected
_ Transfer speed is determined when the base timer is reset by the ch0 WG function

Transfer rate (bps) = base timer count source (frequency) / (k+2) / 2

k : values set to WG register 0
_ Transfer clock is generated when the transfer clock in the phase delayed
waveform output mode
Transmit clock : ch3 WG function
Receive clock : ch2 WG function
Sets the same value in the WG registers on ch2 and ch3
• When external clock is selected
_ Transfer rate (bps) = Clock input to ISCLK pin
Transmission start condition To start transmission, the following requirements must be met:
• Transmit enable bit = “1”
• Write data to transmit buffer
Reception start condition To start reception, the following requirements must be met:
• Receive enable bit = “1”
Interrupt request • When transmitting
_ When transmit buffer is empty, transmit interrupt cause select bit = “0”
generation timing
_ When transmission is completed, transmit interrupt cause select bit = “1”
• When receiving
When data is transferred to SI/O receive buffer register
Error detection • Overrun error
This error occurs when the next data is ready before the contents of SI/O receive
buffer register are read out
Select function • LSB first/MSB first selection
When transmission/reception begins with bit 0 or bit 7, it can be selected
• Transmit/receive data polarity switching
This function is reversing ISTxD pin output and ISRxD pin input.
(All I/O data level is reversed.)

Note: Set the transmission clock to at least 6 divisions of the base timer clock.

Table 1.23.13 lists I/O pin functions for the clock synchronous serial I/O mode of groups 0 and 1.
From when the operating mode is selected until transmission starts, the ISTxDi pin is "H" level. Figure
1.23.31 shows typical transmit/receive timings in clock synchronous serial I/O mode in group 0 and 1.

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Table 1.23.13. I/O pin functions in clock synchronous serial I/O mode of group 0, group 1
Pin name Function Selected method
ISTxD Serial data output • Use the ch0 WG function
(P76, P150, P73, P110) • Sets "111" for the operating mode select bit (bits 2, 1 and 0) in
WG control register 0
• Selects ISTxD output for the port using function select registers
A, B and C

ISRxD Serial data input • Selects a using port with input function select register
(P80, P152, P75, P112) • Selects I/O with function select register A
• Sets a selected port to input using the port direction register
ISCLK Transfer clock output • Use the ch1 WG function
(P77, P151, P74, P111) • Sets "111" for the operating mode select bit (bits 2, 1 and 0) in
WG control register 1
• Sets "0" for the internal/external clock select bit (bit 2) of the
SI/O communication mode register
• Selects ISCLK output for the port using function select registers
A, B and C
Transfer clock input • Selects a using port with input function select register
• Sets "1" for the internal/external clock select bit (bit 2) of the
SI/O communication mode register
• Sets a selected port to input using the port direction register
• Selects I/O port with function select register A

Write to transmit buffer

Base timer resets using

ch0 WG function
T
Base timer
t

Receive clock using

ch2 WG function

Transmit clock using

ch3 WG function

Receive data bit 0 bit 1 bit 6 bit 7

(Input to INPCi2/ISRxDi pin
(i=0,1))
Transmit data bit 0 bit 1 bit 2 bit 6 bit 7

T: Transfer rate/2
t : Values set to ch2 WG register
Values set to ch3 WG register

Figure 1.23.31. Typical transmit/receive timings in clock synchronous serial I/O mode in group 0 and 1

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(2) Clock asynchronous serial I/O mode (UART) (group 0 and 1)

Table 1.23.14 lists the specifications for the UART mode.

Table 1.23.14. Specifications of UART mode

Item Specification
Transfer data format • Character bit (transfer data) : 8 bits
• Start bit : 1 bit
• Parity bit : Odd, even, or nothing selected
• Stop bit : 1 bit or 2 bits selected
Transfer clock • When internal clock is selected (Generates the transmit/receive clock in the phase
delayed waveform output mode)
_ Transfer speed is determined when the base timer is reset by the ch0 WG function
Transfer rate (bps) = base timer count source (frequency) / (k+2) / 2
k : values set to WG register 0
_ Transfer clock is generated when the transfer clock in the phase delayed
waveform output mode
Transmit clock : ch3 WG function
Receive clock : Change ch2 TM function to WG function
Detects falling edge of start bit
Changes to the WG mode when the time measurement interrupt arrives
• When external clock is selected
_ Transfer rate (bps) = Clock input to ISCLK pin
Transmission start condition To start transmission, the following requirements must be met:
• Transmit enable bit = “1”
• Write data to transmit buffer
Reception start condition To start reception, the following requirements must be met:
• Receive enable bit = “1”
Interrupt request • When transmitting
generation timing _ When transmit buffer is empty, transmit interrupt cause select bit = “0”
_ When transmission is completed, transmit interrupt cause select bit = “1”
• When receiving
_ When data is transferred to SI/O receive buffer register
Error detection • Overrun error : This error occurs when the next data is ready before contents
of SI/O receive buffer register are read out
• Framing error : This error occurs when the number of stop bits set is not detected
• Parity error : This error occurs when if parity is enabled, the number of 1’s in
parity and character bits does not match the number of 1’s set
Select function • Stop bit length : Stop bit length can be selected as 1 bit or 2 bits
• Parity : Parity can be turned on/off
: When parity is on, odd/even parity can be selected
• LSB first/MSB first selection :
Whether transmit/receive begins with bit 0 or bit 7 can be selected
• Transmit/receive data polarity switching :
This function is reversing ISTxD port output and ISRxD port input. (All I/O data level
are reversed.)
• Data transfer bit length : Transmission data length can be set between 1 to 8 bits

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Write to transmit buffer

Base timer resets using ch0 WG function

k+2
Base timer
t

Transmit clock using

ch3 WG function

Transmit data Start Bit bit 0 bit 7 Parity Stop Bit (1 bit)

t : Values set to ch3 WG register

Figure 1.23.32. Typical transmit timings in UART mode

Base timer resets using ch0 WG function

t : Values set to ch2 WG register
k+2
Base timer
t

Receive data
(Input to INPCi2/ISRxDi pin
Start Bit bit 0 bit 7 Parity Stop Bit (1 bit)
(i=0,1))
Receive clock using
ch2 WG function

Reception completed
Interrupt request interrupt request
signal

Figure 1.23.33. Typical receive timing in UART mode

TxD, RxD I/O polarity reverse function

This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) are reversed. TxD output polarity reverse select bit is
set to “0” (not to reverse) for usual use.

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(2) Clock synchronous serial I/O mode (group 2)

Intelligent I/O groups 2 has communication block that have two internal 8-bit shift registers. When used
in conjunction with the communication block and WG function, these shift registers enable variable clock
synchronous and IE Bus (Note) communications.
Table 1.23.16 lists using registers in group 2, figure 1.23.34 to 1.23.37 shows the related registers.

Note : IE Bus is a trademark of NEC corporation.

Table 1.23.16. Using registers in group 2

Clock synchronous serial I/O IE Bus
Base timer control register 0 √ √
Base timer control register 1 √ √
Waveform generate control register 0 √ √
Waveform generate control register 1 – √
Waveform generate control register 2 √ √
Waveform generate control register 3 – √
Waveform generate control register 4 – √ (Note 1)
Waveform generate control register 5 – √
Waveform generate control register 6 – √
Waveform generate control register 7 – √
Waveform generate register 0 √ √
Waveform generate register 1 – √
Waveform generate register 2 √ √
Waveform generate register 3 – √
Waveform generate register 4 – √
Waveform generate register 5 – √
Waveform generate register 6 – √
Waveform generate register 7 – √
Function enable register √ √
SI/O communication mode register √ √
SI/O communication control register √ √
IE Bus control register – √
IE Bus address register – √
IE Bus transmit interrupt cause detect register – √
IE Bus receive interrupt cause detect register – √
SI/O receive buffer register √ √
SI/O transmit buffer register √ √
√ : Use – : Not use
Note 1: When receiving slave, set corresponding value with 32.5 µs. Don't set 170 µs.

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Group 2 SI/O transmit buffer register

b15 b14 b13 b12 b11 b10 b9 b8
(b7)(b6)(b5)(b4)(b3)(b2)(b1)(b0) b7 b0 Symbol Address When reset
G2TB 016D16, 016C16 Indeterminate

Bit
symbol Bit name Function R W

Transmit buffer Transmit data

b10 b9 b8
SZ0 0 0 0 : 8-bit long
0 0 1 : 1-bit long
0 1 0 : 2-bit long
SZ1 Transfer bit length : 3-bit long
0 1 1
select bit 1 0 0 : 4-bit long
SZ2 1 0 1 : 5-bit long
1 1 0 : 6-bit long
1 1 1 : 7-bit long

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.

ACK function 0 : No function

A 1 : Adds an ACK bit after the final
select bit
transmission bit
Parity operation 0 : Adds the parity bit after the transmitted data
PC 1 : Repeats the parity check with the next
continuing bit (Note) transmission
Parity function 0 : No parity
P
select bit 1 : Parity (Only even parity)

Note: When this bit is set to "1", set the parity function select bit to "0".

Group 2 SI/O receive buffer register

b15 b14 b13 b12 b11 b10 b9 b8
(b7)(b6)(b5)(b4)(b3)(b2)(b1)(b0) b7 b0 Symbol Address When reset
G2RB 016F16, 016E16 Indeterminate

Bit
symbol Bit name Function R W

Receive buffer Receive data

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.
Overrun error flag 0 : No overrun error
OER
(Note) 1 : Overrun error found

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.
Note : This bit is automatically set to "0" when communication unit reset is selected for the communication
mode select bit and the reception enable bit is set to "0".

Figure 1. 23. 34. Group 2 Intelligent I/O-related register (1)

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Group 2 IE Bus control register

b7 b0 Symbol Address When reset
IECR 017216 00XXX0002

Bit
symbol Bit name Function R W

IE Bus enable bit 0 : IE Bus disabled (Note)

IEB
1 : IE Bus enabled

IE Bus transmit start 0 : Transmit completed

IETS
request bit 1 : Transmit start

0 : Idle state
IEBBS IE Bus busy flag
1 : Busy state (start condition detected)

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.

Digital filter 0 : No digital filter

DF
select bit 1 : Digital filter

IE Bus mode 0 : Mode 1

IEM
select bit 1 : Mode 2

Note :When this bit is set to "0", hold "0" for at least 1 cycle of base timer .

Group 2 IE Bus address register

b15 b14 b13 b12 b11 b10 b9 b8
(b7)(b6)(b5)(b4)(b3)(b2)(b1)(b0) b7 b0
Symbol Address When reset
IEAR 017116, 017016 Indeterminate

Function R W

Address data

Address data

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.

Figure 1. 23. 35. Group 2 Intelligent I/O-related register (2)

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Group 2 IE Bus transmit interrupt cause determination register

b7 b0 Symbol Address When reset
IETIF 017316 XXX000002

Bit
symbol Bit name Function R W

Normal termination 0 : Terminated in error

IETNF
flag 1 : Terminated normally (Note)

0 : No error
IEACK ACK error flag
1 : Error found (Note)

Max. transfer byte 0 : No error

IETMB
error flag 1 : Error found (Note)

0 : No error
IETT Timing error flag
1 : Error found (Note)

0 : No error
IEABL Arbitration lost flag (Note)
1 : Error found

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.

Note : Only "0" can be written for this bit. Also, it is cleared to "0" when "0" is written for bit 0 of the IE Bus
control register. At this time, hold "0" for at least 1 cycle of base timer clock.

Group 2 IE Bus receive interrupt cause determination register

b7 b0 Symbol Address When reset
IERIF 017416 XXX000002

Bit
symbol Bit name Function R W

Normal termination 0 : Terminated in error

IERNF 1 : Terminated normally
flag (Note)

0 : No error
IEPAR Parity error flag
1 : Error found (Note)

Max. transfer byte 0 : No error

IERMB
error flag 1 : Error found (Note)

0 : No error
IERT Timing error flag
1 : Error found (Note)

Other cause receive 0 : No error

IERETC (Note)
completed flag 1 : Error found

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.

Note : Only "0" can be written for this bit. Also, it is cleared to "0" when "0" is written for bit 0 of the IE Bus
control register. At this time, hold "0" for at least 1 cycle of base timer clock.

Figure 1. 23. 36. Group 2 Intelligent I/O-related register (3)

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Group 2 SI/O communication mode register

b7 b0 Symbol Address When reset
G2MR 016A16 00XXX0002

Bit
symbol Bit name Function R W
b1 b0
GMD0 0 0 : Communication part is reset
Communication mode (Overrun error flag is cleared)
select bit 0 1 : Serial I/O mode
GMD1 1 0 : Special communication mode
1 1 : HDLC data process mode
Internal/external clock 0 : Internal clock (Note 2)
CKDIR
select bit 1 : External clock (Note 3)

Nothing is assigned. When write, set "0".

When read, their contents are indeterminate.

Transfer direction 0 : LSB first

UFORM
select bit 1 : MSB first

Transmit interrupt 0 : Transmit buffer is empty

IRS
cause select bit 1 : Transmit is completed

Note 1: Intelligent I/O group 2 has IE bus communication function as special communication function.
Note 2: Select a pin for clock output by setting the waveform generation control register, input function select
register, and function select registers A, B and C. Data transmission pins are the same as clock
output pins.
Note 3: Select which pins will input the clock with the input function select register and set those pins to the
input port using function select register A. Data input pins are the same as with clock input pins.

Group 2 SI/O communication control register

b7 b0 Symbol Address When reset
G2CR 016B16 0000 X0002

Bit
symbol Bit name Function R W

0 : Transmission disabled
TE Transmit enable bit
1 : Transmission enabled

0 : Data present in transmit register

Transmit register (during transmission)
TXEPT
empty flag 1 : No data present in transmit register
(transmission completed)

Transmit buffer 0 : Data present in transmit buffer register

TI
empty flag 1 : No data present in transmit buffer register

Nothing is assigned. When write, set to "0".

When read, the contents is indeterminate.

0 : Reception disabled
RE Receive enable bit
1 : Reception enabled

Receive complete 0 : No data present in receive buffer register

RI
flag 1 : Data present in receive buffer register

TxD output polarity 0 : No reverse (Usually set to "0")

OPOL
reverse select bit 1 : Reverse

RxD input polarity 0 : No reverse (Usually set to "0")

IPOL
reverse select bit 1 : Reverse

Figure 1. 23. 37. Group 2 Intelligent I/O-related register (4)

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Intelligent I/O (Serial I/O)

• Clock synchronous serial I/O mode (group 2)

Table 1.23.17 gives specifications for the group 2 clock synchronous serial I/O mode.

Table 1.23.17. Specifications of clock synchronous serial I/O mode

Item Specification
Transfer data format • Transfer data length: Variable length (group2)
Transfer clock • When internal clock is selected, the transfer clock in the single waveform output
mode is generated.
_ Transfer speed is determined when the base timer is reset by the ch0 WG function
Transfer rate (bps) = base timer count source (frequency) / (k+2)
k : values set to WG register 0
_ Transfer clock is generated by ch2 single phase WG function
Ch3 WG register = (k+2)/2 (Note 1)
• When external clock is selected
_ Transfer rate (bps) = Clock input to ISCLK pin (Note 2)
Transmission start condition • To start transmission, the following requirements must be met:
_ Transmit enable bit = “1”

_ Write data to SI/O transmit buffer register

Reception start condition • To start reception, the following requirements must be met:
_ Receive enable bit = “1”
_ Transmit enable bit = “1”
_ Write data to SI/O transmit buffer register
Interrupt request • When transmitting
_ When SI/O communication buffer register is empty, transmit interrupt cause select
generation timing
bit = “0”
_ When transmission is completed, transmit interrupt cause select bit = “1”
• When receiving
_ When data is transferred to SI/O receive buffer register
Error detection • Overrun error
This error occurs when the next data is ready before the contents of SI/O receive
buffer register are read out
Select function • LSB first/MSB first selection
When transmission/reception begins with bit 0 or bit 7, it can be selected.
• Transmit/receive data polarity switching
_ This function is reversing ISTxD pin output and ISRxD pin input.

(All I/O data level is reversed.)

• Data transfer bit length
_ Transmission data length can be set between 1 to 8 bits
Note 1: When the transfer clock and transfer data are transmission, transfer clock is set to at least 6 divi-
sions of the base timer clock. Except this, transfer clock is set to at least 20 divisions of the base
timer clock.
Note 2: Transfer clock is set to at least 20 divisions of the base timer clock.

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Base timer resets using

ch0 WG function

k+2
Base timer
t

Writes data to the transmit register Writes data to the transmit register
(8 bits) (4 bits)

Transmit/Receive clock
using ch2 WG function

First writing to
bit 0 bit 1 bit 2 bit 6 bit 7
the transmit buffer

Second writing to
bit 8 bit 9 bit 10 bit 11
the transmit buffer

Receive data bit 0 bit 1 bit 2 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11

Transfer to the receive register Transfer to the receive register

t : Values set to ch2 WG register

Values set to ch3 WG register

Figure 1. 23. 38. Typical transmit/receive timings in clock synchronous serial I/O mode in group 2

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A-D Converter

A-D Converter
The A-D converter consists of two 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P100 to P107, P150 to P157, P00 to P07, P20 to P27, P95, and P96 are shared as the
analog signal input pins. Pins P150 to P157, P00 to P07 and P20 to P27 can be used as the analog signal
input pins and switched by analog input port select bit. However, P00 to P07 and P20 to P27 can be used in
single chip mode. Set input to direction register corresponding to a pin doing A-D conversion.
The result of A-D conversion is stored in the A-D registers of the selected pins.
Table 1.24.1 shows the performance of the A-D converter. Figure 1.24.1 shows the block diagram of the
A-D converter, and Figures 1.24.2 to 1.24.7 show the A-D converter-related registers.

This section is described to 144-pin version as example.

In 100-pin version, AN10 to AN17 cannot be selected because there is no P15.

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A-D Converter

AN20
000
AN21
ADiCON2 : 001
TRG1, TRG0 AN22
010
ADTRG AN23
011
TB2INT EX TRGi P2
AN24
100
IIOG2 ch1 INT (i=0) ADiCON0 :
TRG AN25
or 101
IIOG3 ch1 INT (i=1) AN26
110
AN27
111

000
AN00

001
AN01

010
AN02
AD0CON1 :
OPA0, OPA1 011
AN03
AN04 P0
100
P96 ANEX1 AN05
X1 101

P95 ANEX0 110

AN06
1X 11 01
111
AN07

AN0 AN150
000 000
AN1 AD1CON2 : 11 AN151
001 APS1, APS0 10 001
AN2 00 AN152
010 010
01
AN3 AN153
011 011
00
P10 AN4
100
0 1 0 1
100
AN154 P15
AN5 AD0CON2 : ADS AN155
101 101
AN6 AN156
110 110
AD0CON0 : AD1CON0 :
AN7 AN157
111 CH2, CH1, CH0 CH2, CH1, CH0 111

Address Comparator 0 Comparator 1 Address

(038116, 038016) A-D0 register 0 A-D1 register 0 (01C116, 01C016)
(038316, 038216) A-D0 register 1 A-D1 register 1 (01C316, 01C216)
(038516, 038416) A-D0 register 2 A-D1 register 2 (01C516, 01C416)
Decoder

Decoder

(038716, 038616) A-D0 register 3 A-D1 register 3 (01C716, 01C616)

(038916, 038816) A-D0 register 4 A-D1 register 4 (01C916, 01C816)
(038B16, 038A16) A-D0 register 5 A-D1 register 5 (01CB16, 01CA16)
(038D16, 038C16) A-D0 register 6 A-D1 register 6 (01CD16, 01CC16)
(038F16, 038E16) A-D0 register 7 A-D1 register 7 (01CF16, 01CE16)

AD0 control register 0 Successive AD1 control register 0

Successive
(address 039616) conversion register conversion register (address 01D616)

Resister ladder Resister ladder

AD0 control register 1 AD1 control register 1

(address 039716) (address 01D716)

1 1
1/3 1 1/3 1
0 0
ØAD0 ØAD1
0 0
1 1
fAD 1/2 1/2 fAD 1/2 1/2
0 0

AD0CON0 : CSK0 AD1CON0 : CSK0

AD0CON1 : CSK1 AD1CON1 : CSK1

Figure 1.24.1. Block diagram of A-D converter

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A-D Converter

Table 1.24.1. Performance of A-D converter

Item Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock ØAD (Note 2) fAD, fAD/2, fAD/3 , fAD/4 fAD=f(XIN)
Resolution 8-bit or 10-bit (selectable)
Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins 34 pins
AN, AN0, AN2, AN15(Note 3) each 8 pins
Extended input 2 pins (ANEX0(Note 4) and ANEX1(Note 5))
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts by outbreak of the following factors chosen among in three
(Note 6)

· ADTRG/P97 input changes from “H” to “L”

· Timer B2 interrupt occurrences frequency counter overflow
· Interrupt of Intelligent I/O group 2 or 3 channel 1
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 ØAD cycles
10-bit resolution: 59 ØAD cycles
• With sample and hold function
8-bit resolution: 28 ØAD cycles
10-bit resolution: 33 ØAD cycles

Note 1: Does not depend on use of sample and hold function.

Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing.
Without sample and hold function, set the fAD frequency to 250kHz or more.
With the sample and hold function, set the fAD frequency to 1MHz or more.
Note 3: When port P15 is used as analog input port, port P15 input peripheral function select bit (bit 2 of address
017816) must set to be "1".
Note 4: When port P95 is used as analog input port, port P95 output peripheral function select bit (bit 5 of address
03B716) must set to be "1".
Note 5: When port P96 is used as analog input port, port P96 output peripheral function select bit (bit 6 of address
03B716) must set to be "1".
Note 6: Set the port direction register to input.

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A-D Converter

A-D0 control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
AD0CON0 039616 0016

Bit Bit name Function

symbol R W
b2 b1 b0
CH0 0 0 0 : AN0
0 0 1 : AN1
0 1 0 : AN2
Analog input pin
CH1 0 1 1 : AN3 (Note 2, 3)
select bit 1 0 0 : AN4
1 0 1 : AN5
CH2 1 1 0 : AN6
1 1 1 : AN7
b4 b3
MD0 0 0 : One-shot mode
A-D operation 0 1 : Repeat mode
1 0 : Single sweep mode (Note 2)
mode select bit 0
MD1 1 1 : Repeat sweep mode 0
Repeat sweep mode 1
0 : Software trigger
TRG Trigger select bit
1 : External trigger (Note 4)

A-D conversion 0 : A-D conversion disabled

ADST start flag 1 : A-D conversion started (Note 5)

Frequency select 0 : fAD/3 or fAD/4 is selected

CKS0 bit (Note 6) 1 : fAD/1 or fAD/2 is selected

Note 1: If the A-D0 control register 0 is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Note 3: This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1.
Note 4: External trigger request cause can be selected in external trigger request cause select bit (bit5
and bit 6 of address 039416).
Note 5: When External trigger is selected, set to "1" after selecting the external trigger request cause
using the external trigger request cause select bit.
Note 6: When f(XIN) is over 10 MHz, the AD frequency must be under 10 MHz by dividing.

Figure 1.24.2. A-D converter-related registers (1)

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A-D Converter

A-D0 control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
AD0CON1 039716 0016

Bit Bit name Function

symbol R W
b0 b1
SCAN0 0 0 : ANj0, ANj1 (ANj0)
A-D sweep pin
0 1 : ANj0 to ANj3 (ANj0, ANj1) (Note 2, 3)
select bit
1 0 : ANj0 to ANj5 (ANj0 to ANj2)
SCAN1
1 1 : ANj0 to ANj7 (ANj0 to ANj3)

A-D operation 0 : Any mode other than repeat sweep mode 1

MD2 mode select bit 1 1 : Repeat sweep mode 1

8/10-bit mode 0 : 8-bit mode

BITS
select bit 1 : 10-bit mode
Frequency select 0 : fAD/2 or fAD/4 is selected
CKS1 bit
(Note 3) 1 : fAD/1 or fAD/3 is selected
0 : VREF not connectec
VCUT VREF connect bit
1 : VREF connectec

b6 b7
OPA0 External op-amp 0 0 : ANEX0 and ANEX1 are not used (Note 5)
connection mode 0 1 : ANEX0 input is A-D converted (Note 6)
bit 1 0 : ANEX1 input is A-D converted (Note 7)
OPA1 (Note 4) 1 1 : External op-amp connection mode (Note 8)

Note 1: If the A-D0 control register 1 is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: This bit is invalid in One-shot mode and Repeat mode. Channel shown in the parentheses,
becomes valid when repeat sweep mode 1(bit2="1") is selected.
Note 3: When f(XIN) is over 10 MHz, the AD frequency must be under 10 MHz by dividing.

Note 4: In single sweep mode and repeat sweep mode 0, 1, bit 7 and bit 6 cannot be set "01" and "10".
Note 5: When this bit is set, set "00" to bit6 and bit5 of function select register B3.
Note 6: When this bit is set, set "1" to bit5 of function select register B3.
Note 7: When this bit is set, set "1" to bit6 of function select register B3.
Note 8: When this bit is set, set "11" to bit6 and bit5 of function select register B3.

Figure 1.24.3. A-D converter-related registers (2)

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A-D Converter

A-D0 control register 2 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 0 0 AD0CON2 039416 X000 00002

Bit
Symbol Bit name Function R W

A-D conversion 0 : Without sample and hold

SMP
method select bit 1 : With sample and hold

Reserved bit Must always set to "0"

A-D Channel replace 0 : Channel replace is invalid

ADS
select bit (Note 2) 1 : Channel replace is valid
b6 b5
0 0 : ADTRG is selected
TRG0 0 1 : Timer B2 interrupt occurrence
External trigger
frequency counter overflow is
request cause selected (Note 3)
select bit 1 0 : Group 2 channel 1 interrupt is
TRG1 selected
1 1 : Must not be set
Simultaneous start bit 0 : Invalid
PST
(Note 4) (Note 5) (Note 6) 1 : 2 circuit A-D simultaneous start

Note 1: If the A-D0 control register 2 is rewritten during A-D conversion, the conversion result is indeterminate
Note 2: When the A-D circuit of either of A-D0 and A-D1 are operated, do not write "1" to this bit.
Note 3: This bit is valid when software trigger is selected.
Note 4: When this bit read, the value is indeterminate.
Note 5: This is valid in three-phase PWM mode.
Note 6: Turn every setting of A-D0 and A-D1 into same, and start at the same time in sweep mode.

A-D0 register j (j=0 to 7)

b15 b8
(b7) (b0)b7 b0 Symbol Address When reset
AD0j(j=0 to 2) 038116,038016, 038316,038216, 038516,038416 indeterminate
AD0j(j=3 to 5) 038716,038616, 038916,038816, 038B16,038A16 indeterminate
AD0j(j=6,7) 038D16,038C16, 038F16,038E16 indeterminate

Function R W

Eight low-order bits of A-D conversion result

During 10-bit mode : Two high-order bits of A-D conversion result

During 8-bit mode : When read, their contents are indeterminate

Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.

Figure 1.24.4. A-D converter-related registers (3)

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A-D Converter

A-D1 control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
AD1CON0 01D616 0016

Bit Bit name Function

symbol R W
b2 b1 b0

CH0 0 0 0 : ANj0
0 0 1 : ANj1
0 1 0 : ANj2
Analog input pin 0 1 1 : ANj3
CH1 (Note 2, 3, 4)
select bit 1 0 0 : ANj4
1 0 1 : ANj5
CH2 1 1 0 : ANj6
1 1 1 : ANj7 (j=0, 2, 15)
b4 b3
MD0 0 0 : One-shot mode
A-D operation 0 1 : Repeat mode
mode select bit 0 1 0 : Single sweep mode (Note 2)
MD1 1 1 : Repeat sweep mode 0
Repeat sweep mode 1
0 : Software trigger
TRG Trigger select bit
1 : External trigger (Note 5, 6)

A-D conversion 0 : A-D conversion disabled

ADST
start flag 1 : A-D conversion started (Note 7)

Frequency select 0 : fAD/3 or fAD/4 is selected

CKS0 bit (Note 8) 1 : fAD/1 or fAD/2 is selected
Note 1: If the A-D1 control register 0 is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Note 3: This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1.
Note 4: j=0, 2, 15 is selected by analog input port select bits (bit1 and bit 2 of address 01D416).
Note 5: External trigger request cause can be selected in external trigger request cause select bit (bit5
and bit 6 of address 01D416).
Note 6: After selecting external trigger request cause, set to "1".
Note 7: When External trigger is selected, set to "1" after selecting the external trigger.
Note 8: When f(XIN) is over 10 MHz, the AD frequency must be under 10 MHz by dividing.

Figure 1.24.5. A-D converter-related registers (4)

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A-D Converter

A-D1 control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
AD1CON1 01D716 XX0000002

Bit Bit name Function

symbol R W

b1 b0
SCAN0 0 0 : ANj0,ANj1 (ANj0)
A-D sweep pin 0 1 : ANj0 to ANj3 (ANj0,ANj1) (Note 2, 3)
select bit 1 0 : ANj0 to ANj5 (ANj0 to ANj2)
SCAN1
1 1 : ANj0 to ANj7 (ANj0 to ANj3) (j=0, 2, 15)

A-D operation 0 : Any mode except repeat sweep mode 1

MD2
mode select bit 1 1 : Repeat sweep mode 1

8/10-bit mode 0 : 8-bit mode

BITS
select bit 1 : 10-bit mode

Frequency select 0 : fAD/2 or fAD/4 is selected

CKS1
bit (Note 4) 1 : fAD/1 or fAD/3 is selected

0 : VREF not connectec

VCUT VREF connect bit
1 : VREF connectec

Nothing is assigned.
When write, set to "0". When read,
their contents are indeterminate.

Note 1: If the A-D1 control register 1 is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: This bit is invalid in one-shot mode and repeat mode. Channel shown in the parentheses,
becomes valid when repeat sweep mode 1(bit 2 = "1") is selected.
Note 3: j=0, 2, 15 is selected by analog input port select bits (bit1 and bit 2 of address 01D416).
Note 4: When f(XIN) is over 10 MHz, the AD frequency must be under 10 MHz by dividing.

Figure 1.24.6. A-D converter-related registers (5)

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A-D Converter

A-D1 control register 2 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
AD1CON2 01D416 X00XX0002

Bit
Symbol Bit name Bit name R W

A-D conversion 0 : Without sample and hold

SMP
method select bit 1 : With sample and hold
b2 b1
APS0 0 0 : P15
Analog input port 0 1 : Must not be set
select bit 1 0 : P0
APS1 1 1 : P2

Nothing is assigned.
When write, set to "0". When read, their contents are
indeterminate.

b6 b5

TRG0 External trigger 0 0 : ADTRG is selected

request cause 0 1 : Timer B2 interrupt occurrence
frequency counter overflow is
select bit
selected (Note 2)
1 0 : Group 3 channel 1 interrupt is
TRG1 selected
1 1 : Must not be set

Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.

Note 1: If the A-D1 control register 2 is rewritten during A-D conversion, the conversion.
Note 2: This is valid in three-phase PWM mode.

A-D1 register j (j=0 to 7)

b15 b8
(b7) (b0)b7 b0 Symbol Address When reset
AD1j(j=0 to 2) 01C116,01C016, 01C316,01C216, 01C516,01C416 indeterminate
AD1j(j=3 to 5) 01C716,01C616, 01C916,01C816, 01CB16,01CA16 indeterminate
AD1j(j=6,7) 01CD16,01CC16, 01CF16,01CE16 indeterminate

Function R W

Eight low-order bits of A-D conversion result

During 10-bit mode : Two high-order bits of A-D conversion result

During 8-bit mode : When read, their contents are indeterminate

Nothing is assigned.
When write, set to "0". When read, their contents are indeterminate.

Figure 1.24.7. A-D converter-related registers (6)

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A-D Converter

(1) One-shot mode

In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. Table 1.24.2 shows the specifications of one-shot mode.

Table 1.24.2. One-shot mode specifications

Item Specification
Function The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition Writing “1” to A-Di conversion start flag, external trigger
Stop condition • End of A-Di conversion (A-Di conversion start flag changes to “0”, except when
external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin One of ANj0 to ANj7 (j =non, 0, 2, 15), ANEX0, ANEX1
Reading of result of A-D converter Read A-D register corresponding to selected pin

(2) Repeat mode

In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
Table 1.24.3 shows the A-D control register in repeat mode.

Table 1.24.3. Repeat mode specifications

Item Specification
Function The pin selected by the analog input pin select bit is used for repeated A-D con-
version
Start condition Writing “1” to A-D conversion start flag, external trigger
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin One of ANj0 to ANj7 (j =non, 0, 2, 15), ANEX0, ANEX1
Reading of result of A-D converter Read A-D register corresponding to selected pin

(3) Single sweep mode

In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 1.24.4 shows the A-D control register in single sweep mode.

Table 1.24.4. Single sweep mode specifications

Item Specification
Function The pins selected by the A-Di sweep pin select bit are used for one-by-one
A-D conversion
Start condition Writing “1” to A-D converter start flag, external trigger
Stop condition • End of A-Di conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-Di conversion start flag
Interrupt request generation timing End of sweep
Input pin ANj0 and ANj1 (2 pins), ANj0 to ANj3 (4 pins), ANj0 to ANj5 (6 pins), or ANj0 to ANj7
(8 pins) (j =non, 0, 2, 15)
Reading of result of A-D converter Read A-D register corresponding to selected pin

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A-D Converter

(4) Repeat sweep mode 0

In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 1.24.5 shows the specifications of repeat sweep mode 0.

Table 1.24.5. Repeat sweep mode 0 specifications

Item Specification
Function The pins selected by the A-D sweep pin select bit are used for repeat sweep
A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin ANj0 and ANj1 (2 pins), ANj0 to ANj3 (4 pins), ANj0 to ANj5 (6 pins), or ANj0 to AN7
(8 pins) (j =non, 0, 2, 15)
Reading of result of A-D converter Read A-D register corresponding to selected pin

(5) Repeat sweep mode 1

In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 1.26.6 shows the specifications of repeat sweep mode 1.

Table 1.26.6. Repeat sweep mode 1 specifications

Item Specification
Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins
selected by the A-D sweep pin select bit
Example : AN0 selected
ANj0 ANj1 ANj0 ANj2 ANj0 ANj3 etc. (j =non, 0, 2, 15)
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin ANj0 to ANj7 (j =non, 0, 2, 15)
With emphasis on the pin ANj0 (1 pin), ANj0 and ANj1 (2 pins), ANj0 to ANj2 (3 pins), ANj0 to ANj3 (4 pins) (j
=non, 0, 2, 15)
Reading of result of A-D converter Read A-D register corresponding to selected pin

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A-D Converter

(a) Resolution select function

8/10-bit mode select bit of A-D control register 1 (bit 3 at address 039716, 01D716)
When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd
addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses.

(b) Sample and hold

Sample and hold are selected by setting bit 0 of the A-D control register 2 (address 039416, 01D416) to
“1”. When sample and hold are selected, the rate of conversion of each pin increases. As a result, a 28
ØAD cycle is achieved with 8-bit resolution and 33 ØAD with 10-bit resolution. Sample and hold can be
selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether
sample and hold are to be used.

(c) Trigger select function

Can appoint start of conversion, by a combination of setting of trigger select bit (bit 5 at address 039616,
01D616) and external trigger request cause select bit (bit 5 and bit 6 at address 039416, 01D416), as
follows.

Table 1.24.7. Trigger select function setting

Trigger select bit="1"

Trigger select bit="0" External trigger cause select bits

00 01 10

A-D0 Software trigger ADTRG Timer B2 OFCOI(Note) Group 2 channel 1 interrupt

A-D1 Software trigger ADTRG Timer B2 OFCOI(Note) Group 3 channel 1 interrupt

Timer B2 OFCOI : Timer B2 occurrence frequency counter overflow interrupt

Note :Valid in three-phase PWM mode.

(d) Two circuit same time start (software trigger)

Two A-D converters can start at the same time by setting simultaneous start bit (bit 7 of address 039416)
to “1”.
During the A-D circuit of either of A-D0 and A-D1 are operated, do not set “1” to the simultaneous start bit.
Do not set to "1" when external trigger is selected. When using this bit, do not set A-D conversion start
flag (bit 6 of address 039616, 01D616) to "1".

(e) Replace function of input pin

Setting "1" to A-D channel replace select bit of A-D0 control register 2 (ADS:bit 4 at address 039416) can
replace channel of A-D0 and A-D1. A-D conversion reliability is confirmed by replacing channels.
When ADS bit is "1", a corresponding pin of A-D0 register i is selected by analog input port select bits of
A-D1 control register 2 (bits 2 and 1 at address 01D416). In this case, A-D0 control register 0 and A-D1
control register 0 must be set to same value.

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A-D Converter

Table 1.24.8. Setting of analog input port replace of A-D converter

Setting value A-D channel replace select bit 1

A-D conversion stored register Analog output port select bit 00 10 11

A-D0 register 0 AN150 AN00 AN20

A-D0 register 1 AN151 AN01 AN21

A-D0 register 2 AN152 AN02 AN22

A-D0 register 3 AN153 AN03 AN23

A-D0 register 4 AN154 AN04 AN24

A-D0 register 5 AN155 AN05 AN25

A-D0 register 6 AN156 AN06 AN26

A-D0 register 7 AN157 AN07 AN27

A-D1 register 0 AN0

A-D1 register 1 AN1

A-D1 register 2 AN2

A-D1 register 3 AN3

A-D1 register 4 AN4

A-D1 register 5 AN5

A-D1 register 6 AN6

A-D1 register 7 AN7

(f) Extended analog input pins

In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital as AN0 and AN1 analog input signal respectively.
Set the related input peripheral function of the function select register B3 to disabled.

(g) External operation amp connection mode

In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 and bit 7 of the A-D control register 1 (address 039716) is “11”, input via AN0 to AN7 is output
from ANEX0.
The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A-D
register. The speed of A-D conversion depends on the response of the external operation amp. Do not
connect the ANEX0 and ANEX1 pins directly. Figure 1.24.8 is an example of how to connect the pins in
external operation amp mode.
Set the related input peripheral function of the function select register B3 to disabled.

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A-D Converter

Table 1.24.9. Setting of extended analog input pins

A-D0 control register 1 ANEX0 function ANEX1 function

Bit 7 Bit 6

0 0 Not used Not used

0 1 P95 analog input Not used

1 0 Not used P96 analog input

1 1 Output to external ope-amp Input from external ope-amp

Resistance ladder

Successive conversion register

AN0
AN1
AN2
Analog AN3
input AN4
AN5
AN6
AN7

ANEX0

ANEX1
Comparator
External op-amp

Figure 1.24.8. Example of external op-amp connection mode

(h) Power consumption reduction function

VREF connect bit (bit 5 at addresses 039716, 01D716)
The VREF connect bit (bit 5 at address 039716, 01D716) can be used to isolate the resistance ladder of the
A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so
stops any current flowing into the resistance ladder from VREF, reducing the power dissipation.
When using the A-D converter, start A-D conversion only after connecting VREF.
Do not write A-D conversion start flag and VREF connect bit to “1” at the same time. Do not clear VREF
connect bit to “0” during A-D conversion. This VREF is without reference to D-A converter's VREF.

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A-D Converter

Precaution
After A-D conversion is complete, if the CPU reads the A-D register at the same time as the A-D conver-
sion result is being saved to A-D register, wrong A-D conversion value is saved into the A-D register. This
happens when the internal CPU clock is selected from divided main clock or sub-clock.

• When using the one-shot or single sweep mode

Confirm that A-D conversion is complete before reading the A-D register.
(Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.)

• When using the repeat mode or repeat sweep mode 0 or 1

Use the undivided main clock as the internal CPU clock.

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D-A Conversion

D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of
this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Set the
function select register A3 to I/O port, the related input peripheral function of the function select register B3
to disabled and the direction register to input mode. Do not set the target port to pulled-up when D-A output
is enabled.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage (This is unrelated to bit 5 of A-D control register 1 (addresses 039716, 01D716)
Table 1.25.1 lists the performance of the D-A converter. Figure 1.25.1 shows the block diagram of the D-A
converter. Figure 1.25.2 shows the D-A control register. Figure 1.25.3 shows the D-A converter equivalent
circuit.
When the D-A converter is not used, set the D-A register to "00" and D-A output enable bit to "0".
Table 1.25.1. Performance of D-A converter
Item Performance
Conversion method R-2R method
Resolution 8 bits
Analog output pin 2 channels

Data bus low-order bits

A
D-A register i (8) (i = 0, 1) (Address 039816, 039A16)

R-2R resistance ladder

AAAAAA
D-Ai output enable bit (i = 0, 1)

AAAAAA
P93 / DA0
P94 / DA1

Figure 1.25.1. Block diagram of D-A converter

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D-A Conversion

D-A control register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
DACON 039C16 XXXXXX002

Bit
symbol Bit name Function R W

0 : Output disabled
DA0E D-A0 output enable bit
1 : Output enabled

0 : Output disabled
DA1E D-A1 output enable bit
1 : Output enabled

Nothing is assigned.
When write, set to "0". When read, their contents are "0".

D-A register i
b7 b0 Symbol Address When reset
DAi(i=0,1) 039816, 039A16 Indeterminate

Function Setting range R W

Output value of D-A conversion 0016 to FF16

Figure 1.25.2. D-A control register

D-A0 output enable bit

R "0" R R R R R R R 2R
DA0
"1"
2R 2R 2R 2R 2R 2R 2R 2R
MSB LSB

D-A register 0
"0" "1"
AVSS
VREF

Note 1: In the above figure, the D-A register value is "2A16".

Note 2: This circuit is the same in D-A1.
Note 3: To save power dissipation when not using the D-A converter, set the D-A output enable bit to
"0" and the D-A register to "0016", and prevent current flowing to the R-2R resistance.

Figure 1.25.3. D-A converter equivalent circuit

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CRC

CRC Calculation Circuit

The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom-
puter uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com-
pleted in two machine cycles.
Figure 1.26.1 shows the block diagram of the CRC circuit. Figure 1.26.2 shows the CRC-related registers.
Figure 1.26.3 shows the CRC example.

Data bus high-order bits

AAAAA AAAAAA
Data bus low-order bits

AAAAAAAAAA
AAAAA AAAAAA
Eight low-order bits Eight high-order bits

AAAAAAAAAA
AAAAAAAAAA
CRC data register (16)
(Addresses 037D16, 037C16)

AAAAAAAAAA
AAAAAAAAAA
CRC code generating circuit
x16 + x12 + x5 + 1

AAAAA
AAAAA
CRC input register (8) (Address 037E16)

Figure 1.26.1. Block diagram of CRC circuit

CRC data register

b15 b8
(b7) (b0) b7 b0 Symbol Address When reset
CRCD 037D16, 037C16 Indeterminate

Function Setting range R W

CRC calculation output register 000016 to FFFF16

CRC input register

b7 b0 Symbol Address When reset
CRCIN 037E16 Indeterminate

Function Setting range R W

Data input register 0016 to FF16

Figure 1.26.2. CRC-related registers

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CRC

b15 b0
CRC data register CRCD
(1) Setting 000016
[037D16, 037C16]

b7 b0

(2) Setting 0116 CRC input register CRCIN

[037E16]

2 cycles
After CRC calculation is complete
b15 b0
118916 CRC data register CRCD
[037D16, 037C16]

Stores CRC code

The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
(X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.

LSB
MSB Modulo-2 operation is
1000 1000 operation that complies
1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 with the law given below.
1000 1000 0001 0000 1 0+0=0
1000 0001 0000 1000 0 0+1=1
1000 1000 0001 0000 1 1+0=1
1001 0001 1000 1000 1+1=0
LSB MSB -1 = 1

9 8 1 1

Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M32C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.

b7 b0
CRC input register CRCIN
(3) Setting 2316
[037E16]

After CRC calculation is complete

b15 b0

0A4116 CRC data register CRCD

[037D16, 037C16]

Stores CRC code

Figure 1.26.3. CRC example

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X-Y Converter

X-Y Converter
X-Y conversion rotates the 16 x 16 matrix data by 90 degrees. It can also be used to invert the top and
bottom of the 16-bit data. Figure 1.27.1 shows the XY control register.
The Xi and the Yi registers are 16-bit registers. There are 16 of each (where i= 0 to 15).
The Xi and Yi registers are mapped to the same address. The Xi register is a write-only register, while the
Yi register is a read-only register. Be sure to access the Xi and Yi registers in 16-bit units from an even
address. Operation cannot be guaranteed if you attempt to access these registers in 8-bit units.

XY control register
b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
XYC 02E016 XXXXXX002

Bit
symbol Bit name Function R W

Read-mode set bit 0 : Data conversion

XYC0
1 : No data conversion

Write-mode set bit 0 : No bit mapping conversion

XYC1
1 : Bit mapping conversion

Noting is assigned. When write, set to "0".

When read, their contents are indeterminate.

Figure 1.27.1. XY control register

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X-Y Converter

The reading of the Yi register is controlled by the read-mode set bit (bit 0 at address 02E016).
When the read-mode set bit (bit 0 at address 02E016) is “0”, specific bits in the Xi register can be read at the
same time as the Yi register is read.
For example, when you read the Y0 register, bit 0 is read as bit 0 of the X0 register, bit 1 is read as bit 0 of
the X1 register, ..., bit 14 is read as bit 0 of the X14 register, bit 15 as bit 0 of the X15 register. Similarly,
when you read the Y15 register, bit 0 is bit 15 of the X0 register, bit 1 is bit 15 of the X1 register, ..., bit 14 is
bit 15 of the X14 register, bit 15 is bit 15 of the X15 register.
Figure 1.27.2 shows the conversion table when the read mode set bit = “0”. Figure 1.27.3 shows the X-Y
conversion example.

Read address

Y14 register (0002DC16)

Y15 register (0002DE16)

Y13 register (0002DA16)

Y10 register (0002D416)

Y12 register (0002D816)
Y11 register (0002D616)

Y6 register (0002CC16)
Y7 register (0002CE16)

Y5 register (0002CA16)
Y9 register (0002D216)
Y8 register (0002D016)

Y4 register (0002C816)
Y3 register (0002C616)
Y2 register (0002C416)
Y1 register (0002C216)
Y0 register (0002C016)
AA
AA
A
AA AA
A
AAA
A AAAA
A
AA
A AA
AAA
A
AA
AAA
A AA
A
AA
A
b15
X15 register (0002DE16)
X14 register (0002DC16)

AA
AA
A AA
A AA
A AA
AAA
A AA
A
X13 register (0002DA16)
X12 register (0002D816)
X11 register (0002D616)

AA
AA
A AA
A AA
A AA
AAA
A AA
A
X10 register (0002D416)
X9 register (0002D216)

Bit of Yi register
AA
AA
A AA
A AA
A AA
AAA
A AA
A
Write address X8 register (0002D016)
X7 register (0002CE16)
X6 register (0002CC16)

AA
AA
A AA
A AA
A AA
AAA
A AA
A
X5 register (0002CA16)
X4 register (0002C816)
X3 register (0002C616)

AA
AAA
A AAAA
A AA
AAA
A AA
A
X2 register (0002C416)
X1 register (0002C216)
b0

X0 register (0002C016)
b15 b0
Bit of Xi register

Figure 1.27.2. Conversion table when the read mode set bit = “0”

(X register) (Y register)
b14

b10
b13

b10
b13
b12
b15

b12
b11

b15

b11
b14
b7

b0
b3
b6

b3
b9

b2

b6
b5

b9

b2
b8

b1

b5
b4

b8

b1
b4
b7

b0

AAAAAAAA
X0-Reg Y0-Reg

A AA
X1 Y1

A AA
X2 Y2
X3 Y3
X4
X5
Y4
Y5 A A
AA
A
X6 Y6

AAAA
X7 Y7

AA
X8 Y8
X9 Y9
X10
X11
Y10
Y11 AA
AA
A
A
X12 Y12

A
X13 Y13
X14 Y14
X15 Y15

Figure 1.27.3. X-Y conversion example

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X-Y Converter

When the read-mode set bit (bit 0 at address 02E016) is “1”, you can read the value written to the Xi register
by reading the Yi register. Figure 1.27.4 shows the conversion table when the read mode set bit = “1”.

AA
AA
A AA
AAA
AAA
A AA
A AA
A A
AA
AA
A
X15,Y15 register (0002DE16)

AA
AA
A
X14,Y14 register (0002DC16)
X13,Y13 register (0002DA16)
X12,Y12 register (0002D816)
AA
AAA
A
AA
A AA
A
AA
AAA
A AA
A
AA
A AA
A
AA
A A
A
AA
AA
A AA
AAA
AAA
A AA
A AA
A A
X11,Y11 register (0002D616)
X10,Y10 register (0002D416)
X9,Y9 register (0002D216)

AA
AA
A AA
AAA
AAA
A AA
A AA
A A
Write address X8,Y8 register (0002D016)
Read address X7,Y7 register (0002CE16)

AA
AA
A AA
AAA
AAA
A AA
A AA
A A
X6,Y6 register (0002CC16)
X5,Y5 register (0002CA16)
X4,Y4 register (0002C816)

AA
AA
A AA
AAA
AAA
A AA
A AA
A A
X3,Y3 register (0002C616)
X2,Y2 register (0002C416)
X1,Y1 register (0002C216)
X0,Y0 register (0002C016)
b15 b0
Bit of Xi register
Bit of Yi register

Figure 1.27.4. Conversion table when the read mode set bit = “1”

The value written to the Xi register is controlled by the write mode set bit (bit 1 at address 02E016).
When the write mode set bit (bit 1 at address 02E016) is “0” and data is written to the Xi register, the bit
stream is written directly.
When the write mode set bit (bit 1 at address 02E016) is “1” and data is written to the Xi register, the bit
sequence is reversed so that the high becomes low and vice versa. Figure 1.27.5 shows the conversion
table when the write mode set bit = “1”.

b15 b0
Write address

b15 b0
Bit of Xi register

Figure 1.27.5. Conversion table when the write mode set bit = “1”

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DRAM Controller

DRAM Controller
There is a built in DRAM controller to which it is possible to connect between 512 Kbytes and 8 Mbytes of
DRAM. Table 1.28.1 shows the functions of the DRAM controller.
Table 1.28.1. DRAM Controller Functions
DRAM space 512KB, 1MB, 2MB, 4MB, 8MB
Bus control 2CAS/1W
________ ________
Refresh CAS before RAS refresh, Self refresh-compatible
Function modes EDO-compatible, fast page mode-compatible
Waits 1 wait or 2 waits, programmable

To use the DRAM controller, use the DRAM space select bit of the DRAM control register (address 004016)
to specify the DRAM size. Figure 1.28.1 shows the DRAM control register.
The DRAM controller cannot be used in external memory mode 3 (bits 1 and 2 at address 000516 are “112”).
Always use the DRAM controller in external memory modes 0, 1, or 2.
When the data bus width is 16-bit in DRAM area, set "1" to R/W mode select bit (bit 2 at address 000416).
Set wait time between after DRAM power ON and before memory processing, and processing necessary
for dummy cycle to refresh DRAM by software.

DRAM Control register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
DRAMCONT 004016 Indeterminate (Note 1)

Bit Bit name Function

symbol R W

Wait select bit 0 : Two wait

WT (Note 2) 1 : One wait
b3 b2 b1
0 0 0 : DRAM ignored
AR0
0 0 1 : Must not be set
0 1 0 : 0.5MB
AR1 DRAM space select bit 0 1 1 : 1MB
1 0 0 : 2MB
1 0 1 : 4MB
1 1 0 : 8MB
AR2
1 1 1 : Must not be set

Nothing is assigned. When write, set to "0".

When read, their contents are indeterminate.

Self-refresh mode bit 0 : Self-refresh OFF

SREF (Note 3) 1 : Self-refresh ON

Note 1: After reset, the content of this register is indeterminate. DRAM controller starts operation after
writing to this register.
Note 2: The number of cycles with 2 waits is 3-2-2. With 1 wait, it is 2-1-1.
Note 3: When you set to "1", both RAS and CAS change to "L". When you set to "0", RAS and CAS
change to "H" and then normal operation (read/write, refresh) is resumed. In stop mode, there is
no control.
Note 4: Set the bus width using the external data bus width control register (address 000B16). When
selecting 8-bit bus width, CASH is indeterminate.

Figure 1.28.1. DRAM control register

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DRAM Controller

• DRAM Controller Multiplex Address Output

The DRAM controller outputs the row addresses and column addresses as a multiplexed signal to the
address bus A8 to A20. Figure 1.28.2 shows the output format for multiplexed addresses.

8-bit bus mode

MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
Pin function (A20) (A19) (A18) (A17) (A16) (A9)
(A15) (A14) (A13) (A12) (A11) (A10) (A8)

Row address (A20) (A19) A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 –

Column address (A22) (A22) A19 A8 A7 A6 A5 A4 A3 A2 A1 A0 –

512KB, 1MB

Row address (A20) A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 –

Column address (A22) A21 A20 A8 A7 A6 A5 A4 A3 A2 A1 A0 –

2MB, 4MB

Row address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 –

Column address (A22) A22 A21 A8 A7 A6 A5 A4 A3 A2 A1 A0 –

8MB

16-bit bus mode

MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
Pin function (A20) (A19) (A18) (A17) (A16) (A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8)

Row address (A20) (A19) A18 A17 A16 A15 A14 A13 A12 A11 A10 (A9) –

Column address (A22) (A20) A9 A8 A7 A6 A5 A4 A3 A2 A1 (A0) –

512KB

Row address (A20) A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 (A9) –

(A22) A20 A9 A8 A7 A6 A5 A4 A3 A2 A1 (A0) –

Column address
1MB, 2MB

Row address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 (A9) –

Column address A22 A21 A9 A8 A7 A6 A5 A4 A3 A2 A1 (A0) –

4MB, 8MB (Note 2)

Note 1: ( ) invalid bit: bits that change according to selected mode (8-bit/16-bit bus mode, DRAM
space).
Note 2: The figure is for 4Mx1 or 4Mx4 memory configuration. If you are using a 4Mx16 configuration,
use combinations of the following: For row addresses, MA0 to MA12; for column addresses
MA2 to MA8, MA11, and MA12. Or for row addresses MA1 to MA12; for column addresses
MA2 to MA9, MA11, MA12.
Note 3: "–" is indetermimate.

Figure 1.28.2. Output format for multiplexed addresses

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DRAM Controller

• Refresh
_______ _______
The refresh method is CAS before RAS. The refresh interval is set by the DRAM refresh interval set
register (address 004116). The refresh signal is not output in HOLD state. Figure 1.28.3 shows the
DRAM refresh interval set register.
Use the following formula to determine the value to set in the refresh interval set register.

Refresh interval set register value (0 to 255) = refresh interval time / (BCLK frequency X 32) - 1

DRAM refresh interval set register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
REFCNT 004116 Indeterminate

Bit Bit name Function

symbol R W

b7 b6 b5 b4 b3 b2 b1 b0
REFCNT0 0 0 0 0 0 0 0 0 : 1.1 µs (Note)
0 0 0 0 0 0 0 1 : 2.1 µs
0 0 0 0 0 0 1 0 : 3.2 µs
REFCNT1

REFCNT2
1 1 1 1 1 1 1 1 : 272.8 µs

REFCNT3

Refresh interval set bit

REFCNT4

REFCNT5

REFCNT6

REFCNT7

Note. Refresh interval at 30 MHz operating (no division).

Refresh interval = BCLK frequency X (refresh interval set bit + 1) X 32

Figure 1.28.3. DRAM refresh interval set register

The DRAM self-refresh operates in STOP mode, etc.

When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction,
simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also, insert
two NOPs after the instruction that sets the self-refresh mode bit to "1".
Do not access external memory while operating in self-refresh. (All external memory space access is
inhibited. )
When disabling self-refresh, simultaneously select DRAM ignored by the DRAM space select bit and self-
refresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit.
Do not access the DRAM space immediately after setting the DRAM space select bit.

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DRAM Controller

Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit
Shifting to self-refresh
•••
mov.b #00000001b,DRAMCONT ;DRAM ignored, one wait is selected
mov.b #10001011b,DRAMCONT ;Set self-refresh, select 4MB and one wait
nop ;Two nops are needed
nop ;
•••

Disable self-refresh
•••
mov.b #00000001b,DRAMCONT ;Disable self-refresh, DRAM ignored, one wait is
;selected
mov.b #00001011b,DRAMCONT ;Select 4MB and one wait
nop ;Inhibit instruction to access DRAM area
nop
•••

Figures 1.28.4 to 1.28.6 show the bus timing during DRAM access.

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DRAM Controller

< Read cycle (wait control bit = 0) >

BCLK

MA0 to MA12 Row Column Column Column

address address 1 address 2 address 3

RAS

CASH
CASL
'H'

DW

D0 to D15
(EDO mode)

Note : Only CASL is operating in 8-bit data bus width.

< Write cycle (wait control bit = 0) >

BCLK

Row Column Column Column

MA0 to MA12 address address 1 address 2 address 3

RAS

CASH
CASL

DW

D0 to D15

Note : Only CASL is operating in 8-bit data bus width.

Figure 1.28.4. The bus timing during DRAM access (1)

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DRAM Controller

< Read cycle (wait control bit = 1) >

BCLK

Row Column Column Column Column

MA0 to MA12 address address 1 address 2 address 3 address 4

RAS

CASH
CASL

'H'
DW

D0 to D15
(EDO mode)

Note : Only CASL is operating in 8-bit data bus width.

< Write cycle (wait control bit = 1) >

BCLK

Row Column Column Column Column

MA0 to MA12 address address 1 address 2 address 3 address 4

RAS

CASH
CASL

DW

D0 to D15

Note : Only CASL is operating in 8-bit data bus width.

Figure 1.28.5. The bus timing during DRAM access (2)

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DRAM Controller

BCLK

RAS

CASH
CASL
"H"
DW

< CAS before RAS refresh cycle >

Note : Only CASL is operating in 8-bit data bus width.

BCLK

RAS

CASH
CASL

"H"
DW

< Self refresh cycle >

Note : Only CASL is operating in 8-bit data bus width.

Figure 1.28.6. The bus timing during DRAM access (3)

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Programmable I/O Port

Programmable I/O Ports

There are 123 programmable I/O ports in 144-pin version: P0 to P15 (excluding P85). There are 87 pro-
grammable I/O ports in 100-pin version: P0 to P10 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is
an input-only port and has no built-in pull-up resistance.
Figures 1.29.1 to 1.29.4 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), set the corresponding function select registers A, B and C. When pins are to be used as the outputs
for the D-A converter, set the function select register A3 of each pin to I/O port, and set the direction
registers to input mode.
See the descriptions of the respective functions for how to set up the built-in peripheral devices.

(1) Direction registers

Figurs 1.29.5 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding direction register of pins
_____ _______ _______ _______ _____ _________ _______ _______ _______ _____ _____
A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/
_________ _________ _______ _______
ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
Note: There is no direction register bit for P85.

(2) Port registers

Figure 1.29.6 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in a port register corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding port register of pins A0 to
_____ _______ _______ _______ _____ _________ _______ _______ _______ _____ _____
A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE/
_________ _________ _______ _______
CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.

(3) Function select register A

Figures 1.29.7 to 1.29.11 show the function select registers A.
The register is used to select port output and peripheral function output when the port functions for both
port output and peripheral function output.
Each bit of this register corresponds to each pin that functions for both port output and peripheral function
output.

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Programmable I/O Port

(4) Function select register B

Figures 1.29.12 and 1.29.13 show the function select registers B.
This register selects the first peripheral function output and second peripheral function output when mul-
tiple peripheral function outputs are assigned to a pin. For pins with a third peripheral function, this regis-
ter selects whether to enable the function select register C, or output the second peripheral function.
Each bit of this register corresponds to each pin that has multiple peripheral function outputs assigned to it.
This register is enabled when the bits of the corresponding function select register A are set for peripheral
functions.
The bit 3 to bit 6 of function select register B3 is ignored bit for input peripheral function. When using DA0/DA1
and ANEX0/ANEX1, set related bit to“1”. When not using DA0/DA1 or ANEX0/ANEX1, set related bit to “0”.

(5) Function select register C

Figure 1.29.14 shows the function select register C.
This register is used to select the first peripheral function output and the third peripheral function output
when three peripheral function outputs are assigned to a pin.
This register is effective when the bits of the function select register A of the counterpart pin have selected
a peripheral function and when the function select register B has made effective the function select
register C.
The bit 7 (PSC_7) is assigned the key-in interrupt inhibit bit. Setting “1” in the key-in interrupt inhibit bit
causes no key-in interrupts regardless of the settings in the interrupt control register even if “L” is entered
______ ______
in pins KI0 to KI3. With “1” set in the key-in interrupt inhibit bit, input from a port pin cannot be effected
even if the port direction register is set to input mode.

(6) Pull-up control registers

Figures 1.29.15 to 1.29.17 show the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode, do not set the
pull-up control register. However, it is possible to select pull-up resistance presence to the usable port as
I/O port by setting.

(7) Port control register

Figure 1.29.18 shows the port control register.
This register is used to choose whether to make port P1 a CMOS port or an Nch open drain. In the Nch
open drain, the CMOS port’s Pch is kept always turned off so that the port P1 cannot be a complete open
drain. Thus the absolute maximum rating of the input voltage falls within the range from “- 0.3 V to Vcc +
0.3 V”.
The port control register functions similarly to the above. Also in the case in which port P1 can be used as
a port when the bus width in the full external areas comprises 8 bits in either microprocessor mode or in
memory expansion mode.

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Programmable I/O ports

Pull-up selection

Direction register

Data bus Port latch

B
Input to respective peripheral functions

C
Analog signal

Option Circuit (B)

(A) Circuit (C)
Input to respective
Hysteresis presence Analog I/F
Port peripheral functions
P00 to P07
P20 to P27
P30 to P37
P40 to P47
P50 to P52
P54
P55
P56
P57
P83, P84
P86
P87
P100 to P103
P104 to P107
P114
P144 to P146
(Note)
P152, P153
P156, P157
: Present, : Not present
Note: These ports exist in 144-pin version.

Figure 1.29.1. Programmable I/O ports (1)

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Programmable I/O ports with port control register

Pull-up selection

Direction register

Port P1 control
register

Data bus Port latch

B
Input to respective peripheral functions

Option Circuit (B)

(A)
Input to respective
Hysteresis presence
Port peripheral functions
P10 to P14
P15 to P17

: Present, : Not present

Figure 1.29.2. Programmable I/O ports (2)

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Programmable I/O ports with function select register

Pull-up selection D

Function select (Note 1)

register A

Direction register

Output from each

peripheral function

Data bus Port latch

B
Input to respective peripheral functions

C
Analog signal

Option Circuit (B)

(A) Circuit (C)
Input to respective Circuit (D)
Hysteresis presence Analog I/F
Port peripheral functions

P53 (Note 1)
P60, P61
P63 to P65, P67
P70, P71 (Note 2)
P72 to P77
P80, P81
P82
P90 to P92
P93 to P96
P97
P110
P111, P112
P113
P120
P121, P122
P123 to P127
P130 to P134
(Note 3)
P135, P136
P137
P140, P141
P142, P143
P150, P151
P154, P155
: Present, : Not present
Note 1: P53 is clock output select bit for BCLK.
Note 2: P70 and P71 are N-channel open drain output.
Note 3: These ports exist in 144-pin version.

Figure 1.29.3. Programmable I/O ports (3)

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Input-only port

Data bus

NMI

Figure 1.29.4. Programmable I/O ports (4)

Port Pi direction register (Note 1, 2, 3)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
PDi(i=0 to 5) 03E216, 03E316, 03E616, 03E716, 03EA16, 03EB16 0016
PDi(i=6 to 11) 03C216, 03C316, 03C616, 03C716, 03CA16, 03CB16 0016
PDi(i=12 to 15) 03CE16, 03CF16, 03D216, 03D316 0016

Bit
Symbol Bit name Function R W

Port Pi0 direction 0 : Input mode (Functions as an input port)

PDi_0
register 1 : Output mode (Functions as an output port)

Port Pi1 direction 0 : Input mode (Functions as an input port)

PDi_1
register 1 : Output mode (Functions as an output port)

Port Pi2 direction 0 : Input mode (Functions as an input port)

PDi_2
register 1 : Output mode (Functions as an output port)

Port Pi3 direction 0 : Input mode (Functions as an input port)

PDi_3
register 1 : Output mode (Functions as an output port)

Port Pi4 direction 0 : Input mode (Functions as an input port)

PDi_4
register 1 : Output mode (Functions as an output port)

Port Pi5 direction 0 : Input mode (Functions as an input port)

PDi_5 1 : Output mode (Functions as an output port)
register
(Note 4)
Port Pi6 direction 0 : Input mode (Functions as an input port)
PDi_6 1 : Output mode (Functions as an output port)
register (Note 4)
Port Pi7 direction 0 : Input mode (Functions as an input port)
PDi_7 1 : Output mode (Functions as an output port)
register (Note 4)
Note 1: Set bit 2 of protect register (address 000A16) to "1" before rewriting to the port P9 direction register.
Note 2: In memory expansion and microprocessor mode, the contents of corresponding port direction register
of pins A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH,
RD/DW, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
Note 3: Port 11 to 15 registers exist in 144-pin version.
Note 4: Nothing is assigned in bit5 of Port P8 direction register, bit7 to bit5 of port P11 direction register and
bit7 of port P14 direction register.
When write, set to "0". When read, its content is indeterminate.

Figure 1.29.5. Direction register

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Port Pi register (Note 1, 2, 3)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
Pi(i=0 to 5) 03E016, 03E116, 03E416, 03E516, 03E816, 03E916 Indeterminate
Pi(i=6 to 11) 03C016, 03C116, 03C416, 03C516, 03C816, 03C916 Indeterminate
Pi(i=12 to 15) 03CC16, 03CD16, 03D016, 03D116 Indeterminate

Bit
symbol Bit name Function R W

0 : "L" level
Pi_0 Port Pi0 register
1 : "H" level (Note 4)

0 : "L" level
Pi_1 Port Pi1 register
1 : "H" level (Note 4)

0 : "L" level
Pi_2 Port Pi2 register
1 : "H" level

0 : "L" level
Pi_3 Port Pi3 register
1 : "H" level

0 : "L" level
Pi_4 Port Pi4 register
1 : "H" level

0 : "L" level
Pi_5 Port Pi5 register (Note 5) (Note 6)
1 : "H" level

0 : "L" level
Pi_6 Port Pi6 register (Note 6)
1 : "H" level

0 : "L" level
Pi_7 Port Pi7 register (Note 6)
1 : "H" level

Note 1: Data is input and output to and from each pin by reading and writing to and from each corresponding bit.
Note 2: In memory expansion and microprocessor mode, the contents of corresponding port direction register
of pins A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH,
RD/DW, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
Note 3: Port 11 to 15 direction registers exist in 144-pin version.
Note 4: Port P70 and P71 output high impedance because of N-channel open drain output.
Note 5: Port P85 is read only (There is not W).
Note 6: Nothing is assigned in bit7 to bit5 of port P11 and bit7 of port P14.
When write, set to "0". When read, its content is indeterminate.

Figure 1.29.6. Port register

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Function select register A0

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
PS0 03B016 0016

Bit Bit name Function

symbol R W

Port P60 function 0 : I/O port

PS0_0
select bit 1 : UART0 output (RTS0)

Port P61 function 0 : I/O port

PS0_1
select bit 1 : UART0 output (CLK0 output)

Port P62 function 0 : I/O port

PS0_2 1 : Function that was selected in bit2 of
select bit function select register B0
Port P63 function 0 : I/O port
PS0_3
select bit 1 : UART0 output (TXD0/SDA0)

Port P64 function 0 : I/O port

PS0_4 1 : Function that was selected in bit4 of
select bit function select register B0
Port P65 function 0 : I/O port
PS0_5
select bit 1 : UART1 output (CLK1 output)

Port P66 function 0 : I/O port

PS0_6 1 : Function that was selected in bit6 of
select bit function select register B0
Port P67 function 0 : I/O port
PS0_7
select bit 1 : UART1 output (TXD1/SDA1)

Function select register A1

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
PS1 03B116 0016

Bit
symbol Bit name Function R W

Port P70 function 0 : I/O port

PS1_0 1 : Function that was selected in bit0 of
select bit function select register B1
Port P71 function 0 : I/O port
PS1_1 1 : Function that was selected in bit1 of
select bit function select register B1
Port P72 function 0 : I/O port
PS1_2 1 : Function that was selected in bit2 of
select bit function select register B1
Port P73 function 0 : I/O port
PS1_3 1 : Function that was selected in bit3 of
select bit function select register B1
Port P74 function 0 : I/O port
PS1_4 1 : Function that was selected in bit4 of
select bit function select register B1
Port P75 function 0 : I/O port
PS1_5 1 : Function that was selected in bit5 of
select bit function select register B1
Port P76 function 0 : I/O port
PS1_6 1 : Function that was selected in bit6 of
select bit function select register B1
Port P77 function 0 : I/O port
PS1_7 1 : Intelligent I/O group 0 output
select bit (OUTC01/ISCLK0)

Figure 1.29.7. Function select register A (1)

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Function select register A2

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 0 0 0 PS2 03B416 00X000002

Bit
symbol Bit name Function R W

Port P80 function 0 : I/O port

PS2_0 1 : Function that was selected in bit0 of
select bit function select register B2
Port P81 function 0 : I/O port
PS2_1 1 : Function that was selected in bit1 of
select bit
function select register B2
Port P82 function 0 : I/O port
PS2_2 1 : Function that was selected in bit2 of
select bit function select register B2

Reserve bit Must always be "0".

Noting is assigned. When write, set to "0".

When read, their contents are indeterminate.

Reserve bit Must always be "0".

Function select register A3 (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
PS3 03B516 0016

Bit Bit Name Function

symbol R W

Port P90 function 0 : I/O port

PS3_0
select bit 1 : UART3 output (CLK3)

Port P91 function 0 : I/O port

PS3_1 1 : Function that was selected in bit1 of
select bit
function select register B3
Port P92 function 0 : I/O port
PS3_2 1 : Function that was selected in bit2 of
select bit
function select register B3

PS3_3 Port P93 function 0 : I/O port

select bit 1 : UART3 output (RTS3)

Port P94 function 0 : I/O port

PS3_4
select bit 1 : UART4 output (RTS4)

Port P95 function 0 : I/O port

PS3_5
select bit 1 : UART4 output (CLK4)

Port P96 function 0 : I/O port

PS3_6
select bit 1 : UART4 output (TXD4/SDA4)

Port P97 function 0 : I/O port

PS3_7 1 : Function that was selected in bit7 of
select bit function select register B3
Note :Set bit 2 of protect register (address 000A16) to "1" before rewriting to this register.

Figure 1.29.8. Function select register A (2)

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Function select register A5 (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset

0 PS5 03B916 XXX0 00002

Bit Bit name Function

symbol R W

Port P110 function 0 : I/O port

PS5_0 1 : Intelligent I/O group 1 output
select bit (OUTC10/ ISTXD1/BE1OUT)
Port P111 function 0 : I/O port
PS5_1 1 : Intelligent I/O group 1 output
select bit (OUTC11/ ISCLK1)
Port P112 function 0 : I/O port
PS5_2
select bit 1 : Intelligent I/O group 1 output (OUTC12)

Port P113 function 0 : I/O port

PS5_3
select bit 1 : Intelligent I/O group 1 output (OUTC13)

Reserve bit Must always be "0".

Noting is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: This register exists in 144-pin version.

Function select register A6 (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset

PS6 03BC16 0016

Bit Bit name Function

symbol R W

Port P120 function 0 : I/O port

PS6_0 1 : Intelligent I/O group 3 output (OUTC30)
select bit

Port P121 function 0 : I/O port

PS6_1 1 : Intelligent I/O group 3 output (OUTC31)
select bit

Port P122 function 0 : I/O port

PS6_2
select bit 1 : Intelligent I/O group 3 output (OUTC32)

Port P123 function 0 : I/O port

PS6_3
select bit 1 : Intelligent I/O group 3 output (OUTC33)

Port P124 function 0 : I/O port

PS6_4
select bit 1 : Intelligent I/O group 3 output (OUTC34)

Port P125 function 0 : I/O port

PS6_5 1 : Intelligent I/O group 3 output (OUTC35)
select bit

Port P126 function 0 : I/O port

PS6_6 1 : Intelligent I/O group 3 output (OUTC36)
select bit

Port P127 function 0 : I/O port

PS6_7 1 : Intelligent I/O group 3 output (OUTC37)
select bit

Note: This register exists in 144-pin version.

Figure 1.29.9. Function select register A (3)

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Function select register A7 (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset

PS7 03BD16 0016

Bit Bit name Function

symbol R W

Port P130 function 0 : I/O port

PS7_0
select bit 1 : Intelligent I/O group 2 output (OUTC24)

Port P131 function 0 : I/O port

PS7_1
select bit 1 : Intelligent I/O group 2 output (OUTC25)

Port P132 function 0 : I/O port

PS7_2
select bit 1 : Intelligent I/O group 2 output (OUTC26)

Port P133 function 0 : I/O port

PS7_3
select bit 1 : Intelligent I/O group 2 output (OUTC23)

Port P134 function 0 : I/O port

PS7_4 1 : Intelligent I/O group 2 output
select bit (OUTC20/ISTXD2/IEOUT)
Port P135 function 0 : I/O port
PS7_5
select bit 1 : Intelligent I/O group 2 output (OUTC22)

Port P136 function 0 : I/O port

PS7_6 1 : Intelligent I/O group 2 output
select bit (OUTC21/ISCLK2)
Port P137 function 0 : I/O port
PS7_7 select bit 1 : Intelligent I/O group 2 output (OUTC27)

Note: This register exists in 144-pin version.

Function select register A8 (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset

0 0 0 PS8 03A016 X00000002

Bit Bit name Function

symbol R W

Port P140 function 0 : I/O port

PS8_0 1 : Intelligent I/O group 1 output (OUTC14)
select bit

Port P141 function 0 : I/O port

PS8_1
select bit 1 : Intelligent I/O group 1 output (OUTC15)

Port P142 function 0 : I/O port

PS8_2
select bit 1 : Intelligent I/O group 1 output (OUTC16)

Port P143 function 0 : I/O port

PS8_3
select bit 1 : Intelligent I/O group 1 output (OUTC17)

Reserve bit Must always be "0".

Noting is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: This register exists in 144-pin version.

Figure 1.29.10. Function select register A (4)

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Function select register A9 (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset

0 0 0 0 PS9 03A116 0016

Bit Bit name Function

symbol R W

Port P150 function 0 : I/O port

PS9_0 1 : Intelligent I/O group 0 output
select bit (OUTC00/ ISTXD0/BE0OUT)
Port P151 function 0 : I/O port
PS9_1 1 : Intelligent I/O group 0 output
select bit (OUTC01/ ISCLK0)

Reserve bit Must always be "0".

Port P154 function 0 : I/O port

PS9_4
select bit 1 : Intelligent I/O group 0 output (OUTC04)

Port P155 function 0 : I/O port

PS9_5
select bit 1 : Intelligent I/O group 0 output (OUTC05)

Reserve bit Must always be "0".

Note: This register exists in 144-pin version.

Figure 1.29.11. Function select register A (5)

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Function select register B0

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 0 0 0 0 PSL0 03B216 0016

Bit Bit name Function

symbol R W

Reserve bit Must always be "0".

Port P62 peripheral 0 : UART0 output (SCL0)

PSL0_2
function select bit 1 : UART0 output (STXD0)

Reserve bit Must always be "0".

Port P64 peripheral 0 : UART1 output (RTS1)

PSL0_4 1 : Intelligent I/O group 2 output
function select bit (OUTC21/ISCLK2)

Reserve bit Must always be "0".

Port P66 peripheral 0 : UART1 output (SCL1)

PSL0_6
function select bit 1 : UART1 output (STXD1)

Reserve bit Must always be "0".

Function select register B1

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 PSL1 03B316 0016

Bit Bit name Function

symbol R W

Port P70 peripheral 0 : Function that was selected in bit0 of

PSL1_0 function select register C
function select bit 1 : Timer output (TA0OUT)

Port P71 peripheral 0 : Function that was selected in bit1 of

PSL1_1 function select register C
function select bit 1 : UART2 output (STXD2)

Port P72 peripheral 0 : Function that was selected in bit2 of

PSL1_2 function select register C
function select bit 1 : Timer output (TA1OUT)

Port P73 peripheral 0 : Function that was selected in bit3 of

PSL1_3 function select register C
function select bit 1 : Three-phase PWM output (V)

Port P74 peripheral 0 : Function that was selected in bit4 of

PSL1_4 function select register C
function select bit 1 : Three-phase PWM output (W)

Port P75 peripheral 0 : Three-phase PWM output (W)

PSL1_5
function select bit 1 : Intelligent I/O group 1 output (OUTC12)

Port P76 peripheral 0 : Function that was selected in bit6 of

PSL1_6 function select register C
function select bit 1 : Timer output (TA3OUT)

Reserve bit Must always be "0".

Figure 1.29.12. Function select register B (1)

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Function select register B2

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 0 0 0 PSL2 03B616 00X000002

Bit Bit name Function

symbol R W

Port P80 peripheral 0 : Timer output (TA4OUT)

PSL2_0
function select bit 1 : Three-phase PWM output (U)

Port P81 peripheral 0 : Three-phase PWM output (U)

PSL2_1 1 : Intelligent I/O group 3 output
function select bit
(OUTC30)
Port P82 peripheral 0 : Intelligent I/O group 3 output (OUTC32)
PSL2_2
function select bit 1 : CAN output (CANOUT)

Reserve bit Must always be "0".

Noting is assigned. When write, set to "0".

When read, their contents are indeterminate.

Reserve bit Must always be "0".

Function select register B3

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 PSL3 03B716 0016

Bit Bit name Function

symbol R W

Reserve bit Must always be "0".

Port P91 peripheral 0 : UART3 output (SCL3)

PSL3_1
function select bit 1 : UART3 output (STXD3)
0 : UART3 output (TXD3/SDA3)
Port P92 peripheral
PSL3_2 1 : Intelligent I/O group 2 output
function select bit
(OUTC20/IEOUT)
Port P93 peripheral 0 : Input peripheral function enabled
PSL3_3 (Expect DA0 output) (Note)
function select bit 1 : Input peripheral function disabled (DA0 output)
Port P94 peripheral 0 : Input peripheral function enabled
PSL3_4 (Expect DA1 output) (Note)
function select bit 1 : Input peripheral function disabled (DA1 output)
0 : Input peripheral function enabled
Port P95 peripheral
PSL3_5 (Expect ANEX0 output) (Note)
function select bit 1 : Input peripheral function disabled (ANEX0 output)
Port P96 peripheral 0 : Input peripheral function enabled
PSL3_6 (Expect ANEX1 output) (Note)
function select bit
1 : Input peripheral function disabled (ANEX1 output)
Port P97 peripheral 0 : UART4 output (SCL4)
PSL3_7
function select bit 1 : UART4 output (STXD4)
Note: Although DA0, DA1, ANEX0 and ANEX1 can be used when "0" is set in these bits, the power supply
may be increased.

Figure 1.29.13. Function select register B (2)

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Function select register C

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
PSC 03AF16 00X000002

Bit Bit name Function

symbol R W

Port P70 peripheral 0 : UART2 output (TXD2/SDA2)

PSC_0 1 : Intelligent I/O group 2 output
function select bit (OUTC20/ ISTXD2/IEOUT)
Port P71 peripheral 0 : UART2 output (SCL2)
PSC_1
function select bit 1 : Intelligent I/O group 2 output (OUTC22)

Port P72 peripheral 0 : UART2 output (CLK2)

PSC_2
function select bit 1 : Three-phase PWM output (V)

Port P73 peripheral 0 : UART2 output (RTS2)

PSC_3 1 : Intelligent I/O group 1 output
function select bit
(OUTC10/ ISTXD1/BE1OUT)
Port P74 peripheral 0 : Timer output (TA2OUT)
PSC_4 1 : Intelligent I/O group 1 output
function select bit (OUTC11/ ISCLK1)
Noting is assigned. When write, set to "0".
When read, its content is indeterminate.

Port P76 peripheral 0 : Intelligent I/O group 0 output

PSC_6 (OUTC00/ISTXD0/BE0OUT)
function select bit 1 : CAN output (CANOUT)

Key input interrupt 0 : Enabled (Note)

PSC_7
disable bit 1 : Disabled

Note: Although DA0, DA1, ANEX0 and ANEX1 can be used when "0" is set in this bit, the power supply
may be increased.

Figure 1.29.14. Function select register C

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Pull-up control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset

PUR0 03F016 000000002

Bit Bit name Function

symbol R W

0 : Not pulled high

PU00 P00 to P03 pull-up
1 : Pulled high

0 : Not pulled high

PU01 P04 to P07 pull-up
1 : Pulled high

0 : Not pulled high

PU02 P10 to P13 pull-up
1 : Pulled high

0 : Not pulled high

PU03 P14 to P17 pull-up
1 : Pulled high

0 : Not pulled high

PU04 P20 to P23 pull-up
1 : Pulled high

0 : Not pulled high

PU05 P24 to P27 pull-up
1 : Pulled high

0 : Not pulled high

PU06 P30 to P33 pull-up
1 : Pulled high

0 : Not pulled high

PU07 P34 to P37 pull-up
1 : Pulled high

Note: Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode,
do not set the pull-up control register. However, it is possible to select pull-up resistance
presence to the usable port as I/O port by setting.

Pull-up control register 1 (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset

PUR1 03F116 XXXX00002

Bit Bit name Function

symbol R W

0 : Not pulled high

PU10 P40 to P43 pull-up
1 : Pulled high

0 : Not pulled high

PU11 P44 to P47 pull-up
1 : Pulled high

0 : Not pulled high

PU12 P50 to P53 pull-up
1 : Pulled high

0 : Not pulled high

PU13 P54 to P57 pull-up
1 : Pulled high

Noting is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode,
do not set the pull-up control register. However, it is possible to select pull-up resistance
presence to the usable port as I/O port by setting.

Figure 1.29.15. Pull-up control register (1)

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Pull-up control register 2 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset

PUR2 03DA16 000000002

Bit Bit name Function

symbol R W

0 : Not pulled high

PU20 P60 to P63 pull-up
1 : Pulled high

0 : Not pulled high

PU21 P64 to P67 pull-up
1 : Pulled high

0 : Not pulled high

PU22 P70 to P73 pull-up
1 : Pulled high (Note 2)

0 : Not pulled high

PU23 P74 to P77 pull-up
1 : Pulled high

0 : Not pulled high

PU24 P80 to P83 pull-up
1 : Pulled high

0 : Not pulled high

PU25 P84 to P87 pull-up
1 : Pulled high (Note 3)

0 : Not pulled high

PU26 P90 to P93 pull-up
1 : Pulled high

0 : Not pulled high

PU27 P94 to P97 pull-up
1 : Pulled high
Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them.
Note 2: Except port P85.

Pull-up control register 3 <144-pin version>

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
PUR3 03DB16 000000002

Bit Bit name Function

symbol R W

0 : Not pulled high

PU30 P100 to P103 pull-up
1 : Pulled high

0 : Not pulled high

PU31 P104 to P107 pull-up
1 : Pulled high

0 : Not pulled high

PU32 P110 to P113 pull-up
1 : Pulled high

0 : Not pulled high

PU33 P114 pull-up
1 : Pulled high

0 : Not pulled high

PU34 P120 to P123 pull-up
1 : Pulled high

0 : Not pulled high

PU35 P124 to P127 pull-up
1 : Pulled high

0 : Not pulled high

PU36 P130 to P133 pull-up
1 : Pulled high

0 : Not pulled high

PU37 P134 to P137 pull-up
1 : Pulled high

Figure 1.29.16. Pull-up control register (2)

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Pull-up control register 3 <100-pin version>

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 0 0 0 0 0 PUR3 03DB16 0016

Bit Bit name Function

symbol R W

0 : Not pulled high

PU30 P100 to P103 pull-up
1 : Pulled high

0 : Not pulled high

PU31 P104 to P107 pull-up
1 : Pulled high

Reserve bit Must always be "0".

Pull-up control register 4 (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset

PUR4 03DC16 XXXX00002

Bit Bit name Function

symbol R W

0 : Not pulled high

PU40 P140 to P143 pull-up
1 : Pulled high

0 : Not pulled high

PU41 P144 to P146 pull-up
1 : Pulled high

0 : Not pulled high

PU42 P150 to P153 pull-up
1 : Pulled high

0 : Not pulled high

PU43 P154 to P157 pull-up
1 : Pulled high

Noting is assigned. When write, set to "0".

When read, their contents are indeterminate.

Note: This register exists in 144-pin version..

Figure 1.29.17. Pull-up control register (3)

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Port control register (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset

PCR 03FF16 XXXXXXX02

Bit Bit name Function

symbol R W

Port P1 control 0 : Function as common CMOS port

PCR0
register 1 : Function as N-ch open drain port
(Note 2)
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
Note 1: Since P1 operates as the data bus in memory expansion mode and microprocessor
mode, do not set the port control register. However, it is possible to select CMOS port
or N-channel open drain pin to the usable port as I/O port by setting.
Note 2: This function is designed to permanently turn OFF the Pch of the CMOS port.
It dose not make port P1 a full open drain.
Therefore, the absolute maximum input voltage rating is [-3 to VCC + 3.0V].

Input function select register

b7 b0 Symbol Address When reset
IPS 017816 00000X002

Bit
symbol Bit name Function R W
Assigns functions of INPC00, INPC01
/ISCLK0 and INPC02/ISRxD0/BE0IN
Group 0 input pin
IPS0 to the following ports.
select bit 0
0 : P76, P77, P80
1 : P150, P151, P152
Assigns functions of INPC11/ISCLK1
and INPC12/ISRxD1/BE1IN to the
Group 1 input pin
IPS1 following ports.
select bit 1
0 : P74, P75
1 : P111, P112

P15 input peripheral 0 : Input peripheral function is enabled

IPS2 1 : Input peripheral function is disabled
function select bit
(Note)
CANIN function 0 : P77
IPS3
pin select bit 1 : P83
b5 b4
IPS4 0 0 : P71
ISRxD2/IEIN function : P91
0 1
pin select bit : P135
1 0
IPS5
1 1 : Must not be set

ISCLK2 function 0 : P64

IPS6
pin select bit 1 : P136

Reserve bit Must always be "0".

Note: Although AD input pin can be used when "0" is set in this bit,
the power supply may be increased.

Figure 1.29.18. Port control register and input function select register

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Table 1.29.1. Example connection of unused pins in single-chip mode

Pin name Connection

Ports P0 to P15 (excluding P85) After setting for input mode, connect every pin to VSS via a resistance
(Note 1) (pull-down); or after setting for output mode, leave these pins open.
XOUT (Note 2) Open
NMI Connect via resistance to VCC (pull-up)
AVCC Connect to VCC
AVSS, VREF, BYTE Connect to VSS
Note 1: Ports P11 to P15 exist in 144-pin version.
Note 2: With external clock input to XIN pin.

Table 1.29.2. Example connection of unused pins in memory expansion mode and microprocessor mode
Pin name Connection
Ports P6 to P15 (excluding P85) After setting for input mode, connect every pin to VSS via a resistance
(Note 1) (pull-down); or after setting for output mode, leave these pins open.
BHE, ALE, HLDA, Open
XOUT(Note 2), BCLK
HOLD, RDY, NMI Connect via resistance to VCC (pull-up)
AVCC Connect to VCC
AVSS, VREF Connect to VSS
Note 1: Ports P11 to P15 exist in 144-pin version.
Note 2: With external clock input to XIN pin.

Microcomputer Microcomputer
Port P0 to P15 (except for P85) Port P6 to P15 (except for P85)
(Note)
(Input mode) (Input mode)
· · · ·
· · · ·
· · · ·
(Input mode) (Input mode)
(Output mode) Open (Output mode) Open
NMI
NMI BHE
HLDA
XOUT Open ALE Open
VCC XOUT
BCLK VCC
AVCC
BYTE HOLD
AVSS RDY
VREF AVCC
AVSS VSS
VSS
VREF

In single-chip mode In memory expansion mode or

in microprocessor mode
Note : Ports P11 to P15 exist in 144-pin version.

Figure 1.29.19. Example connection of unused pins

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Table 1.29.3. Port P6 output control

PS0 register PSL0 register
Bit 0 0: P60 ________
Must set to "0"
1: UART0 output (RTS0)(Note)
Bit 1 0: P61 Must set to "0"
1: UART0 output (CLK0)(Note)
Bit 2 0: P62 0: UART0 output (SCL0)
1: Selected by PSL0 register 1: UART0 output (STxD0)
Bit 3 0: P63 Must set to "0"
1: UART0 output (TxD0/SDA0)(Note)
________
Bit 4 0: P64 0: UART1 output (RTS1)
1: Selected by PSL0 register 1: Intelligent I/O group 2 (OUTC21/ISCLK2)
Bit 5 0: P65 Must set to "0"
1: UART1 output (CLK1)(Note)
Bit 6 0: P66 0: UART1 output (SCL1)
1: Selected by PSL0 register 1: UART1 output (STxD1)
Bit 7 0: P67 Must set to "0"
1: UART1 output (TxD1/SDA1)(Note)
PS0 register: Function select register A0
PSL0 register: Function select register B0
Note : Select "0" in corresponding bit of PSL0 register.

Table 1.29.4. Port P7 output control

PS1 register PSL1 register PSC register
Bit 0 0: P70 0: Selected by PSC register 0: UART2 output (TxD2/SDA2)
1: Selected by PSL1 register 1: TImer output (TA0OUT)(Note 1) 1: Intelligent I/O group 2
(OUTC20/ISTxD2/IEOUT)
Bit 1 0: P71 0: Selected by PSC register 0: UART2 output (SCL2)
1: Selected by PSL1 register 1: UART2 output (STxD2)(Note 1) 1: Intelligent I/O group 2
(OUTC22)
Bit 2 0: P72 0: Selected by PSC register 0: UART2 output (CLK2)
1: Selected by PSL1 register 1: TImer output (TA1OUT)(Note 1) 1: Three-phase PWM output (V)
_______
Bit 3 0: P73 0: Selected by PSC register __ 0: UART2 output (RTS2)
1: Selected by PSL1 register 1: Three-phase PWM output (V)(Note 1) 1: Intelligent I/O group 1
(OUTC10/ISTxD1/BE1OUT)
Bit 4 0: P74 0: Selected by PSC register 0: TImer output (TA2OUT)
1: Selected by PSL1 register 1: Three-phase PWM output (W)(Note 1) 1: Intelligent I/O group 1
(OUTC11/ISCLK1)
___
Bit 5 0: P75 0: Three-phase PWM output (W)(Note 1) Must set to "0"
1: Selected by PSL1 register 1: Intelligent I/O group 1
(OUTC12)
Bit 6 0: P76 0: Selected by PSC register 0: Intelligent I/O group 0
(OUTC00/ISTxD0/BE0OUT)
1: Selected by PSL1 register 1: TImer output (TA3OUT) 1: CAN output (CANOUT)
Bit 7 0: P77 Must set to "0" 0: Key input interrupt signal enabled
1: Intelligent I/O group 0 1: Key input interrupt signal disabled
(OUTC01/ISCLK0)
PS1 register: Function select register A1
PSL1 register: Function select register B1
PSC register: Function select register C
Note 1: Select "0" in corresponding bit of PSC register.
Note 2: Select "0" in corresponding bit of PSL1 register.

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Table 1.29.5. Port P8 output control

PS2 register PSL2 register
Bit 0 0: P80 0: Timer output (TA4OUT)
1: Selected by PSL2 register 1: Three-phase PWM output (U)
____
Bit 1 0: P81 0: Three-phase PWM output (U)
1: Selected by PSL2 register 1: Intelligent I/O group 3(OUTC30)
Bit 2 0: P82 0: Intelligent I/O group 3(OUTC32)
1: Selected by PSL2 register 1: CAN output (CANOUT)
Bit 3 to 7 Must set to "0"
PS2 register: Function select register A2
PSL2 register: Function select register B2

Table 1.29.6. Port P9 output control

PS3 register PSL3 register
Bit 0 0: P90 Must set to "0"
1: UART3 output (CLK3)(Note)
Bit 1 0: P91 0: UART3 output (SCL3)
1: Selected by PSL3 register 1: UART3 output (STxD3)
Bit 2 0: P92 0: UART3 output (TxD3/SDA3)
1: Selected by PSL3 register 1: Intelligent I/O group 2 (OUTC20/IEOUT)
Bit 3 0: P93 ________
0: Except DA0 output
1: UART3 output (RTS3)(Note) 1: DA0 output
Bit 4 0: P94 ________
0: Except DA1 output
1: UART4 output (RTS4)(Note) 1: DA1 output
Bit 5 0: P95 0: Except ANEX0
1: UART4 output (CLK4)(Note) 1: ANEX0
Bit 6 0: P96 0: Except ANEX1
1: UART4 output (TxD4/SDA4)(Note) 1: ANEX1
Bit 7 0: P97 0: UART4 output (SCL4)
1: Selected by PSL3 register 1: UART4 output (STxD4)
PS3 register: Function select register A3
PSL3 register: Function select register B3
Note : Select "0" in corresponding bit of PSL3 register.

Table 1.29.7. Port P11 output control

PS5 register
Bit 0 0: P110
1: Intelligent I/O group 1(OUTC10/ISTxD1/BE1OUT)
Bit 1 0: P111
1: Intelligent I/O group 1(OUTC11/ISCLK1)
Bit 2 0: P112
1: Intelligent I/O group 1(OUTC12)
Bit 3 0: P113
1: Intelligent I/O group 1(OUTC13)
Bit 4 to 7 Must set to "0"
PS5 register: Function select register A5

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Table 1.29.8. Port P12 output control

PS6 register
Bit 0 0: P120
1: Intelligent I/O group 3(OUTC30)
Bit 1 0: P121
1: Intelligent I/O group 3(OUTC31)
Bit 2 0: P122
1: Intelligent I/O group 3(OUTC32)
Bit 3 0: P123
1: Intelligent I/O group 3(OUTC33)
Bit 4 0: P124
1: Intelligent I/O group 3(OUTC34)
Bit 5 0: P125
1: Intelligent I/O group 3(OUTC35)
Bit 6 0: P126
1: Intelligent I/O group 3(OUTC36)
Bit 7 0: P127
1: Intelligent I/O group 3(OUTC37)
PS6 register: Function select register A6

Table 1.29.9. Port P13 output control

PS7 register
Bit 0 0: P130
1: Intelligent I/O group 2(OUTC24)
Bit 1 0: P131
1: Intelligent I/O group 2(OUTC25)
Bit 2 0: P132
1: Intelligent I/O group 2(OUTC26)
Bit 3 0: P133
1: Intelligent I/O group 2(OUTC23)
Bit 4 0: P134
1: Intelligent I/O group 2(OUTC20/ISTxD2/IEOUT)
Bit 5 0: P135
1: Intelligent I/O group 2(OUTC22)
Bit 6 0: P136
1: Intelligent I/O group 2(OUTC21/ISCLK2)
Bit 7 0: P137
1: Intelligent I/O group 2(OUTC27)
PS7 register: Function select register A7

Table 1.29.10. Port P14 output control

PS8 register
Bit 0 0: P140
1: Intelligent I/O group 1(OUTC14)
Bit 1 0: P141
1: Intelligent I/O group 1(OUTC15)
Bit 2 0: P142
1: Intelligent I/O group 1(OUTC16)
Bit 3 0: P143
1: Intelligent I/O group 1(OUTC17)
Bit 4 to 7 Must set to "0"
PS8 register: Function select register A8

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Table 1.29.11. Port P15 output control

PS9 register
Bit 0 0: P150
1: Intelligent I/O group 0 (OUTC00/ISTxD0/BEOUT)
Bit 1 0: P151
1: Intelligent I/O group 0 (OUTC01/ISCLK0)
Bit 2 to 3 Must set to "0"
Bit 4 0: P154
1: Intelligent I/O group 0 (OUTC04)
Bit 5 0: P155
1: Intelligent I/O group 0 (OUTC05)
Bit 6 to 7 Must set to "0"
PS9 register: Function select register A9

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VDC

VDC
When power-supply voltage is 3.3V or under, set the internal VDC (Voltage Down Converter) unused.
Follow the steps given below to disable the VDC.
(1) Set bit 3 of the protect register to "1".
(2) Set the VDC control register 0 to "0F16".
(3) Set the VDC control register 0 to "8F16".
(4) Set bit 3 of the protect register to "0".
These steps must be performed after reset as immediately as possible with divide-by-8 clock. When the
VDC select bit has been set to "112" once, do not set any other values.

Figure 1.30.1 shows the VDC control register 0.

VDC control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
VDC0 001B16 0016

Bit
symbol Bit name Function R W
b1b0
VDC00 1 1: VDC unused
VDC select bit
Do not set any values other than "11".
VDC01

b3 b2
VDC02 1 1: VDC reference voltage Off
VDC reference voltage
select bit Do not set any values other than "11".
VDC03

VDC04

VDC05 Reserved bit Must set to "0"

VDC06

0: VDC Off
VDC07 VDC enable bit
(Note 2) 1: VDC On
Note 1: Set bit 3 of the protect register (address 000A16) to "1" before rewriting this register.
Rewriting this register should be performed only when the VDC is to be off.
Note 2: This bit enables the setting of bit 0 to bit 3.
Set bit 7 to "0" first, and then write values to bit 0 to bit 3. After that, write "1" to bit 7.
The state changes at the time "1" is written to bit 7.

Figure 1.30.1. VDC control register

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Usage precaution

Usage Precaution
Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register while reloading gets “FFFF16”. Reading the timer Ai
register after setting a value in the timer Ai register with a count halted but before the counter starts
counting gets a proper value.

Timer A (event counter mode)

(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register while reloading gets “FFFF16” by underflow or
“000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a
count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
(3) In the case of using as “Free-Run type”, the timer register contents may be unknown when counting
begins. If the timer register is set before counting has started, then the starting value will be unknown.
• In the case where the up/down count will not be changed.
Enable the “Reload” function and write to the timer register before counting begins. Rewrite
the value to the timer register immediately after counting has started. If counting up, rewrite
“000016” to the timer register. If counting down, rewrite “FFFF16” to the timer register. This
will cause the same operation as “Free-Run type” mode.
• In the case where the up/down count has changed.
First set to “Reload type” operation. Once the first counting pulse has occurred, the timer
may be changed to “Free-Run type”.

Timer A (one-shot timer mode)

(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(2) The output from the one-shot timer synchronizes with the count source generated internally. There-
fore, when an external trigger has been selected, a delay of one cycle of count source as maximum
occurs between the trigger input to the TAiIN pin and the one-shot timer output.
(3) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after
the above listed changes have been made.
(4) If a trigger occurs while a count is in progress, after the counter performs one down count following the
reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To
generate a trigger while a count is in progress, generate the second trigger after an elapse longer
than one cycle of the timer's count source after the previous trigger occurred.

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Usage precaution

Timer A (pulse width modulation mode)

(1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after
the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance,
the level does not change, and the timer Ai interrupt request bit does not becomes “1”.

Timer B (timer mode, event counter mode)

(1) Reading the timer Bi register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Bi register while reloading gets “FFFF16”. Reading the timer Bi
register after setting a value in the timer Bi register with a count halted but before the counter starts
counting gets a proper value.

Timer B (pulse period/pulse width measurement mode)

(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
(3) The value of the counter is indeterminate at the beginning of a count. Therefore, the timer Bi overflow
flag may go to “1” and timer Bi interrupt request may be generated during the interval between a count
start and an effective edge input.

Stop Mode and Wait Mode

____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When shifting to WAIT mode or STOP mode, the program stops after reading from the WAIT instruc-
tion and the instruction that sets all clock stop control bits to “1” in the instruction queue. Therefore,
insert a minimum of 4 NOPs after the WAIT instruction and the instruction that sets all clock stop
control bits to “1” in order to flush the instruction queue.

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Usage precaution

A-D Converter
(1) Write to each bit (except bit 6) of A-D i (i=0,1) control register 0, to each bit of A-D i control register 1,
and to each bit of A-D i control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-
D conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
(5) When f(XIN) is faster than 10 MHz, make the frequency 10 MHz or less by dividing.
(6) Output impedance of sensor at A-D conversion (Reference value)
To carry out A-D conversion properly, charging the internal capacitor C shown in Figure 1.31.1 has to
be completed within a specified period of time T. Let output impedance of sensor equivalent circuit be
R0, microcomputer’s internal resistance be R, precision (error) of the A-D converter be X, and the A-
D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
t
–
Vc is generally VC = VIN {1 – e C (R0 + R) }

X X
And when t = T, VC=VIN – VIN=VIN(1 – )
Y Y

T
– X
C (R0 + R)
e =
Y
T X
– =ln
C (R0 +R) Y
T
Hence, R0 = – –R
X
C • ln
Y

With the model shown in Figure 1.31.1 as an example, when the difference between VIN and VC becomes
0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-(0.1/1024) VIN in
time T. (0.1/1024) means that A-D precision drop due to insufficient capacitor charge is held to 0.1LSB at
time of A-D conversion in the 10-bit mode. Actual error however is the value of absolute precision added
to 0.1LSB. When f(XIN) = 10 MHz, T = 0.3 µs in the A-D conversion mode with sample & hold. Output
impedance R0 for sufficiently charging capacitor C within time T is determined as follows.

T = 0.3 µs, R = 7.8 kΩ, C = 3 pF, X = 0.1, and Y = 1024 . Hence,

0.3 X 10-6
R0 = – – 7.8 X103 3.0 X 103
0.1
3.0 X 10 –12 • ln
1024

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Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A-D con-
verter turns out to be approximately 3.0 kΩ. Tables 1.31.1 and 1.31.2 show output impedance values
based on the LSB values.

Internal circuit of microprocessor

Sensor-equivalent circuit

R0 R (7.8k Ω)

VIN
C (3.0pF)
VC

Figure 1.31.1 A circuit equivalent to the A-D conversion terminal

(7) After A-D conversion is complete, if the CPU reads the A-D register at the same time as the A-D
conversion result is being saved to A-D register, wrong A-D conversion value is saved into the A-D
register. This happens when the internal CPU clock is selected from divided main clock or sub-clock.

• When using the one-shot or single sweep mode

Confirm that A-D conversion is complete before reading the A-D register.
(Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.)
• When using the repeat mode or repeat sweep mode 0 or 1
Use the undivided main clock as the internal CPU clock.

Interrupts
(1) Setting the stack pointer
• The value of the stack pointer is initialized to 00000016 immediately after reset. Accepting an
interrupt before setting a value in the stack pointer may cause runaway. Be sure to set a value in
the stack pointer before accepting an interrupt.
_______
When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Regard-
_______
ing the first instruction immediately after reset, generating any interrupts including the NMI inter-
rupt is prohibited.
Set an even address to the stack pointer so that operating efficiency is increased.
_______
(2) The NMI interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the VCC pin via a
resistance (pulled-up) if unused.
_______
• The NMI pin also serves as P8 5, which is exclusively input. Reading the contents of the P8
register allows reading the pin value. Use the reading of this pin only for establishing the pin level
_______
at the time when the NMI interrupt is input.
_______
• Signal of "L" level width more than 1 clock of CPU operation clock (BCLK) is necessary for NMI
pin.

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Tables 1.31.1. Output impedance values based on the LSB values (10-bit mode) Reference value
f(XIN) Cycle Sampling time R C Resolution R0max
(MHz) (µs) (µs) (kΩ) (pF) (LSB) (kΩ)
10 0.1 0.3 7.8 3.0 0.1 3.0
(3 X cycle, 0.3 4.5
Sample & hold 0.5 5.3
bit is enabled) 0.7 5.9
0.9 6.4
1.1 6.8
1.3 7.2
1.5 7.5
1.7 7.8
1.9 8.1
10 0.1 0.2 7.8 3.0 0.3 0.4
(2 X cycle, 0.5 0.9
Sample & hold 0.7 1.3
bit is disabled) 0.9 1.7
1.1 2.0
1.3 2.2
1.5 2.4
1.7 2.6
1.9 2.8

Tables 1.31.2. Output impedance values based on the LSB values (8-bit mode) Reference value
f(XIN) Cycle Sampling time R C Resolution R0max
(MHz) (µs) (µs) (kΩ) (pF) (LSB) (kΩ)
10 0.1 0.3 7.8 3.0 0.1 4.9
(3 X cycle, 0.3 7.0
Sample & hold 0.5 8.2
bit is enabled) 0.7 9.1
0.9 9.9
1.1 10.5
1.3 11.1
1.5 11.7
1.7 12.1
1.9 12.6
10 0.1 0.2 7.8 3.0 0.1 0.7
(2 X cycle, 0.3 2.1
Sample & hold 0.5 2.9
bit is disabled) 0.7 3.5
0.9 4.0
1.1 4.4
1.3 4.8
1.5 5.2
1.7 5.5
1.9 5.8

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(3) External interrupt

• Edge sense
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins
_______ _______
INT0 to INT5 regardless of the CPU operation clock.
• Level sense
Either an “L” level or an “H” level of 1 cycle of BCLK + at least 200 ns width is necessary for the
_______ _______
signal input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=30MHz and
no division mode, at least 233 ns width is necessary.)
_______ _______
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to
"1". After changing the polarity, set the interrupt request bit to "0". Figure 1.31.2 shows the
______
procedure for changing the INT interrupt generate factor.

Set the interrupt priority level to level 0

(Disable INTi interrupt)

Set the polarity select bit

Clear the interrupt request bit to “0”

Set the interrupt priority level to level 1 to 7

(Enable the accepting of INTi interrupt request)

______
Figure 1.31.2. Switching condition of INT interrupt request
(4) Rewrite the interrupt control register
• When a instruction to rewrite the interrupt control register is executed but the interrupt is dis-
abled, the interrupt request bit is not set sometimes even if the interrupt request for that register
has been generated. This will depend on the instructions. If this creates problems, use the below
instructions to change the register.
Instructions : AND, OR, BCLR, BSET

DMAC
(1) Do not clear the DMA request bit of the DMAi request cause select register.
In M32C/83, when a DMA request is generated while the channel is disabled (Note), the DMA trans-
fer is not executed and the DMA request bit is cleared automatically.
Note :The DMA is disabled or the transfer count register is "0".
(2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause
select register to "1" simultaneously using the OR instruction.
e.g.) OR.B #0A0h, DMiSL ; DMiSL is DMAi request cause select register
(3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1"
to the DMA request bit, simultaneously. In this case, disable the corresponding DMA channel to
disabled before changing the DMAi request cause select bit. To enable DMA at least 8+6xN cycles
(N: enabled channel number) following the instruction to write to the DMAi request cause select
register are needed.

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Usage precaution

Example) When DMA request cause is changed to timer A0 and using DMA0 in single transfer
after DMA initial setting
push.w R0 ; Store R0 register
stc DMD0, R0 ; Read DMA mode register 0
and.b #11111100b, R0L ; Clear DMA0 transfer mode select bit to "00"
ldc R0, DMD0 ; DMA0 disabled
mov.b #10000011b, DM0SL ; Select timer A0
; (Write "1" to DMA request bit simultaneously)
nop At least 8 + 6 x N cycles
: (N: enabled channel number)
ldc R0, DMD0 ; DMA0 enabled
pop.w R0 ; Restore R0 register

Noise
(1) A bypass capacitor should be inserted between Vcc-Vss line for reducing noise and latch-up
Connect a bypass capacitor (approx. 0.1µF) between the Vcc and Vss pins using short wiring and
thicker circuit traces.

Precautions for using CLKOUT pin

When using the Clock Output function of P53/CLKOUT pin (f8, f32 or fc output) in single chip mode, use
port P57 as an input only port (port P57 direction register is "0").
Although port P57 may be set as an output port (port P57 direction register is "1"), it will become high
impedance and will not output "H" or "L" levels.

__________
HOLD signal
__________
When using the HOLD input while P40 to P47 and P50 to P52 are set as output ports in single-chip mode,
you must first set all pins for P40 to P47 and P50 to P52 as input ports, then shift to microprocessor mode
or memory expansion mode.

Reducing power consumption

(1) When A-D conversion is not performed, select the Vref not connected with the Vref connect bit of A-D
control register 1. When A-D conversion is performed, start the A-D conversion at least 1 µs or longer
after connecting Vref.
(2) When using AN4 (P104) to AN7 (P107), select the input disable of the key input interrupt signal with the
key input interrupt disable bit of the function select register C .
When selecting the input disable of the key input interrupt signal, the key input interrupt cannot be
used. Also, the port cannot be input even if the direction register of P104 to P107 is set to input (the
input result becomes undefined). When the input disable of the key input interrupt signal is selected,
use all AN4 to AN7 as A-D inputs.
(3) When ANEX0 and ANEX1 are used, select the input peripheral function disable with port P95 and P96
input peripheral function select bit of the function select register B3.
When the input peripheral function disable is selected, the port cannot be input even if the port direc-
tion register is set to input (the input result becomes undefined).
Also, it is not possible to input a peripheral function except ANEX0 and ANEX1.

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(4) When D-A converter is not used, set output disabled with the D-A output enable bit of D-A control
register and set the D-A register to "0016".
(5) When D-A conversion is used, select the input peripheral function disabled with port P93 and P94 input
peripheral function select bit of the function select register B3.
When the input peripheral function disabled is selected, the port cannot be input even if the port
direction register is set to input (the input result becomes undefined).
Also, it is not possible to input a peripheral function.

DRAM controller
The DRAM self-refresh operates in stop mode, etc.
When shifting to self-refresh, select DRAM is ignored by the DRAM space select bit. In the next instruc-
tion, simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also,
insert two NOPs after the instruction that sets the self-refresh mode bit to "1".
Do not access external memory while operating in self-refresh. (All external memory space access is
inhibited. )
When disabling self-refresh, simultaneously select DRAM is ignored by the DRAM space select bit and
self-refresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit.
Do not access the DRAM space immediately after setting the DRAM space select bit.

Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit
Shifting to self-refresh
•••
mov.b #00000001b,DRAMCONT ;DRAM is ignored, one wait is selected
mov.b #10001011b,DRAMCONT ;Set self-refresh, select 4MB and one wait
nop ;Two nops are needed
nop ;
•••
Disable self-refresh
•••
mov.b #00000001b,DRAMCONT ;Disable self-refresh, DRAM ignored, one wait is
;selected
mov.b #00001011b,DRAMCONT ;Select 4MB and one wait
nop ;Inhibit instruction to access DRAM area
nop
•••

Setting the registers

The registers shown in Table 1.31.3 include indeterminate bit when read. Set immidiate to these regis-
ters.
Store the content of the frequently used register to RAM, change the content of RAM, then transfer to the
register.

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Table 1.31.3 The object registers

Register name Symbol Address
Watchdog timer start register WDTS 000E16
Group0 receive input register G0RI 00EC16
Group1 receive input register G1RI 012C16
Group2 SI/O transmit buffer register G2TB 016D16, 016C16
UART4 bit rate generator U4BRG 02F916
UART4 transfer buffer register U4TB 02FB16, 02FA16
Timer A1-1 register TA11 030316, 030216
Timer A2-1 register TA21 030516, 030416
Timer A4-1 register TA41 030716, 030616
Dead time timer DTT 030C16
Timer B2 interrupt occurrence frequency set counter ICTB2 030D16
UART3 bit rate generator U3BRG 032916
UART3 transfer buffer register U3TB 032B16, 032A16
UART2 bit rate generator U2BRG 033916
UART2 transfer buffer register U2TB 033B16, 033A16
Up-down flag UDF 034416
Timer A0 register (Note) TA0 034716, 034616
Timer A1 register (Note) TA1 034916, 034816
Timer A2 register (Note) TA2 034B16, 034A16
Timer A3 register (Note) TA3 034D16, 034C16
Timer A4 register (Note) TA4 034F16, 034E16
UART0 bit rate generator U0BRG 036916
UART0 transfer buffer register U0TB 036B16, 036A16
UART1 bit rate generator U1BRG 02E916
UART1 transfer buffer register U1TB 02EB16, 02EA16
A-D0 control register 2 ADCON2 039416
Note: In one-shot timer mode and pulse width modulation mode.

Notes on the microprocessor mode and transition after shifting from the micropro-
cessor mode to the memory expansion mode / single-chip mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed.
For that reason, the internal ROM area cannot be accessed.
After the reset has been released and the operation of shifting from the microprocessor mode has started
(“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the
memory expansion mode or single-chip mode.

Notes on CNVss pin reset at "H" level

When the CNVss pin is reset at "H" level, the contents of internal ROM cannot be read out.

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Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Electrical characteristics
Table 1.32.1. Absolute maximum ratings
Symbol Parameter Condition Rated value Unit
VCC Supply voltage VCC=AVCC -0.3 to 6.0 V
AVCC Analog supply voltage VCC=AVCC -0.3 to 6.0 V
______________
VI Input voltage RESET, CNVss, BYTE, P00-P07, P10-P17, -0.3 to Vcc+0.3 V
P20-P27, P30-P37, P40-P47, P50-P57, P60-
P67, P72-P77, P80-P87, P90-P97, P100-P107,
P110-P114, P120-P127, P130-P137, P140-
P146, P150-P157(Note1), VREF, XIN
P70, P71 -0.3 to 6.0 V
VO Output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40- -0.3 to Vcc+0.3 V
P47, P50-P57, P60-P67, P72-P77, P80-P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P13 7, P14 0-P14 6 , P15 0-P15 7(Note1) ,
VREF, XIN
P70, P71 -0.3 to 6.0 V
Pd Power dissipation Topr=25°C 500 mW
Topr Operating ambient temperature -20 to 85/-40 to 85(Note 2) °C
Tstg Storage temperature -65 to 150 °C

Note 1: Ports P11 to P15 exist in 144-pin version.

Note 2: Specify a product of -40 to 85°C to use it.

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Table 1.32.2. Recommended operating conditions (referenced to VCC = 3.0V to 5.5V at Topr = – 20
to 85oC / – 40 to 85oC(Note3) unless otherwise specified)
Standard
Symbol Parameter Unit
Min. Typ. Max.
VCC Supply voltage(When VDC-ON) 3.0 5.0 5.5 V
Supply voltage(When VDC-pass through) 3.0 3.3 3.6 V
AVCC Analog supply voltage VCC V
VSS Supply voltage 0 V
AVSS Analog supply voltage 0 V
VIH "H" input voltage P20 -P27, P3 0-P3 7, P40-P4 7, P50 -P5 7, P60-P6 7, P7 2- 0.8Vcc Vcc V
P77, P80-P87, P90-P97, P100-P107, P110-P114, P120-
P127, P130-P137, P140-P146, P150-P157(Note5), XIN,
____________
RESET, CNVss, BYTE
P70, P71 0.8Vcc 6.0 V
P00-P07, P10-P17 0.8Vcc Vcc V
(during single-chip mode)
P00-P07, P10-P17 0.5Vcc Vcc V
(during memory-expansion and microprocessor modes)
VIL "L" input voltage P20 -P27, P3 0-P3 7, P40-P4 7, P50 -P5 7, P60-P6 7, P7 0- 0 0.2Vcc V
P77, P80-P87, P90-P97, P100-P107, P110-P114, P120-
P127, P130-P137, P140-P146, P150-P157(Note5), XIN,
____________
RESET, CNVss, BYTE
P00-P07, P10-P17 0 0.2Vcc V
(during single-chip mode)
P00-P07, P10-P17 0 0.16Vcc V
(during memory-expansion and microprocessor modes)
IOH(peak) "H" peak output P00 -P07, P1 0-P1 7, P20-P2 7, P30 -P3 7, P40-P4 7, P5 0- -10.0 mA
current P5 7, P60-P6 7, P70-P7 7, P80-P8 4, P86, P8 7, P90-P9 7,
P100-P107, P110-P114, P120-P127, P130-P137, P140-
P146, P150-P157(Note5)
IOH(avg) "H" average P00 -P07, P1 0-P1 7, P20-P2 7, P30 -P3 7, P40-P4 7, P5 0- -5.0 mA
output current P5 7, P60-P6 7, P70-P7 7, P80-P8 4, P86, P8 7, P90-P9 7,
P100-P107, P110-P114, P120-P127, P130-P137, P140-
P146, P150-P157(Note5)
IOL(peak) "L" peak output P00 -P07, P1 0-P1 7, P20-P2 7, P30 -P3 7, P40-P4 7, P5 0- 10.0 mA
current P5 7, P60-P6 7, P70-P7 7, P80-P8 4, P86, P8 7, P90-P9 7,
P100-P107, P110-P114, P120-P127, P130-P137, P140-
P146, P150-P157(Note5)
IOL(avg) "L" average P00 -P07, P1 0-P1 7, P20-P2 7, P30 -P3 7, P40-P4 7, P5 0- 5.0 mA
output current P5 7, P60-P6 7, P70-P7 7, P80-P8 4, P86, P8 7, P90-P9 7,
P100-P107, P110-P114, P120-P127, P130-P137, P140-
P146, P150-P157(Note5)
f(XIN) Main clock input frequency VDC-ON Vcc=4.2 to 5.5V 0 30 MHz
Vcc=3.0 to 4.2V 0 20 MHz
VDC-pass through Vcc=3.0 to 3.6V 0 20 MHz
f(XCIN) Sub-clock oscillation frequency 32.768 kHz
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be 80mA max. The total
IOH (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be -80mA max. The total IOL (peak)
for ports P3, P4, P5, P6, P7,P80 to P84, P12 and P13 must be 80mA max. The total IOH (peak) for ports P3, P4,
P5, P6, P72 to P77, P80 to P84, P12 and P13 must be -80mA max.
Note 3: Specify a product of -40 to 85°C to use it.
Note 4: The specification of VIH and VIL of P87 is not when using as XCIN but when using programmable input port.
Note 5: Port P11 to P15 exist in 144-pin version.

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Electrical characteristics (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.32.3. Electrical characteristics (referenced to VCC=5V, VSS=0V at

Topr=25oC, f(XIN)=30MHZ unless otherwise specified)
VCC = 5V
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH "H" output voltage P00-P07, P10-P1 7, P20-P27, P30-P37, P40-P47, IOH=-5mA 3.0 V
P50-P57, P60-P67, P70-P7 7, P80-P84, P8 6, P87,
P9 0 -P9 7 , P10 0 -P10 7 , P11 0 -P11 4 , P12 0 -P12 7 ,
P130-P137, P140-P146, P150-P157(Note1)
VOH "H" output voltage P00-P07, P10-P1 7, P20-P27, P30-P37, P40-P47, IOH=-200µA 4.7 V
P50-P57, P60-P67, P70-P7 7, P80-P84, P8 6, P87,
P9 0 -P9 7 , P10 0 -P10 7 , P11 0 -P11 4 , P12 0 -P12 7 ,
P130-P137, P140-P146, P150-P157(Note1)
VOH "H" output voltage XOUT HIGH POWER IOH=-1mA 3.0 V
LOW POWER IOH=-0.5mA 3.0 V
"H" output voltage XCOUT No load applied 3.0 V
VOL "L" output voltage P00-P07, P10-P1 7, P20-P27, P30-P37, P40-P47, IOH=5mA 2.0 V
P50-P57, P60-P67, P70-P7 7, P80-P84, P8 6, P87,
P9 0 -P9 7 , P10 0 -P10 7 , P11 0 -P11 4 , P12 0 -P12 7 ,
P130-P137, P140-P146, P150-P157(Note1)
VOL "L" output voltage P00-P07, P10-P1 7, P20-P27, P30-P37, P40-P47, IOH=200µA 0.45 V
P50-P57, P60-P67, P70-P7 7, P80-P84, P8 6, P87,
P9 0 -P9 7 , P10 0 -P10 7 , P11 0 -P11 4 , P12 0 -P12 7 ,
P130-P137, P140-P146, P150-P157(Note1)
VOL "L" output voltage XOUT HIGH POWER IOL=1mA 2.0 V
LOW POWER IOL=0.5mA 2.0 V
"L" output voltage XCOUT No load applied 0 V
__________ _______ ________
VT+-VT- Hysteresis HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0- 0.2 1.0 V
________ ________ ________
INT5, AD TRG , CTS0-CTS4, CLK0-CLK4,
_______ ______ ______
TA0 OUT-TA4 OUT, NMI, KI0-KI3, RxD0-RxD4,
SCL0-SCL4, SDA0-SDA4
___________
VT+-VT- Hysteresis RESET 0.2 1.8 V
IIH "H" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=5V 5.0 µA
P50-P57, P60-P67, P72-P77, P80-P87, P90-P97,
P10 0 -P10 7 , P11 0 -P11 4 , P12 0 -P12 7 , P13 0 -
P137, P140-P146, P150-P157(Note1),
___________
XIN, RESET, CNVss, BYTE
IIL "L" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V -5.0 µA
P50-P57, P60-P67, P72-P77, P80-P87, P90-P97,
P10 0 -P10 7 , P11 0 -P11 4 , P12 0 -P12 7 , P13 0 -
P137, P140-P146, P150-P157(Note1),
___________
XIN, RESET, CNVss, BYTE
RPULLUP Pull-up resistance P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V 30 50 167 kΩ
P50-P57, P60-P67, P72-P77, P80-P84, P86, P87,
P90-P9 7, P100-P10 7, P110-P11 4, P120-P12 7,
P130-P137, P140-P146, P150-P157(Note1)
RfXIN Feedback resistance XIN 1.5 MΩ
RfXCIN Feedback resistance XCIN 10 MΩ
VRAM RAM retention voltage VDC-ON 2.5 V
ICC Power supply Measuring condition: f(XIN)=30MHz, square wave, no division 38 54 mA
current In sigle-chip mode, the out- f(XCIN)=32kHz, with WAIT instruction executed 470 µA
put pins are open and other
pins are Vss. when clock is stopped Topr=25oC 0.4 20 µA
Note 1: Port P11 to P15 exist in 144-pin version.

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Electrical characteristics (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V
Table 1.32.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS =
0V at Topr = 25oC, f(XIN) = 30MHZ unless otherwise specified)
Standard
Symbol Parameter Measuring condition Unit
Min. Typ. Max.
Resolution VREF = VCC 10 Bits
INL Integral nonlinearity error AN0 to AN7 LSB
VREF = ±3
ANEX0, ANEX1
VCC = 5V
External op-amp
±7 LSB
connection mode
DNL Differential nonlinearity error ±1 LSB
Offset error ±3 LSB
Gain error ±3 LSB
RLADDER Ladder resistance VREF = VCC 10 40 kΩ
tCONV Conversion time(10bit) 3.3 µs
tCONV Conversion time(8bit) 2.8 µs
tSAMP Sampling time 0.3 µs
VREF Reference voltage 2 VCC V
VIA Analog input voltage 0 VREF V
Note: Divide the frequency if f(XIN) exceeds 10 MHz, and make ØAD equal to or lower than 10 MHz.

Table 1.32.5. D-A conversion characteristics (referenced to VCC = VREF = 5V, VSS = AVSS = 0V
at Topr = 25oC, f(XIN) = 30MHZ unless otherwise specified)
Standard
Symbol Parameter Measuring condition Min. Typ. Max. Unit
Resolution 8 Bits
Absolute accuracy 1.0 %
tsu Setup time 3 µs
RO Output resistance 4 10 20 kΩ
IVREF Reference power supply input current (Note) 1.5 mA
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
“0016”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register 1, IVREF is sent.

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Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified)

Table 1.32.6. External clock input

Standard
Symbol Parameter Unit
Min. Max.
tc External clock input cycle time 33 ns
tw(H) External clock input HIGH pulse width 13 ns
tw(L) External clock input LOW pulse width 13 ns
tr External clock rise time 5 ns
tf External clock fall time 5 ns

Table 1.32.7. Memory expansion and microprocessor modes

Standard
Symbol Parameter Unit
Min. Max.
tac1(RD-DB) Data input access time (RD standard, no wait) (Note) ns
tac1(AD-DB) Data input access time (AD standard, CS standard, no wait) (Note) ns
tac2(RD-DB) Data input access time (RD standard, with wait) (Note) ns
tac2(AD-DB) Data input access time (AD standard, CS standard, with wait) (Note) ns
tac3(RD-DB) Data input access time (RD standard, when accessing multiplex bus area) (Note) ns
tac3(AD-DB) Data input access time (AD standard, CS standard, when accessing (Note) ns
multiplex bus area)
tac4(RAS-DB) Data input access time (RAS standard, DRAM access) (Note) ns
tac4(CAS-DB) Data input access time (CAS standard, DRAM access) (Note) ns
tac4(CAD-DB) Data input access time (CAD standard, DRAM access) (Note) ns
tsu(DB-BCLK) Data input setup time 26 ns
tsu(RDY-BCLK ) RDY input setup time 26 ns
tsu(HOLD-BCLK ) HOLD input setup time 30 ns
th(RD-DB) Data input hold time 0 ns
th(CAS -DB) Data input hold time 0 ns
th(BCLK -RDY) RDY input hold time 0 ns
th(BCLK-HOLD ) HOLD input hold time 0 ns
td(BCLK-HLDA ) HLDA output delay time 25 ns
Note: Calculated according to the BCLK frequency as follows:
Note that inserting wait or using lower operation frequency f(BCLK) is needed when
calculated value is negative.
10 9
tac1(RD – DB) = – 35 [ns]
f(BCLK) X 2
9
10
tac1(AD – DB) = – 35 [ns]
f(BCLK)

10 9X m
tac2(RD – DB) = – 35 [ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively)
f(BCLK) X 2
9
10 X n
tac2(AD – DB) = – 35 [ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively)
f(BCLK)
9
10 X m
tac3(RD – DB) = – 35 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
f(BCLK) X 2
9
10 X n
tac3(AD – DB) = – 35 [ns] (n=5 and 7 when 2 wait and 3 wait, respectively)
f(BCLK) X 2
9
10 X m
tac4(RAS – DB) = – 35 [ns] (m=3 and 5 when 1 wait and 2 wait, respectively)
f(BCLK) X 2
9
10 X n
tac4(CAS – DB) = – 35 [ns] (n=1 and 3 when 1 wait and 2 wait, respectively)
f(BCLK) X 2
9
10 X l [ns] (l=1 and 2 when 1 wait and 2 wait, respectively)
tac4(CAD – DB) = – 35
f(BCLK)

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Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified)

Table 1.32.8. Timer A input (count input in event counter mode)

Standard
Symbol Parameter Min. Max. Unit
tc(TA) TAiIN input cycle time 100 ns
tw(TAH) TAiIN input HIGH pulse width 40 ns
tw(TAL) TAiIN input LOW pulse width 40 ns

Table 1.32.9. Timer A input (gating input in timer mode)

Standard
Symbol Parameter Min. Max. Unit
tc(TA) TAiIN input cycle time 400 ns
tw(TAH) TAiIN input HIGH pulse width 200 ns
tw(TAL) TAiIN input LOW pulse width 200 ns

Table 1.32.10. Timer A input (external trigger input in one-shot timer mode)
Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 200 ns
tw(TAH) TAiIN input HIGH pulse width 100 ns
tw(TAL) TAiIN input LOW pulse width 100 ns

Table 1.32.11. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol Parameter Min. Max. Unit
tw(TAH) TAiIN input HIGH pulse width 100 ns
tw(TAL) TAiIN input LOW pulse width 100 ns

Table 1.32.12. Timer A input (up/down input in event counter mode)

Standard
Symbol Parameter Min. Max. Unit
tc(UP) TAiOUT input cycle time 2000 ns
tw(UPH) TAiOUT input HIGH pulse width 1000 ns
tw(UPL) TAiOUT input LOW pulse width 1000 ns
tsu(UP-TIN) TAiOUT input setup time 400 ns
th(TIN-UP) TAiOUT input hold time 400 ns

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Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified)

Table 1.32.13. Timer B input (count input in event counter mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time (counted on one edge) 100 ns
tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 40 ns
tw(TBL) TBiIN input LOW pulse width (counted on one edge) 40 ns
tc(TB) TBiIN input cycle time (counted on both edges) 200 ns
tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 80 ns
tw(TBL) TBiIN input LOW pulse width (counted on both edges) 80 ns

Table 1.28.14. Timer B input (pulse period measurement mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time 400 ns
tw(TBH) TBiIN input HIGH pulse width 200 ns
tw(TBL) TBiIN input LOW pulse width 200 ns

Table 1.32.15. Timer B input (pulse width measurement mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time 400 ns
tw(TBH) TBiIN input HIGH pulse width 200 ns
tw(TBL) TBiIN input LOW pulse width 200 ns

Table 1.32.16. A-D trigger input

Standard
Symbol Parameter Unit
Min. Max.
tc(AD) ADTRG input cycle time (trigger able minimum) 1000 ns
tw(ADL) ADTRG input LOW pulse width 125 ns

Table 1.32.17. Serial I/O

Standard
Symbol Parameter Unit
Min. Max.
tc(CK) CLKi input cycle time 200 ns
tw(CKH) CLKi input HIGH pulse width 100 ns
tw(CKL) CLKi input LOW pulse width 100 ns
td(C-Q) TxDi output delay time 80 ns
th(C-Q) TxDi hold time 0 ns
tsu(D-C) RxDi input setup time 30 ns
th(C-D) RxDi input hold time 90 ns

_______
Table 1.32.18. External interrupt INTi inputs
Standard
Symbol Parameter Unit
Min. Max.
tw(INH) INTi input HIGH pulse width 250 ns
tw(INL) INTi input LOW pulse width 250 ns

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Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC, CM15 = “1” unless
otherwise specified)

Table 1.32.19. Memory expansion mode and microprocessor mode (no wait)
Standard
Symbol Parameter Measuring condition Unit
Min. Max.
td(BCLK-AD) Address output delay time 18 ns
th(BCLK-AD) Address output hold time (BCLK standard) -3 ns
th(RD-AD) Address output hold time (RD standard) 0 ns
th(WR-AD) Address output hold time (WR standard) (Note) ns
td(BCLK-CS) Chip select output delay time 18 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) -3 ns
th(RD-CS) Chip select output hold time (RD standard) 0 ns
th(WR-CS) Chip select output hold time (WR standard) Figure 1.32.1 (Note) ns
td(BCLK-ALE) ALE signal output delay time 18 ns
th(BCLK-ALE) ALE signal output hold time –2 ns
td(BCLK-RD) RD signal output delay time 18 ns
th(BCLK-RD) RD signal output hold time -5 ns
td(BCLK-WR) WR signal output delay time 18 ns
th(BCLK-WR) WR signal output hold time -3 ns
td(DB-WR) Data output delay time (WR standard) (Note) ns
th(WR-DB) Data output hold time (WR standard) (Note) ns
tw(WR) WR signal width (Note) ns

Note: Calculated according to the BCLK frequency as follows:

10 9
td(DB – WR) = – 20
f(BCLK) [ns]
9
10
th(WR – DB) = – 10
f(BCLK) X 2 [ns]
9
10
th(WR – AD) = – 10
f(BCLK) X 2 [ns]
9
10
th(WR – CS) = – 10
f(BCLK) X 2 [ns]
9
10
tw(WR) = – 15
f(BCLK) X 2 [ns]

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Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise
specified)

Table 1.32.20. Memory expansion mode and microprocessor mode

(with wait, accessing external memory)
Standard
Symbol Parameter Measuring condition Unit
Min. Max.
td(BCLK-AD) Address output delay time 18 ns
th(BCLK-AD) Address output hold time (BCLK standard) –3 ns
th(RD-AD) Address output hold time (RD standard) 0 ns
th(WR-AD) Address output hold time (WR standard) (Note) ns
td(BCLK-CS) Chip select output delay time 18 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) –3 ns
th(RD-CS) Chip select output hold time (RD standard) 0 ns
th(WR-CS) Chip select output hold time (WR standard) (Note) ns
Figure 1.32.1
td(BCLK-ALE) ALE signal output delay time 18 ns
th(BCLK-ALE) ALE signal output hold time –2 ns
td(BCLK-RD) RD signal output delay time 18 ns
th(BCLK-RD) RD signal output hold time –5 ns
td(BCLK-WR) WR signal output delay time 18 ns
th(BCLK-WR) WR signal output hold time –3 ns
td(DB-WR) Data output delay time (WR standard) (Note) ns
th(WR-DB) Data output hold time (WR standard) (Note) ns
tw(WR) WR signal width (Note) ns

Note: Calculated according to the BCLK frequency as follows:

10 9 X n
td(DB – WR) = – 20
f(BCLK) [ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively)
9
10
th(WR – DB) = – 10
f(BCLK) X 2 [ns]
9
10
th(WR – AD) = – 10
f(BCLK) X 2 [ns]
9
10
th(WR – CS) = – 10
f(BCLK) X 2 [ns]

10 9 X n
tw( WR) = – 15
f(BCLK) X 2 [ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively)

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Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise
specified)

Table 1.32.21. Memory expansion mode and microprocessor mode

(with wait, accessing external memory, multiplex bus area selected)
Standard
Symbol Parameter Measuring condition Unit
Min. Max.
td(BCLK-AD) Address output delay time 18 ns
th(BCLK-AD) Address output hold time (BCLK standard) -3 ns
th(RD-AD) Address output hold time (RD standard) (Note) ns
th(WR-AD) Address output hold time (WR standard) (Note) ns
td(BCLK-CS) Chip select output delay time 18 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) -3 ns
th(RD-CS) Chip select output hold time (RD standard) (Note) ns
th(WR-CS) Chip select output hold time (WR standard) Figure 1.32.1 (Note) ns
td(BCLK-RD) RD signal output delay time 18 ns
th(BCLK-RD) RD signal output hold time -5 ns
td(BCLK-WR) WR signal output delay time 18 ns
th(BCLK-WR) WR signal output hold time -3 ns
td(DB-WR) Data output delay time (WR standard) (Note) ns
th(WR-DB) Data output hold time (WR standard) (Note) ns
td(BCLK-ALE) ALE signal output delay time (BCLK standard) 18 ns
th(BCLK-ALE) ALE signal output hold time (BCLK standard) –2 ns
td(AD-ALE) ALE signal output delay time (address standard) (Note) ns
th(ALE-AD) ALE signal output hold time (address standard) (Note) ns
tdz(RD-AD) Address output flowting start time 8 ns

Note: Calculated according to the BCLK frequency as follows:

10 9
th(RD – AD) = – 10
f(BCLK) X 2 [ns]
10 9
th(WR – AD) = – 10
f(BCLK) X 2 [ns]
10 9
th(RD – CS) = – 10
f(BCLK) X 2 [ns]
10 9
th(WR – CS) = – 10
f(BCLK) X 2 [ns]
9
10 X m
td(DB – WR) = – 25
f(BCLK) X 2 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
9
10
th(WR – DB) = – 10
f(BCLK) X 2 [ns]
9
10
td(AD – ALE) = – 20
f(BCLK) X 2 [ns]

9
10
th(ALE – AD) = – 10
f(BCLK) X 2 [ns]

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Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise
specified)

Table 1.32.22. Memory expansion mode and microprocessor mode

(with wait, accessing external memory, DRAM area selected)
Measuring Standard
Symbol Parameter Unit
condition Min. Max.
td(BCLK-RAD) Row address output delay time 18 ns
th(BCLK-RAD) Row address output hold time (BCLK standard) -3 ns
td(BCLK-CAD) String address output delay time 18 ns
th(BCLK-CAD) String address output hold time (BCLK standard) -3 ns
th(RAS-RAD) Row address output hold time after RAS output (Note) ns
td(BCLK-RAS) RAS output delay time (BCLK standard) 18 ns
th(BCLK-RAS) RAS output hold time (BCLK standard) Figure 1.32.1 -3 ns
tRP RAS "H" hold time (Note) ns
td(BCLK-CAS) CAS output delay time (BCLK standard) 18 ns
th(BCLK-CAS) CAS output hold time (BCLK standard) -3 ns
td(BCLK-DW) DW output delay time (BCLK standard) 18 ns
th(BCLK-DW) DW output hold time (BCLK standard) -5 ns
tsu(DB-CAS) CAS output setup time after DB output (Note) ns
th(BCLK-DB) DB signal output hold time (BCLK standard) -7 ns
tsu(CAS-RAS) CAS output setup time before RAS output (refresh) (Note) ns
Note: Calculated according to the BCLK frequency as follows:

10 9
th(RAS – RAD) = – 13
f(BCLK) X 2 [ns]

10 9
tRP = X 3 – 20 [ns]
f(BCLK) X 2
10 9
tsu(DB – CAS) = – 20
f(BCLK) [ns]
9
10
tsu(CAS – RAS) = – 13
f(BCLK) X 2 [ns]

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Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

P0
P1
P2 30pF
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15

Figure 1.32.1. Port P0 to P15 measurement circuit

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Timing (Vcc = 5V)

Vcc=5V
Memory Expansion Mode and Microprocessor Mode (without wait)
Read Timing

BCLK
td(BCLK-ALE) th(BCLK-ALE)
18ns.max -2ns.min
ALE
td(BCLK-CS) th(BCLK-CS)
*1 -3ns.min
18ns.max
CSi
tcyc th(RD-CS)
0ns.min
td(BCLK-AD) th(BCLK-AD)
18ns.max*1 -3ns.min
ADi
BHE
td(BCLK-RD) th(RD-AD)
18ns.max 0ns.min
RD
tac1(RD-DB)*2 th(BCLK-RD)
-5ns.min
tac1(AD-DB)*2
Hi-Z
DB
tsu(DB-BCLK) th(RD-DB)
26ns.min*1 0ns.min
*1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK).
*2:It depends on operation frequency.
tac1(RD-DB)=(tcyc/2-35)ns.max
tac1(AD-DB)=(tcyc-35)ns.max

Write Timing ( Written by 2 cycles in selecting no wait)

BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE

td(BCLK-CS) th(BCLK-CS)
18ns.max -3ns.min
CSi
tcyc th(WR-CS)*3
td(BCLK-AD) th(BCLK-AD)
18ns.max -3ns.min
ADi
BHE
td(BCLK-WR) th(WR-AD)*3
tw(WR)*3
18ns.max
WR,WRL,
WRH th(BCLK-WR)
-3ns.min
td(DB-WR)*3 th(WR-DB)*3

DBi

*3:It depends on operation frequency. Measuring conditions

td(DB-WR)=(tcyc-20)ns.min
th(WR-DB)=(tcyc/2-10)ns.min • VCC=5V±10%
th(WR-AD)=(tcyc/2-10)ns.min • Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
th(WR-CS)=(tcyc/2-10)ns.min • Output timing voltage :Determined with VOH=2.0V, VOL=0.8V
tw(WR)=(tcyc/2-15)ns.min

Figure 1.32.2. VCC=5V timing diagram (1)

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Timing (Vcc = 5V)

Vcc=5V
Memory Expansion Mode and Microprocessor Mode (with wait)
Read Timing
BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS) th(BCLK-CS)
18ns.max*1 -3ns.min
CSi
tcyc th(RD-CS)
0ns.min
td(BCLK-AD) th(BCLK-AD)
18ns.max*1 -3ns.min
ADi
BHE
td(BCLK-RD) th(RD-AD)
18ns.max 0ns.min
RD
th(BCLK-RD)
tac2(RD-DB)*2 -5ns.min
tac2(AD-DB)*2
DB
Hi-Z
tsu(DB-BCLK) th(RD-DB)
26ns.min*1 0ns.min

*1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK).

*2:It depends on operation frequency.
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)

Write Timing ( Written by 2 cycles in selecting no wait)

BCLK 18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
ALE

td(BCLK-CS) th(BCLK-CS)
18ns.max -3ns.min
CSi
tcyc th(WR-CS)*3
td(BCLK-AD) th(BCLK-AD)
18ns.max -3ns.min
ADi
BHE
td(BCLK-WR) tw(WR)*3 th(WR-AD)*3
18ns.max
WR,WRL,
WRH th(BCLK-WR)
-3ns.min
td(DB-WR)*3 th(WR-DB)*3
DBi

*3:It depends on operation frequency. Measuring conditions

td(DB-WR)=(tcyc x n-20)ns.min • VCC=5V±10%
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) • Input timing voltage
th(WR-DB)=(tcyc/2-10)ns.min :Determined with VIH=2.5V, VIL=0.8V
th(WR-AD)=(tcyc/2-10)ns.min • Output timing voltage
th(WR-CS)=(tcyc/2-10)ns.min :Determined with VOH=2.0V, VOL=0.8V
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)

Figure 1.32.3. VCC=5V timing diagram (2)

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Timing (Vcc = 5V)

Memory Expansion Mode and Microprocessor Mode Vcc=5V

(When accessing external memory area with wait, and select multiplexed bus))
Read Timing
BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS) tcyc th(BCLK-CS)
18ns.max -3ns.min

CSi
th(RD-CS)*1

td(AD-ALE)*1 th(ALE-AD)*1
ADi Address Data input Address
/DBi tdz(RD-AD) th(RD-DB)
8ns.max
td(BCLK-AD) tsu(DB-BCLK) 0ns.min
26ns.min
th(BCLK-AD)
18ns.max tac3(RD-DB)*1 -3ns.min
ADi
BHE
tac3(AD-DB)*1 td(BCLK-RD) th(BCLK-RD) th(RD-AD)*1
18ns.max -5ns.min
RD

*1:It depends on operation frequency.

td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.)
tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.)
Write Timing (Written by 2 cycles in selecting no wait)
BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE

tcyc th(BCLK-CS)
td(BCLK-CS) th(WR-CS)*2 -3ns.min
18ns.max
CSi

td(AD-ALE)*2 th(ALE-AD)*2
ADi Address Data output Address
/DBi
td(DB-WR)*2 th(WR-DB)*2
td(BCLK-AD) th(BCLK-AD)
18ns.max -3ns.min
ADi
BHE

td(BCLK-WR) th(BCLK-WR) th(WR-AD)*2

18ns.max -3ns.min
WR,WRL,
WRH

*2:It depends on operation frequency. Measuring conditions

td(AD-ALE)=(tcyc/2-20)ns.min • VCC=5V±10%
th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min • Input timing voltage
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min :Determined with VIH=2.5V, VIL=0.8V
td(DB-WR)=(tcyc/2 x m-25)ns.min • Output timing voltage
(m=3 and 5 when 2 wait and 3 wait, respectively.) :Determined with VOH=2.0V, VOL=0.8V
Figure 1.32.4. VCC=5V timing diagram (3)

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Timing (Vcc = 5V)

Memory Expansion Mode and Microprocessor Mode Vcc=5V

(When accessing DRAM area)
Read Timing
BCLK
tcyc
td(BCLK-CAD)
td(BCLK-RAD) th(BCLK-RAD) th(BCLK-CAD)
18ns.max*1
18ns.max -3ns.min -3ns.min
MAi Row address String address

th(RAS-RAD)*2 tRP*2

RAS
td(BCLK-RAS) th(BCLK-RAS)
td(BCLK-CAS) -3ns.min
18ns.max*1 18ns.max*1
CASL
CASH th(BCLK-CAS)
-3ns.min

DW
tac4(CAS-DB)*2
tac4(CAD-DB)*2
tac4(RAS-DB)*2
Hi-Z
DB
tsu(DB-BCLK) th(CAS-DB)
26ns.min*1 0ns.min

*1:It is a guarantee value with being alone. 35ns.max garantees as follows:

td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)

*2:It depends on operation frequency.

tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min

Measuring conditions
• VCC=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V

Figure 1.32.5. VCC=5V timing diagram (4)

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Timing (Vcc = 5V)

Memory Expansion Mode and Microprocessor Mode Vcc=5V

(When accessing DRAM area)
Write Timing
BCLK
tcyc

td(BCLK-RAD) td(BCLK-CAD)
th(BCLK-RAD) th(BCLK-CAD)
18ns.max 18ns.max -3ns.min
-3ns.min
MAi Row address String address

th(RAS-RAD)*1 tRP*1
RAS
td(BCLK-RAS) td(BCLK-CAS) th(BCLK-RAS)
18ns.max -3ns.min
18ns.max
CASL
CASH
th(BCLK-CAS)
td(BCLK-DW) -3ns.min
18ns.max
DW
th(BCLK-DW)
-5ns.min
tsu(DB-CAS)*1
Hi-Z
DB
th(BCLK-DB)
-7ns.min

*1:It depends on operation frequency.

th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
tsu(DB-CAS)=(tcyc-20)ns.min

Measuring conditions
• VCC=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V

Figure 1.32.6. VCC=5V timing diagram (5)

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Timing (Vcc = 5V)

Memory expansion Mode and Microprocessor Mode Vcc=5V

Refresh Timing (CAS before RAS refresh)

BCLK

tcyc
td(BCLK-RAS)
18ns.max
RAS
th(BCLK-RAS)
tsu(CAS-RAS)*1 -3ns.min

CASL
CASH td(BCLK-CAS) th(BCLK-CAS)
-3ns.min
18ns.max

DW

*1:It depends on operation frequency.

tsu(CAS-RAS)=(tcyc/2-13)ns.min

Refresh Timing (Self-refresh)

BCLK

td(BCLK-RAS) tcyc
18ns.max
RAS
th(BCLK-RAS)
tsu(CAS-RAS)*1 -3ns.min

CASL
CASH th(BCLK-CAS)
td(BCLK-CAS) -3ns.min
18ns.max

DW

*1:It depends on operation frequency.

tsu(CAS-RAS)=(tcyc/2-13)ns.min

Measuring conditions
• VCC=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V

Figure 1.32.7. VCC=5V timing diagram (6)

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Timing (Vcc = 5V)

tc(TA)
tw(TAH)

TAiIN input
tw(TAL)

tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)

TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling th(TIN–UP) tsu(UP–TIN)
edge is selected)

TAiIN input
(When count on rising
edge is selected)
tc(TB)
tw(TBH)

TBiIN input
tw(TBL)

tc(AD)
tw(ADL)

ADTRG input

tc(CK)
tw(CKH)

CLKi
tw(CKL)
th(C–Q)

TxDi
td(C–Q) tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi input
tw(INH)

Figure 1.32.8. VCC=5V timing diagram (7)

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Timing (Vcc = 5V)

Memory Expansion Mode and Microprocessor Mode

(Valid only with wait)

BCLK

RD
(Separate bus)

WR, WRL, WRH

(Separate bus)

RD
(Multiplexed bus)

WR, WRL, WRH

(Multiplexed bus)

RDY input

tsu(RDY–BCLK) th(BCLK–RDY)

(Valid with or without wait)

BCLK

tsu(HOLD–BCLK) th(BCLK–HOLD)

HOLD input

HLDA output
td(BCLK–HLDA) td(BCLK–HLDA)
P0, P1, P2, Hi–Z
P3, P4,
P50 to P52

Note: Regardless of the level of the BYTE pin input and the setting of the port P40 to
P43 function select bit (PM06) of the processor mode register 0, all ports above
become the high-impedance state.

Measuring conditions :
• VCC=5V±10%
• Input timing voltage : Determined with VIH=4.0V, VIL=1.0V
• Output timing voltage : Determined with VOH=2.5V, VOL=2.5V

Figure 1.32.9. VCC=5V timing diagram (8)

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Electrical characteristics (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Electrical characteristics (Vcc = 3V)

Table 1.32.23. Electrical characteristics (referenced to VCC=3.3V, VSS=0V at VCC = 3V
Topr=25oC, f(XIN)=20MHZ unless otherwise specified)
Standard
Symbol Parameter Condition Unit
Min. Typ. Max.
VOH "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOH=-1mA 2.7 V
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
P9 0-P9 7, P10 0-P10 7, P110 -P114 , P120-P12 7,
P130-P137, P140-P146, P150-P157(Note1)
VOH "H" output voltage XOUT HIGH POWER IOH=-0.1mA 2.7 V
LOW POWER IOH=-50µA 2.7 V
"H" output voltage XCOUT No load applied 3.0 V
VOL "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOL=1mA 0.5
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
P9 0-P9 7, P10 0-P10 7, P110 -P114 , P120-P12 7,
P130-P137, P140-P146, P150-P157(Note1)
VOL "L" output voltage XOUT HIGH POWER IOL=0.1mA 0.5 V
LOW POWER IOL=50µA 0.5 V
"L" output voltage XCOUT No load applied 0 V
__________ _______ ________
VT+-VT- Hysteresis HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0- 0.2 1.0 V
________ ________ ________
INT5, AD TRG , CTS0-CTS4, CLK0-CLK4,
_______ ______ ______
TA0 OUT-TA4 OUT, NMI, KI0-KI3, RxD0-RxD4,
SCL0-SCL4, SDA0-SDA4
___________
VT+-VT- Hysteresis RESET 0.2 1.8 V
IIH "H" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=3V 4.0 µA
P50-P57, P60-P67, P72-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(Note1),
___________
XIN, RESET, CNVss, BYTE
IIL "L" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V -4.0 µA
P50-P57, P60-P67, P72-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(Note1),
___________
XIN, RESET, CNVss, BYTE
RPULLUP Pull-up resistance P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V 66 120 500 kΩ
P50-P57, P60-P67, P72-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110Å`P114, P120-P127,
P130-P137, P140-P146, P150-P157(Note1)
RfXIN Feedback resistance XIN 3.0 MΩ
RfXCIN Feedback resistance XCIN 20.0 MΩ
VRAM RAM retention voltage VDC-ON 2.5 V
VDC-pass through 2.0 V
ICC Power supply Measuring condition: f(XIN)=20MHz, square wave, no division 26 38 mA
current In sigle-chip mode, f(XCIN)=32kHz, with WAIT, VDC-pass through 5.0 µA
the output pins are
open and other pins f(XCIN)=32kHz, with WAIT, VDC-ON 340 µA
are Vss. when clock is stopped Topr=25oC 0.4 20 µA
Note 1: Port P11 to P15 exist in 144-pin version.

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Electrical characteristics (Vcc = 3V)

VCC = 3V
Table 1.32.24. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS =
0V at Topr = 25oC, f(XIN) = 20MHZ unless otherwise specified)
Standard
Symbol Parameter Measuring condition Unit
Min. Typ. Max
Resolution VREF = VCC 10 Bits
ISL Integral nonlinearity error No S&H function(8-bit) ±2 LSB
DSL Differential nonlinearity error No S&H function(8-bit) ±1 LSB
Offset error No S&H function(8-bit) ±2 LSB
Gain error No S&H function(8-bit) ±2 LSB
RLADDER Ladder resistance VREF = VCC 10 40 kΩ
tCONV Conversion time(8bit) 9.8 µs
VREF Reference voltage 2.7 VCC V
VIA Analog input voltage 0 VREF V
S&H: Sample and hold
Note: Divide the frequency if f(XIN) exceeds 10 MHz, and make ØAD equal to or lower than 10 MHz.

Table 1.32.25. D-A conversion characteristics (referenced to VCC = VREF = 3V, VSS = AVSS = 0V,
at Topr = 25oC, f(XIN) = 20MHZ unless otherwise specified)
Standard
Symbol Parameter Measuring condition Min. Typ. Max Unit
Resolution 8 Bits
Absolute accuracy 1.0 %
tsu Setup time 3 µs
RO Output resistance 4 10 20 kΩ
IVREF Reference power supply input current (Note) 1.0 mA
Note :This applies when using one D-A converter, with the D-A register for the unused D-A converter
set to “0016”. The A-D converter's ladder resistance is not included.
Also, the Vref is unconnected at the A-D control register 1, IVREF is sent.

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Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified)
Table 1.32.26. External clock input
Standard
Symbol Parameter Unit
Min. Max.
tc External clock input cycle time 50 ns
tw(H) External clock input HIGH pulse width 22 ns
tw(L) External clock input LOW pulse width 22 ns
tr External clock rise time 5 ns
tf External clock fall time 5 ns

Table 1.32.27. Memory expansion and microprocessor modes

Symbol Parameter Standard Unit
Min. Max.
tac1(RD-DB) Data input access time (RD standard, no wait) (Note) ns
tac1(AD-DB) Data input access time (AD standard, CS standard, no wait) (Note) ns
tac2(RD-DB) Data input access time (RD standard, with wait) (Note) ns
tac2(AD-DB) Data input access time (AD standard, CS standard, with wait) (Note) ns
tac3(RD-DB) Data input access time (RD standard, when accessing multiplex bus area) (Note) ns
tac3(AD-DB) Data input access time (AD standard, CS standard, when accessing (Note) ns
multiplex bus area)
tac4(RAS-DB) Data input access time (RAS standard, DRAM access) (Note) ns
tac4(CAS-DB) Data input access time (CAS standard, DRAM access) (Note) ns
tac4(CAD-DB) Data input access time (CAD standard, DRAM access) (Note) ns
tsu(DB-BCLK) Data input setup time 30 ns
tsu(RDY-BCLK ) RDY input setup time 40 ns
tsu(HOLD-BCLK ) HOLD input setup time 60 ns
th(RD-DB) Data input hold time 0 ns
th(CAS-DB) Data input hold time 0 ns
th(BCLK -RDY) RDY input hold time 0 ns
th(BCLK-HOLD ) HOLD input hold time 0 ns
td(BCLK-HLDA ) HLDA output delay time 25 ns
Note: Calculated according to the BCLK frequency as follows:
Note that inserting wait or using lower operation frequency f(BCLK) is needed when
calculated value is negative.
9
10
tac1(RD – DB) = – 35 [ns]
f(BCLK) X 2
10 9
tac1(AD – DB) = – 35 [ns]
f(BCLK)

10 9X m
tac2(RD – DB) = – 35 [ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively)
f(BCLK) X 2
10 9 X n
tac2(AD – DB) = – 35 [ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively)
f(BCLK)
10 9 X m
tac3(RD – DB) = – 35 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
f(BCLK) X 2
9
10 X n
tac3(AD – DB) = – 35 [ns] (n=5 and 7 when 2 wait and 3 wait, respectively)
f(BCLK) X 2
9
10 X m
tac4(RAS – DB) = – 35 [ns] (m=3 and 5 when 1 wait and 2 wait, respectively)
f(BCLK) X 2
9
10 X n
tac4(CAS – DB) = – 35 [ns] (n=1 and 3 when 1 wait and 2 wait, respectively)
f(BCLK) X 2
9
10 X l [ns] (l=1 and 2 when 1 wait and 2 wait, respectively)
tac4(CAD – DB) = – 35
f(BCLK)

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Timing (Vcc = 3V)

VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified)

Table 1.32.28. Timer A input (counter input in event counter mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 100 ns
tw(TAH) TAiIN input HIGH pulse width 40 ns
tw(TAL) TAiIN input LOW pulse width 40 ns

Table 1.32.29. Timer A input (gating input in timer mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 400 ns
tw(TAH) TAiIN input HIGH pulse width 200 ns
tw(TAL) TAiIN input LOW pulse width 200 ns

Table 1.32.30. Timer A input (external trigger input in one-shot timer mode)
Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 200 ns
tw(TAH) TAiIN input HIGH pulse width 100 ns
tw(TAL) TAiIN input LOW pulse width 100 ns

Table 1.32.31. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol Parameter Unit
Min. Max.
tw(TAH) TAiIN input HIGH pulse width 100 ns
tw(TAL) TAiIN input LOW pulse width 100 ns

Table 1.32.32. Timer A input (up/down input in event counter mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(UP) TAiOUT input cycle time 2000 ns
tw(UPH) TAiOUT input HIGH pulse width 1000 ns
tw(UPL) TAiOUT input LOW pulse width 1000 ns
tsu(UP-TIN) TAiOUT input setup time 400 ns
th(TIN-UP) TAiOUT input hold time 400 ns

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Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified)

Table 1.32.33. Timer B input (counter input in event counter mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time (counted on one edge) 100 ns
tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 40 ns
tw(TBL) TBiIN input LOW pulse width (counted on one edge) 40 ns
tc(TB) TBiIN input cycle time (counted on both edges) 200 ns
tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 80 ns
tw(TBL) TBiIN input LOW pulse width (counted on both edges) 80 ns

Table 1.32.34. Timer B input (pulse period measurement mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time 400 ns
tw(TBH) TBiIN input HIGH pulse width 200 ns
tw(TBL) TBiIN input LOW pulse width 200 ns

Table 1.32.35. Timer B input (pulse width measurement mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time 400 ns
tw(TBH) TBiIN input HIGH pulse width 200 ns
tw(TBL) TBiIN input LOW pulse width 200 ns

Table 1.32.36. A-D trigger input

Standard
Symbol Parameter Unit
Min. Max.
tc(AD) ADTRG input cycle time (trigger able minimum) 1000 ns
tw(ADL) ADTRG input LOW pulse width 125 ns

Table 1.32.37. Serial I/O

Standard
Symbol Parameter Unit
Min. Max.
tc(CK) CLKi input cycle time 200 ns
tw(CKH) CLKi input HIGH pulse width 100 ns
tw(CKL) CLKi input LOW pulse width 100 ns
td(C-Q) TxDi output delay time 80 ns
th(C-Q) TxDi hold time 0 ns
tsu(D-C) RxDi input setup time 30 ns
th(C-D) RxDi input hold time 90 ns

_______
Table 1.32.38. External interrupt INTi inputs
Standard
Symbol Parameter Unit
Min. Max.
tw(INH) INTi input HIGH pulse width 250 ns
tw(INL) INTi input LOW pulse width 250 ns

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Timing (Vcc = 3V)

VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC, CM15="1" unless
otherwise specified)

Table 1.32.39. Memory expansion and microprocessor modes (with no wait)

Standard
Symbol Parameter Measuring condition Unit
Min. Max.
td(BCLK-AD) Address output delay time 18 ns
th(BCLK-AD) Address output hold time (BCLK standard) 0 ns
th(RD-AD) Address output hold time (RD standard) 0 ns
th(WR-AD) Address output hold time (WR standard) (Note) ns
td(BCLK-CS) Chip select output delay time 18 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) 0 ns
th(RD-CS) Chip select output hold time (RD standard) 0 ns
th(WR-CS) Chip select output hold time (WR standard) (Note) ns
td(BCLK-ALE) ALE signal output delay time 18 ns
th(BCLK-ALE) ALE signal output hold time Figure 1.32.1 –2 ns
td(BCLK-RD) RD signal output delay time 18 ns
th(BCLK-RD) RD signal output hold time –3 ns
td(BCLK-WR) WR signal output delay time 18 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(DB-WR) Data output delay time (WR standard) (Note) ns
th(WR-DB) Data output hold time (WR standard) (Note) ns
tw(WR) Write pulse width (Note) ns
Note: Calculated according to the BCLK frequency as follows:
10 9
td(DB – WR) = – 20
f(BCLK) [ns]
10 9
th(WR – DB) = – 10
f(BCLK) X 2 [ns]
9
10
th(WR – AD) = – 10
f(BCLK) X 2 [ns]
9
10
th(WR – CS) = – 10
f(BCLK) X 2 [ns]
9
10
tw(WR) = – 15
f(BCLK) X 2 [ns]

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Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise
specified)

Table 1.32.40. Memory expansion and microprocessor modes

(with wait, accessing external memory)
Standard
Symbol Parameter Measuring condition Unit
Min. Max.
td(BCLK-AD) Address output delay time 18 ns
th(BCLK-AD) Address output hold time (BCLK standard) 0 ns
th(RD-AD) Address output hold time (RD standard) 0 ns
th(WR-AD) Address output hold time (WR standard) (Note) ns
td(BCLK-CS) Chip select output delay time 18 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) 0 ns
th(RD-CS) Chip select output hold time (RD standard) 0 ns
th(WR-CS) Chip select output hold time (WR standard) Figure 1.32.1 (Note) ns
td(BCLK-ALE) ALE signal output delay time 18 ns
th(BCLK-ALE) ALE signal output hold time –2 ns
td(BCLK-RD) RD signal output delay time 18 ns
th(BCLK-RD) RD signal output hold time –3 ns
td(BCLK-WR) WR signal output delay time 18 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(DB-WR) Data output delay time (WR standard) (Note) ns
th(WR-DB) Data output hold time (WR standard) (Note) ns
tw(WR) Write pulse width (Note) ns
Note: Calculated according to the BCLK frequency as follows:
10 9 X n
td(DB – WR) = – 20
f(BCLK) [ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively)
9
10
th(WR – DB) = – 10
f(BCLK) X 2 [ns]
9
10
th(WR – AD) = – 10
f(BCLK) X 2 [ns]
9
10
th(WR – CS) = – 10
f(BCLK) X 2 [ns]

10 9 X n
tw( WR) = – 15
f(BCLK) X 2 [ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively)

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Timing (Vcc = 3V)

VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise
specified)

Table 1.32.41. Memory expansion and microprocessor modes

(with wait, accessing external memory, multiplex bus area selected)
Standard
Symbol Parameter Measuring condition Unit
Min. Max.
td(BCLK-AD) Address output delay time 18 ns
th(BCLK-AD) Address output hold time (BCLK standard) 0 ns
th(RD-AD) Address output hold time (RD standard) (Note) ns
th(WR-AD) Address output hold time (WR standard) (Note) ns
td(BCLK-CS) Chip select output delay time 18 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) 0 ns
th(RD-CS) Chip select output hold time (RD standard) (Note) ns
th(WR-CS) Chip select output hold time (WR standard) (Note) ns
td(BCLK-RD) RD signal output delay time 18 ns
Figure 1.32.1
th(BCLK-RD) RD signal output hold time –3 ns
td(BCLK-WR) WR signal output delay time 18 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(DB-WR) Data output delay time (WR standard) (Note) ns
th(WR-DB) Data output hold time (WR standard) (Note) ns
td(BCLK-ALE) ALE signal output delay time (BCLK standard) 18 ns
th(BCLK-ALE) ALE signal output hold time (BCLK standard) –2 ns
td(AD-ALE) ALE signal output delay time (address standard) (Note) ns
th(ALE-AD) ALE signal output hold time (address standard) (Note) ns
tdz(RD-AD) Address output flowting start time 8 ns

Note: Calculated according to the BCLK frequency as follows:

10 9
th(RD – AD) = – 10
f(BCLK) X 2 [ns]
10 9
th(WR – AD) = – 10
f(BCLK) X 2 [ns]
10 9
th(RD – CS) = –10
f(BCLK) X 2 [ns]
10 9
th(WR – CS) = – 10
f(BCLK) X 2 [ns]
9
10 X m
td(DB – WR) = – 25
f(BCLK) X 2 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively)

10 9
th(WR – DB) = – 10
f(BCLK) X 2 [ns]

10 9
td(AD – ALE) = – 20
f(BCLK) X 2 [ns]

10 9
th(ALE – AD) = – 10
f(BCLK) X 2 [ns]

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Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise
specified)

Table 1.32.42. Memory expansion and microprocessor modes

(with wait, accessing external memory, DRAM area selected)
Standard
Symbol Parameter Measuring condition Unit
Min. Max.
td(BCLK-RAD) Row address output delay time 18 ns
th(BCLK-RAD) Row address output hold time (BCLK standard) 0 ns
td(BCLK-CAD) String address output delay time 18 ns
th(BCLK-CAD) String address output hold time (BCLK standard) 0 ns
th(RAS-RAD) Row address output hold time after RAS output (Note) ns
td(BCLK-RAS) RAS output delay time (BCLK standard) 18 ns
Figure 1.32.1
th(BCLK-RAS) RAS output hold time (BCLK standard) 0 ns
tRP RAS "H" hold time (Note) ns
td(BCLK-CAS) CAS output delay time (BCLK standard) 18 ns
th(BCLK-CAS) CAS output hold time (BCLK standard) 0 ns
td(BCLK-DW) Data output delay time (BCLK standard) 18 ns
th(BCLK-DW) Data output hold time (BCLK standard) –3 ns
tsu(DB-CAS) CAS after DB output setup time (Note) ns
th(BCLK-DB) DB signal output hold time (BCLK standard) –7 ns
tsu(CAS-RAS) CAS output setup time before RAS output (refresh) (Note) ns
Note: Calculated according to the BCLK frequency as follows:

10 9
th(RAS – RAD) = – 13
f(BCLK) X 2 [ns]

10 9 X 3
tRP = – 20
f(BCLK) X 2 [ns]
9
10
tsu(DB – CAS) = – 20
f(BCLK) [ns]
9
10
tsu(CAS – RAS) = – 13
f(BCLK) X 2 [ns]

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Timing (Vcc = 3V)

Vcc=3V
Memory expansion Mode and Microprocessor Mode (without wait)
Read Timing
BCLK
td(BCLK-ALE)
18ns.max th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS) th(BCLK-CS)
0ns.min
18ns.max*1
CSi
tcyc th(RD-CS)
0ns.min
td(BCLK-AD) th(BCLK-AD)
18ns.max*1 0ns.min
ADi
BHE
td(BCLK-RD) th(RD-AD)
18ns.max 0ns.min
RD
tac2(RD-DB)*2 th(BCLK-RD)
-3ns.min
tac2(AD-DB)*2
Hi-Z
DB
tsu(DB-BCLK) th(RD-DB)
30ns.min*1 0ns.min
*1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK).
*2:It depends on operation frequency.
tac2(RD-DB)=(tcyc/2-35)ns.max
tac2(AD-DB)=(tcyc-35)ns.max

Write Timing
BCLK
td(BCLK-ALE)
18ns.max th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS) th(BCLK-CS)
18ns.max 0ns.min
CSi
tcyc th(WR-CS)*3
td(BCLK-AD) th(BCLK-AD)
18ns.max 0ns.min
ADi
BHE
td(BCLK-WR) tw(WR)*3 th(WR-AD)*3
18ns.max
WR,WRL,
WRH th(BCLK-WR)
0ns.min
td(DB-WR)*3 th(WR-DB)*3

DBi

*3:It depends on operation frequency. Measuring conditions

td(DB-WR)=(tcyc-20)ns.min
• VCC=3V±10%
th(WR-DB)=(tcyc/2-10)ns.min
• Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
th(WR-AD)=(tcyc/2-10)ns.min
• Output timing voltage :Determined with VOH=1.5V, VOL=1.5V
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2-15)ns.min

Figure 1.32.10. VCC=3V timing diagram (1)

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Timing (Vcc = 3V)

Vcc=3V
Memory expansion Mode and Microprocessor Mode (with wait)
Read Timing
BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS) th(BCLK-CS)
0ns.min
18ns.max*1
CSi
th(RD-CS)
tcyc
0ns.min

td(BCLK-AD) th(BCLK-AD)
18ns.max*1 0ns.min
ADi
BHE
td(BCLK-RD) th(RD-AD)
18ns.max 0ns.min
RD
th(BCLK-RD)
tac2(RD-DB)*2 -3ns.min
tac2(AD-DB)*2
DB
Hi-Z
tsu(DB-BCLK) th(RD-DB)
30ns.min*1 0ns.min

*1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK).

*2:It depends on operation frequency.
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)

Write Timing
BCLK 18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
ALE

td(BCLK-CS) th(BCLK-CS)
18ns.max 0ns.min
CSi
tcyc th(WR-CS)*3
td(BCLK-AD) th(BCLK-AD)
18ns.max 0ns.min
ADi
BHE
td(BCLK-WR) tw(WR)*3 th(WR-AD)*3
18ns.max
WR,WRL,
WRH th(BCLK-WR)
0ns.min
td(DB-WR) *3 th(WR-DB)*3
DBi

*3:It depends on operation frequency. Measuring conditions

td(DB-WR)=(tcyc x n-20)ns.min • VCC=3V±10%
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
th(WR-DB)=(tcyc/2-10)ns.min • Input timing voltage
th(WR-AD)=(tcyc/2-10)ns.min :Determined with VIH=1.5V, VIL=0.5V
th(WR-CS)=(tcyc/2-10)ns.min • Output timing voltage
tw(WR)=(tcyc/2 x n-15)ns.min :Determined with VOH=1.5V, VOL=1.5V
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)

Figure 1.32.11. VCC=3V timing diagram (2)

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Timing (Vcc = 3V)

Memory expansion Mode and Microprocessor Mode Vcc=3V

(When accessing external memory area with wait, and select multiplexed bus)
Read Timing
BCLK
td(BCLK-ALE) th(BCLK-ALE)
18ns.max
-2ns.min
ALE
td(BCLK-CS) tcyc th(BCLK-CS)
18ns.max 0ns.min
th(RD-CS)*1
CSi
td(AD-ALE)*1 th(ALE-AD)*1
ADi Address Data input Address
/DBi tdz(RD-AD) th(RD-DB)
8ns.max
td(BCLK-AD) tsu(DB-BCLK) 0ns.min th(BCLK-AD)
30ns.min
18ns.max tac3(RD-DB)*1 0ns.min
ADi
BHE

tac3(AD-DB)*1 td(BCLK-RD) th(BCLK-RD) th(RD-AD)*1

18ns.max -3ns.min
RD

*1:It depends on operation frequency.

td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.)
tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.)
Write Timing
BCLK
td(BCLK-ALE) th(BCLK-ALE)
18ns.max -2ns.min
ALE

tcyc th(BCLK-CS)
td(BCLK-CS) th(WR-CS)*2 0ns.min
18ns.max
CSi

td(AD-ALE)*2 th(ALE-AD)*2
ADi Address Data output Address
/DBi
td(DB-WR)*2 th(WR-DB)*2
td(BCLK-AD) th(BCLK-AD)
18ns.max 0ns.min
ADi
BHE

td(BCLK-WR) th(BCLK-WR) th(WR-AD)*2

18ns.max 0ns.min
WR,WRL,
WRH

*2:It depends on operation frequency. Measuring conditions

td(AD-ALE)=(tcyc/2-20)ns.min • VCC=3V±10%
th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min
• Input timing voltage
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min :Determined with VIH=1.5V, VIL=0.5V
(m=3 and 5 when 2 wait and 3 wait, respectively.) • Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V

Figure 1.32.12. VCC=3V timing diagram (3)

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Timing (Vcc = 3V)

Memory expansion Mode and Microprocessor Mode Vcc=3V

(When accessing DRAM area with 2 wait)
Read Timing
BCLK
tcyc
td(BCLK-CAD)
td(BCLK-RAD) th(BCLK-RAD) th(BCLK-CAD)
18ns.max*1
18ns.max*1 0ns.min
0ns.min

MAi Row address String address

th(RAS-RAD)*2 tRP*2

RAS
td(BCLK-RAS) th(BCLK-RAS)
td(BCLK-CAS) 0ns.min
18ns.max*1 18ns.max*1
CASL
CASH th(BCLK-CAS)
0ns.min

DW
tac4(CAS-DB)*2
tac4(CAD-DB)*2
tac4(RAS-DB)*2
Hi-Z
DB
tsu(DB-BCLK) th(CAS-DB)
30ns.min*1 0ns.min

*1:It is a guarantee value with being alone. 35ns.max garantees as follows:

td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)

*2:It depends on operation frequency.

tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min

Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V

Figure 1.32.13. VCC=3V timing diagram (4)

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Timing (Vcc = 3V)

Memory expansion Mode and Microprocessor Mode Vcc=3V

(When accessing DRAM area with 2 wait)
Write Timing
BCLK
tcyc

td(BCLK-RAD) td(BCLK-CAD) th(BCLK-CAD)

th(BCLK-RAD)
18ns.max 18ns.max 0ns.min
0ns.min
MAi Row address String address

th(RAS-RAD)*1 tRP*1

RAS
td(BCLK-RAS) td(BCLK-CAS) th(BCLK-RAS)
18ns.max 0ns.min
18ns.max
CASL
CASH
th(BCLK-CAS)
td(BCLK-DW) 0ns.min
18ns.max
DW
th(BCLK-DW)
tsu(DB-CAS)*1 -3ns.min
Hi-Z
DB
th(BCLK-DB)
-7ns.min

*1:It depends on operation frequency.

th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
tsu(DB-CAS)=(tcyc-20)ns.min

Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V

Figure 1.32.14. VCC=3V timing diagram (5)

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Timing (Vcc = 3V)

Memory expansion Mode and Microprocessor Mode Vcc=3V

Refresh Timing (CAS before RAS refresh)

BCLK

td(BCLK-RAS) tcyc
18ns.max
RAS
th(BCLK-RAS)
tsu(CAS-RAS)*1 0ns.min

CASL
CASH td(BCLK-CAS) th(BCLK-CAS)
0ns.min
18ns.max

DW

*1:It depends on operation frequency.

tsu(CAS-RAS)=(tcyc/2-13)ns.min

Refresh Timing (Self-refresh)

BCLK

td(BCLK-RAS) tcyc
18ns.max
RAS

tsu(CAS-RAS)*1 th(BCLK-RAS)
0ns.min
CASL
CASH th(BCLK-CAS)
td(BCLK-CAS) 0ns.min
18ns.max

DW

*1:It depends on operation frequency.

tsu(CAS-RAS)=(tcyc/2-13)ns.min

Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V

Figure 1.32.15. VCC=3V timing diagram (6)

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Timing (Vcc = 3V)

tc(TA)
tw(TAH)

TAiIN input
tw(TAL)

tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)

TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling th(TIN–UP) tsu(UP–TIN)
edge is selected)
TAiIN input
(When count on rising
edge is selected)
tc(TB)
tw(TBH)

TBiIN input
tw(TBL)

tc(AD)
tw(ADL)

ADTRG input

tc(CK)
tw(CKH)

CLKi
tw(CKL)
th(C–Q)

TxDi
td(C–Q) tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi input
tw(INH)

Figure 1.32.16. VCC=3V timing diagram (7)

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Timing (Vcc = 3V)

Memory Expansion Mode and Microprocessor Mode

(Valid only with wait)

BCLK

RD
(Separate bus)

WR, WRL, WRH

(Separate bus)

RD
(Multiplexed bus)

WR, WRL, WRH

(Multiplexed bus)

RDY input

tsu(RDY–BCLK) th(BCLK–RDY)

(Valid with or without wait)

BCLK

tsu(HOLD–BCLK) th(BCLK–HOLD)

HOLD input

HLDA output

td(BCLK–HLDA) td(BCLK–HLDA)
P0, P1, P2,
P3, P4, Hi–Z
P50 to P52

Measuring conditions :
• VCC=3V±10%
• Input timing voltage : Determined with VIH=2.4V, VIL=0.6V
• Output timing voltage : Determined with VOH=1.5V, VOL=1.5V

Figure 1.32.17. VCC=3V timing diagram (8)

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Description (Flash Memory Version)

Outline Performance
Table 1.33.1 shows the outline performance of the M32C/83 (flash memory version).

Table 1.33.1. Outline Performance of the M32C/83 (flash memory version)

Item Performance

Power supply voltage f(XIN)=30MHz, without wait, 4.2V to 5.5V

f(XIN)=20MHz, without wait, 3.0V to 3.6V

Program/erase voltage 4.2V to 5.5 V : f(BCLK)=12.5MHz, with one wait

: f(BCLK)=6.25MHz, without wait

Flash memory operation mode Three modes (parallel I/O, standard serial I/O, CPU rewrite)

Erase block User ROM area See Figure 1.33.3

division
Boot ROM area One division (8 Kbytes) (Note 1)
Program method In units of pages (in units of 256 bytes)

Erase method Collective erase/block erase

Program/erase control method Program/erase control by software command
Protect method Protected for each block by lock bit
Number of commands 8 commands
Program/erase count 100 times
Data holding 10 years
ROM code protect Parallel I/O and standard serial modes are supported.
Note: The boot ROM area contains a standard serial I/O mode control program which is stored in
it when shipped from the factory. This area can be erased and programmed in only parallel
I/O mode.

The following shows Mitsubishi plans to develop a line of M32C/83 products (flash memory version).
(1) ROM capacity
(2) Package 100P6S-A ... Plastic molded QFP
100P6Q-A ... Plastic molded QFP
144P6Q-A ... Plastic molded QFP

ROM size
(Bytes)

External
ROM
M30835FJGP
512K M30833FJFP
M30833FJGP
256K

128K

Flash memory version

Figure 1.33.1. ROM Expansion

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Description (Flash Memory Version)

The following lists the M32C/83 products to be supported in the future.

Table 1.33.2. Product List As of Nov., 2001

Type No ROM capacity RAM capacity Package type Remarks
M30835FJGP ** 144P6Q-A
M30833FJGP ** 512 Kbytes 31 Kbytes 100P6Q-A
M30833FJFP ** 100P6S-A
** : Under development

Type No. M3083 5 F J – XXX FP

Package type:
FP : Package 100P6S-A
GP : Package 100P6Q-A, 144P6Q-A
ROM No.
Omitted for external ROM version
and blank flash memory version

ROM capacity:
J : 512K bytes

Memory type:
M : Mask ROM version
S : External ROM version
F : Flash memory version

Shows RAM capacity, pin count, etc

(The value itself has no specific meaning)

M32C/83 Group

M16C Family

Figure 1.33.2. Type No., memory size, and package

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Description (Flash Memory Version)

Flash Memory
The M32C/83 (flash memory version) contains the flash memory that can be rewritten with a single voltage
of 5 V. For this flash memory, three flash memory modes are available in which to read, program, and
erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a
programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Pro-
cessing Unit (CPU). Each mode is detailed in the pages to follow.
The flash memory is divided into several blocks as shown in Figure 1.33.3, so that memory can be erased
one block at a time. Each block has a lock bit to enable or disable execution of an erase or program
operation, allowing for data in each block to be protected.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and
standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored
in it when shipped from the factory. However, the user can write a rewrite control program in this area that
suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.

0F8000016 Block 10 : 64K bytes

0F9000016 Block 9 : 64K bytes

0FA000016 Block 8 : 64K bytes

0FB000016 Block 7 : 64K bytes

0FC000016 Block 6 : 64K bytes

0FD000016
Block 5 : 64K bytes

0FE000016
Block 4 : 64K bytes
Note 1: The boot ROM area can be rewritten in only parallel input/
output mode. (Access to any other areas is inhibited.)
0FF000016 Note 2: To specify a block, use the maximum address in the block
Block 3 : 32K bytes that is an even address.

0FF800016
Block 2 : 8K bytes
0FFA00016
Block 1 : 8K bytes
0FFC00016 0FFE00016
Block 0 : 16K bytes 8K bytes
0FFFFFF16 0FFFFFF16
User ROM area Boot ROM area

Figure 1.33.3. Block diagram of flash memory version

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CPU Rewrite Mode (Flash Memory Version)

CPU Rewrite Mode

In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control
of the Central Processing Unit (CPU).
In CPU rewrite mode, only the user ROM area shown in Figure 1.33.3 can be rewritten; the boot ROM area
cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM
area and each block area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to any area other than the internal flash memory before it can be executed.

Microcomputer Mode and Boot Mode

The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure 1.33.3 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In
this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P55 pin low, the CNVSS pin high, and the P50 pin high, the
CPU starts operating using the control program in the boot ROM area. This mode is called the “boot”
mode. The control program in the boot ROM area can also be used to rewrite the user ROM area.

Block Address
Block addresses refer to the maximum even address of each block. These addresses are used in the
block erase command, lock bit program command, and read lock status command.

Outline Performance of CPU Rewrite Mode

In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by
software commands. Operations must be executed from a memory other than the internal flash memory,
such as the internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 037716) is set to “1”, transition to CPU rewrite mode
occurs and software commands can be accepted.
In the CPU rewrite mode, write to and read from software commands and data into even-numbered ad-
dress (“0” for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered
address. Commands are ignored with odd-numbered addresses.
Use software commands to control program and erase operations. Whether a program or erase operation
has terminated normally or in error can be verified by reading the status register.
Figure 1.34.1 shows the flash memory control register 0.

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CPU Rewrite Mode (Flash Memory Version)

Flash memory control register 0

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
0 FMR0 005716 XX0000012

AA
Bit symbol Bit name Function R WW
R

FMR00 RY/BY signal status bit 0: Busy (being written or erased)

1: Ready

AA
A
FMR01 CPU rewrite mode 0: Normal mode
select bit (Note 1) (Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)

AA
A
FMR02 Lock bit disable bit 0: Block lock by lock bit data is
(Note 2) enabled

AA
A
1: Block lock by lock bit data is
disabled

AA
A
FMR03 Flash memory reset bit 0: Normal operation
(Note 3) 1: Reset

Reserved bit Must always be set to “0”

AA
A
FMR05 User ROM area select bit ( 0: Boot ROM area is accessed
Note 4) (Effective in only 1: User ROM area is accessed
boot mode)

Noting is assigned. When write, set to "0".

AA
A
When read, their contents are indeterminate.
Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Use the
control program except in the internal flash memory for write to this bit. Also write to this
bit when NMI pin is "H" level.
Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession
when the CPU rewrite mode select bit = “1”. When it is not this procedure, it is not
enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently
after setting it to 1 (reset).
Note 4: Use the control program except in the internal flash memory for write to this bit.

Figure 1.34.1. Flash memory control register

Flash memory control register (address 005716)

_____
Bit 0 of the flash memory control register 0 is the RY/BY signal status bit used exclusively to read the
operating status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is
“1”.
Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is
entered by setting this bit to “1”, so that software commands become acceptable. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area other
than the internal flash memory. To set this bit to “1”, it is necessary to write “0” and then write “1” in
succession when NMI pin is "H" level. The bit can be set to “0” by only writing a “0” .

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CPU Rewrite Mode (Flash Memory Version)

Bit 2 of the flash memory control register 0 is a lock bit disable bit. By setting this bit to “1”, it is possible to
disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable select bit
only disables the lock bit function; it does not change the lock data bit value. However, if an erase operation
is performed when this bit =“1”, the lock bit data that is “0” (locked) is set to “1” (unlocked) after erasure. To
set this bit to “1”, it is necessary to write “0” and then write “1” in succession. This bit can be manipulated
only when the CPU rewrite mode select bit = “1”.
Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of
the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access
has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control circuit. To
release the reset, it is necessary to set this bit to “0”.
Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot
mode. If this bit is set to “1” in boot mode, the area to be accessed is switched from the boot ROM area to
the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to “1”. Note
that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be
accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of
whether the CPU rewrite mode is on or off. Use the control program except in the internal flash memory to
rewrite this bit.
Figure 1.34.2 shows a flowchart for setting/releasing the CPU rewrite mode. Always perform operation as
indicated in these flowcharts.

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CPU Rewrite Mode (Flash Memory Version)

Program in ROM Program in RAM

Start *1

Single-chip mode, memory expansion (Boot mode only)

mode, or boot mode Set user ROM area select bit to “1”

Set processor mode register (Note 1) Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)(Note 2)

Transfer CPU rewrite mode control Using software command execute erase,
program to internal RAM program, or other operation
(Set lock bit disable bit as required)

Jump to transferred control program in RAM

(Subsequent operations are executed by control
Execute read array command or reset flash
program in this RAM)
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)

*1

Write “0” to CPU rewrite mode select bit

(Boot mode only)

Write “0” to user ROM area select bit (Note 4)

End

Note 1: During CPU rewrite mode, set the main clock frequency as shown below using the main clock division
register (address 000C16):
6.25 MHz or less when wait bit (bit 2 at address 000516) = “0” (without internal access wait state)
12.5 MHz or less when wait bit (bit 2 at address 000516) = “1” (with internal access wait state)
Note 2: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval. Use the program except in the internal
flash memory for write to this bit. Also write to this bit when NMI pin is "H" level.
Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Note 4: “1” can be set. However, when this bit is “1”, user ROM area is accessed.

Figure 1.34.2. CPU rewrite mode set/reset flowchart

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CPU Rewrite Mode (Flash Memory Version)

Precautions on CPU Rewrite Mode

Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During CPU rewrite mode, set the main clock frequency as shown below using the main clock division
register (address 000C16):
6.25 MHz or less when wait bit (bit 2 at address 000516) = 0 (without internal access wait state)
12.5 MHz or less when wait bit (bit 2 at address 000516) = 1 (with internal access wait state)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
The address match interrupt cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be
_______
used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts each can
be used to change the CPU rewrite mode select bit forcibly to normal mode (FMR01="0") upon occur-
_______
rence of the interrupt. Since the rewrite operation is halted when the NMI and watchdog timer inter-
rupts occur, set the CPU rewite mode select bit to "1" and the erase/program operation needs to be
performed over again.
(4) Reset
Reset input is always accepted.
(5) Access disable
Write CPU rewrite mode select bit and user ROM area select bit in an area other than the internal flash
memory.
(6) How to access
For CPU rewrite mode select bit and lock bit disable bit to be set to “1”, the user needs to write a “0”
and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is neces-
sary to ensure that no interrupt or DMA transfer will be executed during the interval.
Write to the CPU rewrite mode select bit when NMI pin is "H" level.
(7)Writing in the user ROM area
If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode,
those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be
rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O
mode to rewrite these blocks.
(8)Using the lock bit
To use the CPU rewrite mode, use a boot program that can set and cancel the lock command.

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CPU Rewrite Mode (Flash Memory Version)

Software Commands
Table 1.34.1 lists the software commands available with the M16C/62A (flash memory version).
After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or
program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored.
The content of each software command is explained below.

Table 1.34.1. List of software commands (CPU rewrite mode)

First bus cycle Second bus cycle Third bus cycle
Command Data Data Data
Mode Address (D0 to D7) Mode Address (D0 to D7) Mode Address (D0 to D7)

Read array Write X (Note 6) FF16

Read status register Write X 7016 Read X SRD (Note 2)

Clear status register Write X 5016

Page program (Note 3) Write X 4116 Write WA0 (Note 3) WD0 (Note 3) Write WA1 WD1
Block erase Write X 2016 Write BA (Note 4) D016
Erase all unlock block Write X A716 Write X D016
Lock bit program Write X 7716 Write BA D016
Read lock bit status Write X 7116 Read BA D6 (Note 5)

Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored.
Note 2: SRD = Status Register Data
Note 3: WA = Write Address, WD = Write Data
WA and WD must be set sequentially from 0016 to FE16 (byte address; however, an even address). The page size is
256 bytes.
Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)
Note 5: D6 corresponds to the block lock status. Block not locked when D6 = 1, block locked when D6 = 0.
Note 6: X denotes a given address in the user ROM area (that is an even address).

Read Array Command (FF16)

The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an
even address to be read is input in one of the bus cycles that follow, the content of the specified
address is read out at the data bus (D0–D15), 16 bits at a time.
The read array mode is retained intact until another command is written.

Read Status Register Command (7016)

When the command code “7016” is written in the first bus cycle, the content of the status register is
read out at the data bus (D0–D7) by a read in the second bus cycle.
The status register is explained in the next section.

Clear Status Register Command (5016)

This command is used to clear the bits SR3 to 5 of the status register after they have been set. These
bits indicate that operation has ended in an error. To use this command, write the command code
“5016” in the first bus cycle.

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CPU Rewrite Mode (Flash Memory Version)

Page Program Command (4116)

Page program allows for high-speed programming in units of 256 bytes. Page program operation
starts when the command code “4116” is written in the first bus cycle. In the second bus cycle through
the 129th bus cycle, the write data is sequentially written 16 bits at a time. At this time, the addresses
A0-A7 need to be incremented by 2 from “0016” to “FE16.” When the system finishes loading the data,
it starts an auto write operation (data program and verify operation).
Whether the auto write operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto write operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to 0 at the same time the auto write operation starts and is returned to
1 upon completion of the auto write operation. In this case, the read status register mode remains
active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the
flash memory is reset using its reset bit.
____
The RY/BY signal status bit of the flash memory control register 0 is 0 during auto write operation and
1 when the auto write operation is completed as is the status register bit 7.
After the auto write operation is completed, the status register can be read out to know the result of the
auto write operation. For details, refer to the section where the status register is detailed.
Figure 1.34.3 shows an example of a page program flowchart.
Each block of the flash memory can be write protected by using a lock bit. For details, refer to the
section where the data protect function is detailed.
Additional writes to the already programmed pages are prohibited.

Start

Write 4116

n=0

Write address n and n=n+2

data n

NO
n = FE16

YES

RY/BY signal NO
status bit
= 1?
YES

Check full status

Page program
completed

Figure 1.34.3. Page program flowchart

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CPU Rewrite Mode (Flash Memory Version)

Block Erase Command (2016/D016)

By writing the command code “2016” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows to the block address of a flash memory block, the system initiates
an auto erase (erase and erase verify) operation.
Whether the auto erase operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto erase operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned
to 1 upon completion of the auto erase operation. In this case, the read status register mode remains
active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the
flash memory is reset using its reset bit.
____
The RY/BY signal status bit of the flash memory control register 0 is 0 during auto erase operation and
1 when the auto erase operation is completed as is the status register bit 7.
After the auto erase operation is completed, the status register can be read out to know the result of
the auto erase operation. For details, refer to the section where the status register is detailed.
Figure 1.34.4 shows an example of a block erase flowchart.
Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer
to the section where the data protect function is detailed.

Start

Write 2016

Write D016
Block address

RY/BY signal NO
status bit
= 1?
YES
Check full status check

Block erase
completed

Figure 1.34.4. Block erase flowchart

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CPU Rewrite Mode (Flash Memory Version)

Erase All Unlock Blocks Command (A716/D016)

By writing the command code “A716” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows, the system starts erasing blocks successively.
Whether the erase all unlock blocks command is terminated can be confirmed by reading the status
register or the flash memory control register 0, in the same way as for block erase. Also, the status
register can be read out to know the result of the auto erase operation.
When the lock bit disable bit of the flash memory control register 0 = 1, all blocks are erased no matter
how the lock bit is set. On the other hand, when the lock bit disable bit = 0, the function of the lock bit
is effective and only nonlocked blocks (where lock bit data = 1) are erased.

Lock Bit Program Command (7716/D016)

By writing the command code “7716” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows to the block address of a flash memory block, the system sets the
lock bit for the specified block to 0 (locked).
Figure 1.34.5 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit
data) can be read out by a read lock bit status command.
Whether the lock bit program command is terminated can be confirmed by reading the status register
or the flash memory control register 0, in the same way as for page program.
For details about the function of the lock bit and how to reset the lock bit, refer to the section where the
data protect function is detailed.

Start

Write 7716

Write D016
block address

RY/BY signal NO
status bit
= 1?
YES
NO Lock bit program in
SR4 = 0?
error
YES
Lock bit program
completed

Figure 1.34.5. Lock bit program flowchart

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CPU Rewrite Mode (Flash Memory Version)

Read Lock Bit Status Command (7116)

By writing the command code “7116” in the first bus cycle and then the block address of a flash
memory block in the second bus cycle that follows, the system reads out the status of the lock bit of the
specified block on to the data (D6).
Figure 1.34.6 shows an example of a read lock bit program flowchart.

Start

Write 7116

Enter block address

NO
D6 = 0?

YES
Blocks locked Blocks not locked

Figure 1.34.6. Read lock bit status flowchart

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CPU Rewrite Mode (Flash Memory Version)

Data Protect Function (Block Lock)

Each block in Figure 1.33.3 has a nonvolatile lock bit to specify that the block be protected (locked)
against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of
each block can be read out using the read lock bit status command.
Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash
memory control register 0’s lock bit disable bit is set.
(1) When the lock bit disable bit = 0, a specified block can be locked or unlocked by the lock bit status
(lock bit data). Blocks whose lock bit data = 0 are locked, so they are disabled against erase/write.
On the other hand, the blocks whose lock bit data = 1 are not locked, so they are enabled for erase/
write.
(2) When the lock bit disable bit = 1, all blocks are nonlocked regardless of the lock bit data, so they are
enabled for erase/write. In this case, the lock bit data that is 0 (locked) is set to 1 (nonlocked) after
erasure, so that the lock bit-actuated lock is removed.

Status Register
The status register indicates the operating status of the flash memory and whether an erase or program
operation has terminated normally or in an error. The content of this register can be read out by only
writing the read status register command (7016). Table 1.34.2 details the status register.
The status register is cleared by writing the Clear Status Register command (5016).
After a reset, the status register is set to “8016.”
Each bit in this register is explained below.

Write state machine (WSM) status (SR7)

After power-on, the write state machine (WSM) status is set to 1.
The write state machine (WSM) status indicates the operating status of the device, as for output on the
____
RY/BY pin. This status bit is set to 0 during auto write or auto erase operation and is set to 1 upon
completion of these operations.

Erase status (SR5)

The erase status informs the operating status of auto erase operation to the CPU. When an erase
error occurs, it is set to 1.
The erase status is reset to 0 when cleared.

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CPU Rewrite Mode (Flash Memory Version)

Program status (SR4)

The program status informs the operating status of auto write operation to the CPU. When a write
error occurs, it is set to 1.
The program status is reset to 0 when cleared.
When an erase command is in error (which occurs if the command entered after the block erase
command (2016) is not the confirmation command (D016), both the program status and erase status
(SR5) are set to 1.
When the program status or erase status = 1, the following commands entered by command write are
not accepted.

Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error):
(1) When the valid command is not entered correctly
(2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase
(2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is
entered, read array is assumed and the command that has been set up in the first bus cycle is
canceled.

Block status after program (SR3)

If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,
“9016” is output; and when excessive data is written, “8816” is output.

Table 1.34.2. Definition of each bit in status register

Each bit of Definition
SRD Status name
"1" "0"
SR7 (bit7) Write state machine (WSM) status Ready Busy
SR6 (bit6) Reserved - -
SR5 (bit5) Erase status Terminated in error Terminated normally
SR4 (bit4) Program status Terminated in error Terminated normally
SR3 (bit3) Block status after program Terminated in error Terminated normally
SR2 (bit2) Reserved - -
SR1 (bit1) Reserved - -
SR0 (bit0) Reserved - -

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CPU Rewrite Mode (Flash Memory Version)

Full Status Check

By performing full status check, it is possible to know the execution results of erase and program
operations. Figure 1.34.7 shows a full status check flowchart and the action to be taken when each
error occurs.

Read status register

YES
SR4=1 and SR5 Command Execute the clear status register command (5016)
=1 ? sequence error to clear the status register. Try performing the
operation one more time after confirming that the
NO
command is entered correctly.
NO Should a block erase error occur, the block in error
SR5=0? Block erase error
cannot be used.
YES

NO
SR4=0? Program error (page Execute the read lock bit status command (7116) to
or lock bit) see if the block is locked. After removing lock,
YES execute write operation in the same way. If the
error still occurs, the page in error cannot be used.

NO Program error After erasing the block in error, execute write

SR3=0?
(block) operation one more time. If the same error still
YES occurs, the block in error cannot be used.

End (block erase, program)

Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock
blocks and lock bit program commands is accepted. Execute the clear status register command
(5016) before executing these commands.

Figure 1.34.7. Full status check flowchart and remedial procedure for errors

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Functions To Inhibit Rewriting Flash Memory (Flash Memory Version)

Functions To Inhibit Rewriting Flash Memory Version

To prevent the contents of the flash memory version from being read out or rewritten easily, the device
incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for
use in standard serial I/O mode.

ROM code protect function

The ROM code protect function reading out or modifying the contents of the flash memory version by
using the ROM code protect control address (0FFFFFF16) during parallel I/O mode. Figure 1.34.8 shows
the ROM code protect control address (0FFFFFF16). (This address exists in the user ROM area.)
If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents
of the flash memory version are protected against readout and modification. ROM code protect is imple-
mented in two levels. If level 2 is selected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is
selected by default.
If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the
contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,
the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/
O or some other mode to rewrite the contents of the ROM code protect reset bits.

ROM code protect control address

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
ROMCP 0FFFFFF16 FF16
1 1

Bit symbol Bit name Function

Reserved bit Always set this bit to 1.
b3 b2
ROM code protect level
ROMCP2 00: Protect enabled
2 set bit (Note 1, 2)
01: Protect enabled
10: Protect enabled
11: Protect disabled
b5 b4
ROMCR ROM code protect reset
00: Protect removed
bit (Note 3)
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
b7 b6
ROMCP1 ROM code protect level
1 set bit (Note 1) 00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled

Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against
readout or modification in parallel input/output mode.
Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, since these bits cannot be changed in parallel input/
output mode, they need to be rewritten in serial input/output or some other mode.

Figure 1.34.8. ROM code protect control address

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Functions To Inhibit Rewriting Flash Memory (Flash Memory Version)

ID Code Check Function

Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID
code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they
match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID
code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFFDF16, 0FFFFE316,
0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716, and 0FFFFFB16. Write a program which has had the
ID code preset at these addresses to the flash memory.

Address
0FFFFDC16 to 0FFFFDF16 ID1 Undefined instruction vector

0FFFFE016 to 0FFFFE316 ID2 Overflow vector

0FFFFE416 to 0FFFFE716 BRK instruction vector

0FFFFE816 to 0FFFFEB16 ID3 Address match vector

0FFFFEC16 to 0FFFFEF16 ID4

0FFFFF016 to 0FFFFF316 ID5 Watchdog timer vector

0FFFFF416 to 0FFFFF716 ID6

0FFFFF816 to 0FFFFFB16 ID7 NMI vector

0FFFFFC16 to 0FFFFFF16 Reset vector

4 bytes

Figure 1.34.9. ID code store addresses

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Appendix Parallel I/O Mode (Flash Memory Version)

Parallel I/O Mode

In this mode, the M32C/83 (flash memory version) operates in a manner similar to the flash memory
M5M29FB/T800 from Mitsubishi. Since there are some differences with regard to the functions not avail-
able with the microcomputer and matters related to memory capacity, the M32C/83 cannot be programed
by a programer for the flash memory.
Use an exclusive programer supporting M32C/83 (flash memory version).
Refer to the instruction manual of each programer maker for the details of use.

User ROM and Boot ROM Areas

In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.33.3 can be rewritten. Both
areas of flash memory can be operated on in the same way.
Program and block erase operations can be performed in the user ROM area. The user ROM area and its
blocks are shown in Figure 1.33.3.
The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0FFE00016 through
0FFFFFF16. Make sure program and block erase operations are always performed within this address
range. (Access to any location outside this address range is prohibited.)
In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area
has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory.
Therefore, using the device in standard serial input/output mode, you do not need to write to the boot
ROM area.

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Appendix Standard Serial I/O Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Standard serial I/O mode

The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to
operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two
standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both
modes require a purpose-specific peripheral unit.

The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory
rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re-
_____ ________
leased, which is done when the P50 (CE) pin is "H" level, the P55 (EPM) pin "L" level and the CNVss pin "H"
level. (In the ordinary command mode, set CNVss pin to "L" level.)
This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accord-
ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is
rewritten in the parallel I/O mode. Figures 1.35.1 to 1.35.3 show the pin connections for the standard serial
I/O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/O
switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of
CLK1 pin when the reset is released.

To use standard serial I/O mode 1 (clock synchronized), set the CLK1 pin to "H" level and the TxD1 pin to "L"
level, and release the reset. The CLK1 pin is connected to Vcc via pull-up resistance and the TxD1 is
connected to Vss via pull-down resistance. The operation uses the four UART1 pins CLK1, RxD1, TxD1 and
RTS1 (BUSY). The CLK1 pin is the transfer clock input pin through which an external transfer clock is input.
The TxD1 pin is for CMOS output. The RTS1 (BUSY) pin outputs an "L" level when ready for reception and
an "H" level when reception starts.

To use standard serial I/O mode 2 (clock asynchronized), set the CLK1 pin to "L" level and release the reset.
The operation uses the two UART1 pins RxD1 and TxD1.

In the standard serial I/O mode, only the user ROM area indicated in Figure 1.35.20 can be rewritten. The
boot ROM cannot.
In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com-
mands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.

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Appendix Standard Serial I/O Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pin functions (Flash memory standard serial I/O mode)

Pin Name I/O Description

VCC,VSS Power input Apply 4.2V to 5.5V to Vcc pin and 0 V to Vss pin.

CNVSS CNVSS I Connect to Vcc pin.

RESET Reset input I Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.

XIN Clock input I Connect a ceramic resonator or crystal oscillator between XIN
and XOUT pins. To input an externally generated clock, input it
XOUT Clock output O to XIN pin and open XOUT pin.

BYTE BYTE I Connect this pin to Vcc or Vss.

AVCC, AVSS Analog power supply input I Connect AVSS to Vss and AVcc to Vcc, respectively.

VREF Reference voltage input I Enter the reference voltage for A-D converter from this pin.

P00 to P07 Input port P0 Input "H" or "L" level signal or open.
I
P10 to P17 Input port P1 Input "H" or "L" level signal or open.
I
P20 to P27 Input port P2 Input "H" or "L" level signal or open.
I
P30 to P37 Input port P3 Input "H" or "L" level signal or open.
I
P40 to P47 Input port P4 Input "H" or "L" level signal or open.
I
P51 to P54, Input port P5 Input "H" or "L" level signal or open.
I
P56, P57

P50 CE input Input "H" level signal.

I
P55 EPM input Input "L" level signal.
I
P60 to P63 Input port P6 Input "H" or "L" level signal or open.
I
P64 BUSY output Standard serial mode 1: BUSY signal output pin
O
Standard serial mode 2: Monitors the program operation check

P65 SCLK input Standard serial mode 1: Serial clock input pin
I
Standard serial mode 2: Input "L" level signal.
P66 RxD input Serial data input pin
I
P67 TxD output O Serial data output pin. When using standard serial mode 1, an
"L" level must be input to TxD pin while the RESET pin is “L”.
For this reason, this pin should be pulled down. After being reset,
this pin functions as a data output pin. Thus adjust pull-down
resistance value with the system not to affect data transfer.

P70 to P77 Input port P7 Input "H" or "L" level signal or open.
I
P80 to P84, P86, Input port P8 Input "H" or "L" level signal or open.
I
P87
P85 NMI input I Connect this pin to Vcc.

P90 to P97 Input port P9 Input "H" or "L" level signal or open.
I
P100 to P107 Input port P10 Input "H" or "L" level signal or open.
I
P110 to P114 Input port P11 Input "H" or "L" level signal or open. (Note)
I
P120 to P127 Input port P12 Input "H" or "L" level signal or open. (Note)
I
P130 to P137 Input port P13 Input "H" or "L" level signal or open. (Note)
I
P140 to P146 Input port P14 Input "H" or "L" level signal or open. (Note)
I
P150 to P157 Input port P15 I Input "H" or "L" level signal or open. (Note)

Note: Port P11 to P15 exist in 144-pin version.

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Mode setting
Signal Value
CNVss Vcc
EPM Vss
RESET Vss >> Vcc
CE Vcc

100

87
86
85
84
83
82
81
92
91
90
89
88
99
98
97
96
95
94
93

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

CNVss

RESET
oscillation
Connect

M32C/83(100-pin) Group
circuit

Flash Memory Version

(100P6S)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

EPM
BUSY
RxD
Vcc

Vss

CE
SCLK
TxD

Figure 1.35.1. Pin connections for standard serial I/O mode (1)

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Mode setting
Signal Value
CNVss Vcc
EPM Vss
RESET Vss >> Vcc
CE Vcc

100
99

87
88

76
89

77
90

78
91

79
92

80
93

81
94

82
95

83
96

84
97

85
98

86

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

CNVSS

RESET

M32C/83(100-pin) Group
oscillation
Connect
circuit

Flash Memory Version

(100P6Q)
27

39

50
26

38
37

49
36

48
35

47
34

46
33

45
32

44
31

43
30

42
29

41
28

40
BUSY
VCC

VSS

CE
RX
D

SCLK

EPM
TX
D

Figure 1.35.2. Pin connections for standard serial I/O mode (2)

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Mode setting
Signal Value
CNVss Vcc
EPM Vss
RESET Vss >> Vcc
CE Vcc

108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

109 72
110 71
111 70
112 69
113 68
114 67
115 66
116 65 CE
117 64
118 63
119 62
120 61
121 60
122 59
123 58
124
125
M32C/83(144-pin) Group 57
56
126
127
Flash Memory Version 55
54 EPM
128
129 (144P6Q) 53
52
130 51
131 50
132 49
133 48
134 47
135 46
136 45
137 44
138 43 BUSY
139 42 SCLK
140 41
141 40 RxD
142 39
143 38 TxD
144 37

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

VCC

VSS

Connect
oscillation
circuit
RESET
CNVSS

Figure 1.35.3. Pin connections for standard serial I/O mode (3)

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Overview of standard serial I/O mode 1 (clock synchronized)

In standard serial I/O mode 1, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1).
Standard serial I/O mode 1 is engaged by releasing the reset with the P65 (CLK1) pin "H" level.
In reception, software commands, addresses and program data are synchronized with the rise of the trans-
fer clock that is input to the CLK1 pin, and are then input to the MCU via the RxD1 pin. In transmission, the
read data and status are synchronized with the fall of the transfer clock, and output from the TxD1 pin.
The TxD1 pin is for CMOS output. Transfer is in 8-bit units with LSB first.
When busy, such as during transmission, reception, erasing or program execution, the RTS1 (BUSY) pin is
"H" level. Accordingly, always start the next transfer after the RST1 (BUSY) pin is "L" level.
Also, data and status registers in memory can be read after inputting software commands. Status, such as
the operating state of the flash memory or whether a program or erase operation ended successfully or not,
can be checked by reading the status register. Here following are explained software commands, status
registers, etc.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Software Commands
Table 1.35.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and
reading are controlled by transferring software commands via the RxD1 pin. Software commands are
explained here below.

Table 1.35.1. Software commands (Standard serial I/O mode 1)

1st byte When ID is
Control command transfer 2nd byte 3rd byte 4th byte 5th byte 6th byte
not verified
Address Address Data Data Data Data Not
1 Page read FF16 (middle) (high) output output output output to acceptable
259th byte

Address Address Data Data Data Data input Not

2 Page program 4116 (middle) (high) input input input to 259th acceptable
byte

Address Address D016 Not

3 Block erase 2016 (middle) (high) acceptable
D016 Not
4 Erase all unlocked blocks A716 acceptable
SRD SRD1 Acceptable
5 Read status register 7016 output output
Not
6 Clear status register 5016 acceptable
Address Address Lock bit Not
7 Read lock bit status 7116 (middle) (high) data acceptable
output

Address Address D016 Not

8 Lock bit program 7716 (middle) (high) acceptable
Not
9 Lock bit enable 7A16 acceptable
Not
10 Lock bit disable 7516 acceptable
Address
Address Address
11 Code processing function F516 (low)
(middle) (high) ID size ID1 To ID7 Acceptable
Size Check- To Not
12 Download function FA16 Size (low) (high) sum Data required acceptable
input number
of times
Version Version Version Version Version Version
13 Version data output function FB16 data data data data data data Acceptable
output output output output output output to
9th byte
Address Address Data Data Data Data Not
14 Boot ROM area output FC16 (middle) (high) output output output output to acceptable
function 259th
byte
Check Check Not
15 Read check data FD16 data (low) data acceptable
(high)

Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note 2: SRD refers to status register data. SRD1 refers to status register data1 .
Note 3: All commands can be accepted when the flash memory is totally blank.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Page Read Command

This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.

CLK1

RxD1 FF16 A8 to A16 to

(M32C reception data) A15 A23

TxD1 data0 data255

(M32C transmit data)

RTS1(BUSY)

Figure 1.35.4. Timing for page read

Page Program Command

This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses
A8 to A23 is input sequentially from the smallest address first, that page is automatically written.

When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the “H” to
the “L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed with already programmed pages.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

CLK1

RxD1 4116 A8 to A16 to data0 data255

(M32C reception data) A15 A23

TxD1
(M32C transmit data)

RTS1(BUSY)

Figure 1.35.5. Timing for the page program

Block Erase Command

This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Transfer the “2016” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the
erase operation will start for the specified block in the flash memory. Write the highest address of
the specified block for addresses A16 to A23.

When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. After block
erase ends, the result of the block erase operation can be known by reading the status register. For
more information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.

CLK1

RxD1 A8 to A16 to
2016 D016
(M32C reception data) A15 A23

TxD1
(M32C transmit data)

RTS1(BUSY)

Figure 1.35.6. Timing for block erasing

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Erase All Unlocked Blocks Command

This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the
erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register. Each block can be erase-protected with the
lock bit. For more information, see the section on the data protection function.

CLK1

RxD1
(M32C reception data) A716 D016

TxD1
(M32C transmit data)

RTS1(BUSY)

Figure 1.35.7. Timing for erasing all unlocked blocks

Read Status Register Command

This command reads status information. When the “7016” command code is sent with the 1st byte, the
contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1
(SRD1) specified with the 3rd byte are read.

CLK1

RxD1 7016
(M32C reception data)

SRD SRD1
TxD1 output output
(M32C transmit data)

RTS1(BUSY)

Figure 1.35.8. Timing for reading the status register

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Clear Status Register Command

This command clears the bits (SR3–SR5) which are set when the status register operation ends in
error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared.
When the clear status register operation ends, the RTS1 (BUSY) signal changes from the “H” to the “L”
level.

CLK1

RxD1 5016
(M32C reception data)

TxD1
(M32C transmit data)

RTS1(BUSY)

Figure 1.35.9. Timing for clearing the status register

Read Lock Bit Status Command

This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Transfer the “7116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) The lock bit data of the specified block is output with the 4th byte. The 6th bit (D6) of output data
is the lock bit data. Write the highest address of the specified block for addresses A8 to A23.

CLK1

RxD1 7116 A8 to A16 to

(M32C reception data) A15 A23

TxD1 DQ6
(M32C transmit data)

RTS1(BUSY)

Figure 1.35.10. Timing for reading lock bit status

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Lock Bit Program Command

This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program
command as explained here following.
(1) Transfer the “7716” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, “0” is
written for the lock bit of the specified block. Write the highest address of the specified block for
addresses A8 to A23.
When writing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. Lock bit status can
be read with the read lock bit status command. For information on the lock bit function, reset proce-
dure and so on, see the section on the data protection function.

CLK1

RxD1 7716 A8 to A16 to D016

(M32C reception data) A15 A23

TxD1
(M32C transmit data)

RTS1(BUSY)

Figure 1.35.11. Timing for the lock bit program

Lock Bit Enable Command

This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-
mand. The command code “7A16” is sent with the 1st byte of the serial transmission. This command
only enables the lock bit function; it does not set the lock bit itself.

CLK1

RxD1 7A16
(M32C reception data)

TxD1
(M32C transmit data)

RTS1(BUSY)

Figure 1.35.12. Timing for enabling the lock bit

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Lock Bit Disable Command

This command disables the lock bit. The command code “7516” is sent with the 1st byte of the serial
transmission. This command only disables the lock bit function; it does not set the lock bit itself.
However, if an erase command is executed after executing the lock bit disable command, “0” (locked)
lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is
cancelled, the lock bit is enabled.

CLK1

RxD1
(M32C reception data) 7516

TxD1
(M32C transmit data)

RTS1(BUSY)

Figure 1.35.13. Timing for disabling the lock bit

ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,
3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.

CLK1

RxD1 F516 DF16 FF16 0F16 ID size ID1 ID7

(M32C reception
data)

TxD1
(M32C transmit
data)
RTS1(BUSY)

Figure 1.35.14. Timing for the ID check

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th
byte onward.
(4) The program to execute is sent with the 5th byte onward.

When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.

CLK1

RxD1 Check Program Program

FA16 sum data
(M32C reception data) data

Data size (low)

TxD1 Data size (high)
(M32C transmit data)

RTS1(BUSY)

Figure 1.35.15. Timing for download

Version Information Output Command

This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.

CLK1

RxD1 FB16
(M32C reception data)

TxD1
(M32C transmit data) 'V' 'E' 'R' 'X'

RTS1(BUSY)

Figure 1.35.16. Timing for version information output

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Boot ROM Area Output Command

This command outputs the control program stored in the boot ROM area in one page blocks (256
bytes). Execute the boot ROM area output command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.

CLK1

RxD1 A8 to A16 to
FC16
(M32C reception data) A15 A23

TxD1
(M32C transmit data) data0 data255

RTS1(BUSY)

Figure 1.35.17. Timing for boot ROM area output

Read Check Data

This command reads the check data that confirms that the write data, which was sent with the page
program command, was successfully received.
(1) Transfer the "FD16" command code with the 1st byte.
(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.

To use this read check data command, first execute the command and then initialize the check data.
Next, execute the page program command the required number of times. After that, when the read
check command is executed again, the check data for all of the read data that was sent with the page
program command during this time is read. The check data is the result of CRC operation of write
data.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

CLK1

RxD1 FD16
(M32C reception data)

TxD1
(M32C transmit data)

Check data (low) Check data (high)

RTS1(BUSY)

Figure 1.35.18. Timing for the read check data

ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFFDF 16, 0FFFFE3 16, 0FFFFEB 16 , 0FFFFEF 16, 0FFFFF3 16 , 0FFFFF7 16 and
0FFFFFB16. Write a program into the flash memory, which already has the ID code set for these
addresses.

Address
0FFFFDC16 to 0FFFFDF16 ID1 Undefined instruction vector

0FFFFE016 to 0FFFFE316 ID2 Overflow vector

0FFFFE416 to 0FFFFE716 BRK instruction vector

0FFFFE816 to 0FFFFEB16 ID3 Address match vector

0FFFFEC16 to 0FFFFEF16 ID4

0FFFFF016 to 0FFFFF316 ID5 Watchdog timer vector

0FFFFF416 to 0FFFFF716 ID6

0FFFFF816 to 0FFFFFB16 ID7 NMI vector

0FFFFFC16 to 0FFFFFF16 Reset vector

4 bytes

Figure 1.35.19. ID code storage addresses

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Data Protection (Block Lock)

Each of the blocks in Figure 1.35.20 have a nonvolatile lock bit that specifies protection (block lock)
against erasing/writing. A block is locked (writing “0” for the lock bit) with the lock bit program command.
Also, the lock bit of any block can be read with the read lock bit status command.
Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock
bit disable and lock enable bit commands.
(1) After the reset has been cancelled and the lock bit enable command executed, the specified block
can be locked/unlocked using the lock bit (lock bit data). Blocks with a “0” lock bit data are locked
and cannot be erased or written in. On the other hand, blocks with a “1” lock bit data are unlocked
and can be erased or written in.
(2) After the lock bit enable command has been executed, all blocks are unlocked regardless of lock bit
data status and can be erased or written in. In this case, lock bit data that was “0” before the block
was erased is set to “1” (unlocked) after erasing, therefore the block is actually unlocked with the
lock bit.

0F8000016 Block 10 : 64K bytes

0F9000016 Block 9 : 64K bytes

0FA000016 Block 8 : 64K bytes

0FB000016 Block 7 : 64K bytes

0FC000016 Block 6 : 64K bytes

0FD000016
Block 5 : 64K bytes

0FE000016
Block 4 : 64K bytes

0FF000016
Block 3 : 32K bytes

0FF800016
Block 2 : 8K bytes
0FFA00016
Block 1 : 8K bytes
0FFC00016
Block 0 : 16K bytes
0FFFFFF16
User ROM area

Figure 1.35.20. Blocks in the user area

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Status Register (SRD)

The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 1.35.2 gives the definition of each status register bit. After clearing the reset, the status register
outputs “8016”.

Table 1.35.2. Status register (SRD)

Definition
SRD bits Status name "1" "0"
SR0 (bit0) Reserved - -
SR1 (bit1) Reserved - -
SR2 (bit2) Reserved - -
SR3 (bit3) Block status after program Terminated in error Terminated normally
SR4 (bit4) Program status Terminated in error Terminated normally
SR5 (bit5) Erase status Terminated in error Terminated normally
SR6 (bit6) Reserved - Busy
SR7 (bit7) Write state machine (WSM) status Ready -

Program Status After Program (SR3)

If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,
“9016” is output; and when excessive data is written, “8816” is output.
If “1” is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked
blocks and lock bit program commands are not accepted. Before executing these commands, execute
the clear status register command (5016) and clear the status register.

Program Status (SR4)

The program status reports the operating status of the auto write operation. If a write error occurs, it is
set to “1”. When the program status is cleared, it is set to “0”.

Erase Status (SR5)

The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is
set to “1”. When the erase status is cleared, it is set to “0”.

Write State Machine (WSM) Status (SR7)

The write state machine (WSM) status indicates the operating status of the flash memory. When
power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase
operation, but it is set back to “1” when the operation ends.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Status Register 1 (SRD1)

Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table 1.35.3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON
and the flag status is maintained even after the reset.

Table 1.35.3. Status register 1 (SRD1)

Definition
SRD1 bits Status name "1" "0"
SR8 (bit0) Reserved - -
SR9 (bit1) Data receive time out Time out Normal operation
SR10 (bit2) ID check completed bits 00 Not verified
SR11 (bit3) 01 Verification mismatch
10 Reserved
11 Verified
SR12 (bit4) Checksum match bit Match Mismatch
SR13 (bit5) Reserved - -
SR14 (bit6) Reserved - -
SR15 (bit7) Boot update completed bit Update completed Not update

Data Reception Time Out (SR9)

This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.

ID Check Completed Bits (SR11 and SR10)

These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.

Check Sum Consistency Bit (SR12)

This flag indicates whether the check sum matches or not when a program, is downloaded for execu-
tion using the download function.

Boot Update Completed Bit (SR15)

This flag indicates whether the control program was downloaded to the RAM or not, using the down-
load function.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Full Status Check

Results from executed erase and program operations can be known by running a full status check. Figure
1.35.21 shows a flowchart of the full status check and explains how to remedy errors which occur.

Read status register

YES
SR4=1 and SR5 Command Execute the clear status register command (5016)
=1 ? sequence error to clear the status register. Try performing the
operation one more time after confirming that the
NO
command is entered correctly.
NO Should a block erase error occur, the block in error
SR5=0? Block erase error
cannot be used.
YES

NO
SR4=0? Program error (page Execute the read lock bit status command (7116) to
or lock bit) see if the block is locked. After removing lock,
YES execute write operation in the same way. If the
error still occurs, the page in error cannot be used.

NO Program error After erasing the block in error, execute write

SR3=0?
(block) operation one more time. If the same error still
YES occurs, the block in error cannot be used.

End (block erase, program)

Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock
blocks and lock bit program commands is accepted. Execute the clear status register command
(5016) before executing these commands.

Figure 1.35.21. Full status check flowchart and remedial procedure for errors

Example Circuit Application for The Standard Serial I/O Mode 1

The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary
according to peripheral unit (programmer), therefore see the peripheral unit (programmer) manual for
more information.

Clock input CLK1

Data output TXD1

M32C/83
Flash memory version

CNVss
BUSY output RTS1(BUSY)
Data input RXD1

P50(CE)

P55(EPM)
NMI

(1) Control pins and external circuitry will vary according to peripheral unit (programmer). For more
information, see the peripheral unit (programmer) manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch.

Figure 1.35.22. Example circuit application for the standard serial I/O mode 1

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Overview of standard serial I/O mode 2 (clock asynchronized)

In standard serial I/O mode 2, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART1).
Standard serial I/O mode 2 is engaged by releasing the reset with the P65 (CLK1) pin "L" level.
The TxD1 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF.
After the reset is released, connections can be established at 9,600 bps when initial communications (Fig-
ure 1.35.23) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz
input oscillation frequency. Baud rate can be changed from 9,600 bps to 19,200, 38,400, 57,600 or 115,200
bps by executing software commands. However, communication errors may occur because of the oscilla-
tion frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud
rate.
After executing commands from a peripheral unit that requires time to erase and write data, as with erase
and program commands, allow a sufficient time interval or execute the read status command and check
how processing ended, before executing the next command.
Data and status registers in memory can be read after transmitting software commands. Status, such as
the operating state of the flash memory or whether a program or erase operation ended successfully or not,
can be checked by reading the status register. Here following are explained initial communications with
peripheral units, how frequency is identified and software commands.

Initial communications with peripheral units

After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre-
quency of the main clock, by sending the code as prescribed by the protocol for initial communications
with peripheral units (Figure 1.35.23).
(1) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit
rate generator so that "0016" can be successfully received.)
(2) The MCU with internal flash memory outputs the "B016" check code and initial communications end
successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer
interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps.

*1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main
clock.

Peripheral unit MCU with internal

flash memory

Reset

(1) Transfer "0016" 16 times

1st "0016"
At least 15ms
2nd "0016"
transfer interval

15 th "0016"

16th "0016"
"B016" (2) Transfer check code "B016"

The bit rate generator setting completes (9600bps)

Figure 1.35.23. Peripheral unit and initial communication

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

How frequency is identified

When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the
bit rate generator is set to match the operating frequency (2 - 30 MHz). The highest speed is taken from
the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit
rate generator value for a baud rate of 9,600 bps.
Baud rate cannot be attained with some operating frequencies. Table 1.35.4 gives the operation fre-
quency and the baud rate that can be attained for.

Table 1.35.4 Operation frequency and the baud rate

Operation frequency Baud rate Baud rate Baud rate Baud rate Baud rate
(MHZ) 9,600bps 19,200bps 38,400bps 57,600bps 115,200bps

30MHz √ √ √ √ –
20MHz √ √ √ √ √
16MHZ √ √ √ √ –
12MHZ √ √ √ √ –
11MHZ √ √ √ √ –
10MHZ √ √ √ √ –
8MHZ √ √ √ √ –
7.3728MHZ √ √ √ √ –
6MHZ √ √ √ – –
5MHZ √ √ √ – –
4.5MHZ √ √ √ √ –
4.194304MHZ √ √ √ – –
4MHZ √ √ – – –
3.58MHZ √ √ √ √ –
3MHZ √ √ √ – –
2MHZ √ – – – –

√ : Communications possible
– : Communications not possible

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Software Commands
Table 1.35.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and
reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O mode 2
adds five transmission speed commands - 9,600, 19,200, 38,400, 57,600 and 115,200 bps - to the soft-
ware commands of standard serial I/O mode 1. Software commands are explained here below.

Table 1.35.5. Software commands (Standard serial I/O mode 2)

1st byte When ID is
Control command transfer 2nd byte 3rd byte 4th byte 5th byte 6th byte
not verified
Address Address Data Data Data Data Not
1 Page read FF16 (middle) (high) output output output output to acceptable
259th byte
Address Address Data Data Data Data input Not
2 Page program 4116 (middle) (high) input input input to 259th acceptable
byte

Address Address D016 Not

3 Block erase 2016 (middle) (high) acceptable
D016 Not
4 Erase all unlocked blocks A716 acceptable
SRD SRD1 Acceptable
5 Read status register 7016 output output
Not
6 Clear status register 5016 acceptable
Address Address Lock bit Not
7 Read lock bit status 7116 (middle) (high) data acceptable
output
Address Address D016 Not
8 Lock bit program 7716 (middle) (high) acceptable
Not
9 Lock bit enable 7A16 acceptable
Not
10 Lock bit disable 7516 acceptable
Address
Address Address
11 Code processing function F516 (middle)
(low) (high) ID size ID1 To ID7 Acceptable
Size Check- To Not
12 Download function FA16 Size (low) (high) sum Data required acceptable
input number
of times
Version Version Version Version Version Version
13 Version data output function FB16 data data data data data data Acceptable
output output output output output output to
9th byte
Address Address Data Data Data Data Not
14 Boot ROM area output FC16 (middle) (high) output output output output to acceptable
function 259th byte
Check Check Not
15 Read check data FD16 data (low) data acceptable
(high)

16 Baud rate 9600 B016 B016 Acceptable

17 Baud rate 19200 B116 B116 Acceptable

18 Baud rate 38400 B216 B216 Acceptable

19 Baud rate 57600 B316 B316 Acceptable

20 Baud rate 115200 B416 B416 Acceptable

Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note 2: SRD refers to status register data. SRD1 refers to status register data 1.
Note 3: All commands can be accepted when the flash memory is totally blank.

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Page Read Command

This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.

RxD1 FF16 A8 to A16 to

(M32C reception data) A15 A23

TxD1 data0 data255

(M32C transmit data)

Figure 1.35.24. Timing for page read

Page Program Command

This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses
A8 to A23 is input sequentially from the smallest address first, that page is automatically written.

The result of the page program can be known by reading the status register. For more information, see
the section on the status register.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed with already programmed pages.

RxD1 4116 A8 to A16 to data0 data255

(M32C reception data) A15 A23

TxD1
(M32C transmit data)

Figure 1.35.25. Timing for the page program

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Transfer the “2016” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the
erase operation will start for the specified block in the flash memory. Write the highest address of
the specified block for addresses A16 to A23.

After block erase ends, the result of the block erase operation can be known by reading the status
register. For more information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.

RxD1 A8 to A16 to
2016 D016
(M32C reception data) A15 A23

TxD1
(M32C transmit data)

Figure 1.35.26. Timing for block erasing

Erase All Unlocked Blocks Command

This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the
erase operation will start and continue for all blocks in the flash memory.
The result of the erase operation can be known by reading the status register. Each block can be erase-
protected with the lock bit. For more information, see the section on the data protection function.

RxD1
(M32C reception data) A716 D016

TxD1
(M32C transmit data)

Figure 1.35.27. Timing for erasing all unlocked blocks

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Read Status Register Command

This command reads status information. When the “7016” command code is sent with the 1st byte, the
contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1
(SRD1) specified with the 3rd byte are read.

RxD1 7016
(M32C reception data)

SRD SRD1
TxD1 output output
(M32C transmit data)

Figure 1.35.28. Timing for reading the status register

Clear Status Register Command

This command clears the bits (SR3–SR5) which are set when the status register operation ends in
error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared.

RxD1 5016
(M32C reception data)

TxD1
(M32C transmit data)

Figure 1.35.29. Timing for clearing the status register

Read Lock Bit Status Command

This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Transfer the “7116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) The lock bit data of the specified block is output with the 4th byte. The 6th bit (D6) of output data
is the lock bit data. Write the highest address of the specified block for addresses A8 to A23.

RxD1 7116 A8 to A16 to

(M32C reception data) A15 A23

TxD1 DQ6
(M32C transmit data)

Figure 1.35.30. Timing for reading lock bit status

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Lock Bit Program Command

This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program
command as explained here following.
(1) Transfer the “7716” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, “0” is
written for the lock bit of the specified block. Write the highest address of the specified block for
addresses A8 to A23.
Lock bit status can be read with the read lock bit status command. For information on the lock bit
function, reset procedure and so on, see the section on the data protection function.

RxD1 7716 A8 to A16 to D016

(M32C reception data) A15 A23

TxD1
(M32C transmit data)

Figure 1.35.31. Timing for the lock bit program

Lock Bit Enable Command

This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-
mand. The command code “7A16” is sent with the 1st byte of the serial transmission. This command
only enables the lock bit function; it does not set the lock bit itself.

RxD1 7A16
(M32C reception data)

TxD1
(M32C transmit data)

Figure 1.35.32. Timing for enabling the lock bit

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Lock Bit Disable Command

This command disables the lock bit. The command code “7516” is sent with the 1st byte of the serial
transmission. This command only disables the lock bit function; it does not set the lock bit itself.
However, if an erase command is executed after executing the lock bit disable command, “0” (locked)
lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is
cancelled, the lock bit is enabled.

RxD1
(M32C reception data) 7516

TxD1
(M32C transmit data)

Figure 1.35.33. Timing for disabling the lock bit

ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,
3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.

RxD1 F516 DF16 FF16 0F16 ID size ID1 ID7

(M32C reception
data)

TxD1
(M32C transmit
data)

Figure 1.35.34. Timing for the ID check

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th
byte onward.
(4) The program to execute is sent with the 5th byte onward.

When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.

RxD1 Check Program Program

FA16 sum data
(M32C reception data) data

Data size (low)

TxD1 Data size (high)
(M32C transmit data)

Figure 1.35.35. Timing for download

Version Information Output Command

This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.

RxD1 FB16
(M32C reception data)

TxD1
(M32C transmit data) 'V' 'E' 'R' 'X'

Figure 1.35.36. Timing for version information output

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Boot ROM Area Output Command

This command outputs the control program stored in the boot ROM area in one page blocks (256
bytes). Execute the boot ROM area output command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.

CLK1

RxD1 A8 to A16 to
FC16
(M32C reception data) A15 A23

TxD1
(M32C transmit data) data0 data255

RTS1(BUSY)

Figure 1.35.37. Timing for boot ROM area output

Read Check Data

This command reads the check data that confirms that the write data, which was sent with the page
program command, was successfully received.
(1) Transfer the "FD16" command code with the 1st byte.
(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.

To use this read check data command, first execute the command and then initialize the check data.
Next, execute the page program command the required number of times. After that, when the read
check command is executed again, the check data for all of the read data that was sent with the page
program command during this time is read. The check data is the result of CRC operation of write
data.

RxD1 FD16
(M32C reception data)

TxD1
(M32C transmit data)

Check data (low) Check data (high)

Figure 1.35.38. Timing for the read check data

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Baud Rate 9600

This command changes baud rate to 9,600 bps. Execute it as follows.
(1) Transfer the "B016" command code with the 1st byte.
(2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps.

RxD1 B016
(M32C reception data)

TxD1 B016
(M32C transmit data)

Figure 1.35.39. Timing of baud rate 9600

Baud Rate 19200

This command changes baud rate to 19,200 bps. Execute it as follows.
(1) Transfer the "B116" command code with the 1st byte.
(2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps.

RxD1 B116
(M32C reception data)

TxD1 B116
(M32C transmit data)

Figure 1.35.40. Timing of baud rate 19200

Baud Rate 38400

This command changes baud rate to 38,400 bps. Execute it as follows.
(1) Transfer the "B216" command code with the 1st byte.
(2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps.

RxD1 B216
(M32C reception data)

TxD1 B216
(M32C transmit data)

Figure 1.35.41. Timing of baud rate 38400

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Baud Rate 57600

This command changes baud rate to 57,600 bps. Execute it as follows.
(1) Transfer the "B316" command code with the 1st byte.
(2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps.

RxD1 B316
(M32C reception data)

TxD1 B316
(M32C transmit data)

Figure 1.35.42. Timing of baud rate 57600

Baud Rate 115200

This command changes baud rate to 115,200 bps. Execute it as follows.
(1) Transfer the "B416" command code with the 1st byte.
(2) After the "B416" check code is output with the 2nd byte, change the baud rate to 19,200 bps.

RxD1 B416
(M32C reception data)

TxD1 B416
(M32C transmit data)

Figure 1.35.43. Timing of baud rate 115200

ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFFDF 16 , 0FFFFE3 16 , 0FFFFEB 16 , 0FFFFEF 16, 0FFFFF3 16 , 0FFFFF7 16 and
0FFFFFB16. Write a program into the flash memory, which already has the ID code set for these
addresses.

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Address
0FFFFDC16 to 0FFFFDF16 ID1 Undefined instruction vector

0FFFFE016 to 0FFFFE316 ID2 Overflow vector

0FFFFE416 to 0FFFFE716 BRK instruction vector

0FFFFE816 to 0FFFFEB16 ID3 Address match vector

0FFFFEC16 to 0FFFFEF16 ID4

0FFFFF016 to 0FFFFF316 ID5 Watchdog timer vector

0FFFFF416 to 0FFFFF716 ID6

0FFFFF816 to 0FFFFFB16 ID7 NMI vector

0FFFFFC16 to 0FFFFFF16 Reset vector

4 bytes

Figure 1.35.44. ID code storage addresses

Example Circuit Application for The Standard Serial I/O Mode 2

The below figure shows a circuit application for the standard serial I/O mode 2.

CLK1
Monitor output RTS1(BUSY)

Data input RXD1

Data output TXD1

M32C/80 Flash
memory version
CNVss
NMI

P50(CE)

P55(EPM)

In this example, the microprocessor mode and standard serial I/O mode
are switched via a switch.

Figure 1.35.45. Example circuit application for the standard serial I/O mode 2

432
 REVISION HISTORY M32C/83 GROUP DATA SHEET

Rev. Description
Date Page Errror Correct

B1 100-pin version is added.

1/8/2001 Flash memory version is added.
Others
B1 2,3 Tables 1.1.1 and 1.1.2
30/8/ Interrupt: 12 internal/external sources
2001 (intelligent I/O and CAN module) Delate
Supply voltage 3.0 to 3.6V (f(XIN)=20MHz without wait) add
3 A-D converter
10 bits (8 channels) x 2 circuits, max 26 inputs 10 bits x 2 circuits, standard 10 inputs, max 26 inputs
7 Table 1.1.3 Pin 26 CANIN addition
10-12 Figures 1.1.4, 1.1.5, Table 1.1.7 CANIN is added to Pin 17(GP) and pin 19(FP)
11 Figure 1.1.5 Pin 97 AN00 AN0
12 Pin 32 (FP) Vcc Delate
Pin 34 (FP) Vss Delate
13 Vcc position to pin 64(FP) Pin 62
Vss position to pin 66(FP) Pin 64
RxD4/SCL4/STxD4 position to pin 98 (FP) Pin 100
14 Table 1.1.5 AN20 to AN27 AN00 to AN07
AN30 to AN37 AN20 to AN27
17 Table1.1.12 P120 to P127 ISCLK description Delate
AN10 to AN17 AN150 to AN157
18 Figure 1.1.6 System clock oscillation circuit PLL oscillation stop detect addition
28, 29 Figure 1.4.3 (122), (167) Group0 receive buffer register, Group1 receive buffer
register
(123), (168) Group0 transmit buffer/receive data register, Group1
transmit buffer/receive data register
46 Note 1: Addresses 03C916, 03CB16 to 03D316 Addresses 03A016, 03A116, 03B916, 03BC16, 03BD16,
03C916, 03CB16 to 03D316
48 Figure 1.6.1 Note 2 Addition. Displase after the former Note 2
70 Figure 1.8.6 When reset of PLL control register 0
0X11 0100 0011 0100
72 Figure 1.8.8 Count value set bit Division rate select bit
Count start bit Operation enable bit
Count stop/start Divider stops/starts
Note 2 Delate
76 Line 10 Addition Stop mode is canceled before setting this bit to "1".
77 Line 8 1:Sub clock is selected 1: Clock from ring oscillator is selected
135 Figure 1.14.2 Values that can be set Pulse width
modulation mode (8-bit PWM)
0016 to FF16(High-order and low-order address) 0016 to FE16(High-order address) 0016 to FF16(Low-
order address)
230 Line 5, Bit 1 TrmActive TrmData
266 Table1.23.11 Waveform generate control register
1when clock synchronous serial I/O
- √
280 Table1.23.17 Note 1: When the transfer clock and transfer data are trans-
mission, transfer clock is set to at least 6 divisions of

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 REVISION HISTORY M32C/83 GROUP DATA SHEET

Rev. Description
Date Page Errror Correct
the base timer clock. Except this, transfer clock is set
to at least 20 divisions of the base timer clock.
Note 2 Addition
285 Figure 1.23.37 Delay timing of base timer
284 Table1.24.1 A-D conversion start condition
• Timer B2 interrupt • Timer B2 interrupt occurrences frequency counter
overflow
B2 2, 3, 4 Table 1.1.1, 1.1.2
Feb/1/
Clock generating circuit 4 built-in...circuit 3 built-in clock generation circuits
2002
PLL freq. synthe. Delete
Power consumption 29mA 26mA
44mA 38mA
6,10, Fig 1.1.3-1.1.5 Note: P70 and P71 are N-channel...output.-> Add
11
18 Fig 1.1.6 System clock generator
PLL Delete
Oscillation stop detection Ring oscillator
24 7th line Since the value.....due to the interruption. -> Add
27 Fig 1.4.3 (1)
(2) Processor mode register 1 XX00 X000 -> X000 00XX
(3) System clock control register 0 80 -> 0000 X000
(10) Oscillation stop detect register XXXX 0000 -> 00
(17) VDC control register 1 Add
(21) DRAM refresh interval set register XXXX ?000 -> ??
(46) CAN interrupt 1 control register Add
(47) CAN interrupt 2 control register Add
28 Fig 1.4.3 (2)
(70) CAN interrupt 0 control register Add
28-31 Fig 1.4.3(2) (97)-(104), Fig 1.4.3(3) (142)-(149),
Fig 1.4.3(4) (187)-(194), Fig 1.4.3(5) (222)-(229)
Group 0 -3 time measurement/
waveform generation register 0-7 00 -> ??
29, 30 Fig 1.4.3(3) (124), Fig 1.4.3(4) (169)
Group 0,1 SI/O communication buffer register Group 0,1 SI/O receive buffer register
Fig 1.4.3(3) (125), Fig 1.4.3(4) (170)
Group 0,1 receive data register Group 0,1 transmit buffer/receive data register
(129) Group 0 SI/O comm cont register X000 XXX -> 000 X011
(186) Group 1 SI/O expansion trans cont register 0000 00XX -> 0000 0XXX
31 Fig 1.4.3(5) (238)-(241)
Group 3 waveform generate mask register 4-7 00 -> ??
32 Fig 1.4.3(6) (270)-(308) Note added
(270)-(302) Reset value changed
33 Fig 1.4.3(7) (309)-(338) Note added
(314)-(318),(321),(323),(329),(331),(336) Reset values changed
(337) CAN0 clock control register CAN0 sleep control register
36 Fig 1.4.3(10) (461) A-D control register 2 X000 XXX0 -> X000 0000

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Rev. Description
Date Page Errror Correct
38 Address 007F16 CAN interrupt 1 control register added
Address 008116 CAN interrupt 2 control register added
Address 009D16 CAN interrupt 0 control register added
61 (10) Software wait, 11th line
SFR area is accessed.....with “2 waits”. Add
67 Fig 1.8.2 System clock control register 0
When reset: 0816 0000 X0002
Note 3: When selecting fc,.....as input port. Delete
79 Fig 1.8.9
Note 7: When using PLL.....cannot be used. Delete
90 Fig 1.9.3, Symbol CAN0ICi CANiIC
110 Table 1.11.1, DMA request factors Intelligent I/O interrupt -> add
128 Fig 1.12.4, the number of cycles Change
133 Fig 1.14.3, Timer Ai mode register, MR0
Port output.....registers A and B. Port output.....registers A, B and C.
137, Table 1.14.1, 1.14.2, 1.14,4, 1.14,5
138, TAiOUT pin function Function select register C -> add
142,
144
137 Fig 1.14.7 Timer Ai mode register
bit 2 (MR0) Function select register C -> add
Location of Note 3 (b7, b6): 11 10
139 Fig 1.14.8 Timer Ai mode register
bit 2 (MR0) Function select register C -> add
143, Fig 1.14.11, 1.14.12 Timer Ai mode register
145 bit 2 (MR0) Function select register C -> add
Location of Note 3 (b7, b6): 11 10
159 Fig 1.16.5 Timer Ai mode register
bit 2 (MR0) Function select register C -> add
161 Fig 1.16.6 Reload register Reload register
n = 1 to 255
172 Fig 1.17.4 UARTi transmit/receive control register 0
Note 2 Function select register C -> add
173 Fig 1.17.5 UARTi transmit/receive control register 1
Function of bit 7: Error signal output enable bit Set to “0”
199 Fig 1.22.1 Clock control register Sleep control register
Time stamp count register Time stamp register
200 Fig 1.22.3 Bit 4 0: Forced reset 0: Reset requested
Bit 10 Time stamp count reset bit Time stamp counter reset bit
201 5th line: In no case will the CAN module be ..... In no case will the CAN be.....
Bit 3: BasicCAN mode bit Bit 3: BasicCAN mode select bit
202 Bit 8,9: Timestamp prescaler bits Bit 8, 9: Timestamp prescaler select bits
Bit 11, 1st line: Receive Error Counter Receive Error Counter Register
Transmit Error Counter Transmit Error Counter Register
209 Fig 1.22.8 bit 4: Reserved bit Sampling number
210 6. CAN0 configuration register Explanation of Bit 4 -> add

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Rev. Description
Date Page Errror Correct

211 Note:1 Setting the C0CTLR0 register’s Reset0 bit Note 1: Setting the C0CTLR0 register’s Reset0 and
to 1 resets the CAN protocol control unit, with the Reset1 bits to 1 resets the CAN, and the C0TSR
C0TSR register thereby initialized to 000016. Also, register is thereby initialized to 000016. Also, setting
setting the TSReset (timestamp count reset) bit to the TSReset (timestamp counter reset) bit to 1 ini-
1 initializes the C0TSR register to 000016 on-the- tializes the C0TSR register to 000016 on-the-fly (while
fly (while the CAN protocol control unit remains the CAN remains operating; CAN0 status register’s
operating). State_Reset bit is “0”).

212 Tq period = (C0BRP+1) Tq period = (C0BRP+1)/CPU clock

220 Fig 1.22.19 b0 b2
b2 b1
226 Fig 1.22.25 bit 0 Note 2 -> add
bit 1, When transmit, TrmData When transmit, TrmActive
bit 3 Note 2 -> add
bit 6, 7, Transmit request flag Transmit request bit
229 Fig 1.22.26, explanation of function Change
230, Fig 1.22.27, 1.22.28, 1.22.29
231, Explanation of function Message slot j (j=0 to 15) -> change
232
233 Fig 1.22.30, CAN0 message slot butter i data m
Symbol C0SLOT0_m (m=0 to 3) C0SLOT0_n (n=m+6, m=0 to 3)
C0SLOT0_m (m=4 to 7) C0SLOT0_n (n=m+6, m=4 to 7)
C0SLOT1_m (m=0 to 3) C0SLOT1_n (n=m+6, m=0 to 3)
C0SLOT1_m (m=4 to 7) C0SLOT1_n (n=m+6, m=4 to 7)
235 Table 1.23.1 Group 2, WG register - -> 8chs
Group 3 Comm shift register 16bits x 2chs -> -
240 Fig 1.23.5, Group i base timer cont reg 0
Bit 2 to bit 6, explanations on fPLL Delete
245 Table 1.23.2, Count reset condition, Group 2, 3
(3) Reset request ..... circuit (3) Reset request ..... circuit (group 2 only)
245 Fig 1.23.10 fPLL Delete
246 Fig 1.23.11 Newly added
248 Fig 1.23.13, the values when reset: 0016 000016
249 Table 1.23.3, select function, digital filter function
Strips off pulses less than 3 cycles long from f1 Pulses will pass when they match either f1 or the base
and the base timerclock. timerclock 3 times.
250 Fig 1.23.14, (c) Change
252 Fig 1.23.16, reset values for both registers 000016 -> XXXX16
256 Fig 1.23.20, When WG register is “xxxb16” When WG register is “xxxa16”
270 Table 1.23.12
Transmission start condition
• Write data to transmit buffer register • Write data to transmit buffer
Interrupt request generation timing
•When transmitting
- When SI/O transmit buffer register is..... - When transmit buffer is .....
•When receiving
When....to SI/O communication buffer register When.....to SI/O receive buffer register

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 REVISION HISTORY M32C/83 GROUP DATA SHEET

Rev. Description
Date Page Errror Correct
270 Select function
This.....TxD pin output and RxD pin input. This.....ISTxD pin output and ISRxD pin input.
271 Table 1.23.13, Transfer clock input
•Selects I/O with function..... •Select I/O port with function.....
271 Fig 1.23.31
Write to communication buffer Write to receive buffer
(Input to INPC2/ISRxD0 pin) (Input to INPCi2/ISRxDi pin (i=0, 1))
272 Table 1.23.14
Transmission start condition
• Write data to transmit buffer register • Write data to transmit buffer
Interrupt request generation timing
•When transmitting
- When SI/O transmit buffer register is..... - When transmit buffer is .....
•When receiving
When....to SI/O communication buffer register When.....to SI/O receive buffer register
Error detection
• Overrun error:
.....before contents of receive buffer register.... .....before contents o SI/O receive buffer register.....
273 Fig 1.23.32
Write to communication buffer Write to receive buffer
273 Fig 1.23.33
(Input to INPC2/ISRxD0 pin) (Input to INPCi2/ISRxDi pin (i=0, 1))
279 Table 1.23.17
Transmission start condition
• Write data to transmit buffer register • Write data to SI/O transmit buffer register
Reception start condition
• Write data to transmit buffer register • Write data to SI/O transmit buffer register
Interrupt request generation timing
•When receiving
When....to SI/O communication buffer register When.....to SI/O receive buffer register
Select function
This.....TxD pin output and RxD pin input. This.....ISTxD pin output and ISRxD pin input.
286 Fig 1.24.4, A-D control register 2
When reset: X000 XXX02 X000 00002
287, Fig 1.24.5, Note 4 and Fig 1.24.6, Note 3
288 ..... by A-D sweep pin select bits..... .....by analog input port select bits.....
292 (e) Replace function of input pin
2nd line: .....of A-D0 and A-D2. .....of A-D0 and A-D1.
293 (f) , at the end of 2nd line as AN0.....respectively. -> add
(g) 3rd line: ....., input via AN00 to AN07 is..... , input via AN0 to AN7 is.....
294 Table 1.24.9 P00 analog input P95 analog input
P01 analog input P96 analog input
312 Fig 1.29.1, P00 to P07, P20 to P27: -

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 REVISION HISTORY M32C/83 GROUP DATA SHEET

Rev. Description
Date Page Errror Correct
313 Fig 1.29.2 Delete

Pull-up selection
Pull-up selection

Direction register
Direction register
Port P1 control
register Port P1 control
register

Data bus Port latch

Data bus Port latch

Circuit (C) Delete

P15 to P17, Circuit (B): -
314 Fig 1.29.3 Add
Pull-up selection D Pull-up selection D
Function select (Note 1) Function select (Note 1)
register A register A
Direction register Direction register

Output from each Output from each

peripheral function peripheral function

P121, P122, Circuit (B): -

326 Fig 1.29.16, Pull-up register 2, Note 1 Delete
331 Table 1.29.5
_____
Bit 0, 1: Three-phase PWM output (U) 1: Three-phase PWM output (U)
_____
Bit 1, 0: Three-phase PWM output (U) 0: Three-phase PWM output (U)
331 Table 1.29.6, PS4 PS3
PSL4 PSL3
Bit 1, UART0 UART3
Bit 2, UART4 UART3
Bit 3, UART1 UART3
Bit 4, 5 UART1 UART4
A4 A3
B4 B3
334 VDC Add
337 A-D Converter
1st line: A-D A-D i (i=0,1)
1st line: A-D A-D i
2nd line: .....and to bit 0 of A-D control register 2... .....and to each bit of A-D i control register 2.....
340 (3) External interrupt
• Level sense, 2nd line: (When XIN=20MHz and..) (When XIN=30MHz and .....)
3rd line: (....., at least 250 ns.....) (....., at least 233 ns.....)
_______ _______
• When the polarity of INT0 to INT5 pins is..... • When the polarity of INT0 and INT5 pins is.....
341 Reducing power consumption, (2)
1st line, last line: AN04, AN07 AN4, AN7
343 Table 1.30.3 G0CR 00EF16 G0RI 00EC16
G1RI 012F16 G1RI 012C16
U0BRG 036116 U0BRG 036916
U0TB 036316, 036216 U0TB 036B16, 036A16
U1BRG 036916 U1BRG 02E916
U1TB 036B16, 036A16 U1TB 02EB16, 02EA16
343 Notes on CNVss pin reset at “H” level Add

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 REVISION HISTORY M32C/83 GROUP DATA SHEET

Rev. Description
Date Page Errror Correct
344- Electric characteristics Add
380
385 Fig 1.34.1, Address 037716 Address 005716
_____ _____
Bit 0: RY/BY status bit RY/BY signal status bit
385 Flash memory control register (address 005716)
_____ _____
1st line: .....the RY/BY status flag..... .....the RY/BY signal status bit.....
390 13th line of Page Program Command (4116) and
_____ _____
Fig 1.34.3: RY/BY status flag RY/BY signal status bit
391 11th line of Block Erase Command (2016/D016)
_____ _____
and Fig 1.34.4: RY/BY status flag RY/BY signal status bit
_____ _____
392 Fig 1.34.5: RY/BY status flag RY/BY signal status bit
400 3rd paragraph, 1st line
....., set the CLK1 pin to “H” level and.... ....., set the CLK1 pin to “H” level and the TxD1 pin to
“L” level, and.....
400 3rd paragraph, 2nd line
The CLK1 pin is connected to Vcc.....resistance. Add
401 P67 When using standard.....transfer. Add
419 Fig 1.35.22, Data output Pulled down
421 How frequency is identified, 2nd line: (2 - 20MHz) (2 - 30MHz)

(7/7)
 Keep safety first in your circuit designs!
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble may
occur with them. Trouble with semiconductors may lead to personal injury, fire or
property damage. Remember to give due consideration to safety when making your
circuit designs, with appropriate measures such as (i) placement of substitutive,
auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any
malfunction or mishap.

Notes regarding these materials

● These materials are intended as a reference to assist our customers in the selection
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● Mitsubishi Electric Corporation assumes no responsibility for any damage, or
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● Mitsubishi Electric Corporation semiconductors are not designed or manufactured
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MITSUBISHI SEMICONDUCTORS
M32C/83 Group DATA SHEET REV. B2

February First Edition 2002

Editioned by
Committee of editing of Mitsubishi Semiconductor DATA SHEET

Published by
Mitsubishi Electric Corp., Kitaitami Works

This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©2002 MITSUBISHI ELECTRIC CORPORATION