Experiment 1:

Aim: Plot the input and output characteristics for NMOS and PMOS

Theory:

An NMOS (n-channel metal-oxide semiconductor) transistor is one type of transistor where n-type
dopants are utilized in the gate region. A positive voltage on the gate terminal turns on the device.
This transistor is mainly used in CMOS (complementary metal-oxide semiconductor) design & also in
logic & memory chips. As compared to the PMOS transistor, this transistor is very faster, so more
transistors can be placed on a single chip.

A p-channel metal-oxide semiconductor (pMOS) transistor is one in which p-type dopants are used
in the gate region (the "channel"). A negative voltage on the gate turns the device on. PMOS uses p-
channel (+) metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic
gates and other digital circuits. PMOS transistors operate by creating an inversion layer in an n-
type transistor body. This inversion layer, called the p-channel, can conduct holes between p-
type "source" and "drain" terminals.

Input and Output Characteristics of PMOS and NMOS:

PMOS:

A PMOS transistor's input characteristics are defined by its transfer characteristic curve, illustrating
how drain current (Id) varies with gate-source voltage (Vgs). Below the threshold voltage, Id is
minimal. As VGS increases, ID rises exponentially in the subthreshold region. The threshold voltage
(Vth) represents the point at which conduction initiates.

Output characteristics are represented by the Id vs. drain-source voltage (Vds) graph, indicating the
transistor's behavior under different biasing conditions. Additionally, there's a saturation region
where the transistor functions efficiently as a current source.

NMOS:

Input characteristics:

When VGS is below the threshold voltage, ID remains negligible. As VGS increases positively, ID
experiences an exponential growth in the subthreshold region. The threshold voltage (VTH) is the
gate-source voltage at which the transistor begins to conduct.

output characteristics:

In the triode region, the transistor acts as a variable resistor, with drain current (ID) increasing
proportionally to drain-source voltage (VDS). Transitioning to the saturation (or active) region, ID
stabilizes, behaving as a current source largely unaffected by VDS variations. Finally, in the cutoff
region, when gate-source voltage (VGS) falls below the threshold, ID approaches zero, effectively
turning off the transistor.
INPUT CHARACTERISTICS OF A NMOS: (SCHEMATIC+ GRAPH)

OUTPUT CHARACTERISTICS OF A NMOS:

OUTPUT CHARACTERISTICS OF A PMOS:

Aim: Design a CMOS Inverter and plot VTC for varying width

Theory:

MOS inverter definition is a device that is used to generate logic functions is known as CMOS
inverter and is the essential component in all integrated circuits. A CMOS inverter is a FET (field
effect transistor), composed of a metal gate that lies on top of oxygen’s insulating layer on top of a
semiconductor. These inverters are used in most electronic devices which are accountable for
generating data in small circuits.

CMOS technology combines NMOS and PMOS transistors in a single chip. NMOS transistors handle
pulling current down to ground, while PMOS transistors manage pulling current up to the power
supply voltage (Vdd). This complementary setup enables efficient logic switching, using voltage
levels to represent '1' and '0'. CMOS is crucial for low power consumption and noise-resistant digital
electronics.

Schematic:

Result:
Experiment 3:

Aim: Plot the output characteristics for CMOS and calculate Propagation Delay

Theory:

Parasitic Capacitance is present in the MOSFET device. These capacitance results in delaying the
voltage change in the circuit. So, we will get limitations in our speed of operation depending on how
fast we can charge or discharge these capacitors. We can calculate the propagation delay by plotting
the output voltage w.r.t time and the delay times are represented as follows:

Here, the “p” in the subscript stands for propagation delay. The “hl” stands for high-to-low, and “lh”
stands for low-to-high.

Schematic:
Result: Propagation Delay is 435.928 pico-second

Experiment 4:

Aim: Design NAND and NOR Gates Using NMOS and PMOS Transistors

Theory:

NAND and NOR gates are pivotal elements in digital logic circuits, and their implementation relies on
MOSFET transistors. These include both NMOS and PMOS types, both of which are fundamental to
these designs.

NAND Gate:

In cases where both inputs (A and B) are set to a high logic level, both NMOS transistors conduct,
forming a path of low resistance to ground. Concurrently, both PMOS transistors are inactive due to
the pull up resistors, maintaining a high voltage level at the output. When either of the inputs (A or
B) is at a low logic level, the respective NMOS transistor deactivates, establishing a path of high
resistance to ground. The corresponding PMOS transistor becomes active, linking the output to VDD
via the pull up resistor, resulting in a high output.

NOR Gate:

In situations where both inputs (A and B) are set to a low logic level, both PMOS transistors are in an
active state, providing a path of low resistance to the source voltage. Simultaneously, both NMOS
transistors are inactive, upholding a high voltage level at the output.If either of the inputs (A or B) is
at a low logic level, the respective NMOS transistor deactivates, creating a path of high resistance to
ground. The corresponding PMOS transistor switches on, connecting the output to ground through
the pull down network, resulting in a low output.

Schematic Diagram and Graph:

NAND:

NOR
Experiment 5:

Aim: To implement the Boolean expression ((A+B+C).D)’

Theory:

For the expression ((A+B+C).D)’ , the truth table as follows:

A B C D ((A+B+C).D)’
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

Schematic and Output Graph: