UNIT V

PORTS: Ports are essential to connect a microcontroller to the outside world. The
primary function of a microcontroller is to accept data from input devices such as
keyboards and A/D converters, read instructions from memory, process data according
to the instructions and send the result to output devices. This input and output devices
are called either peripherals or I/O devices.
8051 I/O ports structure is extremely versatile. It has four parallel
ports via p0, p1, p2 and p3 each port of 8 bits. These constitute (8x4) 32 I/O lines and all
ports are bi-directional. Each pin may be serving as input, output or both under software
control.

Port 0: port 0 is an 8 bit port with 8 I/O lines. Port 0 pin serve as

Input or output pins(I/O)

Address/data bus

Port 0 occupies a total of 8 pins. It can be used for input or output. To use
the pins of port 0 as both input and output ports, each pin must be connected externally
to a 10k-ohm pull-up resistor. This is due to the fact that p0 is an open drain. Open drain is
a term used for MOS chip. In any system using 8051chip we normally connect p0 to pull up
resistors.

Port 0 also designed as AD0-AD7, allowing it to be used for both address and
data. When connecting an 8051 to an external memory, port 0 provides both address and
data.
The following code will continuously send out to port 0 the alternating
values of 55H and AAH. It must be noted that complementing 55H (01010101) turns into
AAH (10101010). By sending 55H and AAH to a given port continuously, we toggle all the
bits of that port.
 ;Toggle all bits of p0
Back : MOV A, #55H
MOV P0,A
ACALL DEALY
MOV A, #0AAH
MOV P0,A
ACALL DEALY
SJMP BACK

PORT 0 AS INPUT & OUTPUT: In order to make port 0 as input, the port must be
programmed. By writing 1 to all the bits. In the following code, port 0 is configured first
as an input port by writing 1s to it.
BACK MOV A, #0FFH A= FF hex
MOV P0, A make p0 an input port by writing all 1s to it
CPL A compliments the accumulator
ACALL DELAY wait
MOV P0, A make p0 an output port by writing all 0s to it
SJMP BACK keep doing it
PORT 1: Port 1 occupies a total of 8 pins. It can be used as input or output. In contrast
to port 0, this port does not need any pull-up resistors since it already has pull-up
resistors internally. Upon reset, port 1 is configured as an input port

PORT 1 AS INPUT AND OUTPUT PORT: In order to make port 0 as input, the port must
be programmed. By writing 1 to all the bits. In the following code, port 0 is configured
first as an input port by writing 1s to it.
BACK MOV A, #0FFH A= FF hex
MOV P1, A make p0 an input port by writing all 1s to it
CPL A compliments the accumulator
ACALL DELAY wait
MOV P1, A make p0 an output port by writing all 0s to it
SJMP BACK keep doing it
 Port 2: port 2 is an 8 bit port with 8 I/O lines. Port 2 pin serve as
Input or output pins(I/O)
Address bus
Port 2 can be used as I/O port, when address bus is not required to access
external memory. External pull-up resistors are required for port2 during I/O mode,
internal pull-up resistors are off. When the port 2 pins are assigned as address bus the
output pins are connected through internal pull-up resistors
Note: I/O mode (pull-up resistors), Address bus (no pull-up resistors)

PORT 2 AS INPUT AND OUTPUT PORT: In order to make port 0 as input, the port must be
programmed. By writing 1 to all the bits. In the following code, port 0 is configured first as
an input port by writing 1s to it.
BACK MOV A, #0FFH A= FF hex
MOV P2, A make p0 an input port by writing all 1s to it
CPL A compliments the accumulator
ACALL DELAY wait
MOV P2, A make p0 an output port by writing all 0s to it
SJMP BACK keep doing it

I/O PORT BIT ADDRESSABILITY:

Sometimes we need to access only 1 or 2 bits or the port instead of the

entire 8 bits. A powerful feature of 8051 I/O ports is their capability to access individual
bits of the port without altering the rest of the bits in that port. We can access a port in
single bit manner, we use the syntax “SETB X.Y” where X is the port number 0, 1, 2 or 3,
and Y is the desired bit number from 0 to 7 for data bits D0 TO D7.

AGAIN: SETB P1.2 change only p1.2 = high

ACALL DELAY
CLR P1.2 change only p1.2 = low
 ACALL DELAY
SJMP AGAIN
SINGLE BIT ADDRESSBILITY OF PORTS:

P0 P1 P2 P3
P0.0 P1.0 P2.0 P3.0
P0.1 P1.1 P2.1 P3.1
P0.2 P1.2 P2.2 P3.2
P0.3 P1.3 P2.3 P3.3
P0.4 P1.4 P2.4 P3.4
P0.5 P1.5 P2.5 P3.5
P0.6 P1.6 P2.6 P3.6
P0.7 P1.7 P2.7 P3.7

Write the following program

(a) Create a square wave of 50% duty cycle on bit 0 of port 1
(b) Create a square wave of 66% duty cycle on bit 3 of port 1

Solution:

(a) The 50% duty cycle means that ON and OFF states have the same length.
Therefore, we toggle p1.0 with a time delay in between each state.

HERE : SETB P1.0 set to high bit 0 of port 1

LCALL DELAY call the delay subroutine
CLR P1.0 p1.0 = 0
LCALL DELAY wait
SJMP HERE keep doing
SUBPROGRAM: (delay for 0.5ms)

MOV R5, #0A6H load register

 LOOP DEC R5 decrement r5
CJNE R5, #00H, LOOP compare and jump
RET return to main program

0.5 ms

P1.0 0.5 ms

(b) 66% duty cycle means the ON state is twice the OFF state:

HERE : SETB P1.0 set to high bit 0 of port 1

LCALL DELAY call the delay subroutine
LCALL DELAY call the delay subroutine
CLR P1.0 p1.0 = 0
LCALL DELAY wait
SJMP HERE keep doing

SUBPROGRAM: (delay for 0.5ms)

MOV R5, #0A6H load register
LOOP DEC R5 Decrement R5
CJNE R5, #00H, LOOP compare and jump
RET return to main program

1 ms

P1.3 0.5ms
 INTERRUPTS IN 8051 MICROCONTROLLER: An interrupt is a signal informing the processor
that an event has occurred. When a processor receives an interrupt signal, it performs
some specified task. This signal can cause a processor, to temporarily stop executing the
current sequence of instructions of the current program and perform some other
sequence to service that signal (interrupt).
Signals coming from outside sources are called as hardware interrupts, and
signals generated by the software program are called as software interrupts .
WHY INTERRUPTS: interrupts are considered as important or abnormal conditions, which
the processor should attend. External peripheral devices use interrupts to report events
and request that actions be performed.
MASTABLE AND NON MASKABLE INTERRUPTS: The interrupt of a processor can be
classified as Maskble or non- mask able. A maskable interrupt is one that can be turned off
or disabled by the CPU. A non – mask able interrupt cannot be ignored by the CPU, it must
be serviced. In some instances this form of interrupt is used on power fail conditions.

8051 INTERRUPTS: There are 5 sources of interrupts in 8051, namely,

1. INT0
2. INT1
3. TIMER 0
4. TIMER 1
5. SERIAL PORT

INT 0 and INT 1 are external interrupts and TIMER 0, TIMER 1 and SERIAL PORT interrupts
are internal interrupts.

INTERRUPT ENABLE (IE) REGISTER: Each interrupt source can be individually

enabled or disabled by setting or clearing a bit in special function register IE. IE also
contains global disabled bit

IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

EA X ET2 ES ET1 EX1 ET0 EX0

 EA IE.7 Each interrupt can be individually enabled or disabled by programming
X IE.6 Not implemented reserved for future use*
ET2 IE.5 Enables or disables the timer 2 overflow (8052 only)
ES IE.4 If 1 enables the serial port interrupt and 0 disables the serial port
ET1 IE.3 Enables or disables the timer 1 overflow interrupts
EX1 IE.2 Enables or disables the external interrupt 1 (INT1)
ET0 IE.1 Enables or disables the timer 0 overflow interrupts
EX0 IE.0 Enables or disables the external interrupt 0 (INT0

INTERRUPT PRIORITIES: Each source of the interrupt can be individually programmed

to be in either of the two priority levels.
The interrupt priority register (IP) specifies which one of existing interrupt
sources has higher priority and which one has lower priority. Interrupt priority is
usually specified at the beginning of the program. According to that, there are several
possibilities.
If an interrupt of higher priority arrives while an interrupt is in progress, it will be
immediately stopped and the higher priority will be executed first
If two interrupts requests, at different priority levels, arrive at the same time then the
higher priority interrupt is serviced first

If the both interrupt requests, at the same priority level, occur one after another, the
one which came later has to wait until routine being in progress ends.
If two interrupt requests of equal priority arrive at the same time then the inteeupts to
be serviced is selected according to the following priority list.
If two interrupt requests of equal priority arrive at the same time then the interrupt to
be serviced according to the following priority list.
External interrupt INT0
TIMER 0 INTERRUPT
 External interrupt INT1
Timer 1 interrupt
Serial communication interrupts.

IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0

X X PT2 PS PT1 PX1 PT0 PX0

X IP.7 Not implemented reserved for future use

X IP.6 Not implemented reserved for future use
PT2 IP.5 Timer 2 overflow interrupt (8051 only)
PS IP.4 Priority of serial port interrupt, set/cleared by program
PT1 IP.3 Priority at timer 1 overflow interrupt set/cleared by program
PX1 IP.2 Priority at external interrupts 1 set/cleared by program
PT0 IP.1 Priority at timer 0 overflow interrupts. Set/cleared by program
PX0 IP.0 Priority at external interrupts 0. Set/cleared by program

Show the instruction to

(a) Enable the serial interrupt, timer 0 interrupt, and external hardware interrupt 1 (EX1),
(b) Disable the timer 0 interrupt, then
(c) Show how to disable all the interrupts with a single instruction.
Solution:
(a) MOV IE, #10010110B ; enable serial, timer 0, EX1
(b) CLR IE.1 ; disable timer 0 interrupt only
(c) CLR IE.7 ; Disable all interrupts
Another way to perform the MOV IE, #10010110B instruction is by using single –bit
instruction as shown below.

SETB IE.7 EA = 1 Global enable

SETB IE.4 enable serial interrupt
SETB IE.1 enable timer 0 interrupt
SETB IE.2 enable EX1