p pron menory ahd on-chip data memory

)iINtthe control signals used to interface the external memory

Kbvtes of progranm memory and Kbytesof data memnory can bc interfaced
lo SOST
4 HEA is connectodto Vec, the address of on-chip ROM i fo
number of bytes is allocated for SFR in on-chip data memory.

2.5 ||| NTERN.\LMEMORY LNTEREACING

The NOSt devies have onty 256 bytes of on-chip data random access memory. In applications where large
amount of data randomaccess nmemory is required, the external data random access mcmory is interfaced
witlh NO51. Address, ata. RD (P3.7) and WR (P3.6) pins are used to interface data RAM. P3.7 and P3.6 are
conneeted to RD and WRpins of data RAM as shown in Fig, 2.9.

RD
P3.7
WR
P3.6
Voc EA PSEN
WR RD
P2.7
CS
P2.6
P2.5 A13
8051 P2.0 A8
ALE
16K x 8
Data
G
RAM
PO.7 A7

P0.0 74LS373 A0

D7 DO

Figure 2.9 Connection to external data RAM

Ihe memory chip requires 14 address lines (A13-A0) to decode 16384 x 8 registers. The renmaining
address lines- A15 andAl4 pin are connected through OR gate to CS pin of external data RAM. When
the address lines AI5 and Al4 are low, then external data RAM is selected. The address of external data
RAM is 00004 to 3FFFH. Since LÀ is comected to Vec, internal program memory is selected for address
0000H to OFFFH.
s
DOK
H32 8051 Microcontroller: Hardware, Software &Applications

EXAMPLE 2.1
Design a microcontroller system using 8osi microcontroller, 4 Kbytes of ROM and 8 Kbytes of RAM,
Intertace the external memory such that the startingaddress of ROM is 100oHand RAM is CoooH.
Figure 2.10 shows the interfacingof 4 Kbytes of ROM and 8 Kbytes of RAM. Then, PSEN iS USed as
chip select pin for ROM containing program code, and RD (P2.7) is used as read control
WR iS USed as write controlsiqnal for RAM as signal pin, and
shown in Fig. 2.10.
lable 2.5 gives the memory address. ROM requires 12 address lines (A11-Ao) to
registers. The remaining address lines-A15, A14, A13, A12 and PSEN pin -are decode 4o96 x8
OR gate to CS and RD pin of ROM. When the address lines connected through
A15, A14, A13, PSEN are low and A12 is
high, then ROM is selected. RAM requires 13 address lines
The remaining address lines- A15, A14 and A13-are (A12-Ao) to decode 8192 X8 registers.
connected
When the address lines A15, A14 are high and A13 is low, then through OR gate to CS pin of RAM.
is 1000H to 1FFFH and RAM is RAM is selected. The address of ROM
CoooH to DFFFH.
TABLE 2.5
Memory address table
Address A15 A14 A13 A12 A10 A9 A8 A7 A6 AS A4
ROM A0
(4 K) 0
0 (
to
0 0
RAM
(8 K)
)
to ()
0
1

VGc EA P3.6
WR
RD
P3.7 Vcc Vcc
PSEN
P2.7
RD Vpp WA Vpp
P2.6
P2.5 CS RD
P2.7
P2.4 P2.6
8051 P2.5
P2.3
P2.4
P2.0 A11 |A12
A8 |A11
A8
ALE G 4K x 8
Po.7 8K x 8
ROM
PO.0
74LS373 RAM
A7 2

A0 A7
A0
D7 DO
D7 Do

Figure 2.10 Connection to external ROM and external RAM

 Chapter 2The8051 Microcontroller 33
EXAMPLE 2.2 | |
Design amicrocontroller system using the 8o51
DAM. Interface the memory such that the microcontroller, 16 Kbytes of ROM and 32 Kbytes of
starting address of ROM is o000H and RAM is 8o0oH.
Fiqure 2.11 shows the interfacing of 16
Kbytes of ROM and 32 Kbytes of data RAM. Then, PSEN
eIsed as chip select pin tor ROM containing
program code, and RD (P3.7) is used as readcontrol
signal pin, and WRis Used as write control signal for
Table 2.6 qives the memory address. ROM RAM as shown in Fig. 2.11.
reoisters. The remaining address lines-A15,requires 14 address lines (A13-Ao) to decode 16384
X8
and RD pin of ROM. When the address A14 and PSEN pin-are connected through OR gate to
lines A15, A14 and PSEN are low, then ROM is
The RAM requires 15 address lines selected.
(A14-Ao) to decode 32768 x 8 registers. The address line
connected through NOT gate to CS pin of data RAM. When the A15 is
PAM is selected. The address of address line A1s is high, then data
program ROM is oo00H to zFFFH and data RAM is 800oH to
FFFFH.
TABLE 2.6
Memory address table
Address A15 AI4 Al3 A12 Al1 A10 A9 A8 A7 A6 AS A4 A3 A2 Al A0
ROM
(16 K) 0 0
0 0 0 0 0
to
0 1 1
RAM
(32 K) 0 0 0 0 0 0
to
1
1

WR Voc
P3.6
Gnd EA RD Vcc
P3.7
WR Vpp
RD Vpp
RD
PSENjt
P2.7 CS 28Cs
P2.7-O
P2.6 P2.6 A14
8051 32K x 8
P2.5 A13 A13
P2.0 A8 A8
ALE 16K x 8

P0.7
ROM RAM
P0.0 74LS373 A7 A7
AC AO
D7 DO D7 DO

Figure 2.11 Connection to external ROM and external RAM

 Solle
Miciocontroller Ilardwar
NOS1

EMLE 2.3 Program ROM and

iTocontroler, 8 Kbytes
usng the 8o51that
Deson a mcro ontoller system
the memory such the starting address of program ROM is o00OH
Interface
kbytesof data RQM
and data RAMisEoooH
the terfaing of 8 Kbytes of program ROM and 8 Kbytes of data ROM, Then
Frqure 2.12 shows program code and RD (P3.7) is uSed as rend
PSNNUsed as chp select pin for ROM Contaning
Fig. 2.12. Table 2.7 shows the meme.
ontrol sional pin for ROM contaming data as shown in
8192 8 registers.
address The memory chip requres 13 ddaress 1ines(A12-A0) to decode

TUSLE2.7 Memory address table

Address AL5 A|4 A3 A2 A| A1O A9 A8 A7 A6 AS A4 A3 A2 Al A0
Program ROM
0 0 0 (0 0 0 0 0 0
to

Data ROM
(8K) 1 0 0 0 0 0 0 0
to

RD Vcc
EA P3.7 Vcc
P3.6 WR
RD Vpp
PSEN RD Vpp
P2.7
P2.7
P2.6 CS
P2.5 P2.6 CS
P2.4 A12 P2.5
P2.0 A12
8051 A8
ALE
A8
G 8K x8 8K x 8
DATA PROGRAM
PO.7
PO0
74LS373
RAM ROM
A7
A7
A0
A0
D7 DO
D7 DO

Tigure 2. 12 (onecon to extenal data

ROM nd external program ROM