CIrCC

Consumer Infrared Communications Controller

FEATURES

• Multi-Protocol Serial Communications • Programmable DMA Refresh Counter

Controller • High-Speed NS16C550A-Compatible
• Full IrDA v1.0 Implementation: 2.4 kbps to Universal Asynchronous Receiver/
115.2 kbps Transmitter Interface (ACE UART) with 16-
• Consumer Infrared Remote Control Interface Byte Send and Receive FIFOs
• SHARP Amplitude Shift Keyed Infrared • ISA Single-Byte and Burst-Mode DMA and
(ASK IR) Interface Interrupt-Driven Programmed I/O with Zero
• Direct Rx/Tx Infrared Diode Control (Raw) Wait State and String Move Timing
and General Purpose Data Pins • Automatic Transceiver Control
• Programmable High-Speed Synchronous • Transmit Pulse Width Limiter
Communications Engine (SCE) with a 32- • SCE Transmit Delay Timer
Byte FIFO and Programmable Threshold • IR Media Busy Indicator

GENERAL DESCRIPTION

This document describes the Consumer Infrared version 1.0 and consumer IR modes. All of the
Communications Controller (CIrCC) function, SCE modes use DMA. The CIrCC offers flexible
which is common to a number of SMSC signal routing and programmable output control
products. The CIrCC consists of two main through the Raw mode interface, General
architectural blocks: the ACE 16C550A UART Purpose Data pins and Output Multiplexer.
and a Synchronous Communications Engine Hardware decoding of the NEC PPM Consumer
(SCE) (Figure 2). Each Block is supported by its IR Remote Control format is implemented in the
own unique register set. CIrCC. The CIrCC provides a PME output signal
that is used to indicate the occurrence of a valid
The CIrCC UART-driven IrDA SIR and SHARP CIR Wake-up event. Chip-level address
ASK modes are backward-compatible with early decoding is required to access the CIrCC register
SMSC Super I/O and Ultra I/O infrared sets.
implementations. The CIrCC SCE supports IrDA
 TABLE OF CONTENTS

FEATURES............................................................................................................................... 1

GENERAL DESCRIPTION....................................................................................................... 1

INTERFACE DESCRIPTION.................................................................................................... 5
PORTS ..................................................................................................................................... 5
CHIP-LEVEL CONFIGURATION CONTROLS...................................................................... 7
RAW IR ................................................................................................................................... 10

CONSUMER IR (REMOTE CONTROL)................................................................................. 11

INTRODUCTION ................................................................................................................. 11
NEC HARDWARE FRAME DECODING.............................................................................. 11
IrDA SIR AND SHARP ASK IR INTERFACE ................................................................................ 17

REGISTERS ........................................................................................................................... 22
ACE UART CONTROLS ...................................................................................................... 22
SCE CONTROLS................................................................................................................. 23
MASTER BLOCK CONTROL REGISTER ........................................................................... 24
REGISTER BLOCK ZERO................................................................................................... 25
REGISTER BLOCK ONE..................................................................................................... 30
REGISTER BLOCK TWO .................................................................................................... 35
REGISTER BLOCK THREE ................................................................................................ 38
ACE UART.............................................................................................................................. 39
REGISTER DESCRIPTION ................................................................................................. 39
SCE ......................................................................................................................................... 54

SCE ......................................................................................................................................... 54
FRAMING ............................................................................................................................ 54
ACTIVE FRAME INDICATOR.............................................................................................. 54
FRAME ERRORS ................................................................................................................ 55
BUS INTERFACE I/O ............................................................................................................. 56
FIFO MULTIPLEXER........................................................................................................... 56
32-BYTE SCE FIFO ............................................................................................................. 56
DMA ..................................................................................................................................... 58
PROGRAMMED I/O............................................................................................................. 61
IOCHRDY TIME-OUT ............................................................................................................. 63
ZERO WAIT STATE SUPPORT .................................................................................................. 65
2
OUTPUT MULTIPLEXER....................................................................................................... 66

CHIP-LEVEL CIrCC ADDRESSING SUPPORT.................................................................... 68

AC TIMING ............................................................................................................................. 69

3
 Encoders
Raw
REG IST ERS ACE SCE IR IR
UART T ransducer
Consum er
M odule
IR Output
M ux
ASK
IR

IrDA COM
Bus Interface Clock G enerator
I/O IR

COM M AUX
Port
SM C Infrared Communications Controller

System Controls

FIGURE 1 - SMSC CIrCC FUNCTIONAL COMPONENTS

nACE ACE
Bus Interface Registers
COM
ISA Controls IR
Databus IrDA SIR
Data (0-7) ACE UART
MUX
Sharp ASK COM
Address (0-2)
Output
MUX AUX
FIFO,
DMA, I/O, SCE Consumer
Interrupts G.P.

SCE Raw
nSCE Registers

FIGURE 2 - CIrCC ARCHITECTURAL BLOCK DIAGRAM

4
 INTERFACE DESCRIPTION

The Interface Description lists the signals that Ports

are required to place the CIrCC in a larger chip-
level context. The three Ports (IR, COM, and AUX) provide
external access for serial data and controls. The
There are four groups of signals in this section: active CIrCC encoder is routed through the
PORT signals, HOST BUS controls, SYSTEM Output Multiplexer to the IR, COM, or AUX port.
controls, and CHIP-LEVEL CONFIGURATION
controls.

Table 1 - IR Port Signals

NAME SIZE (BITS) TYPE DESCRIPTION
IRRx 1 Input Infrared Receive Data
IRTx 1 Output Infrared Transmit Data

Table 2 - COM Port Signals

NAME SIZE (BITS) TYPE DESCRIPTION
CRx 1 Input COM Receive Data
CTx 1 Output COM Transmit Data
nRTS 1 Output Request to Send
nDTR 1 Output Data Terminal Ready
nCTS 1 Input Clear To Send
nDSR 1 Input Data Set Ready
nDCD 1 Input Data Carrier Detect
nRI 1 Input Ring Indicator

Table 3 - AUX Port Signals

(e.g., can be used for high-current drivers for Consumer IR)
NAME SIZE (BITS) TYPE DESCRIPTION
ARx 1 Input Aux. Receive Data
ATx 1 Output Aux. Transmit Data

5
 Table 4 - HOST Signals
NAME SIZE (BITS) TYPE DESCRIPTION
D0-D7 8 Bi-directional Host Data Bus
A0-A2 3 Input CIrCC Register Address Bus
nIOR 1 Input ISA I/O Read
nIOW 1 Input ISA I/O Write
AEN 1 Input ISA Address Enable
DRQ 1 Output DMA Request
nDACK 1 Input ISA DMA Acknowledge
TC 1 Input ISA DMA Terminal Count
IRQ 1 Output Interrupt Request
IOCHRDY 1 Output ISA I/O Channel Ready
nSRDY 1 Output ISA Synchronous Ready (Zero Wait State)

6
 Table 5 - SYSTEM Signals
NAME SIZE (BITS) TYPE DESCRIPTION
CLK 1 Input System Clock
RESET 1 Input CIrCC System Reset
CIR_PME 1 Output CIR PME Wake Event
Power Down 1 Input Low Power Control
DMAEN 1 Output DRQ Tristate Control
IRQEN 1 Output IRQ Tristate Control
nACE 1 Input ACE 550 Register Bank Select
nSCE 1 Input SCE Register Bank Select
VCC Power System Supply
GND Power System Ground

DMAEN received and a PME Wake event can be issued.

(See the PME WAKE bit in the Consumer IR
DMAEN is used by the chip-level interface to Control Register in SCE Register Block Two).
tristate the CIrCC DRQ output when the DMA
Enable bit is inactive. The DMA Enable bit is CHIP-LEVEL CONFIGURATION CONTROLS
located in SCE Configuration Register B, bit 0.
The following signals come from chip-level
IRQEN configuration registers. There are two types of
Chip-Level Configuration Controls: CIrCC-
IRQEN is used by the chip-level interface to Specific controls, and Legacy Controls. Both
tristate the CIrCC IRQ output when the OUT2 bit types have equivalent controls in either the
is inactive. The OUT2 bit is located in 16C550A CIrCC ACE or SCE Registers.
MODEM Control Register.
The CIrCC-Specific controls have been newly
Power Down added primarily to support the CIrCC block.
Provisions have been made in new chip-level
The Power Down pin is used by the chip-level configuration contexts to accommodate these
interface to put the SCE into low power mode. signals.
Note: Power Down only forces the SCE into low
power mode. The ACE power down function is The Legacy controls already exist in other
not a part of this specification. contexts. Provisions have been made in legacy
devices to accommodate these controls from
CIR_PME either the Chip-Level Configuration Registers or
the CIrCC Registers; i.e., the last updated value
CIR_PME is used by a chip-level interface to from either source determines the current control
indicate that a valid NEC control frame has been state and is visible in both registers.

7
 Table 6 - CIrCC-Specific Chip-Level Controls
NAME SIZE (BITS) TYPE DESCRIPTION
DMA Channel 4 Input ISA DMA Channel Number
IRQ Level 4 Input ISA Interrupt Level
Software Select A 8 Input Software Programmable Register A
Software Select B 8 Input Software Programmable Register B

DMA Channel value appears in the lower nibble of CIrCC

Register Block Three, Address Four.
4 bit bus from a chip-level configuration register,
used to identify the current CIrCC DMA channel Software Select A/B
number. The value appears in the upper nibble
of CIrCC Register Block Three, Address Four. The 8 bit Software Select A and Software Select
B inputs come from software-only programmable
IRQ Level chip-level configuration controls. The values on
these buses appear in CIrCC Register Block
4 bit bus from a chip-level configuration register, Three, Addresses Five and Six.
used to identify the current CIrCC IRQ level. The

8
 Table 7 - Legacy Chip-Level Controls
NAME SIZE (BITS) TYPE DESCRIPTION
Tx Polarity 1 Input Output Mux. Transmit Polarity
Rx Polarity 1 Input Output Mux. Receive Polarity
Half Duplex 1 Input 16C550A UART Half Duplex
Control
IR Half Duplex Timeout 8 Input IR Transceiver Turnaround Time
IR Mode 3 Input IR Mode Register Bits
IR Location 2 Input IR Option Register Location Bits

Tx Polarity IR Half Duplex Timeout

Typically part of a 16C550A Serial Port Option Typically part of a 16C550A Serial Port 2
Register. The value also appears in CIrCC Configuration Register. The value also appears
Register Block One, Address Zero. in CIrCC Register Block One, Address Zero.

Rx Polarity IR Mode

Typically part of a 16C550A Serial Port Option Typically part of a 16C550A Serial Port Option
Register. The value also appears in CIrCC Register. These values are also part of the
Register Block One, Address Zero. CIrCC Block Control bits 3-5, Register Block
One, Address Zero.
Half Duplex
IR Location
Typically part of a 16C550A Serial Port Option
Register. The value also appears in CIrCC Typically part of a 16C550A Serial Port IR Option
Register Block One, Address Zero. Register. These values are the CIrCC Output
Mux bits, Register Block One, Address One.
Note: These legacy controls are uniformly
updated in the CIrCC and the Top-Level Device
Configuration Registers only when either set of
registers is explicitly written using IOW or
following a device-level POR. CIrCC software
resets will not affect the legacy bits.

9
 OPERATION MODES
RAW IR
The Raw Rx Control bit in SCE Line Control
In Raw mode the state of the IR emitter and Register A represents the state of the PIN diode.
detector can be directly accessed through the For example, depending on the state of the Rx
host interface (Figure 3). Polarity control a logic '1' may mean no IR is
detected, a logic '0' may mean IR is being
The IR emitter tracks the Raw Tx Control bit in detected. If an IR carrier is present, the Raw Rx
SCE Line Control Register A. For example, Control bit will oscillate at the carrier frequency.
depending on the state of the Tx Polarity control
a logic '1' may turn the LED on and a logic '0' If enabled, a Raw Mode Interrupt will occur when
may turn the LED off. Care must be taken in the Raw Rx Control bit transitions to the active
software to ensure that the LED is not on state, depending on the state of the Rx Polarity
continuously. control. Raw Mode is enabled with the Block
Control Bits in SCE Configuration Register A
(see page 30).

Encoder/Decoder
RAW Tx

Registers RAW Rx

Enable Transition
Detect

Interrupt

FIGURE 3 - RAW IR BLOCK DIAGRAM

10
 CONSUMER IR (REMOTE CONTROL)

INTRODUCTION NEC HARDWARE FRAME DECODING

The CIrCC Consumer IR Remote Control block General

is a general-purpose programmable
Synchronous Amplitude Shift Keyed serial The CIrCC implements hardware-level decoding
communications interface that includes a Carrier for the NEC Consumer IR Remote Control
Frequency Divider, a Programmable Receive format. The hardware decoder may be used to
Carrier Range Sensitivity Register, Receive and generate a wake-up event or to send parts of the
Transmit Modulators and an NEC PPM Frame received message frame to the FIFO. The No
Format Decoder. Care Custom Code (NCCC), No Care Data Code
(NCDC), PME Wake and Frame bits of the
The Consumer IR transmit block transfers data Consumer IR Control register configure the
LSB first between the SCE and Output hardware decoder.
Multiplexer as a fixed bit-cell serial NRZ data
stream. The components of this block can also NEC Consumer IR Format
modulate serial data at programmable data rates
and carrier frequencies. The NEC Consumer IR Remote Control format
specifies a 38kHz carrier, 13ms of sync framing,
Variable length encoding and message framing and 32 bits of pulse-position modulated (PPM)
is handled during transmit by system software. message data. The message data includes an 8
Receive message framing may be handled by bit Custom Code field, an 8 bit Custom Code’
either hardware or software. The high degree of field, an 8 bit Data Code field, and an 8 bit Data
control afforded to the system software allows for Code’ field. A single frame of the NEC PPM
the support of many encoding methods; including Consumer Remote Control output is shown in
PPM, PWM and RC-5 Remote Control formats. Figure 5.

Register controls for the Consumer IR hardware The Custom Code fields in this protocol uniquely
can be found in Register Block Two. They are address message frames for specific devices.
the Consumer IR Control Register, the The Custom Code fields can be used as a 16 bit
Consumer IR Carrier Rate Register, the address or as an 8 bit address followed by the
Consumer IR Bit Rate Register, the Custom bit-wise complement of the Custom Code field
Code Register, the Custom Code’ Register, and Custom Code’. The Data Code field is an 8 bit
the Data Code Register. command code, Data Code’ is the bit-wise
complement of Data Code.

Note: The CIrCC hardware can decode NEC

protocol framing (sync pulse, 32 bit PPM
message data) at any carrier frequency or data
rate, depending on the programmed Carrier
Frequency Divider (CFD) and Bit Rate Divider
(BRD).

11
 Encoder/Decoder Tx Enable

Transmit Bit-Rate CIR Tx

Divider

SCE Clock Carrier Frequency

Carrier Off Divider

Programmable
Receive Bit-Rate CIR Rx
Receive Carrier
Divider
Sense
Rx Enable Sync
Range

FIGURE 4 - CIrCC CONSUMER IR (REMOTE CONTROL) BLOCK

C C C C C C C C C’ C’ C’ C’ C’ C’ C’ C’ D D D D D D D D D’ D’ D’ D’ D’ D’ D’ D’
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

L eader C ode C u sto m C o d e C u sto m C o d e ’ D a ta C o d e D a ta C o d e

1 .1 2 5 m s

.5 6 2 5 m s

9m s 4 .5 m s 2 .2 5 m s

0 1

8 .7 7 u s
3 8 K H z C a r r ie r
2 6 .3 u s ( 9 m s o r .5 6 2 5 m s )

FIGURE 5 - NEC PPM CONSUMER REMOTE CONTROL OUTPUT

12
Carrier Frequency Divider carrier like for the NEC remote control frame
format: Fc = 38.095kHz. This is ~.25%
The Carrier Frequency Divider register is used to accuracy. Table 8 contains representative CFD
program the ASK carrier frequency for the vs. Carrier Frequency relationships.
transmit modulator and receive detector (Figure
6). The divider is eight bits wide. The Carrier Frequency range is 1.6MHz to
6.25kHz.
The input clock to the Carrier Frequency Divider
is 1.6MHz (48MHz ÷ 30). The relationship The carrier frequency encoder/decoder can be
between the divider value (CFD) and the carrier defeated using the Carrier Off bit. When Carrier
frequency (Fc) is as follows: Off is one, the transmitter outputs a non-
modulated SCE serial NRZ data stream at the
CFD = (1.6MHz/Fc) - 1 programmed bit rate; the receiver does not
attempt to demodulate a carrier from the
For example, program the Carrier Frequency incoming serial data stream.
Divider register with 41 ('29'Hex) for a 38kHz

Table 8 - Representative Carrier Frequencies

CFD Fc (kHz) CFD Fc (kHz) CFD Fc (kHz) CFD Fc (kHz)
001 800.000 065 24.242 129 12.308 193 8.247
005 266.667 069 22.857 133 11.940 197 8.081
009 160.000 073 21.622 137 11.594 201 7.921
013 114.286 077 20.513 141 11.268 205 7.767
017 88.889 081 19.512 145 10.959 209 7.619
021 72.727 085 18.605 149 10.667 213 7.477
025 61.538 089 17.778 153 10.390 217 7.339
029 53.333 093 17.021 157 10.127 221 7.207
033 47.059 097 16.327 161 9.877 225 7.080
037 42.105 101 15.686 165 9.639 229 6.957
041 38.095 105 15.094 169 9.412 233 6.838
045 34.783 109 14.545 173 9.195 237 6.723
049 32.000 113 14.035 177 8.989 241 6.612
053 29.630 117 13.559 181 8.791 245 6.504
057 27.586 121 13.115 185 8.602 249 6.400
061 25.806 125 12.698 189 8.421 253 6.299

13
Bit Rate Divider like for the NEC remote control frame format: Fb
= 1.786kHz. This is ~.5% accuracy. Table 9
The Transmit and Receive Bit Rate Divider contains representative BRD vs. Bit Rate
register is used to extract a serial NRZ data relationships. The Bit Rate range is 100kHz to
stream for the CIrCC SCE. The divider is eight 390.625Hz.
bits wide.
It is important to note that the bit rate as
The input clock to the Bit Rate Divider is 100kHz determined by the SCE CIR Bit Rate Divider
(Carrier Frequency Divider input clock ÷ 16). register is not necessarily the data signaling rate
The relationship between the Bit Rate Divider for any given consumer remote control
(BRD) and the Bit Rate (Fb) is as follows: modulation scheme. For example, to support the
NEC PPM remote control message frame format
BRD = (.1MHz/Fb) - 1 in the CIrCC, the value programmed in the SCE
CIR Bit Rate register must be one half of the
For example, program the Bit Rate Divider with signaling rate for an NEC PPM “0” (see Figure
55 ('37'Hex) for a .562ms Remote Control bit cell 5).

Table 9 - Representative Bit Rates

BRD Fb (kHz) BRD Fb (kHz) BRD Fb (kHz) BRD Fb (kHz)

003 25.000 067 1.471 131 0.758 195 0.510
007 12.500 071 1.389 135 0.735 199 0.500
011 8.333 075 1.316 139 0.714 203 0.490
015 6.250 079 1.250 143 0.694 207 0.481
019 5.000 083 1.190 147 0.676 211 0.472
023 4.167 087 1.136 151 0.658 215 0.463
027 3.571 091 1.087 155 0.641 219 0.455
031 3.125 095 1.042 159 0.625 223 0.446
035 2.778 099 1.000 163 0.610 227 0.439
039 2.500 103 0.962 167 0.595 231 0.431
043 2.273 107 0.926 171 0.581 235 0.424
047 2.083 111 0.893 175 0.568 239 0.417
051 1.923 115 0.862 179 0.556 243 0.410
055 1.786 119 0.833 183 0.543 247 0.403
059 1.667 123 0.806 187 0.532 251 0.397
063 1.563 127 0.781 191 0.521 255 0.391

14
Receive Carrier Sense wide-to-narrow range of carrier frequencies. The
register is two bits wide.
The Programmable Receive Carrier Sense The range values are shown in Table 10.
register is used to program the Consumer IR Carriers that fall outside of the programmed
decoder to detect the presence of IR energy in a range set the Frame Abort bit. If the “Carrier Off”
bit is active, the Receive Carrier range sensitivity
function is disabled.

Table 10 - Receive Carrier Sense Range

D1 D0 RANGE
0 0 ±10%
0 1 ±20%
1 0 ±40%
1 1 Reserved

1 0 1

SCE Tx Data
Transmitter
Light
TV Tx Output No Light
Tx Polarity bit = 1 (default) 1/Carrier

TV Rx Input No Light

Receiver Light

SCE Rx Data
Driver
Rx Polarity bit = 0 (default) 1/Bit Rate

FIGURE 6 - REMOTE CONTROL ASK ENCODE/DECODE

15
Receiver Bit Cell Synchronization Receiver synchronization can be disabled to
allow direct sampling of the demodulated
The Consumer IR Receiver demodulates incoming infrared data stream at some preset
incoming ASK waveforms into NRZ data for the receive bit rate. This is useful in situations where
SCE. The CIrCC uses the edges of the the speed of the receive data is not strictly
demodulated incoming infrared data to indicate known. In such cases, the receive bit rate is set
changes in bit state. as high as possible, the Receiver Bit Cell
Synchronization is disabled, and the system
For continuous periods of high or low data software is used to measure the bit-cell period
without transitions, the CIrCC samples the signal from the over sampled data. The learned
level in the center of each incoming bit period. parameters can then be used to switch to the
Using the Receiver Bit Cell Synchronization synchronized, fixed bit-cell mode to reduce
mechanism, any transition resets the timer that is processing overhead in the host CPU for all
used in the sampling process to eliminate errors future transactions.
due to timing differences between the receive
decoder and the incoming bit period (Figure 7).

Clock 1 2 3 4 5 6 7 8 9 10
Sync Sync

IR Rx Data

NRZ Rx Data 1 1 0 0 0 1 1 1 0
(SYNC)

Clock 1 2 3 4 5 6 7 8 9 10 11

IR Rx Data
NRZ Rx Data 1 1 0 0 0 1 1 1 1 0
(No SYNC)

FIGURE 7 - REMOTE CONTROL RECEIVER: SYNC VS. NO SYNC

16
IrDA SIR AND SHARP ASK IR INTERFACE A one is signaled by sending no transmission
during the bit time. Please refer to the AC timing
This interface uses the ACE UART to provide a for the parameters of the ASKIR waveform.
two-way wireless communications port using
infrared as a transmission medium. Two distinct If the Half Duplex option is chosen, there is a
implementations have been provided in this block time-out when the direction of the transmission is
of the CIrCC, IrDA SIR and Sharp ASK IR. changed. This time-out starts at the last bit
transferred during a transmission and blocks the
IrDA SIR allows serial communication at baud receiver input until the time-out expires. If the
rates up to 115K Baud. Each word is sent transmit buffer is loaded with more data before
serially beginning with a zero value start bit. the time-out expires, the timer is restarted after
Sending a single infrared pulse at the beginning the new byte is transmitted. If data is loaded into
of the serial bit time signals a zero. A one is the transmit buffer while a character is being
signaled by sending no infrared pulse during the received, the transmission will not start until the
bit time. Please refer to Figure 8-Figure 11 for time-out expires after the last receive bit has
the parameters of these pulses and the IrDA been received. If the start bit of another
waveform. character is received during this time-out, the
timer is restarted after the new character is
The SHARP ASK interface allows asynchronous received. The time-out is programmable up to a
amplitude shift keyed serial communication at maximum of 10ms through the IR Half-Duplex
baud rates up to 19.2K Baud. Each word is sent Time-Out Configuration Register. Note: The IR
serially beginning with a zero value start bit. A Half Duplex Timeout is disabled in hardware
zero is signaled by sending a 500kHz waveform when the CIR decoder is configured for wake-up.
for the duration of the serial bit time.

17
 DATA 0 0 0 0 0
1 1 1 1 1 1

t2
t1 t2 t1
IRRX
nIRRX

FIGURE 8 - IrDA SIR RECEIVE TIMING

PARAMETER MIN TYP MAX UNITS

t1 Pulse Width at 115kbaud 1.4 1.6 2.71 µs
t1 Pulse Width at 57.6kbaud 1.4 3.22 3.69 µs
t1 Pulse Width at 38.4kbaud 1.4 4.8 5.53 µs
t1 Pulse Width at 19.2kbaud 1.4 9.7 11.07 µs
t1 Pulse Width at 9.6kbaud 1.4 19.5 22.13 µs
t1 Pulse Width at 4.8kbaud 1.4 39 44.27 µs
t1 Pulse Width at 2.4kbaud 1.4 78 88.5 µs
t2 Bit Time at 115kbaud 8.68 µs
t2 Bit Time at 57.6kbaud 17.4 µs
t2 Bit Time at 38.4kbaud 26 µs
t2 Bit Time at 19.2kbaud 52 µs
t2 Bit Time at 9.6kbaud 104 µs
t2 Bit Time at 4.8kbaud 208 µs
t2 Bit Time at 2.4kbaud 416 µs

Notes:
1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX.
2. IRRX: Rx Polarity bit = 1
nIRRX: Rx Polarity bit = 0 (default)

18
 DATA 0 0 0 0 0
1 1 1 1 1 1

t2
t1 t2 t1
IRTX

nIRTX
FIGURE 9 - IrDA SIR TRANSMIT TIMING

PARAMETER MIN TYP MAX UNITS

t1 Pulse Width at 115kbaud 1.41 1.6 2.71 µs
t1 Pulse Width at 57.6kbaud 1.41 3.22 3.69 µs
t1 Pulse Width at 38.4kbaud 1.41 4.8 5.53 µs
t1 Pulse Width at 19.2kbaud 1.41 9.7 11.07 µs
t1 Pulse Width at 9.6kbaud 1.41 19.5 22.13 µs
t1 Pulse Width at 4.8kbaud 1.41 39 44.27 µs
t1 Pulse Width at 2.4kbaud 1.41 78 88.55 µs
t2 Bit Time at 115kbaud 8.68 µs
t2 Bit Time at 57.6kbaud 17.4 µs
t2 Bit Time at 38.4kbaud 26 µs
t2 Bit Time at 19.2kbaud 52 µs
t2 Bit Time at 9.6kbaud 104 µs
t2 Bit Time at 4.8kbaud 208 µs
t2 Bit Time at 2.4kbaud 416 µs

Notes:
1. Receive Pulse Detection Criteria: A received pulse is considered detected if the received pulse is a
minimum of 1.41 µs
2. IRTX: Tx Polarity bit = 1 (default)
nIRTX: Tx Polarity bit = 0

19
 DATA
0 1 0 1 0 0 1 1 0 1 1

t1 t2
IRTX

nIRTX

t3 t4
MIRTX

t5 t6
nMIRTX
FIGURE 10 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING

PARAMETER MIN TYP MAX UNITS

t1 Modulated Output Bit Time µs
t2 Off Bit Time µs
t3 Modulated Output “On” 0.8 1 1.2 µs
t4 Modulated Output “Off” 0.8 1 1.2 µs
t5 Modulated Output “On” 0.8 1 1.2 µs
t6 Modulated Output “Off” 0.8 1 1.2 µs

Notes:
1. IRTX: Tx Polarity bit = 1 (default)
nIRTX: Tx Polarity bit = 0
MIRTX, nMIRTX are the modulated outputs.

20
 DATA 0 1 0 1 0 0 1 1 0 1 1

t1 t2

IRRX
nIRRX

t3 t4

MIRRX

t5 t6
nMIRRX

FIGURE 11 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING

PARAMETER MIN TYP MAX UNITS

t1 Modulated Output Bit Time µs
t2 Off Bit Time µs
t3 Modulated Output “On” 0.8 1 1.2 µs
t4 Modulated Output “Off” 0.8 1 1.2 µs
t5 Modulated Output “On” 0.8 1 1.2 µs
t6 Modulated Output “Off” 0.8 1 1.2 µs

Notes:
1. IRRX: Rx Polarity bit = 1
nIRRX: Rx Polarity bit = 0 (default)
MIRRX, nMIRRX are the modulated outputs.

21
 REGISTERS

The CIrCC is partially enabled through binary SCE control bank is addressed. All of the CIrCC
controls found in two 8-byte register banks. The registers are 8 bits wide.
banks, the ACE550 UART Controls and the SCE
Controls, are selected with the nACE and nSCE ACE UART CONTROLS
register-bank selector inputs found in the
Interface Description. The table below (Table 12) lists the ACE UART
Control Registers. See the current SMSC
If nACE is zero, the three least significant bits of 16C550A implementation for a complete
the Host Address Bus decode the 16C550A description.
UART control registers. If nSCE is zero, the

Table 12 - 16C550A UART Addressing

DLAB A2 A1 A0 DIRECTION REGISTER NAME
0 0 0 0 Read Receive Buffer
0 0 0 0 Write Transmit Buffer
0 0 0 1 Read/Write Interrupt Enable
X 0 1 0 Read Interrupt Identification
X 0 1 0 Write FIFO Control
X 0 1 1 Read/Write Line Control
X 1 0 0 Read/Write Modem Control
X 1 0 1 Read/Write Line Status
X 1 1 0 Read/Write Modem Status
X 1 1 1 Read/Write Scratchpad
1 0 0 0 Read/Write Divisor (LSB)
1 0 0 1 Read/Write Divisor (MSB)

22
SCE CONTROLS The Master Block Control Register controls
access to the register blocks. Table 13 lists all of
The CIrCC SCE Registers are arranged in 7-byte the SCE registers in all blocks.
blocks. Of the eight possible register blocks, four
are used in this implementation.

Table 13 - SCE Register Addressing

BLOCK ADDRESS DIRECTION REGISTER NAME
X 7 R/W Master Block Control
0 0 R/W Data Register
0 1 RO Interrupt Identification
0 2 R/W Interrupt Enable
0 3 RO Line Status (read)
0 3 WO Line Status Address (write)
0 4 R/W Line Control A
0 5 R/W Line Control B
0 6 R/W Bus Status
1 0 R/W SCE Configuration A
1 1 R/W SCE Configuration B
1 2 R/W FIFO Threshold
1 3 RO FIFO COUNT
1 6 R/W SCE Configuration C
2 0 R/W Consumer IR Control
2 1 R/W Consumer IR Carrier Rate
2 2 R/W Consumer IR Bit Rate
2 3 R/W Custom Code
2 4 R/W Custom Code
2 5 R/W Data Code
3 0 RO SMSC ID (high)
3 1 RO SMSC ID (low)
3 2 RO CHIP ID
3 3 RO VERSION Number
3 4 RO IRQ Level DMA Channel
3 5 RO Software Select A
3 6 RO Software Select B

23
MASTER BLOCK CONTROL REGISTER Address 7 is solely reserved for the Master Block
Control register. If the nSCE input is 0, the MBC
The Master Block Control Register contains the is always visible, regardless of the state of the
CIrCC Power Down bit, two reset bits, the Master Register Block Select lines.
Interrupt Enable bit, and the Register Block
Select lines (Table 14).

Table 14 - SCE Master Block Control Register

Address Direction Description Default
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 R/W Master Block Control Register '00'hex
power master master error register block
down reset int en. reset select

Register Block Select, bits 0-2 enables are active. Setting this bit to a zero
The Register Block Select bits enable access to disables all SCE interrupts regardless of the
each of the eight possible register blocks. To state of their individual enables.
access a register block other than the default (0),
write a 3 bit register block number to the least Master Reset, bit 6
significant bits of the Master Block Control Setting the Master Reset bit to one forces data in
Register. All subsequent reads and writes to the SCE registers and SCE logical blocks into
addresses 0 through 6 will access the registers in the Power-On-Reset state. The Master Reset bit
the new block. To return to register block 0, is reset to zero following the reset operation.
rewrite zeros to the register block select bits. Note: The Legacy bits (Register Block One,
Address Zero, Bits D0-D6) and the IR Half
Error Reset, bit 4 Duplex Timeout are unaffected by Master Reset.
Writing a one to the Error Reset bit will return all
of the SCE Line Status Register bits (Register Power Down, bit 7
Block Zero) to their inactive states and reset the Setting this bit to a one causes only the SCE to
Message Count bits, the Memory Count bits, and enter the low-power state. Power down mode
the Message Byte Count registers to zero. does not preclude access to the Master Block
Control register so that this mode can be
Master Interrupt Enable, bit 5 maintained entirely under software control. The
Setting the Master Interrupt Enable to one SCE can also be powered-down by the Power
enable the SCE interrupts onto the Interrupt Down input described in the Interface
Request bus (IRQ) only if their individual Description.

24
REGISTER BLOCK ZERO in Register Block Zero are used during
Consumer IR message transactions. Bits and
Register Block Zero contains the SCE Data registers marked “reserved” in the table below
Register, the Interrupt Control/Status registers, cannot be written and return 0s when read.
the Line Control/Status registers, and the Bus Programmers must set reserved bits to 0 when
Status register (Table 15). Typically, the controls writing to registers that contain reserved bits.

Table 15 - Register Block Zero

Address Direction Description Default
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 R/W Data Register
0 0 1 RO Interrupt Identification Register ‘00’hex
active eom raw fifo IR reserved
frame mode busy
0 1 0 R/W Interrupt Enable Register '00'hex
active eom raw fifo IR reserved
frame mode busy
0 1 1 RO Line Status Register (read) '00'hex
under- over- frame reserved frame reserved
run run error abort
0 1 1 WO Line Status Address Register (write)
reserved status register
address
1 0 0 R/W Line Control Register A '00'hex
fifo reserved raw tx raw rx reserved
reset
1 0 1 R/W Line Control Register B '00'hex
sce modes reserved message count
bits
1 1 0 RO Bus Status Register '00'hex
not fifo time- reserved valid
empty full out frame

Data Register (Address 0) Interrupt Identification Register (Address 1)

The Data Register is the FIFO access port. When an interrupt is active the associated
Typically, the user will only write to the FIFO interrupt identifier bit in the IID register is also
when transmitting and read from the FIFO when active regardless of the state of its individual
receiving. The host always has read access to interrupt enable or the Master Interrupt Enable,
the FIFO regardless of the state of the SCE except for the FIFO Interrupt. The Master
Modes bits or the Loopback bit. Host read Interrupt Enable and the individual Interrupt
access to the FIFO is blocked when the FIFO is Enables serve only to enable the IID register
empty. The host has write access to the FIFO interrupts onto the Interrupt Request bus IRQ
only when the Loopback bit is inactive and the shown in the Interface Description.
SCE Modes bits are zero or Transmit mode is
enabled. Host write access to the FIFO is
blocked when the FIFO is full.

25
Active Frame Interrupt, bit 7 filters, the programmed receive data rate, or the
When this bit is one, an Active Frame has state of the ACE or SCE Rx Enables (see Figure
occurred (see the Active Frame Indicator section 36). Reading the IID register will reset the IR
on page 54). The Active Frame typically Busy bit. The IR Busy bit is also reset following
indicates that the SCE receiver has detected a Master Reset and POR. If the IR Busy Enable
valid infrared carrier. Reading the Interrupt bit is high, the IR Busy Interrupt is enabled onto
Identification register resets the Active Frame the Interrupt Request bus IRQ if the master
Interrupt bit. Interrupt Enable is also active. The IR Busy
Enable bit does not affect the IR Busy bit in the
EOM Interrupt, bit 6 IID.
When this bit is one, an End of Message has
occurred. The EOM bit indicates the end of an PROGRAMMER’S NOTE: The IR Busy bit may
Abort, FIFO underruns/overruns and DMA be unintentionally activated during IR Mode
Terminal Counts. Reading the Interrupt changes.
Identification register resets the EOM bit.
Interrupt Enable Register (Address 2)
Raw Mode Interrupt, bit 5
When this bit is one, a Raw Mode interrupt has Setting any of the bits in this register to one
occurred. The Raw Mode Interrupt indicates that enables the associated interrupt (see the
the Raw Rx Control bit has gone active. Reading Interrupt Identification Register). Interrupts will
the Interrupt Identification register resets the Raw only occur if both the interrupt enable bit and the
Mode Interrupt bit. Master Interrupt Enable bit (see the Master Block
Control Register) are active.
FIFO Interrupt, bit 4
When this bit is one, a FIFO Interrupt has The interrupt enables do not affect the state of
occurred. The FIFO Interrupt indicates that the the interrupts, except for the FIFO Interrupt. For
FIFO Interrupt Enable is active and either a example, a Raw Mode interrupt that occurs while
TxServReq or a RxServReq has occurred. The the Raw Mode Interrupt Enable is inactive will be
FIFO Interrupt bit is cleared when the interrupt is visible in the IID register but will not affect IRQ.
disabled; i.e., reading the Interrupt Identification
register does not reset the FIFO Interrupt bit (see Line Status Register(s) (Address 3)
the FIFO Interrupt section on page 57).
Error Indicators (read-only)
IR Busy, bit 3 There are eight Line Status Registers at address
The IR Media Busy hardware sets the IR Busy bit 3. Each register is read-only and is accessed
in the IID high if an infrared pulse that is greater using the three Status Register Address bits,
than TPW_MIN has occurred at the receiver input, also located at this address. The FIFO
except during message transmit or during the IR Underrun, FIFO Overrun, Frame Error, and
Half Duplex Timeout following message transmit. Frame Abort Error flags indicate the status of any
one of eight message frames. The Error
TPW_MIN can be defined as 20ns#TPW_MIN#30ns Indicators, in all registers, are reset following a
Master Reset, Power-On-Reset, and Error Reset
The IR Media Busy hardware operates (see the Master Block Control Register). The
independently of the IR Rx Pulse Rejection error indicators for the current status register only
(see the Message Count bits) are reset following
a valid start of frame sequence.

26
FIFO Underrun, bit 7 address as, the Line Status Registers. The
The FIFO Underrun bit gets set to one when the Status Register Address bits are write-only and
transmitter runs out of FIFO data. occupy bits D0 to D2. To access any one of the
eight Line Status Registers first write the address
FIFO Overrun, bit 6 of the appropriate register (0 - 7), then read the
The FIFO Overrun bit gets set to one when the register contents.
receiver tries to write data to the FIFO when the
FIFO Full flag is active. Line Control Register A (Address 4)

Frame Error, bit 5 FIFO Reset, bit 7

The Frame Error bit is set to one when bit-wide When set to one, the FIFO Reset bit clears the
violations are detected during the payload, i.e. FIFO Full and Not Empty flags in the 32-byte
non-leader code, portion of NEC PPM remote SCE FIFO. The FIFO Reset bit is automatically
control message frames. set to zero following the re-initialization.

Frame Abort, bit 2 Raw Tx, bit 4

The Frame Abort bit is set to one following a The Raw Tx bit controls the state of the infrared
FIFO underrun during transmit, a FIFO Overrun emitter in Raw IR mode. The bit is read/write.
during receive, and when detected carriers are
out of range. Raw Rx, bit 3
The Raw Rx bit represents the state of the
Status Register Address, bits 0 - 2 (write- infrared detector in Raw IR mode. The bit is
only) read-only.

Three Status Register Address bits control

software access to, and reside at the same

27
Line Control Register B (Address 5) message transactions when the FRAME bit is
one. The SCE Modes bits are automatically
SCE Modes, bits 6 - 7 reset by the hardware following FIFO Overruns
The SCE Modes bits enable the SCE transmitter or Underruns. Note: The SCE Modes bits must
and receiver (Table 16). These bits are R/W and be zero for loopback tests.
must be manually reset by the host following CIR

Table 16 - SCE Modes

D7 D6 MODE DESCRIPTION
0 0 Receive/Transmit Disabled (default)
0 1 Transmit Mode
1 0 Receive Mode
1 1 Undefined

Transmit Mode Receive Mode

Transmit mode enables the SCE Consumer IR Receive mode enables the SCE Consumer IR
transmitter whenever TC goes active, or the receiver (see the Receive Timing section on
FIFO THRESHOLD has been exceeded (see the page 54). In Receive mode, the SCE FIFO
Transmit Timing section on page 54). In output is connected to the Host System Data
Transmit mode, the SCE FIFO input is Bus, the FIFO input is connected to the SCE
connected to the Host System Data Bus and the receiver output. The Consumer IR encoder will
FIFO output is connected to the SCE transmitter reset Receive mode in hardware following the
input. The Consumer IR encoder will reset rising edge of nActive Frame following a FIFO
Transmit mode in hardware following the rising underrun or TC.
edge of nActive Frame following a FIFO
underrun.

28
Message Count, bits 0 - 3 are incremented after every active frame. At
The four Message Count bits control (internal) point A in Figure 18, for example, the rising edge
hardware access to the Line Status Registers of nActive Frame increments Message Count by
and are unaffected by the Status Register one indicating that the first message has been
Address. The Message Count bits also indicate received. This means that Line Status Register
the system message-state. For example, if the #1 (status register address 0) is valid, and Line
Message Count bits are zero, i.e. the power-up Status Register #2 is currently active, although
default, Line Status Register zero is active, undefined. Hardware prevents the Message
although undefined because no messages have Count register from exceeding eight
been sent or received. The Message Count bits ('1000'Binary).

nActive Frame

Message Count (0000)

0001 0010 0011

FIGURE 18 - MESSAGE COUNT EXAMPLE

Bus Status Register (Address 6) FIFO Full, bit 6

The FIFO Full bit when set to one indicates that
FIFO Indicators (read-only) there is no room for data in the SCE FIFO.
The FIFO Indicators reflect the current status of
the SCE FIFO. Time-Out, bit 5
The Time-Out bit is the IOCHRDY time-out error
FIFO Not Empty, bit 7 bit. The Time-Out bit when set to one indicates
The FIFO Not Empty bit when set to one that an IOCHRDY time-out error has occurred
indicates that there is data in the SCE FIFO. (see the IOCHRDY Time-Out section on page
63). Time-Out is reset by the CIrCC System
Reset, following a read of the Bus Status
register, and following a Master Reset.

29
Valid Frame, bit 0 REGISTER BLOCK ONE
The Valid Frame bit reflects the state of the
internal state variable nActive Frame. When Register Block One contains the SCE control
nActive Frame=0 (active) Valid Frame=1 (active). registers (Table 17). Typically, the controls in
When nActive Frame=1 (inactive) Valid Frame=0 Register Block One are needed to configure the
(inactive). Valid Frame is only defined for the SCE before message transactions can occur.
SCE Encoder/Decoders during Transmit and Bits and registers marked “reserved” in the table
Receive. below cannot be written and return 0s when read.
Programmers must set reserved bits to 0 (zero)
when writing to registers that contain reserved
bits.

Table 17 - Register Block One

Address Direction Description Default
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 R/W SCE Configuration Register A '02'hex
aux block control half tx po- rx po-
ir bits duplx larity larity
0 0 1 R/W SCE Configuration Register B '00'hex
output mux loop- no string dma dma
bits back wait move burst enable
0 1 0 R/W FIFO Threshold Register '00'hex
0 1 1 RO FIFO COUNT '00'hex
FC7 FC6 FC5 FC4 FC3 FC3 FC1 FC0
1 0 0 Reserved
1 0 1 Reserved
1 1 0 R/W SCE Configuration Register C '03'hex
rsvd tx pw reserved DMA Refresh
limit Count

SCE Configuration Register A (Address 0) equivalent to the IR Mode bits in the chip-level
configuration space of earlier devices; e.g., the
Auxiliary IR, bit 7 FDC37C93x IR Option Register, Serial Port 2,
When the Auxiliary IR bit is one and the active Logical Device 5, Register 0xF1. Provisions
device is routed through the Output Multiplexer to have been made in legacy devices to
the IR Port or the COM Port, the transmit signal accommodate IR Mode selection through either
also appears at the Auxiliary Port. the chip-level configuration registers or the IrCC
2.0 Block Control bits; i.e., the last write from
Block Control, bits 3 – 6 either source determines the current mode
The Block Control bits select one of the six IrCC selection and is visible in both registers.
2.0 operational modes (Table 18). The three
low-order Block Control bits are

30
 TABLE 18 - IRCC LOGICAL BLOCK CONTROLS
D6 D5 D4 D3 MODE DESCRIPTION
0 0 0 0 COM 16550 UART COM Port (default)
0 0 0 1 IrDA SIR - A Up to 115.2 kbps, Variable 3/16 Pulse
0 0 1 0 ASK IR Amplitude Shift Keyed Ir Interface
0 0 1 1 IrDA SIR - B Up to 115.2 kbps, Fixed 1.6µs Pulse
0 1 0 0 - Reserved
0 1 0 1 - Reserved
0 1 1 0 CONSUMER Remote Control
0 1 1 1 RAW IR Direct IR Diode Control
1 X X X - Reserved

Half Duplex, bit 2 For backward compatibility, the Tx and Rx

When Half Duplex is zero (default), the 16C550A Polarity bits do not apply to COM mode; i.e.,
is in full duplex mode. The Half Duplex bit only when the Block Control bits are zero. The
supports the 16C550A UART; i.e., this bit has no relationship between the Output Multiplexer port
effect on the CIrCC SCE. The Half Duplex bit is signals and the Polarity bits is an exclusive-or
analogous to the chip-level configuration register (Table 19). For example, if the IRRx pin in the
Half Duplex bit and has the same effect on the Output Multiplexer is one and the Rx Polarity bit
UART. Provisions have been made in legacy is zero, the signal is inactive and therefore
devices to accommodate Half Duplex selection decoded as a one. The CIrCC Tx Polarity bit (bit
through either the chip-level configuration 1) is equivalent to the Transmit Polarity bit in the
registers or the CIrCC Half Duplex bit; i.e., the chip-level configuration space of earlier devices;
last write from either source determines the e.g., the FDC37C93x IR Option Register, Serial
current mode selection and is visible in both Port 2, Logical Device 5, Register 0xF1. The Rx
registers. Polarity bit (bit 0) is equivalent to the Receive
Polarity bit in the same register. Provisions have
Tx/Rx Polarity Bits, 0 - 1 been made in legacy devices to accommodate
The Tx and Rx Polarity bits define the active Polarity bit selection through either the chip-level
states for signals entering and exiting the Output configuration registers or the SCE registers; i.e.,
Multiplexer ports. Internal CIrCC Active states the last write from either source determines the
are typically decoded as zero. The Tx Polarity bit current Polarity bit value and is visible in both
default is one; the Rx Polarity bit default is zero. registers.

Table 19 - Tx/Rx Polarity Bit Effects

SIGNAL POLARITY BIT DECODED SIGNAL
0 0 0
0 1 1
1 0 1
1 1 0

31
SCE Configuration Register B (Address 1) Register is equivalent to Output Mux bit, D6; bit
7 (Reserved) in the FDC37C93x IR Option
Output Mux, bits 7 - 6 Register is equivalent to Output Mux bit, D7.
The Output Mux bits select the Output Provisions have been made in legacy devices to
Multiplexer port for the active encoder/decoder accommodate Output Multiplexer port selection
(Table 20). When D[7:6]=1,1 in Table 20 through either the chip-level configuration
inactive outputs depend on the state of the Tx registers or the Output Mux bits; i.e., the last
Polarity bit, otherwise inactive outputs are zero. write from either source determines the current
The Output Mux bits are equivalent to the port selection and is visible in both registers.
FDC37C93x IR Option Register bits 6-7. The IR
Location Mux, bit 6, in the FDC37C93x IR Option

Table 20 - CIrCC Output Multiplexer

D7 D6 MUX. MODE
0 0 Active Device to COM Port (default)
0 1 Active Device to IR Port
1 0 Active Device to AUX Port
1 1 Outputs Inactive

Loopback, bit 5 testing. The 32-byte FIFO input is connected to

The Loopback bit configures the FIFO and the SCE receiver output, the FIFO output is
enables the transmitter/receiver for loopback connected to the SCE transmit input. Consumer
testing. The SCE MODES bits must be set to IR loopback tests reset the Loopback bit
zero before activating the Loopback bit. When automatically when the Rx Data Size register
the Loopback bit is one, the SCE enters a full- reaches zero. Provisions must be made
duplex mode with internal loopback capability for following loopback tests in all modes to verify the
Rx message data in the FIFO.

32
No Wait, bit 3 When the DMA Burst Mode bit is one, DMA
When the No Wait bit is one, the ISA Bus Burst (Demand) mode is enabled. When the
nSRDY signal goes active following the trailing DMA Burst Mode bit is zero, Single Byte DMA
edge of the ISA I/O command and inactive mode is enabled (Table 21). See the DMA
following the rising edge (see the Zero Wait State section on page 58.
Support section on page 65).
DMA Enable, bit 0
String Move, Bit 2 DMA Enable is connected to a signal in the
When the String Move bit is one, the Interface Description called DMAEN that is used
programmed I/O host interface is qualified by by the chip-level interface to tristate the CIrCC
IOCHRDY (Table 21). See the IOCHRDY Time- DMA controls when the DMA interface is
Out section on page 63. inactive. When the DMA Enable bit is one, the
DMA host interface is active (Table 21). See the
DMA Burst Mode, bit 1 DMA section on page 58. When the DMA
Enable bit is zero (default), the nDACK and TC
inputs are disabled and DRQ output is gated off.

Table 21 - I/O Interface Modes

STRING DMA DMA
MOVE BURST ENABLE FUNCTION
0 X 0 Programmed I/O, no IOCHRDY
1 X 0 Programmed I/O, uses IOCHRDY
X 0 1 Single Byte DMA Mode
X 1 1 Demand Mode DMA

FIFO Threshold Register (Address 2) FIFO is empty. When the FIFO is full the FIFO
COUNT is 0x80. The FIFO COUNT is
The FIFO Threshold register contains the independent of the data flow direction. For
programmable FIFO threshold count. The FIFO example, if the FIFO COUNT is 0x0A during
threshold is programmable from 0 to 31. Bits 6 transmit there are ten bytes to send; if the FIFO
and 7 in the FIFO Threshold register are read- COUNT is 0x0A during receive there are ten
only and will always return zero. FIFO Threshold bytes to read.
values typically reflect the overall I/O
performance characteristics of the host; the lower Tx PW Limit, bit 6
the value, the longer the interval between service The Tx PW Limit bit enables hardware designed
requests and the faster the host must be to to restrict the IR transmit pulse width (see the
successfully service them. The same threshold Transmit Pulse Width Limit section on page 67).
value can be used for both I/O read and I/O write If Tx PW Limit = 0, The TRANSMIT PULSE
cases. WIDTH LIMIT hardware is defeated and no
transmit pulse width restrictions are made. If Tx
FIFO COUNT Register (Address 3) PW Limit = 1, The TRANSMIT PULSE WIDTH
LIMIT hardware will prevent pulses larger than
The FIFO COUNT register represents the 100Fs with a 25% duty cycle from appearing at
remaining number of data bytes in the 128-byte the IRCC TX output ports.
SCE FIFO. When the FIFO COUNT is 0x00 the

33
DMA Refresh Count, bits 0 - 1 more details. The DMA Refresh Counter can be
The DMA Refresh Count bits are used to preloaded with count values of 4, 8, 16, or 32 as
program the DMA Refresh Counter. See the determined by the DMA Refresh Count bits[1:0]
DMA Refresh Counter section on page 59 for as shown in Table 22.

Table 22 - DMA Refresh Count Bit Encoding

DMA REFRESH
COUNT BITS DMA COUNTER
D1 D0 PRELOAD VALUE
0 0 4
0 1 8
1 0 16
1 1 32 (default)

34
REGISTER BLOCK TWO (Remote Control) encoder/decoder configuration
registers (Table 23).
Register Block Two contains the Consumer IR

Table 23 - Register Block Two

ADDRESS DIR DESCRIPTION DEFAULT
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 R/W Consumer IR Remote Control Register '00'hex
sync frame pme nccc ncdc carrier carrier
bit wake off range bits
0 0 1 R/W Consumer IR Carrier Rate Register '29'hex
0 1 0 R/W Consumer IR Bit Rate Register '37'hex
0 1 1 R/W Custom Code '00'hex
1 0 0 R/W Custom Code’ '00'hex
1 0 1 R/W Data Code '00'hex
1 1 0 Reserved

Consumer IR Control Register (Address 0) Custom Code register and the NCCC bit, and
sends valid data to the FIFO.
Sync Bit, bit 7
The Sync Bit enables the receiver bit-rate clock NCCC, bit 4
synchronization mechanism. When the Sync bit The No Care Custom Code (NCCC) bit
is one, receiver edge synchronization is enabled determines the behavior of the CIR decoder
(see the Receiver Bit Cell Synchronization when the Frame bit is active (one) (Table 24).
section on page 16). When the NCCC bit is one and the PME Wake
bit is one, a PME event will be generated upon
Frame Bit, bit 6 receipt of a valid NEC CIR frame if the data code
The Frame bit determines the compatibility mode field of the NEC frame matches the value of the
of the CIR decoder (Table 24). If the Frame bit is Data Code register, regardless of the custom
one, the CIR hardware decodes NEC PPM code field of the incoming frame. When the
remote control frames. If the Frame bit is zero NCCC bit is zero (default) and the PME Wake bit
(default), frame decoding must be performed in is active (one), a PME event may be generated if
software. the custom code of the incoming NEC CIR frame
matches the value programmed into the 16 bit
PME Wake, bit 5 Custom Code register, depending upon NCDC
The PME Wake bit is used to configure the CIR qualification. When the NCCC bit is one and the
decoder for a PME wake-up event and to clear PME Wake bit is inactive (zero), the 8 bit data
the PME output (Table 24). When the PME code and the 16 bit custom code field of any
Wake bit is one, the CIR decoder qualifies valid NEC CIR frame that is received will be sent
incoming message frames depending upon the to the FIFO. When the NCCC bit is zero
state of the 16 bit Custom Code register, the 8 bit (default) and the PME Wake bit is zero, the data
Data Code register, the NCCC bit and the NCDC code field of an incoming NEC CIR frame will be
bit and activates the CIrCC PME output when written to the FIFO if the custom code field
appropriate. When the PME Wake bit is one, the matches the value programmed into the 16 bit
data received from NEC CIR remote frames is Custom Code register. Non-qualifying frames
not sent to the FIFO. When the PME Wake bit is are ignored by the hardware.
zero (default), the CIrCC PME output is cleared,
the CIR decoder qualifies incoming message NCDC, bit 3
frames depending on the state of the 16 bit
35
The No Care Data Code (NCDC) bit determines programmed in the 8 bit Data Code register,
the behavior of the CIR decoder when both the pending NCCC qualification. This enables a
Frame and the PME Wake bits are active (one) wake-up event on any key press. When the
(Table 24). When the NCDC bit is one, a PME NCDC bit is zero (default), a PME event can only
event may be generated regardless of the data be generated if the data code field in the
received NEC CIR frame matches the value
programmed in the 8 bit Data Code register;
NCCC qualification may also apply. This
enables a wake-up event for a particular key-
press. Note: The NCDC bit has no effect if either
the Frame bit or the PME Wake bit is inactive
(zero).

TABLE 24 - NCCC AND NCDC FUNCTIONALITY

PME
FRAME NCCC NCDC WAKE FUNCTION
0 X X X No CIR Hardware Framing or Wake-up Events.
1 0 X 0 The data code field of incoming frame is written to the
FIFO if the custom code field of incoming NEC CIR frame
matches the value of the 16 bit Custom Code register.
1 0 0 1 PME signal is asserted if the custom code and the data
code fields of incoming NEC CIR frame match the values
programmed in the 16 bit Custom Code and 8 bit Data
Code registers.
1 0 1 1 PME signal is asserted if the custom code field of
incoming NEC CIR frame matches the value
programmed in the 16 bit Custom Code register,
regardless of the data that is programmed in the 8-bit
Data Code register.
1 1 X 0 The custom code and the data code fields of any valid
NEC CIR frame are written to the FIFO.
1 1 0 1 PME signal is asserted if the data code field of an
incoming NEC CIR frame matches the value of the 8 bit
Data Code register.
1 1 1 1 PME asserted upon receipt of any valid NEC CIR frame.

36
Carrier Off, bit 2 Carrier Range, bits 0 - 1
The Carrier Off bit bypasses the Consumer IR The Consumer IR Carrier Range Bits set the
Carrier generator/receiver (see the Carrier carrier detect sensitivity of the receiver. The
Frequency Divider section on page 12). When effects of this register are shown in
the Carrier Off bit is one, the transmitter outputs Table 10.
a non-modulated SCE NRZ serial data stream at
the programmed bit rate. Also, when the Carrier Consumer IR Carrier Rate Register
Off bit is one, the receiver does not attempt to (Address 1)
demodulate a carrier from the incoming data
stream and samples the state of the PIN diode at The Consumer IR Carrier Rate Register
the programmed bit rate. programs the ASK carrier frequency divider. The
effects of this register are shown in Table 8.

Consumer IR Bit Rate Register (Address 2)

The Consumer IR Bit Rate Register programs

the transmit and receive bit-rate divider. The
effects of this register are shown in Table 9.

37
REGISTER BLOCK THREE parameters. Bits and registers marked “reserved”
in the table below cannot be written and return 0
Register Block Three contains the CIrCC Block when read. Programmers must set reserved bits
Identifier Registers. These read-only registers to 0 when writing to registers that contain
classify the hardware Manufacturer, the Device reserved bits.
ID, the Version number, and Host interface

Table 25 - Register Block Three

ADDRESS DIRECTION DESCRIPTION DEFAULT
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 RO SMSC ID (high-byte) '10'hex
0 0 1 RO SMSC ID (low-byte) 'B8'hex
0 1 0 RO CHIP ID 'FA'hex
0 1 1 RO VERSION Number '00'hex
1 0 0 RO IRQ Level DMA Channel Note 1
1 0 1 RO Software Select A Note 1
1 1 0 RO Software Select B Note 1

NOTE 1: The default values for these registers assume the values that have been programmed in chip-
level configuration registers.

SMSC ID (Addresses 0 - 1) the 4 bit IRQ Level Bus found in the Interface
Description.
The SMSC ID registers contain a 16 bit
manufacturer identification code. Address zero DMA Channel, bits 0 – 3
contains the high byte of this code, address one
contains the low byte. The DMA Channel bits identify the current active
DMA Channel number for this device. The value
Chip ID (Address 2) comes from the 4 bit DMA Channel Bus found in
the Interface Description.
The Chip ID register specifically identifies this
SMSC product. Software Select A (Address 5)

Version Number (Address 3) The Software Select A register is software-only

controlled from a chip-level configuration register
The Version Number register identifies the (see the CIrCC-Specific Chip-Level Controls
revision-level of the product referenced by the section on page 8).
Chip ID register.
Software Select B (Address 6)
IRQ Level/ DMA Channel (Address 4)
The Software Select B register is software-only
IRQ Level, bits 4 - 7 controlled from a chip-level configuration register
The IRQ Level bits identify the current active IRQ (see the CIrCC-Specific Chip-Level Controls
number for this device. The value comes from section on page 8).

38
 ACE UART

The SMSC CIrCC incorporates one full function changing the base address of the UART. The
UART compatible with the NS16450, the 16450 interrupt from the UART is enabled by
ACE registers and the NS16C550A. The UART programming OUT2 of the UART to a logic "1".
performs serial-to-parallel conversion on received OUT2 being a logic "0" disables the UART's
characters and parallel-to-serial conversion on interrupt.
transmit characters. The data rates are
independently programmable from 115.2K baud REGISTER DESCRIPTION
down to 50 baud. The character options are
programmable for 1 start; 1, 1.5 or 2 stop bits; Addressing of the accessible registers of the Serial
even, odd, sticky or no parity; and prioritized Port is shown below. The configuration registers
interrupts. The UART contains a programmable define the base addresses of the serial ports. The
baud rate generator that is capable of dividing the Serial Port registers are located at sequentially
input clock or crystal by a number from 1 to 65535. increasing addresses above these base
The UART is also capable of supporting the MIDI addresses. The SMSC CIrCC UART register set
data rate. Refer to the Configuration Register is described below.
section of the device data sheet for the
information on disabling, power down and

Table 26 - Addressing The Serial Port

DLAB* A2 A1 A0 REGISTER NAME
0 0 0 0 Receive Buffer (read)
0 0 0 0 Transmit Buffer (write)
0 0 0 1 Interrupt Enable (read/write)
X 0 1 0 Interrupt Identification (read)
X 0 1 0 FIFO Control (write)
X 0 1 1 Line Control (read/write)
X 1 0 0 Modem Control (read/write)
X 1 0 1 Line Status (read/write)
X 1 1 0 Modem Status (read/write)
X 1 1 1 Scratchpad (read/write)
1 0 0 0 Divisor LSB (read/write)
1 0 0 1 Divisor MSB (read/write)

*NOTE: DLAB is Bit 7 of the Line Control Register

39
The following section describes the operation of Bit 1
the registers. This bit enables the Transmitter Holding Register
Empty Interrupt when set to logic "1".
RECEIVE BUFFER REGISTER (RB)
Address Offset = 0H, DLAB = 0, READ ONLY Bit 2
This bit enables the Received Line Status Interrupt
This register holds the received incoming data when set to logic "1". The error sources causing
byte. Bit 0 is the least significant bit, which is the interrupt are Overrun, Parity, Framing and
transmitted and received first. Received data is Break. The Line Status Register must be read to
double buffered; this uses an additional shift determine the source.
register to receive the serial data stream and
convert it to a parallel 8 bit word which is Bit 3
transferred to the Receive Buffer register. The This bit enables the MODEM Status Interrupt
shift register is not accessible. when set to logic "1". This is caused when one of
the Modem Status Register bits changes state.
TRANSMIT BUFFER REGISTER (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY Bits 4 through 7
These bits are always logic "0".
This register contains the data byte to be
transmitted. The transmit buffer is double FIFO CONTROL REGISTER (FCR)
buffered, utilizing an additional shift register (not Address Offset = 2H, DLAB = X, WRITE
accessible) to convert the 8 bit data word to a
serial format. This shift register is loaded from the This is a write only register at the same location as
Transmit Buffer when the transmission of the the IIR. This register is used to enable and clear
previous byte is complete. the FIFOs, set the RCVR FIFO trigger level. Note:
DMA is not supported.
INTERRUPT ENABLE REGISTER (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE Bit 0
Setting this bit to a logic "1" enables both the XMIT
The lower four bits of this register control the and RCVR FIFOs. Clearing this bit to a logic "0"
enables of the five interrupt sources of the Serial disables both the XMIT and RCVR FIFOs and
Port interrupt. It is possible to totally disable the clears all bytes from both FIFOs. When changing
interrupt system by resetting bits 0 through 3 of from FIFO Mode to non-FIFO (16450) mode, data
this register. Similarly, setting the appropriate bits is automatically cleared from the FIFOs. This bit
of this register to a high, selected interrupts can be must be a 1 when other bits in this register are
enabled. Disabling the interrupt system inhibits written to or they will not be properly programmed.
the Interrupt Identification Register and disables
any Serial Port interrupt out of the SMSC CIrCC. Bit 1
All other system functions operate in their normal Setting this bit to a logic "1" clears all bytes in the
manner, including the Line Status and MODEM RCVR FIFO and resets its counter logic to 0. The
Status Registers. The contents of the Interrupt shift register is not cleared. This bit is self-
Enable Register are described below. clearing.

Bit 0
This bit enables the Received Data Available
Interrupt (and timeout interrupts in the FIFO mode)
when set to logic "1".

40
Bit 2 3. Transmitter Holding Register Empty
Setting this bit to a logic "1" clears all bytes in the 4. MODEM Status (lowest priority)
XMIT FIFO and resets its counter logic to 0. The
shift register is not cleared. This bit is self- Information indicating that a prioritized interrupt is
clearing. pending and the source of that interrupt is stored
in the Interrupt Identification Register (refer to
Bit 3 Table 27 - Interrupt Control Table). When the
Writing to this bit has no effect on the operation of CPU accesses the IIR, the Serial Port freezes all
the UART. The RXRDY and TXRDY pins are not interrupts and indicates the highest priority
available on this chip. pending interrupt to the CPU. During this CPU
access, even if the Serial Port records new
Bit 4,5 interrupts, the current indication does not change
Reserved until access is completed. The contents of the IIR
are described below.
RCVR FIFO
BIT 7 BIT 6 TRIGGER LEVEL Bit 0
This bit can be used in either a hardwired
0 0 1 prioritized or polled environment to indicate
0 1 4 whether an interrupt is pending. When bit 0 is a
logic "0", an interrupt is pending and the contents
1 0 8 of the IIR may be used as a pointer to the
1 1 14 appropriate internal service routine. When bit 0 is
logic "1", no interrupt is pending.
Bit 6,7
These bits are used to set the trigger level for the Bits 1 and 2
RCVR FIFO interrupt. These two bits of the IIR are used to identify the
highest priority interrupt pending as indicated by
INTERRUPT IDENTIFICATION REGISTER the Interrupt Control Table.
(IIR)
Address Offset = 2H, DLAB = X, READ Bit 3
In non-FIFO mode, this bit is a logic "0". In FIFO
By accessing this register, the host CPU can mode this bit is set along with bit 2 when a timeout
determine the highest priority interrupt and its interrupt is pending.
source. Four levels of priority interrupt exist. They
are in descending order of priority: Bits 4 and 5
These bits of the IIR are always logic "0".
1. Receiver Line Status (highest priority)
2. Received Data Ready Bits 6 and 7
These two bits are set when the FIFO CONTROL
Register bit 0 equals 1.

41
 Table 27 - Interrupt Control
FIFO INTERRUPT
MODE IDENTIFICATION
ONLY REGISTER INTERRUPT SET AND RESET FUNCTIONS
INTERRUPT
BIT 3 BIT 2 BIT 1 BIT 0 PRIORITY INTERRUPT INTERRUPT RESET
LEVEL TYPE SOURCE CONTROL
0 0 0 1 - None None -
0 1 1 0 Highest Receiver Line Overrun Error, Reading the
Status Parity Error, Line Status
Framing Error Register
or Break
Interrupt
0 1 0 0 Second Received Data Receiver Data Read
Available Available Receiver
Buffer or the
FIFO drops
below the
trigger level.
1 1 0 0 Second Character No Characters Reading the
Timeout Have Been Receiver
Indication Removed From Buffer
or Input to the Register
RCVR FIFO
during the last 4
Char times and
there is at least
1 char in it
during this time
0 0 1 0 Third Transmitter Transmitter Reading the
Holding Register Holding IIR Register (if
Empty Register Empty Source of
Interrupt) or
Writing the
Transmitter
Holding
Register
0 0 0 0 Fourth MODEM Status Clear to Send or Reading the
Data Set Ready MODEM
or Ring Status
Indicator or Register
Data Carrier
Detect

42
LINE CONTROL REGISTER (LCR) word bit and the first stop bit of the serial data.
Address Offset = 3H, DLAB = 0, READ/WRITE (The parity bit is used to generate an even or odd
number of 1s when the data word bits and the
This register contains the format information of the parity bit are summed).
serial line. The bit definitions are:
Bit 4
Bits 0 and 1 Even Parity Select bit. When bit 3 is a logic "1"
These two bits specify the number of bits in each and bit 4 is a logic "0", an odd number of logic "1"'s
transmitted or received serial character. The is transmitted or checked in the data word bits
encoding of bits 0 and 1 is as follows: and the parity bit. When bit 3 is a logic "1" and bit
4 is a logic "1" an even number of bits is
BIT 1 BIT 0 WORD LENGTH transmitted and checked.

0 0 5 Bits Bit 5
0 1 6 Bits Stick Parity bit. When bit 3 is a logic "1" and bit 5
1 0 7 Bits is a logic "1", the parity bit is transmitted and then
1 1 8 Bits detected by the receiver in the opposite state
indicated by bit 4.
The Start, Stop and Parity bits are not included in
the word length. Bit 6
Set Break Control bit. When bit 6 is a logic "1", the
Bit 2 transmit data output (TXD) is forced to the
This bit specifies the number of stop bits in each Spacing or logic "0" state and remains there (until
transmitted or received serial character. The reset by a low level bit 6) regardless of other
following table summarizes the information. transmitter activity. This feature enables the Serial
Port to alert a terminal in a communications
system.
NUMBER OF
BIT 2 WORD LENGTH STOP BITS Bit 7
0 -- 1 Divisor Latch Access bit (DLAB). It must be set
high (logic "1") to access the Divisor Latches of the
1 5 bits 1.5 Baud Rate Generator during read or write
1 6 bits 2 operations. It must be set low (logic "0") to access
the Receiver Buffer Register, the Transmitter
1 7 bits 2 Holding Register, or the Interrupt Enable Register.
1 8 bits 2
MODEM CONTROL REGISTER (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE
NOTE: The receiver will ignore all stop bits
beyond the first, regardless of the number used in
This 8 bit register controls the interface with the
transmitting.
MODEM or data set (or device emulating a
MODEM). The contents of the MODEM control
Bit 3 register are described below.
Parity Enable bit. When bit 3 is a logic "1", a parity
bit is generated (transmit data) or checked
(receive data) between the last data

43
Bit 0 In the diagnostic mode, the receiver and the
This bit controls the Data Terminal Ready (nDTR) transmitter interrupts are fully operational. The
output. When bit 0 is set to a logic "1", the nDTR MODEM Control Interrupts are also operational
output is forced to a logic "0". When bit 0 is a but the interrupts' sources are now the lower four
logic "0", the nDTR output is forced to a logic "1". bits of the MODEM Control Register instead of the
MODEM Control inputs. The interrupts are still
Bit 1 controlled by the Interrupt Enable Register.
This bit controls the Request To Send (nRTS)
output. Bit 1 affects the nRTS output in a manner Bits 5 through 7
identical to that described above for bit 0. These bits are permanently set to logic zero.

Bit 2 LINE STATUS REGISTER (LSR)

This bit controls the Output 1 (OUT1) bit. This bit Address Offset = 5H, DLAB = X, READ/
does not have an output pin and can only be read WRITE
or written by the CPU.
Bit 0
Bit 3 Data Ready (DR). It is set to a logic "1" whenever
Output 2 (OUT2). This bit is used to enable an a complete incoming character has been received
UART interrupt. When OUT2 is a logic "0", the and transferred into the Receiver Buffer Register
serial port interrupt output is forced to a high or the FIFO. Bit 0 is reset to a logic "0" by reading
impedance state - disabled. When OUT2 is a all of the data in the Receive Buffer Register or the
logic "1", the serial port interrupt outputs are FIFO.
enabled.
Bit 1
Bit 4 Overrun Error (OE). Bit 1 indicates that data in the
This bit provides the loopback feature for Receiver Buffer Register was not read before the
diagnostic testing of the Serial Port. When bit 4 is next character was transferred into the register,
set to logic "1", the following occur: thereby destroying the previous character. In
FIFO mode, an overrun error will occur only when
1. The TXD is set to the Marking State(logic "1"). the FIFO is full and the next character has been
2. The receiver Serial Input (RXD) is completely received in the shift register, the
disconnected. character in the shift register is overwritten but not
3. The output of the Transmitter Shift Register is transferred to the FIFO. The OE indicator is set to
"looped back" into the Receiver Shift Register a logic "1" immediately upon detection of an
input. overrun condition, and reset whenever the Line
4. All MODEM Control inputs (nCTS, nDSR, nRI Status Register is read.
and nDCD) are disconnected.
5. The four MODEM Control outputs (nDTR, Bit 2
nRTS, and OUT2) are internally connected to Parity Error (PE). Bit 2 indicates that the received
the four MODEM Control inputs. data character does not have the correct even or
6. The Modem Control output pins are forced odd parity, as selected by the even parity select
inactive high. bit. The PE is set to a logic "1" upon detection of a
7. Data that is transmitted is immediately parity error and is reset to a logic "0" whenever the
received. Line Status Register is read. In the FIFO mode
this error is associated with the particular character
This feature allows the processor to verify the in the FIFO it applies to. This error is indicated
transmit and receive data paths of the Serial Port. when the associated character is at the top of the
FIFO.

44
Bit 3 Bit 5
Framing Error (FE). Bit 3 indicates that the Transmitter Holding Register Empty (THRE). Bit 5
received character did not have a valid stop bit. indicates that the Serial Port is ready to accept a
Bit 3 is set to a logic "1" whenever the stop bit new character for transmission. In addition, this bit
following the last data bit or parity bit is detected causes the Serial Port to issue an interrupt when
as a zero bit (Spacing level). The FE is reset to a the Transmitter Holding Register interrupt enable
logic "0" whenever the Line Status Register is is set high. The THRE bit is set to a logic "1" when
read. In the FIFO mode this error is associated a character is transferred from the Transmitter
with the particular character in the FIFO it applies Holding Register into the Transmitter Shift
to. This error is indicated when the associated Register. The bit is reset to logic "0" whenever the
character is at the top of the FIFO. The Serial Port CPU loads the Transmitter Holding Register. In
will try to resynchronize after a framing error. To the FIFO mode this bit is set when the XMIT FIFO
do this, it assumes that the framing error was due is empty, it is cleared when at least 1 byte is
to the next start bit, so it samples this 'start' bit written to the XMIT FIFO. Bit 5 is a read only bit.
twice and then takes in the 'data'.
Bit 6
Bit 4 Transmitter Empty (TEMT). Bit 6 is set to a logic
Break Interrupt (BI). Bit 4 is set to a logic "1" "1" whenever the Transmitter Holding Register
whenever the received data input is held in the (THR) and Transmitter Shift Register (TSR) are
Spacing state (logic "0") for longer than a full word both empty. It is reset to logic "0" whenever either
transmission time (that is, the total time of the start the THR or TSR contains a data character. Bit 6
bit + data bits + parity bits + stop bits). The BI is is a read only bit. In the FIFO mode this bit is set
reset after the CPU reads the contents of the Line whenever the THR and TSR are both empty,
Status Register. In the FIFO mode this error is
associated with the particular character in the Bit 7
FIFO it applies to. This error is indicated when the This bit is permanently set to logic "0" in the 450
associated character is at the top of the FIFO. mode. In the FIFO mode, this bit is set to a logic
When break occurs only one zero character is "1" when there is at least one parity error, framing
loaded into the FIFO. Restarting after a break is error or break indication in the FIFO. This bit is
received, requires the serial data (RXD) to be logic cleared when the LSR is read if there are no
"1" for at least 1/2 bit time. subsequent errors in the FIFO.

NOTE: Bits 1 through 4 are the error conditions MODEM STATUS REGISTER (MSR)
that produce a Receiver Line Status Interrupt Address Offset = 6H, DLAB = X, READ/
whenever any of the corresponding conditions are WRITE
detected and the interrupt is enabled.
This 8 bit register provides the current state of the
control lines from the MODEM (or peripheral
device). In addition to this current state
information, four bits of the MODEM Status
Register (MSR) provide change information.

45
These bits are set to logic "1" whenever a Bit 7
control input from the MODEM changes state. This bit is the complement of the Data Carrier
They are reset to logic "0" whenever the MODEM Detect (nDCD) input. If bit 4 of the MCR is set to
Status Register is read. logic "1", this bit is equivalent to OUT2 in the MCR.

Bit 0 SCRATCHPAD REGISTER (SCR)

Delta Clear To Send (DCTS). Bit 0 indicates that Address Offset =7H, DLAB =X, READ/WRITE
the nCTS input to the chip has changed state
since the last time the MSR was read. This 8 bit read/write register has no effect on the
operation of the Serial Port. It is intended as a
Bit 1 scratchpad register to be used by the programmer
Delta Data Set Ready (DDSR). Bit 1 indicates that to hold data temporarily.
the nDSR input has changed state since the last
time the MSR was read. PROGRAMMABLE BAUD RATE GENERATOR
(AND DIVISOR LATCHES DLH, DLL)
Bit 2
Trailing Edge of Ring Indicator (TERI). Bit 2 The Serial Port contains a programmable Baud
indicates that the nRI input has changed from Rate Generator that is capable of taking any clock
logic "0" to logic "1". input (DC to 3 MHz) and dividing it by any divisor
from 1 to 65535. This output frequency of the
Bit 3 Baud Rate Generator is 16x the Baud rate. Two 8
Delta Data Carrier Detect (DDCD). Bit 3 indicates bit latches store the divisor in 16 bit binary format.
that the nDCD input to the chip has changed state. These Divisor Latches must be loaded during
initialization in order to insure desired operation of
NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic the Baud Rate Generator. Upon loading either of
"1", a MODEM Status Interrupt is generated. the Divisor Latches, a 16 bit Baud counter is
immediately loaded. This prevents long counts on
Bit 4 initial load. If a 0 is loaded into the BRG registers
This bit is the complement of the Clear To Send the output divides the clock by the number 3. If a
(nCTS) input. If bit 4 of the MCR is set to logic 1 is loaded the output is the inverse of the input
"1", this bit is equivalent to nRTS in the MCR. oscillator. If a two is loaded the output is a divide
by 2 signal with a 50% duty cycle. If a 3 or greater
Bit 5 is loaded the output is low for 2 bits and high for
This bit is the complement of the Data Set Ready the remainder of the count. The input clock to the
(nDSR) input. If bit 4 of the MCR is set to logic BRG is the 24 MHz crystal divided by 13, giving a
"1", this bit is equivalent to DTR in the MCR. 1.8462 MHz clock.

Bit 6
This bit is the complement of the Ring Indicator Table 28 shows the baud rates possible with a
(nRI) input. If bit 4 of the MCR is set to logic "1", 1.8462 MHz crystal.
this bit is equivalent to OUT1 in the MCR.

46
Effect of the Reset on Register File msec at 300 BAUD with a 12 bit
character.
The Reset Function Table (TABLE 29) details the
effect of the Reset input on each of the registers of A. Character times are calculated by using the
the Serial Port. RCLK input for a clock signal (this makes the
delay proportional to the baudrate).
FIFO INTERRUPT MODE OPERATION
B. When a timeout interrupt has occurred it is
When the RCVR FIFO and receiver interrupts are cleared and the timer reset when the CPU
enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR reads one character from the RCVR FIFO.
interrupts occur as follows:
C. When a timeout interrupt has not occurred the
A. The receive data available interrupt will be timeout timer is reset after a new character is
issued when the FIFO has reached its received or after the CPU reads the RCVR
programmed trigger level; it is cleared as FIFO.
soon as the FIFO drops below its
programmed trigger level. When the XMIT FIFO and transmitter interrupts
are enabled (FCR bit 0 = "1", IER bit 1 = "1"),
B. The IIR receive data available indication also XMIT interrupts occur as follows:
occurs when the FIFO trigger level is reached.
It is cleared when the FIFO drops below the A. The transmitter holding register interrupt (02H)
trigger level. occurs when the XMIT FIFO is empty; it is
cleared as soon as the transmitter holding
C. The receiver line status interrupt (IIR=06H), register is written to (1 of 16 characters may be
has higher priority than the received data written to the XMIT FIFO while servicing this
available (IIR=04H) interrupt. interrupt) or the IIR is read.

D. The data ready bit (LSR bit 0)is set as soon B. The transmitter FIFO empty indications will be
as a character is transferred from the shift delayed 1 character time minus the last stop
register to the RCVR FIFO. It is reset when bit time whenever the following occurs:
the FIFO is empty. THRE=1 and there have not been at least two
bytes at the same time in the transmitter FIFO
When RCVR FIFO and receiver interrupts are since the last THRE=1. The transmitter
enabled, RCVR FIFO timeout interrupts occur as interrupt after changing FCR0 will be
follows: immediate, if it is enabled.

A. A FIFO timeout interrupt occurs if all the Character timeout and RCVR FIFO trigger level
following conditions exist: interrupts have the same priority as the current
− at least one character is in the FIFO received data available interrupt; XMIT FIFO
− The most recent serial character empty has the same priority as the current
received was longer than 4 continuous transmitter holding register empty interrupt.
character times ago. (If 2 stop bits are
programmed, the second one is included FIFO POLLED MODE OPERATION
in this time delay.)
− The most recent CPU read of the FIFO With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3
was longer than 4 continuous character or all to zero puts the UART in the FIFO Polled
times ago. Mode of operation. Since the RCVR and are
− This will cause a maximum character controlled separately, either one or both can be in
received to interrupt issued delay of 160 the polled mode of operation.

47
In this mode, the user's program will check RCVR - Bit 5 indicates when the XMIT FIFO is empty.
and XMITTER status via the LSR. LSR definitions - Bit 6 indicates that both the XMIT FIFO and
for the FIFO Polled Mode are as follows: shift register is empty.
- Bit 7 indicates whether there are any errors in
- Bit 0=1 as long as there is one byte in the the RCVR FIFO.
RCVR FIFO.
- Bits 1 to 4 specify which error(s) have There is no trigger level reached or timeout
occurred. Character error status is handled condition indicated in the FIFO Polled Mode,
the same way as when in the interrupt mode, however, the RCVR and XMIT FIFOs are still fully
the IIR is not affected since EIR bit 2=0. capable of holding characters.

Table 28 - Baud Rates Using 1.8462 MHz Clock (24 MHz/13)

UART HIGH
2
DESIRED BAUD DIVISOR USED TO PERCENT ERROR DIFFERENCE SPEED BIT
RATE GENERATE 16X CLOCK BETWEEN DESIRED AND ACTUAL1
50 2304 0.001 X
75 1536 - X
110 1047 - X
134.5 857 0.004 X
150 768 - X
300 384 - X
600 192 - X
1200 96 - X
1800 64 - X
2000 58 0.005 X
2400 48 - X
3600 32 - X
4800 24 - X
7200 16 - X
9600 12 - X
19200 6 - X
38400 3 0.030 X
57600 2 0.16 X
115200 1 0.16 X
230400 32770 0.16 1
460800 32769 0.16 1
Note1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
Note2: The UART High Speed bit is located in the device configuration space.

48
 Table 29 - Reset Function Table
REGISTER/SIGNAL RESET CONTROL RESET STATE
Interrupt Enable Register RESET All bits low
Interrupt Identification Reg. RESET Bit 0 is high; Bits 1 - 7 low
FIFO Control RESET All bits low
Line Control Reg. RESET All bits low
MODEM Control Reg. RESET All bits low
Line Status Reg. RESET All bits low except 5, 6 high
MODEM Status Reg. RESET Bits 0 - 3 low; Bits 4 - 7 input
TXD1, TXD2 RESET High
INTRPT (RCVR errs) RESET/Read LSR Low
INTRPT (RCVR Data Ready) RESET/Read RBR Low
INTRPT (THRE) RESET/ReadIIR/Write THR Low
OUT2B RESET High
RTSB RESET High
DTRB RESET High
OUT1B RESET High
RCVR FIFO RESET/FCR1*FCR0/_FCR0 All Bits Low
XMIT FIFO RESET/FCR1*FCR0/_FCR0 All Bits Low

49
 Table 30 - Register Summary For An Individual UART Channel
REGISTER REGISTER
ADDRESS* REGISTER NAME SYMBOL BIT 0 BIT 1
ADDR = 0 Receive Buffer Register (Read Only) RBR Data Bit 0 Data Bit 1
DLAB = 0 (Note 1)
ADDR = 0 Transmitter Holding Register (Write THR Data Bit 0 Data Bit 1
DLAB = 0 Only)
ADDR = 1 Interrupt Enable Register IER Enable Enable
DLAB = 0 Received Transmitter
Data Holding
Available Register
Interrupt Empty
(ERDAI) Interrupt
(ETHREI)
ADDR = 2 Interrupt Ident. Register (Read Only) IIR "0" if Interrupt Interrupt ID
Pending Bit
ADDR = 2 FIFO Control Register (Write Only) FCR FIFO Enable RCVR FIFO
Reset
ADDR = 3 Line Control Register LCR Word Length Word Length
Select Bit 0 Select Bit 1
(WLS0) (WLS1)
ADDR = 4 MODEM Control Register MCR Data Request to
Terminal Send (RTS)
Ready (DTR)
ADDR = 5 Line Status Register LSR Data Ready Overrun Error
(DR) (OE)
ADDR = 6 MODEM Status Register MSR Delta Clear to Delta Data
Send (DCTS) Set Ready
(DDSR)
ADDR = 7 Scratch Register (Note 4) SCR Bit 0 Bit 1
ADDR = 0 Divisor Latch (LS) DDL Bit 0 Bit 1
DLAB = 1
ADDR = 1 Divisor Latch (MS) DLM Bit 8 Bit 9
DLAB = 1

*DLAB is Bit 7 of the Line Control Register (ADDR = 3).

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is
empty.

50
 Table 30 - Register Summary For An Individual UART Channel (continued)
BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7
Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7
Enable Enable 0 0 0 0
Receiver Line MODEM
Status Status
Interrupt Interrupt
(ELSI) (EMSI)
Interrupt ID Bit Interrupt ID Bit 0 0 FIFOs FIFOs
(Note 5) Enabled (Note Enabled (Note
5) 5)
XMIT FIFO DMA Mode Reserved Reserved RCVR Trigger RCVR Trigger
Reset Select (Note LSB MSB
6)
Number of Parity Enable Even Parity Stick Parity Set Break Divisor Latch
Stop Bits (PEN) Select (EPS) Access Bit
(STB) (DLAB)
OUT1 OUT2 Loop 0 0 0
(Note 3) (Note 3)
Parity Error Framing Error Break Transmitter Transmitter Error in RCVR
(PE) (FE) Interrupt (BI) Holding Empty (TEMT) FIFO (Note 5)
Register (Note 2)
(THRE)
Trailing Edge Delta Data Clear to Send Data Set Ring Indicator Data Carrier
Ring Indicator Carrier Detect (CTS) Ready (DSR) (RI) Detect (DCD)
(TERI) (DDCD)
Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.

51
NOTES ON SERIAL PORT OPERATION This one character Tx interrupt delay will
remain active until at least two bytes have
FIFO MODE OPERATION: been loaded into the FIFO, concurrently. When
the Tx FIFO empties after this condition, the Tx
GENERAL interrupt will be activated without a one
character delay.
The RCVR FIFO will hold up to 16 bytes
regardless of which trigger level is selected. Rx support functions and operation are quite
different from those described for the transmitter.
TX AND RX FIFO OPERATION The Rx FIFO receives data until the number of
bytes in the FIFO equals the selected interrupt
The Tx portion of the UART transmits data through trigger level. At that time if Rx interrupts are
TXD as soon as the CPU loads a byte into the Tx enabled, the UART will issue an interrupt to the
FIFO. The UART will prevent loads to the Tx CPU. The Rx FIFO will continue to store bytes
FIFO if it currently holds 16 characters. until it holds 16 of them. It will not accept any
Loading to the Tx FIFO will again be enabled as more data when it is full. Any more data entering
soon as the next character is transferred to the Tx the Rx shift register will set the Overrun Error flag.
shift register. These capabilities account for the Normally, the FIFO depth and the programmable
largely autonomous operation of the Tx. trigger levels will give the CPU ample time to
empty the Rx FIFO before an overrun occurs.
The UART starts the above operations typically
with a Tx interrupt. The chip issues a Tx interrupt One side effect of having an Rx FIFO is that the
whenever the Tx FIFO is empty and the Tx selected interrupt trigger level may be above the
interrupt is enabled, except in the following data level in the FIFO. This could occur when
instance. Assume that the Tx FIFO is empty and data at the end of the block contains fewer bytes
the CPU starts to load it. When the first byte than the trigger level. No interrupt would be issued
enters the FIFO the Tx FIFO empty interrupt will to the CPU and the data would remain in the
transition from active too inactive. Depending on UART. To prevent the software from having to
the execution speed of the service routine check for this situation the chip incorporates a
software, the UART may be able to transfer this timeout interrupt.
byte from the FIFO to the shift register before the
CPU loads another byte. If this happens, the Tx The timeout interrupt is activated when there is a
FIFO will be empty again and typically the UART's least one byte in the Rx FIFO, and neither the
interrupt line would transition to the active state. CPU nor the Rx shift register has accessed the Rx
This could cause a system with an interrupt control FIFO within 4 character times of the last byte. The
unit to record a Tx FIFO empty condition, even timeout interrupt is cleared or reset when the CPU
though the CPU is currently servicing that reads the Rx FIFO or another character enters it.
interrupt. Therefore, after the first byte has
been loaded into the FIFO the UART will wait These FIFO related features allow optimization of
one serial character transmission time before CPU/UART transactions and are especially useful
issuing a new Tx FIFO empty interrupt. given the higher baud rate capability (256 kbaud).

52
 nIOW

t1
nRTSx,
nDTRx

t5
IRQx

nCTSx,
nDSRx,
nDCDx
t6
t2 t4

IRQx
nIOW

t3
IRQx

nIOR

nRIx

FIGURE 19 - SERIAL PORT TIMING

53
 SCE

The SCE is a half-duplex synchronous serial duplex loopback functionality for diagnostic
communications controller that directs data flow testing. Bit rates from .4kbps to 100kbps are
between the Bus Interface I/O block and the supported. All of the SCE register controls are
Consumer IR (Remote Control) Encoder (Figure located in the nSCE-addressable 8-bit register
20). The SCE also includes partial full- blocks.

8 Parallel-to-Serial 1 CIR
Transm it Converter Encoder

Tim ing
Controls &
Control

8 Serial-to-Parallel 1 CIR
Receive Converter Decoder

FIGURE 20 - SCE BLOCK DIAGRAM

FRAMING Transmit
nActiveFrame goes active as soon as the
The SCE operates with and without framing, Consumer IR transmitter starts modulating the
depending on the state of the FRAME bit in the SCE data stream. nActiveFrame becomes
Consumer IR Remote Control register in SCE inactive as soon as the transmit register is
Register Block Two. With framing implies that the empty.
SCE works with the NEC Consumer IR decoder
so that the required portions of the frame Receive
message can be extracted and placed in the 32 When the FRAME bit is zero, nActiveFrame
byte FIFO. Without framing implies that the SCE goes active as soon as the Consumer IR
operates simply as a serial-to-parallel converter receiver detects the first active bit-time of
for the Consumer IR (Remote Control) infrared energy. nActiveFrame becomes inactive
encoder/decoder. whenever the Consumer IR receiver is manually
disabled, a DMA Terminal Count has occurred,
ACTIVE FRAME INDICATOR or following a FIFO Overrun.

The SCE signal nActiveFrame is a PLA state When the FRAME bit is one, nActive Frame goes
variable that is synchronized to Consumer IR active as soon as the NEC PPM frame format
message frames. nActiveFrame is primarily decoder detects valid data following the leader
used to trigger active frame interrupts. code. nActive Frame becomes inactive as soon
as the receiver updates the line status register
and signals an End-Of-Message following a FIFO
overrun.

54
FRAME ERRORS carrier for more than two or more bit cells, or the
continuous absence of carrier for four or more bit
A framing error is any bit-wide violation that cells. Note: bit cells are determined by the SCE
occurs during the payload portion of NEC CIR Bit Rate Divider register. For example; if the
consumer remote control message frames. Bit Rate Divider is programmed for the NEC
Payload data in this protocol always follows the format shown in Figure 5 when the FRAME bit is
leader code and includes the custom code and “1”, then the Frame Error bit will be set if carrier
data code fields as shown in Figure 5. is detected for 1.125ms or greater, or if no carrier
is detected for 2.25ms or greater.
The Frame Error bit in the SCE Line Status
Register is set to “1” when a framing error Note: It is possible for the FIFO to be empty with
occurs. The Frame Error bit will not be set if the Frame Error bit set at the end of an invalid
framing errors occur when the FRAME bit in the NEC remote control message frame because the
SCE Consumer IR Remote Control Register is payload data in messages with framing errors will
inactive (“0”). either be ignored or passed to the FIFO
depending on the data pattern and the frequency
The bit-wide violations that produce framing of violations.
errors are defined as the continuous presence of

55
 BUS INTERFACE I/O

The Bus Interface I/O block contains a 32-byte The Databus Multiplexer provides exclusive ISA
FIFO, DMA/Interrupt logic, and multiplexers to Bus access to either the 16C550A UART or the
control access to the FIFO and the ISA Bus CIrCC SCE depending on the state of Block
(Figure 21). Control bits. Disabled blocks are disconnected
from the ISA Bus.

SCE

Transmit FIFO 32-byte

Loopback Multiplexer FIFO

16550A UART Loopback Transmit Function

I/O & Interrupt 0 0 FIFO In to SCE Rx
Control FIFO Out to Host Bus
0 1 FIFO In to Host Bus
FIFO Out to SCE Tx
Databus Multiplexer 1 X FIFO In to SCE Rx
FIFO Out to SCE Tx
ISA Bus

FIGURE 21 - BUS INTERFACE I/O BLOCK

FIFO MULTIPLEXER HOST FIFO Access

SCE FIFO Access The host always has read access to the FIFO,
regardless of the state of the SCE Modes bits, or
The FIFO Multiplexer controls the configuration the Loopback bit. The host has write access to
of the SCE FIFO in the Bus Interface I/O Block. the FIFO when the Loopback bit is inactive and
This configuration can be inferred from the state the transmit/receive modes are disabled or the
of the SCE Modes bits in Line Control Register Transmit mode is enabled.
B. When the transmit/receive modes are
disabled, or the transmit mode is enabled, the 32-BYTE SCE FIFO
FIFO is configured for transmit, otherwise, the
FIFO is configured for receive. The signal FIFO Timing & Controls
Transmit in Figure 21, above, can be satisfied by
the inverse of the SCE Modes msb; e.g., nD7. The FIFO requires interleaved access timing to
allow simultaneous FIFO data reads and data

56
writes. This is required both for normal operation FIFO Threshold value or more data bytes in the
with asynchronous host/SCE access timing, and FIFO, given by:
during loopback tests with synchronous SCE-
only access timing where the FIFO is RxServReq ≥ 32 - FIFO Threshold
simultaneously used for transmit and receive.
FIFO controls include, separate read/ write lines, For example, if the FIFO threshold value is 12,
FIFO Full and FIFO Not Empty flags, Reset, RxServReq will be active whenever there are 20
FIFO Threshold, and Interrupt. to 32 data bytes in the FIFO. If the FIFO
Threshold is 0, RxServReq will be active
FIFO Threshold whenever the FIFO is full. If the FIFO Threshold
is 31, RxServReq will be active whenever the
The SCE FIFO Threshold generates FIFO is not empty.
programmed I/O service requests to
accommodate systems with widely varying I/O Transmit Threshold
response times. FIFO Threshold values typically
reflect the overall I/O response characteristics of Once the FIFO Interrupt is enabled, Transmit
a system. The same threshold value can be Service Requests (TxServReq), i.e. data
used for both I/O read and I/O write cases. transfers from the host to the FIFO, are
During DMA operations, the FIFO Threshold is generated whenever there are FIFO Threshold
only used to trigger the SCE transmitter. NOTE: value or fewer data bytes in the FIFO, given by:
the DMA controller will fill the FIFO until the FIFO
Threshold has been exceeded before the TxServReq ≤ FIFO Threshold
transmitter is enabled.
For example, if the FIFO Threshold value is 12,
The FIFO Threshold value is programmable from TxServReq will be active whenever there are 12
0 to 31. The FIFO Threshold Register, located in or less data bytes in the FIFO. If the FIFO
Register Block One, Address Two, contains the Threshold is 0, TxServReq will be active
FIFO Threshold value. Low threshold values whenever the FIFO is empty. If the FIFO
result in longer periods of time between service Threshold is 31, TxServReq will be active
requests because more of the FIFO is utilized whenever the FIFO is not full.
before the request is issued. Systems that
program low threshold values must typically FIFO Interrupt
provide fast response times to these requests;
i.e., high performance systems that move I/O The FIFO Interrupt becomes active whenever the
data quickly. FIFO Interrupt Enable is active and either
TxServReq or RxServReq is active. When FIFO
High threshold values are used in "sluggish" Interrupt Enable becomes inactive, the FIFO
systems with long service request latencies. Low Interrupt goes inactive.
performance systems typically take longer to
move I/O data and require more frequent I/O For example, the FIFO Interrupt will become
service. For systems that program high FIFO active during a transmit operation if the FIFO
threshold values, much less of the FIFO is Threshold is fifty, the FIFO Interrupt Enable is
utilized before service requests are issued. active, and there are from one to fifty data bytes
in the FIFO (Figure 22).
Receive Threshold
In Figure 22, notice that five bytes are written to
Once the FIFO Interrupt is enabled, Receive the FIFO every time a service request is
Service Requests (RxServReq), i.e. data answered. The third request occurs as soon as
transfers from the FIFO to the host, are the FIFO Interrupt Enable is activated because
generated whenever there are 32 minus the the five bytes written to the FIFO following the

57
second service request was not enough data to interrupt latency.
exceed the FIFO Threshold given the long

Service Req. Serv. Req. Satisfied

Satisfied (long int. latency)

Data Bytes in FIFO 21 20 19 24 ... 21 20 19 18 17 16 15 14 19 18 ...

TxServReq
FIFO Int. Enable
FIFO Interrupt

1st Service 2nd Service 3rd Service

Request Request Request

FIGURE 22 - FIFO INTERRUPT EXAMPLE

DMA the FIFO is not full until TC. During receive DRQ
remains active as long as the FIFO is not empty
The DMA channel works in Single-Byte and until TC.
Burst (Demand) Mode. AEN is high during DMA
transfers. The DMA controls are located in SCE Single-Byte Mode
Configuration Register B. When the DMA
Enable bit (D0) is one, DMA is enabled. The Single-Byte mode is enabled by resetting the
DMA Burst Mode bit (D1) controls the DMA DMA Burst bit in SCE Configuration Register B.
mode. DRQ is further gated by the SCE Modes Single-Byte DMA transfers one data byte for
bits; e.g., DRQ can only be enabled if either each DRQ (Figure 23). Terminal Count occurs
Transmit or Receive mode has been enabled. only once, during the last byte of data block.
During transmit DRQ remains active as long as

AEN
DMA Burst
DMA Enable
DRQ
nDACK
I/Ox
TC

FIGURE 23 - DMA SINGLE-BYTE MODE TIMING

58
Burst (Demand) Mode bytes for each DRQ (Figure 24). The CIrCC
guarantees that DRQ relinquishes the ISA bus
DMA Burst mode is enabled by setting the DMA after thirty-two DMA I/O read or write cycles to
Burst bit in SCE Configuration Register B. allow for memory refresh.
Demand Mode DMA transfers up to 32 data

AEN
DMA Burst
DMA Enable
DRQ
nDACK
I/Ox

TC

FIGURE 24 - DMA BURST MODE TIMING

DMA Refresh Counter In Demand Mode, the count-zero condition

always clears DRQ and triggers a Refresh
The DMA Refresh Counter is used to prevent Interval. The Refresh Interval remains active for
DRQ from staying active for more than 4, 8, 16, 350ns following an inactive nDACK (Figure 25).
or 32 I/O cycles at a time (see DMA Refresh If there is more data to transfer, DRQ goes active
Count, bits 0-1, on page 34). again and the cycle repeats.

The counter is stopped and preloaded whenever Single Byte Mode DMA does not use the DMA
DRQ is not active. Once DRQ becomes active, Refresh Counter. Table 22 illustrates the DMA
the counter decrements until zero-count or DRQ Refresh Count bit encoding; e.g., if D[1:0] = 0,0,
is deactivated. the DMA Refresh Counter will prevent DRQ from
staying active for more than four I/O read/write
cycles at a time.

59
 Disable 32-Clk
Countdown & Reset Enable 32-Clk
32-Clk Counter Countdown

DMA Burst
DMA Enable
DRQ
nDACK
I/Ox
Refresh Interval
32 clocks
max. 350ns
min.

FIGURE 25 - DMA REFRESH COUNT TIMING

DRQ Control completely transferred but there is no room left in

the FIFO for more data. As soon as the FIFO
In DMA Burst Mode, DRQ remains active until Full becomes inactive, DRQ is reasserted. The
the entire DMA data block has been transferred, internal Refresh Interval signal can also
as indicated by DMA Terminal Count (TC). The temporarily deactivate DRQ (see the DMA
internal FIFO Full signal can temporarily Refresh Counter on page 59).
deactivate DRQ if the DMA block has not been
DMA Burst
DMA Enable
DRQ
Refresh Interval
FIFO FULL
Tx Enable
TxServReq
TC

FIGURE 26 - DMA BURST MODE TRANSMIT TIMING

FIFO Not Empty is true. FIFO Not Empty can
Burst Mode Receive temporarily deactivate DRQ if the DMA block has
not been completely transferred but there is no
DRQ Control data left in the FIFO to transfer. As soon as
FIFO Not Empty becomes true, DRQ is
In DMA Burst Mode, DRQ remains active until reasserted. The internal refresh counter can
the entire DMA data block has been transferred, also temporarily deactivate DRQ (see the DMA
as indicated by DMA Terminal Count (TC). Refresh Counter on page 59).
Since the FIFO Threshold is not used for DMA
transfer cycles, DRQ is asserted as soon as
60
 DMA Burst
DMA Enable
Rx Enable
DRQ
Refresh Interval
FIFO NOT EMPTY
TC

FIGURE 27 - DMA BURST MODE RECEIVE TIMING

PROGRAMMED I/O timing which is a block-mode programmed I/O

operation that utilizes IOCHRDY to control the
Programmed I/O mode is selected when the transfer (Figure 28). String Move mode is
DMA Enable bit in SCE Configuration Register B selected when the String Move bit in SCE
is zero. The CIrCC also supports String Move Configuration Register B is one.

AEN
String Move
FIFO Not Empty
IOCHRDY
IOR

FIGURE 28 - STRING MOVE TIMING

Polling Interface Not Empty is true, there is read data available in

the FIFO (Figure 29). The Transmitter interface
Programmed I/O without IOCHRDY requires depends upon the FIFO Full flag. If FIFO Full is
polling the FIFO status flags before reading or false, there is room for write data in the FIFO
writing FIFO data. The Receiver interface (Figure 30).
depends upon the FIFO Not Empty flag. If FIFO

61
 String Move
DMA Enable
FIFO NOT EMPTY
IOR

FIFO Data READ Status READ

FIGURE 29 - PROGRAMMED I/O READ TIMING

String Move
DMA Enable
FIFO FULL
IOW

FIFO Data WRITE Status READ

FIGURE 30 - PROGRAMMED I/O WRITE TIMING

FIFO Interrupt Interface Threshold value allows the host to efficiently satsify
the FIFO service requests until the message
Transmit transmission is complete. For slow systems, the
FIFO can be manually filled with transmit data
Transmitting messages with Programmed I/O before the transmitter is enabled. NOTE: The
using FIFO Interrupt requires writing a fixed FIFO will automatically request service before the
number of data bytes, usually related to the transmitter is activated if the FIFO Threshold is
threshold, whenever the FIFO Interrupt greater than zero.
becomes active. An appropriate FIFO

62
 String Move
DMAString
EnableMove
TxDMA
Enable
Enable
RxIOW
Enable
TxServReq IOR
FIFO Int.RxServReq
Enable
FIFO Interrupt
FIFO Int. Enable
Data
FIFO Done
Interrupt
EOMEOM
Interrupt
Interrupt

FIGURE
FIGURE3132- INTERRUPT
- INTERRUPTDRIVEN
DRIVENPROGRAMMED
PROGRAMMEDI/O
I/OTRANSMIT
RECEIVE TIMING
TIMING

Receive whenever the FIFO Interrupt becomes active.

An appropriate FIFO Threshold value allows the
Receiving messages with Programmed I/O using host to efficiently satsify the FIFO service
FIFO Interrupt requires reading a fixed number of requests until the message reception is
data bytes, usually related to the threshold, complete.

IOCHRDY Time-out more than 10Fs, a time-out error occurs and

subsequent IOCHRDY cycles are prevented until
In programmed I/O mode when AEN = low and the string move bit is specifically reactivated.
String Move = active, IOCHRDY can be used to Because of the 10Fs IOCHRDY time-out, it is
slightly extend the access cycle if the FIFO is recommended that string move timing only be
temporarily unable to fulfill the transfer request used for 1.152 Mbps transfers and above.
(Figure 33). If IOCHRDY remains inactive for

63
 AEN
String Move 10us (max)
FIFO Not Empty
IOCHRDY
IOR

24ns (max)

FIGURE 33 - VALID I/O READ READY CYCLE

IOCHRDY Timer out has elapsed, the timer is stopped and the
count is re-initialized. If IOCHRDY is still inactive
The 10Fs IOCHRDY Timer is initialized when when the 10Fs time-out occurs, the timer stops,
IOCHRDY is active. The timer count sequence the time-out error bit is set, IOCHRDY is re-
is activated when IOCHRDY goes inactive. If asserted, and the string move bit is reset (Figure
IOCHRDY becomes active before the 10Fs time- 34).

AEN
String Move
FIFO Not Empty
IOCHRDY
IOR
IOCHRDY Time-out
10us
Start IOCHRDY
Timer Error

FIGURE 34 - IOCHRDY 10FS TIME-OUT

64
Zero Wait State Support Configuration Register B. When No Wait is one,
nSRDY goes active following the trailing edge of
nSRDY the ISA I/O command and inactive following the
rising edge (Figure 35). nSRDY is suppressed
nSRDY can be driven by the CIrCC to indicate during DMA & refresh cycles, i.e. when AEN is
that an access cycle shorter than the standard active, or when IOCHRDY is inactive. Zero Wait
I/O cycle can be executed. NOTE: the names State support is only available when the SCE is
nSRDY & nNOWS can be used interchangeably. enabled.
nSRDY is enabled by the No Wait bit in SCE

AEN
No Wait
I/Ox
nSRDY

FIGURE 35 - nSRDY TIMING

The Interaction of nSRDY and IOCHRDY cycle (Table 31). NOTE: An inactive IOCHRDY
determine the three types of ISA access suppresses nSRDY.
cycles: no-wait-state cycle, standard cycle, ready

Table 31 - nSRDY and IOCHRDY Interaction

nSRDY IOCHRDY DESCRIPTION
active active No-wait-state Cycle (shortest length)
inactive active Standard Cycle (mean length)
x inactive Ready Cycle (longest length)

65
 OUTPUT MULTIPLEXER

The Output Multiplexer routes the active The Rx and Tx Polarity controls determine the
encoder/decoder to one of three CIrCC serial active states for the IR port signals, see SCE
communications ports. There are no restrictions Configuration Register A. The state of inactive
on any of these connections other than Rx/Tx IR outputs depends upon the Tx Polarity bit; e.g.,
source pairs go to the same destination (Figure if Tx Polarity is one (default), inactive outputs will
36). Descriptions of the Block Control, Output be 0. Routing for the COM Port flow-control
Mux, and Aux IR signals can be found in the signals is fixed. When the COM Port is inactive,
SCE Configuration Registers in Register Block the flow-control signals behave according to the
One. current SMSC 16C550A serial port specification.
NOTE: The Tx/Rx Polarity bits do not apply when
COM mode is selected.

Block Tx Output Rx Aux.

Control Polarity Mux. Polarity IR
4 1 2 1 1

IRRx IR
Raw Rx 6 to 1 1 to 3 IRTx Port
Raw Tx Mux. Demux.
CIR Rx
CIR Tx ARx AUX
ATx Port
ASK Rx 2 to 1
ASK Tx Mux.
IrDA SIR Rx
IrDA SIR Tx CRx
CTx
1 to 6 3 to 1 nRTS COM
nDTR Port
COM Rx Demux. Mux.
nCTS
COM Tx nDSR
nDCD
nRI

FIGURE 36 - OUTPUT MUX WITH TRANSMIT PULSE WIDTH LIMITER

NOTE: This figure is for illustration purposes only and is not intended to suggest specific implementation
details.

66
TRANSMIT PULSE WIDTH LIMIT hardware. If an active Tx pulse goes inactive
before 100Fs, the Transmit Pulse Width Limit
The Transmit Pulse Width Limit reduces the risk hardware is deactivated until the next active Tx
of thermal damage to the transmit LED during level. If the transmit pulse exceeds 100Fs, the
message transactions or from the unpredictable hardware deactivates Tx for 300Fs and cannot
affects that can occur during a power-on-reset. re-activate it until the input to the Transmit Pulse
The Transmit Pulse Width Limit hardware is Width Limit hardware has gone inactive and
controlled by the TX PW LIMIT bit (see Tx PW active again (Figure 37). When the TX PW LIMIT
Limit, bit 6, on page 33). The Transmit Pulse bit is low, the Transmit Pulse Width Limit
Width Limit hardware must apply to all encoders, hardware is disabled.
particularly the Consumer IR Encoder and the
RAW Mode encoder (Figure 36). APPLICATION NOTE: The Transmit Pulse
Width Limit can seriously distort low frequency
When the TX PW LIMIT bit is high, active Tx Consumer IR carriers (≤ 5kHz) or unmodulated
levels trigger the Transmit Pulse Width Limit low frequency Consumer IR bit rates.

TX PW LIMIT IN

TX PW LIMIT OUT
100us 300us

FIGURE 37 - TRANSMIT PULSE WIDTH LIMIT EXAMPLE

67
 CHIP-LEVEL CIrCC ADDRESSING SUPPORT

CIrCC Register addressing is controlled at the access data in the CIrCC register banks (Figure
chip level. Both the ACE bank select, nACE, and 38). Figure 38 illustrates a chip-level CIrCC
the SCE bank select, nSCE, are decoded at the address decoder using a base address of
chip level from the host address bus to ‘400’hex.

Address Bus ACE

nACE
Chip-Level Select
AEN
Address IrCC
SCE
I/O Select Decoder Select
nSCE

FIGURE 38 - CHIP-LEVEL CIRCC ADDRESS DECODE

Table 32 - CIrCC Address Decode at '400'hex

HEX ADDRESS nACE nSCE DESCRIPTION
000 - 3FF 1 1 CIrCC registers not accessible
400 - 407 0 1 ACE UART registers enabled
408 - 40F 1 0 SCE registers enabled
410 - 4FF 1 1 CIrCC registers not accessible

68
 AC TIMING

IR Rx Pulse Rejection

Table 33 - IR Rx Pulse Rejection

ENCODER PULSE REJECTION
IrDA SIR ≤500ns
Consumer IR ≤166ns

RX PULSE JITTER TOLERANCE

Table 34 - RX Pulse Jitter Tolerance

MAX JITTER
115.2 kbps 400ns
9.6 kbps 5Fs
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Copyright © 2007 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications.
Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been
checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to
specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest
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SMSC CIrCC Rev. 3/28/07