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Final Year Project/ Thesis (2023 – 2024)
ELEC Proposal Report
Low-Power SRAM Chip Design
Project ID: SK02b-23
Supervisor: Professor. Sarfraz Khawar
Author (Student ID): HO CHAK SING (20776344), TSUI YUE HANG (20772037)
Date: 01 September 2023
Main Objective
In this project, an 8kb static random-access memory (SRAM) will be investigated and
designed for low-power applications. we will learn how data is stored in, retrieved from, and
held in a SRAM chip. We will learn and design the building blocks of a typical SRAM chip that
include the storage bit cell, power-gated memory array, decoder, column multiplexer,
timing circuit, pre-charge logic, sense amplifier, and write driver. In the process of designing
the memory, you will learn the power/performance/area trade-offs that are made to meet a
given set of product specifications. This project will be completed using TSMC's 180nm
CMOS process, and a lot of emphasis will be placed on how to correctly simulate and verify
circuits.
Objective Statements
1. To understand and suggest viable architectures for the various memory building
blocks to meet the product specification.
2. Circuit design, simulation, and layout of individual blocks using Cadence and
Synopsys tool suite.
3. Analog blocks will be designed and simulated with schematic entry in Cadence tools
and digital blocks will be designed and simulated using Verilog in Synopsys tools. Bit cell
data stability analysis will be performed in MATLAB.
4. To integrate modules and perform chip-level simulations to measure active/standby
power consumption and chip access/cycle time.
5. To learn Verilog-A to model interfacing analog circuit blocks as well as modules used in
the generation of stimulus.
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Contents
Main Objective 1
Objective Statements 1
SECTION 1—INTRODUCTION 2
1.1 Background and Engineering Problem 2
1.3 Literature Review of Existing Solutions 3
SECTION 2—METHODOLOGY 5
2.1 Overview of Low Power SRAM design 5
2.1.1 System Description 5
2.1.2 SRAM Design Components Diagram 6
2.1.3 Parameters list 7
2.1.4 ECE (Electronic and Computer Engineering) Knowledge 7
2.2 Objective Statement Execution—Plan for Producing SRAM 7
2.2.1 SRAM high-density bitcell design 7
SECTION 3— Project Planning 10
3.1 Project Schedule 10
REFERENCES 11
APPENDICES 11
Appendix A – Meeting Minutes 11
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SECTION 1—INTRODUCTION
1.1 Background and Engineering Problem
Static Random Access Memory (SRAM) is a type of volatile memory that is
commonly used in electronic devices for temporary data storage and working
memory. It provides fast access time and does not require constant refreshing like
Dynamic Random Access Memory (DRAM). It is also commonly used in personal
computers, workstations and routers. However, it has limitations to be used on
resource- limited and small-in-size devices due to several issues.
SRAM consumes more power compared to other memory types, such as DRAM or
Flash memory, to name a few. The high-power consumption is primarily due to the
constant power requirement to maintain the stored data in SRAM cells. The
absence of refresh circuitry in SRAM, while bringing an advantage to performance,
leads to continuous power consumption even when the data is not being accessed,
which commonly requires design tradeoff to extensive power-gating technique to
resolve the issue.
Moreover, SRAM has lower memory density compared to DRAM. The larger cell size
and more complex circuitry required for each SRAM cell result in lower storage
capacity per unit area. This density limitation can be a challenge in applications that
require large memory capacities, such as high-capacity storage devices or systems
with extensive data processing requirements.
Therefore, a low power and high memory density SRAM design is needed to cater to
applications with small, resource-limited devices but has performance
requirements. For example, due to the ongoing demand for AI–oriented
computational devices and edge computing, SRAM as common cache layer for
electronic devices, is expected to take massive responsibilities at enabling mobile
and IOT devices to have strong computation power matching with the resource-
intensive AI applications.
As a solution, we propose to design a lower power and high-density custom on chip
design for SRAM, by utilizing power gating technology, power reduction and data
retention techniques.
1.2 Objective
1. To understand and suggest viable architectures for the various memory
building blocks to meet the product specification.
2. To design a circuit, simulation, and layout of individual blocks using
Cadence and Synopsys tool suite.
3. Analog blocks will be designed and simulated with schematic entry in
Cadence tools and digital blocks will be designed and simulated using
Verilog in Synopsys tools. Bit cell data stability analysis will be performed
in MATLAB.
4. To integrate modules and perform chip-level simulations to
measure active/standby power consumption and chip
access/cycle time.
5. To learn Verilog-A to model interfacing analog circuit blocks as well as
modules used in the generation of stimulus.
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1.3 Literature Review of Existing Solutions
There are research papers that studied the techniques in power reduction of SRAM.
They mainly focus on studying the relationship between the power consumption
and the capacitance of the memory size, the performance of SRAM with different
number of transistors, including read/write stability, power consumption and access
time.
Power Gating Technologies
In SRAM, word lines, bitlines and datalines are the main components of the memory.
Changing the size of these lines will significantly affect the power consumption.
Therefore, a technique called Divided Word Line (DWL) is commonly used in
handling large amounts of data. DWL is a technique that aims to decrease power
consumption in SRAM arrays. In traditional SRAM design, the word lines are
responsible for accessing and reading or writing data stored in memory cells.
However, in large SRAM, the word lines become the major source of power
dissipation due to its capacitance and the associated charging and discharging
operations. A research paper [1] has shown the performance comparison of low
power SRAMs with different memory sizes but the same power supply voltage and
CMOS technology. As a result, the access time and power dissipation vary directly
with the size of memory.
To reduce the power consumption, the DWL technique divides the word lines into
smaller sections or sub-word lines, using a two-stage hierarchical row decoder
structure. These sub-word lines are selectively activated, reducing the overall
capacitance and power required for accessing the memory cells. Apart from
reducing the power consumption, dividing the word lines into smaller segments
enables faster access to the targeted memory cells. Since only the relevant sub-
word lines are activated, the access time is reduced, the performance will improve
due to the read and write operations.
Together with single bitline cross-point cell activation (SCPA) architecture, a design
that each memory cell in the array is directly connected to a single bitline, simplified
the access scheme, and allowed for selective of specific cell, to reduce the power
consumption in the read and write operation of a single cell instead of entire rows
or columns.
Both techniques aim to improve power efficiency in memory array. DWL focuses on
the division and selective activation of the word lines. While SCPA focuses on the
connection and activation scheme of single memory cell.
Number of Transistors
The number of transistors in SRAM is also an aspect that greatly changes the
performance and power consumption. Numerous researchers [2] have studied the
difference between 6T, 7T, 8T, 9T and 10T SRAM. In their report, it states that 9T
SRAM cell has the highest value of read stability and the lowest write access time.
7T SRAM has the highest value of write ability. 8T SRAM has the lowest read power
dissipation. To assess the overall performance of different SRAM topologies, they
calculated the static noise per unit area to power delay product ratio (SAPR), finding
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that 8T SRAM has the highest value of SAPR.
In power analysis, dynamic power which is power consumed due to the charging
and discharging of capacitance during read and write operation, and static power
which is power consumed due to leakage current are considered. The researcher
compared the leakage current of conventional 6T SRAM and 7T SRAM cells by
equation and found that although 7T SRAM cell has more leakage current
component than 6T SRAM, it has lower leakage power than 6T SRAM due to stack
effect.
Problems
Although all these techniques can affect the power consumption of SRAM, there are
still some limitations. By using the DWL technique or the SCPA architecture, the
complexity of SRAM design is increased. Also, the synchronization of the sub-word
lines is hard to ensure accurate data access. For SCPA architecture, the access speed
may be affected due to the single bitline.
Meanwhile, changing the number of transistors may reduce the leakage current.
However, the size and area of SRAM may increase. As the design complexity and
number of transistors increases, the manufacturing and production cost will
increase.
Solutions
This project proposes the design of a low power SRAM. It utilizes existing
techniques, if possible. It aims to have low power consumption while meeting a
specific requirement of memory size and number of transistors.
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SECTION 2—METHODOLOGY
2.1 Overview of Low Power SRAM design
2.1.1 System Description
In this project, an industrial level SRAM architecture using the Very Large-Scale
Integration (VLSI) method with TSMC’s 180nm process library will be designed. The
test design aims to propose new solutions to resolve the current significant power
consumption block for modern Socs, supplying optimal and functional embedded
SRAM units to the industry. In the best case, it should be able to keep low static
(write) power consumption by reducing leakage current associated with the SRAM
cells distributed in the array, while providing reasonable read, write noise margin
for data stability.
2.1.2 SRAM Design Components Diagram
Figure 1. Important steps of SRAM Design
There are 7 steps involved in delivering a SRAM design with VLSI methods.
The first step is the SRAM bit cell design. Where dimensions for the transistors
within the bit cell circuits need to be determined and simulations for RSNM, HSNM
and dynamic write margin needs to be run to ensure the design falls within a
reasonable range. After the schematic, the layout of the bit cell and verification with
DRC needs to be done to finish this component.
Then comes the bitcell array design. This constitutes of the memory array itself, say
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128 rows by 128 columns. Each row stores 8 words, each of which is 16 bits wide.
We need to design the pre-charge transistors, the body contact, column MUX, and
write drivers, where power gating on the memory needs to be implemented.
The third step is to design the row and column decoders. The 6T SRAM requires one
decoder, which is shared between read and write operations. The 8T SRAM requires
two decoders, one for reading and a separate one for writing.
Next is to design the sense amplifier, where the 6T SRAM requires a complex
differential sense amplifier.
After that, the timing of the entire memory to ensure all blocks work in the
desired sequence needs to be implemented.
The sixth step is to include ESD (Electrostatic discharge) protection circuit and I/O
(Input/Output) pads.
And finally, to finish the top-level verification of the chip.
2.1.3 Parameters list
Table 1. List of Specifications
*Params Specifications/Model
Width Driver transistor (Nmos)
Width Pass transistor (Nmos)
Width Load transistor (Pmos)
Vcc 1.2V
2.1.4 ECE (Electronic and Computer Engineering) Knowledge
ELEC4410 --- CMOS VLSI Design
This course covers CMOS process and design rules; MOS device electronics; CMOS
circuit and logic circuit characterization and performance estimation; VLSI design
and verification tools. Laboratory work will be centered on industry standard tools.
ELEC3400 --- Introduction to Integrated Circuits and Systems
This course presents an overview, applications, fundamentals, and design flow of
the state-of-the-art integrated circuits (IC) and systems. The course contents include
fabrication process; diodes, bipolar transistors and MOS transistors and modes of
operations; and fundamental of analog, digital and mixed-signal IC design.
ELEC3500 – Integrated Circuit Devices
This is an introductory course for semiconductor device operation principles and
technology in common electronic products such as integrated circuit (IC), digital
camera, solar cell, memory elements, smartcard, etc. Topics covered include
Semiconductor properties, IC fabrication technology, PN junctions, Bipolar Junction
Transistors (BJT), MOSFETs, CCD and the future technology trend in the electronic
industry.
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2.2 Objective Statement Execution—Plan for Producing SRAM
In this subsection, we further describe SRAM and outline how we will design, fabricate and
program SRMA components so that it meets our set objectives.
2.2.1 SRAM high-density bitcell design
Objective: To create a reasonable bitcell design that has minimum area while
maintaining data integrity and performance
In this objective, 6T (6 transistor) bitcell was adopted to create a high-
density(memory-intensive) design. Therefore, minimum sized transistor was chosen
for all the load, driver and pass transistors in the bitcell schematic. After trial and
error through changing the width variables of the transistors, a reasonable noise
margin was achieved after calculation using Matlab scripts provided by FYP (Final
Year Projects) supervisor.
The second step is to create a compact layout for the bit cell by following the
180nm process standard cell DRC rulebook provided by TSMC. In the best case, the
layout should optimize the placement and sizing of transistors, utilizing efficient
wiring schemes, and reducing potential parasitic capacitance. After DRC (Design
Rule Checking) checking with no errors shown, LVS is performed to see if the layout
created matched with the schematic. If the answer is yes, the design process can
proceed to the next step.
Figure 2a. bitcell schematic
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Figure 2b. bitcell noise margin
Task 1
Aim: Research relevant bitcell technology and get familiar with VLSI knowledge.
Expected Outcome: Identify differences between high-density and high-speed
bitcell and relevant transistor variables that affect the SRAM metrics.
Member in charge: All group members.
In this task, we studied ELEC4410 lecture notes provided by supervisor, including
VLSI textbooks and research papers, for better understanding in relevant keywords
and concepts. We learned standard procedures in delivering SRAM design, including
major bottlenecks and concerns.
Task 2
Aim: Design 6T high-density bitcell schematic.
Expected Outcome: Reasonable dimensions for transistor variables are determined
which aligns to the VLSI method and industrial best practices, while ensuring the
margin simulation afterwards falls within a reasonable range.
Member in charge: All group members.
In this task, we used a suite of EDA (electronic design automation) software tools
developed by Cadence Design System Inc, including Cadence Virtuoso and Cadence
Specter, to assist us in performing schematic capture, simulation and layout design.
We first did manual mathematical calculation on determining the suitable
dimension for transistors, then manually modified the transistor parameters in
cadence virtuoso, and reached a satisfactory result through several trails.
Task 3
Aim: Perform RSNM, HSNM and Dynamic Write Margin simulation on the
bitcell and ensure the results falls within reasonable region to prove the
design is valid
Expected Outcome: It is only acceptable that the read/write noise margin falls
within 100-300mV
Member in charge: All group members.
In this task, we create two csv files by sweeping a DC (Direct Current) source at Q
and QB respectively from 0 to 1.2V, then using the Matlab scripts the supervisor
provided to calculate the noise margin from the data points we recorded at the csv
files. The result is that we were able to achieve 252mv for write noise margin.
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Task 4
Aim: Draw layout of the bitcell and ensure it checks out with the TSMC DRC
Expected Outcome: Created layout passed DRC checking with no errors found.
Member in charge: All group members.
In this task, we first located the TSMC 180nm DRC file as guidelines for our layout
drawing, then we draw the layout components one by one and fix errors on the way
through online resources and the DRC doc.
Task 5
Aim: perform LVS to check if the layout created align with the schematic and fix
corresponding errors if not
Expected Outcome: LVS checked successfully with no errors found.
Member in charge: All group members.
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SECTION 3— Project Planning
3.1 Project Schedule
Table 2. SRAM Schedule.
2022/08/30
Schematic and Layout Design
Research HO CHAK SING, TSUI YUE 1
HANG
Design SRAM bit cell HO CHAK SING, TSUI YUE
1
HANG
Design SRAM memory array HO CHAK SING, TSUI YUE
HANG
Design SRAM decoders HO CHAK SING, TSUI YUE
HANG
Design SRAM sense amplifier HO CHAK SING, TSUI YUE
HANG
Design SRAM Timing Block HO CHAK SING, TSUI YUE
HANG
I/O pods and ESD HO CHAK SING, TSUI YUE
HANG
Top level verification HO CHAK SING, TSUI YUE
HANG
FYP Final Report
REFERENCES
[1] M. Margala, "Low-power SRAM circuit design," Records of the 1999 IEEE International Workshop on
Memory Technology, Design and Testing, San Jose, CA, USA, 1999, pp. 115-122, doi:
10.1109/MTDT.1999.782692.
[2] Kumar, H., Tomar, V.K. A Review on Performance Evaluation of Different Low Power SRAM Cells in
Nano- Scale Era. Wireless Pers Commun 117, 1959–1984 (2021). https://doi.org/10.1007/s11277-020-
07953-4
APPENDICES
Appendix A – Meeting Minutes
Meeting 1
Date: 08/30/2023
Time: 01 :30am
Location: Discord
Attendees: HO CHAK SING, TSUI YUE HANG
Absent: None
Minutes taken by: CHAGPT
● We collaborated and finished section 1.1 / 1.2 / 3 / 3.1, 1.3 in progress
● The main objective of the project is confirmed.
● Finish SRAM bit cell schematic design with cadence
Table 2. Action Items for Next Meeting
Action Item to be completed By when By whom
Proposal Report section 1.3 Sep 4th TSUI YUE HANG
Proposal Report section 2.1 Sep 4th HO CHAK SING
Next Meeting: Sep 3, 9:30, Zoom
Meeting 2
Date: 09/03/2023
Time: 09:30pm
Location: Discord
tendees: HO CHAK SING, TSUI YUE HANG
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Absent: None
Minutes taken by: CHAGPT
● We collaborated and finished section 2.1.2 and 2.1.3
Action Item to be completed By when By whom
Proposal Report section 1.3 Sep 5th TSUI YUE HANG
Proposal Report section 2.2 Sep 5th HO CHAK SING
Finalize the proposal report Sep 6th All
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